| Age | Commit message (Collapse) | Author | Files | Lines |
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Extend decode support for more fields for AER CE and UE status prior to
PCIe r6.0.
Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>
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PCIe r6.0, sec 7.9.26.4.2 "Link IDE Stream Status Register defines"
the link state as:
0000b Insecure
0010b Secure
The same definition applies to selective streams as well.
The existing code wrongly assumes "secure" is 0001b, fix that for both
link and selective streams.
While at this, add missing "Selective IDE for Configuration Requests Enable".
Also fix the base and limit parsing for the memory and RID ranges.
Fixes: 42fc4263ec0e ("ls-ecaps: Add decode support for IDE Extended Capability")
Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
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pci_id_hwdb_lookup()
Currently used udev hwdb key "ID_MODEL_FROM_DATABASE" does not return
subsystem, but returns device name.
There is no udev hwdb key which returns subsystem or generic subsystem.
So remove ID_SUBSYSTEM and ID_GEN_SUBSYSTEM from pci_id_hwdb_lookup().
This change fixes issue that pci_id_hwdb_lookup() as subsystem name always
returned device name.
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Sometimes SEM_FAILCRITICALERRORS flag (disable critical-error-handler GUI
messages) is not enough for LoadLibrary() and SEM_NOOPENFILEERRORBOX flag
(disable file-not-found GUI messages) is needed too to prevent showing GUI
messages on LoadLibrary() failures.
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win32_call_func_with_tcb_privilege()
Cleanup phase may change error code as it calls other WinAPI functions.
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At physical address 0x40E (part of BDA) is stored indirect 16-bit paragraph
offset to the EBDA, and not the EBDA itself. Fix it.
ACPI code in linux kernel checks if the EBDA offset in BDA is above
physical address 0x400. Do the same check here. It is for detection if EBDA
is present as it does not have to be on the old computers or in some
virtualised environments.
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Optimization flags like -O2 from $(OPT) passed via $(CFLAGS) used during
compiling individual object files are ignored when gcc's LTO is enabled for
the linking final executable.
Optimization flags used for compiling individual object files should be
same as optimization flags for linking final executable.
Fix propagation of $(CFLAGS) and $(OPT) when LTO is enabled.
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Haiku: fix build with DNS=yes.
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lspci.man: update the path used to store the cached files.
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Build fix on Haiku.
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PCIe r6.1, sec 7.5.3.3 defines "TEE-IO Supported" in the PCI Express Device
Capabilities Register which indicates that the function implements
the TEE-IO functionality as described by the TEE Device Interface Security
Protocol (TDISP, PCIe r6.1, chapter 11).
tests/cap-ide is an example of such device.
Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
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IDE (Integrity & Data Encryption) Extended Capability defined in [1]
implements control of the PCI link encryption. The verbose level > 2 prints
offsets of the fields to make running setpci easier.
The example output is:
Capabilities: [830 v1] Integrity & Data Encryption
IDECap: Lnk=0 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ Alg='AES-GCM-256-96b' TCs=8 TeeLim+
IDECtl: FTEn-
SelectiveIDE#0 Cap: RID#=1
SelectiveIDE#0 Ctl: En- NPR- PR- CPL- PCRC- HdrEnc=no Alg='AES-GCM-256-96b' TC0 ID0
SelectiveIDE#0 Sta: insecure RecvChkFail-
SelectiveIDE#0 RID: Valid- Base=0 Limit=0 SegBase=0
SelectiveIDE#0 RID#0: Valid- Base=0 Limit=0
[1] PCIe r6.0.1, sections 6.33, 7.9.26
Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
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The typo was introduced by merging the AmigaOS back-end.
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Call 'sysi86(SI86V86, V86SC_IOPL, 0);' - same what is X11 and FlashROM doing.
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Windows builds for versioned symbols use inline asm .set directive which in
some cases makes x86-64 LTO compiler to drop the referenced value. Define
STATIC_ALIAS macro with VERSIONED_ABI (used) attribute which forces LTO
compiler to not drop the symbol from the final DLL library.
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MinGW-w64
MinGW-w64 toolchain (as opposite to MinGW32) provides all needed cfgmgr32
functions in import library. Use import library and do not resolve
functions at runtime.
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Older version of cfgmgr32.h header file use define name fMD_Prefetchable
instead of mMD_Prefetchable. Define constant to fix compilation.
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language
The default LANG_NEUTRAL language is the system language, not the "C" locale.
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This will speed up listing devices by lspci as it is not needed to scan
BIOS memory two times.
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Search for ACPI MCFG table in detect sequence, so on failure we can move to
the next pci access method.
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Solaris can access physical memory via mmap() of /dev/xsvc device and
Haiku + BeOS of /dev/misc/mem device.
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Expression ((1 << n) - 1) for n=31 has undefined behavior and gcc 11
already evaluates it to zero.
Fix definition of OFF_MAX to prevent signed integer overflow.
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physmem-posix.c file
This deduplicates physical memory mapping mmap() code found in ecam and
mmio-ports backends into common functions with new physmem API.
This new physmem API allows to implement also non-mmap() variants of
physical memory mapping.
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Rewrite function to always add a new allow granting permissions at first
position in DACL. Normally all deny permissions are before allow
permissions, so previously allow permission could have been overridden by
explicit deny permission. With this change, our newly added allow
permission override any possible deny permission and always grant access
for asked process user.
Also properly handle automatic inheritance model which is in use since
Windows 2000 and handle also special case when DACL is not present which
gives allow access to everyone.
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win32-helpers.c
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Function win32_strerror() was duplicated in two different files:
win32-cfgmgr32.c and win32-kldbg.c. Now there is only one in
win32-helpers.c.
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Code for enabling Tcb privilege is split from SetProcessUserModeIOPL() into
new function CallFuncWithTcbPrivilege().
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Semicolon in msvc __asm block means start of the comment, and not end of
the __asm statement, like it is for all other C statements. Also function
which uses msvc inline assembly cannot be inlined to another function
(compiler reports a warning about it, not a fatal error). So add explicit
curly brackets for __asm block, remove misleading semicolons and do not
declare function as inline.
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It is needed by pcilmr anyway.
If it turns out to be missing on your system, please extend
the condition for use of compat/getopt.h in pciutils.h.
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%F is not portable.
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The parsing is guaranteed to be non-destructive in recent libpci.
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It is a part of the utilities, not of libpci.
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Otherwise, they are ignored when "make CFLAGS=something" is used.
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We also create parent directories of net.cache_name automatically.
Tilde expansion is performed internally and it does not change
user-specified net.cache_name any longer.
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If the pci.ids file was empty, it was never considered loaded,
so the loading function was called repeatedly and it always flushed
the name cache.
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This will allow overriding pci_param->malloced.
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It was introduced by commit 0ce6ff4aafb36a7923511a8da6bbbebb642e3109.
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Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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equal to 0
According to spec, for the MaxTimingOffset and MaxVoltageOffset parameters
'A 0 value may be reported if the vendor chooses not to report the offset'.
Use max possible Offset value in such situations and report to the user.
Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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* Add support for different utility modes;
* Make the default (now --margin) mode capable to accept several
components and run test for all of them;
* Add --full mode for sequential start of the test on all ready links
in the system;
* The complication of the main function is due to the need to pre-read the
parameters of the devices before starting the tests in order to calculate
Total ETA of the utility.
Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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Make it possible to change receiver margining parameters depending on
current hardware specificity.
In our tests Intel Ice Lake CPUs RC ports reported
MaxVoltageOffset = 50 (RxA), which led to results several times bigger
than the results of the hardware debugger.
Looks like in Intel Sapphire Rapids this was fixed, these CPU RC ports
report MaxVoltageOffset = 12 (RxA). To solve the problem it was decided
to hardcode Volt Offset to 12 (120 mV) for Ice Lake RC ports.
In the case of margining a specific link, only information about
Downstream and Upstream ports should be sufficient to decide whether to
use quirks, so the feature was implemented based on a list of devices
(vendor - device - revision triples), whose problems are known.
Back to Ice Lake ports, according to Integrators List on the pci-sig site,
the list of possible RC ports of Ice Lake Xeon's includes at least three
more options (with ids 347B/C/D) besides the one used in this commit, but
we don't have such processors to check the relevance of the MaxVoltageOffset
problem for these ports.
Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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Lanes are rated according to the minimum/recommended values.
The minimum values are taken from PCIe Base Spec Rev 5.0 section 8.4.4.
30% UI recommended value for timing is taken from NVIDIA presentation
"PCIe 4.0 Mass Electrical Margins Data Collection".
Receiver lanes are called 'Weird' if all results of all receiver lanes
are equal to the spec minimum value.
Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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* Implement option to turn on/off logging for margining;
* Support systems with several PCI domains;
* margin_log_margining function prints margining in progress log using
one line messages for each Receiver in the form:
"Margining - <direction> - Lanes [<current simultaneous lanes>] - ETA:
<current direction-lanes margining remaining time> Steps: <current
margining steps done> Total ETA: <utility run total remaining time>".
Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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* Implement the margining flow as described in the section "Example
Software Flow for Lane Margining at Receiver"
of the PCIe Base Spec Rev 5.0;
* Implement margining commands formation and response parsing according
to the PCIe Base Spec Rev 5.0 table 4-26;
* Use Receiver margining parameters as described in the
PCIe Base Spec Rev 5.0 table 8-11;
* Support lane reversal and simultaneous margining of several link lanes.
Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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margining processes
Follow the checklist from PCIe Base Spec Rev 5.0 section 4.2.13.3
"Receiver Margin Testing Requirements":
* Verify the Link is at 16 GT/s or higher data rate, in DO PM state;
* Verify that Margining Ready bit of the device is set;
* Disable the ASPM and Autonomous Speed/Width features for the duration
of the test.
Also verify that Upstream Port of the Link is Function 0 of a Device,
according to spec, only it must implement margining registers.
Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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Move several macros from lspci and add some more for operations with
bit masks.
Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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Gather all the info available without writing to the config space.
Without any commands margining capability exposes only 3 status bits to
read through Margining Port Capabilities and Margining Port Status registers.
It makes sense to show them anyway. For example, Margining Ready bit
indicates whether the device is actually ready for the margining process.
Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
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lspci initializes both caches for the device to the same memory block in
its scan_device function. Latter calls to config_fetch function will
realloc cache in struct device, but not in struct pci_dev leading to
the invalid pointer in the latter. pci_dev cache is used by pci_read_*
functions, what will lead to a possible use-after-free situations.
Example:
With patch:
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i386-ports: Add support for OpenBSD
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On all systems except BeOS and Haiku are x86 I/O ports accessed in the
standard way by the x86 in/out instructions.
On more systems there are wrapper functions for x86 in/out instructions but
under different names and sometimes even for same system those names
depends on user version of toolchain/compiler. And also some systems have
same function names but switched order of arguments.
Simplify this code, define own wrapper functions for x86 in/out
instructions in new header file i386-io-access.h and use it for every
platform except BeOS and Haiku.
This change simplifies Windows port, duplicated code between SunOS and
Windows and also tons of redefined port functions in every port.
To not conlict with possible system functions included from some header
file, add intel_ prefix for every function included from the file
lib/i386-io-access.h into lib/i386-ports.c
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This hopefully conveys the purpose much better than just "aux".
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Many things have changed since we introduced work-arounds for Linux
systems with missing pread/pwrite in 1999 (if you are curious, it was
in commit bc6346df8d89ece4814be7dff951ec1a7d259938).
I believe that it is supported by all reasonably recent Linux systems
now. After all, pread() was already defined by POSIX.1-2001.
This should also fix problems with musl libc mentioned in GitHub
issue #158.
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When CXL capability decoding was upgraded to revision 2 by commit
c0ccce1b4cd5b42b17f2e8f7bae4031c311677ff, the value of PCI_CXL_DEV_LEN
in lib/header.h has changed.
This is probably not a good idea - programs using libpci can depend
on the exact value of this constant.
Let us revert PCI_CXL_DEV_LEN to the original value for revision 1
and add PCI_CXL_DEV_LEN_REV2 for the next revision.
Also, fixed a bug in the decoder which caused it to read past the
end of the buffer for a capability which is declared as revision 2,
but too short.
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If more buses span continuous address space then there can be up to the
256 MB long address range which ecam backend tries to map.
Such huge space cannot be mapped on some memory limited systems. And also
it is not needed to map whole 256 MB long address range because ecam
backend cache uses mapping only for one bus. One bus has maximal mapping
size just 32*8*4096 bytes.
So adjust size calculation when mapping ecam bus.
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Move duplicate code block into helper function calculate_bus_addr().
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GetWindowsDirectory() function returns HOME user folder if application is
running on the Terminal Server. So this function is not suitable.
Instead of use GetSystemDirectory() which returns path to system32 folder
or GetSystemWindowsDirectory() which returns path to Windows folder (but
this is not available on all Windows versions).
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Get*Directory() functions have strange API. When called with zero buffer
they return length of the required buffer for storing path including
nul-term in TCHAR units (which is 1 for ANSI builds and 2 for UNICODE
builds). When called with non-zero buffer which can store full path they
return length of the path without nul-term (again in TCHAR units).
GetWindowsDirectory() function returns HOME user folder if application is
running on the Terminal Server. So this function is not suitable.
Fix calculation of path buffer for UNICODE builds and instead of usage
GetWindowsDirectory() function with concatenating "\\system32" string, use
function GetSystemDirectory() which returns path directly to system32
folder and which works correctly also on Terminal Server (per KB281316).
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grant_process_token_dacl_permissions()
When SetEntriesInAcl() call success then new_dacl allocated by this
function has to be released by LocalFree() call.
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CXL: DVSEC fixes and CXLCap3
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Fix compile warnings about unused variables
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While commit 5bdf63b6b1bc ("lspci: Add PCIe 6.0 data rate (64 GT/s)
support") added 64 GT/s support to some registers, LnkCap2 Supported
Link Speeds Vector was not included.
Add PCIe 6.0 data rate bit check also into
cap_express_link2_speed_cap().
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
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Display the PASID required attribute in the Page Request Status Register.
When set, the function expects a PASID on Page Group Response (PRG)
messages when the corresponding page request had a PASID.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
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"Several ways how to identity a register" doesn't read correctly and
misspells "identify". Reword as "several ways to identify a register".
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Remove spurious colon from PTM decoding to match other enabled/disabled
decoding.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Several Capabilities include MSI/MSI-X Interrupt Message Numbers, which
were decoded in various ways:
- MSI %02x PCIe Capability
- IntMsg %d AER Capability
- INT Msg #%d DPC Capability
- Interrupt Message Number %03x SR-IOV Capability
- Interrupt Message Number %03x DOE Capability
Print them all using the same format:
+ IntMsgNum %d
This better matches the "Interrupt Message Number" terminology used in the
spec, e.g., PCIe r6.0, sec 7.5.3.2.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Decode the Link Disable bit as "LnkDisable" (not simply "Disable") to match
the spec terminology (PCIe r6.0, sec 7.5.3.7)
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Decode the PCIe DevCtl2 End-to-End TLP Prefix Blocking bit. The
"EETLPPrefixBlk" format is analogous to the existing "EETLPPrefix" format
used for the corresponding DevCap2 bit.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Decode the PCIe DevCtl2 Emergency Power Reduction Request bit.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Decode the PCIe DevCtl2 ID-Based Ordering Enable bits.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Decode the PCIe DevCtl2 fields in the same order they're documented in the
PCIe spec.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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sysfs.c: In function 'sysfs_read_vpd':
sysfs.c:569:43: warning: unused parameter 'd' [-Wunused-parameter]
static int sysfs_read_vpd(struct pci_dev *d, int pos, byte *buf, int len)
^
sysfs.c:569:50: warning: unused parameter 'pos' [-Wunused-parameter]
static int sysfs_read_vpd(struct pci_dev *d, int pos, byte *buf, int len)
^~~
sysfs.c:569:61: warning: unused parameter 'buf' [-Wunused-parameter]
static int sysfs_read_vpd(struct pci_dev *d, int pos, byte *buf, int len)
^~~
sysfs.c:569:70: warning: unused parameter 'len' [-Wunused-parameter]
static int sysfs_read_vpd(struct pci_dev *d, int pos, byte *buf, int len)
^~~
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Unfortunately, this leads to the User-Agent not containing version
of curl/wget/lynx we used.
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Previously, if pciutils were configured with compression of pci.ids,
update-pciids downloaded the gzipped version. Now, it downloads the
most compressed version for which tools are found installed, and
recompresses it to gzip if needed.
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Given that PCI VFs are expected to have a vendor and device ID of
0xffff, when examining vendor capabilities use the mangled vendor and
device IDs (typically copied from the PF) rather than those read from
the VF configuration space.
Signed-off-by: David Edmondson <david.edmondson@oracle.com>
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The error bit is specified by the 2nd (zero indexed) bit
in the status register, so the respective bit value is 4 (PCI Base Spec
6.0.1). Let's fix that up.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
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Previously, the only information about the specific version of GPL
was present in the README and individual source files mentioned only
GPL alone.
Let us update all copyright comments to explicitly say "GPL v2+"
and also include the machine readable SPDX license identifier.
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8.1.3 PCIe DVSEC for CXL Devices
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Fixes 3d7466ef8545d37a4666e185a9f5d65ceb9c8af4.
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Makefile: change STRIP to '--strip-program' when cross-compile
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lspci: Fix bridge filter support in tree view
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Represent each domain as domain bridge under the &host_bridge and put root
bus of each domain under the domain bridge.
With this change lspci in tree view does not show zero bus on domain 0 in
the output if this bus does not exist at all. Root bus in PCIe hierarchy
does not have to be zero and on Freescale PowerPC systems it is common.
Also with this change are separate domain showed in the output separately.
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It refers to the previous value in linked-list, not to the next.
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For PCIe devices of PCI Bridge type is Primary Bus Number not used and the
default value is 0. PCIe devices capture their Bus and Device numbers
automatically from PCIe TLP packets.
Instead of Primary Bus Number use Device Number because zero value confuse
tree building algorithm. Existing code already expects that Device Number
of PCI Bridge is already set to Primary Bus Number.
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Correctly show whole subtree of PCI-to-PCI bridge in tree view when filter
(-s or -d option) was specified for PCI-to-PCI bridge device itself.
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When cross-compile, we should use specific strip instead of default
/usr/bin/strip.
reference:https://man7.org/linux/man-pages/man1/install.1.html
Signed-off-by: mingrui.ren <mingrui.ren@bst.ai>
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When multiple back-ends use the same option (e.g., "devmem.path"),
they tend to define it each. This is not nice, but before we generalize
these options properly, let us at least remove the duplicate definitions.
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This is a new direct hardware access method via PCIe ECAM (Enhanced
Configuration Access Mechanism). It is available on all PCIe-compliant
hardware. Requires root privileges and access to physical memory.
ECAM mapping can be specified manually via a new ecam.addrs parameter or
can be read from ACPI MCFG table. ACPI MCFG table can be located in the
system or read from x86 BIOS memory.
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Apparently, people started considering "which" obsolete. I still
consider "which" rather useful and definitely more comfortable to type
than "command -v".
Still, "command -v" should be more portable, so let us use it.
I wonder which of the ancient systems which we are still supporting
will be broken by this change...
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On 64-bit non-LLP64 systems is type long 64-bit. On 32-bit and 64-bit LLP64
systems is type long only 32-bit. But readl() and writel() functions works
with 32-bit PCI word. Fix it for non-LLP64 systems by using type u32.
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Extend win32-cfgmgr32 backend and add a new option win32.cfgmethod for
specifying other backend for accessing PCI config space. There are more
config space access methods available on Windows and each is working only
sometimes (either requires special privileges or special setup).
So by default try to choose the first working one via order defined in pci
probe_sequence[] array. If none is available then emulate PCI config space
like before this change.
Function pci_init_v35() is extended and renamed to pci_init_internal() to
optionally do not throw errors and allow to specify one access method which
will be skipped in AUTO mode. This is used to prevent choosing win32-cfgmgr32
as config space access method for win32-cfgmgr32.
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Suggested by Pali.
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Fix compile issues with older toolchain which does not define ERROR_NOT_FOUND macro.
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Worked around encoding issues in the database before we fix them
for real.
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C function fopen() implemented by msvcrt.dll requires special prefix
"\\\\?\\" for paths longer than 260 bytes. Because GetModuleFileName()
returns absolute path, it may be longer than 260 bytes. Add fixup to handle
long paths.
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GetModuleFileName() on Windows 10 has bugs and returns bogus path.
Implement fixups to make path usable for later fopen() call.
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Like for windows builds this will cause to load pci.ids file from the same
directory where is stored application binary. Code is same as for Windows,
just djgpp uses global symbol __dos_argv0 instead of _pgmptr.
Tested with following compile command:
make CROSS_COMPILE=i586-pc-msdosdjgpp- HOST=i586-djgpp ZLIB=no DNS=no IDSDIR=
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When using shared libpci DLL library, it is expected that pci.ids file is
stored in directory where is also libpci DLL library and not in directory
where is application executable.
Based on the build mode and compile options, choose the appropriate
function for retrieving path to the libpci DLL library or application
executable. Also pass correct module argument to GetModuleFileName() call.
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Module file name can have arbitrary length despite all MS examples say
about MAX_PATH upper limit. This limit does not apply for example when
executable is running from network disk with very long UNC paths or
when using "\\??\\" prefix for specifying executable binary path.
So handle buffer truncatenation by retrying GetModuleFileName() call with
larger buffer.
Fixes loading of pci.ids file when lspci.exe binary is running from network
drive with path longer than 260 bytes.
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Extended method allows to access all PCIe registers, including extended
registers starting at 0x100 offset. This method uses 4 reserved buts above
bus bits for PCIe registers. On ARM platforms it is very common for PCIe
controllers. Like standard method, it needs to be properly configured.
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Between accessing address address and data I/O ports it is needed to issue
barriers. Use explicit readl() for barrier and O_DSYNC to bypass CPU cache.
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Microsoft Kernel Local Debugging Driver (kldbgdrv.sys) allow access for
userspace processes to the PCI config space. It supports access up to
65536 domains and whole 4096 bytes long extended PCIe config space. Driver
is signed by Microsoft and is available for both 32-bit and 64-bit systems.
Driver is not part of Windows system and has to be installed via WinDbg
installation package. Standalone installers for WinDbg 6.12.2.633 version:
https://download.microsoft.com/download/A/6/A/A6AC035D-DA3F-4F0C-ADA4-37C8E5D34E3D/setup/WinSDKDebuggingTools_amd64/dbg_amd64.msi
https://download.microsoft.com/download/A/6/A/A6AC035D-DA3F-4F0C-ADA4-37C8E5D34E3D/setup/WinSDKDebuggingTools/dbg_x86.msi
This kldbgdrv.sys API is used by the !pci command of new WinDbg kernel
debugger for displaying PCI config space.
API of this driver is available only for processes with Debug privilege and
only if system was booted with Debugging option.
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Feel free to re-enable it if you find it useful.
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Add requested config space dump of CXL device for testing
Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>
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Add Non-CXL Function Map DVSEC Registers 0-7 decoding according to
DVSEC Revision ID 0.
Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>
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Add MLD DVSEC decoding for CXL device accoring to DVSEC revision ID 0.
Decode Number of Logical Devices Supported.
Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>
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Add Global Persistent Flush DVSEC decoding for CXL port according to
DVSEC Revision ID 0.
Decode GPF Phase 1 Control and GPF Phase 2 Control.
Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>
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Add DVSEC Flex Bus Port for CXL devices according to DVSEC Revision ID 1,
capability decoding, control decoding, and status decoding.
Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>
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Do not call pci_generic_block_read() and pci_generic_block_write()
functions when io is locked. These functions call back same backend
read/write function which tries to lock and unlock io again.
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NT namespace separator may be single or double backslash.
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Since Linux 2.6.8, it is possible to use ioperm() syscall to gain access
for all I/O ports. Because iopl() syscall before Linux 5.5 allowed
userspace to disable interrupts, prefer usage of ioperm() syscall and ask
for access only for PCI ports.
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