CXL3.0: Add DVSEC CXLCtrl3 and missing CXLCtl2

8.1.3 PCIe DVSEC for CXL Devices

2 files changed, 90 insertions, 48 deletions

diff --git a/lib/header.h b/lib/header.h
index 1a04a78..332c97b 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1069,7 +1069,7 @@
 #define PCI_DVSEC_ID_CXL	0	/* Designated Vendor-Specific ID for Intel CXL */
 
 /* PCIe CXL Designated Vendor-Specific Capabilities for Devices: Control, Status */
-#define PCI_CXL_DEV_LEN 0x38 /* CXL Device DVSEC Length */
+#define PCI_CXL_DEV_LEN 0x3c /* CXL Device DVSEC Length */
 #define PCI_CXL_DEV_CAP			0x0a	/* CXL Capability Register */
 #define  PCI_CXL_DEV_CAP_CACHE		0x0001	/* CXL.cache Protocol Support */
 #define  PCI_CXL_DEV_CAP_IO		0x0002	/* CXL.io Protocol Support */
@@ -1087,6 +1087,12 @@
 #define  PCI_CXL_DEV_CTRL_VIRAL		0x4000	/* CXL Viral Handling Enable */
 #define PCI_CXL_DEV_STATUS		0x0e	/* CXL Status Register */
 #define  PCI_CXL_DEV_STATUS_VIRAL	0x4000	/* CXL Viral Handling Status */
+#define PCI_CXL_DEV_CTRL2		0x10	/* CXL Control Register 2 */
+#define  PCI_CXL_DEV_CTRL2_DISABLE_CACHING            0x0001
+#define  PCI_CXL_DEV_CTRL2_INIT_WB_INVAL              0x0002
+#define  PCI_CXL_DEV_CTRL2_INIT_CXL_RST               0x0003
+#define  PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN        0x0004
+#define  PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST  0x0005
 #define PCI_CXL_DEV_STATUS2		0x12
 #define  PCI_CXL_DEV_STATUS_CACHE_INV	0x0001
 #define  PCI_CXL_DEV_STATUS_RC		0x0002  /* Device Reset Complete */
@@ -1110,6 +1116,13 @@
 #define PCI_CXL_DEV_RANGE2_SIZE_LO	0x2c
 #define PCI_CXL_DEV_RANGE2_BASE_HI	0x30
 #define PCI_CXL_DEV_RANGE2_BASE_LO	0x34
+/* From Rev2 */
+#define PCI_CXL_DEV_CAP3  0x38
+#define  PCI_CXL_DEV_CAP3_HDM_STATE_RST_COLD     0x0001
+#define  PCI_CXL_DEV_CAP3_HDM_STATE_RST_WARM     0x0002
+#define  PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT      0x0003
+#define  PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT_CFG  0x0004
+
 
 /* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Ports */
 #define PCI_CXL_PORT_EXT_LEN 0x28 /* CXL Extensions DVSEC for Ports Length */
diff --git a/ls-ecaps.c b/ls-ecaps.c
index a9d8470..f58a5ff 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -701,7 +701,7 @@ cxl_range(u64 base, u64 size, int n)
 
   size &= ~0x0fffffffULL;
 
-  printf("\t\tRange%d: %016"PCI_U64_FMT_X"-%016"PCI_U64_FMT_X"\n", n, base, base + size - 1);
+  printf("\t\tRange%d: %016"PCI_U64_FMT_X"-%016"PCI_U64_FMT_X" [size=0x%"PCI_U64_FMT_X"]\n", n, base, base + size - 1, size);
   printf("\t\t\tValid%c Active%c Type=%s Class=%s interleave=%d timeout=%ds\n",
     FLAG(w, PCI_CXL_RANGE_VALID), FLAG(w, PCI_CXL_RANGE_ACTIVE),
     type[PCI_CXL_RANGE_TYPE(w)], class[PCI_CXL_RANGE_CLASS(w)],
@@ -716,61 +716,90 @@ dvsec_cxl_device(struct device *d, int rev, int where, int len)
   u64 range_base, range_size;
   u16 w;
 
-  if (len < PCI_CXL_DEV_LEN)
+  if (len < 0x38)
     return;
 
   /* Legacy 1.1 revs aren't handled */
-  if (rev < 1)
+  if (rev == 0)
     return;
 
-  w = get_conf_word(d, where + PCI_CXL_DEV_CAP);
-  printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n",
-    FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM),
-    FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL));
-
-  w = get_conf_word(d, where + PCI_CXL_DEV_CTRL);
-  printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n",
-    FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM),
-    PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN),
-    FLAG(w, PCI_CXL_DEV_CTRL_VIRAL));
+  if (rev >= 1) {
+    w = get_conf_word(d, where + PCI_CXL_DEV_CAP);
+    printf("\t\tCXLCap:\tCache%c IO%c Mem%c MemHWInit%c HDMCount %d Viral%c\n",
+      FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM),
+      FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL));
+
+    w = get_conf_word(d, where + PCI_CXL_DEV_CTRL);
+    printf("\t\tCXLCtl:\tCache%c IO%c Mem%c CacheSFCov %d CacheSFGran %d CacheClean%c Viral%c\n",
+      FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM),
+      PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN),
+      FLAG(w, PCI_CXL_DEV_CTRL_VIRAL));
+
+    w = get_conf_word(d, where + PCI_CXL_DEV_STATUS);
+    printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL));
+
+    w = get_conf_word(d, where + PCI_CXL_DEV_CTRL2);
+    printf("\t\tCXLCtl2:\tDisableCaching%c InitCacheWB&Inval%c InitRst%c RstMemClrEn%c",
+      FLAG(w, PCI_CXL_DEV_CTRL2_DISABLE_CACHING),
+      FLAG(w, PCI_CXL_DEV_CTRL2_INIT_WB_INVAL),
+      FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST),
+      FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN));
+    if (rev >= 2) {
+      printf(" DesiredVolatileHDMStateAfterHotReset%c", FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST));
+    }
+    printf("\n");
+
+    w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2);
+    printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n",
+      FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC));
+
+    w = get_conf_word(d, where + PCI_CXL_DEV_CAP2);
+    printf("\t\tCXLCap2:\t");
+    cache_unit_size = BITS(w, 0, 4);
+    cache_size = BITS(w, 8, 8);
+    switch (cache_unit_size)
+      {
+        case PCI_CXL_DEV_CAP2_CACHE_1M:
+          printf("Cache Size: %08x\n", cache_size * (1<<20));
+    break;
+        case PCI_CXL_DEV_CAP2_CACHE_64K:
+          printf("Cache Size: %08x\n", cache_size * (64<<10));
+    break;
+        case PCI_CXL_DEV_CAP2_CACHE_UNK:
+          printf("Cache Size Not Reported\n");
+    break;
+        default:
+          printf("Cache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size);
+    break;
+      }
 
-  w = get_conf_word(d, where + PCI_CXL_DEV_STATUS);
-  printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL));
+    range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32;
+    range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
+    range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32;
+    range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
+    cxl_range(range_base, range_size, 1);
+
+    range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32;
+    range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
+    range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32;
+    range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
+    cxl_range(range_base, range_size, 2);
+  }
 
-  w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2);
-  printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n",
-    FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC));
+  if (rev >= 2) {
+    w = get_conf_word(d, where + PCI_CXL_DEV_CAP3);
+    printf("\t\tCXLCap3:\tDefaultVolatile HDM State After:\tColdReset%c WarmReset%c HotReset%c HotResetConfigurability%c\n",
+      FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_COLD),
+      FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_WARM),
+      FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT),
+      FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT_CFG));
+  }
 
-  w = get_conf_word(d, where + PCI_CXL_DEV_CAP2);
-  cache_unit_size = BITS(w, 0, 4);
-  cache_size = BITS(w, 8, 8);
-  switch (cache_unit_size)
-    {
-      case PCI_CXL_DEV_CAP2_CACHE_1M:
-        printf("\t\tCache Size: %08x\n", cache_size * (1<<20));
-	break;
-      case PCI_CXL_DEV_CAP2_CACHE_64K:
-        printf("\t\tCache Size: %08x\n", cache_size * (64<<10));
-	break;
-      case PCI_CXL_DEV_CAP2_CACHE_UNK:
-        printf("\t\tCache Size Not Reported\n");
-	break;
-      default:
-        printf("\t\tCache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size);
-	break;
-    }
+  // Unparsed data
+  if (len > PCI_CXL_DEV_LEN) {
+    printf("\t\t<?>\n");
+  }
 
-  range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32;
-  range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
-  range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32;
-  range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
-  cxl_range(range_base, range_size, 1);
-
-  range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32;
-  range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
-  range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32;
-  range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
-  cxl_range(range_base, range_size, 2);
 }
 
 static void