Merge remote-tracking branch 'jphaws/cxl-dvsec-decoded'

3 files changed, 560 insertions, 5 deletions

diff --git a/lib/header.h b/lib/header.h
index e74f6d8..63ee03c 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1129,6 +1129,86 @@
 /* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Register Locator */
 #define PCI_CXL_RL_BLOCK1_LO 0x0c
 
+/* PCIe CXL Designated Vendor-Specific Capabilities for Global Persistent Flush */
+#define PCI_CXL_GPF_DEV_LEN         0x10
+#define PCI_CXL_GPF_DEV_PHASE2_DUR  0x0a /* GPF Phase 2 Duration Register */
+#define PCI_CXL_GPF_DEV_PHASE2_POW  0x0c /* GPF Phase 2 Power Register */
+#define PCI_CXL_GPF_DEV_1US     0x0
+#define PCI_CXL_GPF_DEV_10US    0x1
+#define PCI_CXL_GPF_DEV_100US   0x2
+#define PCI_CXL_GPF_DEV_1MS     0x3
+#define PCI_CXL_GPF_DEV_10MS    0x4
+#define PCI_CXL_GPF_DEV_100MS   0x5
+#define PCI_CXL_GPF_DEV_1S      0x6
+#define PCI_CXL_GPF_DEV_10S     0x7
+#define PCI_CXL_GPF_PORT_LEN    0x10
+#define PCI_CXL_GPF_PORT_PHASE1_CTRL  0x0c /* GPF Phase 1 Control Register */
+#define PCI_CXL_GPF_PORT_PHASE2_CTRL 0x0e /* GPF Phase 2 Control Register */
+#define PCI_CXL_GPF_PORT_1US     0x0
+#define PCI_CXL_GPF_PORT_10US    0x1
+#define PCI_CXL_GPF_PORT_100US   0x2
+#define PCI_CXL_GPF_PORT_1MS     0x3
+#define PCI_CXL_GPF_PORT_10MS    0x4
+#define PCI_CXL_GPF_PORT_100MS   0x5
+#define PCI_CXL_GPF_PORT_1S      0x6
+#define PCI_CXL_GPF_PORT_10S     0x7
+
+/* PCIe CXL Designated Vendor-Specific Capabilities for Flex Bus Port */
+#define PCI_CXL_FB_LEN                0x20
+#define PCI_CXL_FB_PORT_CAP           0x0a    /* CXL Flex Bus Port Capability Register */
+#define  PCI_CXL_FB_CAP_CACHE         0x0001  /* CXL.cache Capable */
+#define  PCI_CXL_FB_CAP_IO            0x0002  /* CXL.io Capable */
+#define  PCI_CXL_FB_CAP_MEM           0x0004  /* CXL.mem Capable */
+#define  PCI_CXL_FB_CAP_68B_FLIT      0x0020  /* CXL 68B Flit and VH Capable */
+#define  PCI_CXL_FB_CAP_MULT_LOG_DEV  0x0040  /* CXL Multi-Logical Device Capable */
+#define  PCI_CXL_FB_CAP_256B_FLIT     0x2000  /* CXL Latency Optimized 256B Flit Capable */
+#define  PCI_CXL_FB_CAP_PBR_FLIT      0x4000  /* CXL PBR Flit Capable */
+#define PCI_CXL_FB_PORT_CTRL            0x0c    /* CXL Flex Bus Port Control Register */
+#define  PCI_CXL_FB_CTRL_CACHE          0x0001  /* CXL.cache Enable */
+#define  PCI_CXL_FB_CTRL_IO             0x0002  /* CXL.io Enable */
+#define  PCI_CXL_FB_CTRL_MEM            0x0004  /* CXL.mem Enable */
+#define  PCI_CXL_FB_CTRL_SYNC_HDR_BYP   0x0008  /* CXL Sync Header Bypass Enable */
+#define  PCI_CXL_FB_CTRL_DRFT_BUF       0x0010  /* Drift Buffer Enable */
+#define  PCI_CXL_FB_CTRL_68B_FLIT       0x0020  /* CXL 68B Flit and VH Enable */
+#define  PCI_CXL_FB_CTRL_MULT_LOG_DEV   0x0040  /* CXL Multi Logical Device Enable */
+#define  PCI_CXL_FB_CTRL_RCD            0x0080  /* Disable RCD Training */
+#define  PCI_CXL_FB_CTRL_RETIMER1       0x0100  /* Retimer1 Present */
+#define  PCI_CXL_FB_CTRL_RETIMER2       0x0200  /* Retimer2 Present */
+#define  PCI_CXL_FB_CTRL_256B_FLIT      0x2000  /* CXL Latency Optimized 256B Flit Enable */
+#define  PCI_CXL_FB_CTRL_PBR_FLIT       0x4000  /* CXL PBR Flit Enable */
+#define PCI_CXL_FB_PORT_STATUS            0x0e    /* CXL Flex Bus Port Status Register */
+#define  PCI_CXL_FB_STAT_CACHE            0x0001  /* CXL.cache Enabled */
+#define  PCI_CXL_FB_STAT_IO               0x0002  /* CXL.io Enabled */
+#define  PCI_CXL_FB_STAT_MEM              0x0004  /* CXL.mem Enabled */
+#define  PCI_CXL_FB_STAT_SYNC_HDR_BYP     0x0008  /* CXL Sync Header Bypass Enabled */
+#define  PCI_CXL_FB_STAT_DRFT_BUF         0x0010  /* Drift Buffer Enabled */
+#define  PCI_CXL_FB_STAT_68B_FLIT         0x0020  /* CXL 68B Flit and VH Enabled */
+#define  PCI_CXL_FB_STAT_MULT_LOG_DEV     0x0040  /* CXL Multi Logical Device Enabled */
+#define  PCI_CXL_FB_STAT_256B_FLIT        0x2000  /* CXL Latency Optimized 256B Flit Enabled */
+#define  PCI_CXL_FB_STAT_PBR_FLIT         0x4000  /* CXL PBR Flit Enabled */
+#define PCI_CXL_FB_MOD_TS_DATA              0x10    /* CXL Flex Bus Port Received Modified TS Data Phase1 Register */
+#define PCI_CXL_FB_PORT_CAP2                0x14    /* CXL Flex Bus Port Capability2 Register */
+#define  PCI_CXL_FB_CAP2_NOP_HINT           0x01    /* NOP Hint Capable */
+#define PCI_CXL_FB_PORT_CTRL2               0x18    /* CXL Flex Bus Port Control2 Register */
+#define  PCI_CXL_FB_CTRL2_NOP_HINT          0x01    /* NOP Hint Enable */
+#define PCI_CXL_FB_PORT_STATUS2             0x1c    /* CXL Flex Bus Port Status2 Register */
+
+/* PCIe CXL Designated Vendor-Specific Capabilities for Multi-Logical Device */
+#define PCI_CXL_MLD_LEN     0x10
+#define PCI_CXL_MLD_NUM_LD  0xa
+#define PCI_CXL_MLD_MAX_LD  0x10
+
+/* PCIe CXL Designated Vendor-Specific Capabilities for Non-CXL Function Map */
+#define PCI_CXL_FUN_MAP_LEN     0x2c
+#define PCI_CXL_FUN_MAP_REG_0   0x0c
+#define PCI_CXL_FUN_MAP_REG_1   0x10
+#define PCI_CXL_FUN_MAP_REG_2   0x14
+#define PCI_CXL_FUN_MAP_REG_3   0x18
+#define PCI_CXL_FUN_MAP_REG_4   0x1c
+#define PCI_CXL_FUN_MAP_REG_5   0x20
+#define PCI_CXL_FUN_MAP_REG_6   0x24
+#define PCI_CXL_FUN_MAP_REG_7   0x28
+
 /* Access Control Services */
 #define PCI_ACS_CAP		0x04	/* ACS Capability Register */
 #define PCI_ACS_CAP_VALID	0x0001	/* ACS Source Validation */
diff --git a/ls-ecaps.c b/ls-ecaps.c
index b9a4512..df41626 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -839,6 +839,223 @@ dvsec_cxl_register_locator(struct device *d, int where, int len)
 }
 
 static void
+dvsec_cxl_gpf_device(struct device *d, int where)
+{
+  u32 l;
+  u16 w, duration;
+  u8 time_base, time_scale;
+
+  w = get_conf_word(d, where + PCI_CXL_GPF_DEV_PHASE2_DUR);
+  time_base = BITS(w, 0, 4);
+  time_scale = BITS(w, 8, 4);
+
+  switch (time_scale)
+    {
+      case PCI_CXL_GPF_DEV_100US:
+      case PCI_CXL_GPF_DEV_100MS:
+        duration = time_base * 100;
+        break;
+      case PCI_CXL_GPF_DEV_10US:
+      case PCI_CXL_GPF_DEV_10MS:
+      case PCI_CXL_GPF_DEV_10S:
+        duration = time_base * 10;
+        break;
+      case PCI_CXL_GPF_DEV_1US:
+      case PCI_CXL_GPF_DEV_1MS:
+      case PCI_CXL_GPF_DEV_1S:
+        duration = time_base;
+        break;
+      default:
+        /* Reserved */
+        printf("\t\tReserved time scale encoding %x\n", time_scale);
+        duration = time_base;
+    }
+
+  printf("\t\tGPF Phase 2 Duration: %u%s\n", duration,
+      (time_scale < PCI_CXL_GPF_DEV_1MS) ? "us":
+      (time_scale < PCI_CXL_GPF_DEV_1S) ? "ms" :
+      (time_scale == PCI_CXL_GPF_DEV_1S) ? "s" : "<?>");
+
+  l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW);
+  printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l);
+}
+
+static void
+dvsec_cxl_gpf_port(struct device *d, int where)
+{
+  u16 w, timeout;
+  u8 time_base, time_scale;
+
+  w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE1_CTRL);
+  time_base = BITS(w, 0, 4);
+  time_scale = BITS(w, 8, 4);
+
+  switch (time_scale)
+    {
+      case PCI_CXL_GPF_PORT_100US:
+      case PCI_CXL_GPF_PORT_100MS:
+        timeout = time_base * 100;
+        break;
+      case PCI_CXL_GPF_PORT_10US:
+      case PCI_CXL_GPF_PORT_10MS:
+      case PCI_CXL_GPF_PORT_10S:
+        timeout = time_base * 10;
+        break;
+      case PCI_CXL_GPF_PORT_1US:
+      case PCI_CXL_GPF_PORT_1MS:
+      case PCI_CXL_GPF_PORT_1S:
+        timeout = time_base;
+        break;
+      default:
+        /* Reserved */
+        printf("\t\tReserved time scale encoding %x\n", time_scale);
+        timeout = time_base;
+    }
+
+  printf("\t\tGPF Phase 1 Timeout: %d%s\n", timeout,
+      (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
+      (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
+      (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
+
+  w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE2_CTRL);
+  time_base = BITS(w, 0, 4);
+  time_scale = BITS(w, 8, 4);
+
+  switch (time_scale)
+    {
+      case PCI_CXL_GPF_PORT_100US:
+      case PCI_CXL_GPF_PORT_100MS:
+        timeout = time_base * 100;
+        break;
+      case PCI_CXL_GPF_PORT_10US:
+      case PCI_CXL_GPF_PORT_10MS:
+      case PCI_CXL_GPF_PORT_10S:
+        timeout = time_base * 10;
+        break;
+      case PCI_CXL_GPF_PORT_1US:
+      case PCI_CXL_GPF_PORT_1MS:
+      case PCI_CXL_GPF_PORT_1S:
+        timeout = time_base;
+        break;
+      default:
+        /* Reserved */
+        printf("\t\tReserved time scale encoding %x\n", time_scale);
+        timeout = time_base;
+    }
+
+  printf("\t\tGPF Phase 2 Timeout: %d%s\n", timeout,
+      (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
+      (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
+      (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
+}
+
+static void
+dvsec_cxl_flex_bus(struct device *d, int where, int rev)
+{
+  u16 w;
+  u32 l, data;
+
+  if (rev < 1)
+  {
+    printf("\t\tRevision %d not supported\n", rev);
+    return;
+  }
+
+  w = get_conf_word(d, where + PCI_CXL_FB_PORT_CAP);
+  printf("\t\tFBCap:\tCache%c IO%c Mem%c 68BFlit%c MltLogDev%c",
+      FLAG(w, PCI_CXL_FB_CAP_CACHE), FLAG(w, PCI_CXL_FB_CAP_IO),
+      FLAG(w, PCI_CXL_FB_CAP_MEM), FLAG(w, PCI_CXL_FB_CAP_68B_FLIT),
+      FLAG(w, PCI_CXL_FB_CAP_MULT_LOG_DEV));
+
+  if (rev > 1)
+    printf(" 256BFlit%c PBRFlit%c",
+        FLAG(w, PCI_CXL_FB_CAP_256B_FLIT), FLAG(w, PCI_CXL_FB_CAP_PBR_FLIT));
+
+  w = get_conf_word(d, where + PCI_CXL_FB_PORT_CTRL);
+  printf("\n\t\tFBCtl:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c",
+      FLAG(w, PCI_CXL_FB_CTRL_CACHE), FLAG(w, PCI_CXL_FB_CTRL_IO),
+      FLAG(w, PCI_CXL_FB_CTRL_MEM), FLAG(w, PCI_CXL_FB_CTRL_SYNC_HDR_BYP),
+      FLAG(w, PCI_CXL_FB_CTRL_DRFT_BUF), FLAG(w, PCI_CXL_FB_CTRL_68B_FLIT),
+      FLAG(w, PCI_CXL_FB_CTRL_MULT_LOG_DEV), FLAG(w, PCI_CXL_FB_CTRL_RCD),
+      FLAG(w, PCI_CXL_FB_CTRL_RETIMER1), FLAG(w, PCI_CXL_FB_CTRL_RETIMER2));
+
+  if (rev > 1)
+    printf(" 256BFlit%c PBRFlit%c",
+        FLAG(w, PCI_CXL_FB_CTRL_256B_FLIT), FLAG(w, PCI_CXL_FB_CTRL_PBR_FLIT));
+
+  w = get_conf_word(d, where + PCI_CXL_FB_PORT_STATUS);
+  printf("\n\t\tFBSta:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c",
+      FLAG(w, PCI_CXL_FB_STAT_CACHE), FLAG(w, PCI_CXL_FB_STAT_IO),
+      FLAG(w, PCI_CXL_FB_STAT_MEM), FLAG(w, PCI_CXL_FB_STAT_SYNC_HDR_BYP),
+      FLAG(w, PCI_CXL_FB_STAT_DRFT_BUF), FLAG(w, PCI_CXL_FB_STAT_68B_FLIT),
+      FLAG(w, PCI_CXL_FB_STAT_MULT_LOG_DEV));
+
+  if (rev > 1)
+    printf(" 256BFlit%c PBRFlit%c",
+        FLAG(w, PCI_CXL_FB_STAT_256B_FLIT), FLAG(w, PCI_CXL_FB_STAT_PBR_FLIT));
+
+  l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA);
+  data = BITS(l, 0, 24);
+  printf("\n\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data);
+
+  if (rev > 1)
+  {
+    u8 nop;
+
+    l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2);
+    printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT));
+
+    l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2);
+    printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT));
+
+    l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2);
+    nop = BITS(l, 0, 2);
+    printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop);
+    }
+}
+
+static void
+dvsec_cxl_mld(struct device *d, int where)
+{
+  u16 w;
+
+  w = get_conf_word(d, where + PCI_CXL_MLD_NUM_LD);
+
+  /* Encodings greater than 16 are reserved */
+  if (w && w <= PCI_CXL_MLD_MAX_LD)
+    printf("\t\tNumLogDevs: %d\n", w);
+}
+
+static void
+dvsec_cxl_function_map(struct device *d, int where)
+{
+
+  printf("\t\tFuncMap 0: %08x\n",
+      (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_0)));
+
+  printf("\t\tFuncMap 1: %08x\n",
+    (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_1)));
+
+  printf("\t\tFuncMap 2: %08x\n",
+    (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_2)));
+
+  printf("\t\tFuncMap 3: %08x\n",
+      (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_3)));
+
+  printf("\t\tFuncMap 4: %08x\n",
+      (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_4)));
+
+  printf("\t\tFuncMap 5: %08x\n",
+      (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_5)));
+
+  printf("\t\tFuncMap 6: %08x\n",
+      (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_6)));
+
+  printf("\t\tFuncMap 7: %08x\n",
+      (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_7)));
+}
+
+static void
 cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
 {
   printf(": CXL\n");
@@ -854,25 +1071,25 @@ cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
       dvsec_cxl_device(d, rev, where, len);
       break;
     case 2:
-      printf("\t\tNon-CXL Function Map DVSEC\n");
+      dvsec_cxl_function_map(d, where);
       break;
     case 3:
       dvsec_cxl_port(d, where, len);
       break;
     case 4:
-      printf("\t\tGPF DVSEC for Port\n");
+      dvsec_cxl_gpf_port(d, where);
       break;
     case 5:
-      printf("\t\tGPF DVSEC for Device\n");
+      dvsec_cxl_gpf_device(d, where);
       break;
     case 7:
-      printf("\t\tPCIe DVSEC Flex Bus Port\n");
+      dvsec_cxl_flex_bus(d, where, rev);
       break;
     case 8:
       dvsec_cxl_register_locator(d, where, len);
       break;
     case 9:
-      printf("\t\tMLD DVSEC\n");
+      dvsec_cxl_mld(d, where);
       break;
     default:
       printf("\t\tUnknown ID %04x\n", id);
diff --git a/tests/cap-dvsec-cxl b/tests/cap-dvsec-cxl
index a24e3fb..c5fa9e7 100644
--- a/tests/cap-dvsec-cxl
+++ b/tests/cap-dvsec-cxl
@@ -351,3 +351,261 @@ fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+7f:00.0 CXL: Xilinx Corporation Device c084 (rev 70) (prog-if 10 [CXL Memory Device (CXL 2.x)])
+00: ee 10 84 c0 02 00 10 00 70 10 02 05 10 00 00 00
+10: 0c 00 00 b0 80 03 00 00 0c 00 10 b0 80 03 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 ee 10 84 c0
+30: 00 00 00 00 80 00 00 00 00 00 00 00 05 01 00 00
+40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 10 e0 92 00 21 80 2c 11 30 29 00 00 00 00 00 00
+90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+a0: 00 00 00 00 10 00 11 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e0: 05 f8 88 00 00 00 00 00 00 00 00 00 00 00 00 00
+f0: 00 00 00 00 00 00 00 00 01 00 03 00 08 00 00 00
+100: 0b 00 81 12 56 15 81 00 00 00 00 00 00 00 00 00
+110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+120: 00 00 00 00 00 00 00 00 0e 00 01 1e 00 00 00 00
+130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1e0: 25 00 01 20 01 00 00 80 01 00 00 80 00 00 00 00
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+350: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+370: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+380: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+390: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+3a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+3b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+3c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+3d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+3e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+3f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+400: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+410: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+420: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+430: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+440: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+450: 2e 00 01 50 03 00 00 00 00 00 00 00 02 00 00 00
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+470: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+480: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+490: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+4a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+4b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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