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| author | Jaxon Haws <jaxon.haws@amd.com> | 2022-10-19 16:29:37 -0500 |
|---|---|---|
| committer | Jaxon Haws <jaxon.haws@amd.com> | 2022-11-16 12:25:58 -0600 |
| commit | 4582426202ad6ac6539305dae2c0b70016f014f4 (patch) | |
| tree | 751e6f04bf01fdb46213d90b8ac06926e18a8fdf | |
| parent | 5c75f737b19d4a21756cc2001cce7ec164731f5a (diff) | |
| download | pciutils-4582426202ad6ac6539305dae2c0b70016f014f4.tar.gz | |
lspci: Add support for CXL MLD DVSEC
Add MLD DVSEC decoding for CXL device accoring to DVSEC revision ID 0.
Decode Number of Logical Devices Supported.
Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>
| -rw-r--r-- | lib/header.h | 5 | ||||
| -rw-r--r-- | ls-ecaps.c | 14 |
2 files changed, 18 insertions, 1 deletions
diff --git a/lib/header.h b/lib/header.h index 5dbd8ac..84600b5 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1193,6 +1193,11 @@ #define PCI_CXL_FB_CTRL2_NOP_HINT 0x01 /* NOP Hint Enable */ #define PCI_CXL_FB_PORT_STATUS2 0x1c /* CXL Flex Bus Port Status2 Register */ +/* PCIe CXL Designated Vendor-Specific Capabilities for Multi-Logical Device */ +#define PCI_CXL_MLD_LEN 0x10 +#define PCI_CXL_MLD_NUM_LD 0xa +#define PCI_CXL_MLD_MAX_LD 0x10 + /* Access Control Services */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ #define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */ @@ -1015,6 +1015,18 @@ dvsec_cxl_flex_bus(struct device *d, int where, int rev) } static void +dvsec_cxl_mld(struct device *d, int where) +{ + u16 w; + + w = get_conf_word(d, where + PCI_CXL_MLD_NUM_LD); + + /* Encodings greater than 16 are reserved */ + if (w && w <= PCI_CXL_MLD_MAX_LD) + printf("\t\tNumLogDevs: %d\n", w); +} + +static void cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len) { printf(": CXL\n"); @@ -1048,7 +1060,7 @@ cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len) dvsec_cxl_register_locator(d, where, len); break; case 9: - printf("\t\tMLD DVSEC\n"); + dvsec_cxl_mld(d, where); break; default: printf("\t\tUnknown ID %04x\n", id); |