diff options
| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2015-11-27 16:50:08 -0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2015-11-27 16:50:08 -0800 |
| commit | 4492c05233729ce9c7775ab3e96fa6220c6c3661 (patch) | |
| tree | bf16b6b1974f5da1aa7e8b88ef933863ad0f3025 | |
| parent | 0b6cbae6e8ff595f9b1c37f9d55b9f924f36dc81 (diff) | |
| download | ltsi-kernel-4492c05233729ce9c7775ab3e96fa6220c6c3661.tar.gz | |
more renesas patches
196 files changed, 28611 insertions, 0 deletions
diff --git a/patches.renesas/0130-clk-shmobile-Remove-unneeded-include-linux-clkdev.h.patch b/patches.renesas/0130-clk-shmobile-Remove-unneeded-include-linux-clkdev.h.patch new file mode 100644 index 00000000000000..3104e230468ee6 --- /dev/null +++ b/patches.renesas/0130-clk-shmobile-Remove-unneeded-include-linux-clkdev.h.patch @@ -0,0 +1,149 @@ +From d3d10c1571835d1a74d8746d3c2d0f2c83fd35f3 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 23 Jun 2015 15:09:27 +0200 +Subject: [PATCH 130/326] clk: shmobile: Remove unneeded #include + <linux/clkdev.h> + +The CCF implementations for the various shmobile SoCs don't use clkdev +functionality, hence drop the inclusion of <linux/clkdev.h>. + +Add the missing #include <linux/slab.h>, which was included implicitly +through <asm/clkdev.h> before. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> +(cherry picked from commit 5a1cfafaeab5237523d43cd033e1fb42bf5c1933) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/shmobile/clk-div6.c | 2 +- + drivers/clk/shmobile/clk-r8a73a4.c | 2 +- + drivers/clk/shmobile/clk-r8a7740.c | 2 +- + drivers/clk/shmobile/clk-r8a7778.c | 2 +- + drivers/clk/shmobile/clk-r8a7779.c | 2 +- + drivers/clk/shmobile/clk-rcar-gen2.c | 2 +- + drivers/clk/shmobile/clk-sh73a0.c | 2 +- + 7 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c +index 036a692c7219..6810bfb6ef5e 100644 +--- a/drivers/clk/shmobile/clk-div6.c ++++ b/drivers/clk/shmobile/clk-div6.c +@@ -11,12 +11,12 @@ + */ + + #include <linux/clk-provider.h> +-#include <linux/clkdev.h> + #include <linux/init.h> + #include <linux/io.h> + #include <linux/kernel.h> + #include <linux/of.h> + #include <linux/of_address.h> ++#include <linux/slab.h> + + #define CPG_DIV6_CKSTP BIT(8) + #define CPG_DIV6_DIV(d) ((d) & 0x3f) +diff --git a/drivers/clk/shmobile/clk-r8a73a4.c b/drivers/clk/shmobile/clk-r8a73a4.c +index 29b9a0b0012a..9326204bed9d 100644 +--- a/drivers/clk/shmobile/clk-r8a73a4.c ++++ b/drivers/clk/shmobile/clk-r8a73a4.c +@@ -9,10 +9,10 @@ + */ + + #include <linux/clk-provider.h> +-#include <linux/clkdev.h> + #include <linux/clk/shmobile.h> + #include <linux/init.h> + #include <linux/kernel.h> ++#include <linux/slab.h> + #include <linux/of.h> + #include <linux/of_address.h> + #include <linux/spinlock.h> +diff --git a/drivers/clk/shmobile/clk-r8a7740.c b/drivers/clk/shmobile/clk-r8a7740.c +index 1e2eaae21e01..1e6b1da58065 100644 +--- a/drivers/clk/shmobile/clk-r8a7740.c ++++ b/drivers/clk/shmobile/clk-r8a7740.c +@@ -9,10 +9,10 @@ + */ + + #include <linux/clk-provider.h> +-#include <linux/clkdev.h> + #include <linux/clk/shmobile.h> + #include <linux/init.h> + #include <linux/kernel.h> ++#include <linux/slab.h> + #include <linux/of.h> + #include <linux/of_address.h> + #include <linux/spinlock.h> +diff --git a/drivers/clk/shmobile/clk-r8a7778.c b/drivers/clk/shmobile/clk-r8a7778.c +index cb33b57274bf..e97e28fcfc13 100644 +--- a/drivers/clk/shmobile/clk-r8a7778.c ++++ b/drivers/clk/shmobile/clk-r8a7778.c +@@ -9,9 +9,9 @@ + */ + + #include <linux/clk-provider.h> +-#include <linux/clkdev.h> + #include <linux/clk/shmobile.h> + #include <linux/of_address.h> ++#include <linux/slab.h> + + struct r8a7778_cpg { + struct clk_onecell_data data; +diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c +index 652ecacb6daf..af297963489f 100644 +--- a/drivers/clk/shmobile/clk-r8a7779.c ++++ b/drivers/clk/shmobile/clk-r8a7779.c +@@ -11,12 +11,12 @@ + */ + + #include <linux/clk-provider.h> +-#include <linux/clkdev.h> + #include <linux/clk/shmobile.h> + #include <linux/init.h> + #include <linux/kernel.h> + #include <linux/of.h> + #include <linux/of_address.h> ++#include <linux/slab.h> + #include <linux/spinlock.h> + + #include <dt-bindings/clock/r8a7779-clock.h> +diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c +index acfb6d7dbd6b..9233ebf8cc49 100644 +--- a/drivers/clk/shmobile/clk-rcar-gen2.c ++++ b/drivers/clk/shmobile/clk-rcar-gen2.c +@@ -11,13 +11,13 @@ + */ + + #include <linux/clk-provider.h> +-#include <linux/clkdev.h> + #include <linux/clk/shmobile.h> + #include <linux/init.h> + #include <linux/kernel.h> + #include <linux/math64.h> + #include <linux/of.h> + #include <linux/of_address.h> ++#include <linux/slab.h> + #include <linux/spinlock.h> + + struct rcar_gen2_cpg { +diff --git a/drivers/clk/shmobile/clk-sh73a0.c b/drivers/clk/shmobile/clk-sh73a0.c +index cd529cfe412f..8966f8bbfd72 100644 +--- a/drivers/clk/shmobile/clk-sh73a0.c ++++ b/drivers/clk/shmobile/clk-sh73a0.c +@@ -9,12 +9,12 @@ + */ + + #include <linux/clk-provider.h> +-#include <linux/clkdev.h> + #include <linux/clk/shmobile.h> + #include <linux/init.h> + #include <linux/kernel.h> + #include <linux/of.h> + #include <linux/of_address.h> ++#include <linux/slab.h> + #include <linux/spinlock.h> + + struct sh73a0_cpg { +-- +2.6.2 + diff --git a/patches.renesas/0131-clk-shmobile-emev2-deassert-reset-for-IIC0-1.patch b/patches.renesas/0131-clk-shmobile-emev2-deassert-reset-for-IIC0-1.patch new file mode 100644 index 00000000000000..5aef8f7e985e67 --- /dev/null +++ b/patches.renesas/0131-clk-shmobile-emev2-deassert-reset-for-IIC0-1.patch @@ -0,0 +1,43 @@ +From 6aaa9e5b42a4b3685cb43b47fecc9deafe0def0e Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Sat, 11 Jul 2015 09:46:22 +0200 +Subject: [PATCH 131/326] clk: shmobile: emev2: deassert reset for IIC0/1 + +We have a driver now for IIC, so disable reset for them. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +Signed-off-by: Wolfram Sang <wsa@the-dreams.de> +(cherry picked from commit e1069878b957c5f6d0eb2f441a8372db8d6198b2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/shmobile/clk-emev2.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/clk/shmobile/clk-emev2.c b/drivers/clk/shmobile/clk-emev2.c +index 5b60beb7d0eb..a91825471c79 100644 +--- a/drivers/clk/shmobile/clk-emev2.c ++++ b/drivers/clk/shmobile/clk-emev2.c +@@ -28,6 +28,8 @@ + #define USIBU1_RSTCTRL 0x0ac + #define USIBU2_RSTCTRL 0x0b0 + #define USIBU3_RSTCTRL 0x0b4 ++#define IIC0_RSTCTRL 0x0dc ++#define IIC1_RSTCTRL 0x0e0 + #define STI_RSTCTRL 0x124 + #define STI_CLKSEL 0x688 + +@@ -66,6 +68,10 @@ static void __init emev2_smu_init(void) + emev2_smu_write(2, USIBU1_RSTCTRL); + emev2_smu_write(2, USIBU2_RSTCTRL); + emev2_smu_write(2, USIBU3_RSTCTRL); ++ ++ /* deassert reset for IIC0->IIC1 */ ++ emev2_smu_write(1, IIC0_RSTCTRL); ++ emev2_smu_write(1, IIC1_RSTCTRL); + } + + static void __init emev2_smu_clkdiv_init(struct device_node *np) +-- +2.6.2 + diff --git a/patches.renesas/0132-clk-shmobile-Add-CPG-MSTP-Clock-Domain-support.patch b/patches.renesas/0132-clk-shmobile-Add-CPG-MSTP-Clock-Domain-support.patch new file mode 100644 index 00000000000000..69fe84a4c3aeb0 --- /dev/null +++ b/patches.renesas/0132-clk-shmobile-Add-CPG-MSTP-Clock-Domain-support.patch @@ -0,0 +1,173 @@ +From a48d6af3298fb901cdae017fe804ce72299eca36 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:02 +0200 +Subject: [PATCH 132/326] clk: shmobile: Add CPG/MSTP Clock Domain support + +Add Clock Domain support to the Clock Pulse Generator (CPG) Module Stop +(MSTP) Clocks driver using the generic PM Domain. This allows to +power-manage the module clocks of SoC devices that are part of the +CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. + +SoC devices that are part of the CPG/MSTP Clock Domain and can be +power-managed through an MSTP clock should be tagged in DT with a +proper "power-domains" property. + +The CPG/MSTP Clock Domain code will scan such devices for clocks that +are suitable for power-managing the device, by looking for a clock that +is compatible with "renesas,cpg-mstp-clocks". + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Reviewed-by: Kevin Hilman <khilman@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 752b5ed5f6998e118626feea7375782c4cf5aad6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/shmobile/clk-mstp.c | 87 +++++++++++++++++++++++++++++++++++++++++ + include/linux/clk/shmobile.h | 12 ++++++ + 2 files changed, 99 insertions(+) + +diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c +index 2d2fe773ac81..b1df7b2f1e97 100644 +--- a/drivers/clk/shmobile/clk-mstp.c ++++ b/drivers/clk/shmobile/clk-mstp.c +@@ -2,6 +2,7 @@ + * R-Car MSTP clocks + * + * Copyright (C) 2013 Ideas On Board SPRL ++ * Copyright (C) 2015 Glider bvba + * + * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> + * +@@ -10,11 +11,16 @@ + * the Free Software Foundation; version 2 of the License. + */ + ++#include <linux/clk.h> + #include <linux/clk-provider.h> + #include <linux/clkdev.h> ++#include <linux/clk/shmobile.h> ++#include <linux/device.h> + #include <linux/io.h> + #include <linux/of.h> + #include <linux/of_address.h> ++#include <linux/pm_clock.h> ++#include <linux/pm_domain.h> + #include <linux/spinlock.h> + + /* +@@ -236,3 +242,84 @@ static void __init cpg_mstp_clocks_init(struct device_node *np) + of_clk_add_provider(np, of_clk_src_onecell_get, &group->data); + } + CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init); ++ ++ ++#ifdef CONFIG_PM_GENERIC_DOMAINS_OF ++int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev) ++{ ++ struct device_node *np = dev->of_node; ++ struct of_phandle_args clkspec; ++ struct clk *clk; ++ int i = 0; ++ int error; ++ ++ while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, ++ &clkspec)) { ++ if (of_device_is_compatible(clkspec.np, ++ "renesas,cpg-mstp-clocks")) ++ goto found; ++ ++ of_node_put(clkspec.np); ++ i++; ++ } ++ ++ return 0; ++ ++found: ++ clk = of_clk_get_from_provider(&clkspec); ++ of_node_put(clkspec.np); ++ ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ error = pm_clk_create(dev); ++ if (error) { ++ dev_err(dev, "pm_clk_create failed %d\n", error); ++ goto fail_put; ++ } ++ ++ error = pm_clk_add_clk(dev, clk); ++ if (error) { ++ dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error); ++ goto fail_destroy; ++ } ++ ++ return 0; ++ ++fail_destroy: ++ pm_clk_destroy(dev); ++fail_put: ++ clk_put(clk); ++ return error; ++} ++ ++void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev) ++{ ++ if (!list_empty(&dev->power.subsys_data->clock_list)) ++ pm_clk_destroy(dev); ++} ++ ++void __init cpg_mstp_add_clk_domain(struct device_node *np) ++{ ++ struct generic_pm_domain *pd; ++ u32 ncells; ++ ++ if (of_property_read_u32(np, "#power-domain-cells", &ncells)) { ++ pr_warn("%s lacks #power-domain-cells\n", np->full_name); ++ return; ++ } ++ ++ pd = kzalloc(sizeof(*pd), GFP_KERNEL); ++ if (!pd) ++ return; ++ ++ pd->name = np->name; ++ ++ pd->flags = GENPD_FLAG_PM_CLK; ++ pm_genpd_init(pd, &simple_qos_governor, false); ++ pd->attach_dev = cpg_mstp_attach_dev; ++ pd->detach_dev = cpg_mstp_detach_dev; ++ ++ of_genpd_add_provider_simple(np, pd); ++} ++#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */ +diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h +index 63a8159c4e64..cb19cc1865ca 100644 +--- a/include/linux/clk/shmobile.h ++++ b/include/linux/clk/shmobile.h +@@ -16,8 +16,20 @@ + + #include <linux/types.h> + ++struct device; ++struct device_node; ++struct generic_pm_domain; ++ + void r8a7778_clocks_init(u32 mode); + void r8a7779_clocks_init(u32 mode); + void rcar_gen2_clocks_init(u32 mode); + ++#ifdef CONFIG_PM_GENERIC_DOMAINS_OF ++void cpg_mstp_add_clk_domain(struct device_node *np); ++int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev); ++void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev); ++#else ++static inline void cpg_mstp_add_clk_domain(struct device_node *np) {} ++#endif ++ + #endif +-- +2.6.2 + diff --git a/patches.renesas/0133-clk-shmobile-r8a7778-Add-CPG-MSTP-Clock-Domain-suppo.patch b/patches.renesas/0133-clk-shmobile-r8a7778-Add-CPG-MSTP-Clock-Domain-suppo.patch new file mode 100644 index 00000000000000..220d4b198879bb --- /dev/null +++ b/patches.renesas/0133-clk-shmobile-r8a7778-Add-CPG-MSTP-Clock-Domain-suppo.patch @@ -0,0 +1,109 @@ +From 7de81b01075a4192386f6f1b4b66d9ec986d06d2 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:03 +0200 +Subject: [PATCH 133/326] clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain + support + +Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG) +driver using the generic PM Domain. This allows to power-manage the +module clocks of SoC devices that are part of the CPG/MSTP Clock Domain +using Runtime PM, or for system suspend/resume. + +SoC devices that are part of the CPG/MSTP Clock Domain and can be +power-managed through an MSTP clock should be tagged in DT with a proper +"power-domains" property. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8bc964aa25e56b7445ffebffccd455f959370a16) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/clock/renesas,r8a7778-cpg-clocks.txt | 29 +++++++++++++++++++--- + arch/arm/mach-shmobile/Kconfig | 1 + + drivers/clk/shmobile/clk-r8a7778.c | 2 ++ + 3 files changed, 29 insertions(+), 3 deletions(-) + +diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt +index 2f3747fdcf1c..e4cdaf1cb333 100644 +--- a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt ++++ b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt +@@ -1,7 +1,9 @@ + * Renesas R8A7778 Clock Pulse Generator (CPG) + + The CPG generates core clocks for the R8A7778. It includes two PLLs and +-several fixed ratio dividers ++several fixed ratio dividers. ++The CPG also provides a Clock Domain for SoC devices, in combination with the ++CPG Module Stop (MSTP) Clocks. + + Required Properties: + +@@ -10,10 +12,18 @@ Required Properties: + - #clock-cells: Must be 1 + - clock-output-names: The names of the clocks. Supported clocks are + "plla", "pllb", "b", "out", "p", "s", and "s1". ++ - #power-domain-cells: Must be 0 + ++SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed ++through an MSTP clock should refer to the CPG device node in their ++"power-domains" property, as documented by the generic PM domain bindings in ++Documentation/devicetree/bindings/power/power_domain.txt. + +-Example +-------- ++ ++Examples ++-------- ++ ++ - CPG device node: + + cpg_clocks: cpg_clocks@ffc80000 { + compatible = "renesas,r8a7778-cpg-clocks"; +@@ -22,4 +32,17 @@ Example + clocks = <&extal_clk>; + clock-output-names = "plla", "pllb", "b", + "out", "p", "s", "s1"; ++ #power-domain-cells = <0>; ++ }; ++ ++ ++ - CPG/MSTP Clock Domain member device node: ++ ++ sdhi0: sd@ffe4c000 { ++ compatible = "renesas,sdhi-r8a7778"; ++ reg = <0xffe4c000 0x100>; ++ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; ++ power-domains = <&cpg_clocks>; ++ status = "disabled"; + }; +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 45006479d461..e14fa5e87475 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -4,6 +4,7 @@ config ARCH_SHMOBILE + + config PM_RCAR + bool ++ select PM_GENERIC_DOMAINS if PM + + config PM_RMOBILE + bool +diff --git a/drivers/clk/shmobile/clk-r8a7778.c b/drivers/clk/shmobile/clk-r8a7778.c +index e97e28fcfc13..87c1d2f2fb57 100644 +--- a/drivers/clk/shmobile/clk-r8a7778.c ++++ b/drivers/clk/shmobile/clk-r8a7778.c +@@ -124,6 +124,8 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np) + } + + of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); ++ ++ cpg_mstp_add_clk_domain(np); + } + + CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks", +-- +2.6.2 + diff --git a/patches.renesas/0134-clk-shmobile-r8a7779-Add-CPG-MSTP-Clock-Domain-suppo.patch b/patches.renesas/0134-clk-shmobile-r8a7779-Add-CPG-MSTP-Clock-Domain-suppo.patch new file mode 100644 index 00000000000000..c6a8cfbe283ad3 --- /dev/null +++ b/patches.renesas/0134-clk-shmobile-r8a7779-Add-CPG-MSTP-Clock-Domain-suppo.patch @@ -0,0 +1,100 @@ +From 216ba3c27e290b48c78b4f4f33ba0266c6a78b67 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:04 +0200 +Subject: [PATCH 134/326] clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain + support + +Add Clock Domain support to the R-Car H1 Clock Pulse Generator (CPG) +driver using the generic PM Domain. This allows to power-manage the +module clocks of SoC devices that are part of the CPG/MSTP Clock Domain +using Runtime PM, or for system suspend/resume. + +SoC devices that are part of the CPG/MSTP Clock Domain and can be +power-managed through an MSTP clock should be tagged in DT with a proper +"power-domains" property. + +Also update the reg property in the DT binding doc example to match the +actual dtsi, which uses #address-cells and #size-cells == 1, not 2. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b31fc90c14d9e584ac19983686cecab3e0764289) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/clock/renesas,r8a7779-cpg-clocks.txt | 30 +++++++++++++++++++--- + drivers/clk/shmobile/clk-r8a7779.c | 2 ++ + 2 files changed, 28 insertions(+), 4 deletions(-) + +diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt +index ed3c8cb12f4e..8c81547c29f5 100644 +--- a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt ++++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt +@@ -1,7 +1,9 @@ + * Renesas R8A7779 Clock Pulse Generator (CPG) + + The CPG generates core clocks for the R8A7779. It includes one PLL and +-several fixed ratio dividers ++several fixed ratio dividers. ++The CPG also provides a Clock Domain for SoC devices, in combination with the ++CPG Module Stop (MSTP) Clocks. + + Required Properties: + +@@ -12,16 +14,36 @@ Required Properties: + - #clock-cells: Must be 1 + - clock-output-names: The names of the clocks. Supported clocks are "plla", + "z", "zs", "s", "s1", "p", "b", "out". ++ - #power-domain-cells: Must be 0 + ++SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed ++through an MSTP clock should refer to the CPG device node in their ++"power-domains" property, as documented by the generic PM domain bindings in ++Documentation/devicetree/bindings/power/power_domain.txt. + +-Example +-------- ++ ++Examples ++-------- ++ ++ - CPG device node: + + cpg_clocks: cpg_clocks@ffc80000 { + compatible = "renesas,r8a7779-cpg-clocks"; +- reg = <0 0xffc80000 0 0x30>; ++ reg = <0xffc80000 0x30>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "plla", "z", "zs", "s", "s1", "p", + "b", "out"; ++ #power-domain-cells = <0>; ++ }; ++ ++ ++ - CPG/MSTP Clock Domain member device node: ++ ++ sata: sata@fc600000 { ++ compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; ++ reg = <0xfc600000 0x2000>; ++ interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp1_clks R8A7779_CLK_SATA>; ++ power-domains = <&cpg_clocks>; + }; +diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c +index af297963489f..92275c5f2c60 100644 +--- a/drivers/clk/shmobile/clk-r8a7779.c ++++ b/drivers/clk/shmobile/clk-r8a7779.c +@@ -168,6 +168,8 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) + } + + of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); ++ ++ cpg_mstp_add_clk_domain(np); + } + CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks", + r8a7779_cpg_clocks_init); +-- +2.6.2 + diff --git a/patches.renesas/0135-clk-shmobile-rcar-gen2-Add-CPG-MSTP-Clock-Domain-sup.patch b/patches.renesas/0135-clk-shmobile-rcar-gen2-Add-CPG-MSTP-Clock-Domain-sup.patch new file mode 100644 index 00000000000000..2fddc1e01a5808 --- /dev/null +++ b/patches.renesas/0135-clk-shmobile-rcar-gen2-Add-CPG-MSTP-Clock-Domain-sup.patch @@ -0,0 +1,93 @@ +From fbd31c4fb0ca3644a5f451a81244aae38115a16d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:05 +0200 +Subject: [PATCH 135/326] clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain + support + +Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) +driver using the generic PM Domain. This allows to power-manage the +module clocks of SoC devices that are part of the CPG/MSTP Clock Domain +using Runtime PM, or for system suspend/resume. + +SoC devices that are part of the CPG/MSTP Clock Domain and can be +power-managed through an MSTP clock should be tagged in DT with a proper +"power-domains" property. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 63e05d9365dc25ae71bdde436b27c49daedf1977) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../clock/renesas,rcar-gen2-cpg-clocks.txt | 26 ++++++++++++++++++++-- + drivers/clk/shmobile/clk-rcar-gen2.c | 2 ++ + 2 files changed, 26 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +index b02944fba9de..6d49d35bee2c 100644 +--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt ++++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +@@ -2,6 +2,8 @@ + + The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs + and several fixed ratio dividers. ++The CPG also provides a Clock Domain for SoC devices, in combination with the ++CPG Module Stop (MSTP) Clocks. + + Required Properties: + +@@ -20,10 +22,18 @@ Required Properties: + - clock-output-names: The names of the clocks. Supported clocks are "main", + "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and + "adsp" ++ - #power-domain-cells: Must be 0 + ++SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed ++through an MSTP clock should refer to the CPG device node in their ++"power-domains" property, as documented by the generic PM domain bindings in ++Documentation/devicetree/bindings/power/power_domain.txt. + +-Example +-------- ++ ++Examples ++-------- ++ ++ - CPG device node: + + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7790-cpg-clocks", +@@ -34,4 +44,16 @@ Example + clock-output-names = "main", "pll0, "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "sd1", "z", + "rcan", "adsp"; ++ #power-domain-cells = <0>; ++ }; ++ ++ ++ - CPG/MSTP Clock Domain member device node: ++ ++ thermal@e61f0000 { ++ compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; ++ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; ++ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; ++ power-domains = <&cpg_clocks>; + }; +diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c +index 9233ebf8cc49..745496f7ee9c 100644 +--- a/drivers/clk/shmobile/clk-rcar-gen2.c ++++ b/drivers/clk/shmobile/clk-rcar-gen2.c +@@ -415,6 +415,8 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np) + } + + of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); ++ ++ cpg_mstp_add_clk_domain(np); + } + CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks", + rcar_gen2_cpg_clocks_init); +-- +2.6.2 + diff --git a/patches.renesas/0136-clk-shmobile-rz-Add-CPG-MSTP-Clock-Domain-support.patch b/patches.renesas/0136-clk-shmobile-rz-Add-CPG-MSTP-Clock-Domain-support.patch new file mode 100644 index 00000000000000..7481fc9eb357ea --- /dev/null +++ b/patches.renesas/0136-clk-shmobile-rz-Add-CPG-MSTP-Clock-Domain-support.patch @@ -0,0 +1,115 @@ +From bc699f83f546d9fc5a084aaf85dba3d0f606b286 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:06 +0200 +Subject: [PATCH 136/326] clk: shmobile: rz: Add CPG/MSTP Clock Domain support + +Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver +using the generic PM Domain. This allows to power-manage the module +clocks of SoC devices that are part of the CPG/MSTP Clock Domain using +Runtime PM, or for system suspend/resume. + +SoC devices that are part of the CPG/MSTP Clock Domain and can be +power-managed through an MSTP clock should be tagged in DT with a proper +"power-domains" property. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f04b486d34ac6bab2aaa3988ee098b2bad3950de) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/clock/renesas,rz-cpg-clocks.txt | 29 ++++++++++++++++++++-- + arch/arm/mach-shmobile/Kconfig | 1 + + drivers/clk/shmobile/clk-rz.c | 3 +++ + 3 files changed, 31 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt +index 98a257492522..72b738fc5600 100644 +--- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt ++++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt +@@ -2,6 +2,8 @@ + + The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable + CPU and GPU clocks, and several fixed ratio dividers. ++The CPG also provides a Clock Domain for SoC devices, in combination with the ++CPG Module Stop (MSTP) Clocks. + + Required Properties: + +@@ -14,10 +16,18 @@ Required Properties: + - #clock-cells: Must be 1 + - clock-output-names: The names of the clocks. Supported clocks are "pll", + "i", and "g" ++ - #power-domain-cells: Must be 0 + ++SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed ++through an MSTP clock should refer to the CPG device node in their ++"power-domains" property, as documented by the generic PM domain bindings in ++Documentation/devicetree/bindings/power/power_domain.txt. + +-Example +-------- ++ ++Examples ++-------- ++ ++ - CPG device node: + + cpg_clocks: cpg_clocks@fcfe0000 { + #clock-cells = <1>; +@@ -26,4 +36,19 @@ Example + reg = <0xfcfe0000 0x18>; + clocks = <&extal_clk>, <&usb_x1_clk>; + clock-output-names = "pll", "i", "g"; ++ #power-domain-cells = <0>; ++ }; ++ ++ ++ - CPG/MSTP Clock Domain member device node: ++ ++ mtu2: timer@fcff0000 { ++ compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; ++ reg = <0xfcff0000 0x400>; ++ interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "tgi0a"; ++ clocks = <&mstp3_clks R7S72100_CLK_MTU2>; ++ clock-names = "fck"; ++ power-domains = <&cpg_clocks>; ++ status = "disabled"; + }; +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index e14fa5e87475..34eac88a9889 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -51,6 +51,7 @@ config ARCH_EMEV2 + + config ARCH_R7S72100 + bool "RZ/A1H (R7S72100)" ++ select PM_GENERIC_DOMAINS if PM + select SYS_SUPPORTS_SH_MTU2 + + config ARCH_R8A73A4 +diff --git a/drivers/clk/shmobile/clk-rz.c b/drivers/clk/shmobile/clk-rz.c +index 7e68e8630962..9766e3cb595f 100644 +--- a/drivers/clk/shmobile/clk-rz.c ++++ b/drivers/clk/shmobile/clk-rz.c +@@ -10,6 +10,7 @@ + */ + + #include <linux/clk-provider.h> ++#include <linux/clk/shmobile.h> + #include <linux/init.h> + #include <linux/kernel.h> + #include <linux/of.h> +@@ -99,5 +100,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np) + } + + of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); ++ ++ cpg_mstp_add_clk_domain(np); + } + CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init); +-- +2.6.2 + diff --git a/patches.renesas/0137-regulator-da9210-Add-optional-interrupt-support.patch b/patches.renesas/0137-regulator-da9210-Add-optional-interrupt-support.patch new file mode 100644 index 00000000000000..4572969ec29a3a --- /dev/null +++ b/patches.renesas/0137-regulator-da9210-Add-optional-interrupt-support.patch @@ -0,0 +1,138 @@ +From 0d2570a3cf4b90d6e029822245afe3986d716781 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 24 Jun 2015 14:14:21 +0200 +Subject: [PATCH 137/326] regulator: da9210: Add optional interrupt support + +Add optional interrupt support to the da9210 regulator driver, to handle +over-current, under- and over-voltage, and over-temperature events. + +Only the interrupt sources for which we handle events are unmasked, to +avoid interrupts we cannot handle. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 4245746037e379dc9f1388e422d52001cd431921) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../devicetree/bindings/regulator/da9210.txt | 4 ++ + drivers/regulator/da9210-regulator.c | 75 ++++++++++++++++++++++ + 2 files changed, 79 insertions(+) + +diff --git a/Documentation/devicetree/bindings/regulator/da9210.txt b/Documentation/devicetree/bindings/regulator/da9210.txt +index 3297c53cb915..7aa9b1fa6b21 100644 +--- a/Documentation/devicetree/bindings/regulator/da9210.txt ++++ b/Documentation/devicetree/bindings/regulator/da9210.txt +@@ -5,6 +5,10 @@ Required properties: + - compatible: must be "dlg,da9210" + - reg: the i2c slave address of the regulator. It should be 0x68. + ++Optional properties: ++ ++- interrupts: a reference to the DA9210 interrupt, if available. ++ + Any standard regulator properties can be used to configure the single da9210 + DCDC. + +diff --git a/drivers/regulator/da9210-regulator.c b/drivers/regulator/da9210-regulator.c +index f0489cb9018b..8e39f7457bc3 100644 +--- a/drivers/regulator/da9210-regulator.c ++++ b/drivers/regulator/da9210-regulator.c +@@ -22,6 +22,8 @@ + #include <linux/i2c.h> + #include <linux/module.h> + #include <linux/init.h> ++#include <linux/interrupt.h> ++#include <linux/irq.h> + #include <linux/slab.h> + #include <linux/regulator/driver.h> + #include <linux/regulator/machine.h> +@@ -120,6 +122,55 @@ static int da9210_get_current_limit(struct regulator_dev *rdev) + return da9210_buck_limits[sel]; + } + ++static irqreturn_t da9210_irq_handler(int irq, void *data) ++{ ++ struct da9210 *chip = data; ++ unsigned int val, handled = 0; ++ int error, ret = IRQ_NONE; ++ ++ error = regmap_read(chip->regmap, DA9210_REG_EVENT_B, &val); ++ if (error < 0) ++ goto error_i2c; ++ ++ if (val & DA9210_E_OVCURR) { ++ regulator_notifier_call_chain(chip->rdev, ++ REGULATOR_EVENT_OVER_CURRENT, ++ NULL); ++ handled |= DA9210_E_OVCURR; ++ } ++ if (val & DA9210_E_NPWRGOOD) { ++ regulator_notifier_call_chain(chip->rdev, ++ REGULATOR_EVENT_UNDER_VOLTAGE, ++ NULL); ++ handled |= DA9210_E_NPWRGOOD; ++ } ++ if (val & (DA9210_E_TEMP_WARN | DA9210_E_TEMP_CRIT)) { ++ regulator_notifier_call_chain(chip->rdev, ++ REGULATOR_EVENT_OVER_TEMP, NULL); ++ handled |= val & (DA9210_E_TEMP_WARN | DA9210_E_TEMP_CRIT); ++ } ++ if (val & DA9210_E_VMAX) { ++ regulator_notifier_call_chain(chip->rdev, ++ REGULATOR_EVENT_REGULATION_OUT, ++ NULL); ++ handled |= DA9210_E_VMAX; ++ } ++ if (handled) { ++ /* Clear handled events */ ++ error = regmap_write(chip->regmap, DA9210_REG_EVENT_B, handled); ++ if (error < 0) ++ goto error_i2c; ++ ++ ret = IRQ_HANDLED; ++ } ++ ++ return ret; ++ ++error_i2c: ++ dev_err(regmap_get_device(chip->regmap), "I2C error : %d\n", error); ++ return ret; ++} ++ + /* + * I2C driver interface functions + */ +@@ -168,6 +219,30 @@ static int da9210_i2c_probe(struct i2c_client *i2c, + } + + chip->rdev = rdev; ++ if (i2c->irq) { ++ error = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, ++ da9210_irq_handler, ++ IRQF_TRIGGER_LOW | ++ IRQF_ONESHOT | IRQF_SHARED, ++ "da9210", chip); ++ if (error) { ++ dev_err(&i2c->dev, "Failed to request IRQ%u: %d\n", ++ i2c->irq, error); ++ return error; ++ } ++ ++ error = regmap_update_bits(chip->regmap, DA9210_REG_MASK_B, ++ DA9210_M_OVCURR | DA9210_M_NPWRGOOD | ++ DA9210_M_TEMP_WARN | ++ DA9210_M_TEMP_CRIT | DA9210_M_VMAX, 0); ++ if (error < 0) { ++ dev_err(&i2c->dev, "Failed to update mask reg: %d\n", ++ error); ++ return error; ++ } ++ } else { ++ dev_warn(&i2c->dev, "No IRQ configured\n"); ++ } + + i2c_set_clientdata(i2c, chip); + +-- +2.6.2 + diff --git a/patches.renesas/0138-gpio-rcar-Fine-grained-Runtime-PM-support.patch b/patches.renesas/0138-gpio-rcar-Fine-grained-Runtime-PM-support.patch new file mode 100644 index 00000000000000..cd6d500a1d07c1 --- /dev/null +++ b/patches.renesas/0138-gpio-rcar-Fine-grained-Runtime-PM-support.patch @@ -0,0 +1,93 @@ +From 16ea8e361fb43dcdc02d2707bc75f078b1e3b9c4 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 25 Jun 2015 16:45:57 +0200 +Subject: [PATCH 138/326] gpio: rcar: Fine-grained Runtime PM support + +Currently gpio modules are runtime-resumed at probe time. This means the +gpio module will be active all the time (except during system suspend, +if not configured as a wake-up source). + +While an R-Car Gen2 gpio module retains pins configured for output at +the requested level while put in standby mode, gpio registercannot be +accessed while suspended. Unfortunately pm_runtime_get_sync() cannot be +called from all contexts where gpio register access is needed. Hence +move the Runtime PM handling from probe/remove time to gpio request/free +time, which is probably the best we can do. + +On r8a7791/koelsch, gpio modules 0, 1, 3, and 4 are now suspended during +normal use (gpio2 is used for LEDs and regulators, gpio5 for keys, gpio6 +for SD-Card CD & WP, gpio7 for keys and regulators). + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 65194cb174b873448b208eb6e04ecb72237af76e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpio/gpio-rcar.c | 20 ++++++++++++++++---- + 1 file changed, 16 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c +index 1e14a6c74ed1..4fc13ce9c60a 100644 +--- a/drivers/gpio/gpio-rcar.c ++++ b/drivers/gpio/gpio-rcar.c +@@ -251,17 +251,32 @@ static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, + + static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) + { +- return pinctrl_request_gpio(chip->base + offset); ++ struct gpio_rcar_priv *p = gpio_to_priv(chip); ++ int error; ++ ++ error = pm_runtime_get_sync(&p->pdev->dev); ++ if (error < 0) ++ return error; ++ ++ error = pinctrl_request_gpio(chip->base + offset); ++ if (error) ++ pm_runtime_put(&p->pdev->dev); ++ ++ return error; + } + + static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) + { ++ struct gpio_rcar_priv *p = gpio_to_priv(chip); ++ + pinctrl_free_gpio(chip->base + offset); + + /* Set the GPIO as an input to ensure that the next GPIO request won't + * drive the GPIO pin as an output. + */ + gpio_rcar_config_general_input_output_mode(chip, offset, false); ++ ++ pm_runtime_put(&p->pdev->dev); + } + + static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) +@@ -405,7 +420,6 @@ static int gpio_rcar_probe(struct platform_device *pdev) + } + + pm_runtime_enable(dev); +- pm_runtime_get_sync(dev); + + io = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); +@@ -487,7 +501,6 @@ static int gpio_rcar_probe(struct platform_device *pdev) + err1: + gpiochip_remove(gpio_chip); + err0: +- pm_runtime_put(dev); + pm_runtime_disable(dev); + return ret; + } +@@ -498,7 +511,6 @@ static int gpio_rcar_remove(struct platform_device *pdev) + + gpiochip_remove(&p->gpio_chip); + +- pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); + return 0; + } +-- +2.6.2 + diff --git a/patches.renesas/0139-gpio-rcar-Add-r8a7795-R-Car-H3-support.patch b/patches.renesas/0139-gpio-rcar-Add-r8a7795-R-Car-H3-support.patch new file mode 100644 index 00000000000000..b161605999874e --- /dev/null +++ b/patches.renesas/0139-gpio-rcar-Add-r8a7795-R-Car-H3-support.patch @@ -0,0 +1,48 @@ +From afb2129c0479f584c84ee659be293b1ffc52ad70 Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Tue, 21 Jul 2015 11:08:50 +0200 +Subject: [PATCH 139/326] gpio: rcar: Add r8a7795 (R-Car H3) support + +R-Car Gen3's GPIO blocks are identical to Gen2's in every respect. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 8cd14702be9bcb2ec45e1ec30af04aea9b965708) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 + + drivers/gpio/gpio-rcar.c | 4 ++++ + 2 files changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +index 38fb86f28ba2..f60e2f477e93 100644 +--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt ++++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +@@ -9,6 +9,7 @@ Required Properties: + - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller. + - "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller. + - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller. ++ - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller. + - "renesas,gpio-rcar": for generic R-Car GPIO controller. + + - reg: Base address and length of each memory resource used by the GPIO +diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c +index 4fc13ce9c60a..2a8122444614 100644 +--- a/drivers/gpio/gpio-rcar.c ++++ b/drivers/gpio/gpio-rcar.c +@@ -342,6 +342,10 @@ static const struct of_device_id gpio_rcar_of_table[] = { + .compatible = "renesas,gpio-r8a7794", + .data = &gpio_rcar_info_gen2, + }, { ++ .compatible = "renesas,gpio-r8a7795", ++ /* Gen3 GPIO is identical to Gen2. */ ++ .data = &gpio_rcar_info_gen2, ++ }, { + .compatible = "renesas,gpio-rcar", + .data = &gpio_rcar_info_gen1, + }, { +-- +2.6.2 + diff --git a/patches.renesas/0140-irqchip-renesas-irqc-Get-rid-of-IRQF_VALID.patch b/patches.renesas/0140-irqchip-renesas-irqc-Get-rid-of-IRQF_VALID.patch new file mode 100644 index 00000000000000..ac6e92e30a7802 --- /dev/null +++ b/patches.renesas/0140-irqchip-renesas-irqc-Get-rid-of-IRQF_VALID.patch @@ -0,0 +1,35 @@ +From 628833e3c01289566e78ba8019d98f85901f8948 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm+renesas@opensource.se> +Date: Mon, 20 Jul 2015 19:06:14 +0900 +Subject: [PATCH 140/326] irqchip/renesas-irqc: Get rid of IRQF_VALID + +IRQF_VALID is not needed on ARM anymore, so get rid of it. + +Signed-off-by: Magnus Damm <damm+renesas@opensource.se> +Cc: jason@lakedaemon.net +Cc: geert+renesas@glider.be +Cc: horms@verge.net.au +Cc: Magnus Damm <magnus.damm@gmail.com> +Link: http://lkml.kernel.org/r/20150720100614.2552.86867.sendpatchset@little-apple +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +(cherry picked from commit 35c3f67f11849d80cc0e3cd3dd898977567c9c29) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/irqchip/irq-renesas-irqc.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c +index 778bd076aeea..74e980fa7b4e 100644 +--- a/drivers/irqchip/irq-renesas-irqc.c ++++ b/drivers/irqchip/irq-renesas-irqc.c +@@ -162,7 +162,6 @@ static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq, + irqc_dbg(&p->irq[hw], "map"); + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); +- set_irq_flags(virq, IRQF_VALID); /* kill me now */ + return 0; + } + +-- +2.6.2 + diff --git a/patches.renesas/0141-irqchip-renesas-irqc-Use-linear-IRQ-domain.patch b/patches.renesas/0141-irqchip-renesas-irqc-Use-linear-IRQ-domain.patch new file mode 100644 index 00000000000000..02ce826e3b50ef --- /dev/null +++ b/patches.renesas/0141-irqchip-renesas-irqc-Use-linear-IRQ-domain.patch @@ -0,0 +1,40 @@ +From 11a78319e3b2670e04d8b27e8b6c49db69169a07 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm+renesas@opensource.se> +Date: Mon, 20 Jul 2015 19:06:25 +0900 +Subject: [PATCH 141/326] irqchip/renesas-irqc: Use linear IRQ domain + +Use linear IRQ domain instead of irq_domain_add_simple() that also +handles non-DT cases. This reduces the delta between the IRQC code and +the generic chip implementation. + +Signed-off-by: Magnus Damm <damm+renesas@opensource.se> +Cc: jason@lakedaemon.net +Cc: geert+renesas@glider.be +Cc: horms@verge.net.au +Cc: Magnus Damm <magnus.damm@gmail.com> +Link: http://lkml.kernel.org/r/20150720100625.2552.63939.sendpatchset@little-apple +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +(cherry picked from commit 7d153751c79e84a88e8c80e82ee5293085b9081b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/irqchip/irq-renesas-irqc.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c +index 74e980fa7b4e..7f750920ed90 100644 +--- a/drivers/irqchip/irq-renesas-irqc.c ++++ b/drivers/irqchip/irq-renesas-irqc.c +@@ -242,8 +242,8 @@ static int irqc_probe(struct platform_device *pdev) + irq_chip->irq_set_wake = irqc_irq_set_wake; + irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND; + +- p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, +- p->number_of_irqs, 0, ++ p->irq_domain = irq_domain_add_linear(pdev->dev.of_node, ++ p->number_of_irqs, + &irqc_irq_domain_ops, p); + if (!p->irq_domain) { + ret = -ENXIO; +-- +2.6.2 + diff --git a/patches.renesas/0142-irqchip-renesas-irqc-Make-use-of-irq_find_mapping.patch b/patches.renesas/0142-irqchip-renesas-irqc-Make-use-of-irq_find_mapping.patch new file mode 100644 index 00000000000000..b29265d87d1f9d --- /dev/null +++ b/patches.renesas/0142-irqchip-renesas-irqc-Make-use-of-irq_find_mapping.patch @@ -0,0 +1,75 @@ +From 7cefd8faf336b0299f069bba54efb675b8f879c3 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm+renesas@opensource.se> +Date: Mon, 20 Jul 2015 19:06:35 +0900 +Subject: [PATCH 142/326] irqchip/renesas-irqc: Make use of irq_find_mapping() + +Instead of locally caching the virq as domain_irq simply rely on the +IRQ domain code and irq_find_mapping(). This reduces the delta +between the IRQC driver and the generic chip implementation. + +Signed-off-by: Magnus Damm <damm+renesas@opensource.se> +Cc: jason@lakedaemon.net +Cc: geert+renesas@glider.be +Cc: horms@verge.net.au +Cc: Magnus Damm <magnus.damm@gmail.com> +Link: http://lkml.kernel.org/r/20150720100635.2552.20906.sendpatchset@little-apple +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +(cherry picked from commit e10fc03c4f89e5191f0ad2a3885d476f498bf131) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/irqchip/irq-renesas-irqc.c | 11 ++++------- + 1 file changed, 4 insertions(+), 7 deletions(-) + +diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c +index 7f750920ed90..2aa3add711a6 100644 +--- a/drivers/irqchip/irq-renesas-irqc.c ++++ b/drivers/irqchip/irq-renesas-irqc.c +@@ -53,7 +53,6 @@ + struct irqc_irq { + int hw_irq; + int requested_irq; +- int domain_irq; + struct irqc_priv *p; + }; + +@@ -70,8 +69,8 @@ struct irqc_priv { + + static void irqc_dbg(struct irqc_irq *i, char *str) + { +- dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", +- str, i->requested_irq, i->hw_irq, i->domain_irq); ++ dev_dbg(&i->p->pdev->dev, "%s (%d:%d)\n", ++ str, i->requested_irq, i->hw_irq); + } + + static void irqc_irq_enable(struct irq_data *d) +@@ -145,7 +144,7 @@ static irqreturn_t irqc_irq_handler(int irq, void *dev_id) + if (ioread32(p->iomem + DETECT_STATUS) & bit) { + iowrite32(bit, p->iomem + DETECT_STATUS); + irqc_dbg(i, "demux2"); +- generic_handle_irq(i->domain_irq); ++ generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq)); + return IRQ_HANDLED; + } + return IRQ_NONE; +@@ -156,9 +155,6 @@ static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq, + { + struct irqc_priv *p = h->host_data; + +- p->irq[hw].domain_irq = virq; +- p->irq[hw].hw_irq = hw; +- + irqc_dbg(&p->irq[hw], "map"); + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); +@@ -214,6 +210,7 @@ static int irqc_probe(struct platform_device *pdev) + break; + + p->irq[k].p = p; ++ p->irq[k].hw_irq = k; + p->irq[k].requested_irq = irq->start; + } + +-- +2.6.2 + diff --git a/patches.renesas/0143-ARM-shmobile-R-Mobile-Move-to_rmobile_pd-from-header.patch b/patches.renesas/0143-ARM-shmobile-R-Mobile-Move-to_rmobile_pd-from-header.patch new file mode 100644 index 00000000000000..23d25e81c0c1bc --- /dev/null +++ b/patches.renesas/0143-ARM-shmobile-R-Mobile-Move-to_rmobile_pd-from-header.patch @@ -0,0 +1,54 @@ +From ebd8253705e7a12c307b317f045801f85a590f49 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 4 Jun 2015 20:22:25 +0200 +Subject: [PATCH 143/326] ARM: shmobile: R-Mobile: Move to_rmobile_pd from + header to source file + +to_rmobile_pd() is only used inside pm-rmobile.c + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 23758258220c2fcdabb30a3c6fe0a3ce6c705550) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/pm-rmobile.c | 6 ++++++ + arch/arm/mach-shmobile/pm-rmobile.h | 6 ------ + 2 files changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c +index 95018209ff0b..94161c9b1878 100644 +--- a/arch/arm/mach-shmobile/pm-rmobile.c ++++ b/arch/arm/mach-shmobile/pm-rmobile.c +@@ -34,6 +34,12 @@ + #define PSTR_RETRIES 100 + #define PSTR_DELAY_US 10 + ++static inline ++struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d) ++{ ++ return container_of(d, struct rmobile_pm_domain, genpd); ++} ++ + static int rmobile_pd_power_down(struct generic_pm_domain *genpd) + { + struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd); +diff --git a/arch/arm/mach-shmobile/pm-rmobile.h b/arch/arm/mach-shmobile/pm-rmobile.h +index 53219786f539..3992b619c127 100644 +--- a/arch/arm/mach-shmobile/pm-rmobile.h ++++ b/arch/arm/mach-shmobile/pm-rmobile.h +@@ -26,12 +26,6 @@ struct rmobile_pm_domain { + bool no_debug; + }; + +-static inline +-struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d) +-{ +- return container_of(d, struct rmobile_pm_domain, genpd); +-} +- + struct pm_domain_device { + const char *domain_name; + struct platform_device *pdev; +-- +2.6.2 + diff --git a/patches.renesas/0144-ARM-shmobile-R-Mobile-Use-BIT-macro-instead-of-open-.patch b/patches.renesas/0144-ARM-shmobile-R-Mobile-Use-BIT-macro-instead-of-open-.patch new file mode 100644 index 00000000000000..81d9b149d06423 --- /dev/null +++ b/patches.renesas/0144-ARM-shmobile-R-Mobile-Use-BIT-macro-instead-of-open-.patch @@ -0,0 +1,39 @@ +From 6773cf21d5f71b270b5aeb53821d6d6f73655e31 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 4 Jun 2015 20:22:26 +0200 +Subject: [PATCH 144/326] ARM: shmobile: R-Mobile: Use BIT() macro instead of + open coding + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 23e95fc2964de5a38c1c76109188756420268858) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/pm-rmobile.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c +index 94161c9b1878..b9b494f5ca99 100644 +--- a/arch/arm/mach-shmobile/pm-rmobile.c ++++ b/arch/arm/mach-shmobile/pm-rmobile.c +@@ -48,7 +48,7 @@ static int rmobile_pd_power_down(struct generic_pm_domain *genpd) + if (rmobile_pd->bit_shift == ~0) + return -EBUSY; + +- mask = 1 << rmobile_pd->bit_shift; ++ mask = BIT(rmobile_pd->bit_shift); + if (rmobile_pd->suspend) { + int ret = rmobile_pd->suspend(); + +@@ -85,7 +85,7 @@ static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd, + if (rmobile_pd->bit_shift == ~0) + return 0; + +- mask = 1 << rmobile_pd->bit_shift; ++ mask = BIT(rmobile_pd->bit_shift); + if (__raw_readl(rmobile_pd->base + PSTR) & mask) + goto out; + +-- +2.6.2 + diff --git a/patches.renesas/0145-ARM-shmobile-r8a7779-Remove-GENPD_FLAG_PM_CLK-flag.patch b/patches.renesas/0145-ARM-shmobile-r8a7779-Remove-GENPD_FLAG_PM_CLK-flag.patch new file mode 100644 index 00000000000000..3be1507ba00be9 --- /dev/null +++ b/patches.renesas/0145-ARM-shmobile-r8a7779-Remove-GENPD_FLAG_PM_CLK-flag.patch @@ -0,0 +1,38 @@ +From 0b1581f545b45cc0ac968f4db04ecc83662d2a1f Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 4 Jun 2015 20:22:33 +0200 +Subject: [PATCH 145/326] ARM: shmobile: r8a7779: Remove GENPD_FLAG_PM_CLK flag + +The R-Car SYSC PM Domain only manages power domains for the main CPUs +and for coprocessors. It does not fill in the genpd .{at,de}tach_dev() +callbacks, and no power management clocks are registered for devices. +Hence pm_clk_{suspend,resume}() are no-ops, and setting of the +GENPD_FLAG_PM_CLK flag can be removed. + +Originally the clock handling was copied from the R-Mobile PM Domain +code, which does manage a clock domain, in addition to device power +domains. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 564ec128320b3a69e7be6bed938be5b78e5aac95) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/pm-r8a7779.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c +index 44a74c4c5a01..d5f258e4d890 100644 +--- a/arch/arm/mach-shmobile/pm-r8a7779.c ++++ b/arch/arm/mach-shmobile/pm-r8a7779.c +@@ -83,7 +83,6 @@ static void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd) + { + struct generic_pm_domain *genpd = &r8a7779_pd->genpd; + +- genpd->flags = GENPD_FLAG_PM_CLK; + pm_genpd_init(genpd, NULL, false); + genpd->dev_ops.active_wakeup = pd_active_wakeup; + genpd->power_off = pd_power_down; +-- +2.6.2 + diff --git a/patches.renesas/0146-ARM-shmobile-Remove-legacy-board-code-for-KZM-A9-GT.patch b/patches.renesas/0146-ARM-shmobile-Remove-legacy-board-code-for-KZM-A9-GT.patch new file mode 100644 index 00000000000000..3f4472339bdab9 --- /dev/null +++ b/patches.renesas/0146-ARM-shmobile-Remove-legacy-board-code-for-KZM-A9-GT.patch @@ -0,0 +1,1775 @@ +From 3902319f7130e4433017c608aedc70bc74370928 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:31:17 +0200 +Subject: [PATCH 146/326] ARM: shmobile: Remove legacy board code for KZM-A9-GT + +The KZM-A9-GT board is sufficiently supported by DT-based and board-less +SH-Mobile AG5 (sh73a0) multiplatform kernels. Hence remove the legacy +board code to reduce maintenance effort. + +Lacking areas are: + - USB (it does't work in legacy, neither), + - LCDC (the LCDC is wired to the legacy INTC, which is not planned to + be supported with DT). + - DMAC/IPMMU (no DT bindings are planned). + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 30f8925a57d8ad4990fca14bcf454abd91228afd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 8 - + arch/arm/mach-shmobile/Makefile | 1 - + arch/arm/mach-shmobile/Makefile.boot | 1 - + arch/arm/mach-shmobile/board-kzm9g.c | 916 --------------------- + arch/arm/mach-shmobile/include/mach/head-kzm9g.txt | 410 --------- + arch/arm/mach-shmobile/include/mach/zboot.h | 5 - + arch/arm/mach-shmobile/intc-sh73a0.c | 337 -------- + 7 files changed, 1678 deletions(-) + delete mode 100644 arch/arm/mach-shmobile/board-kzm9g.c + delete mode 100644 arch/arm/mach-shmobile/include/mach/head-kzm9g.txt + delete mode 100644 arch/arm/mach-shmobile/intc-sh73a0.c + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 34eac88a9889..b85b34c1d6e0 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -173,14 +173,6 @@ config MACH_MARZEN + select REGULATOR_FIXED_VOLTAGE if REGULATOR + select USE_OF + +-config MACH_KZM9G +- bool "KZM-A9-GT board" +- depends on ARCH_SH73A0 +- select ARCH_REQUIRE_GPIOLIB +- select REGULATOR_FIXED_VOLTAGE if REGULATOR +- select SND_SOC_AK4642 if SND_SIMPLE_CARD +- select USE_OF +- + comment "Renesas ARM SoCs System Configuration" + + config CPU_HAS_INTEVT +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 89e463de4479..a4d7f5734e91 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -58,7 +58,6 @@ obj-$(CONFIG_MACH_BOCKW) += board-bockw.o + obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o + obj-$(CONFIG_MACH_MARZEN) += board-marzen.o + obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o +-obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o intc-sh73a0.o + endif + + # Framework support +diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot +index e1ef19cef89c..2269b1c3c30b 100644 +--- a/arch/arm/mach-shmobile/Makefile.boot ++++ b/arch/arm/mach-shmobile/Makefile.boot +@@ -3,7 +3,6 @@ loadaddr-y := + loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 + loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 + loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 +-loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 + loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 + + __ZRELADDR := $(sort $(loadaddr-y)) +diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c +deleted file mode 100644 +index 260d8319fd82..000000000000 +--- a/arch/arm/mach-shmobile/board-kzm9g.c ++++ /dev/null +@@ -1,916 +0,0 @@ +-/* +- * KZM-A9-GT board support +- * +- * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include <linux/delay.h> +-#include <linux/gpio.h> +-#include <linux/gpio_keys.h> +-#include <linux/io.h> +-#include <linux/irq.h> +-#include <linux/i2c.h> +-#include <linux/i2c/pcf857x.h> +-#include <linux/input.h> +-#include <linux/irqchip/arm-gic.h> +-#include <linux/mmc/host.h> +-#include <linux/mmc/sh_mmcif.h> +-#include <linux/mmc/sh_mobile_sdhi.h> +-#include <linux/mfd/as3711.h> +-#include <linux/mfd/tmio.h> +-#include <linux/pinctrl/machine.h> +-#include <linux/pinctrl/pinconf-generic.h> +-#include <linux/platform_device.h> +-#include <linux/reboot.h> +-#include <linux/regulator/fixed.h> +-#include <linux/regulator/machine.h> +-#include <linux/smsc911x.h> +-#include <linux/usb/r8a66597.h> +-#include <linux/usb/renesas_usbhs.h> +-#include <linux/videodev2.h> +- +-#include <sound/sh_fsi.h> +-#include <sound/simple_card.h> +-#include <asm/hardware/cache-l2x0.h> +-#include <asm/mach-types.h> +-#include <asm/mach/arch.h> +-#include <video/sh_mobile_lcdc.h> +- +-#include "common.h" +-#include "intc.h" +-#include "irqs.h" +-#include "sh73a0.h" +- +-/* +- * external GPIO +- */ +-#define GPIO_PCF8575_BASE (310) +-#define GPIO_PCF8575_PORT10 (GPIO_PCF8575_BASE + 8) +-#define GPIO_PCF8575_PORT11 (GPIO_PCF8575_BASE + 9) +-#define GPIO_PCF8575_PORT12 (GPIO_PCF8575_BASE + 10) +-#define GPIO_PCF8575_PORT13 (GPIO_PCF8575_BASE + 11) +-#define GPIO_PCF8575_PORT14 (GPIO_PCF8575_BASE + 12) +-#define GPIO_PCF8575_PORT15 (GPIO_PCF8575_BASE + 13) +-#define GPIO_PCF8575_PORT16 (GPIO_PCF8575_BASE + 14) +- +-/* Dummy supplies, where voltage doesn't matter */ +-static struct regulator_consumer_supply dummy_supplies[] = { +- REGULATOR_SUPPLY("vddvario", "smsc911x.0"), +- REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), +-}; +- +-/* +- * FSI-AK4648 +- * +- * this command is required when playback. +- * +- * # amixer set "LINEOUT Mixer DACL" on +- */ +- +-/* SMSC 9221 */ +-static struct resource smsc9221_resources[] = { +- [0] = { +- .start = 0x10000000, /* CS4 */ +- .end = 0x100000ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = irq_pin(3), /* IRQ3 */ +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct smsc911x_platform_config smsc9221_platdata = { +- .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, +- .phy_interface = PHY_INTERFACE_MODE_MII, +- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, +- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +-}; +- +-static struct platform_device smsc_device = { +- .name = "smsc911x", +- .dev = { +- .platform_data = &smsc9221_platdata, +- }, +- .resource = smsc9221_resources, +- .num_resources = ARRAY_SIZE(smsc9221_resources), +-}; +- +-/* USB external chip */ +-static struct r8a66597_platdata usb_host_data = { +- .on_chip = 0, +- .xtal = R8A66597_PLATDATA_XTAL_48MHZ, +-}; +- +-static struct resource usb_resources[] = { +- [0] = { +- .start = 0x10010000, +- .end = 0x1001ffff - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = irq_pin(1), /* IRQ1 */ +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device usb_host_device = { +- .name = "r8a66597_hcd", +- .dev = { +- .platform_data = &usb_host_data, +- .dma_mask = NULL, +- .coherent_dma_mask = 0xffffffff, +- }, +- .num_resources = ARRAY_SIZE(usb_resources), +- .resource = usb_resources, +-}; +- +-/* USB Func CN17 */ +-struct usbhs_private { +- void __iomem *phy; +- void __iomem *cr2; +- struct renesas_usbhs_platform_info info; +-}; +- +-#define IRQ15 irq_pin(15) +-#define USB_PHY_MODE (1 << 4) +-#define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) +-#define USB_PHY_ON (1 << 1) +-#define USB_PHY_OFF (1 << 0) +-#define USB_PHY_INT_CLR (USB_PHY_ON | USB_PHY_OFF) +- +-#define usbhs_get_priv(pdev) \ +- container_of(renesas_usbhs_get_info(pdev), struct usbhs_private, info) +- +-static int usbhs_get_vbus(struct platform_device *pdev) +-{ +- struct usbhs_private *priv = usbhs_get_priv(pdev); +- +- return !((1 << 7) & __raw_readw(priv->cr2)); +-} +- +-static int usbhs_phy_reset(struct platform_device *pdev) +-{ +- struct usbhs_private *priv = usbhs_get_priv(pdev); +- +- /* init phy */ +- __raw_writew(0x8a0a, priv->cr2); +- +- return 0; +-} +- +-static int usbhs_get_id(struct platform_device *pdev) +-{ +- return USBHS_GADGET; +-} +- +-static irqreturn_t usbhs_interrupt(int irq, void *data) +-{ +- struct platform_device *pdev = data; +- struct usbhs_private *priv = usbhs_get_priv(pdev); +- +- renesas_usbhs_call_notify_hotplug(pdev); +- +- /* clear status */ +- __raw_writew(__raw_readw(priv->phy) | USB_PHY_INT_CLR, priv->phy); +- +- return IRQ_HANDLED; +-} +- +-static int usbhs_hardware_init(struct platform_device *pdev) +-{ +- struct usbhs_private *priv = usbhs_get_priv(pdev); +- int ret; +- +- /* clear interrupt status */ +- __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->phy); +- +- ret = request_irq(IRQ15, usbhs_interrupt, IRQF_TRIGGER_HIGH, +- dev_name(&pdev->dev), pdev); +- if (ret) { +- dev_err(&pdev->dev, "request_irq err\n"); +- return ret; +- } +- +- /* enable USB phy interrupt */ +- __raw_writew(USB_PHY_MODE | USB_PHY_INT_EN, priv->phy); +- +- return 0; +-} +- +-static int usbhs_hardware_exit(struct platform_device *pdev) +-{ +- struct usbhs_private *priv = usbhs_get_priv(pdev); +- +- /* clear interrupt status */ +- __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->phy); +- +- free_irq(IRQ15, pdev); +- +- return 0; +-} +- +-static u32 usbhs_pipe_cfg[] = { +- USB_ENDPOINT_XFER_CONTROL, +- USB_ENDPOINT_XFER_ISOC, +- USB_ENDPOINT_XFER_ISOC, +- USB_ENDPOINT_XFER_BULK, +- USB_ENDPOINT_XFER_BULK, +- USB_ENDPOINT_XFER_BULK, +- USB_ENDPOINT_XFER_INT, +- USB_ENDPOINT_XFER_INT, +- USB_ENDPOINT_XFER_INT, +- USB_ENDPOINT_XFER_BULK, +- USB_ENDPOINT_XFER_BULK, +- USB_ENDPOINT_XFER_BULK, +- USB_ENDPOINT_XFER_BULK, +- USB_ENDPOINT_XFER_BULK, +- USB_ENDPOINT_XFER_BULK, +- USB_ENDPOINT_XFER_BULK, +-}; +- +-static struct usbhs_private usbhs_private = { +- .phy = IOMEM(0xe60781e0), /* USBPHYINT */ +- .cr2 = IOMEM(0xe605810c), /* USBCR2 */ +- .info = { +- .platform_callback = { +- .hardware_init = usbhs_hardware_init, +- .hardware_exit = usbhs_hardware_exit, +- .get_id = usbhs_get_id, +- .phy_reset = usbhs_phy_reset, +- .get_vbus = usbhs_get_vbus, +- }, +- .driver_param = { +- .buswait_bwait = 4, +- .has_otg = 1, +- .pipe_type = usbhs_pipe_cfg, +- .pipe_size = ARRAY_SIZE(usbhs_pipe_cfg), +- }, +- }, +-}; +- +-static struct resource usbhs_resources[] = { +- [0] = { +- .start = 0xE6890000, +- .end = 0xE68900e6 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(62), +- .end = gic_spi(62), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device usbhs_device = { +- .name = "renesas_usbhs", +- .id = -1, +- .dev = { +- .dma_mask = NULL, +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &usbhs_private.info, +- }, +- .num_resources = ARRAY_SIZE(usbhs_resources), +- .resource = usbhs_resources, +-}; +- +-/* LCDC */ +-static struct fb_videomode kzm_lcdc_mode = { +- .name = "WVGA Panel", +- .xres = 800, +- .yres = 480, +- .left_margin = 220, +- .right_margin = 110, +- .hsync_len = 70, +- .upper_margin = 20, +- .lower_margin = 5, +- .vsync_len = 5, +- .sync = 0, +-}; +- +-static struct sh_mobile_lcdc_info lcdc_info = { +- .clock_source = LCDC_CLK_BUS, +- .ch[0] = { +- .chan = LCDC_CHAN_MAINLCD, +- .fourcc = V4L2_PIX_FMT_RGB565, +- .interface_type = RGB24, +- .lcd_modes = &kzm_lcdc_mode, +- .num_modes = 1, +- .clock_divider = 5, +- .flags = 0, +- .panel_cfg = { +- .width = 152, +- .height = 91, +- }, +- } +-}; +- +-static struct resource lcdc_resources[] = { +- [0] = { +- .name = "LCDC", +- .start = 0xfe940000, +- .end = 0xfe943fff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = intcs_evt2irq(0x580), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device lcdc_device = { +- .name = "sh_mobile_lcdc_fb", +- .num_resources = ARRAY_SIZE(lcdc_resources), +- .resource = lcdc_resources, +- .dev = { +- .platform_data = &lcdc_info, +- .coherent_dma_mask = DMA_BIT_MASK(32), +- }, +-}; +- +-/* Fixed 1.8V regulator to be used by MMCIF */ +-static struct regulator_consumer_supply fixed1v8_power_consumers[] = +-{ +- REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), +- REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"), +-}; +- +-/* MMCIF */ +-static struct resource sh_mmcif_resources[] = { +- [0] = { +- .name = "MMCIF", +- .start = 0xe6bd0000, +- .end = 0xe6bd00ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(140), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .start = gic_spi(141), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct sh_mmcif_plat_data sh_mmcif_platdata = { +- .ocr = MMC_VDD_165_195, +- .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, +- .ccs_unsupported = true, +- .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, +- .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, +-}; +- +-static struct platform_device mmc_device = { +- .name = "sh_mmcif", +- .dev = { +- .dma_mask = NULL, +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &sh_mmcif_platdata, +- }, +- .num_resources = ARRAY_SIZE(sh_mmcif_resources), +- .resource = sh_mmcif_resources, +-}; +- +-/* Fixed 3.3V regulators to be used by SDHI0 */ +-static struct regulator_consumer_supply vcc_sdhi0_consumers[] = +-{ +- REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), +-}; +- +-static struct regulator_init_data vcc_sdhi0_init_data = { +- .constraints = { +- .valid_ops_mask = REGULATOR_CHANGE_STATUS, +- }, +- .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers), +- .consumer_supplies = vcc_sdhi0_consumers, +-}; +- +-static struct fixed_voltage_config vcc_sdhi0_info = { +- .supply_name = "SDHI0 Vcc", +- .microvolts = 3300000, +- .gpio = 15, +- .enable_high = 1, +- .init_data = &vcc_sdhi0_init_data, +-}; +- +-static struct platform_device vcc_sdhi0 = { +- .name = "reg-fixed-voltage", +- .id = 0, +- .dev = { +- .platform_data = &vcc_sdhi0_info, +- }, +-}; +- +-/* Fixed 3.3V regulators to be used by SDHI2 */ +-static struct regulator_consumer_supply vcc_sdhi2_consumers[] = +-{ +- REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"), +-}; +- +-static struct regulator_init_data vcc_sdhi2_init_data = { +- .constraints = { +- .valid_ops_mask = REGULATOR_CHANGE_STATUS, +- }, +- .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi2_consumers), +- .consumer_supplies = vcc_sdhi2_consumers, +-}; +- +-static struct fixed_voltage_config vcc_sdhi2_info = { +- .supply_name = "SDHI2 Vcc", +- .microvolts = 3300000, +- .gpio = 14, +- .enable_high = 1, +- .init_data = &vcc_sdhi2_init_data, +-}; +- +-static struct platform_device vcc_sdhi2 = { +- .name = "reg-fixed-voltage", +- .id = 1, +- .dev = { +- .platform_data = &vcc_sdhi2_info, +- }, +-}; +- +-/* SDHI */ +-static struct tmio_mmc_data sdhi0_info = { +- .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX, +- .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX, +- .flags = TMIO_MMC_HAS_IDLE_WAIT, +- .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | +- MMC_CAP_POWER_OFF_CARD, +-}; +- +-static struct resource sdhi0_resources[] = { +- [0] = { +- .name = "SDHI0", +- .start = 0xee100000, +- .end = 0xee1000ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, +- .start = gic_spi(83), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .name = SH_MOBILE_SDHI_IRQ_SDCARD, +- .start = gic_spi(84), +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .name = SH_MOBILE_SDHI_IRQ_SDIO, +- .start = gic_spi(85), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sdhi0_device = { +- .name = "sh_mobile_sdhi", +- .num_resources = ARRAY_SIZE(sdhi0_resources), +- .resource = sdhi0_resources, +- .dev = { +- .platform_data = &sdhi0_info, +- }, +-}; +- +-/* Micro SD */ +-static struct tmio_mmc_data sdhi2_info = { +- .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI2_TX, +- .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI2_RX, +- .flags = TMIO_MMC_HAS_IDLE_WAIT | +- TMIO_MMC_USE_GPIO_CD | +- TMIO_MMC_WRPROTECT_DISABLE, +- .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_POWER_OFF_CARD, +- .cd_gpio = 13, +-}; +- +-static struct resource sdhi2_resources[] = { +- [0] = { +- .name = "SDHI2", +- .start = 0xee140000, +- .end = 0xee1400ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, +- .start = gic_spi(103), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .name = SH_MOBILE_SDHI_IRQ_SDCARD, +- .start = gic_spi(104), +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .name = SH_MOBILE_SDHI_IRQ_SDIO, +- .start = gic_spi(105), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sdhi2_device = { +- .name = "sh_mobile_sdhi", +- .id = 2, +- .num_resources = ARRAY_SIZE(sdhi2_resources), +- .resource = sdhi2_resources, +- .dev = { +- .platform_data = &sdhi2_info, +- }, +-}; +- +-/* KEY */ +-#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 } +- +-static struct gpio_keys_button gpio_buttons[] = { +- GPIO_KEY(KEY_BACK, GPIO_PCF8575_PORT10, "SW3"), +- GPIO_KEY(KEY_RIGHT, GPIO_PCF8575_PORT11, "SW2-R"), +- GPIO_KEY(KEY_LEFT, GPIO_PCF8575_PORT12, "SW2-L"), +- GPIO_KEY(KEY_ENTER, GPIO_PCF8575_PORT13, "SW2-P"), +- GPIO_KEY(KEY_UP, GPIO_PCF8575_PORT14, "SW2-U"), +- GPIO_KEY(KEY_DOWN, GPIO_PCF8575_PORT15, "SW2-D"), +- GPIO_KEY(KEY_HOME, GPIO_PCF8575_PORT16, "SW1"), +-}; +- +-static struct gpio_keys_platform_data gpio_key_info = { +- .buttons = gpio_buttons, +- .nbuttons = ARRAY_SIZE(gpio_buttons), +-}; +- +-static struct platform_device gpio_keys_device = { +- .name = "gpio-keys", +- .dev = { +- .platform_data = &gpio_key_info, +- }, +-}; +- +-/* FSI-AK4648 */ +-static struct sh_fsi_platform_info fsi_info = { +- .port_a = { +- .tx_id = SHDMA_SLAVE_FSI2A_TX, +- }, +-}; +- +-static struct resource fsi_resources[] = { +- [0] = { +- .name = "FSI", +- .start = 0xEC230000, +- .end = 0xEC230400 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(146), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device fsi_device = { +- .name = "sh_fsi2", +- .id = -1, +- .num_resources = ARRAY_SIZE(fsi_resources), +- .resource = fsi_resources, +- .dev = { +- .platform_data = &fsi_info, +- }, +-}; +- +-static struct asoc_simple_card_info fsi2_ak4648_info = { +- .name = "AK4648", +- .card = "FSI2A-AK4648", +- .codec = "ak4642-codec.0-0012", +- .platform = "sh_fsi2", +- .daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM, +- .cpu_dai = { +- .name = "fsia-dai", +- }, +- .codec_dai = { +- .name = "ak4642-hifi", +- .sysclk = 11289600, +- }, +-}; +- +-static struct platform_device fsi_ak4648_device = { +- .name = "asoc-simple-card", +- .dev = { +- .platform_data = &fsi2_ak4648_info, +- .coherent_dma_mask = DMA_BIT_MASK(32), +- .dma_mask = &fsi_ak4648_device.dev.coherent_dma_mask, +- }, +-}; +- +-/* I2C */ +- +-/* StepDown1 is used to supply 1.315V to the CPU */ +-static struct regulator_init_data as3711_sd1 = { +- .constraints = { +- .name = "1.315V CPU", +- .boot_on = 1, +- .always_on = 1, +- .min_uV = 1315000, +- .max_uV = 1335000, +- }, +-}; +- +-/* StepDown2 is used to supply 1.8V to the CPU and to the board */ +-static struct regulator_init_data as3711_sd2 = { +- .constraints = { +- .name = "1.8V", +- .boot_on = 1, +- .always_on = 1, +- .min_uV = 1800000, +- .max_uV = 1800000, +- }, +-}; +- +-/* +- * StepDown3 is switched in parallel with StepDown2, seems to be off, +- * according to read-back pre-set register values +- */ +- +-/* StepDown4 is used to supply 1.215V to the CPU and to the board */ +-static struct regulator_init_data as3711_sd4 = { +- .constraints = { +- .name = "1.215V", +- .boot_on = 1, +- .always_on = 1, +- .min_uV = 1215000, +- .max_uV = 1235000, +- }, +-}; +- +-/* LDO1 is unused and unconnected */ +- +-/* LDO2 is used to supply 2.8V to the CPU */ +-static struct regulator_init_data as3711_ldo2 = { +- .constraints = { +- .name = "2.8V CPU", +- .boot_on = 1, +- .always_on = 1, +- .min_uV = 2800000, +- .max_uV = 2800000, +- }, +-}; +- +-/* LDO3 is used to supply 3.0V to the CPU */ +-static struct regulator_init_data as3711_ldo3 = { +- .constraints = { +- .name = "3.0V CPU", +- .boot_on = 1, +- .always_on = 1, +- .min_uV = 3000000, +- .max_uV = 3000000, +- }, +-}; +- +-/* LDO4 is used to supply 2.8V to the board */ +-static struct regulator_init_data as3711_ldo4 = { +- .constraints = { +- .name = "2.8V", +- .boot_on = 1, +- .always_on = 1, +- .min_uV = 2800000, +- .max_uV = 2800000, +- }, +-}; +- +-/* LDO5 is switched parallel to LDO4, also set to 2.8V */ +-static struct regulator_init_data as3711_ldo5 = { +- .constraints = { +- .name = "2.8V #2", +- .boot_on = 1, +- .always_on = 1, +- .min_uV = 2800000, +- .max_uV = 2800000, +- }, +-}; +- +-/* LDO6 is unused and unconnected */ +- +-/* LDO7 is used to supply 1.15V to the CPU */ +-static struct regulator_init_data as3711_ldo7 = { +- .constraints = { +- .name = "1.15V CPU", +- .boot_on = 1, +- .always_on = 1, +- .min_uV = 1150000, +- .max_uV = 1150000, +- }, +-}; +- +-/* LDO8 is switched parallel to LDO7, also set to 1.15V */ +-static struct regulator_init_data as3711_ldo8 = { +- .constraints = { +- .name = "1.15V CPU #2", +- .boot_on = 1, +- .always_on = 1, +- .min_uV = 1150000, +- .max_uV = 1150000, +- }, +-}; +- +-static struct as3711_platform_data as3711_pdata = { +- .regulator = { +- .init_data = { +- [AS3711_REGULATOR_SD_1] = &as3711_sd1, +- [AS3711_REGULATOR_SD_2] = &as3711_sd2, +- [AS3711_REGULATOR_SD_4] = &as3711_sd4, +- [AS3711_REGULATOR_LDO_2] = &as3711_ldo2, +- [AS3711_REGULATOR_LDO_3] = &as3711_ldo3, +- [AS3711_REGULATOR_LDO_4] = &as3711_ldo4, +- [AS3711_REGULATOR_LDO_5] = &as3711_ldo5, +- [AS3711_REGULATOR_LDO_7] = &as3711_ldo7, +- [AS3711_REGULATOR_LDO_8] = &as3711_ldo8, +- }, +- }, +- .backlight = { +- .su2_fb = "sh_mobile_lcdc_fb.0", +- .su2_max_uA = 36000, +- .su2_feedback = AS3711_SU2_CURR_AUTO, +- .su2_fbprot = AS3711_SU2_GPIO4, +- .su2_auto_curr1 = true, +- .su2_auto_curr2 = true, +- .su2_auto_curr3 = true, +- }, +-}; +- +-static struct pcf857x_platform_data pcf8575_pdata = { +- .gpio_base = GPIO_PCF8575_BASE, +-}; +- +-static struct i2c_board_info i2c0_devices[] = { +- { +- I2C_BOARD_INFO("ak4648", 0x12), +- }, +- { +- I2C_BOARD_INFO("r2025sd", 0x32), +- }, +- { +- I2C_BOARD_INFO("ak8975", 0x0c), +- .irq = irq_pin(28), /* IRQ28 */ +- }, +- { +- I2C_BOARD_INFO("adxl34x", 0x1d), +- .irq = irq_pin(26), /* IRQ26 */ +- }, +- { +- I2C_BOARD_INFO("as3711", 0x40), +- .irq = intcs_evt2irq(0x3300), /* IRQ24 */ +- .platform_data = &as3711_pdata, +- }, +-}; +- +-static struct i2c_board_info i2c1_devices[] = { +- { +- I2C_BOARD_INFO("st1232-ts", 0x55), +- .irq = irq_pin(8), /* IRQ8 */ +- }, +-}; +- +-static struct i2c_board_info i2c3_devices[] = { +- { +- I2C_BOARD_INFO("pcf8575", 0x20), +- .irq = irq_pin(19), /* IRQ19 */ +- .platform_data = &pcf8575_pdata, +- }, +-}; +- +-static struct platform_device *kzm_devices[] __initdata = { +- &smsc_device, +- &usb_host_device, +- &usbhs_device, +- &lcdc_device, +- &mmc_device, +- &vcc_sdhi0, +- &vcc_sdhi2, +- &sdhi0_device, +- &sdhi2_device, +- &gpio_keys_device, +- &fsi_device, +- &fsi_ak4648_device, +-}; +- +-static unsigned long pin_pullup_conf[] = { +- PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), +-}; +- +-static const struct pinctrl_map kzm_pinctrl_map[] = { +- /* FSIA (AK4648) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", +- "fsia_mclk_in", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", +- "fsia_sclk_in", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", +- "fsia_data_in", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", +- "fsia_data_out", "fsia"), +- /* I2C3 */ +- PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", +- "i2c3_1", "i2c3"), +- /* LCD */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", +- "lcd_data24", "lcd"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", +- "lcd_sync", "lcd"), +- /* MMCIF */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", +- "mmc0_data8_0", "mmc0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", +- "mmc0_ctrl_0", "mmc0"), +- PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", +- "PORT279", pin_pullup_conf), +- PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", +- "mmc0_data8_0", pin_pullup_conf), +- /* SCIFA4 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", +- "scifa4_data", "scifa4"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", +- "scifa4_ctrl", "scifa4"), +- /* SDHI0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "sdhi0_data4", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "sdhi0_ctrl", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "sdhi0_cd", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", +- "sdhi0_wp", "sdhi0"), +- /* SDHI2 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", +- "sdhi2_data4", "sdhi2"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", +- "sdhi2_ctrl", "sdhi2"), +- /* SMSC */ +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", +- "bsc_cs4", "bsc"), +- /* USB */ +- PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0", +- "usb_vbus", "usb"), +-}; +- +-static void __init kzm_init(void) +-{ +- regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers, +- ARRAY_SIZE(fixed1v8_power_consumers), 1800000); +- regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies)); +- +- pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map)); +- +- sh73a0_pinmux_init(); +- +- /* SMSC */ +- gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */ +- +- /* LCDC */ +- gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */ +- gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */ +- +- /* Touchscreen */ +- gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */ +- +-#ifdef CONFIG_CACHE_L2X0 +- /* Shared attribute override enable, 64K*8way */ +- l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); +-#endif +- +- i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); +- i2c_register_board_info(1, i2c1_devices, ARRAY_SIZE(i2c1_devices)); +- i2c_register_board_info(3, i2c3_devices, ARRAY_SIZE(i2c3_devices)); +- +- sh73a0_add_standard_devices(); +- platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices)); +- +- sh73a0_pm_init(); +-} +- +-static void kzm9g_restart(enum reboot_mode mode, const char *cmd) +-{ +-#define RESCNT2 IOMEM(0xe6188020) +- /* Do soft power on reset */ +- writel((1 << 31), RESCNT2); +-} +- +-static const char *kzm9g_boards_compat_dt[] __initdata = { +- "renesas,kzm9g", +- NULL, +-}; +- +-DT_MACHINE_START(KZM9G_DT, "kzm9g") +- .smp = smp_ops(sh73a0_smp_ops), +- .map_io = sh73a0_map_io, +- .init_early = sh73a0_add_early_devices, +- .init_irq = sh73a0_init_irq, +- .init_machine = kzm_init, +- .init_late = shmobile_init_late, +- .init_time = sh73a0_earlytimer_init, +- .restart = kzm9g_restart, +- .dt_compat = kzm9g_boards_compat_dt, +-MACHINE_END +diff --git a/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt b/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt +deleted file mode 100644 +index 9531f46a822a..000000000000 +--- a/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt ++++ /dev/null +@@ -1,410 +0,0 @@ +-LIST "KZM9G low-level initialization routine." +-LIST "Adapted from u-boot KZM9G support code." +- +-LIST "Copyright (C) 2013 Ulrich Hecht" +- +-LIST "This program is free software; you can redistribute it and/or modify" +-LIST "it under the terms of the GNU General Public License version 2 as" +-LIST "published by the Free Software Foundation." +- +-LIST "This program is distributed in the hope that it will be useful," +-LIST "but WITHOUT ANY WARRANTY; without even the implied warranty of" +-LIST "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the" +-LIST "GNU General Public License for more details." +- +- +-LIST "Register definitions:" +- +-LIST "Secure control register" +-#define LIFEC_SEC_SRC (0xE6110008) +- +-LIST "RWDT" +-#define RWDT_BASE (0xE6020000) +-#define RWTCSRA0 (RWDT_BASE + 0x04) +- +-LIST "HPB Semaphore Control Registers" +-#define HPBSCR_BASE (0xE6000000) +-#define HPBCTRL6 (HPBSCR_BASE + 0x1030) +- +-#define SBSC1_BASE (0xFE400000) +-#define SDCR0A (SBSC1_BASE + 0x0008) +-#define SDCR1A (SBSC1_BASE + 0x000C) +-#define SDPCRA (SBSC1_BASE + 0x0010) +-#define SDCR0SA (SBSC1_BASE + 0x0018) +-#define SDCR1SA (SBSC1_BASE + 0x001C) +-#define RTCSRA (SBSC1_BASE + 0x0020) +-#define RTCORA (SBSC1_BASE + 0x0028) +-#define RTCORHA (SBSC1_BASE + 0x002C) +-#define SDWCRC0A (SBSC1_BASE + 0x0040) +-#define SDWCRC1A (SBSC1_BASE + 0x0044) +-#define SDWCR00A (SBSC1_BASE + 0x0048) +-#define SDWCR01A (SBSC1_BASE + 0x004C) +-#define SDWCR10A (SBSC1_BASE + 0x0050) +-#define SDWCR11A (SBSC1_BASE + 0x0054) +-#define SDWCR2A (SBSC1_BASE + 0x0060) +-#define SDWCRC2A (SBSC1_BASE + 0x0064) +-#define ZQCCRA (SBSC1_BASE + 0x0068) +-#define SDMRACR0A (SBSC1_BASE + 0x0084) +-#define SDMRTMPCRA (SBSC1_BASE + 0x008C) +-#define SDMRTMPMSKA (SBSC1_BASE + 0x0094) +-#define SDGENCNTA (SBSC1_BASE + 0x009C) +-#define SDDRVCR0A (SBSC1_BASE + 0x00B4) +-#define DLLCNT0A (SBSC1_BASE + 0x0354) +- +-#define SDMRA1 (0xFE500000) +-#define SDMRA2 (0xFE5C0000) +-#define SDMRA3 (0xFE504000) +- +-#define SBSC2_BASE (0xFB400000) +-#define SDCR0B (SBSC2_BASE + 0x0008) +-#define SDCR1B (SBSC2_BASE + 0x000C) +-#define SDPCRB (SBSC2_BASE + 0x0010) +-#define SDCR0SB (SBSC2_BASE + 0x0018) +-#define SDCR1SB (SBSC2_BASE + 0x001C) +-#define RTCSRB (SBSC2_BASE + 0x0020) +-#define RTCORB (SBSC2_BASE + 0x0028) +-#define RTCORHB (SBSC2_BASE + 0x002C) +-#define SDWCRC0B (SBSC2_BASE + 0x0040) +-#define SDWCRC1B (SBSC2_BASE + 0x0044) +-#define SDWCR00B (SBSC2_BASE + 0x0048) +-#define SDWCR01B (SBSC2_BASE + 0x004C) +-#define SDWCR10B (SBSC2_BASE + 0x0050) +-#define SDWCR11B (SBSC2_BASE + 0x0054) +-#define SDPDCR0B (SBSC2_BASE + 0x0058) +-#define SDWCR2B (SBSC2_BASE + 0x0060) +-#define SDWCRC2B (SBSC2_BASE + 0x0064) +-#define ZQCCRB (SBSC2_BASE + 0x0068) +-#define SDMRACR0B (SBSC2_BASE + 0x0084) +-#define SDMRTMPCRB (SBSC2_BASE + 0x008C) +-#define SDMRTMPMSKB (SBSC2_BASE + 0x0094) +-#define SDGENCNTB (SBSC2_BASE + 0x009C) +-#define DPHYCNT0B (SBSC2_BASE + 0x00A0) +-#define DPHYCNT1B (SBSC2_BASE + 0x00A4) +-#define DPHYCNT2B (SBSC2_BASE + 0x00A8) +-#define SDDRVCR0B (SBSC2_BASE + 0x00B4) +-#define DLLCNT0B (SBSC2_BASE + 0x0354) +- +-#define SDMRB1 (0xFB500000) +-#define SDMRB2 (0xFB5C0000) +-#define SDMRB3 (0xFB504000) +- +-#define CPG_BASE (0xE6150000) +-#define FRQCRA (CPG_BASE + 0x0000) +-#define FRQCRB (CPG_BASE + 0x0004) +-#define FRQCRD (CPG_BASE + 0x00E4) +-#define VCLKCR1 (CPG_BASE + 0x0008) +-#define VCLKCR2 (CPG_BASE + 0x000C) +-#define VCLKCR3 (CPG_BASE + 0x001C) +-#define ZBCKCR (CPG_BASE + 0x0010) +-#define FLCKCR (CPG_BASE + 0x0014) +-#define SD0CKCR (CPG_BASE + 0x0074) +-#define SD1CKCR (CPG_BASE + 0x0078) +-#define SD2CKCR (CPG_BASE + 0x007C) +-#define FSIACKCR (CPG_BASE + 0x0018) +-#define SUBCKCR (CPG_BASE + 0x0080) +-#define SPUACKCR (CPG_BASE + 0x0084) +-#define SPUVCKCR (CPG_BASE + 0x0094) +-#define MSUCKCR (CPG_BASE + 0x0088) +-#define HSICKCR (CPG_BASE + 0x008C) +-#define FSIBCKCR (CPG_BASE + 0x0090) +-#define MFCK1CR (CPG_BASE + 0x0098) +-#define MFCK2CR (CPG_BASE + 0x009C) +-#define DSITCKCR (CPG_BASE + 0x0060) +-#define DSI0PCKCR (CPG_BASE + 0x0064) +-#define DSI1PCKCR (CPG_BASE + 0x0068) +-#define DSI0PHYCR (CPG_BASE + 0x006C) +-#define DVFSCR3 (CPG_BASE + 0x0174) +-#define DVFSCR4 (CPG_BASE + 0x0178) +-#define DVFSCR5 (CPG_BASE + 0x017C) +-#define MPMODE (CPG_BASE + 0x00CC) +- +-#define PLLECR (CPG_BASE + 0x00D0) +-#define PLL0CR (CPG_BASE + 0x00D8) +-#define PLL1CR (CPG_BASE + 0x0028) +-#define PLL2CR (CPG_BASE + 0x002C) +-#define PLL3CR (CPG_BASE + 0x00DC) +-#define PLL0STPCR (CPG_BASE + 0x00F0) +-#define PLL1STPCR (CPG_BASE + 0x00C8) +-#define PLL2STPCR (CPG_BASE + 0x00F8) +-#define PLL3STPCR (CPG_BASE + 0x00FC) +-#define RMSTPCR0 (CPG_BASE + 0x0110) +-#define RMSTPCR1 (CPG_BASE + 0x0114) +-#define RMSTPCR2 (CPG_BASE + 0x0118) +-#define RMSTPCR3 (CPG_BASE + 0x011C) +-#define RMSTPCR4 (CPG_BASE + 0x0120) +-#define RMSTPCR5 (CPG_BASE + 0x0124) +-#define SMSTPCR0 (CPG_BASE + 0x0130) +-#define SMSTPCR2 (CPG_BASE + 0x0138) +-#define SMSTPCR3 (CPG_BASE + 0x013C) +-#define CPGXXCR4 (CPG_BASE + 0x0150) +-#define SRCR0 (CPG_BASE + 0x80A0) +-#define SRCR2 (CPG_BASE + 0x80B0) +-#define SRCR3 (CPG_BASE + 0x80A8) +-#define VREFCR (CPG_BASE + 0x00EC) +-#define PCLKCR (CPG_BASE + 0x1020) +- +-#define PORT32CR (0xE6051020) +-#define PORT33CR (0xE6051021) +-#define PORT34CR (0xE6051022) +-#define PORT35CR (0xE6051023) +- +-LIST "DRAM initialization code:" +- +-EW RWTCSRA0, 0xA507 +- +-ED_AND LIFEC_SEC_SRC, 0xFFFF7FFF +- +-ED_AND SMSTPCR3,0xFFFF7FFF +-ED_AND SRCR3, 0xFFFF7FFF +-ED_AND SMSTPCR2,0xFFFBFFFF +-ED_AND SRCR2, 0xFFFBFFFF +-ED PLLECR, 0x00000000 +- +-WAIT_MASK PLLECR, 0x00000F00, 0x00000000 +-WAIT_MASK FRQCRB, 0x80000000, 0x00000000 +- +-ED PLL0CR, 0x2D000000 +-ED PLL1CR, 0x17100000 +-ED FRQCRB, 0x96235880 +-WAIT_MASK FRQCRB, 0x80000000, 0x00000000 +- +-ED FLCKCR, 0x0000000B +-ED_AND SMSTPCR0, 0xFFFFFFFD +- +-ED_AND SRCR0, 0xFFFFFFFD +-ED 0xE6001628, 0x514 +-ED 0xE6001648, 0x514 +-ED 0xE6001658, 0x514 +-ED 0xE6001678, 0x514 +- +-ED DVFSCR4, 0x00092000 +-ED DVFSCR5, 0x000000DC +-ED PLLECR, 0x00000000 +-WAIT_MASK PLLECR, 0x00000F00, 0x00000000 +- +-ED FRQCRA, 0x0012453C +-ED FRQCRB, 0x80431350 +-WAIT_MASK FRQCRB, 0x80000000, 0x00000000 +-ED FRQCRD, 0x00000B0B +-WAIT_MASK FRQCRD, 0x80000000, 0x00000000 +- +-ED PCLKCR, 0x00000003 +-ED VCLKCR1, 0x0000012F +-ED VCLKCR2, 0x00000119 +-ED VCLKCR3, 0x00000119 +-ED ZBCKCR, 0x00000002 +-ED FLCKCR, 0x00000005 +-ED SD0CKCR, 0x00000080 +-ED SD1CKCR, 0x00000080 +-ED SD2CKCR, 0x00000080 +-ED FSIACKCR, 0x0000003F +-ED FSIBCKCR, 0x0000003F +-ED SUBCKCR, 0x00000080 +-ED SPUACKCR, 0x0000000B +-ED SPUVCKCR, 0x0000000B +-ED MSUCKCR, 0x0000013F +-ED HSICKCR, 0x00000080 +-ED MFCK1CR, 0x0000003F +-ED MFCK2CR, 0x0000003F +-ED DSITCKCR, 0x00000107 +-ED DSI0PCKCR, 0x00000313 +-ED DSI1PCKCR, 0x0000130D +-ED DSI0PHYCR, 0x2A800E0E +-ED PLL0CR, 0x1E000000 +-ED PLL0CR, 0x2D000000 +-ED PLL1CR, 0x17100000 +-ED PLL2CR, 0x27000080 +-ED PLL3CR, 0x1D000000 +-ED PLL0STPCR, 0x00080000 +-ED PLL1STPCR, 0x000120C0 +-ED PLL2STPCR, 0x00012000 +-ED PLL3STPCR, 0x00000030 +-ED PLLECR, 0x0000000B +-WAIT_MASK PLLECR, 0x00000B00, 0x00000B00 +- +-ED DVFSCR3, 0x000120F0 +-ED MPMODE, 0x00000020 +-ED VREFCR, 0x0000028A +-ED RMSTPCR0, 0xE4628087 +-ED RMSTPCR1, 0xFFFFFFFF +-ED RMSTPCR2, 0x53FFFFFF +-ED RMSTPCR3, 0xFFFFFFFF +-ED RMSTPCR4, 0x00800D3D +-ED RMSTPCR5, 0xFFFFF3FF +-ED SMSTPCR2, 0x00000000 +-ED SRCR2, 0x00040000 +-ED_AND PLLECR, 0xFFFFFFF7 +-WAIT_MASK PLLECR, 0x00000800, 0x00000000 +- +-LIST "set SBSC operational" +-ED HPBCTRL6, 0x00000001 +-WAIT_MASK HPBCTRL6, 0x00000001, 0x00000001 +- +-LIST "set SBSC operating frequency" +-ED FRQCRD, 0x00001414 +-WAIT_MASK FRQCRD, 0x80000000, 0x00000000 +-ED PLL3CR, 0x1D000000 +-ED_OR PLLECR, 0x00000008 +-WAIT_MASK PLLECR, 0x00000800, 0x00000800 +- +-LIST "enable DLL oscillation in DDRPHY" +-ED_OR DLLCNT0A, 0x00000002 +- +-LIST "wait >= 100 ns" +-ED SDGENCNTA, 0x00000005 +-WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 +- +-LIST "target LPDDR2 device settings" +-ED SDCR0A, 0xACC90159 +-ED SDCR1A, 0x00010059 +-ED SDWCRC0A, 0x50874114 +-ED SDWCRC1A, 0x33199B37 +-ED SDWCRC2A, 0x008F2313 +-ED SDWCR00A, 0x31020707 +-ED SDWCR01A, 0x0017040A +-ED SDWCR10A, 0x31020707 +-ED SDWCR11A, 0x0017040A +- +-ED SDDRVCR0A, 0x055557ff +- +-ED SDWCR2A, 0x30000000 +- +-LIST "drive CKE high" +-ED_OR SDPCRA, 0x00000080 +-WAIT_MASK SDPCRA, 0x00000080, 0x00000080 +- +-LIST "wait >= 200 us" +-ED SDGENCNTA, 0x00002710 +-WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 +- +-LIST "issue reset command to LPDDR2 device" +-ED SDMRACR0A, 0x0000003F +-ED SDMRA1, 0x00000000 +- +-LIST "wait >= 10 (or 1) us (docs inconsistent)" +-ED SDGENCNTA, 0x000001F4 +-WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 +- +-LIST "MRW ZS initialization calibration command" +-ED SDMRACR0A, 0x0000FF0A +-ED SDMRA3, 0x00000000 +- +-LIST "wait >= 1 us" +-ED SDGENCNTA, 0x00000032 +-WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 +- +-LIST "specify operating mode in LPDDR2" +-ED SDMRACR0A, 0x00002201 +-ED SDMRA1, 0x00000000 +-ED SDMRACR0A, 0x00000402 +-ED SDMRA1, 0x00000000 +-ED SDMRACR0A, 0x00000203 +-ED SDMRA1, 0x00000000 +- +-LIST "initialize DDR interface" +-ED SDMRA2, 0x00000000 +- +-LIST "temperature sensor control" +-ED SDMRTMPCRA, 0x88800004 +-ED SDMRTMPMSKA,0x00000004 +- +-LIST "auto-refreshing control" +-ED RTCORA, 0xA55A0032 +-ED RTCORHA, 0xA55A000C +-ED RTCSRA, 0xA55A2048 +- +-ED_OR SDCR0A, 0x00000800 +-ED_OR SDCR1A, 0x00000400 +- +-LIST "auto ZQ calibration control" +-ED ZQCCRA, 0xFFF20000 +- +-ED_OR DLLCNT0B, 0x00000002 +-ED SDGENCNTB, 0x00000005 +-WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 +- +-ED SDCR0B, 0xACC90159 +-ED SDCR1B, 0x00010059 +-ED SDWCRC0B, 0x50874114 +-ED SDWCRC1B, 0x33199B37 +-ED SDWCRC2B, 0x008F2313 +-ED SDWCR00B, 0x31020707 +-ED SDWCR01B, 0x0017040A +-ED SDWCR10B, 0x31020707 +-ED SDWCR11B, 0x0017040A +-ED SDDRVCR0B, 0x055557ff +-ED SDWCR2B, 0x30000000 +-ED_OR SDPCRB, 0x00000080 +-WAIT_MASK SDPCRB, 0x00000080, 0x00000080 +- +-ED SDGENCNTB, 0x00002710 +-WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 +-ED SDMRACR0B, 0x0000003F +- +-LIST "upstream u-boot writes to SDMRA1A for both SBSC 1 and 2, which does" +-LIST "not seem to make a lot of sense..." +-ED SDMRB1, 0x00000000 +- +-ED SDGENCNTB, 0x000001F4 +-WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 +- +-ED SDMRACR0B, 0x0000FF0A +-ED SDMRB3, 0x00000000 +-ED SDGENCNTB, 0x00000032 +-WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 +- +-ED SDMRACR0B, 0x00002201 +-ED SDMRB1, 0x00000000 +-ED SDMRACR0B, 0x00000402 +-ED SDMRB1, 0x00000000 +-ED SDMRACR0B, 0x00000203 +-ED SDMRB1, 0x00000000 +-ED SDMRB2, 0x00000000 +-ED SDMRTMPCRB, 0x88800004 +-ED SDMRTMPMSKB, 0x00000004 +-ED RTCORB, 0xA55A0032 +-ED RTCORHB, 0xA55A000C +-ED RTCSRB, 0xA55A2048 +-ED_OR SDCR0B, 0x00000800 +-ED_OR SDCR1B, 0x00000400 +-ED ZQCCRB, 0xFFF20000 +-ED_OR SDPDCR0B, 0x00030000 +-ED DPHYCNT1B, 0xA5390000 +-ED DPHYCNT0B, 0x00001200 +-ED DPHYCNT1B, 0x07CE0000 +-ED DPHYCNT0B, 0x00001247 +-WAIT_MASK DPHYCNT2B, 0xFFFFFFFF, 0x07CE0000 +- +-ED_AND SDPDCR0B, 0xFFFCFFFF +- +-ED FRQCRD, 0x00000B0B +-WAIT_MASK FRQCRD, 0x80000000, 0x00000000 +- +-ED CPGXXCR4, 0xfffffffc +- +-LIST "Setup SCIF4 / workaround" +-EB PORT32CR, 0x12 +-EB PORT33CR, 0x22 +-EB PORT34CR, 0x12 +-EB PORT35CR, 0x22 +- +-EW 0xE6C80000, 0 +-EB 0xE6C80004, 0x19 +-EW 0xE6C80008, 0x0030 +-EW 0xE6C80018, 0 +-EW 0xE6C80030, 0x0014 +- +-LIST "Magic to avoid hangs and corruption on DRAM writes." +- +-LIST "It has been observed that the system would most often hang while" +-LIST "decompressing the kernel, and if it didn't it would always write" +-LIST "a corrupt image to DRAM." +-LIST "This problem does not occur in u-boot, and the reason is that" +-LIST "u-boot performs an additional cache invalidation after setting up" +-LIST "the DRAM controller. Such an invalidation should not be necessary at" +-LIST "this point, and attempts at removing parts of the routine to arrive" +-LIST "at the minimal snippet of code necessary to avoid the DRAM stability" +-LIST "problem yielded the following:" +- +-MRC p15, 0, r0, c1, c0, 0 +-MCR p15, 0, r0, c1, c0, 0 +diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h +index 175ee05465da..80f599f4b5ab 100644 +--- a/arch/arm/mach-shmobile/include/mach/zboot.h ++++ b/arch/arm/mach-shmobile/include/mach/zboot.h +@@ -9,11 +9,6 @@ + * + **************************************************/ + +-#ifdef CONFIG_MACH_KZM9G +-#define MEMORY_START 0x43000000 +-#include "mach/head-kzm9g.txt" +-#else + #error "unsupported board." +-#endif + + #endif /* ZBOOT_H */ +diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c +deleted file mode 100644 +index fd63ae6532fc..000000000000 +--- a/arch/arm/mach-shmobile/intc-sh73a0.c ++++ /dev/null +@@ -1,337 +0,0 @@ +-/* +- * sh73a0 processor support - INTC hardware block +- * +- * Copyright (C) 2010 Magnus Damm +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +-#include <linux/kernel.h> +-#include <linux/init.h> +-#include <linux/interrupt.h> +-#include <linux/module.h> +-#include <linux/irq.h> +-#include <linux/io.h> +-#include <linux/irqchip.h> +-#include <linux/irqchip/arm-gic.h> +- +-#include <asm/mach-types.h> +-#include <asm/mach/arch.h> +- +-#include "intc.h" +-#include "irqs.h" +-#include "sh73a0.h" +- +-enum { +- UNUSED = 0, +- +- /* interrupt sources INTCS */ +- PINTCS_PINT1, PINTCS_PINT2, +- RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3, +- CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0, +- RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR, +- KEYSC_KEY, VINT, MSIOF, +- TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02, +- CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2, +- CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC, +- RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9, +- RTDMAC_3_DEI10, RTDMAC_3_DEI11, +- FRC, GCU, LCDC1, CSIRX, +- DSITX0_DSITX00, DSITX0_DSITX01, +- SPU2_SPU0, SPU2_SPU1, FSI, +- TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, +- TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW, +- VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11, +- DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I, +- MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I, +- SPUV, +- +- /* interrupt groups INTCS */ +- RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3, +- DSITX0, SPU2, TMU1, MSU, +-}; +- +-static struct intc_vect intcs_vectors[] = { +- INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620), +- INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820), +- INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860), +- INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900), +- INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980), +- INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0), +- INTCS_VECT(_2DDMAC_2DDM0, 0x0a00), +- INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0), +- INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0), +- INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80), +- INTCS_VECT(MSIOF, 0x0d20), +- INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0), +- INTCS_VECT(TMU0_TUNI02, 0x0ec0), +- INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20), +- INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60), +- INTCS_VECT(MSUG, 0x0f80), +- INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0), +- INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440), +- INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0), +- INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560), +- INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0), +- INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320), +- INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360), +- INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0), +- INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760), +- INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0), +- INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0), +- INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820), +- INTCS_VECT(FSI, 0x1840), +- INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920), +- INTCS_VECT(TMU1_TUNI12, 0x1940), +- INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980), +- INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20), +- INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00), +- INTCS_VECT(SCUW, 0x1b40), +- INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80), +- INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0), +- INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20), +- INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60), +- INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0), +- INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0), +- INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20), +- INTCS_VECT(SPUV, 0x2300), +-}; +- +-static struct intc_group intcs_groups[] __initdata = { +- INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1, +- RTDMAC_0_DEI2, RTDMAC_0_DEI3), +- INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR), +- INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7, +- RTDMAC_2_DEI8, RTDMAC_2_DEI9), +- INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11), +- INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10), +- INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01), +- INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), +- INTC_GROUP(MSU, MSU_MSU, MSU_MSU2), +-}; +- +-static struct intc_mask_reg intcs_mask_registers[] = { +- { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */ +- { 0, 0, 0, CEU, +- 0, 0, 0, 0 } }, +- { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */ +- { 0, 0, 0, VPU, +- BBIF2, 0, 0, MFI } }, +- { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */ +- { 0, 0, 0, _2DDMAC_2DDM0, +- 0, ASA, PEP, ICB } }, +- { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */ +- { 0, 0, 0, CTI, +- JPU_JPEG, 0, LCRC, LCDC } }, +- { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */ +- { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4, +- RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } }, +- { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ +- { 0, 0, MSIOF, 0, +- _3DG_SGX543, 0, 0, 0 } }, +- { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ +- { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00, +- 0, 0, 0, 0 } }, +- { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */ +- { 0, 0, 0, 0, +- 0, MSU_MSU, MSU_MSU2, MSUG } }, +- { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */ +- { 0, RWDT0, CMT2, CMT0, +- 0, 0, 0, 0 } }, +- { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */ +- { 0, 0, 0, 0, +- 0, TSIF1, LMB, TSIF0 } }, +- { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */ +- { 0, 0, 0, 0, +- 0, 0, PINTCS_PINT2, PINTCS_PINT1 } }, +- { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */ +- { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9, +- RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } }, +- { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */ +- { FRC, 0, 0, GCU, +- LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } }, +- { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */ +- { SPU2_SPU0, SPU2_SPU1, FSI, 0, +- 0, 0, 0, 0 } }, +- { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */ +- { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0, +- TSIF2, CMT4, 0, 0 } }, +- { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */ +- { MFIS2, CPORTS2R, 0, 0, +- 0, 0, 0, TSG } }, +- { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */ +- { DMASCH1, 0, SCUW, VIO60, +- VIO61, CEU21, 0, CSI21 } }, +- { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */ +- { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV, +- EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } }, +- { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */ +- { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0, +- 0, 0, 0, 0 } }, +- { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */ +- { SPUV, 0, 0, 0, +- 0, 0, 0, 0 } }, +-}; +- +-/* Priority is needed for INTCA to receive the INTCS interrupt */ +-static struct intc_prio_reg intcs_prio_registers[] = { +- { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } }, +- { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } }, +- { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } }, +- { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2, +- 0, 0 } }, +- { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } }, +- { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1, +- CMT2, CMT0 } }, +- { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01, +- TMU0_TUNI02, TSIF1 } }, +- { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } }, +- { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } }, +- { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } }, +- { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } }, +- { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } }, +- { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } }, +- { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } }, +- { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } }, +- { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } }, +- { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } }, +- { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } }, +- { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } }, +- { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } }, +- { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } }, +- { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } }, +- { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11, +- DISP, DSRV } }, +- { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I, +- MSTIF0_MST00I, MSTIF0_MST01I } }, +- { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I, +- 0, 0 } }, +- { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } }, +-}; +- +-static struct resource intcs_resources[] __initdata = { +- [0] = { +- .start = 0xffd20000, +- .end = 0xffd201ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = 0xffd50000, +- .end = 0xffd501ff, +- .flags = IORESOURCE_MEM, +- }, +- [2] = { +- .start = 0xffd60000, +- .end = 0xffd601ff, +- .flags = IORESOURCE_MEM, +- } +-}; +- +-static struct intc_desc intcs_desc __initdata = { +- .name = "sh73a0-intcs", +- .resource = intcs_resources, +- .num_resources = ARRAY_SIZE(intcs_resources), +- .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, +- intcs_prio_registers, NULL, NULL), +-}; +- +-static struct irqaction sh73a0_intcs_cascade; +- +-static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id) +-{ +- unsigned int evtcodeas = ioread32((void __iomem *)dev_id); +- +- generic_handle_irq(intcs_evt2irq(evtcodeas)); +- +- return IRQ_HANDLED; +-} +- +-#define PINTER0_PHYS 0xe69000a0 +-#define PINTER1_PHYS 0xe69000a4 +-#define PINTER0_VIRT IOMEM(0xe69000a0) +-#define PINTER1_VIRT IOMEM(0xe69000a4) +-#define PINTRR0 IOMEM(0xe69000d0) +-#define PINTRR1 IOMEM(0xe69000d4) +- +-#define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq)) +-#define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8)) +-#define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16)) +-#define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24)) +-#define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq)) +- +-INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0", \ +- INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ +- INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \ +- INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \ +- INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ +- INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D)); +- +-INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1", \ +- INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \ +- INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \ +- INTC_PINT_V_NONE, INTC_PINT_V_NONE, \ +- INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \ +- INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE); +- +-static struct irqaction sh73a0_pint0_cascade; +-static struct irqaction sh73a0_pint1_cascade; +- +-static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq) +-{ +- unsigned long value = ioread32(rr) & ioread32(er); +- int k; +- +- for (k = 0; k < 32; k++) { +- if (value & (1 << (31 - k))) { +- generic_handle_irq(base_irq + k); +- iowrite32(~(1 << (31 - k)), rr); +- } +- } +-} +- +-static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id) +-{ +- pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0)); +- return IRQ_HANDLED; +-} +- +-static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id) +-{ +- pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0)); +- return IRQ_HANDLED; +-} +- +-void __init sh73a0_init_irq(void) +-{ +- void __iomem *gic_dist_base = IOMEM(0xf0001000); +- void __iomem *gic_cpu_base = IOMEM(0xf0000100); +- void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); +- +- gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE); +- gic_init(0, 29, gic_dist_base, gic_cpu_base); +- +- register_intc_controller(&intcs_desc); +- register_intc_controller(&intc_pint0_desc); +- register_intc_controller(&intc_pint1_desc); +- +- /* demux using INTEVTSA */ +- sh73a0_intcs_cascade.name = "INTCS cascade"; +- sh73a0_intcs_cascade.handler = sh73a0_intcs_demux; +- sh73a0_intcs_cascade.dev_id = intevtsa; +- setup_irq(gic_spi(50), &sh73a0_intcs_cascade); +- +- /* PINT pins are sanely tied to the GIC as SPI */ +- sh73a0_pint0_cascade.name = "PINT0 cascade"; +- sh73a0_pint0_cascade.handler = sh73a0_pint0_demux; +- setup_irq(gic_spi(33), &sh73a0_pint0_cascade); +- +- sh73a0_pint1_cascade.name = "PINT1 cascade"; +- sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; +- setup_irq(gic_spi(34), &sh73a0_pint1_cascade); +-} +-- +2.6.2 + diff --git a/patches.renesas/0147-ARM-shmobile-Remove-legacy-kzm9g_defconfig.patch b/patches.renesas/0147-ARM-shmobile-Remove-legacy-kzm9g_defconfig.patch new file mode 100644 index 00000000000000..c7d4a725e4a622 --- /dev/null +++ b/patches.renesas/0147-ARM-shmobile-Remove-legacy-kzm9g_defconfig.patch @@ -0,0 +1,192 @@ +From 59083d469907cf5f2e758f59b688e74058667807 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:31:18 +0200 +Subject: [PATCH 147/326] ARM: shmobile: Remove legacy kzm9g_defconfig + +The legacy board code for KZM-A9-GT has been removed. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 04320ccfc11b9ca9b7cf933e221a765d78705cf8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + MAINTAINERS | 1 - + arch/arm/configs/kzm9g_defconfig | 154 --------------------------------------- + 2 files changed, 155 deletions(-) + delete mode 100644 arch/arm/configs/kzm9g_defconfig + +diff --git a/MAINTAINERS b/MAINTAINERS +index d8afd2953678..77edd4bec210 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -1442,7 +1442,6 @@ F: arch/arm/boot/dts/r8a* + F: arch/arm/boot/dts/sh* + F: arch/arm/configs/armadillo800eva_defconfig + F: arch/arm/configs/bockw_defconfig +-F: arch/arm/configs/kzm9g_defconfig + F: arch/arm/configs/marzen_defconfig + F: arch/arm/configs/shmobile_defconfig + F: arch/arm/include/debug/renesas-scif.S +diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig +deleted file mode 100644 +index 23e8d146dc16..000000000000 +--- a/arch/arm/configs/kzm9g_defconfig ++++ /dev/null +@@ -1,154 +0,0 @@ +-# CONFIG_ARM_PATCH_PHYS_VIRT is not set +-CONFIG_EXPERIMENTAL=y +-# CONFIG_LOCALVERSION_AUTO is not set +-CONFIG_SYSVIPC=y +-CONFIG_IKCONFIG=y +-CONFIG_IKCONFIG_PROC=y +-CONFIG_LOG_BUF_SHIFT=16 +-CONFIG_NAMESPACES=y +-# CONFIG_UTS_NS is not set +-# CONFIG_IPC_NS is not set +-# CONFIG_USER_NS is not set +-# CONFIG_PID_NS is not set +-# CONFIG_NET_NS is not set +-CONFIG_CC_OPTIMIZE_FOR_SIZE=y +-CONFIG_SYSCTL_SYSCALL=y +-CONFIG_EMBEDDED=y +-CONFIG_PERF_EVENTS=y +-CONFIG_SLAB=y +-CONFIG_MODULES=y +-CONFIG_MODULE_FORCE_LOAD=y +-CONFIG_MODULE_UNLOAD=y +-# CONFIG_BLK_DEV_BSG is not set +-# CONFIG_IOSCHED_DEADLINE is not set +-# CONFIG_IOSCHED_CFQ is not set +-CONFIG_ARCH_SHMOBILE_LEGACY=y +-CONFIG_ARCH_SH73A0=y +-CONFIG_MACH_KZM9G=y +-CONFIG_MEMORY_START=0x41000000 +-CONFIG_MEMORY_SIZE=0x1f000000 +-CONFIG_ARM_ERRATA_743622=y +-CONFIG_ARM_ERRATA_754322=y +-CONFIG_NO_HZ=y +-CONFIG_HIGH_RES_TIMERS=y +-CONFIG_SMP=y +-CONFIG_SCHED_MC=y +-CONFIG_AEABI=y +-# CONFIG_OABI_COMPAT is not set +-CONFIG_HIGHMEM=y +-CONFIG_ZBOOT_ROM_TEXT=0x0 +-CONFIG_ZBOOT_ROM_BSS=0x0 +-CONFIG_ARM_APPENDED_DTB=y +-CONFIG_KEXEC=y +-CONFIG_VFP=y +-CONFIG_NEON=y +-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +-CONFIG_PM=y +-CONFIG_NET=y +-CONFIG_PACKET=y +-CONFIG_UNIX=y +-CONFIG_INET=y +-CONFIG_IP_PNP=y +-CONFIG_IP_PNP_DHCP=y +-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +-# CONFIG_INET_XFRM_MODE_TUNNEL is not set +-# CONFIG_INET_XFRM_MODE_BEET is not set +-# CONFIG_INET_LRO is not set +-# CONFIG_INET_DIAG is not set +-# CONFIG_IPV6 is not set +-CONFIG_IRDA=y +-CONFIG_SH_IRDA=y +-# CONFIG_WIRELESS is not set +-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +-CONFIG_DEVTMPFS=y +-CONFIG_DEVTMPFS_MOUNT=y +-CONFIG_SCSI=y +-CONFIG_BLK_DEV_SD=y +-CONFIG_NETDEVICES=y +-CONFIG_SMSC911X=y +-# CONFIG_WLAN is not set +-CONFIG_INPUT_SPARSEKMAP=y +-# CONFIG_INPUT_MOUSEDEV is not set +-CONFIG_INPUT_EVDEV=y +-# CONFIG_KEYBOARD_ATKBD is not set +-CONFIG_KEYBOARD_GPIO=y +-# CONFIG_INPUT_MOUSE is not set +-CONFIG_INPUT_TOUCHSCREEN=y +-CONFIG_TOUCHSCREEN_ST1232=y +-CONFIG_INPUT_MISC=y +-CONFIG_INPUT_ADXL34X=y +-# CONFIG_LEGACY_PTYS is not set +-CONFIG_SERIAL_SH_SCI=y +-CONFIG_SERIAL_SH_SCI_NR_UARTS=9 +-CONFIG_SERIAL_SH_SCI_CONSOLE=y +-# CONFIG_HW_RANDOM is not set +-CONFIG_I2C_CHARDEV=y +-CONFIG_I2C_SH_MOBILE=y +-CONFIG_GPIO_PCF857X=y +-# CONFIG_HWMON is not set +-CONFIG_MFD_AS3711=y +-CONFIG_REGULATOR=y +-CONFIG_REGULATOR_AS3711=y +-CONFIG_FB=y +-CONFIG_FB_SH_MOBILE_LCDC=y +-CONFIG_BACKLIGHT_AS3711=y +-CONFIG_FRAMEBUFFER_CONSOLE=y +-CONFIG_LOGO=y +-CONFIG_FB_SH_MOBILE_MERAM=y +-CONFIG_SOUND=y +-CONFIG_SND=y +-# CONFIG_SND_SUPPORT_OLD_API is not set +-# CONFIG_SND_VERBOSE_PROCFS is not set +-# CONFIG_SND_DRIVERS is not set +-# CONFIG_SND_ARM is not set +-# CONFIG_SND_USB is not set +-CONFIG_SND_SOC=y +-CONFIG_SND_SOC_SH4_FSI=y +-# CONFIG_HID_SUPPORT is not set +-CONFIG_USB=y +-CONFIG_USB_R8A66597_HCD=y +-CONFIG_USB_RENESAS_USBHS=y +-CONFIG_USB_STORAGE=y +-CONFIG_USB_GADGET=y +-CONFIG_USB_RENESAS_USBHS_UDC=y +-CONFIG_USB_ETH=m +-CONFIG_USB_MASS_STORAGE=m +-CONFIG_MMC=y +-# CONFIG_MMC_BLOCK_BOUNCE is not set +-CONFIG_MMC_SDHI=y +-CONFIG_MMC_SH_MMCIF=y +-CONFIG_NEW_LEDS=y +-CONFIG_LEDS_CLASS=y +-CONFIG_LEDS_GPIO=y +-CONFIG_RTC_CLASS=y +-CONFIG_RTC_DRV_RS5C372=y +-CONFIG_DMADEVICES=y +-CONFIG_SH_DMAE=y +-CONFIG_ASYNC_TX_DMA=y +-CONFIG_STAGING=y +-CONFIG_IIO=y +-CONFIG_AK8975=y +-# CONFIG_DNOTIFY is not set +-CONFIG_VFAT_FS=y +-CONFIG_TMPFS=y +-# CONFIG_MISC_FILESYSTEMS is not set +-CONFIG_NFS_FS=y +-CONFIG_NFS_V3=y +-CONFIG_NFS_V3_ACL=y +-CONFIG_NFS_V4=y +-CONFIG_NFS_V4_1=y +-CONFIG_ROOT_NFS=y +-CONFIG_NLS_CODEPAGE_437=y +-CONFIG_NLS_ISO8859_1=y +-# CONFIG_ENABLE_WARN_DEPRECATED is not set +-# CONFIG_ENABLE_MUST_CHECK is not set +-# CONFIG_SCHED_DEBUG is not set +-# CONFIG_DEBUG_PREEMPT is not set +-# CONFIG_DEBUG_BUGVERBOSE is not set +-# CONFIG_FTRACE is not set +-# CONFIG_ARM_UNWIND is not set +-CONFIG_CRYPTO=y +-CONFIG_CRYPTO_CBC=y +-CONFIG_CRYPTO_MD5=y +-CONFIG_CRYPTO_DES=y +-CONFIG_CRC16=y +-- +2.6.2 + diff --git a/patches.renesas/0148-ARM-shmobile-Drop-sh73a0-kzm9g.dtb-for-legacy-builds.patch b/patches.renesas/0148-ARM-shmobile-Drop-sh73a0-kzm9g.dtb-for-legacy-builds.patch new file mode 100644 index 00000000000000..02959f0e7f97ca --- /dev/null +++ b/patches.renesas/0148-ARM-shmobile-Drop-sh73a0-kzm9g.dtb-for-legacy-builds.patch @@ -0,0 +1,33 @@ +From b1f84221c25fdcc690c6749a64d38e8227a3e3fd Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:31:19 +0200 +Subject: [PATCH 148/326] ARM: shmobile: Drop sh73a0-kzm9g.dtb for legacy + builds + +The legacy board code for KZM-A9-GT has been removed. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d99f70b9533dc355e0facbaee8a42dcd821a5e73) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/Makefile | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 992736b5229b..b7b3f0fbb25b 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -480,8 +480,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \ + r8a7740-armadillo800eva.dtb \ + r8a7778-bockw.dtb \ + r8a7778-bockw-reference.dtb \ +- r8a7779-marzen.dtb \ +- sh73a0-kzm9g.dtb ++ r8a7779-marzen.dtb + dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ + emev2-kzm9d.dtb \ + r7s72100-genmai.dtb \ +-- +2.6.2 + diff --git a/patches.renesas/0149-ARM-shmobile-Remove-legacy-SoC-code-for-SH-Mobile-AG.patch b/patches.renesas/0149-ARM-shmobile-Remove-legacy-SoC-code-for-SH-Mobile-AG.patch new file mode 100644 index 00000000000000..598ec43d586e65 --- /dev/null +++ b/patches.renesas/0149-ARM-shmobile-Remove-legacy-SoC-code-for-SH-Mobile-AG.patch @@ -0,0 +1,1755 @@ +From d6d88ed57d08894da1fc690b39ad67a3befc9635 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:31:20 +0200 +Subject: [PATCH 149/326] ARM: shmobile: Remove legacy SoC code for SH-Mobile + AG5 + +The last user of the SH-Mobile AG5 (sh73a0) legacy SoC code was the +KZM-A9-GT legacy board code, which has been removed. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9a9863987bf7307f619f1dbba678a3e6d65c901a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 9 - + arch/arm/mach-shmobile/Makefile | 3 +- + arch/arm/mach-shmobile/clock-sh73a0.c | 752 ---------------------------------- + arch/arm/mach-shmobile/pm-sh73a0.c | 32 -- + arch/arm/mach-shmobile/setup-sh73a0.c | 739 +-------------------------------- + arch/arm/mach-shmobile/sh73a0.h | 83 ---- + arch/arm/mach-shmobile/smp-sh73a0.c | 8 - + 7 files changed, 2 insertions(+), 1624 deletions(-) + delete mode 100644 arch/arm/mach-shmobile/clock-sh73a0.c + delete mode 100644 arch/arm/mach-shmobile/pm-sh73a0.c + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index b85b34c1d6e0..c506be27b610 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -105,15 +105,6 @@ if ARCH_SHMOBILE_LEGACY + + comment "Renesas ARM SoCs System Type" + +-config ARCH_SH73A0 +- bool "SH-Mobile AG5 (R8A73A00)" +- select ARCH_RMOBILE +- select ARCH_WANT_OPTIONAL_GPIOLIB +- select ARM_GIC +- select I2C +- select SH_INTC +- select RENESAS_INTC_IRQPIN +- + config ARCH_R8A7740 + bool "R-Mobile A1 (R8A77400)" + select ARCH_RMOBILE +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index a4d7f5734e91..28e0f05a8577 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -6,7 +6,7 @@ + obj-y := timer.o console.o + + # CPU objects +-obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o pm-sh73a0.o ++obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o + obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o + obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o + obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o +@@ -20,7 +20,6 @@ obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o + # Clock objects + ifndef CONFIG_COMMON_CLK + obj-y += clock.o +-obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o + obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o + obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o + obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o +diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c +deleted file mode 100644 +index 3855fb024fdb..000000000000 +--- a/arch/arm/mach-shmobile/clock-sh73a0.c ++++ /dev/null +@@ -1,752 +0,0 @@ +-/* +- * sh73a0 clock framework support +- * +- * Copyright (C) 2010 Magnus Damm +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +-#include <linux/init.h> +-#include <linux/kernel.h> +-#include <linux/io.h> +-#include <linux/sh_clk.h> +-#include <linux/clkdev.h> +-#include <asm/processor.h> +-#include "clock.h" +-#include "common.h" +- +-#define FRQCRA IOMEM(0xe6150000) +-#define FRQCRB IOMEM(0xe6150004) +-#define FRQCRD IOMEM(0xe61500e4) +-#define VCLKCR1 IOMEM(0xe6150008) +-#define VCLKCR2 IOMEM(0xe615000C) +-#define VCLKCR3 IOMEM(0xe615001C) +-#define ZBCKCR IOMEM(0xe6150010) +-#define FLCKCR IOMEM(0xe6150014) +-#define SD0CKCR IOMEM(0xe6150074) +-#define SD1CKCR IOMEM(0xe6150078) +-#define SD2CKCR IOMEM(0xe615007C) +-#define FSIACKCR IOMEM(0xe6150018) +-#define FSIBCKCR IOMEM(0xe6150090) +-#define SUBCKCR IOMEM(0xe6150080) +-#define SPUACKCR IOMEM(0xe6150084) +-#define SPUVCKCR IOMEM(0xe6150094) +-#define MSUCKCR IOMEM(0xe6150088) +-#define HSICKCR IOMEM(0xe615008C) +-#define MFCK1CR IOMEM(0xe6150098) +-#define MFCK2CR IOMEM(0xe615009C) +-#define DSITCKCR IOMEM(0xe6150060) +-#define DSI0PCKCR IOMEM(0xe6150064) +-#define DSI1PCKCR IOMEM(0xe6150068) +-#define DSI0PHYCR 0xe615006C +-#define DSI1PHYCR 0xe6150070 +-#define PLLECR IOMEM(0xe61500d0) +-#define PLL0CR IOMEM(0xe61500d8) +-#define PLL1CR IOMEM(0xe6150028) +-#define PLL2CR IOMEM(0xe615002c) +-#define PLL3CR IOMEM(0xe61500dc) +-#define SMSTPCR0 IOMEM(0xe6150130) +-#define SMSTPCR1 IOMEM(0xe6150134) +-#define SMSTPCR2 IOMEM(0xe6150138) +-#define SMSTPCR3 IOMEM(0xe615013c) +-#define SMSTPCR4 IOMEM(0xe6150140) +-#define SMSTPCR5 IOMEM(0xe6150144) +-#define CKSCR IOMEM(0xe61500c0) +- +-/* Fixed 32 KHz root clock from EXTALR pin */ +-static struct clk r_clk = { +- .rate = 32768, +-}; +- +-/* +- * 26MHz default rate for the EXTAL1 root input clock. +- * If needed, reset this with clk_set_rate() from the platform code. +- */ +-struct clk sh73a0_extal1_clk = { +- .rate = 26000000, +-}; +- +-/* +- * 48MHz default rate for the EXTAL2 root input clock. +- * If needed, reset this with clk_set_rate() from the platform code. +- */ +-struct clk sh73a0_extal2_clk = { +- .rate = 48000000, +-}; +- +-static struct sh_clk_ops main_clk_ops = { +- .recalc = followparent_recalc, +-}; +- +-/* Main clock */ +-static struct clk main_clk = { +- /* .parent wll be set on sh73a0_clock_init() */ +- .ops = &main_clk_ops, +-}; +- +-/* PLL0, PLL1, PLL2, PLL3 */ +-static unsigned long pll_recalc(struct clk *clk) +-{ +- unsigned long mult = 1; +- +- if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) { +- mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1); +- /* handle CFG bit for PLL1 and PLL2 */ +- switch (clk->enable_bit) { +- case 1: +- case 2: +- if (__raw_readl(clk->enable_reg) & (1 << 20)) +- mult *= 2; +- } +- } +- +- return clk->parent->rate * mult; +-} +- +-static struct sh_clk_ops pll_clk_ops = { +- .recalc = pll_recalc, +-}; +- +-static struct clk pll0_clk = { +- .ops = &pll_clk_ops, +- .flags = CLK_ENABLE_ON_INIT, +- .parent = &main_clk, +- .enable_reg = (void __iomem *)PLL0CR, +- .enable_bit = 0, +-}; +- +-static struct clk pll1_clk = { +- .ops = &pll_clk_ops, +- .flags = CLK_ENABLE_ON_INIT, +- .parent = &main_clk, +- .enable_reg = (void __iomem *)PLL1CR, +- .enable_bit = 1, +-}; +- +-static struct clk pll2_clk = { +- .ops = &pll_clk_ops, +- .flags = CLK_ENABLE_ON_INIT, +- .parent = &main_clk, +- .enable_reg = (void __iomem *)PLL2CR, +- .enable_bit = 2, +-}; +- +-static struct clk pll3_clk = { +- .ops = &pll_clk_ops, +- .flags = CLK_ENABLE_ON_INIT, +- .parent = &main_clk, +- .enable_reg = (void __iomem *)PLL3CR, +- .enable_bit = 3, +-}; +- +-/* A fixed divide block */ +-SH_CLK_RATIO(div2, 1, 2); +-SH_CLK_RATIO(div7, 1, 7); +-SH_CLK_RATIO(div13, 1, 13); +- +-SH_FIXED_RATIO_CLK(extal1_div2_clk, sh73a0_extal1_clk, div2); +-SH_FIXED_RATIO_CLK(extal2_div2_clk, sh73a0_extal2_clk, div2); +-SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2); +-SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); +-SH_FIXED_RATIO_CLK(pll1_div7_clk, pll1_clk, div7); +-SH_FIXED_RATIO_CLK(pll1_div13_clk, pll1_clk, div13); +- +-/* External input clock */ +-struct clk sh73a0_extcki_clk = { +-}; +- +-struct clk sh73a0_extalr_clk = { +-}; +- +-static struct clk *main_clks[] = { +- &r_clk, +- &sh73a0_extal1_clk, +- &sh73a0_extal2_clk, +- &extal1_div2_clk, +- &extal2_div2_clk, +- &main_clk, +- &main_div2_clk, +- &pll0_clk, +- &pll1_clk, +- &pll2_clk, +- &pll3_clk, +- &pll1_div2_clk, +- &pll1_div7_clk, +- &pll1_div13_clk, +- &sh73a0_extcki_clk, +- &sh73a0_extalr_clk, +-}; +- +-static int frqcr_kick(void) +-{ +- int i; +- +- /* set KICK bit in FRQCRB to update hardware setting, check success */ +- __raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB); +- for (i = 1000; i; i--) +- if (__raw_readl(FRQCRB) & (1 << 31)) +- cpu_relax(); +- else +- return i; +- +- return -ETIMEDOUT; +-} +- +-static void div4_kick(struct clk *clk) +-{ +- frqcr_kick(); +-} +- +-static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, +- 24, 0, 36, 48, 7 }; +- +-static struct clk_div_mult_table div4_div_mult_table = { +- .divisors = divisors, +- .nr_divisors = ARRAY_SIZE(divisors), +-}; +- +-static struct clk_div4_table div4_table = { +- .div_mult_table = &div4_div_mult_table, +- .kick = div4_kick, +-}; +- +-enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, +- DIV4_Z, DIV4_ZX, DIV4_HP, DIV4_NR }; +- +-#define DIV4(_reg, _bit, _mask, _flags) \ +- SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) +- +-static struct clk div4_clks[DIV4_NR] = { +- [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT), +- /* +- * ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to +- * exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and +- * 239.2MHz for VDD_DVFS=1.315V. +- */ +- [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), +- [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), +- [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT), +- [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), +- [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), +- [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), +- [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), +- [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), +-}; +- +-static unsigned long twd_recalc(struct clk *clk) +-{ +- return clk_get_rate(clk->parent) / 4; +-} +- +-static struct sh_clk_ops twd_clk_ops = { +- .recalc = twd_recalc, +-}; +- +-static struct clk twd_clk = { +- .parent = &div4_clks[DIV4_Z], +- .ops = &twd_clk_ops, +-}; +- +-static struct sh_clk_ops zclk_ops, kicker_ops; +-static const struct sh_clk_ops *div4_clk_ops; +- +-static int zclk_set_rate(struct clk *clk, unsigned long rate) +-{ +- int ret; +- +- if (!clk->parent || !__clk_get(clk->parent)) +- return -ENODEV; +- +- if (readl(FRQCRB) & (1 << 31)) +- return -EBUSY; +- +- if (rate == clk_get_rate(clk->parent)) { +- /* 1:1 - switch off divider */ +- __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB); +- /* nullify the divider to prepare for the next time */ +- ret = div4_clk_ops->set_rate(clk, rate / 2); +- if (!ret) +- ret = frqcr_kick(); +- if (ret > 0) +- ret = 0; +- } else { +- /* Enable the divider */ +- __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB); +- +- ret = frqcr_kick(); +- if (ret >= 0) +- /* +- * set the divider - call the DIV4 method, it will kick +- * FRQCRB too +- */ +- ret = div4_clk_ops->set_rate(clk, rate); +- if (ret < 0) +- goto esetrate; +- } +- +-esetrate: +- __clk_put(clk->parent); +- return ret; +-} +- +-static long zclk_round_rate(struct clk *clk, unsigned long rate) +-{ +- unsigned long div_freq = div4_clk_ops->round_rate(clk, rate), +- parent_freq = clk_get_rate(clk->parent); +- +- if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq) +- return parent_freq; +- +- return div_freq; +-} +- +-static unsigned long zclk_recalc(struct clk *clk) +-{ +- /* +- * Must recalculate frequencies in case PLL0 has been changed, even if +- * the divisor is unused ATM! +- */ +- unsigned long div_freq = div4_clk_ops->recalc(clk); +- +- if (__raw_readl(FRQCRB) & (1 << 28)) +- return div_freq; +- +- return clk_get_rate(clk->parent); +-} +- +-static int kicker_set_rate(struct clk *clk, unsigned long rate) +-{ +- if (__raw_readl(FRQCRB) & (1 << 31)) +- return -EBUSY; +- +- return div4_clk_ops->set_rate(clk, rate); +-} +- +-static void div4_clk_extend(void) +-{ +- int i; +- +- div4_clk_ops = div4_clks[0].ops; +- +- /* Add a kicker-busy check before changing the rate */ +- kicker_ops = *div4_clk_ops; +- /* We extend the DIV4 clock with a 1:1 pass-through case */ +- zclk_ops = *div4_clk_ops; +- +- kicker_ops.set_rate = kicker_set_rate; +- zclk_ops.set_rate = zclk_set_rate; +- zclk_ops.round_rate = zclk_round_rate; +- zclk_ops.recalc = zclk_recalc; +- +- for (i = 0; i < DIV4_NR; i++) +- div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops; +-} +- +-enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, +- DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, +- DIV6_FSIA, DIV6_FSIB, DIV6_SUB, +- DIV6_SPUA, DIV6_SPUV, DIV6_MSU, +- DIV6_HSI, DIV6_MFG1, DIV6_MFG2, +- DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P, +- DIV6_NR }; +- +-static struct clk *vck_parent[8] = { +- [0] = &pll1_div2_clk, +- [1] = &pll2_clk, +- [2] = &sh73a0_extcki_clk, +- [3] = &sh73a0_extal2_clk, +- [4] = &main_div2_clk, +- [5] = &sh73a0_extalr_clk, +- [6] = &main_clk, +-}; +- +-static struct clk *pll_parent[4] = { +- [0] = &pll1_div2_clk, +- [1] = &pll2_clk, +- [2] = &pll1_div13_clk, +-}; +- +-static struct clk *hsi_parent[4] = { +- [0] = &pll1_div2_clk, +- [1] = &pll2_clk, +- [2] = &pll1_div7_clk, +-}; +- +-static struct clk *pll_extal2_parent[] = { +- [0] = &pll1_div2_clk, +- [1] = &pll2_clk, +- [2] = &sh73a0_extal2_clk, +- [3] = &sh73a0_extal2_clk, +-}; +- +-static struct clk *dsi_parent[8] = { +- [0] = &pll1_div2_clk, +- [1] = &pll2_clk, +- [2] = &main_clk, +- [3] = &sh73a0_extal2_clk, +- [4] = &sh73a0_extcki_clk, +-}; +- +-static struct clk div6_clks[DIV6_NR] = { +- [DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0, +- vck_parent, ARRAY_SIZE(vck_parent), 12, 3), +- [DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0, +- vck_parent, ARRAY_SIZE(vck_parent), 12, 3), +- [DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0, +- vck_parent, ARRAY_SIZE(vck_parent), 12, 3), +- [DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT, +- pll_parent, ARRAY_SIZE(pll_parent), 7, 1), +- [DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0, +- pll_parent, ARRAY_SIZE(pll_parent), 7, 1), +- [DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0, +- pll_parent, ARRAY_SIZE(pll_parent), 6, 2), +- [DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0, +- pll_parent, ARRAY_SIZE(pll_parent), 6, 2), +- [DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0, +- pll_parent, ARRAY_SIZE(pll_parent), 6, 2), +- [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0, +- pll_parent, ARRAY_SIZE(pll_parent), 6, 1), +- [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0, +- pll_parent, ARRAY_SIZE(pll_parent), 6, 1), +- [DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0, +- pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2), +- [DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0, +- pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2), +- [DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0, +- pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2), +- [DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0, +- pll_parent, ARRAY_SIZE(pll_parent), 7, 1), +- [DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0, +- hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2), +- [DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0, +- pll_parent, ARRAY_SIZE(pll_parent), 7, 1), +- [DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0, +- pll_parent, ARRAY_SIZE(pll_parent), 7, 1), +- [DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0, +- pll_parent, ARRAY_SIZE(pll_parent), 7, 1), +- [DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0, +- dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3), +- [DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0, +- dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3), +-}; +- +-/* DSI DIV */ +-static unsigned long dsiphy_recalc(struct clk *clk) +-{ +- u32 value; +- +- value = __raw_readl(clk->mapping->base); +- +- /* FIXME */ +- if (!(value & 0x000B8000)) +- return clk->parent->rate; +- +- value &= 0x3f; +- value += 1; +- +- if ((value < 12) || +- (value > 33)) { +- pr_err("DSIPHY has wrong value (%d)", value); +- return 0; +- } +- +- return clk->parent->rate / value; +-} +- +-static long dsiphy_round_rate(struct clk *clk, unsigned long rate) +-{ +- return clk_rate_mult_range_round(clk, 12, 33, rate); +-} +- +-static void dsiphy_disable(struct clk *clk) +-{ +- u32 value; +- +- value = __raw_readl(clk->mapping->base); +- value &= ~0x000B8000; +- +- __raw_writel(value , clk->mapping->base); +-} +- +-static int dsiphy_enable(struct clk *clk) +-{ +- u32 value; +- int multi; +- +- value = __raw_readl(clk->mapping->base); +- multi = (value & 0x3f) + 1; +- +- if ((multi < 12) || (multi > 33)) +- return -EIO; +- +- __raw_writel(value | 0x000B8000, clk->mapping->base); +- +- return 0; +-} +- +-static int dsiphy_set_rate(struct clk *clk, unsigned long rate) +-{ +- u32 value; +- int idx; +- +- idx = rate / clk->parent->rate; +- if ((idx < 12) || (idx > 33)) +- return -EINVAL; +- +- idx += -1; +- +- value = __raw_readl(clk->mapping->base); +- value = (value & ~0x3f) + idx; +- +- __raw_writel(value, clk->mapping->base); +- +- return 0; +-} +- +-static struct sh_clk_ops dsiphy_clk_ops = { +- .recalc = dsiphy_recalc, +- .round_rate = dsiphy_round_rate, +- .set_rate = dsiphy_set_rate, +- .enable = dsiphy_enable, +- .disable = dsiphy_disable, +-}; +- +-static struct clk_mapping dsi0phy_clk_mapping = { +- .phys = DSI0PHYCR, +- .len = 4, +-}; +- +-static struct clk_mapping dsi1phy_clk_mapping = { +- .phys = DSI1PHYCR, +- .len = 4, +-}; +- +-static struct clk dsi0phy_clk = { +- .ops = &dsiphy_clk_ops, +- .parent = &div6_clks[DIV6_DSI0P], /* late install */ +- .mapping = &dsi0phy_clk_mapping, +-}; +- +-static struct clk dsi1phy_clk = { +- .ops = &dsiphy_clk_ops, +- .parent = &div6_clks[DIV6_DSI1P], /* late install */ +- .mapping = &dsi1phy_clk_mapping, +-}; +- +-static struct clk *late_main_clks[] = { +- &dsi0phy_clk, +- &dsi1phy_clk, +- &twd_clk, +-}; +- +-enum { MSTP001, +- MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100, +- MSTP219, MSTP218, MSTP217, +- MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, +- MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322, +- MSTP314, MSTP313, MSTP312, MSTP311, +- MSTP304, MSTP303, MSTP302, MSTP301, MSTP300, +- MSTP411, MSTP410, MSTP403, +- MSTP508, +- MSTP_NR }; +- +-#define MSTP(_parent, _reg, _bit, _flags) \ +- SH_CLK_MSTP32(_parent, _reg, _bit, _flags) +- +-static struct clk mstp_clks[MSTP_NR] = { +- [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */ +- [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* CEU1 */ +- [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* CSI2-RX1 */ +- [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU0 */ +- [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2-RX0 */ +- [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ +- [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */ +- [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */ +- [MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */ +- [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ +- [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */ +- [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */ +- [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* MP-DMAC */ +- [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ +- [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ +- [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ +- [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */ +- [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */ +- [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ +- [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ +- [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */ +- [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ +- [MSTP328] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /*FSI*/ +- [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */ +- [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ +- [MSTP322] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 22, 0), /* USB */ +- [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */ +- [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */ +- [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */ +- [MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */ +- [MSTP304] = MSTP(&main_div2_clk, SMSTPCR3, 4, 0), /* TPU0 */ +- [MSTP303] = MSTP(&main_div2_clk, SMSTPCR3, 3, 0), /* TPU1 */ +- [MSTP302] = MSTP(&main_div2_clk, SMSTPCR3, 2, 0), /* TPU2 */ +- [MSTP301] = MSTP(&main_div2_clk, SMSTPCR3, 1, 0), /* TPU3 */ +- [MSTP300] = MSTP(&main_div2_clk, SMSTPCR3, 0, 0), /* TPU4 */ +- [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */ +- [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */ +- [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ +- [MSTP508] = MSTP(&div4_clks[DIV4_HP], SMSTPCR5, 8, 0), /* INTCA0 */ +-}; +- +-/* The lookups structure below includes duplicate entries for some clocks +- * with alternate names. +- * - The traditional name used when a device is initialised with platform data +- * - The name used when a device is initialised using device tree +- * The longer-term aim is to remove these duplicates, and indeed the +- * lookups table entirely, by describing clocks using device tree. +- */ +-static struct clk_lookup lookups[] = { +- /* main clocks */ +- CLKDEV_CON_ID("r_clk", &r_clk), +- CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */ +- +- /* DIV4 clocks */ +- CLKDEV_DEV_ID("cpu0", &div4_clks[DIV4_Z]), +- +- /* DIV6 clocks */ +- CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), +- CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]), +- CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]), +- CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]), +- CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]), +- CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]), +- +- /* MSTP32 clocks */ +- CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ +- CLKDEV_DEV_ID("e6824000.i2c", &mstp_clks[MSTP001]), /* I2C2 */ +- CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */ +- CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */ +- CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */ +- CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */ +- CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */ +- CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */ +- CLKDEV_DEV_ID("e6820000.i2c", &mstp_clks[MSTP116]), /* I2C0 */ +- CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */ +- CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */ +- CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP219]), /* SCIFA7 */ +- CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */ +- CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* MP-DMAC */ +- CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ +- CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */ +- CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */ +- CLKDEV_DEV_ID("e6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */ +- CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ +- CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */ +- CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ +- CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]), /* SCIFA1 */ +- CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */ +- CLKDEV_DEV_ID("e6c60000.serial", &mstp_clks[MSTP202]), /* SCIFA2 */ +- CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ +- CLKDEV_DEV_ID("e6c70000.serial", &mstp_clks[MSTP201]), /* SCIFA3 */ +- CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ +- CLKDEV_DEV_ID("e6c80000.serial", &mstp_clks[MSTP200]), /* SCIFA4 */ +- CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ +- CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP331]), /* SCIFA6 */ +- CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */ +- CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */ +- CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ +- CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ +- CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ +- CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */ +- CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ +- CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), /* SDHI0 */ +- CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ +- CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), /* SDHI1 */ +- CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ +- CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]), /* MMCIF0 */ +- CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ +- CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP311]), /* SDHI2 */ +- CLKDEV_DEV_ID("renesas-tpu-pwm.0", &mstp_clks[MSTP304]), /* TPU0 */ +- CLKDEV_DEV_ID("renesas-tpu-pwm.1", &mstp_clks[MSTP303]), /* TPU1 */ +- CLKDEV_DEV_ID("renesas-tpu-pwm.2", &mstp_clks[MSTP302]), /* TPU2 */ +- CLKDEV_DEV_ID("renesas-tpu-pwm.3", &mstp_clks[MSTP301]), /* TPU3 */ +- CLKDEV_DEV_ID("renesas-tpu-pwm.4", &mstp_clks[MSTP300]), /* TPU4 */ +- CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */ +- CLKDEV_DEV_ID("e6826000.i2c", &mstp_clks[MSTP411]), /* I2C3 */ +- CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */ +- CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */ +- CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ +- CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP508]), /* INTCA0 */ +- CLKDEV_DEV_ID("e6900000.irqpin", &mstp_clks[MSTP508]), /* INTCA0 */ +- CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP508]), /* INTCA0 */ +- CLKDEV_DEV_ID("e6900004.irqpin", &mstp_clks[MSTP508]), /* INTCA0 */ +- CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP508]), /* INTCA0 */ +- CLKDEV_DEV_ID("e6900008.irqpin", &mstp_clks[MSTP508]), /* INTCA0 */ +- CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP508]), /* INTCA0 */ +- CLKDEV_DEV_ID("e690000c.irqpin", &mstp_clks[MSTP508]), /* INTCA0 */ +- +- /* ICK */ +- CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), +- CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), +- CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), +- CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), +- CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk), +- CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk), +- CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]), /* CMT1 */ +- CLKDEV_ICK_ID("fck", "e6138000.timer", &mstp_clks[MSTP329]), /* CMT1 */ +- CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), /* TMU0 */ +-}; +- +-void __init sh73a0_clock_init(void) +-{ +- int k, ret = 0; +- +- /* Set SDHI clocks to a known state */ +- __raw_writel(0x108, SD0CKCR); +- __raw_writel(0x108, SD1CKCR); +- __raw_writel(0x108, SD2CKCR); +- +- /* detect main clock parent */ +- switch ((__raw_readl(CKSCR) >> 28) & 0x03) { +- case 0: +- main_clk.parent = &sh73a0_extal1_clk; +- break; +- case 1: +- main_clk.parent = &extal1_div2_clk; +- break; +- case 2: +- main_clk.parent = &sh73a0_extal2_clk; +- break; +- case 3: +- main_clk.parent = &extal2_div2_clk; +- break; +- } +- +- for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) +- ret = clk_register(main_clks[k]); +- +- if (!ret) { +- ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); +- if (!ret) +- div4_clk_extend(); +- } +- +- if (!ret) +- ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); +- +- if (!ret) +- ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); +- +- for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) +- ret = clk_register(late_main_clks[k]); +- +- clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +- +- if (!ret) +- shmobile_clk_init(); +- else +- panic("failed to setup sh73a0 clocks\n"); +-} +diff --git a/arch/arm/mach-shmobile/pm-sh73a0.c b/arch/arm/mach-shmobile/pm-sh73a0.c +deleted file mode 100644 +index a7e466817965..000000000000 +--- a/arch/arm/mach-shmobile/pm-sh73a0.c ++++ /dev/null +@@ -1,32 +0,0 @@ +-/* +- * sh73a0 Power management support +- * +- * Copyright (C) 2012 Bastian Hecht <hechtb+renesas@gmail.com> +- * +- * This file is subject to the terms and conditions of the GNU General Public +- * License. See the file "COPYING" in the main directory of this archive +- * for more details. +- */ +- +-#include <linux/suspend.h> +-#include "common.h" +- +-#ifdef CONFIG_SUSPEND +-static int sh73a0_enter_suspend(suspend_state_t suspend_state) +-{ +- cpu_do_idle(); +- return 0; +-} +- +-static void sh73a0_suspend_init(void) +-{ +- shmobile_suspend_ops.enter = sh73a0_enter_suspend; +-} +-#else +-static void sh73a0_suspend_init(void) {} +-#endif +- +-void __init sh73a0_pm_init(void) +-{ +- sh73a0_suspend_init(); +-} +diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c +index fb2ab7590af8..a1e8e72e25b5 100644 +--- a/arch/arm/mach-shmobile/setup-sh73a0.c ++++ b/arch/arm/mach-shmobile/setup-sh73a0.c +@@ -18,28 +18,17 @@ + #include <linux/init.h> + #include <linux/interrupt.h> + #include <linux/irq.h> +-#include <linux/platform_device.h> + #include <linux/of_platform.h> + #include <linux/delay.h> + #include <linux/input.h> +-#include <linux/i2c/i2c-sh_mobile.h> + #include <linux/io.h> +-#include <linux/serial_sci.h> +-#include <linux/sh_dma.h> +-#include <linux/sh_timer.h> +-#include <linux/platform_data/sh_ipmmu.h> +-#include <linux/platform_data/irq-renesas-intc-irqpin.h> + + #include <asm/hardware/cache-l2x0.h> +-#include <asm/mach-types.h> + #include <asm/mach/map.h> + #include <asm/mach/arch.h> + #include <asm/mach/time.h> + + #include "common.h" +-#include "dma-register.h" +-#include "intc.h" +-#include "irqs.h" + #include "sh73a0.h" + + static struct map_desc sh73a0_io_desc[] __initdata = { +@@ -54,737 +43,12 @@ static struct map_desc sh73a0_io_desc[] __initdata = { + }, + }; + +-void __init sh73a0_map_io(void) ++static void __init sh73a0_map_io(void) + { + debug_ll_io_init(); + iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); + } + +-/* PFC */ +-static struct resource pfc_resources[] __initdata = { +- DEFINE_RES_MEM(0xe6050000, 0x8000), +- DEFINE_RES_MEM(0xe605801c, 0x000c), +-}; +- +-void __init sh73a0_pinmux_init(void) +-{ +- platform_device_register_simple("pfc-sh73a0", -1, pfc_resources, +- ARRAY_SIZE(pfc_resources)); +-} +- +-/* SCIF */ +-#define SH73A0_SCIF(scif_type, index, baseaddr, irq) \ +-static struct plat_sci_port scif##index##_platform_data = { \ +- .type = scif_type, \ +- .flags = UPF_BOOT_AUTOCONF, \ +- .scscr = SCSCR_RE | SCSCR_TE, \ +-}; \ +- \ +-static struct resource scif##index##_resources[] = { \ +- DEFINE_RES_MEM(baseaddr, 0x100), \ +- DEFINE_RES_IRQ(irq), \ +-}; \ +- \ +-static struct platform_device scif##index##_device = { \ +- .name = "sh-sci", \ +- .id = index, \ +- .resource = scif##index##_resources, \ +- .num_resources = ARRAY_SIZE(scif##index##_resources), \ +- .dev = { \ +- .platform_data = &scif##index##_platform_data, \ +- }, \ +-} +- +-SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72)); +-SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73)); +-SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74)); +-SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75)); +-SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78)); +-SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79)); +-SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156)); +-SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143)); +-SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80)); +- +-static struct sh_timer_config cmt1_platform_data = { +- .channels_mask = 0x3f, +-}; +- +-static struct resource cmt1_resources[] = { +- DEFINE_RES_MEM(0xe6138000, 0x200), +- DEFINE_RES_IRQ(gic_spi(65)), +-}; +- +-static struct platform_device cmt1_device = { +- .name = "sh-cmt-48", +- .id = 1, +- .dev = { +- .platform_data = &cmt1_platform_data, +- }, +- .resource = cmt1_resources, +- .num_resources = ARRAY_SIZE(cmt1_resources), +-}; +- +-/* TMU */ +-static struct sh_timer_config tmu0_platform_data = { +- .channels_mask = 7, +-}; +- +-static struct resource tmu0_resources[] = { +- DEFINE_RES_MEM(0xfff60000, 0x2c), +- DEFINE_RES_IRQ(intcs_evt2irq(0xe80)), +- DEFINE_RES_IRQ(intcs_evt2irq(0xea0)), +- DEFINE_RES_IRQ(intcs_evt2irq(0xec0)), +-}; +- +-static struct platform_device tmu0_device = { +- .name = "sh-tmu", +- .id = 0, +- .dev = { +- .platform_data = &tmu0_platform_data, +- }, +- .resource = tmu0_resources, +- .num_resources = ARRAY_SIZE(tmu0_resources), +-}; +- +-static struct resource i2c0_resources[] = { +- [0] = DEFINE_RES_MEM(0xe6820000, 0x426), +- [1] = { +- .start = gic_spi(167), +- .end = gic_spi(170), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct resource i2c1_resources[] = { +- [0] = DEFINE_RES_MEM(0xe6822000, 0x426), +- [1] = { +- .start = gic_spi(51), +- .end = gic_spi(54), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct resource i2c2_resources[] = { +- [0] = DEFINE_RES_MEM(0xe6824000, 0x426), +- [1] = { +- .start = gic_spi(171), +- .end = gic_spi(174), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct resource i2c3_resources[] = { +- [0] = DEFINE_RES_MEM(0xe6826000, 0x426), +- [1] = { +- .start = gic_spi(183), +- .end = gic_spi(186), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct resource i2c4_resources[] = { +- [0] = DEFINE_RES_MEM(0xe6828000, 0x426), +- [1] = { +- .start = gic_spi(187), +- .end = gic_spi(190), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct i2c_sh_mobile_platform_data i2c_platform_data = { +- .clks_per_count = 2, +-}; +- +-static struct platform_device i2c0_device = { +- .name = "i2c-sh_mobile", +- .id = 0, +- .resource = i2c0_resources, +- .num_resources = ARRAY_SIZE(i2c0_resources), +- .dev = { +- .platform_data = &i2c_platform_data, +- }, +-}; +- +-static struct platform_device i2c1_device = { +- .name = "i2c-sh_mobile", +- .id = 1, +- .resource = i2c1_resources, +- .num_resources = ARRAY_SIZE(i2c1_resources), +- .dev = { +- .platform_data = &i2c_platform_data, +- }, +-}; +- +-static struct platform_device i2c2_device = { +- .name = "i2c-sh_mobile", +- .id = 2, +- .resource = i2c2_resources, +- .num_resources = ARRAY_SIZE(i2c2_resources), +- .dev = { +- .platform_data = &i2c_platform_data, +- }, +-}; +- +-static struct platform_device i2c3_device = { +- .name = "i2c-sh_mobile", +- .id = 3, +- .resource = i2c3_resources, +- .num_resources = ARRAY_SIZE(i2c3_resources), +- .dev = { +- .platform_data = &i2c_platform_data, +- }, +-}; +- +-static struct platform_device i2c4_device = { +- .name = "i2c-sh_mobile", +- .id = 4, +- .resource = i2c4_resources, +- .num_resources = ARRAY_SIZE(i2c4_resources), +- .dev = { +- .platform_data = &i2c_platform_data, +- }, +-}; +- +-static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { +- { +- .slave_id = SHDMA_SLAVE_SCIF0_TX, +- .addr = 0xe6c40020, +- .chcr = CHCR_TX(XMIT_SZ_8BIT), +- .mid_rid = 0x21, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF0_RX, +- .addr = 0xe6c40024, +- .chcr = CHCR_RX(XMIT_SZ_8BIT), +- .mid_rid = 0x22, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF1_TX, +- .addr = 0xe6c50020, +- .chcr = CHCR_TX(XMIT_SZ_8BIT), +- .mid_rid = 0x25, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF1_RX, +- .addr = 0xe6c50024, +- .chcr = CHCR_RX(XMIT_SZ_8BIT), +- .mid_rid = 0x26, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF2_TX, +- .addr = 0xe6c60020, +- .chcr = CHCR_TX(XMIT_SZ_8BIT), +- .mid_rid = 0x29, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF2_RX, +- .addr = 0xe6c60024, +- .chcr = CHCR_RX(XMIT_SZ_8BIT), +- .mid_rid = 0x2a, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF3_TX, +- .addr = 0xe6c70020, +- .chcr = CHCR_TX(XMIT_SZ_8BIT), +- .mid_rid = 0x2d, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF3_RX, +- .addr = 0xe6c70024, +- .chcr = CHCR_RX(XMIT_SZ_8BIT), +- .mid_rid = 0x2e, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF4_TX, +- .addr = 0xe6c80020, +- .chcr = CHCR_TX(XMIT_SZ_8BIT), +- .mid_rid = 0x39, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF4_RX, +- .addr = 0xe6c80024, +- .chcr = CHCR_RX(XMIT_SZ_8BIT), +- .mid_rid = 0x3a, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF5_TX, +- .addr = 0xe6cb0020, +- .chcr = CHCR_TX(XMIT_SZ_8BIT), +- .mid_rid = 0x35, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF5_RX, +- .addr = 0xe6cb0024, +- .chcr = CHCR_RX(XMIT_SZ_8BIT), +- .mid_rid = 0x36, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF6_TX, +- .addr = 0xe6cc0020, +- .chcr = CHCR_TX(XMIT_SZ_8BIT), +- .mid_rid = 0x1d, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF6_RX, +- .addr = 0xe6cc0024, +- .chcr = CHCR_RX(XMIT_SZ_8BIT), +- .mid_rid = 0x1e, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF7_TX, +- .addr = 0xe6cd0020, +- .chcr = CHCR_TX(XMIT_SZ_8BIT), +- .mid_rid = 0x19, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF7_RX, +- .addr = 0xe6cd0024, +- .chcr = CHCR_RX(XMIT_SZ_8BIT), +- .mid_rid = 0x1a, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF8_TX, +- .addr = 0xe6c30040, +- .chcr = CHCR_TX(XMIT_SZ_8BIT), +- .mid_rid = 0x3d, +- }, { +- .slave_id = SHDMA_SLAVE_SCIF8_RX, +- .addr = 0xe6c30060, +- .chcr = CHCR_RX(XMIT_SZ_8BIT), +- .mid_rid = 0x3e, +- }, { +- .slave_id = SHDMA_SLAVE_SDHI0_TX, +- .addr = 0xee100030, +- .chcr = CHCR_TX(XMIT_SZ_16BIT), +- .mid_rid = 0xc1, +- }, { +- .slave_id = SHDMA_SLAVE_SDHI0_RX, +- .addr = 0xee100030, +- .chcr = CHCR_RX(XMIT_SZ_16BIT), +- .mid_rid = 0xc2, +- }, { +- .slave_id = SHDMA_SLAVE_SDHI1_TX, +- .addr = 0xee120030, +- .chcr = CHCR_TX(XMIT_SZ_16BIT), +- .mid_rid = 0xc9, +- }, { +- .slave_id = SHDMA_SLAVE_SDHI1_RX, +- .addr = 0xee120030, +- .chcr = CHCR_RX(XMIT_SZ_16BIT), +- .mid_rid = 0xca, +- }, { +- .slave_id = SHDMA_SLAVE_SDHI2_TX, +- .addr = 0xee140030, +- .chcr = CHCR_TX(XMIT_SZ_16BIT), +- .mid_rid = 0xcd, +- }, { +- .slave_id = SHDMA_SLAVE_SDHI2_RX, +- .addr = 0xee140030, +- .chcr = CHCR_RX(XMIT_SZ_16BIT), +- .mid_rid = 0xce, +- }, { +- .slave_id = SHDMA_SLAVE_MMCIF_TX, +- .addr = 0xe6bd0034, +- .chcr = CHCR_TX(XMIT_SZ_32BIT), +- .mid_rid = 0xd1, +- }, { +- .slave_id = SHDMA_SLAVE_MMCIF_RX, +- .addr = 0xe6bd0034, +- .chcr = CHCR_RX(XMIT_SZ_32BIT), +- .mid_rid = 0xd2, +- }, +-}; +- +-#define DMAE_CHANNEL(_offset) \ +- { \ +- .offset = _offset - 0x20, \ +- .dmars = _offset - 0x20 + 0x40, \ +- } +- +-static const struct sh_dmae_channel sh73a0_dmae_channels[] = { +- DMAE_CHANNEL(0x8000), +- DMAE_CHANNEL(0x8080), +- DMAE_CHANNEL(0x8100), +- DMAE_CHANNEL(0x8180), +- DMAE_CHANNEL(0x8200), +- DMAE_CHANNEL(0x8280), +- DMAE_CHANNEL(0x8300), +- DMAE_CHANNEL(0x8380), +- DMAE_CHANNEL(0x8400), +- DMAE_CHANNEL(0x8480), +- DMAE_CHANNEL(0x8500), +- DMAE_CHANNEL(0x8580), +- DMAE_CHANNEL(0x8600), +- DMAE_CHANNEL(0x8680), +- DMAE_CHANNEL(0x8700), +- DMAE_CHANNEL(0x8780), +- DMAE_CHANNEL(0x8800), +- DMAE_CHANNEL(0x8880), +- DMAE_CHANNEL(0x8900), +- DMAE_CHANNEL(0x8980), +-}; +- +-static struct sh_dmae_pdata sh73a0_dmae_platform_data = { +- .slave = sh73a0_dmae_slaves, +- .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves), +- .channel = sh73a0_dmae_channels, +- .channel_num = ARRAY_SIZE(sh73a0_dmae_channels), +- .ts_low_shift = TS_LOW_SHIFT, +- .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, +- .ts_high_shift = TS_HI_SHIFT, +- .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, +- .ts_shift = dma_ts_shift, +- .ts_shift_num = ARRAY_SIZE(dma_ts_shift), +- .dmaor_init = DMAOR_DME, +-}; +- +-static struct resource sh73a0_dmae_resources[] = { +- DEFINE_RES_MEM(0xfe000020, 0x89e0), +- { +- .name = "error_irq", +- .start = gic_spi(129), +- .end = gic_spi(129), +- .flags = IORESOURCE_IRQ, +- }, +- { +- /* IRQ for channels 0-19 */ +- .start = gic_spi(109), +- .end = gic_spi(128), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device dma0_device = { +- .name = "sh-dma-engine", +- .id = 0, +- .resource = sh73a0_dmae_resources, +- .num_resources = ARRAY_SIZE(sh73a0_dmae_resources), +- .dev = { +- .platform_data = &sh73a0_dmae_platform_data, +- }, +-}; +- +-/* MPDMAC */ +-static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = { +- { +- .slave_id = SHDMA_SLAVE_FSI2A_RX, +- .addr = 0xec230020, +- .chcr = CHCR_RX(XMIT_SZ_32BIT), +- .mid_rid = 0xd6, /* CHECK ME */ +- }, { +- .slave_id = SHDMA_SLAVE_FSI2A_TX, +- .addr = 0xec230024, +- .chcr = CHCR_TX(XMIT_SZ_32BIT), +- .mid_rid = 0xd5, /* CHECK ME */ +- }, { +- .slave_id = SHDMA_SLAVE_FSI2C_RX, +- .addr = 0xec230060, +- .chcr = CHCR_RX(XMIT_SZ_32BIT), +- .mid_rid = 0xda, /* CHECK ME */ +- }, { +- .slave_id = SHDMA_SLAVE_FSI2C_TX, +- .addr = 0xec230064, +- .chcr = CHCR_TX(XMIT_SZ_32BIT), +- .mid_rid = 0xd9, /* CHECK ME */ +- }, { +- .slave_id = SHDMA_SLAVE_FSI2B_RX, +- .addr = 0xec240020, +- .chcr = CHCR_RX(XMIT_SZ_32BIT), +- .mid_rid = 0x8e, /* CHECK ME */ +- }, { +- .slave_id = SHDMA_SLAVE_FSI2B_TX, +- .addr = 0xec240024, +- .chcr = CHCR_RX(XMIT_SZ_32BIT), +- .mid_rid = 0x8d, /* CHECK ME */ +- }, { +- .slave_id = SHDMA_SLAVE_FSI2D_RX, +- .addr = 0xec240060, +- .chcr = CHCR_RX(XMIT_SZ_32BIT), +- .mid_rid = 0x9a, /* CHECK ME */ +- }, +-}; +- +-#define MPDMA_CHANNEL(a, b, c) \ +-{ \ +- .offset = a, \ +- .dmars = b, \ +- .dmars_bit = c, \ +- .chclr_offset = (0x220 - 0x20) + a \ +-} +- +-static const struct sh_dmae_channel sh73a0_mpdma_channels[] = { +- MPDMA_CHANNEL(0x00, 0, 0), +- MPDMA_CHANNEL(0x10, 0, 8), +- MPDMA_CHANNEL(0x20, 4, 0), +- MPDMA_CHANNEL(0x30, 4, 8), +- MPDMA_CHANNEL(0x50, 8, 0), +- MPDMA_CHANNEL(0x70, 8, 8), +-}; +- +-static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { +- .slave = sh73a0_mpdma_slaves, +- .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves), +- .channel = sh73a0_mpdma_channels, +- .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels), +- .ts_low_shift = TS_LOW_SHIFT, +- .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, +- .ts_high_shift = TS_HI_SHIFT, +- .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, +- .ts_shift = dma_ts_shift, +- .ts_shift_num = ARRAY_SIZE(dma_ts_shift), +- .dmaor_init = DMAOR_DME, +- .chclr_present = 1, +-}; +- +-/* Resource order important! */ +-static struct resource sh73a0_mpdma_resources[] = { +- /* Channel registers and DMAOR */ +- DEFINE_RES_MEM(0xec618020, 0x270), +- /* DMARSx */ +- DEFINE_RES_MEM(0xec619000, 0xc), +- { +- .name = "error_irq", +- .start = gic_spi(181), +- .end = gic_spi(181), +- .flags = IORESOURCE_IRQ, +- }, +- { +- /* IRQ for channels 0-5 */ +- .start = gic_spi(175), +- .end = gic_spi(180), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device mpdma0_device = { +- .name = "sh-dma-engine", +- .id = 1, +- .resource = sh73a0_mpdma_resources, +- .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources), +- .dev = { +- .platform_data = &sh73a0_mpdma_platform_data, +- }, +-}; +- +-static struct resource pmu_resources[] = { +- [0] = { +- .start = gic_spi(55), +- .end = gic_spi(55), +- .flags = IORESOURCE_IRQ, +- }, +- [1] = { +- .start = gic_spi(56), +- .end = gic_spi(56), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device pmu_device = { +- .name = "armv7-pmu", +- .id = -1, +- .num_resources = ARRAY_SIZE(pmu_resources), +- .resource = pmu_resources, +-}; +- +-/* an IPMMU module for ICB */ +-static struct resource ipmmu_resources[] = { +- DEFINE_RES_MEM(0xfe951000, 0x100), +-}; +- +-static const char * const ipmmu_dev_names[] = { +- "sh_mobile_lcdc_fb.0", +-}; +- +-static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { +- .dev_names = ipmmu_dev_names, +- .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), +-}; +- +-static struct platform_device ipmmu_device = { +- .name = "ipmmu", +- .id = -1, +- .dev = { +- .platform_data = &ipmmu_platform_data, +- }, +- .resource = ipmmu_resources, +- .num_resources = ARRAY_SIZE(ipmmu_resources), +-}; +- +-static struct renesas_intc_irqpin_config irqpin0_platform_data = { +- .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ +- .control_parent = true, +-}; +- +-static struct resource irqpin0_resources[] = { +- DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ +- DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ +- DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ +- DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ +- DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ +- DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ +- DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ +- DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ +- DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ +- DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ +- DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ +- DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ +- DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ +-}; +- +-static struct platform_device irqpin0_device = { +- .name = "renesas_intc_irqpin", +- .id = 0, +- .resource = irqpin0_resources, +- .num_resources = ARRAY_SIZE(irqpin0_resources), +- .dev = { +- .platform_data = &irqpin0_platform_data, +- }, +-}; +- +-static struct renesas_intc_irqpin_config irqpin1_platform_data = { +- .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ +- .control_parent = true, /* Disable spurious IRQ10 */ +-}; +- +-static struct resource irqpin1_resources[] = { +- DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ +- DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ +- DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ +- DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ +- DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ +- DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */ +- DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */ +- DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */ +- DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */ +- DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */ +- DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */ +- DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */ +- DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */ +-}; +- +-static struct platform_device irqpin1_device = { +- .name = "renesas_intc_irqpin", +- .id = 1, +- .resource = irqpin1_resources, +- .num_resources = ARRAY_SIZE(irqpin1_resources), +- .dev = { +- .platform_data = &irqpin1_platform_data, +- }, +-}; +- +-static struct renesas_intc_irqpin_config irqpin2_platform_data = { +- .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ +- .control_parent = true, +-}; +- +-static struct resource irqpin2_resources[] = { +- DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ +- DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */ +- DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */ +- DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */ +- DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */ +- DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */ +- DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */ +- DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */ +- DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */ +- DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */ +- DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */ +- DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */ +- DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */ +-}; +- +-static struct platform_device irqpin2_device = { +- .name = "renesas_intc_irqpin", +- .id = 2, +- .resource = irqpin2_resources, +- .num_resources = ARRAY_SIZE(irqpin2_resources), +- .dev = { +- .platform_data = &irqpin2_platform_data, +- }, +-}; +- +-static struct renesas_intc_irqpin_config irqpin3_platform_data = { +- .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ +- .control_parent = true, +-}; +- +-static struct resource irqpin3_resources[] = { +- DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */ +- DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ +- DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ +- DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ +- DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ +- DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */ +- DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */ +- DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */ +- DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */ +- DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */ +- DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */ +- DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */ +- DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */ +-}; +- +-static struct platform_device irqpin3_device = { +- .name = "renesas_intc_irqpin", +- .id = 3, +- .resource = irqpin3_resources, +- .num_resources = ARRAY_SIZE(irqpin3_resources), +- .dev = { +- .platform_data = &irqpin3_platform_data, +- }, +-}; +- +-static struct platform_device *sh73a0_early_devices[] __initdata = { +- &scif0_device, +- &scif1_device, +- &scif2_device, +- &scif3_device, +- &scif4_device, +- &scif5_device, +- &scif6_device, +- &scif7_device, +- &scif8_device, +- &tmu0_device, +- &ipmmu_device, +- &cmt1_device, +-}; +- +-static struct platform_device *sh73a0_late_devices[] __initdata = { +- &i2c0_device, +- &i2c1_device, +- &i2c2_device, +- &i2c3_device, +- &i2c4_device, +- &dma0_device, +- &mpdma0_device, +- &pmu_device, +- &irqpin0_device, +- &irqpin1_device, +- &irqpin2_device, +- &irqpin3_device, +-}; +- +-#define SRCR2 IOMEM(0xe61580b0) +- +-void __init sh73a0_add_standard_devices(void) +-{ +- /* Clear software reset bit on SY-DMAC module */ +- __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); +- +- platform_add_devices(sh73a0_early_devices, +- ARRAY_SIZE(sh73a0_early_devices)); +- platform_add_devices(sh73a0_late_devices, +- ARRAY_SIZE(sh73a0_late_devices)); +-} +- +-/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ +-void __init __weak sh73a0_register_twd(void) { } +- +-void __init sh73a0_earlytimer_init(void) +-{ +- shmobile_init_delay(); +-#ifndef CONFIG_COMMON_CLK +- sh73a0_clock_init(); +-#endif +- shmobile_earlytimer_init(); +- sh73a0_register_twd(); +-} +- +-void __init sh73a0_add_early_devices(void) +-{ +- early_platform_add_devices(sh73a0_early_devices, +- ARRAY_SIZE(sh73a0_early_devices)); +- +- /* setup early console here as well */ +- shmobile_setup_console(); +-} +- +-#ifdef CONFIG_USE_OF +- + static void __init sh73a0_generic_init(void) + { + #ifdef CONFIG_CACHE_L2X0 +@@ -807,4 +71,3 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") + .init_late = shmobile_init_late, + .dt_compat = sh73a0_boards_compat_dt, + MACHINE_END +-#endif /* CONFIG_USE_OF */ +diff --git a/arch/arm/mach-shmobile/sh73a0.h b/arch/arm/mach-shmobile/sh73a0.h +index 5a80f18b4fa0..39646806cf64 100644 +--- a/arch/arm/mach-shmobile/sh73a0.h ++++ b/arch/arm/mach-shmobile/sh73a0.h +@@ -1,89 +1,6 @@ + #ifndef __ASM_SH73A0_H__ + #define __ASM_SH73A0_H__ + +-/* DMA slave IDs */ +-enum { +- SHDMA_SLAVE_INVALID, +- SHDMA_SLAVE_SCIF0_TX, +- SHDMA_SLAVE_SCIF0_RX, +- SHDMA_SLAVE_SCIF1_TX, +- SHDMA_SLAVE_SCIF1_RX, +- SHDMA_SLAVE_SCIF2_TX, +- SHDMA_SLAVE_SCIF2_RX, +- SHDMA_SLAVE_SCIF3_TX, +- SHDMA_SLAVE_SCIF3_RX, +- SHDMA_SLAVE_SCIF4_TX, +- SHDMA_SLAVE_SCIF4_RX, +- SHDMA_SLAVE_SCIF5_TX, +- SHDMA_SLAVE_SCIF5_RX, +- SHDMA_SLAVE_SCIF6_TX, +- SHDMA_SLAVE_SCIF6_RX, +- SHDMA_SLAVE_SCIF7_TX, +- SHDMA_SLAVE_SCIF7_RX, +- SHDMA_SLAVE_SCIF8_TX, +- SHDMA_SLAVE_SCIF8_RX, +- SHDMA_SLAVE_SDHI0_TX, +- SHDMA_SLAVE_SDHI0_RX, +- SHDMA_SLAVE_SDHI1_TX, +- SHDMA_SLAVE_SDHI1_RX, +- SHDMA_SLAVE_SDHI2_TX, +- SHDMA_SLAVE_SDHI2_RX, +- SHDMA_SLAVE_MMCIF_TX, +- SHDMA_SLAVE_MMCIF_RX, +- SHDMA_SLAVE_FSI2A_TX, +- SHDMA_SLAVE_FSI2A_RX, +- SHDMA_SLAVE_FSI2B_TX, +- SHDMA_SLAVE_FSI2B_RX, +- SHDMA_SLAVE_FSI2C_TX, +- SHDMA_SLAVE_FSI2C_RX, +- SHDMA_SLAVE_FSI2D_RX, +-}; +- +-/* +- * SH73A0 IRQ LOCATION TABLE +- * +- * 416 ----------------------------------------- +- * IRQ0-IRQ15 +- * 431 ----------------------------------------- +- * ... +- * 448 ----------------------------------------- +- * sh73a0-intcs +- * sh73a0-intca-irq-pins +- * 680 ----------------------------------------- +- * ... +- * 700 ----------------------------------------- +- * sh73a0-pint0 +- * 731 ----------------------------------------- +- * 732 ----------------------------------------- +- * sh73a0-pint1 +- * 739 ----------------------------------------- +- * ... +- * 800 ----------------------------------------- +- * IRQ16-IRQ31 +- * 815 ----------------------------------------- +- * ... +- * 928 ----------------------------------------- +- * sh73a0-intca-irq-pins +- * 943 ----------------------------------------- +- */ +- +-/* PINT interrupts are located at Linux IRQ 700 and up */ +-#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) +-#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) +- +-extern void sh73a0_init_irq(void); +-extern void sh73a0_init_irq_dt(void); +-extern void sh73a0_map_io(void); +-extern void sh73a0_earlytimer_init(void); +-extern void sh73a0_add_early_devices(void); +-extern void sh73a0_add_standard_devices(void); +-extern void sh73a0_clock_init(void); +-extern void sh73a0_pinmux_init(void); +-extern void sh73a0_pm_init(void); +-extern struct clk sh73a0_extal1_clk; +-extern struct clk sh73a0_extal2_clk; +-extern struct clk sh73a0_extcki_clk; +-extern struct clk sh73a0_extalr_clk; + extern struct smp_operations sh73a0_smp_ops; + + #endif /* __ASM_SH73A0_H__ */ +diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c +index 2106d6b76a06..d03aa11fb46d 100644 +--- a/arch/arm/mach-shmobile/smp-sh73a0.c ++++ b/arch/arm/mach-shmobile/smp-sh73a0.c +@@ -33,14 +33,6 @@ + + #define SH73A0_SCU_BASE 0xf0000000 + +-#if defined(CONFIG_HAVE_ARM_TWD) && !defined(CONFIG_ARCH_MULTIPLATFORM) +-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); +-void __init sh73a0_register_twd(void) +-{ +- twd_local_timer_register(&twd_local_timer); +-} +-#endif +- + static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) + { + unsigned int lcpu = cpu_logical_map(cpu); +-- +2.6.2 + diff --git a/patches.renesas/0150-ARM-shmobile-Remove-legacy-board-code-for-Armadillo-.patch b/patches.renesas/0150-ARM-shmobile-Remove-legacy-board-code-for-Armadillo-.patch new file mode 100644 index 00000000000000..16c3d237c29384 --- /dev/null +++ b/patches.renesas/0150-ARM-shmobile-Remove-legacy-board-code-for-Armadillo-.patch @@ -0,0 +1,1446 @@ +From d70869329e4608ec6351016075ef2567b377123f Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:31:21 +0200 +Subject: [PATCH 150/326] ARM: shmobile: Remove legacy board code for + Armadillo-800 EVA + +The Armadillo-800 EVA board is sufficiently supported by DT-based and +board-less R-Mobile A1 (r8a7740) multiplatform kernels, and board +staging code. Hence remove the legacy board code to reduce maintenance +effort. + +Lacking areas are: + - USB (it doesn't work in legacy, neither), + - HDMI (it doesn't work in legacy, neither), + - Camera (we don't care), + - DMAC/IPMMU (no DT bindings are planned). + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1fa59bda21c7fa3644e374be0547395975286599) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 9 - + arch/arm/mach-shmobile/Makefile | 1 - + arch/arm/mach-shmobile/Makefile.boot | 1 - + arch/arm/mach-shmobile/board-armadillo800eva.c | 1365 ------------------------ + 4 files changed, 1376 deletions(-) + delete mode 100644 arch/arm/mach-shmobile/board-armadillo800eva.c + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index c506be27b610..9e916fafc77d 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -126,15 +126,6 @@ config ARCH_R8A7779 + + comment "Renesas ARM SoCs Board Type" + +-config MACH_ARMADILLO800EVA +- bool "Armadillo-800 EVA board" +- depends on ARCH_R8A7740 +- select ARCH_REQUIRE_GPIOLIB +- select REGULATOR_FIXED_VOLTAGE if REGULATOR +- select SMSC_PHY if SH_ETH +- select SND_SOC_WM8978 if SND_SIMPLE_CARD && I2C +- select USE_OF +- + config MACH_BOCKW + bool "BOCK-W platform" + depends on ARCH_R8A7778 +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 28e0f05a8577..548536fcb3b1 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -56,7 +56,6 @@ else + obj-$(CONFIG_MACH_BOCKW) += board-bockw.o + obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o + obj-$(CONFIG_MACH_MARZEN) += board-marzen.o +-obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o + endif + + # Framework support +diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot +index 2269b1c3c30b..14cdfc0ed075 100644 +--- a/arch/arm/mach-shmobile/Makefile.boot ++++ b/arch/arm/mach-shmobile/Makefile.boot +@@ -1,6 +1,5 @@ + # per-board load address for uImage + loadaddr-y := +-loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 + loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 + loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 + loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 +diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c +deleted file mode 100644 +index bf37e3c532f6..000000000000 +--- a/arch/arm/mach-shmobile/board-armadillo800eva.c ++++ /dev/null +@@ -1,1365 +0,0 @@ +-/* +- * armadillo 800 eva board support +- * +- * Copyright (C) 2012 Renesas Solutions Corp. +- * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include <linux/clk.h> +-#include <linux/delay.h> +-#include <linux/err.h> +-#include <linux/gpio.h> +-#include <linux/gpio_keys.h> +-#include <linux/i2c-gpio.h> +-#include <linux/input.h> +-#include <linux/irq.h> +-#include <linux/kernel.h> +-#include <linux/mfd/tmio.h> +-#include <linux/mmc/host.h> +-#include <linux/mmc/sh_mmcif.h> +-#include <linux/mmc/sh_mobile_sdhi.h> +-#include <linux/pinctrl/machine.h> +-#include <linux/platform_data/st1232_pdata.h> +-#include <linux/platform_device.h> +-#include <linux/pwm.h> +-#include <linux/pwm_backlight.h> +-#include <linux/reboot.h> +-#include <linux/regulator/driver.h> +-#include <linux/regulator/fixed.h> +-#include <linux/regulator/gpio-regulator.h> +-#include <linux/regulator/machine.h> +-#include <linux/sh_eth.h> +-#include <linux/usb/renesas_usbhs.h> +-#include <linux/videodev2.h> +- +-#include <asm/hardware/cache-l2x0.h> +-#include <asm/mach-types.h> +-#include <asm/mach/arch.h> +-#include <asm/mach/map.h> +-#include <asm/mach/time.h> +-#include <asm/page.h> +-#include <media/mt9t112.h> +-#include <media/sh_mobile_ceu.h> +-#include <media/soc_camera.h> +-#include <sound/sh_fsi.h> +-#include <sound/simple_card.h> +-#include <video/sh_mobile_hdmi.h> +-#include <video/sh_mobile_lcdc.h> +- +-#include "common.h" +-#include "irqs.h" +-#include "pm-rmobile.h" +-#include "r8a7740.h" +-#include "sh-gpio.h" +- +-/* +- * CON1 Camera Module +- * CON2 Extension Bus +- * CON3 HDMI Output +- * CON4 Composite Video Output +- * CON5 H-UDI JTAG +- * CON6 ARM JTAG +- * CON7 SD1 +- * CON8 SD2 +- * CON9 RTC BackUp +- * CON10 Monaural Mic Input +- * CON11 Stereo Headphone Output +- * CON12 Audio Line Output(L) +- * CON13 Audio Line Output(R) +- * CON14 AWL13 Module +- * CON15 Extension +- * CON16 LCD1 +- * CON17 LCD2 +- * CON19 Power Input +- * CON20 USB1 +- * CON21 USB2 +- * CON22 Serial +- * CON23 LAN +- * CON24 USB3 +- * LED1 Camera LED(Yellow) +- * LED2 Power LED (Green) +- * ED3-LED6 User LED(Yellow) +- * LED7 LAN link LED(Green) +- * LED8 LAN activity LED(Yellow) +- */ +- +-/* +- * DipSwitch +- * +- * SW1 +- * +- * -12345678-+---------------+---------------------------- +- * 1 | boot | hermit +- * 0 | boot | OS auto boot +- * -12345678-+---------------+---------------------------- +- * 00 | boot device | eMMC +- * 10 | boot device | SDHI0 (CON7) +- * 01 | boot device | - +- * 11 | boot device | Extension Buss (CS0) +- * -12345678-+---------------+---------------------------- +- * 0 | Extension Bus | D8-D15 disable, eMMC enable +- * 1 | Extension Bus | D8-D15 enable, eMMC disable +- * -12345678-+---------------+---------------------------- +- * 0 | SDHI1 | COM8 disable, COM14 enable +- * 1 | SDHI1 | COM8 enable, COM14 disable +- * -12345678-+---------------+---------------------------- +- * 0 | USB0 | COM20 enable, COM24 disable +- * 1 | USB0 | COM20 disable, COM24 enable +- * -12345678-+---------------+---------------------------- +- * 00 | JTAG | SH-X2 +- * 10 | JTAG | ARM +- * 01 | JTAG | - +- * 11 | JTAG | Boundary Scan +- *-----------+---------------+---------------------------- +- */ +- +-/* +- * FSI-WM8978 +- * +- * this command is required when playback. +- * +- * # amixer set "Headphone" 50 +- * +- * this command is required when capture. +- * +- * # amixer set "Input PGA" 15 +- * # amixer set "Left Input Mixer MicP" on +- * # amixer set "Left Input Mixer MicN" on +- * # amixer set "Right Input Mixer MicN" on +- * # amixer set "Right Input Mixer MicP" on +- */ +- +-/* +- * USB function +- * +- * When you use USB Function, +- * set SW1.6 ON, and connect cable to CN24. +- * +- * USBF needs workaround on R8A7740 chip. +- * These are a little bit complex. +- * see +- * usbhsf_power_ctrl() +- */ +-#define IRQ7 irq_pin(7) +-#define USBCR1 IOMEM(0xe605810a) +-#define USBH 0xC6700000 +-#define USBH_USBCTR 0x10834 +- +-struct usbhsf_private { +- struct clk *phy; +- struct clk *usb24; +- struct clk *pci; +- struct clk *func; +- struct clk *host; +- void __iomem *usbh_base; +- struct renesas_usbhs_platform_info info; +-}; +- +-#define usbhsf_get_priv(pdev) \ +- container_of(renesas_usbhs_get_info(pdev), \ +- struct usbhsf_private, info) +- +-static int usbhsf_get_id(struct platform_device *pdev) +-{ +- return USBHS_GADGET; +-} +- +-static int usbhsf_power_ctrl(struct platform_device *pdev, +- void __iomem *base, int enable) +-{ +- struct usbhsf_private *priv = usbhsf_get_priv(pdev); +- +- /* +- * Work around for USB Function. +- * It needs USB host clock, and settings +- */ +- if (enable) { +- /* +- * enable all the related usb clocks +- * for usb workaround +- */ +- clk_enable(priv->usb24); +- clk_enable(priv->pci); +- clk_enable(priv->host); +- clk_enable(priv->func); +- clk_enable(priv->phy); +- +- /* +- * set USBCR1 +- * +- * Port1 is driven by USB function, +- * Port2 is driven by USB HOST +- * One HOST (Port1 or Port2 is HOST) +- * USB PLL input clock = 24MHz +- */ +- __raw_writew(0xd750, USBCR1); +- mdelay(1); +- +- /* +- * start USB Host +- */ +- __raw_writel(0x0000000c, priv->usbh_base + USBH_USBCTR); +- __raw_writel(0x00000008, priv->usbh_base + USBH_USBCTR); +- mdelay(10); +- +- /* +- * USB PHY Power ON +- */ +- __raw_writew(0xd770, USBCR1); +- __raw_writew(0x4000, base + 0x102); /* USBF :: SUSPMODE */ +- +- } else { +- __raw_writel(0x0000010f, priv->usbh_base + USBH_USBCTR); +- __raw_writew(0xd7c0, USBCR1); /* GPIO */ +- +- clk_disable(priv->phy); +- clk_disable(priv->func); /* usb work around */ +- clk_disable(priv->host); /* usb work around */ +- clk_disable(priv->pci); /* usb work around */ +- clk_disable(priv->usb24); /* usb work around */ +- } +- +- return 0; +-} +- +-static int usbhsf_get_vbus(struct platform_device *pdev) +-{ +- return gpio_get_value(209); +-} +- +-static irqreturn_t usbhsf_interrupt(int irq, void *data) +-{ +- struct platform_device *pdev = data; +- +- renesas_usbhs_call_notify_hotplug(pdev); +- +- return IRQ_HANDLED; +-} +- +-static int usbhsf_hardware_exit(struct platform_device *pdev) +-{ +- struct usbhsf_private *priv = usbhsf_get_priv(pdev); +- +- if (!IS_ERR(priv->phy)) +- clk_put(priv->phy); +- if (!IS_ERR(priv->usb24)) +- clk_put(priv->usb24); +- if (!IS_ERR(priv->pci)) +- clk_put(priv->pci); +- if (!IS_ERR(priv->host)) +- clk_put(priv->host); +- if (!IS_ERR(priv->func)) +- clk_put(priv->func); +- if (priv->usbh_base) +- iounmap(priv->usbh_base); +- +- priv->phy = NULL; +- priv->usb24 = NULL; +- priv->pci = NULL; +- priv->host = NULL; +- priv->func = NULL; +- priv->usbh_base = NULL; +- +- free_irq(IRQ7, pdev); +- +- return 0; +-} +- +-static int usbhsf_hardware_init(struct platform_device *pdev) +-{ +- struct usbhsf_private *priv = usbhsf_get_priv(pdev); +- int ret; +- +- priv->phy = clk_get(&pdev->dev, "phy"); +- priv->usb24 = clk_get(&pdev->dev, "usb24"); +- priv->pci = clk_get(&pdev->dev, "pci"); +- priv->func = clk_get(&pdev->dev, "func"); +- priv->host = clk_get(&pdev->dev, "host"); +- priv->usbh_base = ioremap_nocache(USBH, 0x20000); +- +- if (IS_ERR(priv->phy) || +- IS_ERR(priv->usb24) || +- IS_ERR(priv->pci) || +- IS_ERR(priv->host) || +- IS_ERR(priv->func) || +- !priv->usbh_base) { +- dev_err(&pdev->dev, "USB clock setting failed\n"); +- usbhsf_hardware_exit(pdev); +- return -EIO; +- } +- +- ret = request_irq(IRQ7, usbhsf_interrupt, IRQF_TRIGGER_NONE, +- dev_name(&pdev->dev), pdev); +- if (ret) { +- dev_err(&pdev->dev, "request_irq err\n"); +- return ret; +- } +- irq_set_irq_type(IRQ7, IRQ_TYPE_EDGE_BOTH); +- +- /* usb24 use 1/1 of parent clock (= usb24s = 24MHz) */ +- clk_set_rate(priv->usb24, +- clk_get_rate(clk_get_parent(priv->usb24))); +- +- return 0; +-} +- +-static struct usbhsf_private usbhsf_private = { +- .info = { +- .platform_callback = { +- .get_id = usbhsf_get_id, +- .get_vbus = usbhsf_get_vbus, +- .hardware_init = usbhsf_hardware_init, +- .hardware_exit = usbhsf_hardware_exit, +- .power_ctrl = usbhsf_power_ctrl, +- }, +- .driver_param = { +- .buswait_bwait = 5, +- .detection_delay = 5, +- .d0_rx_id = SHDMA_SLAVE_USBHS_RX, +- .d1_tx_id = SHDMA_SLAVE_USBHS_TX, +- }, +- } +-}; +- +-static struct resource usbhsf_resources[] = { +- { +- .name = "USBHS", +- .start = 0xe6890000, +- .end = 0xe6890104 - 1, +- .flags = IORESOURCE_MEM, +- }, +- { +- .start = gic_spi(51), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device usbhsf_device = { +- .name = "renesas_usbhs", +- .dev = { +- .platform_data = &usbhsf_private.info, +- }, +- .id = -1, +- .num_resources = ARRAY_SIZE(usbhsf_resources), +- .resource = usbhsf_resources, +-}; +- +-/* Ether */ +-static struct sh_eth_plat_data sh_eth_platdata = { +- .phy = 0x00, /* LAN8710A */ +- .edmac_endian = EDMAC_LITTLE_ENDIAN, +- .phy_interface = PHY_INTERFACE_MODE_MII, +-}; +- +-static struct resource sh_eth_resources[] = { +- { +- .start = 0xe9a00000, +- .end = 0xe9a00800 - 1, +- .flags = IORESOURCE_MEM, +- }, { +- .start = 0xe9a01800, +- .end = 0xe9a02000 - 1, +- .flags = IORESOURCE_MEM, +- }, { +- .start = gic_spi(110), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sh_eth_device = { +- .name = "r8a7740-gether", +- .id = -1, +- .dev = { +- .platform_data = &sh_eth_platdata, +- .dma_mask = &sh_eth_device.dev.coherent_dma_mask, +- .coherent_dma_mask = DMA_BIT_MASK(32), +- }, +- .resource = sh_eth_resources, +- .num_resources = ARRAY_SIZE(sh_eth_resources), +-}; +- +-/* PWM */ +-static struct resource pwm_resources[] = { +- [0] = { +- .start = 0xe6600000, +- .end = 0xe66000ff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device pwm_device = { +- .name = "renesas-tpu-pwm", +- .id = -1, +- .num_resources = ARRAY_SIZE(pwm_resources), +- .resource = pwm_resources, +-}; +- +-static struct pwm_lookup pwm_lookup[] = { +- PWM_LOOKUP("renesas-tpu-pwm", 2, "pwm-backlight.0", NULL, +- 33333, PWM_POLARITY_INVERSED), +-}; +- +-/* LCDC and backlight */ +-static struct platform_pwm_backlight_data pwm_backlight_data = { +- .lth_brightness = 50, +- .max_brightness = 255, +- .dft_brightness = 255, +- .pwm_period_ns = 33333, /* 30kHz */ +- .enable_gpio = 61, +-}; +- +-static struct platform_device pwm_backlight_device = { +- .name = "pwm-backlight", +- .dev = { +- .platform_data = &pwm_backlight_data, +- }, +-}; +- +-static struct fb_videomode lcdc0_mode = { +- .name = "AMPIER/AM-800480", +- .xres = 800, +- .yres = 480, +- .left_margin = 88, +- .right_margin = 40, +- .hsync_len = 128, +- .upper_margin = 20, +- .lower_margin = 5, +- .vsync_len = 5, +- .sync = 0, +-}; +- +-static struct sh_mobile_lcdc_info lcdc0_info = { +- .clock_source = LCDC_CLK_BUS, +- .ch[0] = { +- .chan = LCDC_CHAN_MAINLCD, +- .fourcc = V4L2_PIX_FMT_RGB565, +- .interface_type = RGB24, +- .clock_divider = 5, +- .flags = 0, +- .lcd_modes = &lcdc0_mode, +- .num_modes = 1, +- .panel_cfg = { +- .width = 111, +- .height = 68, +- }, +- }, +-}; +- +-static struct resource lcdc0_resources[] = { +- [0] = { +- .name = "LCD0", +- .start = 0xfe940000, +- .end = 0xfe943fff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(177), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device lcdc0_device = { +- .name = "sh_mobile_lcdc_fb", +- .num_resources = ARRAY_SIZE(lcdc0_resources), +- .resource = lcdc0_resources, +- .id = 0, +- .dev = { +- .platform_data = &lcdc0_info, +- .coherent_dma_mask = DMA_BIT_MASK(32), +- }, +-}; +- +-/* +- * LCDC1/HDMI +- */ +-static struct sh_mobile_hdmi_info hdmi_info = { +- .flags = HDMI_OUTPUT_PUSH_PULL | +- HDMI_OUTPUT_POLARITY_HI | +- HDMI_32BIT_REG | +- HDMI_HAS_HTOP1 | +- HDMI_SND_SRC_SPDIF, +-}; +- +-static struct resource hdmi_resources[] = { +- [0] = { +- .name = "HDMI", +- .start = 0xe6be0000, +- .end = 0xe6be03ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(131), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .name = "HDMI emma3pf", +- .start = 0xe6be4000, +- .end = 0xe6be43ff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device hdmi_device = { +- .name = "sh-mobile-hdmi", +- .num_resources = ARRAY_SIZE(hdmi_resources), +- .resource = hdmi_resources, +- .id = -1, +- .dev = { +- .platform_data = &hdmi_info, +- }, +-}; +- +-static const struct fb_videomode lcdc1_mode = { +- .name = "HDMI 720p", +- .xres = 1280, +- .yres = 720, +- .pixclock = 13468, +- .left_margin = 220, +- .right_margin = 110, +- .hsync_len = 40, +- .upper_margin = 20, +- .lower_margin = 5, +- .vsync_len = 5, +- .refresh = 60, +- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, +-}; +- +-static struct sh_mobile_lcdc_info hdmi_lcdc_info = { +- .clock_source = LCDC_CLK_PERIPHERAL, /* HDMI clock */ +- .ch[0] = { +- .chan = LCDC_CHAN_MAINLCD, +- .fourcc = V4L2_PIX_FMT_RGB565, +- .interface_type = RGB24, +- .clock_divider = 1, +- .flags = LCDC_FLAGS_DWPOL, +- .lcd_modes = &lcdc1_mode, +- .num_modes = 1, +- .tx_dev = &hdmi_device, +- .panel_cfg = { +- .width = 1280, +- .height = 720, +- }, +- }, +-}; +- +-static struct resource hdmi_lcdc_resources[] = { +- [0] = { +- .name = "LCDC1", +- .start = 0xfe944000, +- .end = 0xfe948000 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(178), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device hdmi_lcdc_device = { +- .name = "sh_mobile_lcdc_fb", +- .num_resources = ARRAY_SIZE(hdmi_lcdc_resources), +- .resource = hdmi_lcdc_resources, +- .id = 1, +- .dev = { +- .platform_data = &hdmi_lcdc_info, +- .coherent_dma_mask = DMA_BIT_MASK(32), +- }, +-}; +- +-/* LEDS */ +-static struct gpio_led gpio_leds[] = { +- { +- .name = "LED3", +- .gpio = 102, +- .default_state = LEDS_GPIO_DEFSTATE_ON, +- }, { +- .name = "LED4", +- .gpio = 111, +- .default_state = LEDS_GPIO_DEFSTATE_ON, +- }, { +- .name = "LED5", +- .gpio = 110, +- .default_state = LEDS_GPIO_DEFSTATE_ON, +- }, { +- .name = "LED6", +- .gpio = 177, +- .default_state = LEDS_GPIO_DEFSTATE_ON, +- }, +-}; +- +-static struct gpio_led_platform_data leds_gpio_info = { +- .leds = gpio_leds, +- .num_leds = ARRAY_SIZE(gpio_leds), +-}; +- +-static struct platform_device leds_gpio_device = { +- .name = "leds-gpio", +- .id = -1, +- .dev = { +- .platform_data = &leds_gpio_info, +- }, +-}; +- +-/* GPIO KEY */ +-#define GPIO_KEY(c, g, d, ...) \ +- { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ } +- +-static struct gpio_keys_button gpio_buttons[] = { +- GPIO_KEY(KEY_POWER, 99, "SW3", .wakeup = 1), +- GPIO_KEY(KEY_BACK, 100, "SW4"), +- GPIO_KEY(KEY_MENU, 97, "SW5"), +- GPIO_KEY(KEY_HOME, 98, "SW6"), +-}; +- +-static struct gpio_keys_platform_data gpio_key_info = { +- .buttons = gpio_buttons, +- .nbuttons = ARRAY_SIZE(gpio_buttons), +-}; +- +-static struct platform_device gpio_keys_device = { +- .name = "gpio-keys", +- .id = -1, +- .dev = { +- .platform_data = &gpio_key_info, +- }, +-}; +- +-/* Fixed 3.3V regulator to be used by SDHI1, MMCIF */ +-static struct regulator_consumer_supply fixed3v3_power_consumers[] = { +- REGULATOR_SUPPLY("vmmc", "sh_mmcif"), +- REGULATOR_SUPPLY("vqmmc", "sh_mmcif"), +-}; +- +-/* Fixed 3.3V regulator used by LCD backlight */ +-static struct regulator_consumer_supply fixed5v0_power_consumers[] = { +- REGULATOR_SUPPLY("power", "pwm-backlight.0"), +-}; +- +-/* Fixed 3.3V regulator to be used by SDHI0 */ +-static struct regulator_consumer_supply vcc_sdhi0_consumers[] = { +- REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), +-}; +- +-static struct regulator_init_data vcc_sdhi0_init_data = { +- .constraints = { +- .valid_ops_mask = REGULATOR_CHANGE_STATUS, +- }, +- .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers), +- .consumer_supplies = vcc_sdhi0_consumers, +-}; +- +-static struct fixed_voltage_config vcc_sdhi0_info = { +- .supply_name = "SDHI0 Vcc", +- .microvolts = 3300000, +- .gpio = 75, +- .enable_high = 1, +- .init_data = &vcc_sdhi0_init_data, +-}; +- +-static struct platform_device vcc_sdhi0 = { +- .name = "reg-fixed-voltage", +- .id = 1, +- .dev = { +- .platform_data = &vcc_sdhi0_info, +- }, +-}; +- +-/* 1.8 / 3.3V SDHI0 VccQ regulator */ +-static struct regulator_consumer_supply vccq_sdhi0_consumers[] = { +- REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +-}; +- +-static struct regulator_init_data vccq_sdhi0_init_data = { +- .constraints = { +- .input_uV = 3300000, +- .min_uV = 1800000, +- .max_uV = 3300000, +- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | +- REGULATOR_CHANGE_STATUS, +- }, +- .num_consumer_supplies = ARRAY_SIZE(vccq_sdhi0_consumers), +- .consumer_supplies = vccq_sdhi0_consumers, +-}; +- +-static struct gpio vccq_sdhi0_gpios[] = { +- {17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" }, +-}; +- +-static struct gpio_regulator_state vccq_sdhi0_states[] = { +- { .value = 3300000, .gpios = (0 << 0) }, +- { .value = 1800000, .gpios = (1 << 0) }, +-}; +- +-static struct gpio_regulator_config vccq_sdhi0_info = { +- .supply_name = "vqmmc", +- +- .enable_gpio = 74, +- .enable_high = 1, +- .enabled_at_boot = 0, +- +- .gpios = vccq_sdhi0_gpios, +- .nr_gpios = ARRAY_SIZE(vccq_sdhi0_gpios), +- +- .states = vccq_sdhi0_states, +- .nr_states = ARRAY_SIZE(vccq_sdhi0_states), +- +- .type = REGULATOR_VOLTAGE, +- .init_data = &vccq_sdhi0_init_data, +-}; +- +-static struct platform_device vccq_sdhi0 = { +- .name = "gpio-regulator", +- .id = -1, +- .dev = { +- .platform_data = &vccq_sdhi0_info, +- }, +-}; +- +-/* Fixed 3.3V regulator to be used by SDHI1 */ +-static struct regulator_consumer_supply vcc_sdhi1_consumers[] = { +- REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), +-}; +- +-static struct regulator_init_data vcc_sdhi1_init_data = { +- .constraints = { +- .valid_ops_mask = REGULATOR_CHANGE_STATUS, +- }, +- .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi1_consumers), +- .consumer_supplies = vcc_sdhi1_consumers, +-}; +- +-static struct fixed_voltage_config vcc_sdhi1_info = { +- .supply_name = "SDHI1 Vcc", +- .microvolts = 3300000, +- .gpio = 16, +- .enable_high = 1, +- .init_data = &vcc_sdhi1_init_data, +-}; +- +-static struct platform_device vcc_sdhi1 = { +- .name = "reg-fixed-voltage", +- .id = 2, +- .dev = { +- .platform_data = &vcc_sdhi1_info, +- }, +-}; +- +-/* SDHI0 */ +-static struct tmio_mmc_data sdhi0_info = { +- .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX, +- .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX, +- .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | +- MMC_CAP_POWER_OFF_CARD, +- .flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, +- .cd_gpio = 167, +-}; +- +-static struct resource sdhi0_resources[] = { +- { +- .name = "SDHI0", +- .start = 0xe6850000, +- .end = 0xe6850100 - 1, +- .flags = IORESOURCE_MEM, +- }, +- /* +- * no SH_MOBILE_SDHI_IRQ_CARD_DETECT here +- */ +- { +- .name = SH_MOBILE_SDHI_IRQ_SDCARD, +- .start = gic_spi(118), +- .flags = IORESOURCE_IRQ, +- }, +- { +- .name = SH_MOBILE_SDHI_IRQ_SDIO, +- .start = gic_spi(119), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sdhi0_device = { +- .name = "sh_mobile_sdhi", +- .id = 0, +- .dev = { +- .platform_data = &sdhi0_info, +- }, +- .num_resources = ARRAY_SIZE(sdhi0_resources), +- .resource = sdhi0_resources, +-}; +- +-/* SDHI1 */ +-static struct tmio_mmc_data sdhi1_info = { +- .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI1_TX, +- .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI1_RX, +- .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | +- MMC_CAP_POWER_OFF_CARD, +- .flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, +- /* Port72 cannot generate IRQs, will be used in polling mode. */ +- .cd_gpio = 72, +-}; +- +-static struct resource sdhi1_resources[] = { +- [0] = { +- .name = "SDHI1", +- .start = 0xe6860000, +- .end = 0xe6860100 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(121), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- .start = gic_spi(122), +- .flags = IORESOURCE_IRQ, +- }, +- [3] = { +- .start = gic_spi(123), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sdhi1_device = { +- .name = "sh_mobile_sdhi", +- .id = 1, +- .dev = { +- .platform_data = &sdhi1_info, +- }, +- .num_resources = ARRAY_SIZE(sdhi1_resources), +- .resource = sdhi1_resources, +-}; +- +-static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = { +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", +- "sdhi1_data4", "sdhi1"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", +- "sdhi1_ctrl", "sdhi1"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", +- "sdhi1_cd", "sdhi1"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", +- "sdhi1_wp", "sdhi1"), +-}; +- +-/* MMCIF */ +-static struct sh_mmcif_plat_data sh_mmcif_plat = { +- .sup_pclk = 0, +- .caps = MMC_CAP_4_BIT_DATA | +- MMC_CAP_8_BIT_DATA | +- MMC_CAP_NONREMOVABLE, +- .ccs_unsupported = true, +- .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, +- .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, +-}; +- +-static struct resource sh_mmcif_resources[] = { +- [0] = { +- .name = "MMCIF", +- .start = 0xe6bd0000, +- .end = 0xe6bd0100 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- /* MMC ERR */ +- .start = gic_spi(56), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- /* MMC NOR */ +- .start = gic_spi(57), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sh_mmcif_device = { +- .name = "sh_mmcif", +- .id = -1, +- .dev = { +- .platform_data = &sh_mmcif_plat, +- }, +- .num_resources = ARRAY_SIZE(sh_mmcif_resources), +- .resource = sh_mmcif_resources, +-}; +- +-/* Camera */ +-static int mt9t111_power(struct device *dev, int mode) +-{ +- struct clk *mclk = clk_get(NULL, "video1"); +- +- if (IS_ERR(mclk)) { +- dev_err(dev, "can't get video1 clock\n"); +- return -EINVAL; +- } +- +- if (mode) { +- /* video1 (= CON1 camera) expect 24MHz */ +- clk_set_rate(mclk, clk_round_rate(mclk, 24000000)); +- clk_enable(mclk); +- gpio_set_value(158, 1); +- } else { +- gpio_set_value(158, 0); +- clk_disable(mclk); +- } +- +- clk_put(mclk); +- +- return 0; +-} +- +-static struct i2c_board_info i2c_camera_mt9t111 = { +- I2C_BOARD_INFO("mt9t112", 0x3d), +-}; +- +-static struct mt9t112_camera_info mt9t111_info = { +- .divider = { 16, 0, 0, 7, 0, 10, 14, 7, 7 }, +-}; +- +-static struct soc_camera_link mt9t111_link = { +- .i2c_adapter_id = 0, +- .bus_id = 0, +- .board_info = &i2c_camera_mt9t111, +- .power = mt9t111_power, +- .priv = &mt9t111_info, +-}; +- +-static struct platform_device camera_device = { +- .name = "soc-camera-pdrv", +- .id = 0, +- .dev = { +- .platform_data = &mt9t111_link, +- }, +-}; +- +-/* CEU0 */ +-static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { +- .flags = SH_CEU_FLAG_LOWER_8BIT, +-}; +- +-static struct resource ceu0_resources[] = { +- [0] = { +- .name = "CEU", +- .start = 0xfe910000, +- .end = 0xfe91009f, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(160), +- .flags = IORESOURCE_IRQ, +- }, +- [2] = { +- /* place holder for contiguous memory */ +- }, +-}; +- +-static struct platform_device ceu0_device = { +- .name = "sh_mobile_ceu", +- .id = 0, +- .num_resources = ARRAY_SIZE(ceu0_resources), +- .resource = ceu0_resources, +- .dev = { +- .platform_data = &sh_mobile_ceu0_info, +- .coherent_dma_mask = 0xffffffff, +- }, +-}; +- +-/* FSI */ +-static struct sh_fsi_platform_info fsi_info = { +- /* FSI-WM8978 */ +- .port_a = { +- .tx_id = SHDMA_SLAVE_FSIA_TX, +- }, +- /* FSI-HDMI */ +- .port_b = { +- .flags = SH_FSI_FMT_SPDIF | +- SH_FSI_ENABLE_STREAM_MODE | +- SH_FSI_CLK_CPG, +- .tx_id = SHDMA_SLAVE_FSIB_TX, +- } +-}; +- +-static struct resource fsi_resources[] = { +- [0] = { +- .name = "FSI", +- .start = 0xfe1f0000, +- .end = 0xfe1f0400 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(9), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device fsi_device = { +- .name = "sh_fsi2", +- .id = -1, +- .num_resources = ARRAY_SIZE(fsi_resources), +- .resource = fsi_resources, +- .dev = { +- .platform_data = &fsi_info, +- }, +-}; +- +-/* FSI-WM8978 */ +-static struct asoc_simple_card_info fsi_wm8978_info = { +- .name = "wm8978", +- .card = "FSI2A-WM8978", +- .codec = "wm8978.0-001a", +- .platform = "sh_fsi2", +- .daifmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, +- .cpu_dai = { +- .name = "fsia-dai", +- }, +- .codec_dai = { +- .name = "wm8978-hifi", +- .sysclk = 12288000, +- }, +-}; +- +-static struct platform_device fsi_wm8978_device = { +- .name = "asoc-simple-card", +- .id = 0, +- .dev = { +- .platform_data = &fsi_wm8978_info, +- .coherent_dma_mask = DMA_BIT_MASK(32), +- .dma_mask = &fsi_wm8978_device.dev.coherent_dma_mask, +- }, +-}; +- +-/* FSI-HDMI */ +-static struct asoc_simple_card_info fsi2_hdmi_info = { +- .name = "HDMI", +- .card = "FSI2B-HDMI", +- .codec = "sh-mobile-hdmi", +- .platform = "sh_fsi2", +- .daifmt = SND_SOC_DAIFMT_CBS_CFS, +- .cpu_dai = { +- .name = "fsib-dai", +- }, +- .codec_dai = { +- .name = "sh_mobile_hdmi-hifi", +- }, +-}; +- +-static struct platform_device fsi_hdmi_device = { +- .name = "asoc-simple-card", +- .id = 1, +- .dev = { +- .platform_data = &fsi2_hdmi_info, +- .coherent_dma_mask = DMA_BIT_MASK(32), +- .dma_mask = &fsi_hdmi_device.dev.coherent_dma_mask, +- }, +-}; +- +-/* RTC: RTC connects i2c-gpio. */ +-static struct i2c_gpio_platform_data i2c_gpio_data = { +- .sda_pin = 208, +- .scl_pin = 91, +- .udelay = 5, /* 100 kHz */ +-}; +- +-static struct platform_device i2c_gpio_device = { +- .name = "i2c-gpio", +- .id = 2, +- .dev = { +- .platform_data = &i2c_gpio_data, +- }, +-}; +- +-/* I2C */ +-static struct st1232_pdata st1232_i2c0_pdata = { +- .reset_gpio = 166, +-}; +- +-static struct i2c_board_info i2c0_devices[] = { +- { +- I2C_BOARD_INFO("st1232-ts", 0x55), +- .irq = irq_pin(10), +- .platform_data = &st1232_i2c0_pdata, +- }, +- { +- I2C_BOARD_INFO("wm8978", 0x1a), +- }, +-}; +- +-static struct i2c_board_info i2c2_devices[] = { +- { +- I2C_BOARD_INFO("s35390a", 0x30), +- .type = "s35390a", +- }, +-}; +- +-/* +- * board devices +- */ +-static struct platform_device *eva_devices[] __initdata = { +- &lcdc0_device, +- &pwm_device, +- &pwm_backlight_device, +- &leds_gpio_device, +- &gpio_keys_device, +- &sh_eth_device, +- &vcc_sdhi0, +- &vccq_sdhi0, +- &sdhi0_device, +- &sh_mmcif_device, +- &hdmi_device, +- &hdmi_lcdc_device, +- &camera_device, +- &ceu0_device, +- &fsi_device, +- &fsi_wm8978_device, +- &fsi_hdmi_device, +- &i2c_gpio_device, +-}; +- +-static const struct pinctrl_map eva_pinctrl_map[] = { +- /* CEU0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", +- "ceu0_data_0_7", "ceu0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", +- "ceu0_clk_0", "ceu0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", +- "ceu0_sync", "ceu0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", +- "ceu0_field", "ceu0"), +- /* FSIA */ +- PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", +- "fsia_sclk_in", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", +- "fsia_mclk_out", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", +- "fsia_data_in_1", "fsia"), +- PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", +- "fsia_data_out_0", "fsia"), +- /* FSIB */ +- PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740", +- "fsib_mclk_in", "fsib"), +- /* GETHER */ +- PIN_MAP_MUX_GROUP_DEFAULT("r8a7740-gether", "pfc-r8a7740", +- "gether_mii", "gether"), +- PIN_MAP_MUX_GROUP_DEFAULT("r8a7740-gether", "pfc-r8a7740", +- "gether_int", "gether"), +- /* HDMI */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740", +- "hdmi", "hdmi"), +- /* LCD0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", +- "lcd0_data24_0", "lcd0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", +- "lcd0_lclk_1", "lcd0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", +- "lcd0_sync", "lcd0"), +- /* MMCIF */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740", +- "mmc0_data8_1", "mmc0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740", +- "mmc0_ctrl_1", "mmc0"), +- /* SCIFA1 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740", +- "scifa1_data", "scifa1"), +- /* SDHI0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", +- "sdhi0_data4", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", +- "sdhi0_ctrl", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", +- "sdhi0_wp", "sdhi0"), +- /* ST1232 */ +- PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740", +- "intc_irq10", "intc"), +- /* TPU0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("renesas-tpu-pwm", "pfc-r8a7740", +- "tpu0_to2_1", "tpu0"), +- /* USBHS */ +- PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740", +- "intc_irq7_1", "intc"), +-}; +- +-static void __init eva_clock_init(void) +-{ +- struct clk *system = clk_get(NULL, "system_clk"); +- struct clk *xtal1 = clk_get(NULL, "extal1"); +- struct clk *usb24s = clk_get(NULL, "usb24s"); +- struct clk *fsibck = clk_get(NULL, "fsibck"); +- +- if (IS_ERR(system) || +- IS_ERR(xtal1) || +- IS_ERR(usb24s) || +- IS_ERR(fsibck)) { +- pr_err("armadillo800eva board clock init failed\n"); +- goto clock_error; +- } +- +- /* armadillo 800 eva extal1 is 24MHz */ +- clk_set_rate(xtal1, 24000000); +- +- /* usb24s use extal1 (= system) clock (= 24MHz) */ +- clk_set_parent(usb24s, system); +- +- /* FSIBCK is 12.288MHz, and it is parent of FSI-B */ +- clk_set_rate(fsibck, 12288000); +- +-clock_error: +- if (!IS_ERR(system)) +- clk_put(system); +- if (!IS_ERR(xtal1)) +- clk_put(xtal1); +- if (!IS_ERR(usb24s)) +- clk_put(usb24s); +- if (!IS_ERR(fsibck)) +- clk_put(fsibck); +-} +- +-/* +- * board init +- */ +-#define GPIO_PORT7CR IOMEM(0xe6050007) +-#define GPIO_PORT8CR IOMEM(0xe6050008) +-static void __init eva_init(void) +-{ +- static struct pm_domain_device domain_devices[] __initdata = { +- { "A4LC", &lcdc0_device }, +- { "A4LC", &hdmi_lcdc_device }, +- { "A4MP", &hdmi_device }, +- { "A4MP", &fsi_device }, +- { "A4R", &ceu0_device }, +- { "A4S", &sh_eth_device }, +- { "A3SP", &pwm_device }, +- { "A3SP", &sdhi0_device }, +- { "A3SP", &sh_mmcif_device }, +- }; +- struct platform_device *usb = NULL, *sdhi1 = NULL; +- +- regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, +- ARRAY_SIZE(fixed3v3_power_consumers), 3300000); +- regulator_register_always_on(3, "fixed-5.0V", fixed5v0_power_consumers, +- ARRAY_SIZE(fixed5v0_power_consumers), 5000000); +- +- pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map)); +- pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup)); +- +- r8a7740_pinmux_init(); +- r8a7740_meram_workaround(); +- +- /* GETHER */ +- gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ +- +- /* USB */ +- gpio_request_one(159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */ +- +- if (gpio_get_value(159)) { +- /* USB Host */ +- } else { +- /* USB Func */ +- /* +- * The USBHS interrupt handlers needs to read the IRQ pin value +- * (HI/LOW) to diffentiate USB connection and disconnection +- * events (usbhsf_get_vbus()). We thus need to select both the +- * intc_irq7_1 pin group and GPIO 209 here. +- */ +- gpio_request_one(209, GPIOF_IN, NULL); +- +- platform_device_register(&usbhsf_device); +- usb = &usbhsf_device; +- } +- +- /* CON1/CON15 Camera */ +- gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */ +- gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */ +- /* see mt9t111_power() */ +- gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */ +- +- /* FSI-WM8978 */ +- gpio_request(7, NULL); +- gpio_request(8, NULL); +- gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */ +- gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */ +- +- /* +- * CAUTION +- * +- * DBGMD/LCDC0/FSIA MUX +- * DBGMD_SELECT_B should be set after setting PFC Function. +- */ +- gpio_request_one(176, GPIOF_OUT_INIT_HIGH, NULL); +- +- /* +- * We can switch CON8/CON14 by SW1.5, +- * but it needs after DBGMD_SELECT_B +- */ +- gpio_request_one(6, GPIOF_IN, NULL); +- if (gpio_get_value(6)) { +- /* CON14 enable */ +- } else { +- /* CON8 (SDHI1) enable */ +- pinctrl_register_mappings(eva_sdhi1_pinctrl_map, +- ARRAY_SIZE(eva_sdhi1_pinctrl_map)); +- +- platform_device_register(&vcc_sdhi1); +- platform_device_register(&sdhi1_device); +- sdhi1 = &sdhi1_device; +- } +- +- +-#ifdef CONFIG_CACHE_L2X0 +- /* Shared attribute override enable, 32K*8way */ +- l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff); +-#endif +- +- i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); +- i2c_register_board_info(2, i2c2_devices, ARRAY_SIZE(i2c2_devices)); +- +- r8a7740_add_standard_devices(); +- +- platform_add_devices(eva_devices, +- ARRAY_SIZE(eva_devices)); +- +- rmobile_add_devices_to_domains(domain_devices, +- ARRAY_SIZE(domain_devices)); +- if (usb) +- rmobile_add_device_to_domain("A3SP", usb); +- if (sdhi1) +- rmobile_add_device_to_domain("A3SP", sdhi1); +- +- r8a7740_pm_init(); +-} +- +-static void __init eva_earlytimer_init(void) +-{ +- r8a7740_clock_init(MD_CK0 | MD_CK2); +- shmobile_earlytimer_init(); +- +- /* the rate of extal1 clock must be set before late_time_init */ +- eva_clock_init(); +-} +- +-#define RESCNT2 IOMEM(0xe6188020) +-static void eva_restart(enum reboot_mode mode, const char *cmd) +-{ +- /* Do soft power on reset */ +- writel((1 << 31), RESCNT2); +-} +- +-static const char *eva_boards_compat_dt[] __initdata = { +- "renesas,armadillo800eva", +- NULL, +-}; +- +-DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva") +- .map_io = r8a7740_map_io, +- .init_early = r8a7740_add_early_devices, +- .init_irq = r8a7740_init_irq_of, +- .init_machine = eva_init, +- .init_late = shmobile_init_late, +- .init_time = eva_earlytimer_init, +- .dt_compat = eva_boards_compat_dt, +- .restart = eva_restart, +-MACHINE_END +-- +2.6.2 + diff --git a/patches.renesas/0151-ARM-shmobile-Remove-legacy-armadillo800eva_defconfig.patch b/patches.renesas/0151-ARM-shmobile-Remove-legacy-armadillo800eva_defconfig.patch new file mode 100644 index 00000000000000..32be4b1c664de8 --- /dev/null +++ b/patches.renesas/0151-ARM-shmobile-Remove-legacy-armadillo800eva_defconfig.patch @@ -0,0 +1,201 @@ +From e0fce73651e512a9d208ef0c044679dc63d230ad Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:31:22 +0200 +Subject: [PATCH 151/326] ARM: shmobile: Remove legacy + armadillo800eva_defconfig + +The legacy board code for Armadillo-800 EVA has been removed. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 4e7115ad44d544847a294d7d634f5974e344708e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + MAINTAINERS | 1 - + arch/arm/configs/armadillo800eva_defconfig | 162 ----------------------------- + 2 files changed, 163 deletions(-) + delete mode 100644 arch/arm/configs/armadillo800eva_defconfig + +diff --git a/MAINTAINERS b/MAINTAINERS +index 77edd4bec210..b4d93bf4be0c 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -1440,7 +1440,6 @@ F: arch/arm/boot/dts/emev2* + F: arch/arm/boot/dts/r7s* + F: arch/arm/boot/dts/r8a* + F: arch/arm/boot/dts/sh* +-F: arch/arm/configs/armadillo800eva_defconfig + F: arch/arm/configs/bockw_defconfig + F: arch/arm/configs/marzen_defconfig + F: arch/arm/configs/shmobile_defconfig +diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig +deleted file mode 100644 +index 5666e3700a82..000000000000 +--- a/arch/arm/configs/armadillo800eva_defconfig ++++ /dev/null +@@ -1,162 +0,0 @@ +-CONFIG_EXPERIMENTAL=y +-CONFIG_SYSVIPC=y +-CONFIG_IKCONFIG=y +-CONFIG_IKCONFIG_PROC=y +-CONFIG_LOG_BUF_SHIFT=16 +-# CONFIG_UTS_NS is not set +-# CONFIG_IPC_NS is not set +-# CONFIG_PID_NS is not set +-CONFIG_CC_OPTIMIZE_FOR_SIZE=y +-CONFIG_PERF_EVENTS=y +-CONFIG_SLAB=y +-CONFIG_MODULES=y +-CONFIG_MODULE_UNLOAD=y +-CONFIG_MODULE_FORCE_UNLOAD=y +-# CONFIG_BLK_DEV_BSG is not set +-# CONFIG_IOSCHED_DEADLINE is not set +-# CONFIG_IOSCHED_CFQ is not set +-CONFIG_ARCH_SHMOBILE_LEGACY=y +-CONFIG_ARCH_R8A7740=y +-CONFIG_MACH_ARMADILLO800EVA=y +-# CONFIG_SH_TIMER_TMU is not set +-CONFIG_ARM_THUMB=y +-CONFIG_CACHE_L2X0=y +-CONFIG_ARM_ERRATA_430973=y +-CONFIG_ARM_ERRATA_458693=y +-CONFIG_ARM_ERRATA_460075=y +-CONFIG_PL310_ERRATA_588369=y +-CONFIG_ARM_ERRATA_720789=y +-CONFIG_PL310_ERRATA_727915=y +-CONFIG_ARM_ERRATA_743622=y +-CONFIG_ARM_ERRATA_751472=y +-CONFIG_PL310_ERRATA_753970=y +-CONFIG_ARM_ERRATA_754322=y +-CONFIG_PL310_ERRATA_769419=y +-CONFIG_ARM_ERRATA_775420=y +-CONFIG_AEABI=y +-# CONFIG_OABI_COMPAT is not set +-CONFIG_FORCE_MAX_ZONEORDER=13 +-CONFIG_ZBOOT_ROM_TEXT=0x0 +-CONFIG_ZBOOT_ROM_BSS=0x0 +-CONFIG_ARM_APPENDED_DTB=y +-CONFIG_KEXEC=y +-CONFIG_VFP=y +-CONFIG_NEON=y +-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +-CONFIG_PM=y +-CONFIG_NET=y +-CONFIG_PACKET=y +-CONFIG_UNIX=y +-CONFIG_INET=y +-CONFIG_IP_PNP=y +-CONFIG_IP_PNP_DHCP=y +-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +-# CONFIG_INET_XFRM_MODE_TUNNEL is not set +-# CONFIG_INET_XFRM_MODE_BEET is not set +-# CONFIG_INET_LRO is not set +-# CONFIG_INET_DIAG is not set +-# CONFIG_IPV6 is not set +-# CONFIG_WIRELESS is not set +-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +-CONFIG_DEVTMPFS=y +-CONFIG_DEVTMPFS_MOUNT=y +-CONFIG_SCSI=y +-CONFIG_BLK_DEV_SD=y +-CONFIG_MD=y +-CONFIG_BLK_DEV_DM=y +-CONFIG_NETDEVICES=y +-# CONFIG_NET_VENDOR_BROADCOM is not set +-# CONFIG_NET_VENDOR_CHELSIO is not set +-# CONFIG_NET_VENDOR_CIRRUS is not set +-# CONFIG_NET_VENDOR_FARADAY is not set +-# CONFIG_NET_VENDOR_INTEL is not set +-# CONFIG_NET_VENDOR_MARVELL is not set +-# CONFIG_NET_VENDOR_MICREL is not set +-# CONFIG_NET_VENDOR_NATSEMI is not set +-CONFIG_SH_ETH=y +-# CONFIG_NET_VENDOR_SEEQ is not set +-# CONFIG_NET_VENDOR_SMSC is not set +-# CONFIG_NET_VENDOR_STMICRO is not set +-# CONFIG_WLAN is not set +-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +-CONFIG_INPUT_EVDEV=y +-# CONFIG_KEYBOARD_ATKBD is not set +-CONFIG_KEYBOARD_GPIO=y +-# CONFIG_INPUT_MOUSE is not set +-CONFIG_INPUT_TOUCHSCREEN=y +-CONFIG_TOUCHSCREEN_ST1232=y +-# CONFIG_SERIO is not set +-# CONFIG_LEGACY_PTYS is not set +-CONFIG_SERIAL_SH_SCI=y +-CONFIG_SERIAL_SH_SCI_NR_UARTS=9 +-CONFIG_SERIAL_SH_SCI_CONSOLE=y +-# CONFIG_HW_RANDOM is not set +-CONFIG_I2C=y +-CONFIG_I2C_GPIO=y +-CONFIG_I2C_SH_MOBILE=y +-# CONFIG_HWMON is not set +-CONFIG_REGULATOR=y +-CONFIG_REGULATOR_GPIO=y +-CONFIG_MEDIA_SUPPORT=y +-CONFIG_VIDEO_DEV=y +-CONFIG_MEDIA_CAMERA_SUPPORT=y +-CONFIG_V4L_PLATFORM_DRIVERS=y +-CONFIG_SOC_CAMERA=y +-CONFIG_SOC_CAMERA_MT9T112=y +-CONFIG_VIDEO_SH_MOBILE_CEU=y +-CONFIG_FB=y +-CONFIG_FB_SH_MOBILE_LCDC=y +-CONFIG_FB_SH_MOBILE_HDMI=y +-CONFIG_LCD_CLASS_DEVICE=y +-CONFIG_BACKLIGHT_PWM=y +-CONFIG_FRAMEBUFFER_CONSOLE=y +-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +-CONFIG_LOGO=y +-# CONFIG_LOGO_LINUX_MONO is not set +-# CONFIG_LOGO_LINUX_VGA16 is not set +-# CONFIG_SND_SUPPORT_OLD_API is not set +-# CONFIG_SND_VERBOSE_PROCFS is not set +-# CONFIG_SND_DRIVERS is not set +-# CONFIG_SND_ARM is not set +-CONFIG_SND_SOC_SH4_FSI=y +-# CONFIG_HID_SUPPORT is not set +-CONFIG_USB=y +-CONFIG_USB_RENESAS_USBHS=y +-CONFIG_USB_GADGET=y +-CONFIG_USB_RENESAS_USBHS_UDC=y +-CONFIG_USB_ETH=m +-CONFIG_MMC=y +-CONFIG_MMC_SDHI=y +-CONFIG_MMC_SH_MMCIF=y +-CONFIG_NEW_LEDS=y +-CONFIG_LEDS_CLASS=y +-CONFIG_LEDS_GPIO=y +-CONFIG_RTC_CLASS=y +-CONFIG_RTC_DRV_S35390A=y +-CONFIG_DMADEVICES=y +-CONFIG_SH_DMAE=y +-CONFIG_UIO=y +-CONFIG_UIO_PDRV_GENIRQ=y +-CONFIG_PWM=y +-CONFIG_PWM_RENESAS_TPU=y +-# CONFIG_DNOTIFY is not set +-CONFIG_MSDOS_FS=y +-CONFIG_VFAT_FS=y +-CONFIG_TMPFS=y +-# CONFIG_MISC_FILESYSTEMS is not set +-CONFIG_NFS_FS=y +-CONFIG_NFS_V3_ACL=y +-CONFIG_NFS_V4=y +-CONFIG_NFS_V4_1=y +-CONFIG_ROOT_NFS=y +-CONFIG_NLS_CODEPAGE_437=y +-CONFIG_NLS_ISO8859_1=y +-# CONFIG_ENABLE_WARN_DEPRECATED is not set +-# CONFIG_ENABLE_MUST_CHECK is not set +-# CONFIG_ARM_UNWIND is not set +-CONFIG_CRYPTO=y +-CONFIG_CRYPTO_CBC=y +-CONFIG_CRYPTO_MD5=y +-CONFIG_CRYPTO_DES=y +-CONFIG_CRYPTO_ANSI_CPRNG=y +-CONFIG_XZ_DEC=y +-- +2.6.2 + diff --git a/patches.renesas/0152-ARM-shmobile-Drop-r8a7740-armadillo800eva.dtb-for-le.patch b/patches.renesas/0152-ARM-shmobile-Drop-r8a7740-armadillo800eva.dtb-for-le.patch new file mode 100644 index 00000000000000..fd7f44cfbd2f8e --- /dev/null +++ b/patches.renesas/0152-ARM-shmobile-Drop-r8a7740-armadillo800eva.dtb-for-le.patch @@ -0,0 +1,31 @@ +From 923f28e7866e4019f8a3a79ab1e61a8ba64a4648 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:31:23 +0200 +Subject: [PATCH 152/326] ARM: shmobile: Drop r8a7740-armadillo800eva.dtb for + legacy builds + +The legacy board code for Armadillo-800 EVA has been removed. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6a902a2ea1ffe432ce46bb562b9dcae8f396b3b4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/Makefile | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index b7b3f0fbb25b..e13fff1bfa97 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -477,7 +477,6 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ + s5pv210-smdkv210.dtb \ + s5pv210-torbreck.dtb + dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \ +- r8a7740-armadillo800eva.dtb \ + r8a7778-bockw.dtb \ + r8a7778-bockw-reference.dtb \ + r8a7779-marzen.dtb +-- +2.6.2 + diff --git a/patches.renesas/0153-ARM-shmobile-Remove-legacy-SoC-code-for-R-Mobile-A1.patch b/patches.renesas/0153-ARM-shmobile-Remove-legacy-SoC-code-for-R-Mobile-A1.patch new file mode 100644 index 00000000000000..b67182fe7a1f6c --- /dev/null +++ b/patches.renesas/0153-ARM-shmobile-Remove-legacy-SoC-code-for-R-Mobile-A1.patch @@ -0,0 +1,1686 @@ +From 0ba1c1fe1858630b03accdc129869466a604fe16 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:31:24 +0200 +Subject: [PATCH 153/326] ARM: shmobile: Remove legacy SoC code for R-Mobile A1 + +The last user of the R-Mobile A1 (r8a7740) legacy SoC code was the +Armadillo-800 EVA legacy board code, which has been removed. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +[horms: resolved trivial conflicts with v4.2-rc1] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 44d88c754e57a6d9d7ae6ac7540b9596f9b61902) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 7 - + arch/arm/mach-shmobile/Makefile | 3 +- + arch/arm/mach-shmobile/clock-r8a7740.c | 675 -------------------------------- + arch/arm/mach-shmobile/pm-r8a7740.c | 129 ------- + arch/arm/mach-shmobile/r8a7740.h | 58 --- + arch/arm/mach-shmobile/setup-r8a7740.c | 678 +-------------------------------- + 6 files changed, 4 insertions(+), 1546 deletions(-) + delete mode 100644 arch/arm/mach-shmobile/clock-r8a7740.c + delete mode 100644 arch/arm/mach-shmobile/pm-r8a7740.c + delete mode 100644 arch/arm/mach-shmobile/r8a7740.h + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 9e916fafc77d..9725f442d566 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -105,13 +105,6 @@ if ARCH_SHMOBILE_LEGACY + + comment "Renesas ARM SoCs System Type" + +-config ARCH_R8A7740 +- bool "R-Mobile A1 (R8A77400)" +- select ARCH_RMOBILE +- select ARCH_WANT_OPTIONAL_GPIOLIB +- select ARM_GIC +- select RENESAS_INTC_IRQPIN +- + config ARCH_R8A7778 + bool "R-Car M1A (R8A77781)" + select ARCH_RCAR_GEN1 +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 548536fcb3b1..726c219e5b13 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -8,7 +8,7 @@ obj-y := timer.o console.o + # CPU objects + obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o + obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o +-obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o ++obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o + obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o + obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o + obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o +@@ -20,7 +20,6 @@ obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o + # Clock objects + ifndef CONFIG_COMMON_CLK + obj-y += clock.o +-obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o + obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o + obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o + endif +diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c +deleted file mode 100644 +index 9cac8247c72b..000000000000 +--- a/arch/arm/mach-shmobile/clock-r8a7740.c ++++ /dev/null +@@ -1,675 +0,0 @@ +-/* +- * R8A7740 processor support +- * +- * Copyright (C) 2011 Renesas Solutions Corp. +- * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +-#include <linux/init.h> +-#include <linux/kernel.h> +-#include <linux/io.h> +-#include <linux/sh_clk.h> +-#include <linux/clkdev.h> +- +-#include "clock.h" +-#include "common.h" +-#include "r8a7740.h" +- +-/* +- * | MDx | XTAL1/EXTAL1 | System | EXTALR | +- * Clock |-------+-----------------+ clock | 32.768 | RCLK +- * Mode | 2/1/0 | src MHz | source | KHz | source +- * -------+-------+-----------------+-----------+--------+---------- +- * 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR +- * 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR +- * 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR +- * 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR +- * 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024 +- * 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024 +- * 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048 +- * 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048 +- */ +- +-/* CPG registers */ +-#define FRQCRA IOMEM(0xe6150000) +-#define FRQCRB IOMEM(0xe6150004) +-#define VCLKCR1 IOMEM(0xE6150008) +-#define VCLKCR2 IOMEM(0xE615000c) +-#define FRQCRC IOMEM(0xe61500e0) +-#define FSIACKCR IOMEM(0xe6150018) +-#define PLLC01CR IOMEM(0xe6150028) +- +-#define SUBCKCR IOMEM(0xe6150080) +-#define USBCKCR IOMEM(0xe615008c) +- +-#define MSTPSR0 IOMEM(0xe6150030) +-#define MSTPSR1 IOMEM(0xe6150038) +-#define MSTPSR2 IOMEM(0xe6150040) +-#define MSTPSR3 IOMEM(0xe6150048) +-#define MSTPSR4 IOMEM(0xe615004c) +-#define FSIBCKCR IOMEM(0xe6150090) +-#define HDMICKCR IOMEM(0xe6150094) +-#define SMSTPCR0 IOMEM(0xe6150130) +-#define SMSTPCR1 IOMEM(0xe6150134) +-#define SMSTPCR2 IOMEM(0xe6150138) +-#define SMSTPCR3 IOMEM(0xe615013c) +-#define SMSTPCR4 IOMEM(0xe6150140) +- +-#define FSIDIVA IOMEM(0xFE1F8000) +-#define FSIDIVB IOMEM(0xFE1F8008) +- +-/* Fixed 32 KHz root clock from EXTALR pin */ +-static struct clk extalr_clk = { +- .rate = 32768, +-}; +- +-/* +- * 25MHz default rate for the EXTAL1 root input clock. +- * If needed, reset this with clk_set_rate() from the platform code. +- */ +-static struct clk extal1_clk = { +- .rate = 25000000, +-}; +- +-/* +- * 48MHz default rate for the EXTAL2 root input clock. +- * If needed, reset this with clk_set_rate() from the platform code. +- */ +-static struct clk extal2_clk = { +- .rate = 48000000, +-}; +- +-/* +- * 27MHz default rate for the DV_CLKI root input clock. +- * If needed, reset this with clk_set_rate() from the platform code. +- */ +-static struct clk dv_clk = { +- .rate = 27000000, +-}; +- +-SH_CLK_RATIO(div2, 1, 2); +-SH_CLK_RATIO(div1k, 1, 1024); +- +-SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); +-SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k); +-SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k); +-SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); +- +-static struct sh_clk_ops followparent_clk_ops = { +- .recalc = followparent_recalc, +-}; +- +-/* Main clock */ +-static struct clk system_clk = { +- .ops = &followparent_clk_ops, +-}; +- +-SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2); +- +-/* r_clk */ +-static struct clk r_clk = { +- .ops = &followparent_clk_ops, +-}; +- +-/* PLLC0/PLLC1 */ +-static unsigned long pllc01_recalc(struct clk *clk) +-{ +- unsigned long mult = 1; +- +- if (__raw_readl(PLLC01CR) & (1 << 14)) +- mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1; +- +- return clk->parent->rate * mult; +-} +- +-static struct sh_clk_ops pllc01_clk_ops = { +- .recalc = pllc01_recalc, +-}; +- +-static struct clk pllc0_clk = { +- .ops = &pllc01_clk_ops, +- .flags = CLK_ENABLE_ON_INIT, +- .parent = &system_clk, +- .enable_reg = (void __iomem *)FRQCRC, +-}; +- +-static struct clk pllc1_clk = { +- .ops = &pllc01_clk_ops, +- .flags = CLK_ENABLE_ON_INIT, +- .parent = &system_div2_clk, +- .enable_reg = (void __iomem *)FRQCRA, +-}; +- +-/* PLLC1 / 2 */ +-SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2); +- +-/* USB clock */ +-/* +- * USBCKCR is controlling usb24 clock +- * bit[7] : parent clock +- * bit[6] : clock divide rate +- * And this bit[7] is used as a "usb24s" from other devices. +- * (Video clock / Sub clock / SPU clock) +- * You can controll this clock as a below. +- * +- * struct clk *usb24 = clk_get(dev, "usb24"); +- * struct clk *usb24s = clk_get(NULL, "usb24s"); +- * struct clk *system = clk_get(NULL, "system_clk"); +- * int rate = clk_get_rate(system); +- * +- * clk_set_parent(usb24s, system); // for bit[7] +- * clk_set_rate(usb24, rate / 2); // for bit[6] +- */ +-static struct clk *usb24s_parents[] = { +- [0] = &system_clk, +- [1] = &extal2_clk +-}; +- +-static int usb24s_enable(struct clk *clk) +-{ +- __raw_writel(__raw_readl(USBCKCR) & ~(1 << 8), USBCKCR); +- +- return 0; +-} +- +-static void usb24s_disable(struct clk *clk) +-{ +- __raw_writel(__raw_readl(USBCKCR) | (1 << 8), USBCKCR); +-} +- +-static int usb24s_set_parent(struct clk *clk, struct clk *parent) +-{ +- int i, ret; +- u32 val; +- +- if (!clk->parent_table || !clk->parent_num) +- return -EINVAL; +- +- /* Search the parent */ +- for (i = 0; i < clk->parent_num; i++) +- if (clk->parent_table[i] == parent) +- break; +- +- if (i == clk->parent_num) +- return -ENODEV; +- +- ret = clk_reparent(clk, parent); +- if (ret < 0) +- return ret; +- +- val = __raw_readl(USBCKCR); +- val &= ~(1 << 7); +- val |= i << 7; +- __raw_writel(val, USBCKCR); +- +- return 0; +-} +- +-static struct sh_clk_ops usb24s_clk_ops = { +- .recalc = followparent_recalc, +- .enable = usb24s_enable, +- .disable = usb24s_disable, +- .set_parent = usb24s_set_parent, +-}; +- +-static struct clk usb24s_clk = { +- .ops = &usb24s_clk_ops, +- .parent_table = usb24s_parents, +- .parent_num = ARRAY_SIZE(usb24s_parents), +- .parent = &system_clk, +-}; +- +-static unsigned long usb24_recalc(struct clk *clk) +-{ +- return clk->parent->rate / +- ((__raw_readl(USBCKCR) & (1 << 6)) ? 1 : 2); +-}; +- +-static int usb24_set_rate(struct clk *clk, unsigned long rate) +-{ +- u32 val; +- +- /* closer to which ? parent->rate or parent->rate/2 */ +- val = __raw_readl(USBCKCR); +- val &= ~(1 << 6); +- val |= (rate > (clk->parent->rate / 4) * 3) << 6; +- __raw_writel(val, USBCKCR); +- +- return 0; +-} +- +-static struct sh_clk_ops usb24_clk_ops = { +- .recalc = usb24_recalc, +- .set_rate = usb24_set_rate, +-}; +- +-static struct clk usb24_clk = { +- .ops = &usb24_clk_ops, +- .parent = &usb24s_clk, +-}; +- +-/* External FSIACK/FSIBCK clock */ +-static struct clk fsiack_clk = { +-}; +- +-static struct clk fsibck_clk = { +-}; +- +-static struct clk *main_clks[] = { +- &extalr_clk, +- &extal1_clk, +- &extal2_clk, +- &extal1_div2_clk, +- &extal1_div1024_clk, +- &extal1_div2048_clk, +- &extal2_div2_clk, +- &dv_clk, +- &system_clk, +- &system_div2_clk, +- &r_clk, +- &pllc0_clk, +- &pllc1_clk, +- &pllc1_div2_clk, +- &usb24s_clk, +- &usb24_clk, +- &fsiack_clk, +- &fsibck_clk, +-}; +- +-/* DIV4 clocks */ +-static void div4_kick(struct clk *clk) +-{ +- unsigned long value; +- +- /* set KICK bit in FRQCRB to update hardware setting */ +- value = __raw_readl(FRQCRB); +- value |= (1 << 31); +- __raw_writel(value, FRQCRB); +-} +- +-static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, +- 24, 32, 36, 48, 0, 72, 96, 0 }; +- +-static struct clk_div_mult_table div4_div_mult_table = { +- .divisors = divisors, +- .nr_divisors = ARRAY_SIZE(divisors), +-}; +- +-static struct clk_div4_table div4_table = { +- .div_mult_table = &div4_div_mult_table, +- .kick = div4_kick, +-}; +- +-enum { +- DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP, +- DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP, +- DIV4_NR +-}; +- +-static struct clk div4_clks[DIV4_NR] = { +- [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), +- [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), +- [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), +- [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), +- [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0), +- [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0), +- [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0), +- [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0), +- [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0), +- [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0), +- [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0), +-}; +- +-/* DIV6 reparent */ +-enum { +- DIV6_HDMI, +- DIV6_VCLK1, DIV6_VCLK2, +- DIV6_FSIA, DIV6_FSIB, +- DIV6_REPARENT_NR, +-}; +- +-static struct clk *hdmi_parent[] = { +- [0] = &pllc1_div2_clk, +- [1] = &system_clk, +- [2] = &dv_clk +-}; +- +-static struct clk *vclk_parents[8] = { +- [0] = &pllc1_div2_clk, +- [2] = &dv_clk, +- [3] = &usb24s_clk, +- [4] = &extal1_div2_clk, +- [5] = &extalr_clk, +-}; +- +-static struct clk *fsia_parents[] = { +- [0] = &pllc1_div2_clk, +- [1] = &fsiack_clk, /* external clock */ +-}; +- +-static struct clk *fsib_parents[] = { +- [0] = &pllc1_div2_clk, +- [1] = &fsibck_clk, /* external clock */ +-}; +- +-static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { +- [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0, +- hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2), +- [DIV6_VCLK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0, +- vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3), +- [DIV6_VCLK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0, +- vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3), +- [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0, +- fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2), +- [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0, +- fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), +-}; +- +-/* DIV6 clocks */ +-enum { +- DIV6_SUB, +- DIV6_NR +-}; +- +-static struct clk div6_clks[DIV6_NR] = { +- [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0), +-}; +- +-/* HDMI1/2 clock */ +-static unsigned long hdmi12_recalc(struct clk *clk) +-{ +- u32 val = __raw_readl(HDMICKCR); +- int shift = (int)clk->priv; +- +- val >>= shift; +- val &= 0x3; +- +- return clk->parent->rate / (1 << val); +-}; +- +-static int hdmi12_set_rate(struct clk *clk, unsigned long rate) +-{ +- u32 val, mask; +- int i, shift; +- +- for (i = 0; i < 3; i++) +- if (rate == clk->parent->rate / (1 << i)) +- goto find; +- return -ENODEV; +- +-find: +- shift = (int)clk->priv; +- +- val = __raw_readl(HDMICKCR); +- mask = ~(0x3 << shift); +- val = (val & mask) | i << shift; +- __raw_writel(val, HDMICKCR); +- +- return 0; +-}; +- +-static struct sh_clk_ops hdmi12_clk_ops = { +- .recalc = hdmi12_recalc, +- .set_rate = hdmi12_set_rate, +-}; +- +-static struct clk hdmi1_clk = { +- .ops = &hdmi12_clk_ops, +- .priv = (void *)9, +- .parent = &div6_reparent_clks[DIV6_HDMI], /* late install */ +-}; +- +-static struct clk hdmi2_clk = { +- .ops = &hdmi12_clk_ops, +- .priv = (void *)11, +- .parent = &div6_reparent_clks[DIV6_HDMI], /* late install */ +-}; +- +-static struct clk *late_main_clks[] = { +- &hdmi1_clk, +- &hdmi2_clk, +-}; +- +-/* FSI DIV */ +-enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR }; +- +-static struct clk fsidivs[] = { +- [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]), +- [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]), +-}; +- +-/* MSTP */ +-enum { +- MSTP128, MSTP127, MSTP125, +- MSTP116, MSTP111, MSTP100, MSTP117, +- +- MSTP230, MSTP229, +- MSTP222, +- MSTP218, MSTP217, MSTP216, MSTP214, +- MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, +- +- MSTP329, MSTP328, MSTP323, MSTP320, +- MSTP314, MSTP313, MSTP312, +- MSTP309, MSTP304, +- +- MSTP416, MSTP415, MSTP407, MSTP406, +- +- MSTP_NR +-}; +- +-static struct clk mstp_clks[MSTP_NR] = { +- [MSTP128] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 28, 0), /* CEU21 */ +- [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */ +- [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ +- [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ +- [MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_HPP], SMSTPCR1, 16, 0), /* IIC0 */ +- [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */ +- [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ +- +- [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */ +- [MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 29, 0), /* INTCA */ +- [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */ +- [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */ +- [MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */ +- [MSTP216] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */ +- [MSTP214] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */ +- [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ +- [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ +- [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ +- [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */ +- [MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */ +- [MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ +- [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ +- +- [MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ +- [MSTP328] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /* FSI */ +- [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */ +- [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 20, 0), /* USBF */ +- [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ +- [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ +- [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */ +- [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 9, 0), /* GEther */ +- [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP], SMSTPCR3, 4, 0), /* TPU0 */ +- +- [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */ +- [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */ +- [MSTP407] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-Func */ +- [MSTP406] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 6, 0), /* USB Phy */ +-}; +- +-static struct clk_lookup lookups[] = { +- /* main clocks */ +- CLKDEV_CON_ID("extalr", &extalr_clk), +- CLKDEV_CON_ID("extal1", &extal1_clk), +- CLKDEV_CON_ID("extal2", &extal2_clk), +- CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk), +- CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk), +- CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk), +- CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk), +- CLKDEV_CON_ID("dv_clk", &dv_clk), +- CLKDEV_CON_ID("system_clk", &system_clk), +- CLKDEV_CON_ID("system_div2_clk", &system_div2_clk), +- CLKDEV_CON_ID("r_clk", &r_clk), +- CLKDEV_CON_ID("pllc0_clk", &pllc0_clk), +- CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), +- CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), +- CLKDEV_CON_ID("usb24s", &usb24s_clk), +- CLKDEV_CON_ID("hdmi1", &hdmi1_clk), +- CLKDEV_CON_ID("hdmi2", &hdmi2_clk), +- CLKDEV_CON_ID("video1", &div6_reparent_clks[DIV6_VCLK1]), +- CLKDEV_CON_ID("video2", &div6_reparent_clks[DIV6_VCLK2]), +- CLKDEV_CON_ID("fsiack", &fsiack_clk), +- CLKDEV_CON_ID("fsibck", &fsibck_clk), +- +- /* DIV4 clocks */ +- CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), +- CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]), +- CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), +- CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), +- CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), +- CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]), +- CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]), +- CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]), +- CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]), +- CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]), +- +- /* DIV6 clocks */ +- CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]), +- +- /* MSTP32 clocks */ +- CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), +- CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), +- CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), +- CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), +- CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), +- CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]), +- +- CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), +- CLKDEV_DEV_ID("e6c80000.serial", &mstp_clks[MSTP200]), +- CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), +- CLKDEV_DEV_ID("e6c70000.serial", &mstp_clks[MSTP201]), +- CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), +- CLKDEV_DEV_ID("e6c60000.serial", &mstp_clks[MSTP202]), +- CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), +- CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]), +- CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), +- CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), +- CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), +- CLKDEV_DEV_ID("e6c30000.serial", &mstp_clks[MSTP206]), +- CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), +- CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), +- CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), +- CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), +- CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), +- CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), +- CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), +- CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]), +- CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP229]), +- CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP229]), +- CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP229]), +- CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP229]), +- CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), +- CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]), +- +- CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), +- CLKDEV_DEV_ID("fe1f0000.sound", &mstp_clks[MSTP328]), +- CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), +- CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), +- CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), +- CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), +- CLKDEV_DEV_ID("e6850000.sd", &mstp_clks[MSTP314]), +- CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), +- CLKDEV_DEV_ID("e6860000.sd", &mstp_clks[MSTP313]), +- CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), +- CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]), +- CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]), +- CLKDEV_DEV_ID("e9a00000.ethernet", &mstp_clks[MSTP309]), +- CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]), +- CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]), +- +- CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), +- CLKDEV_DEV_ID("e6870000.sd", &mstp_clks[MSTP415]), +- +- /* ICK */ +- CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP111]), +- CLKDEV_ICK_ID("fck", "fff90000.timer", &mstp_clks[MSTP111]), +- CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), +- CLKDEV_ICK_ID("fck", "fff80000.timer", &mstp_clks[MSTP125]), +- CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]), +- CLKDEV_ICK_ID("fck", "e6138000.timer", &mstp_clks[MSTP329]), +- CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), +- CLKDEV_ICK_ID("func", "renesas_usbhs", &mstp_clks[MSTP407]), +- CLKDEV_ICK_ID("phy", "renesas_usbhs", &mstp_clks[MSTP406]), +- CLKDEV_ICK_ID("pci", "renesas_usbhs", &div4_clks[DIV4_USBP]), +- CLKDEV_ICK_ID("usb24", "renesas_usbhs", &usb24_clk), +- CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]), +- +- CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]), +- CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]), +- CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]), +- CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]), +- CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk), +- CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk), +-}; +- +-void __init r8a7740_clock_init(u8 md_ck) +-{ +- int k, ret = 0; +- +- /* detect system clock parent */ +- if (md_ck & MD_CK1) +- system_clk.parent = &extal1_div2_clk; +- else +- system_clk.parent = &extal1_clk; +- +- /* detect RCLK parent */ +- switch (md_ck & (MD_CK2 | MD_CK1)) { +- case MD_CK2 | MD_CK1: +- r_clk.parent = &extal1_div2048_clk; +- break; +- case MD_CK2: +- r_clk.parent = &extal1_div1024_clk; +- break; +- case MD_CK1: +- default: +- r_clk.parent = &extalr_clk; +- break; +- } +- +- for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) +- ret = clk_register(main_clks[k]); +- +- if (!ret) +- ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); +- +- if (!ret) +- ret = sh_clk_div6_register(div6_clks, DIV6_NR); +- +- if (!ret) +- ret = sh_clk_div6_reparent_register(div6_reparent_clks, +- DIV6_REPARENT_NR); +- +- if (!ret) +- ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); +- +- for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) +- ret = clk_register(late_main_clks[k]); +- +- if (!ret) +- ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR); +- +- clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +- +- if (!ret) +- shmobile_clk_init(); +- else +- panic("failed to setup r8a7740 clocks\n"); +-} +diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c +deleted file mode 100644 +index 34608fcf0648..000000000000 +--- a/arch/arm/mach-shmobile/pm-r8a7740.c ++++ /dev/null +@@ -1,129 +0,0 @@ +-/* +- * r8a7740 power management support +- * +- * Copyright (C) 2012 Renesas Solutions Corp. +- * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +- * +- * This file is subject to the terms and conditions of the GNU General Public +- * License. See the file "COPYING" in the main directory of this archive +- * for more details. +- */ +-#include <linux/console.h> +-#include <linux/io.h> +-#include <linux/suspend.h> +- +-#include "common.h" +-#include "pm-rmobile.h" +- +-#define SYSC_BASE IOMEM(0xe6180000) +- +-#if defined(CONFIG_PM) && !defined(CONFIG_ARCH_MULTIPLATFORM) +-static int r8a7740_pd_a3sm_suspend(void) +-{ +- /* +- * The A3SM domain contains the CPU core and therefore it should +- * only be turned off if the CPU is not in use. +- */ +- return -EBUSY; +-} +- +-static int r8a7740_pd_a3sp_suspend(void) +-{ +- /* +- * Serial consoles make use of SCIF hardware located in A3SP, +- * keep such power domain on if "no_console_suspend" is set. +- */ +- return console_suspend_enabled ? 0 : -EBUSY; +-} +- +-static int r8a7740_pd_d4_suspend(void) +-{ +- /* +- * The D4 domain contains the Coresight-ETM hardware block and +- * therefore it should only be turned off if the debug module is +- * not in use. +- */ +- return -EBUSY; +-} +- +-static struct rmobile_pm_domain r8a7740_pm_domains[] = { +- { +- .genpd.name = "A4LC", +- .base = SYSC_BASE, +- .bit_shift = 1, +- }, { +- .genpd.name = "A4MP", +- .base = SYSC_BASE, +- .bit_shift = 2, +- }, { +- .genpd.name = "D4", +- .base = SYSC_BASE, +- .bit_shift = 3, +- .gov = &pm_domain_always_on_gov, +- .suspend = r8a7740_pd_d4_suspend, +- }, { +- .genpd.name = "A4R", +- .base = SYSC_BASE, +- .bit_shift = 5, +- }, { +- .genpd.name = "A3RV", +- .base = SYSC_BASE, +- .bit_shift = 6, +- }, { +- .genpd.name = "A4S", +- .base = SYSC_BASE, +- .bit_shift = 10, +- .no_debug = true, +- }, { +- .genpd.name = "A3SP", +- .base = SYSC_BASE, +- .bit_shift = 11, +- .gov = &pm_domain_always_on_gov, +- .no_debug = true, +- .suspend = r8a7740_pd_a3sp_suspend, +- }, { +- .genpd.name = "A3SM", +- .base = SYSC_BASE, +- .bit_shift = 12, +- .gov = &pm_domain_always_on_gov, +- .suspend = r8a7740_pd_a3sm_suspend, +- }, { +- .genpd.name = "A3SG", +- .base = SYSC_BASE, +- .bit_shift = 13, +- }, { +- .genpd.name = "A4SU", +- .base = SYSC_BASE, +- .bit_shift = 20, +- }, +-}; +- +-void __init r8a7740_init_pm_domains(void) +-{ +- rmobile_init_domains(r8a7740_pm_domains, ARRAY_SIZE(r8a7740_pm_domains)); +- pm_genpd_add_subdomain_names("A4R", "A3RV"); +- pm_genpd_add_subdomain_names("A4S", "A3SP"); +- pm_genpd_add_subdomain_names("A4S", "A3SM"); +- pm_genpd_add_subdomain_names("A4S", "A3SG"); +-} +-#endif /* CONFIG_PM && !CONFIG_ARCH_MULTIPLATFORM */ +- +-#ifdef CONFIG_SUSPEND +-static int r8a7740_enter_suspend(suspend_state_t suspend_state) +-{ +- cpu_do_idle(); +- return 0; +-} +- +-static void r8a7740_suspend_init(void) +-{ +- shmobile_suspend_ops.enter = r8a7740_enter_suspend; +-} +-#else +-static void r8a7740_suspend_init(void) {} +-#endif +- +-void __init r8a7740_pm_init(void) +-{ +- r8a7740_suspend_init(); +-} +diff --git a/arch/arm/mach-shmobile/r8a7740.h b/arch/arm/mach-shmobile/r8a7740.h +deleted file mode 100644 +index ca7805ad7ea3..000000000000 +--- a/arch/arm/mach-shmobile/r8a7740.h ++++ /dev/null +@@ -1,58 +0,0 @@ +-/* +- * Copyright (C) 2011 Renesas Solutions Corp. +- * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#ifndef __ASM_R8A7740_H__ +-#define __ASM_R8A7740_H__ +- +-/* +- * MD_CKx pin +- */ +-#define MD_CK2 (1 << 2) +-#define MD_CK1 (1 << 1) +-#define MD_CK0 (1 << 0) +- +-/* DMA slave IDs */ +-enum { +- SHDMA_SLAVE_INVALID, +- SHDMA_SLAVE_SDHI0_RX, +- SHDMA_SLAVE_SDHI0_TX, +- SHDMA_SLAVE_SDHI1_RX, +- SHDMA_SLAVE_SDHI1_TX, +- SHDMA_SLAVE_SDHI2_RX, +- SHDMA_SLAVE_SDHI2_TX, +- SHDMA_SLAVE_FSIA_RX, +- SHDMA_SLAVE_FSIA_TX, +- SHDMA_SLAVE_FSIB_TX, +- SHDMA_SLAVE_USBHS_TX, +- SHDMA_SLAVE_USBHS_RX, +- SHDMA_SLAVE_MMCIF_TX, +- SHDMA_SLAVE_MMCIF_RX, +-}; +- +-extern void r8a7740_meram_workaround(void); +-extern void r8a7740_init_irq_of(void); +-extern void r8a7740_map_io(void); +-extern void r8a7740_add_early_devices(void); +-extern void r8a7740_add_standard_devices(void); +-extern void r8a7740_clock_init(u8 md_ck); +-extern void r8a7740_pinmux_init(void); +-extern void r8a7740_pm_init(void); +- +-#if defined(CONFIG_PM) && !defined(CONFIG_ARCH_MULTIPLATFORM) +-extern void __init r8a7740_init_pm_domains(void); +-#else +-static inline void r8a7740_init_pm_domains(void) {} +-#endif /* CONFIG_PM && !CONFIG_ARCH_MULTIPLATFORM */ +- +-#endif /* __ASM_R8A7740_H__ */ +diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c +index 00291cc1772d..a158b0bf7762 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7740.c ++++ b/arch/arm/mach-shmobile/setup-r8a7740.c +@@ -13,31 +13,19 @@ + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +-#include <linux/dma-mapping.h> + #include <linux/kernel.h> + #include <linux/init.h> + #include <linux/io.h> + #include <linux/irqchip.h> + #include <linux/irqchip/arm-gic.h> +-#include <linux/platform_data/irq-renesas-intc-irqpin.h> +-#include <linux/platform_device.h> + #include <linux/of_platform.h> +-#include <linux/serial_sci.h> +-#include <linux/sh_dma.h> +-#include <linux/sh_timer.h> +-#include <linux/platform_data/sh_ipmmu.h> + +-#include <asm/mach-types.h> + #include <asm/mach/map.h> + #include <asm/mach/arch.h> + #include <asm/mach/time.h> + #include <asm/hardware/cache-l2x0.h> + + #include "common.h" +-#include "dma-register.h" +-#include "irqs.h" +-#include "pm-rmobile.h" +-#include "r8a7740.h" + + static struct map_desc r8a7740_io_desc[] __initdata = { + /* +@@ -64,613 +52,12 @@ static struct map_desc r8a7740_io_desc[] __initdata = { + #endif + }; + +-void __init r8a7740_map_io(void) ++static void __init r8a7740_map_io(void) + { + debug_ll_io_init(); + iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc)); + } + +-/* PFC */ +-static const struct resource pfc_resources[] = { +- DEFINE_RES_MEM(0xe6050000, 0x8000), +- DEFINE_RES_MEM(0xe605800c, 0x0020), +-}; +- +-void __init r8a7740_pinmux_init(void) +-{ +- platform_device_register_simple("pfc-r8a7740", -1, pfc_resources, +- ARRAY_SIZE(pfc_resources)); +-} +- +-static struct renesas_intc_irqpin_config irqpin0_platform_data = { +- .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ +-}; +- +-static struct resource irqpin0_resources[] = { +- DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ +- DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ +- DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ +- DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ +- DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */ +-}; +- +-static struct platform_device irqpin0_device = { +- .name = "renesas_intc_irqpin", +- .id = 0, +- .resource = irqpin0_resources, +- .num_resources = ARRAY_SIZE(irqpin0_resources), +- .dev = { +- .platform_data = &irqpin0_platform_data, +- }, +-}; +- +-static struct renesas_intc_irqpin_config irqpin1_platform_data = { +- .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ +-}; +- +-static struct resource irqpin1_resources[] = { +- DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ +- DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ +- DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ +- DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ +- DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */ +-}; +- +-static struct platform_device irqpin1_device = { +- .name = "renesas_intc_irqpin", +- .id = 1, +- .resource = irqpin1_resources, +- .num_resources = ARRAY_SIZE(irqpin1_resources), +- .dev = { +- .platform_data = &irqpin1_platform_data, +- }, +-}; +- +-static struct renesas_intc_irqpin_config irqpin2_platform_data = { +- .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ +-}; +- +-static struct resource irqpin2_resources[] = { +- DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ +- DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */ +- DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */ +- DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */ +- DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */ +-}; +- +-static struct platform_device irqpin2_device = { +- .name = "renesas_intc_irqpin", +- .id = 2, +- .resource = irqpin2_resources, +- .num_resources = ARRAY_SIZE(irqpin2_resources), +- .dev = { +- .platform_data = &irqpin2_platform_data, +- }, +-}; +- +-static struct renesas_intc_irqpin_config irqpin3_platform_data = { +- .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ +-}; +- +-static struct resource irqpin3_resources[] = { +- DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */ +- DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ +- DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ +- DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ +- DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */ +- DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */ +-}; +- +-static struct platform_device irqpin3_device = { +- .name = "renesas_intc_irqpin", +- .id = 3, +- .resource = irqpin3_resources, +- .num_resources = ARRAY_SIZE(irqpin3_resources), +- .dev = { +- .platform_data = &irqpin3_platform_data, +- }, +-}; +- +-/* SCIF */ +-#define R8A7740_SCIF(scif_type, index, baseaddr, irq) \ +-static struct plat_sci_port scif##index##_platform_data = { \ +- .type = scif_type, \ +- .flags = UPF_BOOT_AUTOCONF, \ +- .scscr = SCSCR_RE | SCSCR_TE, \ +-}; \ +- \ +-static struct resource scif##index##_resources[] = { \ +- DEFINE_RES_MEM(baseaddr, 0x100), \ +- DEFINE_RES_IRQ(irq), \ +-}; \ +- \ +-static struct platform_device scif##index##_device = { \ +- .name = "sh-sci", \ +- .id = index, \ +- .resource = scif##index##_resources, \ +- .num_resources = ARRAY_SIZE(scif##index##_resources), \ +- .dev = { \ +- .platform_data = &scif##index##_platform_data, \ +- }, \ +-} +- +-R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100)); +-R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101)); +-R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102)); +-R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103)); +-R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104)); +-R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105)); +-R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106)); +-R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107)); +-R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108)); +- +-/* CMT */ +-static struct sh_timer_config cmt1_platform_data = { +- .channels_mask = 0x3f, +-}; +- +-static struct resource cmt1_resources[] = { +- DEFINE_RES_MEM(0xe6138000, 0x170), +- DEFINE_RES_IRQ(gic_spi(58)), +-}; +- +-static struct platform_device cmt1_device = { +- .name = "sh-cmt-48", +- .id = 1, +- .dev = { +- .platform_data = &cmt1_platform_data, +- }, +- .resource = cmt1_resources, +- .num_resources = ARRAY_SIZE(cmt1_resources), +-}; +- +-/* TMU */ +-static struct sh_timer_config tmu0_platform_data = { +- .channels_mask = 7, +-}; +- +-static struct resource tmu0_resources[] = { +- DEFINE_RES_MEM(0xfff80000, 0x2c), +- DEFINE_RES_IRQ(gic_spi(198)), +- DEFINE_RES_IRQ(gic_spi(199)), +- DEFINE_RES_IRQ(gic_spi(200)), +-}; +- +-static struct platform_device tmu0_device = { +- .name = "sh-tmu", +- .id = 0, +- .dev = { +- .platform_data = &tmu0_platform_data, +- }, +- .resource = tmu0_resources, +- .num_resources = ARRAY_SIZE(tmu0_resources), +-}; +- +-/* IPMMUI (an IPMMU module for ICB/LMB) */ +-static struct resource ipmmu_resources[] = { +- [0] = { +- .name = "IPMMUI", +- .start = 0xfe951000, +- .end = 0xfe9510ff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static const char * const ipmmu_dev_names[] = { +- "sh_mobile_lcdc_fb.0", +- "sh_mobile_lcdc_fb.1", +- "sh_mobile_ceu.0", +-}; +- +-static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { +- .dev_names = ipmmu_dev_names, +- .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), +-}; +- +-static struct platform_device ipmmu_device = { +- .name = "ipmmu", +- .id = -1, +- .dev = { +- .platform_data = &ipmmu_platform_data, +- }, +- .resource = ipmmu_resources, +- .num_resources = ARRAY_SIZE(ipmmu_resources), +-}; +- +-static struct platform_device *r8a7740_early_devices[] __initdata = { +- &scif0_device, +- &scif1_device, +- &scif2_device, +- &scif3_device, +- &scif4_device, +- &scif5_device, +- &scif6_device, +- &scif7_device, +- &scif8_device, +- &irqpin0_device, +- &irqpin1_device, +- &irqpin2_device, +- &irqpin3_device, +- &tmu0_device, +- &ipmmu_device, +- &cmt1_device, +-}; +- +-/* DMA */ +-static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = { +- { +- .slave_id = SHDMA_SLAVE_SDHI0_TX, +- .addr = 0xe6850030, +- .chcr = CHCR_TX(XMIT_SZ_16BIT), +- .mid_rid = 0xc1, +- }, { +- .slave_id = SHDMA_SLAVE_SDHI0_RX, +- .addr = 0xe6850030, +- .chcr = CHCR_RX(XMIT_SZ_16BIT), +- .mid_rid = 0xc2, +- }, { +- .slave_id = SHDMA_SLAVE_SDHI1_TX, +- .addr = 0xe6860030, +- .chcr = CHCR_TX(XMIT_SZ_16BIT), +- .mid_rid = 0xc9, +- }, { +- .slave_id = SHDMA_SLAVE_SDHI1_RX, +- .addr = 0xe6860030, +- .chcr = CHCR_RX(XMIT_SZ_16BIT), +- .mid_rid = 0xca, +- }, { +- .slave_id = SHDMA_SLAVE_SDHI2_TX, +- .addr = 0xe6870030, +- .chcr = CHCR_TX(XMIT_SZ_16BIT), +- .mid_rid = 0xcd, +- }, { +- .slave_id = SHDMA_SLAVE_SDHI2_RX, +- .addr = 0xe6870030, +- .chcr = CHCR_RX(XMIT_SZ_16BIT), +- .mid_rid = 0xce, +- }, { +- .slave_id = SHDMA_SLAVE_FSIA_TX, +- .addr = 0xfe1f0024, +- .chcr = CHCR_TX(XMIT_SZ_32BIT), +- .mid_rid = 0xb1, +- }, { +- .slave_id = SHDMA_SLAVE_FSIA_RX, +- .addr = 0xfe1f0020, +- .chcr = CHCR_RX(XMIT_SZ_32BIT), +- .mid_rid = 0xb2, +- }, { +- .slave_id = SHDMA_SLAVE_FSIB_TX, +- .addr = 0xfe1f0064, +- .chcr = CHCR_TX(XMIT_SZ_32BIT), +- .mid_rid = 0xb5, +- }, { +- .slave_id = SHDMA_SLAVE_MMCIF_TX, +- .addr = 0xe6bd0034, +- .chcr = CHCR_TX(XMIT_SZ_32BIT), +- .mid_rid = 0xd1, +- }, { +- .slave_id = SHDMA_SLAVE_MMCIF_RX, +- .addr = 0xe6bd0034, +- .chcr = CHCR_RX(XMIT_SZ_32BIT), +- .mid_rid = 0xd2, +- }, +-}; +- +-#define DMA_CHANNEL(a, b, c) \ +-{ \ +- .offset = a, \ +- .dmars = b, \ +- .dmars_bit = c, \ +- .chclr_offset = (0x220 - 0x20) + a \ +-} +- +-static const struct sh_dmae_channel r8a7740_dmae_channels[] = { +- DMA_CHANNEL(0x00, 0, 0), +- DMA_CHANNEL(0x10, 0, 8), +- DMA_CHANNEL(0x20, 4, 0), +- DMA_CHANNEL(0x30, 4, 8), +- DMA_CHANNEL(0x50, 8, 0), +- DMA_CHANNEL(0x60, 8, 8), +-}; +- +-static struct sh_dmae_pdata dma_platform_data = { +- .slave = r8a7740_dmae_slaves, +- .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves), +- .channel = r8a7740_dmae_channels, +- .channel_num = ARRAY_SIZE(r8a7740_dmae_channels), +- .ts_low_shift = TS_LOW_SHIFT, +- .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, +- .ts_high_shift = TS_HI_SHIFT, +- .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, +- .ts_shift = dma_ts_shift, +- .ts_shift_num = ARRAY_SIZE(dma_ts_shift), +- .dmaor_init = DMAOR_DME, +- .chclr_present = 1, +-}; +- +-/* Resource order important! */ +-static struct resource r8a7740_dmae0_resources[] = { +- { +- /* Channel registers and DMAOR */ +- .start = 0xfe008020, +- .end = 0xfe00828f, +- .flags = IORESOURCE_MEM, +- }, +- { +- /* DMARSx */ +- .start = 0xfe009000, +- .end = 0xfe00900b, +- .flags = IORESOURCE_MEM, +- }, +- { +- .name = "error_irq", +- .start = gic_spi(34), +- .end = gic_spi(34), +- .flags = IORESOURCE_IRQ, +- }, +- { +- /* IRQ for channels 0-5 */ +- .start = gic_spi(28), +- .end = gic_spi(33), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-/* Resource order important! */ +-static struct resource r8a7740_dmae1_resources[] = { +- { +- /* Channel registers and DMAOR */ +- .start = 0xfe018020, +- .end = 0xfe01828f, +- .flags = IORESOURCE_MEM, +- }, +- { +- /* DMARSx */ +- .start = 0xfe019000, +- .end = 0xfe01900b, +- .flags = IORESOURCE_MEM, +- }, +- { +- .name = "error_irq", +- .start = gic_spi(41), +- .end = gic_spi(41), +- .flags = IORESOURCE_IRQ, +- }, +- { +- /* IRQ for channels 0-5 */ +- .start = gic_spi(35), +- .end = gic_spi(40), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-/* Resource order important! */ +-static struct resource r8a7740_dmae2_resources[] = { +- { +- /* Channel registers and DMAOR */ +- .start = 0xfe028020, +- .end = 0xfe02828f, +- .flags = IORESOURCE_MEM, +- }, +- { +- /* DMARSx */ +- .start = 0xfe029000, +- .end = 0xfe02900b, +- .flags = IORESOURCE_MEM, +- }, +- { +- .name = "error_irq", +- .start = gic_spi(48), +- .end = gic_spi(48), +- .flags = IORESOURCE_IRQ, +- }, +- { +- /* IRQ for channels 0-5 */ +- .start = gic_spi(42), +- .end = gic_spi(47), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device dma0_device = { +- .name = "sh-dma-engine", +- .id = 0, +- .resource = r8a7740_dmae0_resources, +- .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources), +- .dev = { +- .platform_data = &dma_platform_data, +- }, +-}; +- +-static struct platform_device dma1_device = { +- .name = "sh-dma-engine", +- .id = 1, +- .resource = r8a7740_dmae1_resources, +- .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources), +- .dev = { +- .platform_data = &dma_platform_data, +- }, +-}; +- +-static struct platform_device dma2_device = { +- .name = "sh-dma-engine", +- .id = 2, +- .resource = r8a7740_dmae2_resources, +- .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources), +- .dev = { +- .platform_data = &dma_platform_data, +- }, +-}; +- +-/* USB-DMAC */ +-static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = { +- { +- .offset = 0, +- }, { +- .offset = 0x20, +- }, +-}; +- +-static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = { +- { +- .slave_id = SHDMA_SLAVE_USBHS_TX, +- .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), +- }, { +- .slave_id = SHDMA_SLAVE_USBHS_RX, +- .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), +- }, +-}; +- +-static struct sh_dmae_pdata usb_dma_platform_data = { +- .slave = r8a7740_usb_dma_slaves, +- .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves), +- .channel = r8a7740_usb_dma_channels, +- .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels), +- .ts_low_shift = USBTS_LOW_SHIFT, +- .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT, +- .ts_high_shift = USBTS_HI_SHIFT, +- .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT, +- .ts_shift = dma_usbts_shift, +- .ts_shift_num = ARRAY_SIZE(dma_usbts_shift), +- .dmaor_init = DMAOR_DME, +- .chcr_offset = 0x14, +- .chcr_ie_bit = 1 << 5, +- .dmaor_is_32bit = 1, +- .needs_tend_set = 1, +- .no_dmars = 1, +- .slave_only = 1, +-}; +- +-static struct resource r8a7740_usb_dma_resources[] = { +- { +- /* Channel registers and DMAOR */ +- .start = 0xe68a0020, +- .end = 0xe68a0064 - 1, +- .flags = IORESOURCE_MEM, +- }, +- { +- /* VCR/SWR/DMICR */ +- .start = 0xe68a0000, +- .end = 0xe68a0014 - 1, +- .flags = IORESOURCE_MEM, +- }, +- { +- /* IRQ for channels */ +- .start = gic_spi(49), +- .end = gic_spi(49), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device usb_dma_device = { +- .name = "sh-dma-engine", +- .id = 3, +- .resource = r8a7740_usb_dma_resources, +- .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources), +- .dev = { +- .platform_data = &usb_dma_platform_data, +- }, +-}; +- +-/* I2C */ +-static struct resource i2c0_resources[] = { +- [0] = { +- .name = "IIC0", +- .start = 0xfff20000, +- .end = 0xfff20425 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(201), +- .end = gic_spi(204), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct resource i2c1_resources[] = { +- [0] = { +- .name = "IIC1", +- .start = 0xe6c20000, +- .end = 0xe6c20425 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_spi(70), /* IIC1_ALI1 */ +- .end = gic_spi(73), /* IIC1_DTEI1 */ +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device i2c0_device = { +- .name = "i2c-sh_mobile", +- .id = 0, +- .resource = i2c0_resources, +- .num_resources = ARRAY_SIZE(i2c0_resources), +-}; +- +-static struct platform_device i2c1_device = { +- .name = "i2c-sh_mobile", +- .id = 1, +- .resource = i2c1_resources, +- .num_resources = ARRAY_SIZE(i2c1_resources), +-}; +- +-static struct resource pmu_resources[] = { +- [0] = { +- .start = gic_spi(83), +- .end = gic_spi(83), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device pmu_device = { +- .name = "armv7-pmu", +- .id = -1, +- .num_resources = ARRAY_SIZE(pmu_resources), +- .resource = pmu_resources, +-}; +- +-static struct platform_device *r8a7740_late_devices[] __initdata = { +- &i2c0_device, +- &i2c1_device, +- &dma0_device, +- &dma1_device, +- &dma2_device, +- &usb_dma_device, +- &pmu_device, +-}; +- + /* + * r8a7740 chip has lasting errata on MERAM buffer. + * this is work-around for it. +@@ -678,7 +65,7 @@ static struct platform_device *r8a7740_late_devices[] __initdata = { + * "Media RAM (MERAM)" on r8a7740 documentation + */ + #define MEBUFCNTR 0xFE950098 +-void __init r8a7740_meram_workaround(void) ++static void __init r8a7740_meram_workaround(void) + { + void __iomem *reg; + +@@ -689,70 +76,13 @@ void __init r8a7740_meram_workaround(void) + } + } + +-void __init r8a7740_add_standard_devices(void) +-{ +- static struct pm_domain_device domain_devices[] __initdata = { +- { "A4R", &tmu0_device }, +- { "A4R", &i2c0_device }, +- { "A4S", &irqpin0_device }, +- { "A4S", &irqpin1_device }, +- { "A4S", &irqpin2_device }, +- { "A4S", &irqpin3_device }, +- { "A3SP", &scif0_device }, +- { "A3SP", &scif1_device }, +- { "A3SP", &scif2_device }, +- { "A3SP", &scif3_device }, +- { "A3SP", &scif4_device }, +- { "A3SP", &scif5_device }, +- { "A3SP", &scif6_device }, +- { "A3SP", &scif7_device }, +- { "A3SP", &scif8_device }, +- { "A3SP", &i2c1_device }, +- { "A3SP", &ipmmu_device }, +- { "A3SP", &dma0_device }, +- { "A3SP", &dma1_device }, +- { "A3SP", &dma2_device }, +- { "A3SP", &usb_dma_device }, +- }; +- +- r8a7740_init_pm_domains(); +- +- /* add devices */ +- platform_add_devices(r8a7740_early_devices, +- ARRAY_SIZE(r8a7740_early_devices)); +- platform_add_devices(r8a7740_late_devices, +- ARRAY_SIZE(r8a7740_late_devices)); +- +- /* add devices to PM domain */ +- rmobile_add_devices_to_domains(domain_devices, +- ARRAY_SIZE(domain_devices)); +-} +- +-void __init r8a7740_add_early_devices(void) +-{ +- early_platform_add_devices(r8a7740_early_devices, +- ARRAY_SIZE(r8a7740_early_devices)); +- +- /* setup early console here as well */ +- shmobile_setup_console(); +-} +- +-#ifdef CONFIG_USE_OF +- +-void __init r8a7740_init_irq_of(void) ++static void __init r8a7740_init_irq_of(void) + { + void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); + void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); + void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); + +-#ifdef CONFIG_ARCH_SHMOBILE_LEGACY +- void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000); +- void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000); +- +- gic_init(0, 29, gic_dist_base, gic_cpu_base); +-#else + irqchip_init(); +-#endif + + /* route signals to GIC */ + iowrite32(0x0, pfc_inta_ctrl); +@@ -800,5 +130,3 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") + .init_late = shmobile_init_late, + .dt_compat = r8a7740_boards_compat_dt, + MACHINE_END +- +-#endif /* CONFIG_USE_OF */ +-- +2.6.2 + diff --git a/patches.renesas/0154-ARM-shmobile-Remove-unused-dma-register.h.patch b/patches.renesas/0154-ARM-shmobile-Remove-unused-dma-register.h.patch new file mode 100644 index 00000000000000..bcc9b4fdd6569a --- /dev/null +++ b/patches.renesas/0154-ARM-shmobile-Remove-unused-dma-register.h.patch @@ -0,0 +1,110 @@ +From dee14fe6975facca1f7e475f8064fac63845ba63 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:31:25 +0200 +Subject: [PATCH 154/326] ARM: shmobile: Remove unused dma-register.h + +The last users of "dma-register.h" were the sh73a0 and r8a7740 legacy +SoC code, which have been removed. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 68a31785697c6292e4de3f54914a6ff5ebd0a82d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/dma-register.h | 84 ----------------------------------- + 1 file changed, 84 deletions(-) + delete mode 100644 arch/arm/mach-shmobile/dma-register.h + +diff --git a/arch/arm/mach-shmobile/dma-register.h b/arch/arm/mach-shmobile/dma-register.h +deleted file mode 100644 +index 52a2f66e600f..000000000000 +--- a/arch/arm/mach-shmobile/dma-register.h ++++ /dev/null +@@ -1,84 +0,0 @@ +-/* +- * SH-ARM CPU-specific DMA definitions, used by both DMA drivers +- * +- * Copyright (C) 2012 Renesas Solutions Corp +- * +- * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +- * +- * Based on arch/sh/include/cpu-sh4/cpu/dma-register.h +- * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- */ +- +-#ifndef DMA_REGISTER_H +-#define DMA_REGISTER_H +- +-/* +- * Direct Memory Access Controller +- */ +- +-/* Transmit sizes and respective CHCR register values */ +-enum { +- XMIT_SZ_8BIT = 0, +- XMIT_SZ_16BIT = 1, +- XMIT_SZ_32BIT = 2, +- XMIT_SZ_64BIT = 7, +- XMIT_SZ_128BIT = 3, +- XMIT_SZ_256BIT = 4, +- XMIT_SZ_512BIT = 5, +-}; +- +-/* log2(size / 8) - used to calculate number of transfers */ +-static const unsigned int dma_ts_shift[] = { +- [XMIT_SZ_8BIT] = 0, +- [XMIT_SZ_16BIT] = 1, +- [XMIT_SZ_32BIT] = 2, +- [XMIT_SZ_64BIT] = 3, +- [XMIT_SZ_128BIT] = 4, +- [XMIT_SZ_256BIT] = 5, +- [XMIT_SZ_512BIT] = 6, +-}; +- +-#define TS_LOW_BIT 0x3 /* --xx */ +-#define TS_HI_BIT 0xc /* xx-- */ +- +-#define TS_LOW_SHIFT (3) +-#define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */ +- +-#define TS_INDEX2VAL(i) \ +- ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\ +- (((i) & TS_HI_BIT) << TS_HI_SHIFT)) +- +-#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL((xmit_sz))) +-#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL((xmit_sz))) +- +- +-/* +- * USB High-Speed DMAC +- */ +-/* Transmit sizes and respective CHCR register values */ +-enum { +- USBTS_XMIT_SZ_8BYTE = 0, +- USBTS_XMIT_SZ_16BYTE = 1, +- USBTS_XMIT_SZ_32BYTE = 2, +-}; +- +-/* log2(size / 8) - used to calculate number of transfers */ +-static const unsigned int dma_usbts_shift[] = { +- [USBTS_XMIT_SZ_8BYTE] = 3, +- [USBTS_XMIT_SZ_16BYTE] = 4, +- [USBTS_XMIT_SZ_32BYTE] = 5, +-}; +- +-#define USBTS_LOW_BIT 0x3 /* --xx */ +-#define USBTS_HI_BIT 0x0 /* ---- */ +- +-#define USBTS_LOW_SHIFT 6 +-#define USBTS_HI_SHIFT 0 +- +-#define USBTS_INDEX2VAL(i) (((i) & 3) << 6) +- +-#endif /* DMA_REGISTER_H */ +-- +2.6.2 + diff --git a/patches.renesas/0155-ARM-shmobile-R-Mobile-Remove-legacy-PM-Domain-code.patch b/patches.renesas/0155-ARM-shmobile-R-Mobile-Remove-legacy-PM-Domain-code.patch new file mode 100644 index 00000000000000..8bdb52790aaa15 --- /dev/null +++ b/patches.renesas/0155-ARM-shmobile-R-Mobile-Remove-legacy-PM-Domain-code.patch @@ -0,0 +1,107 @@ +From f1e59faef0dd121685243126eece19b7873bcec4 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:31:26 +0200 +Subject: [PATCH 155/326] ARM: shmobile: R-Mobile: Remove legacy PM Domain code + +The last user of the legacy R-Mobile PM Domain code was the r8a7740 +legacy SoC code, which has been removed. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b587288001f05c0e6b4bdb5a5f0e7a28594cbf0d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/pm-rmobile.c | 39 ------------------------------------- + arch/arm/mach-shmobile/pm-rmobile.h | 24 ----------------------- + 2 files changed, 63 deletions(-) + +diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c +index b9b494f5ca99..a5b96b990aea 100644 +--- a/arch/arm/mach-shmobile/pm-rmobile.c ++++ b/arch/arm/mach-shmobile/pm-rmobile.c +@@ -169,43 +169,6 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd) + __rmobile_pd_power_up(rmobile_pd, false); + } + +-#ifdef CONFIG_ARCH_SHMOBILE_LEGACY +- +-void rmobile_init_domains(struct rmobile_pm_domain domains[], int num) +-{ +- int j; +- +- for (j = 0; j < num; j++) +- rmobile_init_pm_domain(&domains[j]); +-} +- +-void rmobile_add_device_to_domain_td(const char *domain_name, +- struct platform_device *pdev, +- struct gpd_timing_data *td) +-{ +- struct device *dev = &pdev->dev; +- +- __pm_genpd_name_add_device(domain_name, dev, td); +-} +- +-void rmobile_add_devices_to_domains(struct pm_domain_device data[], +- int size) +-{ +- struct gpd_timing_data latencies = { +- .stop_latency_ns = DEFAULT_DEV_LATENCY_NS, +- .start_latency_ns = DEFAULT_DEV_LATENCY_NS, +- .save_state_latency_ns = DEFAULT_DEV_LATENCY_NS, +- .restore_state_latency_ns = DEFAULT_DEV_LATENCY_NS, +- }; +- int j; +- +- for (j = 0; j < size; j++) +- rmobile_add_device_to_domain_td(data[j].domain_name, +- data[j].pdev, &latencies); +-} +- +-#else /* !CONFIG_ARCH_SHMOBILE_LEGACY */ +- + static int rmobile_pd_suspend_busy(void) + { + /* +@@ -436,5 +399,3 @@ static int __init rmobile_init_pm_domains(void) + } + + core_initcall(rmobile_init_pm_domains); +- +-#endif /* !CONFIG_ARCH_SHMOBILE_LEGACY */ +diff --git a/arch/arm/mach-shmobile/pm-rmobile.h b/arch/arm/mach-shmobile/pm-rmobile.h +index 3992b619c127..30a4a421ee31 100644 +--- a/arch/arm/mach-shmobile/pm-rmobile.h ++++ b/arch/arm/mach-shmobile/pm-rmobile.h +@@ -31,28 +31,4 @@ struct pm_domain_device { + struct platform_device *pdev; + }; + +-#if defined(CONFIG_PM_RMOBILE) && defined(CONFIG_ARCH_SHMOBILE_LEGACY) +-extern void rmobile_init_domains(struct rmobile_pm_domain domains[], int num); +-extern void rmobile_add_device_to_domain_td(const char *domain_name, +- struct platform_device *pdev, +- struct gpd_timing_data *td); +- +-static inline void rmobile_add_device_to_domain(const char *domain_name, +- struct platform_device *pdev) +-{ +- rmobile_add_device_to_domain_td(domain_name, pdev, NULL); +-} +- +-extern void rmobile_add_devices_to_domains(struct pm_domain_device data[], +- int size); +-#else +- +-#define rmobile_init_domains(domains, num) do { } while (0) +-#define rmobile_add_device_to_domain_td(name, pdev, td) do { } while (0) +-#define rmobile_add_device_to_domain(name, pdev) do { } while (0) +- +-static inline void rmobile_add_devices_to_domains(struct pm_domain_device d[], +- int size) {} +-#endif /* CONFIG_PM_RMOBILE */ +- + #endif /* PM_RMOBILE_H */ +-- +2.6.2 + diff --git a/patches.renesas/0156-ARM-shmobile-Remove-obsolete-zboot-support.patch b/patches.renesas/0156-ARM-shmobile-Remove-obsolete-zboot-support.patch new file mode 100644 index 00000000000000..ed2094afabb958 --- /dev/null +++ b/patches.renesas/0156-ARM-shmobile-Remove-obsolete-zboot-support.patch @@ -0,0 +1,251 @@ +From ae4cb5379077dae79c77ae96d235e01096990578 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:31:27 +0200 +Subject: [PATCH 156/326] ARM: shmobile: Remove obsolete zboot support + +The last user of the zboot code was the KZM-A9-GT legacy board code, +which has been removed. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 11e386719b08606502477cddf10c832b6658bb55) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/compressed/Makefile | 4 - + arch/arm/boot/compressed/head-shmobile.S | 71 -------------- + arch/arm/mach-shmobile/include/mach/zboot.h | 14 --- + arch/arm/mach-shmobile/include/mach/zboot_macros.h | 108 --------------------- + 4 files changed, 197 deletions(-) + delete mode 100644 arch/arm/boot/compressed/head-shmobile.S + delete mode 100644 arch/arm/mach-shmobile/include/mach/zboot.h + delete mode 100644 arch/arm/mach-shmobile/include/mach/zboot_macros.h + +diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile +index 6e1fb2b2ecc7..8be2cdec87a8 100644 +--- a/arch/arm/boot/compressed/Makefile ++++ b/arch/arm/boot/compressed/Makefile +@@ -51,10 +51,6 @@ else + endif + endif + +-ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y) +-OBJS += head-shmobile.o +-endif +- + # + # We now have a PIC decompressor implementation. Decompressors running + # from RAM should not define ZTEXTADDR. Decompressors running directly +diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S +deleted file mode 100644 +index 22a75259faa3..000000000000 +--- a/arch/arm/boot/compressed/head-shmobile.S ++++ /dev/null +@@ -1,71 +0,0 @@ +-/* +- * The head-file for SH-Mobile ARM platforms +- * +- * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +- * Simon Horman <horms@verge.net.au> +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +- */ +- +-#ifdef CONFIG_ZBOOT_ROM +- +- .section ".start", "ax" +- +- /* load board-specific initialization code */ +-#include <mach/zboot.h> +- +- adr r0, dtb_info +- ldmia r0, {r1, r3, r4, r5, r7} +- +- sub r0, r0, r1 @ calculate the delta offset +- add r5, r5, r0 @ _edata +- +- ldr lr, [r5, #0] @ check if valid DTB is present +- cmp lr, r3 +- bne 0f +- +- add r9, r7, #31 @ rounded up to a multiple +- bic r9, r9, #31 @ ... of 32 bytes +- +- add r6, r9, r5 @ copy from _edata +- add r9, r9, r4 @ to MEMORY_START +- +-1: ldmdb r6!, {r0 - r3, r10 - r12, lr} +- cmp r6, r5 +- stmdb r9!, {r0 - r3, r10 - r12, lr} +- bhi 1b +- +- /* Success: Zero board ID, pointer to start of memory for atag/dtb */ +- mov r7, #0 +- mov r8, r4 +- b 2f +- +- .align 2 +-dtb_info: +- .word dtb_info +-#ifndef __ARMEB__ +- .word 0xedfe0dd0 @ sig is 0xd00dfeed big endian +-#else +- .word 0xd00dfeed +-#endif +- .word MEMORY_START +- .word _edata +- .word 0x4000 @ maximum DTB size +-0: +- /* Failure: Zero board ID, NULL atag/dtb */ +- mov r7, #0 +- mov r8, #0 @ pass null pointer as atag +-2 : +- +-#endif /* CONFIG_ZBOOT_ROM */ +diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h +deleted file mode 100644 +index 80f599f4b5ab..000000000000 +--- a/arch/arm/mach-shmobile/include/mach/zboot.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-#ifndef ZBOOT_H +-#define ZBOOT_H +- +-#include <mach/zboot_macros.h> +- +-/************************************************** +- * +- * board specific settings +- * +- **************************************************/ +- +-#error "unsupported board." +- +-#endif /* ZBOOT_H */ +diff --git a/arch/arm/mach-shmobile/include/mach/zboot_macros.h b/arch/arm/mach-shmobile/include/mach/zboot_macros.h +deleted file mode 100644 +index 14fd3d538e9a..000000000000 +--- a/arch/arm/mach-shmobile/include/mach/zboot_macros.h ++++ /dev/null +@@ -1,108 +0,0 @@ +-#ifndef __ZBOOT_MACRO_H +-#define __ZBOOT_MACRO_H +- +-/* The LIST command is used to include comments in the script */ +-.macro LIST comment +-.endm +- +-/* The ED command is used to write a 32-bit word */ +-.macro ED, addr, data +- LDR r0, 1f +- LDR r1, 2f +- STR r1, [r0] +- B 3f +-1 : .long \addr +-2 : .long \data +-3 : +-.endm +- +-/* The EW command is used to write a 16-bit word */ +-.macro EW, addr, data +- LDR r0, 1f +- LDR r1, 2f +- STRH r1, [r0] +- B 3f +-1 : .long \addr +-2 : .long \data +-3 : +-.endm +- +-/* The EB command is used to write an 8-bit word */ +-.macro EB, addr, data +- LDR r0, 1f +- LDR r1, 2f +- STRB r1, [r0] +- B 3f +-1 : .long \addr +-2 : .long \data +-3 : +-.endm +- +-/* The WAIT command is used to delay the execution */ +-.macro WAIT, time, reg +- LDR r1, 1f +- LDR r0, 2f +- STR r0, [r1] +-10 : +- LDR r0, [r1] +- CMP r0, #0x00000000 +- BNE 10b +- NOP +- B 3f +-1 : .long \reg +-2 : .long \time * 100 +-3 : +-.endm +- +-/* The DD command is used to read a 32-bit word */ +-.macro DD, start, end +- LDR r1, 1f +- B 2f +-1 : .long \start +-2 : +-.endm +- +-/* loop until a given value has been read (with mask) */ +-.macro WAIT_MASK, addr, data, cmp +- LDR r0, 2f +- LDR r1, 3f +- LDR r2, 4f +-1: +- LDR r3, [r0, #0] +- AND r3, r1, r3 +- CMP r2, r3 +- BNE 1b +- B 5f +-2: .long \addr +-3: .long \data +-4: .long \cmp +-5: +-.endm +- +-/* read 32-bit value from addr, "or" an immediate and write back */ +-.macro ED_OR, addr, data +- LDR r4, 1f +- LDR r5, 2f +- LDR r6, [r4] +- ORR r5, r6, r5 +- STR r5, [r4] +- B 3f +-1: .long \addr +-2: .long \data +-3: +-.endm +- +-/* read 32-bit value from addr, "and" an immediate and write back */ +-.macro ED_AND, addr, data +- LDR r4, 1f +- LDR r5, 2f +- LDR r6, [r4] +- AND r5, r6, r5 +- STR r5, [r4] +- B 3f +-1: .long \addr +-2: .long \data +-3: +-.endm +- +-#endif /* __ZBOOT_MACRO_H */ +-- +2.6.2 + diff --git a/patches.renesas/0157-ARM-shmobile-R-Car-Gen2-CONFIG_ARCH_SHMOBILE_MULTI-i.patch b/patches.renesas/0157-ARM-shmobile-R-Car-Gen2-CONFIG_ARCH_SHMOBILE_MULTI-i.patch new file mode 100644 index 00000000000000..5d2ede710d4a79 --- /dev/null +++ b/patches.renesas/0157-ARM-shmobile-R-Car-Gen2-CONFIG_ARCH_SHMOBILE_MULTI-i.patch @@ -0,0 +1,37 @@ +From f3b32d2dca3eac73844700d1e4e50a9a75cb52f3 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:34:20 +0200 +Subject: [PATCH 157/326] ARM: shmobile: R-Car Gen2: CONFIG_ARCH_SHMOBILE_MULTI + is always set + +Since commit e042681894b62d60 ("ARM: shmobile: r8a7790: Remove legacy +code"), all R-Car Gen2 SoCs are supported by multiplatform kernels only. +As CONFIG_ARCH_SHMOBILE_MULTI is always set for shmobile multiplatform +kernels, we can remove related #ifdefs in code specific to R-Car Gen2 +SoCs. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d62ba10c31ac16aaa16f5b49308658ea2f1e71a9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-rcar-gen2.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c +index 5d13595aa027..aa3339258d9c 100644 +--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c ++++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c +@@ -128,9 +128,7 @@ void __init rcar_gen2_timer_init(void) + #endif /* CONFIG_ARM_ARCH_TIMER */ + + rcar_gen2_clocks_init(mode); +-#ifdef CONFIG_ARCH_SHMOBILE_MULTI + clocksource_of_init(); +-#endif + } + + struct memory_reserve_config { +-- +2.6.2 + diff --git a/patches.renesas/0158-ARM-shmobile-timer-r8a73a4-and-r8a7790-are-multi-pla.patch b/patches.renesas/0158-ARM-shmobile-timer-r8a73a4-and-r8a7790-are-multi-pla.patch new file mode 100644 index 00000000000000..d290e725891b41 --- /dev/null +++ b/patches.renesas/0158-ARM-shmobile-timer-r8a73a4-and-r8a7790-are-multi-pla.patch @@ -0,0 +1,46 @@ +From 31eb9518c561d5e995f7c9ce22d0ae134403d983 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 11:34:21 +0200 +Subject: [PATCH 158/326] ARM: shmobile: timer: r8a73a4 and r8a7790 are + multi-platform only + +Since commits e042681894b62d60 ("ARM: shmobile: r8a7790: Remove legacy +code") and 9d07d414d4c33d86 ("ARM: shmobile: r8a73a4: ape6evm: Remove +legacy platform"), the R-Mobile APE6 and R-Car H2 SoCs are supported by +multiplatform kernels only. +Hence we can drop checks for these SoCs in legacy kernel builds. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 20834a406ee20b57c796f9911f06600b71c75788) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/timer.c | 12 ------------ + 1 file changed, 12 deletions(-) + +diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c +index 0edf2a6d2bbe..f1d027aa7a81 100644 +--- a/arch/arm/mach-shmobile/timer.c ++++ b/arch/arm/mach-shmobile/timer.c +@@ -70,18 +70,6 @@ void __init shmobile_init_delay(void) + if (!max_freq) + return; + +-#ifdef CONFIG_ARCH_SHMOBILE_LEGACY +- /* Non-multiplatform r8a73a4 SoC cannot use arch timer due +- * to GIC being initialized from C and arch timer via DT */ +- if (of_machine_is_compatible("renesas,r8a73a4")) +- has_arch_timer = false; +- +- /* Non-multiplatform r8a7790 SoC cannot use arch timer due +- * to GIC being initialized from C and arch timer via DT */ +- if (of_machine_is_compatible("renesas,r8a7790")) +- has_arch_timer = false; +-#endif +- + if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) { + if (is_a7_a8_a9) + shmobile_setup_delay_hz(max_freq, 1, 3); +-- +2.6.2 + diff --git a/patches.renesas/0159-ARM-shmobile-Enable-gose-board-in-multiplatform-defc.patch b/patches.renesas/0159-ARM-shmobile-Enable-gose-board-in-multiplatform-defc.patch new file mode 100644 index 00000000000000..85dd4a5c37f0e6 --- /dev/null +++ b/patches.renesas/0159-ARM-shmobile-Enable-gose-board-in-multiplatform-defc.patch @@ -0,0 +1,30 @@ +From 4bf4188fa15a2cba131b42a836f0542fdc2fb233 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 2 Jun 2015 10:34:36 +0900 +Subject: [PATCH 159/326] ARM: shmobile: Enable gose board in multiplatform + defconfig + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b059be7ecfa80550f635194f7c12578423177729) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/shmobile_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig +index 9961fbd633f8..c8e9caeb1c02 100644 +--- a/arch/arm/configs/shmobile_defconfig ++++ b/arch/arm/configs/shmobile_defconfig +@@ -18,6 +18,7 @@ CONFIG_ARCH_R8A7778=y + CONFIG_ARCH_R8A7779=y + CONFIG_ARCH_R8A7790=y + CONFIG_ARCH_R8A7791=y ++CONFIG_ARCH_R8A7793=y + CONFIG_ARCH_R8A7794=y + CONFIG_ARCH_SH73A0=y + CONFIG_MACH_MARZEN=y +-- +2.6.2 + diff --git a/patches.renesas/0160-ARM-shmobile-add-r8a7793-minimal-SoC-device-tree.patch b/patches.renesas/0160-ARM-shmobile-add-r8a7793-minimal-SoC-device-tree.patch new file mode 100644 index 00000000000000..edf91420df4163 --- /dev/null +++ b/patches.renesas/0160-ARM-shmobile-add-r8a7793-minimal-SoC-device-tree.patch @@ -0,0 +1,567 @@ +From 02214f50f6f4bf271bee3776bdb8b4532eb186cd Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Mon, 1 Jun 2015 16:22:55 +0200 +Subject: [PATCH 160/326] ARM: shmobile: add r8a7793 minimal SoC device tree + +Minimal r8a7793 device tree including one CPU core, interrupt controllers, +timers, two serial ports, and the Ethernet controller, plus the required +clock descriptions. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0e03e8aed92ce4757a9dbfbf2b7f4edce6380f92) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7793.dtsi | 367 ++++++++++++++++++++++++++++++ + include/dt-bindings/clock/r8a7793-clock.h | 164 +++++++++++++ + 2 files changed, 531 insertions(+) + create mode 100644 arch/arm/boot/dts/r8a7793.dtsi + create mode 100644 include/dt-bindings/clock/r8a7793-clock.h + +diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi +new file mode 100644 +index 000000000000..c50c5f65388a +--- /dev/null ++++ b/arch/arm/boot/dts/r8a7793.dtsi +@@ -0,0 +1,367 @@ ++/* ++ * Device Tree Source for the r8a7793 SoC ++ * ++ * Copyright (C) 2014-2015 Renesas Electronics Corporation ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include <dt-bindings/clock/r8a7793-clock.h> ++#include <dt-bindings/interrupt-controller/arm-gic.h> ++#include <dt-bindings/interrupt-controller/irq.h> ++ ++/ { ++ compatible = "renesas,r8a7793"; ++ interrupt-parent = <&gic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a15"; ++ reg = <0>; ++ clock-frequency = <1500000000>; ++ voltage-tolerance = <1>; /* 1% */ ++ clocks = <&cpg_clocks R8A7793_CLK_Z>; ++ clock-latency = <300000>; /* 300 us */ ++ ++ /* kHz - uV - OPPs unknown yet */ ++ operating-points = <1500000 1000000>, ++ <1312500 1000000>, ++ <1125000 1000000>, ++ < 937500 1000000>, ++ < 750000 1000000>, ++ < 375000 1000000>; ++ }; ++ }; ++ ++ gic: interrupt-controller@f1001000 { ++ compatible = "arm,cortex-a15-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <0>; ++ interrupt-controller; ++ reg = <0 0xf1001000 0 0x1000>, ++ <0 0xf1002000 0 0x1000>, ++ <0 0xf1004000 0 0x2000>, ++ <0 0xf1006000 0 0x2000>; ++ interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; ++ }; ++ ++ timer { ++ compatible = "arm,armv7-timer"; ++ interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ++ <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ++ <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ++ <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; ++ }; ++ ++ cmt0: timer@ffca0000 { ++ compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; ++ reg = <0 0xffca0000 0 0x1004>; ++ interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, ++ <0 143 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp1_clks R8A7793_CLK_CMT0>; ++ clock-names = "fck"; ++ ++ renesas,channels-mask = <0x60>; ++ ++ status = "disabled"; ++ }; ++ ++ cmt1: timer@e6130000 { ++ compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; ++ reg = <0 0xe6130000 0 0x1004>; ++ interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, ++ <0 121 IRQ_TYPE_LEVEL_HIGH>, ++ <0 122 IRQ_TYPE_LEVEL_HIGH>, ++ <0 123 IRQ_TYPE_LEVEL_HIGH>, ++ <0 124 IRQ_TYPE_LEVEL_HIGH>, ++ <0 125 IRQ_TYPE_LEVEL_HIGH>, ++ <0 126 IRQ_TYPE_LEVEL_HIGH>, ++ <0 127 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp3_clks R8A7793_CLK_CMT1>; ++ clock-names = "fck"; ++ ++ renesas,channels-mask = <0xff>; ++ ++ status = "disabled"; ++ }; ++ ++ irqc0: interrupt-controller@e61c0000 { ++ compatible = "renesas,irqc-r8a7793", "renesas,irqc"; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ reg = <0 0xe61c0000 0 0x200>; ++ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, ++ <0 1 IRQ_TYPE_LEVEL_HIGH>, ++ <0 2 IRQ_TYPE_LEVEL_HIGH>, ++ <0 3 IRQ_TYPE_LEVEL_HIGH>, ++ <0 12 IRQ_TYPE_LEVEL_HIGH>, ++ <0 13 IRQ_TYPE_LEVEL_HIGH>, ++ <0 14 IRQ_TYPE_LEVEL_HIGH>, ++ <0 15 IRQ_TYPE_LEVEL_HIGH>, ++ <0 16 IRQ_TYPE_LEVEL_HIGH>, ++ <0 17 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp4_clks R8A7793_CLK_IRQC>; ++ }; ++ ++ scif0: serial@e6e60000 { ++ compatible = "renesas,scif-r8a7793", "renesas,scif"; ++ reg = <0 0xe6e60000 0 64>; ++ interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp7_clks R8A7793_CLK_SCIF0>; ++ clock-names = "sci_ick"; ++ status = "disabled"; ++ }; ++ ++ scif1: serial@e6e68000 { ++ compatible = "renesas,scif-r8a7793", "renesas,scif"; ++ reg = <0 0xe6e68000 0 64>; ++ interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp7_clks R8A7793_CLK_SCIF1>; ++ clock-names = "sci_ick"; ++ status = "disabled"; ++ }; ++ ++ ether: ethernet@ee700000 { ++ compatible = "renesas,ether-r8a7793"; ++ reg = <0 0xee700000 0 0x400>; ++ interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp8_clks R8A7793_CLK_ETHER>; ++ phy-mode = "rmii"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ clocks { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* External root clock */ ++ extal_clk: extal_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ /* This value must be overridden by the board. */ ++ clock-frequency = <0>; ++ clock-output-names = "extal"; ++ }; ++ ++ /* Special CPG clocks */ ++ cpg_clocks: cpg_clocks@e6150000 { ++ compatible = "renesas,r8a7793-cpg-clocks", ++ "renesas,rcar-gen2-cpg-clocks"; ++ reg = <0 0xe6150000 0 0x1000>; ++ clocks = <&extal_clk>; ++ #clock-cells = <1>; ++ clock-output-names = "main", "pll0", "pll1", "pll3", ++ "lb", "qspi", "sdh", "sd0", "z", ++ "rcan", "adsp"; ++ }; ++ ++ /* Variable factor clocks */ ++ sd2_clk: sd2_clk@e6150078 { ++ compatible = "renesas,r8a7793-div6-clock", ++ "renesas,cpg-div6-clock"; ++ reg = <0 0xe6150078 0 4>; ++ clocks = <&pll1_div2_clk>; ++ #clock-cells = <0>; ++ clock-output-names = "sd2"; ++ }; ++ sd3_clk: sd3_clk@e615026c { ++ compatible = "renesas,r8a7793-div6-clock", ++ "renesas,cpg-div6-clock"; ++ reg = <0 0xe615026c 0 4>; ++ clocks = <&pll1_div2_clk>; ++ #clock-cells = <0>; ++ clock-output-names = "sd3"; ++ }; ++ mmc0_clk: mmc0_clk@e6150240 { ++ compatible = "renesas,r8a7793-div6-clock", ++ "renesas,cpg-div6-clock"; ++ reg = <0 0xe6150240 0 4>; ++ clocks = <&pll1_div2_clk>; ++ #clock-cells = <0>; ++ clock-output-names = "mmc0"; ++ }; ++ ++ /* Fixed factor clocks */ ++ pll1_div2_clk: pll1_div2_clk { ++ compatible = "fixed-factor-clock"; ++ clocks = <&cpg_clocks R8A7793_CLK_PLL1>; ++ #clock-cells = <0>; ++ clock-div = <2>; ++ clock-mult = <1>; ++ clock-output-names = "pll1_div2"; ++ }; ++ zg_clk: zg_clk { ++ compatible = "fixed-factor-clock"; ++ clocks = <&cpg_clocks R8A7793_CLK_PLL1>; ++ #clock-cells = <0>; ++ clock-div = <5>; ++ clock-mult = <1>; ++ clock-output-names = "zg"; ++ }; ++ zx_clk: zx_clk { ++ compatible = "fixed-factor-clock"; ++ clocks = <&cpg_clocks R8A7793_CLK_PLL1>; ++ #clock-cells = <0>; ++ clock-div = <3>; ++ clock-mult = <1>; ++ clock-output-names = "zx"; ++ }; ++ zs_clk: zs_clk { ++ compatible = "fixed-factor-clock"; ++ clocks = <&cpg_clocks R8A7793_CLK_PLL1>; ++ #clock-cells = <0>; ++ clock-div = <6>; ++ clock-mult = <1>; ++ clock-output-names = "zs"; ++ }; ++ hp_clk: hp_clk { ++ compatible = "fixed-factor-clock"; ++ clocks = <&cpg_clocks R8A7793_CLK_PLL1>; ++ #clock-cells = <0>; ++ clock-div = <12>; ++ clock-mult = <1>; ++ clock-output-names = "hp"; ++ }; ++ p_clk: p_clk { ++ compatible = "fixed-factor-clock"; ++ clocks = <&cpg_clocks R8A7793_CLK_PLL1>; ++ #clock-cells = <0>; ++ clock-div = <24>; ++ clock-mult = <1>; ++ clock-output-names = "p"; ++ }; ++ rclk_clk: rclk_clk { ++ compatible = "fixed-factor-clock"; ++ clocks = <&cpg_clocks R8A7793_CLK_PLL1>; ++ #clock-cells = <0>; ++ clock-div = <(48 * 1024)>; ++ clock-mult = <1>; ++ clock-output-names = "rclk"; ++ }; ++ mp_clk: mp_clk { ++ compatible = "fixed-factor-clock"; ++ clocks = <&pll1_div2_clk>; ++ #clock-cells = <0>; ++ clock-div = <15>; ++ clock-mult = <1>; ++ clock-output-names = "mp"; ++ }; ++ cp_clk: cp_clk { ++ compatible = "fixed-factor-clock"; ++ clocks = <&extal_clk>; ++ #clock-cells = <0>; ++ clock-div = <2>; ++ clock-mult = <1>; ++ clock-output-names = "cp"; ++ }; ++ ++ /* Gate clocks */ ++ mstp1_clks: mstp1_clks@e6150134 { ++ compatible = "renesas,r8a7793-mstp-clocks", ++ "renesas,cpg-mstp-clocks"; ++ reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; ++ clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, ++ <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, ++ <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, ++ <&zs_clk>, <&zs_clk>, <&zs_clk>; ++ #clock-cells = <1>; ++ clock-indices = < ++ R8A7793_CLK_VCP0 R8A7793_CLK_VPC0 ++ R8A7793_CLK_SSP1 R8A7793_CLK_TMU1 ++ R8A7793_CLK_3DG R8A7793_CLK_2DDMAC ++ R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0 ++ R8A7793_CLK_TMU3 R8A7793_CLK_TMU2 ++ R8A7793_CLK_CMT0 R8A7793_CLK_TMU0 ++ R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0 ++ R8A7793_CLK_VSP1_S ++ >; ++ clock-output-names = ++ "vcp0", "vpc0", "ssp_dev", "tmu1", ++ "pvrsrvkm", "tddmac", "fdp1", "fdp0", ++ "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", ++ "vsp1-du0", "vsps"; ++ }; ++ mstp3_clks: mstp3_clks@e615013c { ++ compatible = "renesas,r8a7793-mstp-clocks", ++ "renesas,cpg-mstp-clocks"; ++ reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; ++ clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, ++ <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>, ++ <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, ++ <&rclk_clk>, <&hp_clk>, <&hp_clk>; ++ #clock-cells = <1>; ++ clock-indices = < ++ R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2 ++ R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0 ++ R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0 ++ R8A7793_CLK_PCIEC R8A7793_CLK_IIC1 ++ R8A7793_CLK_SSUSB R8A7793_CLK_CMT1 ++ R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1 ++ >; ++ clock-output-names = ++ "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", ++ "i2c7", "pciec", "i2c8", "ssusb", "cmt1", ++ "usbdmac0", "usbdmac1"; ++ }; ++ mstp4_clks: mstp4_clks@e6150140 { ++ compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; ++ reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; ++ clocks = <&cp_clk>; ++ #clock-cells = <1>; ++ clock-indices = <R8A7793_CLK_IRQC>; ++ clock-output-names = "irqc"; ++ }; ++ mstp7_clks: mstp7_clks@e615014c { ++ compatible = "renesas,r8a7793-mstp-clocks", ++ "renesas,cpg-mstp-clocks"; ++ reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; ++ clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, ++ <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, ++ <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, ++ <&zx_clk>, <&zx_clk>; ++ #clock-cells = <1>; ++ clock-indices = < ++ R8A7793_CLK_EHCI R8A7793_CLK_HSUSB ++ R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5 ++ R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1 ++ R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3 ++ R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1 ++ R8A7793_CLK_SCIF0 R8A7793_CLK_DU1 ++ R8A7793_CLK_DU0 R8A7793_CLK_LVDS0 ++ >; ++ clock-output-names = ++ "ehci", "hsusb", "hscif2", "scif5", "scif4", ++ "hscif1", "hscif0", "scif3", "scif2", ++ "scif1", "scif0", "du1", "du0", "lvds0"; ++ }; ++ mstp8_clks: mstp8_clks@e6150990 { ++ compatible = "renesas,r8a7793-mstp-clocks", ++ "renesas,cpg-mstp-clocks"; ++ reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; ++ clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, ++ <&p_clk>, <&zs_clk>, <&zs_clk>; ++ #clock-cells = <1>; ++ clock-indices = < ++ R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2 ++ R8A7793_CLK_VIN1 R8A7793_CLK_VIN0 ++ R8A7793_CLK_ETHER R8A7793_CLK_SATA1 ++ R8A7793_CLK_SATA0 ++ >; ++ clock-output-names = ++ "ipmmu_sgx", "vin2", "vin1", "vin0", "ether", ++ "sata1", "sata0"; ++ }; ++ }; ++ ++}; +diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h +new file mode 100644 +index 000000000000..1579e07f96a3 +--- /dev/null ++++ b/include/dt-bindings/clock/r8a7793-clock.h +@@ -0,0 +1,164 @@ ++/* ++ * r8a7793 clock definition ++ * ++ * Copyright (C) 2014 Renesas Electronics Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ ++#define __DT_BINDINGS_CLOCK_R8A7793_H__ ++ ++/* CPG */ ++#define R8A7793_CLK_MAIN 0 ++#define R8A7793_CLK_PLL0 1 ++#define R8A7793_CLK_PLL1 2 ++#define R8A7793_CLK_PLL3 3 ++#define R8A7793_CLK_LB 4 ++#define R8A7793_CLK_QSPI 5 ++#define R8A7793_CLK_SDH 6 ++#define R8A7793_CLK_SD0 7 ++#define R8A7793_CLK_Z 8 ++#define R8A7793_CLK_RCAN 9 ++#define R8A7793_CLK_ADSP 10 ++ ++/* MSTP0 */ ++#define R8A7793_CLK_MSIOF0 0 ++ ++/* MSTP1 */ ++#define R8A7793_CLK_VCP0 1 ++#define R8A7793_CLK_VPC0 3 ++#define R8A7793_CLK_SSP1 9 ++#define R8A7793_CLK_TMU1 11 ++#define R8A7793_CLK_3DG 12 ++#define R8A7793_CLK_2DDMAC 15 ++#define R8A7793_CLK_FDP1_1 18 ++#define R8A7793_CLK_FDP1_0 19 ++#define R8A7793_CLK_TMU3 21 ++#define R8A7793_CLK_TMU2 22 ++#define R8A7793_CLK_CMT0 24 ++#define R8A7793_CLK_TMU0 25 ++#define R8A7793_CLK_VSP1_DU1 27 ++#define R8A7793_CLK_VSP1_DU0 28 ++#define R8A7793_CLK_VSP1_S 31 ++ ++/* MSTP2 */ ++#define R8A7793_CLK_SCIFA2 2 ++#define R8A7793_CLK_SCIFA1 3 ++#define R8A7793_CLK_SCIFA0 4 ++#define R8A7793_CLK_MSIOF2 5 ++#define R8A7793_CLK_SCIFB0 6 ++#define R8A7793_CLK_SCIFB1 7 ++#define R8A7793_CLK_MSIOF1 8 ++#define R8A7793_CLK_SCIFB2 16 ++#define R8A7793_CLK_SYS_DMAC1 18 ++#define R8A7793_CLK_SYS_DMAC0 19 ++ ++/* MSTP3 */ ++#define R8A7793_CLK_TPU0 4 ++#define R8A7793_CLK_SDHI2 11 ++#define R8A7793_CLK_SDHI1 12 ++#define R8A7793_CLK_SDHI0 14 ++#define R8A7793_CLK_MMCIF0 15 ++#define R8A7793_CLK_IIC0 18 ++#define R8A7793_CLK_PCIEC 19 ++#define R8A7793_CLK_IIC1 23 ++#define R8A7793_CLK_SSUSB 28 ++#define R8A7793_CLK_CMT1 29 ++#define R8A7793_CLK_USBDMAC0 30 ++#define R8A7793_CLK_USBDMAC1 31 ++ ++/* MSTP4 */ ++#define R8A7793_CLK_IRQC 7 ++ ++/* MSTP5 */ ++#define R8A7793_CLK_AUDIO_DMAC1 1 ++#define R8A7793_CLK_AUDIO_DMAC0 2 ++#define R8A7793_CLK_ADSP_MOD 6 ++#define R8A7793_CLK_THERMAL 22 ++#define R8A7793_CLK_PWM 23 ++ ++/* MSTP7 */ ++#define R8A7793_CLK_EHCI 3 ++#define R8A7793_CLK_HSUSB 4 ++#define R8A7793_CLK_HSCIF2 13 ++#define R8A7793_CLK_SCIF5 14 ++#define R8A7793_CLK_SCIF4 15 ++#define R8A7793_CLK_HSCIF1 16 ++#define R8A7793_CLK_HSCIF0 17 ++#define R8A7793_CLK_SCIF3 18 ++#define R8A7793_CLK_SCIF2 19 ++#define R8A7793_CLK_SCIF1 20 ++#define R8A7793_CLK_SCIF0 21 ++#define R8A7793_CLK_DU1 23 ++#define R8A7793_CLK_DU0 24 ++#define R8A7793_CLK_LVDS0 26 ++ ++/* MSTP8 */ ++#define R8A7793_CLK_IPMMU_SGX 0 ++#define R8A7793_CLK_VIN2 9 ++#define R8A7793_CLK_VIN1 10 ++#define R8A7793_CLK_VIN0 11 ++#define R8A7793_CLK_ETHER 13 ++#define R8A7793_CLK_SATA1 14 ++#define R8A7793_CLK_SATA0 15 ++ ++/* MSTP9 */ ++#define R8A7793_CLK_GPIO7 4 ++#define R8A7793_CLK_GPIO6 5 ++#define R8A7793_CLK_GPIO5 7 ++#define R8A7793_CLK_GPIO4 8 ++#define R8A7793_CLK_GPIO3 9 ++#define R8A7793_CLK_GPIO2 10 ++#define R8A7793_CLK_GPIO1 11 ++#define R8A7793_CLK_GPIO0 12 ++#define R8A7793_CLK_RCAN1 15 ++#define R8A7793_CLK_RCAN0 16 ++#define R8A7793_CLK_QSPI_MOD 17 ++#define R8A7793_CLK_I2C5 25 ++#define R8A7793_CLK_IICDVFS 26 ++#define R8A7793_CLK_I2C4 27 ++#define R8A7793_CLK_I2C3 28 ++#define R8A7793_CLK_I2C2 29 ++#define R8A7793_CLK_I2C1 30 ++#define R8A7793_CLK_I2C0 31 ++ ++/* MSTP10 */ ++#define R8A7793_CLK_SSI_ALL 5 ++#define R8A7793_CLK_SSI9 6 ++#define R8A7793_CLK_SSI8 7 ++#define R8A7793_CLK_SSI7 8 ++#define R8A7793_CLK_SSI6 9 ++#define R8A7793_CLK_SSI5 10 ++#define R8A7793_CLK_SSI4 11 ++#define R8A7793_CLK_SSI3 12 ++#define R8A7793_CLK_SSI2 13 ++#define R8A7793_CLK_SSI1 14 ++#define R8A7793_CLK_SSI0 15 ++#define R8A7793_CLK_SCU_ALL 17 ++#define R8A7793_CLK_SCU_DVC1 18 ++#define R8A7793_CLK_SCU_DVC0 19 ++#define R8A7793_CLK_SCU_SRC9 22 ++#define R8A7793_CLK_SCU_SRC8 23 ++#define R8A7793_CLK_SCU_SRC7 24 ++#define R8A7793_CLK_SCU_SRC6 25 ++#define R8A7793_CLK_SCU_SRC5 26 ++#define R8A7793_CLK_SCU_SRC4 27 ++#define R8A7793_CLK_SCU_SRC3 28 ++#define R8A7793_CLK_SCU_SRC2 29 ++#define R8A7793_CLK_SCU_SRC1 30 ++#define R8A7793_CLK_SCU_SRC0 31 ++ ++/* MSTP11 */ ++#define R8A7793_CLK_SCIFA3 6 ++#define R8A7793_CLK_SCIFA4 7 ++#define R8A7793_CLK_SCIFA5 8 ++ ++#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */ +-- +2.6.2 + diff --git a/patches.renesas/0161-ARM-shmobile-r8a7793-add-minimal-Gose-board-device-t.patch b/patches.renesas/0161-ARM-shmobile-r8a7793-add-minimal-Gose-board-device-t.patch new file mode 100644 index 00000000000000..65a61875e18d41 --- /dev/null +++ b/patches.renesas/0161-ARM-shmobile-r8a7793-add-minimal-Gose-board-device-t.patch @@ -0,0 +1,104 @@ +From 3c1f622d64c4dfee3bcc26f5f4a0b8ba594ca4a9 Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Mon, 1 Jun 2015 16:22:56 +0200 +Subject: [PATCH 161/326] ARM: shmobile: r8a7793: add minimal Gose board device + tree + +Minimal DT description and Makefile entry for the Gose eval board. +Support for console, timer, and Ethernet. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b8af4591db5bb0529b7f56d25b2e7db3eb71fdf6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/r8a7793-gose.dts | 63 ++++++++++++++++++++++++++++++++++++++ + 2 files changed, 64 insertions(+) + create mode 100644 arch/arm/boot/dts/r8a7793-gose.dts + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index e13fff1bfa97..908fcbf656c1 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -490,6 +490,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ + r8a7790-lager.dtb \ + r8a7791-henninger.dtb \ + r8a7791-koelsch.dtb \ ++ r8a7793-gose.dtb \ + r8a7794-alt.dtb \ + sh73a0-kzm9g.dtb + dtb-$(CONFIG_ARCH_SOCFPGA) += \ +diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts +new file mode 100644 +index 000000000000..96443ec5f6ab +--- /dev/null ++++ b/arch/arm/boot/dts/r8a7793-gose.dts +@@ -0,0 +1,63 @@ ++/* ++ * Device Tree Source for the Gose board ++ * ++ * Copyright (C) 2014-2015 Renesas Electronics Corporation ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++#include "r8a7793.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/input.h> ++ ++/ { ++ model = "Gose"; ++ compatible = "renesas,gose", "renesas,r8a7793"; ++ ++ aliases { ++ serial0 = &scif0; ++ serial1 = &scif1; ++ }; ++ ++ chosen { ++ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; ++ stdout-path = &scif0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0 0x40000000 0 0x40000000>; ++ }; ++}; ++ ++&extal_clk { ++ clock-frequency = <20000000>; ++}; ++ ++ðer { ++ phy-handle = <&phy1>; ++ renesas,ether-link-active-low; ++ status = "okay"; ++ ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ interrupt-parent = <&irqc0>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ micrel,led-mode = <1>; ++ }; ++}; ++ ++&cmt0 { ++ status = "okay"; ++}; ++ ++&scif0 { ++ status = "okay"; ++}; ++ ++&scif1 { ++ status = "okay"; ++}; +-- +2.6.2 + diff --git a/patches.renesas/0162-ARM-shmobile-r8a7790-add-EtherAVB-clocks.patch b/patches.renesas/0162-ARM-shmobile-r8a7790-add-EtherAVB-clocks.patch new file mode 100644 index 00000000000000..e8b01c0717ed93 --- /dev/null +++ b/patches.renesas/0162-ARM-shmobile-r8a7790-add-EtherAVB-clocks.patch @@ -0,0 +1,60 @@ +From 72f66f2497ba6fbfd4c0dd4522b5eab8da8f3a16 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Tue, 16 Jun 2015 02:42:42 +0300 +Subject: [PATCH 162/326] ARM: shmobile: r8a7790: add EtherAVB clocks + +Add the EtherAVB clock to the R8A7790 device tree. + +Based on original patch by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 63d2d750c902dec77439f12b2eac9709468298ce) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 10 ++++++---- + include/dt-bindings/clock/r8a7790-clock.h | 1 + + 2 files changed, 7 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 51ab8865ea37..feb4652ed4b2 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -1249,16 +1249,18 @@ + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, +- <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; ++ <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, ++ <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 +- R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER ++ R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 ++ R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER + R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 + >; + clock-output-names = +- "mlb", "vin3", "vin2", "vin1", "vin0", "ether", +- "sata1", "sata0"; ++ "mlb", "vin3", "vin2", "vin1", "vin0", ++ "etheravb", "ether", "sata1", "sata0"; + }; + mstp9_clks: mstp9_clks@e6150994 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; +diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h +index ff7ca3584e16..e119ef372ba3 100644 +--- a/include/dt-bindings/clock/r8a7790-clock.h ++++ b/include/dt-bindings/clock/r8a7790-clock.h +@@ -108,6 +108,7 @@ + #define R8A7790_CLK_VIN2 9 + #define R8A7790_CLK_VIN1 10 + #define R8A7790_CLK_VIN0 11 ++#define R8A7790_CLK_ETHERAVB 12 + #define R8A7790_CLK_ETHER 13 + #define R8A7790_CLK_SATA1 14 + #define R8A7790_CLK_SATA0 15 +-- +2.6.2 + diff --git a/patches.renesas/0163-ARM-shmobile-r8a7790-add-EtherAVB-DT-support.patch b/patches.renesas/0163-ARM-shmobile-r8a7790-add-EtherAVB-DT-support.patch new file mode 100644 index 00000000000000..63a290bd677124 --- /dev/null +++ b/patches.renesas/0163-ARM-shmobile-r8a7790-add-EtherAVB-DT-support.patch @@ -0,0 +1,41 @@ +From 6ae35daadb510f5735c918fcbe1e474fb89b7c19 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Tue, 16 Jun 2015 02:43:51 +0300 +Subject: [PATCH 163/326] ARM: shmobile: r8a7790: add EtherAVB DT support + +Define the generic R8A7790 part of the EtherAVB device node. + +Based on original patch by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f25d6b977240117eb4b6e3111f4eb41f968d28fb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index feb4652ed4b2..c9aae06319c0 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -671,6 +671,16 @@ + status = "disabled"; + }; + ++ avb: ethernet@e6800000 { ++ compatible = "renesas,etheravb-r8a7790"; ++ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; ++ interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7790"; + reg = <0 0xee300000 0 0x2000>; +-- +2.6.2 + diff --git a/patches.renesas/0164-ARM-shmobile-armadillo800eva-dts-Add-pinctrl-and-gpi.patch b/patches.renesas/0164-ARM-shmobile-armadillo800eva-dts-Add-pinctrl-and-gpi.patch new file mode 100644 index 00000000000000..a57732348f2ea2 --- /dev/null +++ b/patches.renesas/0164-ARM-shmobile-armadillo800eva-dts-Add-pinctrl-and-gpi.patch @@ -0,0 +1,51 @@ +From 51bcd06769df2338b4624611d8bbf5ef14a7afde Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 10:38:56 +0200 +Subject: [PATCH 164/326] ARM: shmobile: armadillo800eva dts: Add pinctrl and + gpio-hog for lcdc0 + +Configure pinctrl and a GPIO-controller board mux for LCD use. +This allows the armadillo800eva board staging code to enable lcdc0. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ffd2f9a5afb730b9f6c1d1938934213c3cfcf249) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +index 2e31d8c01cbf..105d9c95de4a 100644 +--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts ++++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +@@ -224,6 +224,9 @@ + }; + + &pfc { ++ pinctrl-0 = <&lcd0_pins>; ++ pinctrl-names = "default"; ++ + ether_pins: ether { + renesas,groups = "gether_mii", "gether_int"; + renesas,function = "gether"; +@@ -259,6 +262,16 @@ + "fsia_data_in_1", "fsia_data_out_0"; + renesas,function = "fsia"; + }; ++ ++ lcd0_pins: lcd0 { ++ renesas,groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; ++ renesas,function = "lcd0"; ++ ++ /* DBGMD/LCDC0/FSIA MUX */ ++ gpio-hog; ++ gpios = <176 0>; ++ output-high; ++ }; + }; + + &tpu { +-- +2.6.2 + diff --git a/patches.renesas/0165-ARM-shmobile-r8a73a4-dtsi-Use-arm-gic-400-for-GIC.patch b/patches.renesas/0165-ARM-shmobile-r8a73a4-dtsi-Use-arm-gic-400-for-GIC.patch new file mode 100644 index 00000000000000..a8a661d8501a41 --- /dev/null +++ b/patches.renesas/0165-ARM-shmobile-r8a73a4-dtsi-Use-arm-gic-400-for-GIC.patch @@ -0,0 +1,38 @@ +From 337411a2e28f983c61aa7138fd36abfe87434337 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 15:03:32 +0200 +Subject: [PATCH 165/326] ARM: shmobile: r8a73a4 dtsi: Use "arm,gic-400" for + GIC + +Replace the "arm,cortex-a15-gic" compatible value for the GIC by +"arm,gic-400", as the documentation states it's a GIC-400. +This has been confirmed by reading the GICD_IIDR register, which reports +0x0200043b (GIC-400 = 0x02, ARM = 0x43b). + +This has no effect on runtime behavior, as currently the GIC driver +treats both compatible values the same. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit eaec1d675c194965081297014503938a9f58e2f7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a73a4.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi +index 7ee22a41c6c9..5090d1a8f652 100644 +--- a/arch/arm/boot/dts/r8a73a4.dtsi ++++ b/arch/arm/boot/dts/r8a73a4.dtsi +@@ -434,7 +434,7 @@ + }; + + gic: interrupt-controller@f1001000 { +- compatible = "arm,cortex-a15-gic"; ++ compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; +-- +2.6.2 + diff --git a/patches.renesas/0166-ARM-shmobile-r8a7790-dtsi-Use-arm-gic-400-for-GIC.patch b/patches.renesas/0166-ARM-shmobile-r8a7790-dtsi-Use-arm-gic-400-for-GIC.patch new file mode 100644 index 00000000000000..0be55508fb568c --- /dev/null +++ b/patches.renesas/0166-ARM-shmobile-r8a7790-dtsi-Use-arm-gic-400-for-GIC.patch @@ -0,0 +1,38 @@ +From e9ddf1d690f61c3c4c8a0165f9c7979873ecdab4 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 15:03:33 +0200 +Subject: [PATCH 166/326] ARM: shmobile: r8a7790 dtsi: Use "arm,gic-400" for + GIC + +Replace the "arm,cortex-a15-gic" compatible value for the GIC by +"arm,gic-400", as the R-Car Gen2 GIC is assumed to be a GIC-400. +This has been confirmed by reading the GICD_IIDR register (on r8a7791), +which reports 0x0200043b (GIC-400 = 0x02, ARM = 0x43b). + +This has no effect on runtime behavior, as currently the GIC driver +treats both compatible values the same. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e715e9c57826cc3370fc5fcdb9d57602d52bba9a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index c9aae06319c0..3ae0c3bfb9b9 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -113,7 +113,7 @@ + }; + + gic: interrupt-controller@f1001000 { +- compatible = "arm,cortex-a15-gic"; ++ compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; +-- +2.6.2 + diff --git a/patches.renesas/0167-ARM-shmobile-r8a7791-dtsi-Use-arm-gic-400-for-GIC.patch b/patches.renesas/0167-ARM-shmobile-r8a7791-dtsi-Use-arm-gic-400-for-GIC.patch new file mode 100644 index 00000000000000..7516c9bcdc12cc --- /dev/null +++ b/patches.renesas/0167-ARM-shmobile-r8a7791-dtsi-Use-arm-gic-400-for-GIC.patch @@ -0,0 +1,38 @@ +From 03dc21d17cd0f8389fc8f0151fe3f065eebdd797 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 15:03:34 +0200 +Subject: [PATCH 167/326] ARM: shmobile: r8a7791 dtsi: Use "arm,gic-400" for + GIC + +Replace the "arm,cortex-a15-gic" compatible value for the GIC by +"arm,gic-400", as the R-Car Gen2 GIC is assumed to be a GIC-400. +This has been confirmed by reading the GICD_IIDR register, which reports +0x0200043b (GIC-400 = 0x02, ARM = 0x43b). + +This has no effect on runtime behavior, as currently the GIC driver +treats both compatible values the same. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d238b5e628c98c39fe669610e6ab8e06a6f00b5b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi +index dc1cd3f16606..07ea2bebe496 100644 +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -70,7 +70,7 @@ + }; + + gic: interrupt-controller@f1001000 { +- compatible = "arm,cortex-a15-gic"; ++ compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; +-- +2.6.2 + diff --git a/patches.renesas/0168-ARM-shmobile-r8a7793-dtsi-Use-arm-gic-400-for-GIC.patch b/patches.renesas/0168-ARM-shmobile-r8a7793-dtsi-Use-arm-gic-400-for-GIC.patch new file mode 100644 index 00000000000000..a52070d9bfbe4e --- /dev/null +++ b/patches.renesas/0168-ARM-shmobile-r8a7793-dtsi-Use-arm-gic-400-for-GIC.patch @@ -0,0 +1,38 @@ +From 3d8fecf49965104f90237a51f42a2afea8d6df8a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 15:03:35 +0200 +Subject: [PATCH 168/326] ARM: shmobile: r8a7793 dtsi: Use "arm,gic-400" for + GIC + +Replace the "arm,cortex-a15-gic" compatible value for the GIC by +"arm,gic-400", as the R-Car Gen2 GIC is assumed to be a GIC-400. +This has been confirmed by reading the GICD_IIDR register (on r8a7791), +which reports 0x0200043b (GIC-400 = 0x02, ARM = 0x43b). + +This has no effect on runtime behavior, as currently the GIC driver +treats both compatible values the same. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5b3b3268518fb67c7accf83d786909b2a8cbee63) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7793.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi +index c50c5f65388a..3355c487d108 100644 +--- a/arch/arm/boot/dts/r8a7793.dtsi ++++ b/arch/arm/boot/dts/r8a7793.dtsi +@@ -42,7 +42,7 @@ + }; + + gic: interrupt-controller@f1001000 { +- compatible = "arm,cortex-a15-gic"; ++ compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; +-- +2.6.2 + diff --git a/patches.renesas/0169-ARM-shmobile-r8a7794-dtsi-Use-arm-gic-400-for-GIC.patch b/patches.renesas/0169-ARM-shmobile-r8a7794-dtsi-Use-arm-gic-400-for-GIC.patch new file mode 100644 index 00000000000000..f1c5d4bbaedbfd --- /dev/null +++ b/patches.renesas/0169-ARM-shmobile-r8a7794-dtsi-Use-arm-gic-400-for-GIC.patch @@ -0,0 +1,38 @@ +From 712df600e9b78d7d724daa483b8a2d329d3d36c3 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 17 Jun 2015 15:03:36 +0200 +Subject: [PATCH 169/326] ARM: shmobile: r8a7794 dtsi: Use "arm,gic-400" for + GIC + +Replace the "arm,cortex-a15-gic" compatible value for the GIC by +"arm,gic-400", as the R-Car Gen2 GIC is assumed to be a GIC-400. +This has been confirmed by reading the GICD_IIDR register (on r8a7791), +which reports 0x0200043b (GIC-400 = 0x02, ARM = 0x43b). + +This has no effect on runtime behavior, as currently the GIC driver +treats both compatible values the same. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c73ddf42e7a93dabf918b22d3cc2ce02b90d4155) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi +index b73819423311..8824dbd5dbb4 100644 +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -39,7 +39,7 @@ + }; + + gic: interrupt-controller@f1001000 { +- compatible = "arm,cortex-a7-gic"; ++ compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; +-- +2.6.2 + diff --git a/patches.renesas/0170-ARM-shmobile-r8a7779-Configure-IRLM-mode-via-DT.patch b/patches.renesas/0170-ARM-shmobile-r8a7779-Configure-IRLM-mode-via-DT.patch new file mode 100644 index 00000000000000..a6e209e28ee858 --- /dev/null +++ b/patches.renesas/0170-ARM-shmobile-r8a7779-Configure-IRLM-mode-via-DT.patch @@ -0,0 +1,43 @@ +From da3d4b074d7a77846fc37cad2f777aac83e2a9db Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm+renesas@opensource.se> +Date: Thu, 25 Jun 2015 17:57:28 +0900 +Subject: [PATCH 170/326] ARM: shmobile: r8a7779: Configure IRLM mode via DT + +Adjust the r8a7779 SoC DTS and the Marzen Reference +C board code to use DTS only for INTC-IRQPIN IRLM setup. + +Signed-off-by: Magnus Damm <damm+renesas@opensource.se> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7bf46d0be278a3586c78322c65ceff5fd03bb95d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7779.dtsi | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi +index 5c8071e87ae9..a2b5430d3257 100644 +--- a/arch/arm/boot/dts/r8a7779.dtsi ++++ b/arch/arm/boot/dts/r8a7779.dtsi +@@ -148,7 +148,7 @@ + interrupt-controller; + }; + +- irqpin0: interrupt-controller@fe780010 { ++ irqpin0: interrupt-controller@fe78001c { + compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; + #interrupt-cells = <2>; + status = "disabled"; +@@ -157,7 +157,8 @@ + <0xfe780010 4>, + <0xfe780024 4>, + <0xfe780044 4>, +- <0xfe780064 4>; ++ <0xfe780064 4>, ++ <0xfe780000 4>; + interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH + 0 28 IRQ_TYPE_LEVEL_HIGH + 0 29 IRQ_TYPE_LEVEL_HIGH +-- +2.6.2 + diff --git a/patches.renesas/0171-ARM-shmobile-R-Car-Improve-documentation.patch b/patches.renesas/0171-ARM-shmobile-R-Car-Improve-documentation.patch new file mode 100644 index 00000000000000..823fa3b800dd07 --- /dev/null +++ b/patches.renesas/0171-ARM-shmobile-R-Car-Improve-documentation.patch @@ -0,0 +1,119 @@ +From a04ef1ce6d66704579c743fa379ab88f43468ffe Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 4 Jun 2015 20:22:27 +0200 +Subject: [PATCH 171/326] ARM: shmobile: R-Car: Improve documentation + +Add more SYSC register documentation. +Use definitions instead of hardcoded numbers. +Comment important operations. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 577d104d85f05c1de6e56784a5da3e0fb4746f3a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/pm-rcar.c | 46 ++++++++++++++++++++++++++++------------ + 1 file changed, 32 insertions(+), 14 deletions(-) + +diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c +index 00022ee56f80..56ea82a851cb 100644 +--- a/arch/arm/mach-shmobile/pm-rcar.c ++++ b/arch/arm/mach-shmobile/pm-rcar.c +@@ -15,21 +15,35 @@ + #include <asm/io.h> + #include "pm-rcar.h" + +-/* SYSC */ +-#define SYSCSR 0x00 +-#define SYSCISR 0x04 +-#define SYSCISCR 0x08 ++/* SYSC Common */ ++#define SYSCSR 0x00 /* SYSC Status Register */ ++#define SYSCISR 0x04 /* Interrupt Status Register */ ++#define SYSCISCR 0x08 /* Interrupt Status Clear Register */ ++#define SYSCIER 0x0c /* Interrupt Enable Register */ ++#define SYSCIMR 0x10 /* Interrupt Mask Register */ + +-#define PWRSR_OFFS 0x00 +-#define PWROFFCR_OFFS 0x04 +-#define PWRONCR_OFFS 0x0c +-#define PWRER_OFFS 0x14 ++/* SYSC Status Register */ ++#define SYSCSR_PONENB 1 /* Ready for power resume requests */ ++#define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */ + +-#define SYSCSR_RETRIES 100 +-#define SYSCSR_DELAY_US 1 ++/* ++ * Power Control Register Offsets inside the register block for each domain ++ * Note: The "CR" registers for ARM cores exist on H1 only ++ * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2 ++ */ ++#define PWRSR_OFFS 0x00 /* Power Status Register */ ++#define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */ ++#define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */ ++#define PWRONCR_OFFS 0x0c /* Power Resume Control Register */ ++#define PWRONSR_OFFS 0x10 /* Power Resume Status Register */ ++#define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */ ++ ++ ++#define SYSCSR_RETRIES 100 ++#define SYSCSR_DELAY_US 1 + +-#define SYSCISR_RETRIES 1000 +-#define SYSCISR_DELAY_US 1 ++#define SYSCISR_RETRIES 1000 ++#define SYSCISR_DELAY_US 1 + + static void __iomem *rcar_sysc_base; + static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */ +@@ -39,6 +53,7 @@ static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch, + { + int k; + ++ /* Wait until SYSC is ready to accept a power request */ + for (k = 0; k < SYSCSR_RETRIES; k++) { + if (ioread32(rcar_sysc_base + SYSCSR) & (1 << sr_bit)) + break; +@@ -48,6 +63,7 @@ static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch, + if (k == SYSCSR_RETRIES) + return -EAGAIN; + ++ /* Submit power shutoff or power resume request */ + iowrite32(1 << sysc_ch->chan_bit, + rcar_sysc_base + sysc_ch->chan_offs + reg_offs); + +@@ -56,12 +72,12 @@ static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch, + + static int rcar_sysc_pwr_off(struct rcar_sysc_ch *sysc_ch) + { +- return rcar_sysc_pwr_on_off(sysc_ch, 0, PWROFFCR_OFFS); ++ return rcar_sysc_pwr_on_off(sysc_ch, SYSCSR_POFFENB, PWROFFCR_OFFS); + } + + static int rcar_sysc_pwr_on(struct rcar_sysc_ch *sysc_ch) + { +- return rcar_sysc_pwr_on_off(sysc_ch, 1, PWRONCR_OFFS); ++ return rcar_sysc_pwr_on_off(sysc_ch, SYSCSR_PONENB, PWRONCR_OFFS); + } + + static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch, +@@ -78,6 +94,7 @@ static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch, + + iowrite32(isr_mask, rcar_sysc_base + SYSCISCR); + ++ /* Submit power shutoff or resume request until it was accepted */ + do { + ret = on_off_fn(sysc_ch); + if (ret) +@@ -87,6 +104,7 @@ static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch, + sysc_ch->chan_offs + PWRER_OFFS); + } while (status & chan_mask); + ++ /* Wait until the power shutoff or resume request has completed * */ + for (k = 0; k < SYSCISR_RETRIES; k++) { + if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask) + break; +-- +2.6.2 + diff --git a/patches.renesas/0172-ARM-shmobile-R-Car-Shrink-rcar_sysc_ch-size.patch b/patches.renesas/0172-ARM-shmobile-R-Car-Shrink-rcar_sysc_ch-size.patch new file mode 100644 index 00000000000000..3e85d6ea967a5d --- /dev/null +++ b/patches.renesas/0172-ARM-shmobile-R-Car-Shrink-rcar_sysc_ch-size.patch @@ -0,0 +1,42 @@ +From 2bda62352aa85d11082301494c663684a716fcd5 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 4 Jun 2015 20:22:28 +0200 +Subject: [PATCH 172/326] ARM: shmobile: R-Car: Shrink rcar_sysc_ch size + +Shrink the individual fields in struct rcar_sysc_ch, as unsigned long or +int is overkill: + - chan_offs contains a register offset relative to a base value + (< 512), + - chan_bit and isr_bit contain bit indices (0-31). + +This reduces the size of each instance from 3 (4 on 64-bit) 32-bit words +to 1 32-bit word. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6fd2242e60e89a26e731e57dbf8f88d6639e09de) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/pm-rcar.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-shmobile/pm-rcar.h b/arch/arm/mach-shmobile/pm-rcar.h +index ef3a1ef628f1..06ebf00a6a5a 100644 +--- a/arch/arm/mach-shmobile/pm-rcar.h ++++ b/arch/arm/mach-shmobile/pm-rcar.h +@@ -2,9 +2,9 @@ + #define PM_RCAR_H + + struct rcar_sysc_ch { +- unsigned long chan_offs; +- unsigned int chan_bit; +- unsigned int isr_bit; ++ u16 chan_offs; ++ u8 chan_bit; ++ u8 isr_bit; + }; + + int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch); +-- +2.6.2 + diff --git a/patches.renesas/0173-ARM-shmobile-R-Car-Break-infinite-loop.patch b/patches.renesas/0173-ARM-shmobile-R-Car-Break-infinite-loop.patch new file mode 100644 index 00000000000000..78d0b349c04c72 --- /dev/null +++ b/patches.renesas/0173-ARM-shmobile-R-Car-Break-infinite-loop.patch @@ -0,0 +1,64 @@ +From c0ed352b2786ae5da793bdbb8c33f8a44ee216b2 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 4 Jun 2015 20:22:29 +0200 +Subject: [PATCH 173/326] ARM: shmobile: R-Car: Break infinite loop + +rcar_sysc_update() loops (with interrupts disabled and while holding a +spinlock) until submitting a power shutoff or resume request fails, or +until the submitted request was accepted. +If none of these conditions becomes true, this forms an infinite loop. + +Put a limit on the maximum number of loop iterations, and add a small +delay to each iteration, to fix this. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 2f575fcff1fad24e97b8e7d793ad9af9ae5b8a17) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/pm-rcar.c | 16 ++++++++++++++-- + 1 file changed, 14 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c +index 56ea82a851cb..a5e4c3a88ec4 100644 +--- a/arch/arm/mach-shmobile/pm-rcar.c ++++ b/arch/arm/mach-shmobile/pm-rcar.c +@@ -42,6 +42,9 @@ + #define SYSCSR_RETRIES 100 + #define SYSCSR_DELAY_US 1 + ++#define PWRER_RETRIES 100 ++#define PWRER_DELAY_US 1 ++ + #define SYSCISR_RETRIES 1000 + #define SYSCISR_DELAY_US 1 + +@@ -95,14 +98,23 @@ static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch, + iowrite32(isr_mask, rcar_sysc_base + SYSCISCR); + + /* Submit power shutoff or resume request until it was accepted */ +- do { ++ for (k = 0; k < PWRER_RETRIES; k++) { + ret = on_off_fn(sysc_ch); + if (ret) + goto out; + + status = ioread32(rcar_sysc_base + + sysc_ch->chan_offs + PWRER_OFFS); +- } while (status & chan_mask); ++ if (!(status & chan_mask)) ++ break; ++ ++ udelay(PWRER_DELAY_US); ++ } ++ ++ if (k == PWRER_RETRIES) { ++ ret = -EIO; ++ goto out; ++ } + + /* Wait until the power shutoff or resume request has completed * */ + for (k = 0; k < SYSCISR_RETRIES; k++) { +-- +2.6.2 + diff --git a/patches.renesas/0174-ARM-shmobile-R-Car-Make-struct-rcar_sysc_ch-paramete.patch b/patches.renesas/0174-ARM-shmobile-R-Car-Make-struct-rcar_sysc_ch-paramete.patch new file mode 100644 index 00000000000000..13f59966f231ff --- /dev/null +++ b/patches.renesas/0174-ARM-shmobile-R-Car-Make-struct-rcar_sysc_ch-paramete.patch @@ -0,0 +1,94 @@ +From 488804a26d9f2e5257f65ba3bf6fff9e09cf4bc0 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 4 Jun 2015 20:22:30 +0200 +Subject: [PATCH 174/326] ARM: shmobile: R-Car: Make struct rcar_sysc_ch * + parameters const + +The passed struct rcar_sysc_ch is never modified, so it can be const. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 624deb39a1c684b42569a3ec6a0fdcc74b950ed3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/pm-rcar.c | 16 ++++++++-------- + arch/arm/mach-shmobile/pm-rcar.h | 6 +++--- + 2 files changed, 11 insertions(+), 11 deletions(-) + +diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c +index a5e4c3a88ec4..b1a7f2a7f757 100644 +--- a/arch/arm/mach-shmobile/pm-rcar.c ++++ b/arch/arm/mach-shmobile/pm-rcar.c +@@ -51,7 +51,7 @@ + static void __iomem *rcar_sysc_base; + static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */ + +-static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch, ++static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, + int sr_bit, int reg_offs) + { + int k; +@@ -73,18 +73,18 @@ static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch, + return 0; + } + +-static int rcar_sysc_pwr_off(struct rcar_sysc_ch *sysc_ch) ++static int rcar_sysc_pwr_off(const struct rcar_sysc_ch *sysc_ch) + { + return rcar_sysc_pwr_on_off(sysc_ch, SYSCSR_POFFENB, PWROFFCR_OFFS); + } + +-static int rcar_sysc_pwr_on(struct rcar_sysc_ch *sysc_ch) ++static int rcar_sysc_pwr_on(const struct rcar_sysc_ch *sysc_ch) + { + return rcar_sysc_pwr_on_off(sysc_ch, SYSCSR_PONENB, PWRONCR_OFFS); + } + +-static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch, +- int (*on_off_fn)(struct rcar_sysc_ch *)) ++static int rcar_sysc_update(const struct rcar_sysc_ch *sysc_ch, ++ int (*on_off_fn)(const struct rcar_sysc_ch *)) + { + unsigned int isr_mask = 1 << sysc_ch->isr_bit; + unsigned int chan_mask = 1 << sysc_ch->chan_bit; +@@ -136,17 +136,17 @@ static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch, + return ret; + } + +-int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch) ++int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch) + { + return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_off); + } + +-int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch) ++int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch) + { + return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_on); + } + +-bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch) ++bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch) + { + unsigned int st; + +diff --git a/arch/arm/mach-shmobile/pm-rcar.h b/arch/arm/mach-shmobile/pm-rcar.h +index 06ebf00a6a5a..1b901db4a24c 100644 +--- a/arch/arm/mach-shmobile/pm-rcar.h ++++ b/arch/arm/mach-shmobile/pm-rcar.h +@@ -7,9 +7,9 @@ struct rcar_sysc_ch { + u8 isr_bit; + }; + +-int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch); +-int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch); +-bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch); ++int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch); ++int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch); ++bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch); + void __iomem *rcar_sysc_init(phys_addr_t base); + + #endif /* PM_RCAR_H */ +-- +2.6.2 + diff --git a/patches.renesas/0175-ARM-shmobile-R-Car-Use-BIT-macro-instead-of-open-cod.patch b/patches.renesas/0175-ARM-shmobile-R-Car-Use-BIT-macro-instead-of-open-cod.patch new file mode 100644 index 00000000000000..807e9232a0c6ce --- /dev/null +++ b/patches.renesas/0175-ARM-shmobile-R-Car-Use-BIT-macro-instead-of-open-cod.patch @@ -0,0 +1,59 @@ +From 59880f19d1a261647e375ccb6f373fca7d509a31 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 4 Jun 2015 20:22:31 +0200 +Subject: [PATCH 175/326] ARM: shmobile: R-Car: Use BIT() macro instead of open + coding + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 21437c53f3dc2e1e52ccb8aed0a65dd3879ca671) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/pm-rcar.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c +index b1a7f2a7f757..7adf9ce5fc1d 100644 +--- a/arch/arm/mach-shmobile/pm-rcar.c ++++ b/arch/arm/mach-shmobile/pm-rcar.c +@@ -58,7 +58,7 @@ static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, + + /* Wait until SYSC is ready to accept a power request */ + for (k = 0; k < SYSCSR_RETRIES; k++) { +- if (ioread32(rcar_sysc_base + SYSCSR) & (1 << sr_bit)) ++ if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit)) + break; + udelay(SYSCSR_DELAY_US); + } +@@ -67,7 +67,7 @@ static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, + return -EAGAIN; + + /* Submit power shutoff or power resume request */ +- iowrite32(1 << sysc_ch->chan_bit, ++ iowrite32(BIT(sysc_ch->chan_bit), + rcar_sysc_base + sysc_ch->chan_offs + reg_offs); + + return 0; +@@ -86,8 +86,8 @@ static int rcar_sysc_pwr_on(const struct rcar_sysc_ch *sysc_ch) + static int rcar_sysc_update(const struct rcar_sysc_ch *sysc_ch, + int (*on_off_fn)(const struct rcar_sysc_ch *)) + { +- unsigned int isr_mask = 1 << sysc_ch->isr_bit; +- unsigned int chan_mask = 1 << sysc_ch->chan_bit; ++ unsigned int isr_mask = BIT(sysc_ch->isr_bit); ++ unsigned int chan_mask = BIT(sysc_ch->chan_bit); + unsigned int status; + unsigned long flags; + int ret = 0; +@@ -151,7 +151,7 @@ bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch) + unsigned int st; + + st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS); +- if (st & (1 << sysc_ch->chan_bit)) ++ if (st & BIT(sysc_ch->chan_bit)) + return true; + + return false; +-- +2.6.2 + diff --git a/patches.renesas/0176-ARM-shmobile-R-Car-Get-rid-of-on_off_fn-function-poi.patch b/patches.renesas/0176-ARM-shmobile-R-Car-Get-rid-of-on_off_fn-function-poi.patch new file mode 100644 index 00000000000000..dbca0fb91cadaa --- /dev/null +++ b/patches.renesas/0176-ARM-shmobile-R-Car-Get-rid-of-on_off_fn-function-poi.patch @@ -0,0 +1,95 @@ +From ef2015a1b01f8308a1f764faf2e192350a26f855 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 4 Jun 2015 20:22:32 +0200 +Subject: [PATCH 176/326] ARM: shmobile: R-Car: Get rid of on_off_fn() function + pointer + +Simplify the power request code by passing an "on" flag, and picking the +right status bit and register offset in the innermost function, based on +this flag. +This allows to remove the rcar_sysc_pwr_{off,on}() helper functions, and +the function pointer through which they were called. + +Make sr_bit and reg_offs unsigned while we're at it. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit bcb8243792eaa855a51c96bfeaa5dbca19f48d07) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/pm-rcar.c | 31 ++++++++++++++----------------- + 1 file changed, 14 insertions(+), 17 deletions(-) + +diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c +index 7adf9ce5fc1d..4092ad16e0a4 100644 +--- a/arch/arm/mach-shmobile/pm-rcar.c ++++ b/arch/arm/mach-shmobile/pm-rcar.c +@@ -51,11 +51,19 @@ + static void __iomem *rcar_sysc_base; + static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */ + +-static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, +- int sr_bit, int reg_offs) ++static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on) + { ++ unsigned int sr_bit, reg_offs; + int k; + ++ if (on) { ++ sr_bit = SYSCSR_PONENB; ++ reg_offs = PWRONCR_OFFS; ++ } else { ++ sr_bit = SYSCSR_POFFENB; ++ reg_offs = PWROFFCR_OFFS; ++ } ++ + /* Wait until SYSC is ready to accept a power request */ + for (k = 0; k < SYSCSR_RETRIES; k++) { + if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit)) +@@ -73,18 +81,7 @@ static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, + return 0; + } + +-static int rcar_sysc_pwr_off(const struct rcar_sysc_ch *sysc_ch) +-{ +- return rcar_sysc_pwr_on_off(sysc_ch, SYSCSR_POFFENB, PWROFFCR_OFFS); +-} +- +-static int rcar_sysc_pwr_on(const struct rcar_sysc_ch *sysc_ch) +-{ +- return rcar_sysc_pwr_on_off(sysc_ch, SYSCSR_PONENB, PWRONCR_OFFS); +-} +- +-static int rcar_sysc_update(const struct rcar_sysc_ch *sysc_ch, +- int (*on_off_fn)(const struct rcar_sysc_ch *)) ++static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on) + { + unsigned int isr_mask = BIT(sysc_ch->isr_bit); + unsigned int chan_mask = BIT(sysc_ch->chan_bit); +@@ -99,7 +96,7 @@ static int rcar_sysc_update(const struct rcar_sysc_ch *sysc_ch, + + /* Submit power shutoff or resume request until it was accepted */ + for (k = 0; k < PWRER_RETRIES; k++) { +- ret = on_off_fn(sysc_ch); ++ ret = rcar_sysc_pwr_on_off(sysc_ch, on); + if (ret) + goto out; + +@@ -138,12 +135,12 @@ static int rcar_sysc_update(const struct rcar_sysc_ch *sysc_ch, + + int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch) + { +- return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_off); ++ return rcar_sysc_power(sysc_ch, false); + } + + int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch) + { +- return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_on); ++ return rcar_sysc_power(sysc_ch, true); + } + + bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch) +-- +2.6.2 + diff --git a/patches.renesas/0177-ARM-shmobile-r8a7779-Make-struct-rcar_sysc_ch-const.patch b/patches.renesas/0177-ARM-shmobile-r8a7779-Make-struct-rcar_sysc_ch-const.patch new file mode 100644 index 00000000000000..99f370682650b1 --- /dev/null +++ b/patches.renesas/0177-ARM-shmobile-r8a7779-Make-struct-rcar_sysc_ch-const.patch @@ -0,0 +1,84 @@ +From 1aaf7a059d863841059481783255e526b66ba7ce Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 4 Jun 2015 20:22:34 +0200 +Subject: [PATCH 177/326] ARM: shmobile: r8a7779: Make struct rcar_sysc_ch + const + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5afcd90f65ac990ca08b101a0e0fd9eac4e0dcde) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/pm-r8a7779.c | 3 ++- + arch/arm/mach-shmobile/smp-r8a7779.c | 12 ++++++------ + 2 files changed, 8 insertions(+), 7 deletions(-) + +diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c +index d5f258e4d890..47a862e7f8ba 100644 +--- a/arch/arm/mach-shmobile/pm-r8a7779.c ++++ b/arch/arm/mach-shmobile/pm-r8a7779.c +@@ -35,7 +35,8 @@ struct r8a7779_pm_domain { + struct rcar_sysc_ch ch; + }; + +-static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d) ++static inline ++const struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d) + { + return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; + } +diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c +index 01f792fcb220..9122216df060 100644 +--- a/arch/arm/mach-shmobile/smp-r8a7779.c ++++ b/arch/arm/mach-shmobile/smp-r8a7779.c +@@ -32,25 +32,25 @@ + #define AVECR IOMEM(0xfe700040) + #define R8A7779_SCU_BASE 0xf0000000 + +-static struct rcar_sysc_ch r8a7779_ch_cpu1 = { ++static const struct rcar_sysc_ch r8a7779_ch_cpu1 = { + .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ + .chan_bit = 1, /* ARM1 */ + .isr_bit = 1, /* ARM1 */ + }; + +-static struct rcar_sysc_ch r8a7779_ch_cpu2 = { ++static const struct rcar_sysc_ch r8a7779_ch_cpu2 = { + .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ + .chan_bit = 2, /* ARM2 */ + .isr_bit = 2, /* ARM2 */ + }; + +-static struct rcar_sysc_ch r8a7779_ch_cpu3 = { ++static const struct rcar_sysc_ch r8a7779_ch_cpu3 = { + .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ + .chan_bit = 3, /* ARM3 */ + .isr_bit = 3, /* ARM3 */ + }; + +-static struct rcar_sysc_ch *r8a7779_ch_cpu[4] = { ++static const struct rcar_sysc_ch * const r8a7779_ch_cpu[4] = { + [1] = &r8a7779_ch_cpu1, + [2] = &r8a7779_ch_cpu2, + [3] = &r8a7779_ch_cpu3, +@@ -66,7 +66,7 @@ void __init r8a7779_register_twd(void) + + static int r8a7779_platform_cpu_kill(unsigned int cpu) + { +- struct rcar_sysc_ch *ch = NULL; ++ const struct rcar_sysc_ch *ch = NULL; + int ret = -EIO; + + cpu = cpu_logical_map(cpu); +@@ -82,7 +82,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) + + static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) + { +- struct rcar_sysc_ch *ch = NULL; ++ const struct rcar_sysc_ch *ch = NULL; + unsigned int lcpu = cpu_logical_map(cpu); + int ret; + +-- +2.6.2 + diff --git a/patches.renesas/0178-ARM-shmobile-r8a7790-Make-struct-rcar_sysc_ch-const.patch b/patches.renesas/0178-ARM-shmobile-r8a7790-Make-struct-rcar_sysc_ch-const.patch new file mode 100644 index 00000000000000..f77ef8da8d0cec --- /dev/null +++ b/patches.renesas/0178-ARM-shmobile-r8a7790-Make-struct-rcar_sysc_ch-const.patch @@ -0,0 +1,36 @@ +From 369e962a8edf5dc5c840731d836b1201d2bab1e5 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 4 Jun 2015 20:22:35 +0200 +Subject: [PATCH 178/326] ARM: shmobile: r8a7790: Make struct rcar_sysc_ch + const + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit bd82aff9192dad2bfd3cb3fc19fdf741c2f6028e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/smp-r8a7790.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c +index 930f45cbc08a..2ef0054ce934 100644 +--- a/arch/arm/mach-shmobile/smp-r8a7790.c ++++ b/arch/arm/mach-shmobile/smp-r8a7790.c +@@ -26,12 +26,12 @@ + #include "rcar-gen2.h" + #include "r8a7790.h" + +-static struct rcar_sysc_ch r8a7790_ca15_scu = { ++static const struct rcar_sysc_ch r8a7790_ca15_scu = { + .chan_offs = 0x180, /* PWRSR5 .. PWRER5 */ + .isr_bit = 12, /* CA15-SCU */ + }; + +-static struct rcar_sysc_ch r8a7790_ca7_scu = { ++static const struct rcar_sysc_ch r8a7790_ca7_scu = { + .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */ + .isr_bit = 21, /* CA7-SCU */ + }; +-- +2.6.2 + diff --git a/patches.renesas/0179-ARM-shmobile-Basic-r8a7793-SoC-support.patch b/patches.renesas/0179-ARM-shmobile-Basic-r8a7793-SoC-support.patch new file mode 100644 index 00000000000000..b5295451fdc708 --- /dev/null +++ b/patches.renesas/0179-ARM-shmobile-Basic-r8a7793-SoC-support.patch @@ -0,0 +1,88 @@ +From 83c7d421c01c2002b1971871039198a7795ccfee Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Mon, 1 Jun 2015 16:22:54 +0200 +Subject: [PATCH 179/326] ARM: shmobile: Basic r8a7793 SoC support + +Minimal support without power management or SMP. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ec60d95b4faccd61c7ce10316ebc9333f2d7674a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 4 ++++ + arch/arm/mach-shmobile/Makefile | 1 + + arch/arm/mach-shmobile/setup-r8a7793.c | 33 +++++++++++++++++++++++++++++++++ + 3 files changed, 38 insertions(+) + create mode 100644 arch/arm/mach-shmobile/setup-r8a7793.c + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 9725f442d566..4a93a6eade14 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -82,6 +82,10 @@ config ARCH_R8A7791 + select ARCH_RCAR_GEN2 + select I2C + ++config ARCH_R8A7793 ++ bool "R-Car M2-N (R8A7793)" ++ select ARCH_RCAR_GEN2 ++ + config ARCH_R8A7794 + bool "R-Car E2 (R8A77940)" + select ARCH_RCAR_GEN2 +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 726c219e5b13..3a85ca3a6cb1 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o + obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o + obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o + obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o ++obj-$(CONFIG_ARCH_R8A7793) += setup-r8a7793.o + obj-$(CONFIG_ARCH_R8A7794) += setup-r8a7794.o + obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o + obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o +diff --git a/arch/arm/mach-shmobile/setup-r8a7793.c b/arch/arm/mach-shmobile/setup-r8a7793.c +new file mode 100644 +index 000000000000..1d2825cb7a65 +--- /dev/null ++++ b/arch/arm/mach-shmobile/setup-r8a7793.c +@@ -0,0 +1,33 @@ ++/* ++ * r8a7793 processor support ++ * ++ * Copyright (C) 2015 Ulrich Hecht ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <linux/init.h> ++#include <asm/mach/arch.h> ++ ++#include "common.h" ++#include "rcar-gen2.h" ++ ++static const char *r8a7793_boards_compat_dt[] __initconst = { ++ "renesas,r8a7793", ++ NULL, ++}; ++ ++DT_MACHINE_START(R8A7793_DT, "Generic R8A7793 (Flattened Device Tree)") ++ .init_early = shmobile_init_delay, ++ .init_time = rcar_gen2_timer_init, ++ .init_late = shmobile_init_late, ++ .reserve = rcar_gen2_reserve, ++ .dt_compat = r8a7793_boards_compat_dt, ++MACHINE_END +-- +2.6.2 + diff --git a/patches.renesas/0180-ARM-shmobile-gose-enable-R-Car-Gen2-regulator-quirk.patch b/patches.renesas/0180-ARM-shmobile-gose-enable-R-Car-Gen2-regulator-quirk.patch new file mode 100644 index 00000000000000..78ac3106187d39 --- /dev/null +++ b/patches.renesas/0180-ARM-shmobile-gose-enable-R-Car-Gen2-regulator-quirk.patch @@ -0,0 +1,60 @@ +From dcfa56131a12fc1e69870904b508e43a152011ad Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Mon, 1 Jun 2015 16:22:57 +0200 +Subject: [PATCH 180/326] ARM: shmobile: gose: enable R-Car Gen2 regulator + quirk + +Regulator setup seems identical to Koelsch. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 765b50030c218f65ee4ffd2eeb07045aa79fd5ee) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 1 + + arch/arm/mach-shmobile/Makefile | 1 + + arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c | 3 ++- + 3 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 4a93a6eade14..d57bbf1beb70 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -85,6 +85,7 @@ config ARCH_R8A7791 + config ARCH_R8A7793 + bool "R-Car M2-N (R8A7793)" + select ARCH_RCAR_GEN2 ++ select I2C + + config ARCH_R8A7794 + bool "R-Car E2 (R8A77940)" +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 3a85ca3a6cb1..6cb095107f90 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -33,6 +33,7 @@ obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y) + CFLAGS_setup-rcar-gen2.o += -march=armv7-a + obj-$(CONFIG_ARCH_R8A7790) += regulator-quirk-rcar-gen2.o + obj-$(CONFIG_ARCH_R8A7791) += regulator-quirk-rcar-gen2.o ++obj-$(CONFIG_ARCH_R8A7793) += regulator-quirk-rcar-gen2.o + + # SMP objects + smp-y := $(cpu-y) +diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c +index 384e6e934b87..62437b57813e 100644 +--- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c ++++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c +@@ -123,7 +123,8 @@ static int __init rcar_gen2_regulator_quirk(void) + u32 mon; + + if (!of_machine_is_compatible("renesas,koelsch") && +- !of_machine_is_compatible("renesas,lager")) ++ !of_machine_is_compatible("renesas,lager") && ++ !of_machine_is_compatible("renesas,gose")) + return -ENODEV; + + irqc = ioremap(IRQC_BASE, PAGE_SIZE); +-- +2.6.2 + diff --git a/patches.renesas/0181-ARM-shmobile-apmu-silence-build-warnings.patch b/patches.renesas/0181-ARM-shmobile-apmu-silence-build-warnings.patch new file mode 100644 index 00000000000000..c483ba85b94f1d --- /dev/null +++ b/patches.renesas/0181-ARM-shmobile-apmu-silence-build-warnings.patch @@ -0,0 +1,45 @@ +From df157aae98efae424913b24fe0a291bff7480abd Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Fri, 10 Jul 2015 22:48:16 +0200 +Subject: [PATCH 181/326] ARM: shmobile: apmu: silence build warnings + +With shmobile_defconfig but SMP=n && SUSPEND=n, I get: + +arch/arm/mach-shmobile/platsmp-apmu.c:49:12: warning: 'apmu_power_off' defined but not used [-Wunused-function] +arch/arm/mach-shmobile/platsmp-apmu.c:70:12: warning: 'apmu_wrap' defined but not used [-Wunused-function] + +Annotate those functions like the functions around it. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 151dd346a2dadaa151d5110553e3fb08774c888e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/platsmp-apmu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c +index b0790fc32282..4e54512bee30 100644 +--- a/arch/arm/mach-shmobile/platsmp-apmu.c ++++ b/arch/arm/mach-shmobile/platsmp-apmu.c +@@ -46,7 +46,7 @@ static int __maybe_unused apmu_power_on(void __iomem *p, int bit) + return 0; + } + +-static int apmu_power_off(void __iomem *p, int bit) ++static int __maybe_unused apmu_power_off(void __iomem *p, int bit) + { + /* request Core Standby for next WFI */ + writel_relaxed(3, p + CPUNCR_OFFS(bit)); +@@ -67,7 +67,7 @@ static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit) + return 0; + } + +-static int apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu)) ++static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu)) + { + void __iomem *p = apmu_cpus[cpu].iomem; + +-- +2.6.2 + diff --git a/patches.renesas/0182-ARM-shmobile-r8a7779-Generic-CCF-and-timer-support.patch b/patches.renesas/0182-ARM-shmobile-r8a7779-Generic-CCF-and-timer-support.patch new file mode 100644 index 00000000000000..6b21ede687de0d --- /dev/null +++ b/patches.renesas/0182-ARM-shmobile-r8a7779-Generic-CCF-and-timer-support.patch @@ -0,0 +1,63 @@ +From ded8096707335030772202b48198140a2a6fc248 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm+renesas@opensource.se> +Date: Thu, 25 Jun 2015 17:57:39 +0900 +Subject: [PATCH 182/326] ARM: shmobile: r8a7779: Generic CCF and timer support + +Add a r8a7779-specific callback to initialize CCF and +clocksources. With this in place we are one step closer +to be able to use r8a7779 without C board code. + +Also add a multiplatform wrapper to avoid breaking the +r8a7779 marzen legacy case. + +Signed-off-by: Magnus Damm <damm+renesas@opensource.se> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 131c2e0480b0f7afefbc9a46cc4e158e17caa844) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7779.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index c03e562be12b..5625fd1c89c0 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -14,6 +14,8 @@ + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ ++#include <linux/clk/shmobile.h> ++#include <linux/clocksource.h> + #include <linux/kernel.h> + #include <linux/init.h> + #include <linux/interrupt.h> +@@ -756,6 +758,14 @@ u32 __init r8a7779_read_mode_pins(void) + return mode; + } + ++#ifdef CONFIG_ARCH_SHMOBILE_MULTI ++ ++static void __init r8a7779_init_time(void) ++{ ++ r8a7779_clocks_init(r8a7779_read_mode_pins()); ++ clocksource_of_init(); ++} ++ + static const char *r8a7779_compat_dt[] __initdata = { + "renesas,r8a7779", + NULL, +@@ -764,8 +774,10 @@ static const char *r8a7779_compat_dt[] __initdata = { + DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") + .map_io = r8a7779_map_io, + .init_early = shmobile_init_delay, ++ .init_time = r8a7779_init_time, + .init_irq = r8a7779_init_irq_dt, + .init_late = shmobile_init_late, + .dt_compat = r8a7779_compat_dt, + MACHINE_END ++#endif /* CONFIG_ARCH_SHMOBILE_MULTI */ + #endif /* CONFIG_USE_OF */ +-- +2.6.2 + diff --git a/patches.renesas/0183-ARM-shmobile-r8a7779-Generic-SMP-ops.patch b/patches.renesas/0183-ARM-shmobile-r8a7779-Generic-SMP-ops.patch new file mode 100644 index 00000000000000..907c4cd48c625d --- /dev/null +++ b/patches.renesas/0183-ARM-shmobile-r8a7779-Generic-SMP-ops.patch @@ -0,0 +1,32 @@ +From 6171117b3c7f2b7d396194077c35405379a65ef8 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm+renesas@opensource.se> +Date: Mon, 13 Jul 2015 15:15:02 +0900 +Subject: [PATCH 183/326] ARM: shmobile: r8a7779: Generic SMP ops + +Add a r8a7779-specific SMP operation pointer to support +all 4 CPU cores through SMP on r8a7779 without C board code. + +Signed-off-by: Magnus Damm <damm+renesas@opensource.se> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 44ade5edf90ccd38efa741240efb2586239c9751) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r8a7779.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index 5625fd1c89c0..2c3e433f84ca 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -772,6 +772,7 @@ static const char *r8a7779_compat_dt[] __initdata = { + }; + + DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") ++ .smp = smp_ops(r8a7779_smp_ops), + .map_io = r8a7779_map_io, + .init_early = shmobile_init_delay, + .init_time = r8a7779_init_time, +-- +2.6.2 + diff --git a/patches.renesas/0184-ARM-shmobile-emev2-add-IIC-cores-to-dtsi.patch b/patches.renesas/0184-ARM-shmobile-emev2-add-IIC-cores-to-dtsi.patch new file mode 100644 index 00000000000000..3141645e1bf038 --- /dev/null +++ b/patches.renesas/0184-ARM-shmobile-emev2-add-IIC-cores-to-dtsi.patch @@ -0,0 +1,87 @@ +From cdb340241b2be103eb10598b60dbf7551bdfd872 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Sat, 11 Jul 2015 09:46:25 +0200 +Subject: [PATCH 184/326] ARM: shmobile: emev2: add IIC cores to dtsi + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cd42d042a2e712a7f9880f860075815539ce4baf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/emev2.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 48 insertions(+) + +diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi +index bb45694d91bc..edad0c4eea35 100644 +--- a/arch/arm/boot/dts/emev2.dtsi ++++ b/arch/arm/boot/dts/emev2.dtsi +@@ -21,6 +21,8 @@ + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; ++ i2c0 = &iic0; ++ i2c1 = &iic1; + }; + + cpus { +@@ -66,6 +68,30 @@ + clock-frequency = <32768>; + #clock-cells = <0>; + }; ++ iic0_sclkdiv: iic0_sclkdiv { ++ compatible = "renesas,emev2-smu-clkdiv"; ++ reg = <0x624 0>; ++ clocks = <&pll3_fo>; ++ #clock-cells = <0>; ++ }; ++ iic0_sclk: iic0_sclk { ++ compatible = "renesas,emev2-smu-gclk"; ++ reg = <0x48c 1>; ++ clocks = <&iic0_sclkdiv>; ++ #clock-cells = <0>; ++ }; ++ iic1_sclkdiv: iic1_sclkdiv { ++ compatible = "renesas,emev2-smu-clkdiv"; ++ reg = <0x624 16>; ++ clocks = <&pll3_fo>; ++ #clock-cells = <0>; ++ }; ++ iic1_sclk: iic1_sclk { ++ compatible = "renesas,emev2-smu-gclk"; ++ reg = <0x490 1>; ++ clocks = <&iic1_sclkdiv>; ++ #clock-cells = <0>; ++ }; + pll3_fo: pll3_fo { + compatible = "fixed-factor-clock"; + clocks = <&c32ki>; +@@ -234,4 +260,26 @@ + interrupt-controller; + #interrupt-cells = <2>; + }; ++ ++ iic0: i2c@e0070000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,iic-emev2"; ++ reg = <0xe0070000 0x28>; ++ interrupts = <0 32 IRQ_TYPE_EDGE_RISING>; ++ clocks = <&iic0_sclk>; ++ clock-names = "sclk"; ++ status = "disabled"; ++ }; ++ ++ iic1: i2c@e10a0000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,iic-emev2"; ++ reg = <0xe10a0000 0x28>; ++ interrupts = <0 33 IRQ_TYPE_EDGE_RISING>; ++ clocks = <&iic1_sclk>; ++ clock-names = "sclk"; ++ status = "disabled"; ++ }; + }; +-- +2.6.2 + diff --git a/patches.renesas/0185-ARM-shmobile-emev2-kzm9d-enable-IIC-busses.patch b/patches.renesas/0185-ARM-shmobile-emev2-kzm9d-enable-IIC-busses.patch new file mode 100644 index 00000000000000..3bb94319523a92 --- /dev/null +++ b/patches.renesas/0185-ARM-shmobile-emev2-kzm9d-enable-IIC-busses.patch @@ -0,0 +1,35 @@ +From 0700261389e7651ee9a47698e6fa57ca7a7a3b43 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Sat, 11 Jul 2015 09:46:26 +0200 +Subject: [PATCH 185/326] ARM: shmobile: emev2: kzm9d: enable IIC busses + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c53b0c92a829fe804f2f5f749ebc907658ebcf75) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/emev2-kzm9d.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts +index 1dee0aa4f40c..955c24ee4a8c 100644 +--- a/arch/arm/boot/dts/emev2-kzm9d.dts ++++ b/arch/arm/boot/dts/emev2-kzm9d.dts +@@ -95,6 +95,14 @@ + }; + }; + ++&iic0 { ++ status = "okay"; ++}; ++ ++&iic1 { ++ status = "okay"; ++}; ++ + &pfc { + uart1_pins: serial@e1030000 { + renesas,groups = "uart1_ctrl", "uart1_data"; +-- +2.6.2 + diff --git a/patches.renesas/0186-ARM-shmobile-lager-add-sound-label-on-DTS.patch b/patches.renesas/0186-ARM-shmobile-lager-add-sound-label-on-DTS.patch new file mode 100644 index 00000000000000..8b55f515c5f814 --- /dev/null +++ b/patches.renesas/0186-ARM-shmobile-lager-add-sound-label-on-DTS.patch @@ -0,0 +1,31 @@ +From bd9250e04e1bb6dcea8aa8100b96ce707f2a6064 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 14 Jul 2015 04:56:10 +0000 +Subject: [PATCH 186/326] ARM: shmobile: lager: add sound label on DTS + +It is easy to modify settings for Test or other purpose if sound has label + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 30be0ba5f92c9a728bf3b3f41dbf3240eb3bbc11) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790-lager.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts +index 2eb8a995ae9f..5ae07a8385c5 100644 +--- a/arch/arm/boot/dts/r8a7790-lager.dts ++++ b/arch/arm/boot/dts/r8a7790-lager.dts +@@ -174,7 +174,7 @@ + 1800000 0>; + }; + +- sound { ++ rsnd_ak4643: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; +-- +2.6.2 + diff --git a/patches.renesas/0187-ARM-shmobile-koelsch-add-sound-label-on-DTS.patch b/patches.renesas/0187-ARM-shmobile-koelsch-add-sound-label-on-DTS.patch new file mode 100644 index 00000000000000..f427f5c34ac41a --- /dev/null +++ b/patches.renesas/0187-ARM-shmobile-koelsch-add-sound-label-on-DTS.patch @@ -0,0 +1,31 @@ +From a2f835f0dc52005a777830a38a1917c990166cb1 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 14 Jul 2015 04:57:05 +0000 +Subject: [PATCH 187/326] ARM: shmobile: koelsch: add sound label on DTS + +It is easy to modify settings for Test or other purpose if sound has label + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 18f88d22e4167a658091fe020beef723cefe86dd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791-koelsch.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts +index cffe33ff4d16..dc158845afdc 100644 +--- a/arch/arm/boot/dts/r8a7791-koelsch.dts ++++ b/arch/arm/boot/dts/r8a7791-koelsch.dts +@@ -242,7 +242,7 @@ + 1800000 0>; + }; + +- sound { ++ rsnd_ak4643: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; +-- +2.6.2 + diff --git a/patches.renesas/0188-ARM-shmobile-defconfig-add-Renesas-DPCM-Sound-Card.patch b/patches.renesas/0188-ARM-shmobile-defconfig-add-Renesas-DPCM-Sound-Card.patch new file mode 100644 index 00000000000000..48778b3f42221f --- /dev/null +++ b/patches.renesas/0188-ARM-shmobile-defconfig-add-Renesas-DPCM-Sound-Card.patch @@ -0,0 +1,35 @@ +From 6ac0c725617f1ab99178e061d090a7641de04e12 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 14 Jul 2015 04:57:34 +0000 +Subject: [PATCH 188/326] ARM: shmobile: defconfig: add Renesas DPCM Sound Card + +This patch enables DPCM related sound card. +It is used for... + - Sampline rate convert + - CTU/MIXer + +Note: you need to enable these settings on DTS file + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6cec276808bc0a4ac5fc3ab9e42a1b5d1e3e9cc4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/shmobile_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig +index c8e9caeb1c02..8da509327265 100644 +--- a/arch/arm/configs/shmobile_defconfig ++++ b/arch/arm/configs/shmobile_defconfig +@@ -152,6 +152,7 @@ CONFIG_SND=y + CONFIG_SND_SOC=y + CONFIG_SND_SOC_SH4_FSI=y + CONFIG_SND_SOC_RCAR=y ++CONFIG_SND_SOC_RSRC_CARD=y + CONFIG_SND_SOC_AK4642=y + CONFIG_SND_SOC_WM8978=y + CONFIG_USB=y +-- +2.6.2 + diff --git a/patches.renesas/0189-ARM-shmobile-Remove-marzen_defconfig.patch b/patches.renesas/0189-ARM-shmobile-Remove-marzen_defconfig.patch new file mode 100644 index 00000000000000..fc17c047750c4b --- /dev/null +++ b/patches.renesas/0189-ARM-shmobile-Remove-marzen_defconfig.patch @@ -0,0 +1,151 @@ +From d67c030cc7edbd58d0ab20115720d3090d5d95f8 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm+renesas@opensource.se> +Date: Thu, 16 Jul 2015 16:54:14 +0900 +Subject: [PATCH 189/326] ARM: shmobile: Remove marzen_defconfig + +Now when the Marzen legacy board code is removed also +get rid of the marzen_defconfig file. Existing users +shall move over to shmobile_defconfig. + +Signed-off-by: Magnus Damm <damm+renesas@opensource.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 821e79cb5686695f0adaef61587a184e953a937e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/marzen_defconfig | 124 -------------------------------------- + 1 file changed, 124 deletions(-) + delete mode 100644 arch/arm/configs/marzen_defconfig + +diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig +deleted file mode 100644 +index 3c8b6d823189..000000000000 +--- a/arch/arm/configs/marzen_defconfig ++++ /dev/null +@@ -1,124 +0,0 @@ +-# CONFIG_ARM_PATCH_PHYS_VIRT is not set +-CONFIG_EXPERIMENTAL=y +-CONFIG_KERNEL_LZMA=y +-CONFIG_NO_HZ=y +-CONFIG_IKCONFIG=y +-CONFIG_IKCONFIG_PROC=y +-CONFIG_LOG_BUF_SHIFT=16 +-CONFIG_SYSCTL_SYSCALL=y +-CONFIG_EMBEDDED=y +-CONFIG_SLAB=y +-# CONFIG_IOSCHED_CFQ is not set +-CONFIG_ARCH_SHMOBILE_LEGACY=y +-CONFIG_ARCH_R8A7779=y +-CONFIG_MACH_MARZEN=y +-CONFIG_MEMORY_START=0x60000000 +-CONFIG_MEMORY_SIZE=0x10000000 +-CONFIG_SHMOBILE_TIMER_HZ=1024 +-# CONFIG_SH_TIMER_CMT is not set +-# CONFIG_SWP_EMULATE is not set +-CONFIG_ARM_ERRATA_430973=y +-CONFIG_ARM_ERRATA_458693=y +-CONFIG_ARM_ERRATA_460075=y +-CONFIG_ARM_ERRATA_743622=y +-CONFIG_ARM_ERRATA_754322=y +-CONFIG_SMP=y +-# CONFIG_ARM_CPU_TOPOLOGY is not set +-CONFIG_AEABI=y +-# CONFIG_OABI_COMPAT is not set +-CONFIG_HIGHMEM=y +-CONFIG_ZBOOT_ROM_TEXT=0x0 +-CONFIG_ZBOOT_ROM_BSS=0x0 +-CONFIG_ARM_APPENDED_DTB=y +-CONFIG_VFP=y +-CONFIG_KEXEC=y +-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +-CONFIG_PM=y +-CONFIG_NET=y +-CONFIG_PACKET=y +-CONFIG_UNIX=y +-CONFIG_INET=y +-CONFIG_IP_PNP=y +-CONFIG_IP_PNP_DHCP=y +-# CONFIG_IPV6 is not set +-# CONFIG_WIRELESS is not set +-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +-CONFIG_DEVTMPFS=y +-CONFIG_DEVTMPFS_MOUNT=y +-# CONFIG_STANDALONE is not set +-# CONFIG_PREVENT_FIRMWARE_BUILD is not set +-# CONFIG_FW_LOADER is not set +-CONFIG_SCSI=y +-CONFIG_BLK_DEV_SD=y +-CONFIG_ATA=y +-CONFIG_ATA_SFF=y +-CONFIG_ATA_BMDMA=y +-CONFIG_SATA_RCAR=y +-CONFIG_NETDEVICES=y +-# CONFIG_NET_VENDOR_BROADCOM is not set +-# CONFIG_NET_VENDOR_FARADAY is not set +-# CONFIG_NET_VENDOR_INTEL is not set +-# CONFIG_NET_VENDOR_MICREL is not set +-# CONFIG_NET_VENDOR_NATSEMI is not set +-# CONFIG_NET_VENDOR_SEEQ is not set +-CONFIG_SMSC911X=y +-# CONFIG_NET_VENDOR_STMICRO is not set +-# CONFIG_WLAN is not set +-# CONFIG_INPUT_MOUSEDEV is not set +-CONFIG_INPUT_EVDEV=y +-# CONFIG_INPUT_MOUSE is not set +-# CONFIG_VT is not set +-# CONFIG_LEGACY_PTYS is not set +-# CONFIG_DEVKMEM is not set +-CONFIG_SERIAL_SH_SCI=y +-CONFIG_SERIAL_SH_SCI_NR_UARTS=6 +-CONFIG_SERIAL_SH_SCI_CONSOLE=y +-# CONFIG_HW_RANDOM is not set +-CONFIG_I2C=y +-CONFIG_I2C_RCAR=y +-CONFIG_SPI=y +-CONFIG_SPI_SH_HSPI=y +-CONFIG_GPIO_SYSFS=y +-CONFIG_GPIO_RCAR=y +-# CONFIG_HWMON is not set +-CONFIG_THERMAL=y +-CONFIG_RCAR_THERMAL=y +-CONFIG_SSB=y +-CONFIG_REGULATOR=y +-CONFIG_MEDIA_SUPPORT=y +-CONFIG_MEDIA_CAMERA_SUPPORT=y +-CONFIG_V4L_PLATFORM_DRIVERS=y +-CONFIG_SOC_CAMERA=y +-CONFIG_VIDEO_RCAR_VIN=y +-# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +-CONFIG_VIDEO_ADV7180=y +-CONFIG_DRM=y +-CONFIG_DRM_RCAR_DU=y +-CONFIG_USB=y +-CONFIG_USB_RCAR_PHY=y +-CONFIG_MMC=y +-CONFIG_MMC_SDHI=y +-CONFIG_USB_EHCI_HCD=y +-CONFIG_USB_OHCI_HCD=y +-CONFIG_USB_OHCI_HCD_PLATFORM=y +-CONFIG_USB_EHCI_HCD_PLATFORM=y +-CONFIG_USB_STORAGE=y +-CONFIG_NEW_LEDS=y +-CONFIG_LEDS_CLASS=y +-CONFIG_LEDS_GPIO=y +-CONFIG_DMADEVICES=y +-CONFIG_RCAR_HPB_DMAE=y +-CONFIG_UIO=y +-CONFIG_UIO_PDRV_GENIRQ=y +-# CONFIG_IOMMU_SUPPORT is not set +-# CONFIG_DNOTIFY is not set +-CONFIG_TMPFS=y +-# CONFIG_MISC_FILESYSTEMS is not set +-CONFIG_NFS_FS=y +-CONFIG_ROOT_NFS=y +-CONFIG_MAGIC_SYSRQ=y +-CONFIG_DEBUG_INFO=y +-CONFIG_DEBUG_INFO_REDUCED=y +-# CONFIG_FTRACE is not set +-CONFIG_DEBUG_USER=y +-CONFIG_AVERAGE=y +-- +2.6.2 + diff --git a/patches.renesas/0190-ARM-shmobile-lager-Fix-adv7511-IRQ-sensing.patch b/patches.renesas/0190-ARM-shmobile-lager-Fix-adv7511-IRQ-sensing.patch new file mode 100644 index 00000000000000..ee776bfd7c87e6 --- /dev/null +++ b/patches.renesas/0190-ARM-shmobile-lager-Fix-adv7511-IRQ-sensing.patch @@ -0,0 +1,35 @@ +From 97aeae46796625c54b9b215800319e6ef0040582 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 6 May 2015 07:05:31 +0300 +Subject: [PATCH 190/326] ARM: shmobile: lager: Fix adv7511 IRQ sensing + +The adv7511 IRQ is low level triggered, not falling edge triggered. The +wrong sense configuration results in no interrupt being triggered at +all, breaking hotplug detection. Fix it. + +Reported-by: Ben Hutchings <ben.hutchings@codethink.co.uk> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 850346eccc2d32dd6d0a3b08e6ac127b8982c067) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790-lager.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts +index 5ae07a8385c5..37dec5269491 100644 +--- a/arch/arm/boot/dts/r8a7790-lager.dts ++++ b/arch/arm/boot/dts/r8a7790-lager.dts +@@ -548,7 +548,7 @@ + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; +- interrupts = <15 IRQ_TYPE_EDGE_FALLING>; ++ interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; +-- +2.6.2 + diff --git a/patches.renesas/0191-ARM-shmobile-r8a7790-Add-Audio-CTU-support-on-DTSI.patch b/patches.renesas/0191-ARM-shmobile-r8a7790-Add-Audio-CTU-support-on-DTSI.patch new file mode 100644 index 00000000000000..856516a919f21b --- /dev/null +++ b/patches.renesas/0191-ARM-shmobile-r8a7790-Add-Audio-CTU-support-on-DTSI.patch @@ -0,0 +1,93 @@ +From e7001c8034fa4a46448dbb5805772d6c4421606d Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 21 Jul 2015 00:26:20 +0000 +Subject: [PATCH 191/326] ARM: shmobile: r8a7790: Add Audio CTU support on DTSI + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a7163784961e513a6d8c60b264737af623d1f33c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 16 ++++++++++++++++ + include/dt-bindings/clock/r8a7790-clock.h | 2 ++ + 2 files changed, 18 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 3ae0c3bfb9b9..6aa1d759690b 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -1303,6 +1303,7 @@ + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, ++ <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; + + #clock-cells = <1>; +@@ -1312,6 +1313,7 @@ + R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 + R8A7790_CLK_SCU_ALL + R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 ++ R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0 + R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 + R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 + >; +@@ -1321,6 +1323,7 @@ + "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", + "scu-all", + "scu-dvc1", "scu-dvc0", ++ "scu-ctu1-mix1", "scu-ctu0-mix0", + "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", + "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; + }; +@@ -1536,6 +1539,7 @@ + <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, + <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, + <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, ++ <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clock-names = "ssi-all", +@@ -1543,6 +1547,7 @@ + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", "src.5", + "src.4", "src.3", "src.2", "src.1", "src.0", ++ "ctu.0", "ctu.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + +@@ -1559,6 +1564,17 @@ + }; + }; + ++ rcar_sound,ctu { ++ ctu00: ctu@0 { }; ++ ctu01: ctu@1 { }; ++ ctu02: ctu@2 { }; ++ ctu03: ctu@3 { }; ++ ctu10: ctu@4 { }; ++ ctu11: ctu@5 { }; ++ ctu12: ctu@6 { }; ++ ctu13: ctu@7 { }; ++ }; ++ + rcar_sound,src { + src0: src@0 { + interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; +diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h +index e119ef372ba3..7b1ad8922eec 100644 +--- a/include/dt-bindings/clock/r8a7790-clock.h ++++ b/include/dt-bindings/clock/r8a7790-clock.h +@@ -144,6 +144,8 @@ + #define R8A7790_CLK_SCU_ALL 17 + #define R8A7790_CLK_SCU_DVC1 18 + #define R8A7790_CLK_SCU_DVC0 19 ++#define R8A7790_CLK_SCU_CTU1_MIX1 20 ++#define R8A7790_CLK_SCU_CTU0_MIX0 21 + #define R8A7790_CLK_SCU_SRC9 22 + #define R8A7790_CLK_SCU_SRC8 23 + #define R8A7790_CLK_SCU_SRC7 24 +-- +2.6.2 + diff --git a/patches.renesas/0192-ARM-shmobile-r8a7790-Add-Audio-MIX-support-on-DTSI.patch b/patches.renesas/0192-ARM-shmobile-r8a7790-Add-Audio-MIX-support-on-DTSI.patch new file mode 100644 index 00000000000000..b7211a41f047ac --- /dev/null +++ b/patches.renesas/0192-ARM-shmobile-r8a7790-Add-Audio-MIX-support-on-DTSI.patch @@ -0,0 +1,49 @@ +From d3e031652483d16a210a8a50233bf8ac55a41000 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 21 Jul 2015 00:26:42 +0000 +Subject: [PATCH 192/326] ARM: shmobile: r8a7790: Add Audio MIX support on DTSI + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fc67bf42fa9a3e7c891e6318475f9c4d81a1d44e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 6aa1d759690b..f1cdccc0a8c8 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -1540,6 +1540,7 @@ + <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, + <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, + <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, ++ <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clock-names = "ssi-all", +@@ -1548,6 +1549,7 @@ + "src.9", "src.8", "src.7", "src.6", "src.5", + "src.4", "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", ++ "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + +@@ -1564,6 +1566,11 @@ + }; + }; + ++ rcar_sound,mix { ++ mix0: mix@0 { }; ++ mix1: mix@1 { }; ++ }; ++ + rcar_sound,ctu { + ctu00: ctu@0 { }; + ctu01: ctu@1 { }; +-- +2.6.2 + diff --git a/patches.renesas/0193-ARM-shmobile-r8a7791-Add-Audio-CTU-support-on-DTSI.patch b/patches.renesas/0193-ARM-shmobile-r8a7791-Add-Audio-CTU-support-on-DTSI.patch new file mode 100644 index 00000000000000..4efe0345a3214b --- /dev/null +++ b/patches.renesas/0193-ARM-shmobile-r8a7791-Add-Audio-CTU-support-on-DTSI.patch @@ -0,0 +1,92 @@ +From 8640cfa02fad88d729a096f2c99f2911cd6ae45e Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 21 Jul 2015 00:27:03 +0000 +Subject: [PATCH 193/326] ARM: shmobile: r8a7791: Add Audio CTU support on DTSI + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 88401702fe395880bb03c9d17720185c1d89b43f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 16 ++++++++++++++++ + include/dt-bindings/clock/r8a7791-clock.h | 2 ++ + 2 files changed, 18 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi +index 07ea2bebe496..cdd55b82ba4e 100644 +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -1311,6 +1311,7 @@ + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, ++ <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; + + #clock-cells = <1>; +@@ -1320,6 +1321,7 @@ + R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 + R8A7791_CLK_SCU_ALL + R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 ++ R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0 + R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 + R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 + >; +@@ -1329,6 +1331,7 @@ + "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", + "scu-all", + "scu-dvc1", "scu-dvc0", ++ "scu-ctu1-mix1", "scu-ctu0-mix0", + "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", + "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; + }; +@@ -1582,6 +1585,7 @@ + <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, + <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, + <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, ++ <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clock-names = "ssi-all", +@@ -1589,6 +1593,7 @@ + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", "src.5", + "src.4", "src.3", "src.2", "src.1", "src.0", ++ "ctu.0", "ctu.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + +@@ -1605,6 +1610,17 @@ + }; + }; + ++ rcar_sound,ctu { ++ ctu00: ctu@0 { }; ++ ctu01: ctu@1 { }; ++ ctu02: ctu@2 { }; ++ ctu03: ctu@3 { }; ++ ctu10: ctu@4 { }; ++ ctu11: ctu@5 { }; ++ ctu12: ctu@6 { }; ++ ctu13: ctu@7 { }; ++ }; ++ + rcar_sound,src { + src0: src@0 { + interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; +diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h +index 402268384b99..dd09b73c4aaf 100644 +--- a/include/dt-bindings/clock/r8a7791-clock.h ++++ b/include/dt-bindings/clock/r8a7791-clock.h +@@ -141,6 +141,8 @@ + #define R8A7791_CLK_SCU_ALL 17 + #define R8A7791_CLK_SCU_DVC1 18 + #define R8A7791_CLK_SCU_DVC0 19 ++#define R8A7791_CLK_SCU_CTU1_MIX1 20 ++#define R8A7791_CLK_SCU_CTU0_MIX0 21 + #define R8A7791_CLK_SCU_SRC9 22 + #define R8A7791_CLK_SCU_SRC8 23 + #define R8A7791_CLK_SCU_SRC7 24 +-- +2.6.2 + diff --git a/patches.renesas/0194-ARM-shmobile-r8a7791-Add-Audio-MIX-support-on-DTSI.patch b/patches.renesas/0194-ARM-shmobile-r8a7791-Add-Audio-MIX-support-on-DTSI.patch new file mode 100644 index 00000000000000..adddb66fe812de --- /dev/null +++ b/patches.renesas/0194-ARM-shmobile-r8a7791-Add-Audio-MIX-support-on-DTSI.patch @@ -0,0 +1,48 @@ +From 927714095d241026132ab3e55895d9db5eaaeee4 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 21 Jul 2015 00:27:24 +0000 +Subject: [PATCH 194/326] ARM: shmobile: r8a7791: Add Audio MIX support on DTSI + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7fd6e11dca09b21efbe2b9db4eff08c8f4a16125) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi +index cdd55b82ba4e..d37339bd7cdb 100644 +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -1586,6 +1586,7 @@ + <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, + <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, + <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, ++ <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clock-names = "ssi-all", +@@ -1594,6 +1595,7 @@ + "src.9", "src.8", "src.7", "src.6", "src.5", + "src.4", "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", ++ "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + +@@ -1610,6 +1612,11 @@ + }; + }; + ++ rcar_sound,mix { ++ mix0: mix@0 { }; ++ mix1: mix@1 { }; ++ }; ++ + rcar_sound,ctu { + ctu00: ctu@0 { }; + ctu01: ctu@1 { }; +-- +2.6.2 + diff --git a/patches.renesas/0195-ARM-shmobile-Enable-fixed-voltage-regulator-in-shmob.patch b/patches.renesas/0195-ARM-shmobile-Enable-fixed-voltage-regulator-in-shmob.patch new file mode 100644 index 00000000000000..fbef06eebf4c21 --- /dev/null +++ b/patches.renesas/0195-ARM-shmobile-Enable-fixed-voltage-regulator-in-shmob.patch @@ -0,0 +1,33 @@ +From 3ab274297fd2bf39a2b59e4a1338cb38404cb10b Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Wed, 15 Jul 2015 15:42:35 +0900 +Subject: [PATCH 195/326] ARM: shmobile: Enable fixed voltage regulator in + shmobile_defconfig + +This is selected by MACH_MARZEN which is enabled in shmobile_defconfig, +however, MACH_MARZEN is going away along with the board code it enables. + +Acked-by: Magnus Damm <damm@opensource.se> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 4055a722d260ca30610fc52238d0aa49ff5bffa9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/shmobile_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig +index 8da509327265..89bf31ccfbfa 100644 +--- a/arch/arm/configs/shmobile_defconfig ++++ b/arch/arm/configs/shmobile_defconfig +@@ -122,6 +122,7 @@ CONFIG_WATCHDOG=y + CONFIG_DA9063_WATCHDOG=y + CONFIG_MFD_AS3711=y + CONFIG_MFD_DA9063=y ++CONFIG_REGULATOR_FIXED_VOLTAGE=y + CONFIG_REGULATOR_AS3711=y + CONFIG_REGULATOR_DA9210=y + CONFIG_REGULATOR_GPIO=y +-- +2.6.2 + diff --git a/patches.renesas/0196-ARM-shmobile-marzen-reference-Remove-C-board-code.patch b/patches.renesas/0196-ARM-shmobile-marzen-reference-Remove-C-board-code.patch new file mode 100644 index 00000000000000..af467b5677990e --- /dev/null +++ b/patches.renesas/0196-ARM-shmobile-marzen-reference-Remove-C-board-code.patch @@ -0,0 +1,119 @@ +From 41a11fa59dfc6dccafcac5788ed0464b36e6cbd2 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm+renesas@opensource.se> +Date: Mon, 13 Jul 2015 15:15:12 +0900 +Subject: [PATCH 196/326] ARM: shmobile: marzen-reference: Remove C board code + +The generic r8a7779 machine vector is now feature-wise equivalent +to the Marzen-reference case, so simply remove the Marzen C board +code to fall over on the generic r8a7779 machine vector. + +Signed-off-by: Magnus Damm <damm+renesas@opensource.se> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 26f9e03fb1c8b8b5dd2f1ad34da775cc129df98a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 7 ---- + arch/arm/mach-shmobile/Makefile | 4 +- + arch/arm/mach-shmobile/board-marzen-reference.c | 56 ------------------------- + 3 files changed, 1 insertion(+), 66 deletions(-) + delete mode 100644 arch/arm/mach-shmobile/board-marzen-reference.c + +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index d57bbf1beb70..6f3713f3cb36 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -96,13 +96,6 @@ config ARCH_SH73A0 + select ARCH_RMOBILE + select RENESAS_INTC_IRQPIN + +-comment "Renesas ARM SoCs Board Type" +- +-config MACH_MARZEN +- bool "MARZEN board" +- depends on ARCH_R8A7779 +- select REGULATOR_FIXED_VOLTAGE if REGULATOR +- + comment "Renesas ARM SoCs System Configuration" + endif + +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 6cb095107f90..b180eafb0b87 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -51,9 +51,7 @@ obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o + obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o + + # Board objects +-ifdef CONFIG_ARCH_SHMOBILE_MULTI +-obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o +-else ++ifndef CONFIG_ARCH_SHMOBILE_MULTI + obj-$(CONFIG_MACH_BOCKW) += board-bockw.o + obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o + obj-$(CONFIG_MACH_MARZEN) += board-marzen.o +diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c +deleted file mode 100644 +index b15eb923263f..000000000000 +--- a/arch/arm/mach-shmobile/board-marzen-reference.c ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* +- * marzen board support - Reference DT implementation +- * +- * Copyright (C) 2011 Renesas Solutions Corp. +- * Copyright (C) 2011 Magnus Damm +- * Copyright (C) 2013 Simon Horman +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include <linux/clk/shmobile.h> +-#include <linux/clocksource.h> +-#include <linux/of_platform.h> +- +-#include <asm/irq.h> +-#include <asm/mach/arch.h> +- +-#include "common.h" +-#include "irqs.h" +-#include "r8a7779.h" +- +-static void __init marzen_init_timer(void) +-{ +- r8a7779_clocks_init(r8a7779_read_mode_pins()); +- clocksource_of_init(); +-} +- +-static void __init marzen_init(void) +-{ +- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +- r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */ +-} +- +-static const char *marzen_boards_compat_dt[] __initdata = { +- "renesas,marzen", +- "renesas,marzen-reference", +- NULL, +-}; +- +-DT_MACHINE_START(MARZEN, "marzen") +- .smp = smp_ops(r8a7779_smp_ops), +- .map_io = r8a7779_map_io, +- .init_early = shmobile_init_delay, +- .init_time = marzen_init_timer, +- .init_irq = r8a7779_init_irq_dt, +- .init_machine = marzen_init, +- .init_late = shmobile_init_late, +- .dt_compat = marzen_boards_compat_dt, +-MACHINE_END +-- +2.6.2 + diff --git a/patches.renesas/0197-ARM-shmobile-r8a7779-Cleanup-header-file.patch b/patches.renesas/0197-ARM-shmobile-r8a7779-Cleanup-header-file.patch new file mode 100644 index 00000000000000..b00b97d44f9e15 --- /dev/null +++ b/patches.renesas/0197-ARM-shmobile-r8a7779-Cleanup-header-file.patch @@ -0,0 +1,68 @@ +From b450e449dbed0aad40d9560c4b1143c9982b1c7f Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm+renesas@opensource.se> +Date: Mon, 13 Jul 2015 15:15:33 +0900 +Subject: [PATCH 197/326] ARM: shmobile: r8a7779: Cleanup header file + +Remove unused function prototypes from r8a7779.h and +make the functions static. + +Signed-off-by: Magnus Damm <damm+renesas@opensource.se> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 640780efdd97eefd9ee78e1cd03ba97b1a1e1d9a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/clock-r8a7779.c | 2 +- + arch/arm/mach-shmobile/r8a7779.h | 2 -- + arch/arm/mach-shmobile/setup-r8a7779.c | 2 +- + 3 files changed, 2 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c +index fa8ab2cc9187..a376ba3b67c0 100644 +--- a/arch/arm/mach-shmobile/clock-r8a7779.c ++++ b/arch/arm/mach-shmobile/clock-r8a7779.c +@@ -201,7 +201,7 @@ static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ + }; + +-void __init r8a7779_clock_init(void) ++static void __init r8a7779_clock_init(void) + { + u32 mode = r8a7779_read_mode_pins(); + int k, ret = 0; +diff --git a/arch/arm/mach-shmobile/r8a7779.h b/arch/arm/mach-shmobile/r8a7779.h +index 19f97046dd70..f69c7477178b 100644 +--- a/arch/arm/mach-shmobile/r8a7779.h ++++ b/arch/arm/mach-shmobile/r8a7779.h +@@ -11,7 +11,6 @@ enum { + }; + + extern void r8a7779_init_irq_extpin(int irlm); +-extern void r8a7779_init_irq_extpin_dt(int irlm); + extern void r8a7779_init_irq_dt(void); + extern void r8a7779_map_io(void); + extern void r8a7779_earlytimer_init(void); +@@ -19,7 +18,6 @@ extern void r8a7779_add_early_devices(void); + extern void r8a7779_add_standard_devices(void); + extern void r8a7779_init_late(void); + extern u32 r8a7779_read_mode_pins(void); +-extern void r8a7779_clock_init(void); + extern void r8a7779_pinmux_init(void); + extern void r8a7779_pm_init(void); + extern void r8a7779_register_twd(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index 2c3e433f84ca..f436cba958fa 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -99,7 +99,7 @@ static struct resource irqpin0_resources[] __initdata = { + DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ + }; + +-void __init r8a7779_init_irq_extpin_dt(int irlm) ++static void __init r8a7779_init_irq_extpin_dt(int irlm) + { + void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); + u32 tmp; +-- +2.6.2 + diff --git a/patches.renesas/0198-ARM-shmobile-marzen-Remove-legacy-board-code.patch b/patches.renesas/0198-ARM-shmobile-marzen-Remove-legacy-board-code.patch new file mode 100644 index 00000000000000..f398ff9395ffd8 --- /dev/null +++ b/patches.renesas/0198-ARM-shmobile-marzen-Remove-legacy-board-code.patch @@ -0,0 +1,441 @@ +From 1e3facf4f962aa7cf5a085c6242f06124770f1c6 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm+renesas@opensource.se> +Date: Thu, 16 Jul 2015 16:53:52 +0900 +Subject: [PATCH 198/326] ARM: shmobile: marzen: Remove legacy board code + +Remove Marzen legacy board code written in C. Instead +board support expressed in DT shall be used together +with Multiplatform and shmobile_defconfig. + +Signed-off-by: Magnus Damm <damm+renesas@opensource.se> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b97fdb836a36df53de5685278c0126a222903c5e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/boot/dts/Makefile + arch/arm/mach-shmobile/Kconfig + arch/arm/mach-shmobile/Makefile + arch/arm/mach-shmobile/Makefile.boot +--- + arch/arm/boot/dts/Makefile | 3 +- + arch/arm/mach-shmobile/Kconfig | 7 - + arch/arm/mach-shmobile/Makefile | 1 - + arch/arm/mach-shmobile/Makefile.boot | 1 - + arch/arm/mach-shmobile/board-marzen.c | 347 ---------------------------------- + 5 files changed, 1 insertion(+), 358 deletions(-) + delete mode 100644 arch/arm/mach-shmobile/board-marzen.c + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 908fcbf656c1..964ae0041a67 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -478,8 +478,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ + s5pv210-torbreck.dtb + dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \ + r8a7778-bockw.dtb \ +- r8a7778-bockw-reference.dtb \ +- r8a7779-marzen.dtb ++ r8a7778-bockw-reference.dtb + dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ + emev2-kzm9d.dtb \ + r7s72100-genmai.dtb \ +diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig +index 6f3713f3cb36..926e336d6aeb 100644 +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -139,13 +139,6 @@ config MACH_BOCKW_REFERENCE + + This is intended to aid developers + +-config MACH_MARZEN +- bool "MARZEN board" +- depends on ARCH_R8A7779 +- select ARCH_REQUIRE_GPIOLIB +- select REGULATOR_FIXED_VOLTAGE if REGULATOR +- select USE_OF +- + comment "Renesas ARM SoCs System Configuration" + + config CPU_HAS_INTEVT +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index b180eafb0b87..7bdb3ca099e1 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -54,7 +54,6 @@ obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o + ifndef CONFIG_ARCH_SHMOBILE_MULTI + obj-$(CONFIG_MACH_BOCKW) += board-bockw.o + obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o +-obj-$(CONFIG_MACH_MARZEN) += board-marzen.o + endif + + # Framework support +diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot +index 14cdfc0ed075..a489fe9a76cd 100644 +--- a/arch/arm/mach-shmobile/Makefile.boot ++++ b/arch/arm/mach-shmobile/Makefile.boot +@@ -2,7 +2,6 @@ + loadaddr-y := + loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 + loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 +-loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 + + __ZRELADDR := $(sort $(loadaddr-y)) + zreladdr-y += $(__ZRELADDR) +diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c +deleted file mode 100644 +index 51db288f192a..000000000000 +--- a/arch/arm/mach-shmobile/board-marzen.c ++++ /dev/null +@@ -1,347 +0,0 @@ +-/* +- * marzen board support +- * +- * Copyright (C) 2011, 2013 Renesas Solutions Corp. +- * Copyright (C) 2011 Magnus Damm +- * Copyright (C) 2013 Cogent Embedded, Inc. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include <linux/kernel.h> +-#include <linux/init.h> +-#include <linux/interrupt.h> +-#include <linux/irq.h> +-#include <linux/platform_device.h> +-#include <linux/delay.h> +-#include <linux/io.h> +-#include <linux/leds.h> +-#include <linux/dma-mapping.h> +-#include <linux/pinctrl/machine.h> +-#include <linux/platform_data/camera-rcar.h> +-#include <linux/platform_data/gpio-rcar.h> +-#include <linux/platform_data/usb-rcar-phy.h> +-#include <linux/regulator/fixed.h> +-#include <linux/regulator/machine.h> +-#include <linux/smsc911x.h> +-#include <linux/spi/spi.h> +-#include <linux/spi/sh_hspi.h> +-#include <linux/mmc/host.h> +-#include <linux/mmc/sh_mobile_sdhi.h> +-#include <linux/mfd/tmio.h> +- +-#include <media/soc_camera.h> +-#include <asm/mach-types.h> +-#include <asm/mach/arch.h> +-#include <asm/traps.h> +- +-#include "common.h" +-#include "irqs.h" +-#include "r8a7779.h" +- +-/* Fixed 3.3V regulator to be used by SDHI0 */ +-static struct regulator_consumer_supply fixed3v3_power_consumers[] = { +- REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), +- REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +-}; +- +-/* Dummy supplies, where voltage doesn't matter */ +-static struct regulator_consumer_supply dummy_supplies[] = { +- REGULATOR_SUPPLY("vddvario", "smsc911x"), +- REGULATOR_SUPPLY("vdd33a", "smsc911x"), +-}; +- +-/* USB PHY */ +-static struct resource usb_phy_resources[] = { +- [0] = { +- .start = 0xffe70800, +- .end = 0xffe70900 - 1, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct rcar_phy_platform_data usb_phy_platform_data; +- +-static struct platform_device usb_phy = { +- .name = "rcar_usb_phy", +- .id = -1, +- .dev = { +- .platform_data = &usb_phy_platform_data, +- }, +- .resource = usb_phy_resources, +- .num_resources = ARRAY_SIZE(usb_phy_resources), +-}; +- +-/* SMSC LAN89218 */ +-static struct resource smsc911x_resources[] = { +- [0] = { +- .start = 0x18000000, /* ExCS0 */ +- .end = 0x180000ff, /* A1->A7 */ +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = irq_pin(1), /* IRQ 1 */ +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct smsc911x_platform_config smsc911x_platdata = { +- .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */ +- .phy_interface = PHY_INTERFACE_MODE_MII, +- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, +- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +-}; +- +-static struct platform_device eth_device = { +- .name = "smsc911x", +- .id = -1, +- .dev = { +- .platform_data = &smsc911x_platdata, +- }, +- .resource = smsc911x_resources, +- .num_resources = ARRAY_SIZE(smsc911x_resources), +-}; +- +-static struct resource sdhi0_resources[] = { +- [0] = { +- .name = "sdhi0", +- .start = 0xffe4c000, +- .end = 0xffe4c0ff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_iid(0x88), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct tmio_mmc_data sdhi0_platform_data = { +- .chan_priv_tx = (void *)HPBDMA_SLAVE_SDHI0_TX, +- .chan_priv_rx = (void *)HPBDMA_SLAVE_SDHI0_RX, +- .flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT, +- .capabilities = MMC_CAP_SD_HIGHSPEED, +-}; +- +-static struct platform_device sdhi0_device = { +- .name = "sh_mobile_sdhi", +- .num_resources = ARRAY_SIZE(sdhi0_resources), +- .resource = sdhi0_resources, +- .id = 0, +- .dev = { +- .platform_data = &sdhi0_platform_data, +- } +-}; +- +-/* Thermal */ +-static struct resource thermal_resources[] = { +- [0] = { +- .start = 0xFFC48000, +- .end = 0xFFC48038 - 1, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device thermal_device = { +- .name = "rcar_thermal", +- .resource = thermal_resources, +- .num_resources = ARRAY_SIZE(thermal_resources), +-}; +- +-/* HSPI */ +-static struct resource hspi_resources[] = { +- [0] = { +- .start = 0xFFFC7000, +- .end = 0xFFFC7018 - 1, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device hspi_device = { +- .name = "sh-hspi", +- .id = 0, +- .resource = hspi_resources, +- .num_resources = ARRAY_SIZE(hspi_resources), +-}; +- +-/* LEDS */ +-static struct gpio_led marzen_leds[] = { +- { +- .name = "led2", +- .gpio = RCAR_GP_PIN(4, 29), +- .default_state = LEDS_GPIO_DEFSTATE_ON, +- }, { +- .name = "led3", +- .gpio = RCAR_GP_PIN(4, 30), +- .default_state = LEDS_GPIO_DEFSTATE_ON, +- }, { +- .name = "led4", +- .gpio = RCAR_GP_PIN(4, 31), +- .default_state = LEDS_GPIO_DEFSTATE_ON, +- }, +-}; +- +-static struct gpio_led_platform_data marzen_leds_pdata = { +- .leds = marzen_leds, +- .num_leds = ARRAY_SIZE(marzen_leds), +-}; +- +-static struct platform_device leds_device = { +- .name = "leds-gpio", +- .id = 0, +- .dev = { +- .platform_data = &marzen_leds_pdata, +- }, +-}; +- +-/* VIN */ +-static struct rcar_vin_platform_data vin_platform_data __initdata = { +- .flags = RCAR_VIN_BT656, +-}; +- +-#define MARZEN_VIN(idx) \ +-static struct resource vin##idx##_resources[] __initdata = { \ +- DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ +- DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \ +-}; \ +- \ +-static struct platform_device_info vin##idx##_info __initdata = { \ +- .name = "r8a7779-vin", \ +- .id = idx, \ +- .res = vin##idx##_resources, \ +- .num_res = ARRAY_SIZE(vin##idx##_resources), \ +- .dma_mask = DMA_BIT_MASK(32), \ +- .data = &vin_platform_data, \ +- .size_data = sizeof(vin_platform_data), \ +-} +-MARZEN_VIN(1); +-MARZEN_VIN(3); +- +-#define MARZEN_CAMERA(idx) \ +-static struct i2c_board_info camera##idx##_info = { \ +- I2C_BOARD_INFO("adv7180", 0x20 + (idx)), \ +-}; \ +- \ +-static struct soc_camera_link iclink##idx##_adv7180 = { \ +- .bus_id = 1 + 2 * (idx), \ +- .i2c_adapter_id = 0, \ +- .board_info = &camera##idx##_info, \ +-}; \ +- \ +-static struct platform_device camera##idx##_device = { \ +- .name = "soc-camera-pdrv", \ +- .id = idx, \ +- .dev = { \ +- .platform_data = &iclink##idx##_adv7180, \ +- }, \ +-}; +- +-MARZEN_CAMERA(0); +-MARZEN_CAMERA(1); +- +-static struct platform_device *marzen_devices[] __initdata = { +- ð_device, +- &sdhi0_device, +- &thermal_device, +- &hspi_device, +- &leds_device, +- &usb_phy, +- &camera0_device, +- &camera1_device, +-}; +- +-static const struct pinctrl_map marzen_pinctrl_map[] = { +- /* DU (CN10: ARGB0, CN13: LVDS) */ +- PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", +- "du0_rgb888", "du0"), +- PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", +- "du0_sync_1", "du0"), +- PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", +- "du0_clk_out_0", "du0"), +- PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", +- "du1_rgb666", "du1"), +- PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", +- "du1_sync_1", "du1"), +- PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", +- "du1_clk_out", "du1"), +- /* HSPI0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779", +- "hspi0", "hspi0"), +- /* SCIF2 (CN18: DEBUG0) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779", +- "scif2_data_c", "scif2"), +- /* SCIF4 (CN19: DEBUG1) */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779", +- "scif4_data", "scif4"), +- /* SDHI0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", +- "sdhi0_data4", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", +- "sdhi0_ctrl", "sdhi0"), +- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", +- "sdhi0_cd", "sdhi0"), +- /* SMSC */ +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", +- "intc_irq1_b", "intc"), +- PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", +- "lbsc_ex_cs0", "lbsc"), +- /* USB0 */ +- PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779", +- "usb0", "usb0"), +- /* USB1 */ +- PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779", +- "usb1", "usb1"), +- /* USB2 */ +- PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779", +- "usb2", "usb2"), +- /* VIN1 */ +- PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779", +- "vin1_clk", "vin1"), +- PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779", +- "vin1_data8", "vin1"), +- /* VIN3 */ +- PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779", +- "vin3_clk", "vin3"), +- PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779", +- "vin3_data8", "vin3"), +-}; +- +-static void __init marzen_init(void) +-{ +- regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, +- ARRAY_SIZE(fixed3v3_power_consumers), 3300000); +- regulator_register_fixed(1, dummy_supplies, +- ARRAY_SIZE(dummy_supplies)); +- +- pinctrl_register_mappings(marzen_pinctrl_map, +- ARRAY_SIZE(marzen_pinctrl_map)); +- r8a7779_pinmux_init(); +- r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */ +- +- r8a7779_add_standard_devices(); +- platform_device_register_full(&vin1_info); +- platform_device_register_full(&vin3_info); +- platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); +-} +- +-static const char *marzen_boards_compat_dt[] __initdata = { +- "renesas,marzen", +- NULL, +-}; +- +-DT_MACHINE_START(MARZEN, "marzen") +- .smp = smp_ops(r8a7779_smp_ops), +- .map_io = r8a7779_map_io, +- .init_early = r8a7779_add_early_devices, +- .init_irq = r8a7779_init_irq_dt, +- .init_machine = marzen_init, +- .init_late = r8a7779_init_late, +- .dt_compat = marzen_boards_compat_dt, +- .init_time = r8a7779_earlytimer_init, +-MACHINE_END +-- +2.6.2 + diff --git a/patches.renesas/0199-ARM-shmobile-r8a7779-Remove-legacy-SoC-code.patch b/patches.renesas/0199-ARM-shmobile-r8a7779-Remove-legacy-SoC-code.patch new file mode 100644 index 00000000000000..a06ca8d1010800 --- /dev/null +++ b/patches.renesas/0199-ARM-shmobile-r8a7779-Remove-legacy-SoC-code.patch @@ -0,0 +1,1100 @@ +From 30e3fa9cf63b7a65e10142a03e79697651a24574 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm+renesas@opensource.se> +Date: Thu, 16 Jul 2015 16:54:03 +0900 +Subject: [PATCH 199/326] ARM: shmobile: r8a7779: Remove legacy SoC code + +Now when the Marzen legacy board code is gone this patch +removes the unused r8a7779 legacy SoC code. + +Signed-off-by: Magnus Damm <damm+renesas@opensource.se> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c99cd90d98a98aa101b169e44d249e5cd71f46f2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Makefile | 1 - + arch/arm/mach-shmobile/clock-r8a7779.c | 271 ------------- + arch/arm/mach-shmobile/r8a7779.h | 17 - + arch/arm/mach-shmobile/setup-r8a7779.c | 674 +-------------------------------- + arch/arm/mach-shmobile/smp-r8a7779.c | 9 - + 5 files changed, 4 insertions(+), 968 deletions(-) + delete mode 100644 arch/arm/mach-shmobile/clock-r8a7779.c + +diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile +index 7bdb3ca099e1..476de30798d7 100644 +--- a/arch/arm/mach-shmobile/Makefile ++++ b/arch/arm/mach-shmobile/Makefile +@@ -22,7 +22,6 @@ obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o + ifndef CONFIG_COMMON_CLK + obj-y += clock.o + obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o +-obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o + endif + + # CPU reset vector handling objects +diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c +deleted file mode 100644 +index a376ba3b67c0..000000000000 +--- a/arch/arm/mach-shmobile/clock-r8a7779.c ++++ /dev/null +@@ -1,271 +0,0 @@ +-/* +- * r8a7779 clock framework support +- * +- * Copyright (C) 2011 Renesas Solutions Corp. +- * Copyright (C) 2011 Magnus Damm +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +-#include <linux/bitops.h> +-#include <linux/init.h> +-#include <linux/kernel.h> +-#include <linux/io.h> +-#include <linux/sh_clk.h> +-#include <linux/clkdev.h> +-#include <linux/sh_timer.h> +- +-#include "clock.h" +-#include "common.h" +-#include "r8a7779.h" +- +-/* +- * MD1 = 1 MD1 = 0 +- * (PLLA = 1500) (PLLA = 1600) +- * (MHz) (MHz) +- *------------------------------------------------+-------------------- +- * clkz 1000 (2/3) 800 (1/2) +- * clkzs 250 (1/6) 200 (1/8) +- * clki 750 (1/2) 800 (1/2) +- * clks 250 (1/6) 200 (1/8) +- * clks1 125 (1/12) 100 (1/16) +- * clks3 187.5 (1/8) 200 (1/8) +- * clks4 93.7 (1/16) 100 (1/16) +- * clkp 62.5 (1/24) 50 (1/32) +- * clkg 62.5 (1/24) 66.6 (1/24) +- * clkb, CLKOUT +- * (MD2 = 0) 62.5 (1/24) 66.6 (1/24) +- * (MD2 = 1) 41.6 (1/36) 50 (1/32) +-*/ +- +-#define MD(nr) BIT(nr) +- +-#define MSTPCR0 IOMEM(0xffc80030) +-#define MSTPCR1 IOMEM(0xffc80034) +-#define MSTPCR3 IOMEM(0xffc8003c) +-#define MSTPSR1 IOMEM(0xffc80044) +- +-/* ioremap() through clock mapping mandatory to avoid +- * collision with ARM coherent DMA virtual memory range. +- */ +- +-static struct clk_mapping cpg_mapping = { +- .phys = 0xffc80000, +- .len = 0x80, +-}; +- +-/* +- * Default rate for the root input clock, reset this with clk_set_rate() +- * from the platform code. +- */ +-static struct clk plla_clk = { +- /* .rate will be updated on r8a7779_clock_init() */ +- .mapping = &cpg_mapping, +-}; +- +-/* +- * clock ratio of these clock will be updated +- * on r8a7779_clock_init() +- */ +-SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1); +-SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1); +-SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1); +-SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1); +-SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1); +-SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1); +-SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1); +-SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1); +-SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1); +-SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1); +-SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1); +- +-static struct clk *main_clks[] = { +- &plla_clk, +- &clkz_clk, +- &clkzs_clk, +- &clki_clk, +- &clks_clk, +- &clks1_clk, +- &clks3_clk, +- &clks4_clk, +- &clkb_clk, +- &clkout_clk, +- &clkp_clk, +- &clkg_clk, +-}; +- +-enum { MSTP323, MSTP322, MSTP321, MSTP320, +- MSTP120, +- MSTP116, MSTP115, MSTP114, +- MSTP110, MSTP109, MSTP108, +- MSTP103, MSTP101, MSTP100, +- MSTP030, +- MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, +- MSTP016, MSTP015, MSTP014, +- MSTP007, +- MSTP_NR }; +- +-static struct clk mstp_clks[MSTP_NR] = { +- [MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */ +- [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ +- [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ +- [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ +- [MSTP120] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 20, MSTPSR1, 0), /* VIN3 */ +- [MSTP116] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 16, MSTPSR1, 0), /* PCIe */ +- [MSTP115] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 15, MSTPSR1, 0), /* SATA */ +- [MSTP114] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 14, MSTPSR1, 0), /* Ether */ +- [MSTP110] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 10, MSTPSR1, 0), /* VIN0 */ +- [MSTP109] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 9, MSTPSR1, 0), /* VIN1 */ +- [MSTP108] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 8, MSTPSR1, 0), /* VIN2 */ +- [MSTP103] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 3, MSTPSR1, 0), /* DU */ +- [MSTP101] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 1, MSTPSR1, 0), /* USB2 */ +- [MSTP100] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 0, MSTPSR1, 0), /* USB0/1 */ +- [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */ +- [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */ +- [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */ +- [MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */ +- [MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */ +- [MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */ +- [MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */ +- [MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */ +- [MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */ +- [MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */ +- [MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */ +- [MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */ +- [MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */ +- [MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */ +-}; +- +-static struct clk_lookup lookups[] = { +- /* main clocks */ +- CLKDEV_CON_ID("plla_clk", &plla_clk), +- CLKDEV_CON_ID("clkz_clk", &clkz_clk), +- CLKDEV_CON_ID("clkzs_clk", &clkzs_clk), +- +- /* DIV4 clocks */ +- CLKDEV_CON_ID("shyway_clk", &clks_clk), +- CLKDEV_CON_ID("bus_clk", &clkout_clk), +- CLKDEV_CON_ID("shyway4_clk", &clks4_clk), +- CLKDEV_CON_ID("shyway3_clk", &clks3_clk), +- CLKDEV_CON_ID("shyway1_clk", &clks1_clk), +- CLKDEV_CON_ID("peripheral_clk", &clkp_clk), +- +- /* MSTP32 clocks */ +- CLKDEV_DEV_ID("r8a7779-vin.3", &mstp_clks[MSTP120]), /* VIN3 */ +- CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */ +- CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ +- CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ +- CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ +- CLKDEV_DEV_ID("r8a7779-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ +- CLKDEV_DEV_ID("r8a7779-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ +- CLKDEV_DEV_ID("r8a7779-vin.2", &mstp_clks[MSTP108]), /* VIN2 */ +- CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */ +- CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */ +- CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ +- CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ +- CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]), /* TMU0 */ +- CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ +- CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */ +- CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ +- CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */ +- CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ +- CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */ +- CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ +- CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */ +- CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ +- CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ +- CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ +- CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */ +- CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ +- CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ +- CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ +- CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */ +- CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ +- CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */ +- CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ +- CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */ +- CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ +- CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */ +- CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ +- CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */ +- CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ +- CLKDEV_DEV_ID("ffe4e000.sd", &mstp_clks[MSTP321]), /* SDHI2 */ +- CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ +- CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP320]), /* SDHI3 */ +- CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ +-}; +- +-static void __init r8a7779_clock_init(void) +-{ +- u32 mode = r8a7779_read_mode_pins(); +- int k, ret = 0; +- +- if (mode & MD(1)) { +- plla_clk.rate = 1500000000; +- +- SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3); +- SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6); +- SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2); +- SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6); +- SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12); +- SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8); +- SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16); +- SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24); +- SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24); +- if (mode & MD(2)) { +- SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36); +- SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36); +- } else { +- SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24); +- SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24); +- } +- } else { +- plla_clk.rate = 1600000000; +- +- SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2); +- SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8); +- SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2); +- SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8); +- SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16); +- SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8); +- SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16); +- SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32); +- SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24); +- if (mode & MD(2)) { +- SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32); +- SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32); +- } else { +- SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24); +- SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24); +- } +- } +- +- for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) +- ret = clk_register(main_clks[k]); +- +- if (!ret) +- ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); +- +- clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +- +- if (!ret) +- shmobile_clk_init(); +- else +- panic("failed to setup r8a7779 clocks\n"); +-} +- +-/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ +-void __init __weak r8a7779_register_twd(void) { } +- +-void __init r8a7779_earlytimer_init(void) +-{ +- r8a7779_clock_init(); +- r8a7779_register_twd(); +- shmobile_earlytimer_init(); +-} +diff --git a/arch/arm/mach-shmobile/r8a7779.h b/arch/arm/mach-shmobile/r8a7779.h +index f69c7477178b..db303f76704e 100644 +--- a/arch/arm/mach-shmobile/r8a7779.h ++++ b/arch/arm/mach-shmobile/r8a7779.h +@@ -3,24 +3,7 @@ + + #include <linux/sh_clk.h> + +-/* HPB-DMA slave IDs */ +-enum { +- HPBDMA_SLAVE_DUMMY, +- HPBDMA_SLAVE_SDHI0_TX, +- HPBDMA_SLAVE_SDHI0_RX, +-}; +- +-extern void r8a7779_init_irq_extpin(int irlm); +-extern void r8a7779_init_irq_dt(void); +-extern void r8a7779_map_io(void); +-extern void r8a7779_earlytimer_init(void); +-extern void r8a7779_add_early_devices(void); +-extern void r8a7779_add_standard_devices(void); +-extern void r8a7779_init_late(void); +-extern u32 r8a7779_read_mode_pins(void); +-extern void r8a7779_pinmux_init(void); + extern void r8a7779_pm_init(void); +-extern void r8a7779_register_twd(void); + + #ifdef CONFIG_PM + extern void __init r8a7779_init_pm_domains(void); +diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c +index f436cba958fa..c18d85a96c67 100644 +--- a/arch/arm/mach-shmobile/setup-r8a7779.c ++++ b/arch/arm/mach-shmobile/setup-r8a7779.c +@@ -16,37 +16,15 @@ + */ + #include <linux/clk/shmobile.h> + #include <linux/clocksource.h> +-#include <linux/kernel.h> + #include <linux/init.h> +-#include <linux/interrupt.h> + #include <linux/irq.h> + #include <linux/irqchip.h> + #include <linux/irqchip/arm-gic.h> +-#include <linux/of_platform.h> +-#include <linux/platform_data/dma-rcar-hpbdma.h> +-#include <linux/platform_data/gpio-rcar.h> +-#include <linux/platform_data/irq-renesas-intc-irqpin.h> +-#include <linux/platform_device.h> +-#include <linux/delay.h> +-#include <linux/input.h> +-#include <linux/io.h> +-#include <linux/serial_sci.h> +-#include <linux/sh_timer.h> +-#include <linux/dma-mapping.h> +-#include <linux/usb/otg.h> +-#include <linux/usb/hcd.h> +-#include <linux/usb/ehci_pdriver.h> +-#include <linux/usb/ohci_pdriver.h> +-#include <linux/pm_runtime.h> + +-#include <asm/mach-types.h> + #include <asm/mach/arch.h> +-#include <asm/mach/time.h> + #include <asm/mach/map.h> +-#include <asm/hardware/cache-l2x0.h> + + #include "common.h" +-#include "irqs.h" + #include "r8a7779.h" + + static struct map_desc r8a7779_io_desc[] __initdata = { +@@ -66,7 +44,7 @@ static struct map_desc r8a7779_io_desc[] __initdata = { + }, + }; + +-void __init r8a7779_map_io(void) ++static void __init r8a7779_map_io(void) + { + debug_ll_io_init(); + iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); +@@ -82,652 +60,12 @@ void __init r8a7779_map_io(void) + #define INT2NTSR0 IOMEM(0xfe700060) + #define INT2NTSR1 IOMEM(0xfe700064) + +-static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = { +- .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ +- .sense_bitfield_width = 2, +-}; +- +-static struct resource irqpin0_resources[] __initdata = { +- DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ +- DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ +- DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ +- DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ +- DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ +- DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ +- DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ +- DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ +- DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ +-}; +- +-static void __init r8a7779_init_irq_extpin_dt(int irlm) +-{ +- void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); +- u32 tmp; +- +- if (!icr0) { +- pr_warn("r8a7779: unable to setup external irq pin mode\n"); +- return; +- } +- +- tmp = ioread32(icr0); +- if (irlm) +- tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ +- else +- tmp &= ~(1 << 23); /* IRL mode - not supported */ +- tmp |= (1 << 21); /* LVLMODE = 1 */ +- iowrite32(tmp, icr0); +- iounmap(icr0); +-} +- +-void __init r8a7779_init_irq_extpin(int irlm) +-{ +- r8a7779_init_irq_extpin_dt(irlm); +- if (irlm) +- platform_device_register_resndata( +- NULL, "renesas_intc_irqpin", -1, +- irqpin0_resources, ARRAY_SIZE(irqpin0_resources), +- &irqpin0_platform_data, sizeof(irqpin0_platform_data)); +-} +- +-/* PFC/GPIO */ +-static struct resource r8a7779_pfc_resources[] = { +- DEFINE_RES_MEM(0xfffc0000, 0x023c), +-}; +- +-static struct platform_device r8a7779_pfc_device = { +- .name = "pfc-r8a7779", +- .id = -1, +- .resource = r8a7779_pfc_resources, +- .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), +-}; +- +-#define R8A7779_GPIO(idx, npins) \ +-static struct resource r8a7779_gpio##idx##_resources[] = { \ +- DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \ +- DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \ +-}; \ +- \ +-static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \ +- .gpio_base = 32 * (idx), \ +- .irq_base = 0, \ +- .number_of_pins = npins, \ +- .pctl_name = "pfc-r8a7779", \ +-}; \ +- \ +-static struct platform_device r8a7779_gpio##idx##_device = { \ +- .name = "gpio_rcar", \ +- .id = idx, \ +- .resource = r8a7779_gpio##idx##_resources, \ +- .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \ +- .dev = { \ +- .platform_data = &r8a7779_gpio##idx##_platform_data, \ +- }, \ +-} +- +-R8A7779_GPIO(0, 32); +-R8A7779_GPIO(1, 32); +-R8A7779_GPIO(2, 32); +-R8A7779_GPIO(3, 32); +-R8A7779_GPIO(4, 32); +-R8A7779_GPIO(5, 32); +-R8A7779_GPIO(6, 9); +- +-static struct platform_device *r8a7779_pinctrl_devices[] __initdata = { +- &r8a7779_pfc_device, +- &r8a7779_gpio0_device, +- &r8a7779_gpio1_device, +- &r8a7779_gpio2_device, +- &r8a7779_gpio3_device, +- &r8a7779_gpio4_device, +- &r8a7779_gpio5_device, +- &r8a7779_gpio6_device, +-}; +- +-void __init r8a7779_pinmux_init(void) +-{ +- platform_add_devices(r8a7779_pinctrl_devices, +- ARRAY_SIZE(r8a7779_pinctrl_devices)); +-} +- +-/* SCIF */ +-#define R8A7779_SCIF(index, baseaddr, irq) \ +-static struct plat_sci_port scif##index##_platform_data = { \ +- .type = PORT_SCIF, \ +- .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ +- .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ +-}; \ +- \ +-static struct resource scif##index##_resources[] = { \ +- DEFINE_RES_MEM(baseaddr, 0x100), \ +- DEFINE_RES_IRQ(irq), \ +-}; \ +- \ +-static struct platform_device scif##index##_device = { \ +- .name = "sh-sci", \ +- .id = index, \ +- .resource = scif##index##_resources, \ +- .num_resources = ARRAY_SIZE(scif##index##_resources), \ +- .dev = { \ +- .platform_data = &scif##index##_platform_data, \ +- }, \ +-} +- +-R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78)); +-R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79)); +-R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a)); +-R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b)); +-R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c)); +-R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d)); +- +-/* TMU */ +-static struct sh_timer_config tmu0_platform_data = { +- .channels_mask = 7, +-}; +- +-static struct resource tmu0_resources[] = { +- DEFINE_RES_MEM(0xffd80000, 0x30), +- DEFINE_RES_IRQ(gic_iid(0x40)), +- DEFINE_RES_IRQ(gic_iid(0x41)), +- DEFINE_RES_IRQ(gic_iid(0x42)), +-}; +- +-static struct platform_device tmu0_device = { +- .name = "sh-tmu", +- .id = 0, +- .dev = { +- .platform_data = &tmu0_platform_data, +- }, +- .resource = tmu0_resources, +- .num_resources = ARRAY_SIZE(tmu0_resources), +-}; +- +-/* I2C */ +-static struct resource rcar_i2c0_res[] = { +- { +- .start = 0xffc70000, +- .end = 0xffc70fff, +- .flags = IORESOURCE_MEM, +- }, { +- .start = gic_iid(0x6f), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device i2c0_device = { +- .name = "i2c-rcar", +- .id = 0, +- .resource = rcar_i2c0_res, +- .num_resources = ARRAY_SIZE(rcar_i2c0_res), +-}; +- +-static struct resource rcar_i2c1_res[] = { +- { +- .start = 0xffc71000, +- .end = 0xffc71fff, +- .flags = IORESOURCE_MEM, +- }, { +- .start = gic_iid(0x72), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device i2c1_device = { +- .name = "i2c-rcar", +- .id = 1, +- .resource = rcar_i2c1_res, +- .num_resources = ARRAY_SIZE(rcar_i2c1_res), +-}; +- +-static struct resource rcar_i2c2_res[] = { +- { +- .start = 0xffc72000, +- .end = 0xffc72fff, +- .flags = IORESOURCE_MEM, +- }, { +- .start = gic_iid(0x70), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device i2c2_device = { +- .name = "i2c-rcar", +- .id = 2, +- .resource = rcar_i2c2_res, +- .num_resources = ARRAY_SIZE(rcar_i2c2_res), +-}; +- +-static struct resource rcar_i2c3_res[] = { +- { +- .start = 0xffc73000, +- .end = 0xffc73fff, +- .flags = IORESOURCE_MEM, +- }, { +- .start = gic_iid(0x71), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device i2c3_device = { +- .name = "i2c-rcar", +- .id = 3, +- .resource = rcar_i2c3_res, +- .num_resources = ARRAY_SIZE(rcar_i2c3_res), +-}; +- +-static struct resource sata_resources[] = { +- [0] = { +- .name = "rcar-sata", +- .start = 0xfc600000, +- .end = 0xfc601fff, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_iid(0x84), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device sata_device = { +- .name = "sata_rcar", +- .id = -1, +- .resource = sata_resources, +- .num_resources = ARRAY_SIZE(sata_resources), +- .dev = { +- .dma_mask = &sata_device.dev.coherent_dma_mask, +- .coherent_dma_mask = DMA_BIT_MASK(32), +- }, +-}; +- +-/* USB */ +-static struct usb_phy *phy; +- +-static int usb_power_on(struct platform_device *pdev) ++static void __init r8a7779_init_irq_dt(void) + { +- if (IS_ERR(phy)) +- return PTR_ERR(phy); +- +- pm_runtime_enable(&pdev->dev); +- pm_runtime_get_sync(&pdev->dev); +- +- usb_phy_init(phy); +- +- return 0; +-} +- +-static void usb_power_off(struct platform_device *pdev) +-{ +- if (IS_ERR(phy)) +- return; +- +- usb_phy_shutdown(phy); +- +- pm_runtime_put_sync(&pdev->dev); +- pm_runtime_disable(&pdev->dev); +-} +- +-static int ehci_init_internal_buffer(struct usb_hcd *hcd) +-{ +- /* +- * Below are recommended values from the datasheet; +- * see [USB :: Setting of EHCI Internal Buffer]. +- */ +- /* EHCI IP internal buffer setting */ +- iowrite32(0x00ff0040, hcd->regs + 0x0094); +- /* EHCI IP internal buffer enable */ +- iowrite32(0x00000001, hcd->regs + 0x009C); +- +- return 0; +-} +- +-static struct usb_ehci_pdata ehcix_pdata = { +- .power_on = usb_power_on, +- .power_off = usb_power_off, +- .power_suspend = usb_power_off, +- .pre_setup = ehci_init_internal_buffer, +-}; +- +-static struct resource ehci0_resources[] = { +- [0] = { +- .start = 0xffe70000, +- .end = 0xffe70400 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_iid(0x4c), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device ehci0_device = { +- .name = "ehci-platform", +- .id = 0, +- .dev = { +- .dma_mask = &ehci0_device.dev.coherent_dma_mask, +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &ehcix_pdata, +- }, +- .num_resources = ARRAY_SIZE(ehci0_resources), +- .resource = ehci0_resources, +-}; +- +-static struct resource ehci1_resources[] = { +- [0] = { +- .start = 0xfff70000, +- .end = 0xfff70400 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_iid(0x4d), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device ehci1_device = { +- .name = "ehci-platform", +- .id = 1, +- .dev = { +- .dma_mask = &ehci1_device.dev.coherent_dma_mask, +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &ehcix_pdata, +- }, +- .num_resources = ARRAY_SIZE(ehci1_resources), +- .resource = ehci1_resources, +-}; +- +-static struct usb_ohci_pdata ohcix_pdata = { +- .power_on = usb_power_on, +- .power_off = usb_power_off, +- .power_suspend = usb_power_off, +-}; +- +-static struct resource ohci0_resources[] = { +- [0] = { +- .start = 0xffe70400, +- .end = 0xffe70800 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_iid(0x4c), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device ohci0_device = { +- .name = "ohci-platform", +- .id = 0, +- .dev = { +- .dma_mask = &ohci0_device.dev.coherent_dma_mask, +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &ohcix_pdata, +- }, +- .num_resources = ARRAY_SIZE(ohci0_resources), +- .resource = ohci0_resources, +-}; +- +-static struct resource ohci1_resources[] = { +- [0] = { +- .start = 0xfff70400, +- .end = 0xfff70800 - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = gic_iid(0x4d), +- .flags = IORESOURCE_IRQ, +- }, +-}; +- +-static struct platform_device ohci1_device = { +- .name = "ohci-platform", +- .id = 1, +- .dev = { +- .dma_mask = &ohci1_device.dev.coherent_dma_mask, +- .coherent_dma_mask = 0xffffffff, +- .platform_data = &ohcix_pdata, +- }, +- .num_resources = ARRAY_SIZE(ohci1_resources), +- .resource = ohci1_resources, +-}; +- +-/* HPB-DMA */ +- +-/* Asynchronous mode register bits */ +-#define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */ +-#define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */ +-#define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */ +-#define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */ +-#define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */ +-#define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */ +-#define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */ +-#define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */ +-#define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */ +-#define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */ +-#define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */ +-#define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */ +-#define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */ +- +-static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { +- { +- .id = HPBDMA_SLAVE_SDHI0_TX, +- .addr = 0xffe4c000 + 0x30, +- .dcr = HPB_DMAE_DCR_SPDS_16BIT | +- HPB_DMAE_DCR_DMDL | +- HPB_DMAE_DCR_DPDS_16BIT, +- .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | +- HPB_DMAE_ASYNCRSTR_ASRST22 | +- HPB_DMAE_ASYNCRSTR_ASRST23, +- .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE | +- HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST, +- .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK | +- HPB_DMAE_ASYNCMDR_ASBTMD21_MASK, +- .port = 0x0D0C, +- .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, +- .dma_ch = 21, +- }, { +- .id = HPBDMA_SLAVE_SDHI0_RX, +- .addr = 0xffe4c000 + 0x30, +- .dcr = HPB_DMAE_DCR_SMDL | +- HPB_DMAE_DCR_SPDS_16BIT | +- HPB_DMAE_DCR_DPDS_16BIT, +- .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | +- HPB_DMAE_ASYNCRSTR_ASRST22 | +- HPB_DMAE_ASYNCRSTR_ASRST23, +- .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE | +- HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST, +- .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK | +- HPB_DMAE_ASYNCMDR_ASBTMD22_MASK, +- .port = 0x0D0C, +- .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, +- .dma_ch = 22, +- }, +-}; +- +-static const struct hpb_dmae_channel hpb_dmae_channels[] = { +- HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ +- HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ +-}; +- +-static struct hpb_dmae_pdata dma_platform_data __initdata = { +- .slaves = hpb_dmae_slaves, +- .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), +- .channels = hpb_dmae_channels, +- .num_channels = ARRAY_SIZE(hpb_dmae_channels), +- .ts_shift = { +- [XMIT_SZ_8BIT] = 0, +- [XMIT_SZ_16BIT] = 1, +- [XMIT_SZ_32BIT] = 2, +- }, +- .num_hw_channels = 44, +-}; +- +-static struct resource hpb_dmae_resources[] __initdata = { +- /* Channel registers */ +- DEFINE_RES_MEM(0xffc08000, 0x1000), +- /* Common registers */ +- DEFINE_RES_MEM(0xffc09000, 0x170), +- /* Asynchronous reset registers */ +- DEFINE_RES_MEM(0xffc00300, 4), +- /* Asynchronous mode registers */ +- DEFINE_RES_MEM(0xffc00400, 4), +- /* IRQ for DMA channels */ +- DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ), +-}; +- +-static void __init r8a7779_register_hpb_dmae(void) +-{ +- platform_device_register_resndata(NULL, "hpb-dma-engine", +- -1, hpb_dmae_resources, +- ARRAY_SIZE(hpb_dmae_resources), +- &dma_platform_data, +- sizeof(dma_platform_data)); +-} +- +-static struct platform_device *r8a7779_early_devices[] __initdata = { +- &tmu0_device, +-}; +- +-static struct platform_device *r8a7779_standard_devices[] __initdata = { +- &scif0_device, +- &scif1_device, +- &scif2_device, +- &scif3_device, +- &scif4_device, +- &scif5_device, +- &i2c0_device, +- &i2c1_device, +- &i2c2_device, +- &i2c3_device, +- &sata_device, +-}; +- +-void __init r8a7779_add_standard_devices(void) +-{ +-#ifdef CONFIG_CACHE_L2X0 +- /* Shared attribute override enable, 64K*16way */ +- l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); +-#endif +- r8a7779_pm_init(); +- +- r8a7779_init_pm_domains(); +- +- platform_add_devices(r8a7779_early_devices, +- ARRAY_SIZE(r8a7779_early_devices)); +- platform_add_devices(r8a7779_standard_devices, +- ARRAY_SIZE(r8a7779_standard_devices)); +- r8a7779_register_hpb_dmae(); +-} +- +-void __init r8a7779_add_early_devices(void) +-{ +- early_platform_add_devices(r8a7779_early_devices, +- ARRAY_SIZE(r8a7779_early_devices)); +- +- /* Early serial console setup is not included here due to +- * memory map collisions. The SCIF serial ports in r8a7779 +- * are difficult to identity map 1:1 due to collision with the +- * virtual memory range used by the coherent DMA code on ARM. +- * +- * Anyone wanting to debug early can remove UPF_IOREMAP from +- * the sh-sci serial console platform data, adjust mapbase +- * to a static M:N virt:phys mapping that needs to be added to +- * the mappings passed with iotable_init() above. +- * +- * Then add a call to shmobile_setup_console() from this function. +- * +- * As a final step pass earlyprint=sh-sci.2,115200 on the kernel +- * command line in case of the marzen board. +- */ +-} +- +-static struct platform_device *r8a7779_late_devices[] __initdata = { +- &ehci0_device, +- &ehci1_device, +- &ohci0_device, +- &ohci1_device, +-}; +- +-void __init r8a7779_init_late(void) +-{ +- /* get USB PHY */ +- phy = usb_get_phy(USB_PHY_TYPE_USB2); +- +- shmobile_init_late(); +- platform_add_devices(r8a7779_late_devices, +- ARRAY_SIZE(r8a7779_late_devices)); +-} +- +-#ifdef CONFIG_USE_OF +-void __init r8a7779_init_irq_dt(void) +-{ +-#ifdef CONFIG_ARCH_SHMOBILE_LEGACY +- void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000); +- void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000); +-#endif + gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE); + +-#ifdef CONFIG_ARCH_SHMOBILE_LEGACY +- gic_init(0, 29, gic_dist_base, gic_cpu_base); +-#else + irqchip_init(); +-#endif ++ + /* route all interrupts to ARM */ + __raw_writel(0xffffffff, INT2NTSR0); + __raw_writel(0x3fffffff, INT2NTSR1); +@@ -742,7 +80,7 @@ void __init r8a7779_init_irq_dt(void) + + #define MODEMR 0xffcc0020 + +-u32 __init r8a7779_read_mode_pins(void) ++static u32 __init r8a7779_read_mode_pins(void) + { + static u32 mode; + static bool mode_valid; +@@ -758,8 +96,6 @@ u32 __init r8a7779_read_mode_pins(void) + return mode; + } + +-#ifdef CONFIG_ARCH_SHMOBILE_MULTI +- + static void __init r8a7779_init_time(void) + { + r8a7779_clocks_init(r8a7779_read_mode_pins()); +@@ -780,5 +116,3 @@ DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") + .init_late = shmobile_init_late, + .dt_compat = r8a7779_compat_dt, + MACHINE_END +-#endif /* CONFIG_ARCH_SHMOBILE_MULTI */ +-#endif /* CONFIG_USE_OF */ +diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c +index 9122216df060..353562b8a5ee 100644 +--- a/arch/arm/mach-shmobile/smp-r8a7779.c ++++ b/arch/arm/mach-shmobile/smp-r8a7779.c +@@ -23,7 +23,6 @@ + #include <asm/cacheflush.h> + #include <asm/smp_plat.h> + #include <asm/smp_scu.h> +-#include <asm/smp_twd.h> + + #include "common.h" + #include "pm-rcar.h" +@@ -56,14 +55,6 @@ static const struct rcar_sysc_ch * const r8a7779_ch_cpu[4] = { + [3] = &r8a7779_ch_cpu3, + }; + +-#if defined(CONFIG_HAVE_ARM_TWD) && !defined(CONFIG_ARCH_MULTIPLATFORM) +-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29); +-void __init r8a7779_register_twd(void) +-{ +- twd_local_timer_register(&twd_local_timer); +-} +-#endif +- + static int r8a7779_platform_cpu_kill(unsigned int cpu) + { + const struct rcar_sysc_ch *ch = NULL; +-- +2.6.2 + diff --git a/patches.renesas/0200-ARM-shmobile-r8a7790-Add-JPU-device-node.patch b/patches.renesas/0200-ARM-shmobile-r8a7790-Add-JPU-device-node.patch new file mode 100644 index 00000000000000..974189f380144b --- /dev/null +++ b/patches.renesas/0200-ARM-shmobile-r8a7790-Add-JPU-device-node.patch @@ -0,0 +1,37 @@ +From 452a41833a980c7ef37a6d8d1a382ca92a6fb05e Mon Sep 17 00:00:00 2001 +From: Mikhail Ulyanov <mikhail.ulyanov@cogentembedded.com> +Date: Fri, 24 Jul 2015 16:25:45 +0300 +Subject: [PATCH 200/326] ARM: shmobile: r8a7790: Add JPU device node. + +This patch contains device tree node definition for JPEG codec peripheral +found in the Renesas R-Car r8a7790 SoC. + +Signed-off-by: Mikhail Ulyanov <mikhail.ulyanov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fb847575f8f5a9580c26bdc3e08fe49639144619) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index f1cdccc0a8c8..5b2952d5c700 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -872,6 +872,13 @@ + status = "disabled"; + }; + ++ jpu: jpeg-codec@fe980000 { ++ compatible = "renesas,jpu-r8a7790"; ++ reg = <0 0xfe980000 0 0x10300>; ++ interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp1_clks R8A7790_CLK_JPU>; ++ }; ++ + clocks { + #address-cells = <2>; + #size-cells = <2>; +-- +2.6.2 + diff --git a/patches.renesas/0201-ARM-shmobile-r8a7791-Add-JPU-device-node.patch b/patches.renesas/0201-ARM-shmobile-r8a7791-Add-JPU-device-node.patch new file mode 100644 index 00000000000000..09450db85c41f4 --- /dev/null +++ b/patches.renesas/0201-ARM-shmobile-r8a7791-Add-JPU-device-node.patch @@ -0,0 +1,37 @@ +From eef190746809edb78c716b38efbec4ac92dfbc1b Mon Sep 17 00:00:00 2001 +From: Mikhail Ulyanov <mikhail.ulyanov@cogentembedded.com> +Date: Fri, 24 Jul 2015 16:25:46 +0300 +Subject: [PATCH 201/326] ARM: shmobile: r8a7791: Add JPU device node. + +This patch contains device tree node definition for JPEG codec peripheral +found in the Renesas R-Car r8a7791 SoC. + +Signed-off-by: Mikhail Ulyanov <mikhail.ulyanov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0caa36603300dd4ff4841227cf372e91e940c8bd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi +index d37339bd7cdb..1cb6c2d07933 100644 +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -898,6 +898,13 @@ + status = "disabled"; + }; + ++ jpu: jpeg-codec@fe980000 { ++ compatible = "renesas,jpu-r8a7791"; ++ reg = <0 0xfe980000 0 0x10300>; ++ interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp1_clks R8A7791_CLK_JPU>; ++ }; ++ + clocks { + #address-cells = <2>; + #size-cells = <2>; +-- +2.6.2 + diff --git a/patches.renesas/0202-ARM-shmobile-r8a7794-add-PFC-DT-support.patch b/patches.renesas/0202-ARM-shmobile-r8a7794-add-PFC-DT-support.patch new file mode 100644 index 00000000000000..7923d4ff9e94c4 --- /dev/null +++ b/patches.renesas/0202-ARM-shmobile-r8a7794-add-PFC-DT-support.patch @@ -0,0 +1,38 @@ +From ec9f559d75f825e28e65c55f7b1a9007a16041ee Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Tue, 28 Jul 2015 01:29:31 +0300 +Subject: [PATCH 202/326] ARM: shmobile: r8a7794: add PFC DT support + +Define the generic R8A7794 part of the PFC device node. + +Based on original patch by Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fd1683c18c372d51aeeeb25efa8b451f922c9c52) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi +index 8824dbd5dbb4..51cc2b975c3f 100644 +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -108,6 +108,12 @@ + clocks = <&mstp4_clks R8A7794_CLK_IRQC>; + }; + ++ pfc: pin-controller@e6060000 { ++ compatible = "renesas,pfc-r8a7794"; ++ reg = <0 0xe6060000 0 0x11c>; ++ #gpio-range-cells = <3>; ++ }; ++ + dmac0: dma-controller@e6700000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; +-- +2.6.2 + diff --git a/patches.renesas/0203-ARM-shmobile-silk-initial-device-tree.patch b/patches.renesas/0203-ARM-shmobile-silk-initial-device-tree.patch new file mode 100644 index 00000000000000..45fd5a40c8df00 --- /dev/null +++ b/patches.renesas/0203-ARM-shmobile-silk-initial-device-tree.patch @@ -0,0 +1,93 @@ +From 489844a218c6f46e4ef35ee708d36a63694ac495 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 29 Jul 2015 01:14:59 +0300 +Subject: [PATCH 203/326] ARM: shmobile: silk: initial device tree + +Add the initial device tree for the R8A7794 SoC based SILK low cost board. +SCIF2 serial port support is included, so that the serial console can work. + +Based on the original patch by Vladimir Barinov +<vladimir.barinov@cogentembedded.com>. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a42fc57a9e9d1dbb1d8cc0c3ccf2d7ea1a939559) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/r8a7794-silk.dts | 51 ++++++++++++++++++++++++++++++++++++++ + 2 files changed, 52 insertions(+) + create mode 100644 arch/arm/boot/dts/r8a7794-silk.dts + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 964ae0041a67..e494ddc34319 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -491,6 +491,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ + r8a7791-koelsch.dtb \ + r8a7793-gose.dtb \ + r8a7794-alt.dtb \ ++ r8a7794-silk.dtb \ + sh73a0-kzm9g.dtb + dtb-$(CONFIG_ARCH_SOCFPGA) += \ + socfpga_arria5_socdk.dtb \ +diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts +new file mode 100644 +index 000000000000..f3da95b1dedd +--- /dev/null ++++ b/arch/arm/boot/dts/r8a7794-silk.dts +@@ -0,0 +1,51 @@ ++/* ++ * Device Tree Source for the SILK board ++ * ++ * Copyright (C) 2014 Renesas Electronics Corporation ++ * Copyright (C) 2014-2015 Renesas Solutions Corp. ++ * Copyright (C) 2014-2015 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++#include "r8a7794.dtsi" ++ ++/ { ++ model = "SILK"; ++ compatible = "renesas,silk", "renesas,r8a7794"; ++ ++ aliases { ++ serial0 = &scif2; ++ }; ++ ++ chosen { ++ bootargs = "ignore_loglevel"; ++ stdout-path = &scif2; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0 0x40000000 0 0x40000000>; ++ }; ++}; ++ ++&extal_clk { ++ clock-frequency = <20000000>; ++}; ++ ++&pfc { ++ scif2_pins: serial2 { ++ renesas,groups = "scif2_data"; ++ renesas,function = "scif2"; ++ }; ++}; ++ ++&scif2 { ++ pinctrl-0 = <&scif2_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; +-- +2.6.2 + diff --git a/patches.renesas/0204-ARM-shmobile-r8a7794-add-MMCIF-DT-support.patch b/patches.renesas/0204-ARM-shmobile-r8a7794-add-MMCIF-DT-support.patch new file mode 100644 index 00000000000000..2a64c0919f4aef --- /dev/null +++ b/patches.renesas/0204-ARM-shmobile-r8a7794-add-MMCIF-DT-support.patch @@ -0,0 +1,42 @@ +From 09e340e3c76ca26385d2cb35a03c6ac7ead56b3b Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 31 Jul 2015 00:54:05 +0300 +Subject: [PATCH 204/326] ARM: shmobile: r8a7794: add MMCIF DT support + +Define the generic R8A7794 part of the MMCIF0 device node. + +Based on the orginal patch by Shinobu Uehara <shinobu.uehara.xc@renesas.com>. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6cdf6ba19c8b9a386ef882206b29d97a49271317) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi +index 51cc2b975c3f..43acf185ecc4 100644 +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -383,6 +383,17 @@ + status = "disabled"; + }; + ++ mmcif0: mmc@ee200000 { ++ compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; ++ reg = <0 0xee200000 0 0x80>; ++ interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; ++ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; ++ dma-names = "tx", "rx"; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7794"; + reg = <0 0xee100000 0 0x200>; +-- +2.6.2 + diff --git a/patches.renesas/0205-ARM-shmobile-r8a73a4-dtsi-Add-missing-gpio-ranges-to.patch b/patches.renesas/0205-ARM-shmobile-r8a73a4-dtsi-Add-missing-gpio-ranges-to.patch new file mode 100644 index 00000000000000..75b39deebb084e --- /dev/null +++ b/patches.renesas/0205-ARM-shmobile-r8a73a4-dtsi-Add-missing-gpio-ranges-to.patch @@ -0,0 +1,70 @@ +From 097d29a9c165e7bc6db328caaf2631f123057d9a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 15:55:14 +0200 +Subject: [PATCH 205/326] ARM: shmobile: r8a73a4 dtsi: Add missing + "gpio-ranges" to gpio node + +If a GPIO driver uses gpiochip_add_pin_range() (which is usually the +case for GPIO/PFC combos), the GPIO hogging mechanism configured from DT +doesn't work: + + requesting hog GPIO led1-high (chip r8a73a4_pfc, offset 28) failed + +The actual error code is -517 == -EPROBE_DEFER. + +The problem is that PFC+GPIO registration is handled in multiple steps: + 1. pinctrl_register(), + 2. gpiochip_add(), + 3. gpiochip_add_pin_range(). + +Configuration of the hogs is handled in gpiochip_add(): + + gpiochip_add + of_gpiochip_add + of_gpiochip_scan_hogs + gpiod_hog + gpiochip_request_own_desc + __gpiod_request + chip->request + pinctrl_request_gpio + pinctrl_get_device_gpio_range + +However, at this point the GPIO controller hasn't been added to +pinctrldev_list yet, so the range can't be found, and the operation fails +with -EPROBE_DEFER. + +To fix this, add a "gpio-ranges" property to the gpio device node, so +the ranges are added by of_gpiochip_add_pin_range(), which is called by +of_gpiochip_add() before the call to of_gpiochip_scan_hogs(). + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 17ccec50cc40bef00b26d506d483e928804cb20e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a73a4.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi +index 5090d1a8f652..cb4f7b2798fe 100644 +--- a/arch/arm/boot/dts/r8a73a4.dtsi ++++ b/arch/arm/boot/dts/r8a73a4.dtsi +@@ -207,6 +207,13 @@ + reg = <0 0xe6050000 0 0x9000>; + gpio-controller; + #gpio-cells = <2>; ++ gpio-ranges = ++ <&pfc 0 0 31>, <&pfc 32 32 9>, ++ <&pfc 64 64 22>, <&pfc 96 96 31>, ++ <&pfc 128 128 7>, <&pfc 160 160 19>, ++ <&pfc 192 192 31>, <&pfc 224 224 27>, ++ <&pfc 256 256 28>, <&pfc 288 288 21>, ++ <&pfc 320 320 10>; + interrupts-extended = + <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, + <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, +-- +2.6.2 + diff --git a/patches.renesas/0206-ARM-shmobile-r8a7740-dtsi-Add-missing-gpio-ranges-to.patch b/patches.renesas/0206-ARM-shmobile-r8a7740-dtsi-Add-missing-gpio-ranges-to.patch new file mode 100644 index 00000000000000..86f26bab2d4fab --- /dev/null +++ b/patches.renesas/0206-ARM-shmobile-r8a7740-dtsi-Add-missing-gpio-ranges-to.patch @@ -0,0 +1,64 @@ +From b2b691e4954725d909adda858caa561b780a154a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 15:55:15 +0200 +Subject: [PATCH 206/326] ARM: shmobile: r8a7740 dtsi: Add missing + "gpio-ranges" to gpio node + +If a GPIO driver uses gpiochip_add_pin_range() (which is usually the +case for GPIO/PFC combos), the GPIO hogging mechanism configured from DT +doesn't work: + + requesting hog GPIO lcd0 (chip r8a7740_pfc, offset 176) failed + +The actual error code is -517 == -EPROBE_DEFER. + +The problem is that PFC+GPIO registration is handled in multiple steps: + 1. pinctrl_register(), + 2. gpiochip_add(), + 3. gpiochip_add_pin_range(). + +Configuration of the hogs is handled in gpiochip_add(): + + gpiochip_add + of_gpiochip_add + of_gpiochip_scan_hogs + gpiod_hog + gpiochip_request_own_desc + __gpiod_request + chip->request + pinctrl_request_gpio + pinctrl_get_device_gpio_range + +However, at this point the GPIO controller hasn't been added to +pinctrldev_list yet, so the range can't be found, and the operation fails +with -EPROBE_DEFER. + +To fix this, add a "gpio-ranges" property to the gpio device node, so +the range is added by of_gpiochip_add_pin_range(), which is called by +of_gpiochip_add() before the call to of_gpiochip_scan_hogs(). + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 09d1c7b4babd3ef9bfc0a148931e5e5702db5e1b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7740.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi +index d84714468cce..e14cb1438216 100644 +--- a/arch/arm/boot/dts/r8a7740.dtsi ++++ b/arch/arm/boot/dts/r8a7740.dtsi +@@ -291,6 +291,7 @@ + <0xe605800c 0x20>; + gpio-controller; + #gpio-cells = <2>; ++ gpio-ranges = <&pfc 0 0 212>; + interrupts-extended = + <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, + <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, +-- +2.6.2 + diff --git a/patches.renesas/0207-ARM-shmobile-sh73a0-dtsi-Add-missing-gpio-ranges-to-.patch b/patches.renesas/0207-ARM-shmobile-sh73a0-dtsi-Add-missing-gpio-ranges-to-.patch new file mode 100644 index 00000000000000..1b6d035c1b6b08 --- /dev/null +++ b/patches.renesas/0207-ARM-shmobile-sh73a0-dtsi-Add-missing-gpio-ranges-to-.patch @@ -0,0 +1,66 @@ +From 3d1eab6268135e4101b816a2146351093ccbb36b Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 15:55:16 +0200 +Subject: [PATCH 207/326] ARM: shmobile: sh73a0 dtsi: Add missing "gpio-ranges" + to gpio node + +If a GPIO driver uses gpiochip_add_pin_range() (which is usually the +case for GPIO/PFC combos), the GPIO hogging mechanism configured from DT +doesn't work: + + requesting hog GPIO led1-high (chip sh73a0_pfc, offset 20) failed + +The actual error code is -517 == -EPROBE_DEFER. + +The problem is that PFC+GPIO registration is handled in multiple steps: + 1. pinctrl_register(), + 2. gpiochip_add(), + 3. gpiochip_add_pin_range(). + +Configuration of the hogs is handled in gpiochip_add(): + + gpiochip_add + of_gpiochip_add + of_gpiochip_scan_hogs + gpiod_hog + gpiochip_request_own_desc + __gpiod_request + chip->request + pinctrl_request_gpio + pinctrl_get_device_gpio_range + +However, at this point the GPIO controller hasn't been added to +pinctrldev_list yet, so the range can't be found, and the operation fails +with -EPROBE_DEFER. + +To fix this, add a "gpio-ranges" property to the gpio device node, so +the ranges are added by of_gpiochip_add_pin_range(), which is called by +of_gpiochip_add() before the call to of_gpiochip_scan_hogs(). + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Acked-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 94bdc48d55ca10f90b4a625f0e443197e0013557) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/sh73a0.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi +index 11e17c5f26e2..ff7c8f298f30 100644 +--- a/arch/arm/boot/dts/sh73a0.dtsi ++++ b/arch/arm/boot/dts/sh73a0.dtsi +@@ -392,6 +392,9 @@ + <0xe605801c 0x1c>; + gpio-controller; + #gpio-cells = <2>; ++ gpio-ranges = ++ <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>, ++ <&pfc 288 288 22>; + interrupts-extended = + <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, + <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, +-- +2.6.2 + diff --git a/patches.renesas/0208-ARM-shmobile-r7s72100-dtsi-Add-CPG-MSTP-Clock-Domain.patch b/patches.renesas/0208-ARM-shmobile-r7s72100-dtsi-Add-CPG-MSTP-Clock-Domain.patch new file mode 100644 index 00000000000000..c6c68c60648d5e --- /dev/null +++ b/patches.renesas/0208-ARM-shmobile-r7s72100-dtsi-Add-CPG-MSTP-Clock-Domain.patch @@ -0,0 +1,182 @@ +From 313654a787fd6c06de61841556eea929d15696e3 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:07 +0200 +Subject: [PATCH 208/326] ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock + Domain + +Add an appropriate "#power-domain-cells" property to the cpg_clocks +device node, to create the CPG/MSTP Clock Domain. + +Add "power-domains" properties to all device nodes for devices that are +part of the CPG/MSTP Clock Domain and can be power-managed through an +MSTP clock. This applies to most on-SoC devices, which have a +one-to-one mapping from SoC device to DT device node. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cbe1f83818c6e2c05fca5045fcc4807177988d61) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100.dtsi | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi +index 277e73c110e5..060c32cbd669 100644 +--- a/arch/arm/boot/dts/r7s72100.dtsi ++++ b/arch/arm/boot/dts/r7s72100.dtsi +@@ -86,6 +86,7 @@ + reg = <0xfcfe0000 0x18>; + clocks = <&extal_clk>, <&usb_x1_clk>; + clock-output-names = "pll", "i", "g"; ++ #power-domain-cells = <0>; + }; + + /* MSTP clocks */ +@@ -157,6 +158,7 @@ + <0 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -169,6 +171,7 @@ + <0 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -181,6 +184,7 @@ + <0 197 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -193,6 +197,7 @@ + <0 201 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -205,6 +210,7 @@ + <0 205 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -217,6 +223,7 @@ + <0 209 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -229,6 +236,7 @@ + <0 213 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -241,6 +249,7 @@ + <0 217 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -252,6 +261,7 @@ + <0 240 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI0>; ++ power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; +@@ -266,6 +276,7 @@ + <0 243 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI1>; ++ power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; +@@ -280,6 +291,7 @@ + <0 246 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI2>; ++ power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; +@@ -294,6 +306,7 @@ + <0 249 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI3>; ++ power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; +@@ -308,6 +321,7 @@ + <0 252 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI4>; ++ power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; +@@ -338,6 +352,7 @@ + <0 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C0>; + clock-frequency = <100000>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -356,6 +371,7 @@ + <0 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C1>; + clock-frequency = <100000>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -374,6 +390,7 @@ + <0 180 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C2>; + clock-frequency = <100000>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -392,6 +409,7 @@ + <0 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C3>; + clock-frequency = <100000>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -402,6 +420,7 @@ + interrupt-names = "tgi0a"; + clocks = <&mstp3_clks R7S72100_CLK_MTU2>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + }; +-- +2.6.2 + diff --git a/patches.renesas/0209-ARM-shmobile-r8a7778-dtsi-Add-CPG-MSTP-Clock-Domain.patch b/patches.renesas/0209-ARM-shmobile-r8a7778-dtsi-Add-CPG-MSTP-Clock-Domain.patch new file mode 100644 index 00000000000000..607c835d9b3e05 --- /dev/null +++ b/patches.renesas/0209-ARM-shmobile-r8a7778-dtsi-Add-CPG-MSTP-Clock-Domain.patch @@ -0,0 +1,208 @@ +From f71a7af29f31ce505ea817914738b14aa3786f67 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:08 +0200 +Subject: [PATCH 209/326] ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock + Domain + +Add an appropriate "#power-domain-cells" property to the cpg_clocks +device node, to create the CPG/MSTP Clock Domain. + +Add "power-domains" properties to all device nodes for devices that are +part of the CPG/MSTP Clock Domain and can be power-managed through an +MSTP clock. This applies to most on-SoC devices, which have a +one-to-one mapping from SoC device to DT device node. A notable +exception is the "sound" node, which represents multiple SoC devices, +each having their own MSTP clocks. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a670f3667a0ad53eef1f66fde41acca890462ec9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7778.dtsi | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi +index 7ce9f5fd5865..4b1fa9f42ad5 100644 +--- a/arch/arm/boot/dts/r8a7778.dtsi ++++ b/arch/arm/boot/dts/r8a7778.dtsi +@@ -53,6 +53,7 @@ + reg = <0xfde00000 0x400>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7778_CLK_ETHER>; ++ power-domains = <&cpg_clocks>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; +@@ -152,6 +153,7 @@ + reg = <0xffc70000 0x1000>; + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C0>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -162,6 +164,7 @@ + reg = <0xffc71000 0x1000>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C1>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -172,6 +175,7 @@ + reg = <0xffc72000 0x1000>; + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C2>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -182,6 +186,7 @@ + reg = <0xffc73000 0x1000>; + interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C3>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -193,6 +198,7 @@ + <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_TMU0>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + #renesas,channels = <3>; + +@@ -207,6 +213,7 @@ + <0 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_TMU1>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + #renesas,channels = <3>; + +@@ -221,6 +228,7 @@ + <0 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_TMU2>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + #renesas,channels = <3>; + +@@ -288,6 +296,7 @@ + interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF0>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -297,6 +306,7 @@ + interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF1>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -306,6 +316,7 @@ + interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF2>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -315,6 +326,7 @@ + interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF3>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -324,6 +336,7 @@ + interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF4>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -333,6 +346,7 @@ + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF5>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -341,6 +355,7 @@ + reg = <0xffe4e000 0x100>; + interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_MMC>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -349,6 +364,7 @@ + reg = <0xffe4c000 0x100>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -357,6 +373,7 @@ + reg = <0xffe4d000 0x100>; + interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -365,6 +382,7 @@ + reg = <0xffe4f000 0x100>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -373,6 +391,7 @@ + reg = <0xfffc7000 0x18>; + interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_HSPI>; ++ power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -383,6 +402,7 @@ + reg = <0xfffc8000 0x18>; + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_HSPI>; ++ power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -393,6 +413,7 @@ + reg = <0xfffc6000 0x18>; + interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_HSPI>; ++ power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -419,6 +440,7 @@ + clocks = <&extal_clk>; + clock-output-names = "plla", "pllb", "b", + "out", "p", "s", "s1"; ++ #power-domain-cells = <0>; + }; + + /* Audio clocks; frequencies are set by boards if applicable. */ +-- +2.6.2 + diff --git a/patches.renesas/0210-ARM-shmobile-r8a7779-dtsi-Add-CPG-MSTP-Clock-Domain.patch b/patches.renesas/0210-ARM-shmobile-r8a7779-dtsi-Add-CPG-MSTP-Clock-Domain.patch new file mode 100644 index 00000000000000..ddec0b556d1369 --- /dev/null +++ b/patches.renesas/0210-ARM-shmobile-r8a7779-dtsi-Add-CPG-MSTP-Clock-Domain.patch @@ -0,0 +1,214 @@ +From 84523f3bc1df9cc33bb1a0c33a73219cc85da9f4 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:09 +0200 +Subject: [PATCH 210/326] ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock + Domain + +Add an appropriate "#power-domain-cells" property to the cpg_clocks +device node, to create the CPG/MSTP Clock Domain. + +Add "power-domains" properties to all device nodes for devices that are +part of the CPG/MSTP Clock Domain and can be power-managed through an +MSTP clock. This applies to most on-SoC devices, which have a +one-to-one mapping from SoC device to DT device node. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 33c3632a3f692d82ee0d080350bcd6d1c4cd151f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7779.dtsi | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi +index a2b5430d3257..6afa909865b5 100644 +--- a/arch/arm/boot/dts/r8a7779.dtsi ++++ b/arch/arm/boot/dts/r8a7779.dtsi +@@ -173,6 +173,7 @@ + reg = <0xffc70000 0x1000>; + interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_I2C0>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -183,6 +184,7 @@ + reg = <0xffc71000 0x1000>; + interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_I2C1>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -193,6 +195,7 @@ + reg = <0xffc72000 0x1000>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_I2C2>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -203,6 +206,7 @@ + reg = <0xffc73000 0x1000>; + interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_I2C3>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -212,6 +216,7 @@ + interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_SCIF0>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -221,6 +226,7 @@ + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_SCIF1>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -230,6 +236,7 @@ + interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_SCIF2>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -239,6 +246,7 @@ + interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_SCIF3>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -248,6 +256,7 @@ + interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_SCIF4>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -257,6 +266,7 @@ + interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_SCIF5>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -278,6 +288,7 @@ + <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_TMU0>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + #renesas,channels = <3>; + +@@ -292,6 +303,7 @@ + <0 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_TMU1>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + #renesas,channels = <3>; + +@@ -306,6 +318,7 @@ + <0 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_TMU2>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + #renesas,channels = <3>; + +@@ -317,6 +330,7 @@ + reg = <0xfc600000 0x2000>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7779_CLK_SATA>; ++ power-domains = <&cpg_clocks>; + }; + + sdhi0: sd@ffe4c000 { +@@ -324,6 +338,7 @@ + reg = <0xffe4c000 0x100>; + interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -332,6 +347,7 @@ + reg = <0xffe4d000 0x100>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -340,6 +356,7 @@ + reg = <0xffe4e000 0x100>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -348,6 +365,7 @@ + reg = <0xffe4f000 0x100>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -358,6 +376,7 @@ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mstp0_clks R8A7779_CLK_HSPI>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -368,6 +387,7 @@ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mstp0_clks R8A7779_CLK_HSPI>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -378,6 +398,7 @@ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mstp0_clks R8A7779_CLK_HSPI>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -386,6 +407,7 @@ + reg = <0 0xfff80000 0 0x40000>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7779_CLK_DU>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + + ports { +@@ -427,6 +449,7 @@ + #clock-cells = <1>; + clock-output-names = "plla", "z", "zs", "s", + "s1", "p", "b", "out"; ++ #power-domain-cells = <0>; + }; + + /* Fixed factor clocks */ +-- +2.6.2 + diff --git a/patches.renesas/0211-ARM-shmobile-r8a7790-dtsi-Add-CPG-MSTP-Clock-Domain.patch b/patches.renesas/0211-ARM-shmobile-r8a7790-dtsi-Add-CPG-MSTP-Clock-Domain.patch new file mode 100644 index 00000000000000..c17afcd4284a7c --- /dev/null +++ b/patches.renesas/0211-ARM-shmobile-r8a7790-dtsi-Add-CPG-MSTP-Clock-Domain.patch @@ -0,0 +1,605 @@ +From 76bf2c3947b1619e21d1eccde9884eda1f05eab7 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:10 +0200 +Subject: [PATCH 211/326] ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock + Domain + +Add an appropriate "#power-domain-cells" property to the cpg_clocks +device node, to create the CPG/MSTP Clock Domain. + +Add "power-domains" properties to all device nodes for devices that are +part of the CPG/MSTP Clock Domain and can be power-managed through an +MSTP clock. This applies to most on-SoC devices, which have a +one-to-one mapping from SoC device to DT device node. Notable +exceptions are the "display" and "sound" nodes, which represent multiple +SoC devices, each having their own MSTP clocks. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 484adb005886b1db79050afc7074d2356618b0c2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 86 +++++++++++++++++++++++++++++++++++++----- + 1 file changed, 77 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 5b2952d5c700..a0b2a79cbfbd 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -134,6 +134,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; ++ power-domains = <&cpg_clocks>; + }; + + gpio1: gpio@e6051000 { +@@ -146,6 +147,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; ++ power-domains = <&cpg_clocks>; + }; + + gpio2: gpio@e6052000 { +@@ -158,6 +160,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; ++ power-domains = <&cpg_clocks>; + }; + + gpio3: gpio@e6053000 { +@@ -170,6 +173,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; ++ power-domains = <&cpg_clocks>; + }; + + gpio4: gpio@e6054000 { +@@ -182,6 +186,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; ++ power-domains = <&cpg_clocks>; + }; + + gpio5: gpio@e6055000 { +@@ -194,6 +199,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; ++ power-domains = <&cpg_clocks>; + }; + + thermal@e61f0000 { +@@ -201,6 +207,7 @@ + reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; ++ power-domains = <&cpg_clocks>; + }; + + timer { +@@ -218,6 +225,7 @@ + <0 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_CMT0>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + renesas,channels-mask = <0x60>; + +@@ -237,6 +245,7 @@ + <0 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_CMT1>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + renesas,channels-mask = <0xff>; + +@@ -253,6 +262,7 @@ + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7790_CLK_IRQC>; ++ power-domains = <&cpg_clocks>; + }; + + dmac0: dma-controller@e6700000 { +@@ -281,6 +291,7 @@ + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <15>; + }; +@@ -311,6 +322,7 @@ + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <15>; + }; +@@ -339,6 +351,7 @@ + "ch12"; + clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <13>; + }; +@@ -367,6 +380,7 @@ + "ch12"; + clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <13>; + }; +@@ -378,6 +392,7 @@ + 0 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <2>; + }; +@@ -389,6 +404,7 @@ + 0 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <2>; + }; +@@ -400,6 +416,7 @@ + reg = <0 0xe6508000 0 0x40>; + interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_I2C0>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -410,6 +427,7 @@ + reg = <0 0xe6518000 0 0x40>; + interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_I2C1>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -420,6 +438,7 @@ + reg = <0 0xe6530000 0 0x40>; + interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_I2C2>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -430,6 +449,7 @@ + reg = <0 0xe6540000 0 0x40>; + interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_I2C3>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -442,6 +462,7 @@ + clocks = <&mstp3_clks R8A7790_CLK_IIC0>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -454,6 +475,7 @@ + clocks = <&mstp3_clks R8A7790_CLK_IIC1>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -466,6 +488,7 @@ + clocks = <&mstp3_clks R8A7790_CLK_IIC2>; + dmas = <&dmac0 0x69>, <&dmac0 0x6a>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -478,6 +501,7 @@ + clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -488,6 +512,7 @@ + clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; +@@ -500,6 +525,7 @@ + clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; +@@ -517,6 +543,7 @@ + clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; + dmas = <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -527,6 +554,7 @@ + clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; + dmas = <&dmac1 0xc9>, <&dmac1 0xca>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -537,6 +565,7 @@ + clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; + dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -547,6 +576,7 @@ + clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; + dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -558,6 +588,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -569,6 +600,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -580,6 +612,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -591,6 +624,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -602,6 +636,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -613,6 +648,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -624,6 +660,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -635,6 +672,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -646,6 +684,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -657,6 +696,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -665,6 +705,7 @@ + reg = <0 0xee700000 0 0x400>; + interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_ETHER>; ++ power-domains = <&cpg_clocks>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; +@@ -676,6 +717,7 @@ + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; ++ power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -686,6 +728,7 @@ + reg = <0 0xee300000 0 0x2000>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_SATA0>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -694,6 +737,7 @@ + reg = <0 0xee500000 0 0x2000>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_SATA1>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -702,12 +746,13 @@ + reg = <0 0xe6590000 0 0x100>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; +- renesas,buswait = <4>; +- phys = <&usb0 1>; +- phy-names = "usb"; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; ++ power-domains = <&cpg_clocks>; ++ renesas,buswait = <4>; ++ phys = <&usb0 1>; ++ phy-names = "usb"; + status = "disabled"; + }; + +@@ -718,6 +763,7 @@ + #size-cells = <0>; + clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; + clock-names = "usbhs"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + + usb0: usb-channel@0 { +@@ -732,33 +778,37 @@ + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7790"; +- clocks = <&mstp8_clks R8A7790_CLK_VIN0>; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp8_clks R8A7790_CLK_VIN0>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7790"; +- clocks = <&mstp8_clks R8A7790_CLK_VIN1>; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp8_clks R8A7790_CLK_VIN1>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7790"; +- clocks = <&mstp8_clks R8A7790_CLK_VIN2>; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp8_clks R8A7790_CLK_VIN2>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7790"; +- clocks = <&mstp8_clks R8A7790_CLK_VIN3>; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp8_clks R8A7790_CLK_VIN3>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -767,6 +817,7 @@ + reg = <0 0xfe920000 0 0x8000>; + interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; ++ power-domains = <&cpg_clocks>; + + renesas,has-sru; + renesas,#rpf = <5>; +@@ -779,6 +830,7 @@ + reg = <0 0xfe928000 0 0x8000>; + interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; ++ power-domains = <&cpg_clocks>; + + renesas,has-lut; + renesas,has-sru; +@@ -792,6 +844,7 @@ + reg = <0 0xfe930000 0 0x8000>; + interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; ++ power-domains = <&cpg_clocks>; + + renesas,has-lif; + renesas,has-lut; +@@ -805,6 +858,7 @@ + reg = <0 0xfe938000 0 0x8000>; + interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; ++ power-domains = <&cpg_clocks>; + + renesas,has-lif; + renesas,has-lut; +@@ -859,6 +913,7 @@ + clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, + <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -869,6 +924,7 @@ + clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, + <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -877,6 +933,7 @@ + reg = <0 0xfe980000 0 0x10300>; + interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_JPU>; ++ power-domains = <&cpg_clocks>; + }; + + clocks { +@@ -953,6 +1010,7 @@ + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "sd1", + "z", "rcan", "adsp"; ++ #power-domain-cells = <0>; + }; + + /* Variable factor clocks */ +@@ -1343,6 +1401,7 @@ + clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; +@@ -1356,6 +1415,7 @@ + clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1368,6 +1428,7 @@ + clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1380,6 +1441,7 @@ + clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1392,6 +1454,7 @@ + clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; + dmas = <&dmac0 0x45>, <&dmac0 0x46>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1402,6 +1465,7 @@ + reg = <0 0xee000000 0 0xc00>; + interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; ++ power-domains = <&cpg_clocks>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; +@@ -1410,10 +1474,11 @@ + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7790"; + device_type = "pci"; +- clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp7_clks R8A7790_CLK_EHCI>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + + bus-range = <0 0>; +@@ -1444,10 +1509,11 @@ + pci1: pci@ee0b0000 { + compatible = "renesas,pci-r8a7790"; + device_type = "pci"; +- clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + reg = <0 0xee0b0000 0 0xc00>, + <0 0xee0a0000 0 0x1100>; + interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp7_clks R8A7790_CLK_EHCI>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + + bus-range = <1 1>; +@@ -1465,6 +1531,7 @@ + compatible = "renesas,pci-r8a7790"; + device_type = "pci"; + clocks = <&mstp7_clks R8A7790_CLK_EHCI>; ++ power-domains = <&cpg_clocks>; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; +@@ -1517,6 +1584,7 @@ + interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +-- +2.6.2 + diff --git a/patches.renesas/0212-ARM-shmobile-r8a7791-dtsi-Add-CPG-MSTP-Clock-Domain.patch b/patches.renesas/0212-ARM-shmobile-r8a7791-dtsi-Add-CPG-MSTP-Clock-Domain.patch new file mode 100644 index 00000000000000..3276d8e0f5254d --- /dev/null +++ b/patches.renesas/0212-ARM-shmobile-r8a7791-dtsi-Add-CPG-MSTP-Clock-Domain.patch @@ -0,0 +1,635 @@ +From 60334da9cc98f3baa96de8bef4a4b152d337d302 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:11 +0200 +Subject: [PATCH 212/326] ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock + Domain + +Add an appropriate "#power-domain-cells" property to the cpg_clocks +device node, to create the CPG/MSTP Clock Domain. + +Add "power-domains" properties to all device nodes for devices that are +part of the CPG/MSTP Clock Domain and can be power-managed through an +MSTP clock. This applies to most on-SoC devices, which have a +one-to-one mapping from SoC device to DT device node. Notable +exceptions are the "display" and "sound" nodes, which represent multiple +SoC devices, each having their own MSTP clocks. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 797a0626e08ca4af539cd4888ebbc8c5aacc993d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 88 ++++++++++++++++++++++++++++++++++++++---- + 1 file changed, 80 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi +index 1cb6c2d07933..831525dd39a6 100644 +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -91,6 +91,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; ++ power-domains = <&cpg_clocks>; + }; + + gpio1: gpio@e6051000 { +@@ -103,6 +104,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; ++ power-domains = <&cpg_clocks>; + }; + + gpio2: gpio@e6052000 { +@@ -115,6 +117,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; ++ power-domains = <&cpg_clocks>; + }; + + gpio3: gpio@e6053000 { +@@ -127,6 +130,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; ++ power-domains = <&cpg_clocks>; + }; + + gpio4: gpio@e6054000 { +@@ -139,6 +143,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; ++ power-domains = <&cpg_clocks>; + }; + + gpio5: gpio@e6055000 { +@@ -151,6 +156,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; ++ power-domains = <&cpg_clocks>; + }; + + gpio6: gpio@e6055400 { +@@ -163,6 +169,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; ++ power-domains = <&cpg_clocks>; + }; + + gpio7: gpio@e6055800 { +@@ -175,6 +182,7 @@ + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; ++ power-domains = <&cpg_clocks>; + }; + + thermal@e61f0000 { +@@ -182,6 +190,7 @@ + reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; ++ power-domains = <&cpg_clocks>; + }; + + timer { +@@ -199,6 +208,7 @@ + <0 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_CMT0>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + renesas,channels-mask = <0x60>; + +@@ -218,6 +228,7 @@ + <0 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_CMT1>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + renesas,channels-mask = <0xff>; + +@@ -240,6 +251,7 @@ + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7791_CLK_IRQC>; ++ power-domains = <&cpg_clocks>; + }; + + dmac0: dma-controller@e6700000 { +@@ -268,6 +280,7 @@ + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <15>; + }; +@@ -298,6 +311,7 @@ + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <15>; + }; +@@ -326,6 +340,7 @@ + "ch12"; + clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <13>; + }; +@@ -354,6 +369,7 @@ + "ch12"; + clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <13>; + }; +@@ -365,6 +381,7 @@ + 0 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <2>; + }; +@@ -376,6 +393,7 @@ + 0 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <2>; + }; +@@ -388,6 +406,7 @@ + reg = <0 0xe6508000 0 0x40>; + interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C0>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -398,6 +417,7 @@ + reg = <0 0xe6518000 0 0x40>; + interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C1>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -408,6 +428,7 @@ + reg = <0 0xe6530000 0 0x40>; + interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C2>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -418,6 +439,7 @@ + reg = <0 0xe6540000 0 0x40>; + interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C3>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -428,6 +450,7 @@ + reg = <0 0xe6520000 0 0x40>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C4>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -439,6 +462,7 @@ + reg = <0 0xe6528000 0 0x40>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C5>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -452,6 +476,7 @@ + clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -464,6 +489,7 @@ + clocks = <&mstp3_clks R8A7791_CLK_IIC0>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -476,6 +502,7 @@ + clocks = <&mstp3_clks R8A7791_CLK_IIC1>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -492,6 +519,7 @@ + clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; +@@ -504,6 +532,7 @@ + clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; + dmas = <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -514,6 +543,7 @@ + clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; + dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -524,6 +554,7 @@ + clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; + dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -535,6 +566,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -546,6 +578,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -557,6 +590,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -568,6 +602,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -579,6 +614,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -590,6 +626,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -601,6 +638,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -612,6 +650,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -623,6 +662,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -634,6 +674,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -645,6 +686,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -656,6 +698,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -667,6 +710,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -678,6 +722,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -689,6 +734,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -700,6 +746,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -711,6 +758,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -722,6 +770,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -730,6 +779,7 @@ + reg = <0 0xee700000 0 0x400>; + interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7791_CLK_ETHER>; ++ power-domains = <&cpg_clocks>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; +@@ -741,6 +791,7 @@ + reg = <0 0xee300000 0 0x2000>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7791_CLK_SATA0>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -749,6 +800,7 @@ + reg = <0 0xee500000 0 0x2000>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7791_CLK_SATA1>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -757,12 +809,13 @@ + reg = <0 0xe6590000 0 0x100>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; +- renesas,buswait = <4>; +- phys = <&usb0 1>; +- phy-names = "usb"; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; ++ power-domains = <&cpg_clocks>; ++ renesas,buswait = <4>; ++ phys = <&usb0 1>; ++ phy-names = "usb"; + status = "disabled"; + }; + +@@ -773,6 +826,7 @@ + #size-cells = <0>; + clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; + clock-names = "usbhs"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + + usb0: usb-channel@0 { +@@ -787,25 +841,28 @@ + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7791"; +- clocks = <&mstp8_clks R8A7791_CLK_VIN0>; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp8_clks R8A7791_CLK_VIN0>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7791"; +- clocks = <&mstp8_clks R8A7791_CLK_VIN1>; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp8_clks R8A7791_CLK_VIN1>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7791"; +- clocks = <&mstp8_clks R8A7791_CLK_VIN2>; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp8_clks R8A7791_CLK_VIN2>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -814,6 +871,7 @@ + reg = <0 0xfe928000 0 0x8000>; + interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; ++ power-domains = <&cpg_clocks>; + + renesas,has-lut; + renesas,has-sru; +@@ -827,6 +885,7 @@ + reg = <0 0xfe930000 0 0x8000>; + interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; ++ power-domains = <&cpg_clocks>; + + renesas,has-lif; + renesas,has-lut; +@@ -840,6 +899,7 @@ + reg = <0 0xfe938000 0 0x8000>; + interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; ++ power-domains = <&cpg_clocks>; + + renesas,has-lif; + renesas,has-lut; +@@ -885,6 +945,7 @@ + clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, + <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -895,6 +956,7 @@ + clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, + <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -903,6 +965,7 @@ + reg = <0 0xfe980000 0 0x10300>; + interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_JPU>; ++ power-domains = <&cpg_clocks>; + }; + + clocks { +@@ -979,6 +1042,7 @@ + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "z", + "rcan", "adsp"; ++ #power-domain-cells = <0>; + }; + + /* Variable factor clocks */ +@@ -1361,6 +1425,7 @@ + clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; +@@ -1374,6 +1439,7 @@ + clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1386,6 +1452,7 @@ + clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1398,6 +1465,7 @@ + clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1408,6 +1476,7 @@ + reg = <0 0xee000000 0 0xc00>; + interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; ++ power-domains = <&cpg_clocks>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; +@@ -1416,10 +1485,11 @@ + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7791"; + device_type = "pci"; +- clocks = <&mstp7_clks R8A7791_CLK_EHCI>; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp7_clks R8A7791_CLK_EHCI>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + + bus-range = <0 0>; +@@ -1450,10 +1520,11 @@ + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7791"; + device_type = "pci"; +- clocks = <&mstp7_clks R8A7791_CLK_EHCI>; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&mstp7_clks R8A7791_CLK_EHCI>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + + bus-range = <1 1>; +@@ -1503,6 +1574,7 @@ + interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +-- +2.6.2 + diff --git a/patches.renesas/0213-ARM-shmobile-r8a7793-dtsi-Add-CPG-MSTP-Clock-Domain.patch b/patches.renesas/0213-ARM-shmobile-r8a7793-dtsi-Add-CPG-MSTP-Clock-Domain.patch new file mode 100644 index 00000000000000..4b2699dd840f29 --- /dev/null +++ b/patches.renesas/0213-ARM-shmobile-r8a7793-dtsi-Add-CPG-MSTP-Clock-Domain.patch @@ -0,0 +1,86 @@ +From 12de21984a47aadcd7ed83d59ebe2d097ee2a6e1 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:12 +0200 +Subject: [PATCH 213/326] ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock + Domain + +Add an appropriate "#power-domain-cells" property to the cpg_clocks +device node, to create the CPG/MSTP Clock Domain. + +Add "power-domains" properties to all device nodes for devices that are +part of the CPG/MSTP Clock Domain and can be power-managed through an +MSTP clock. This applies to most on-SoC devices, which have a +one-to-one mapping from SoC device to DT device node. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 4b31bad51f83bcce039e43f1659ffcb4bff454dc) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7793.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi +index 3355c487d108..c4654047e684 100644 +--- a/arch/arm/boot/dts/r8a7793.dtsi ++++ b/arch/arm/boot/dts/r8a7793.dtsi +@@ -68,6 +68,7 @@ + <0 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7793_CLK_CMT0>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + renesas,channels-mask = <0x60>; + +@@ -87,6 +88,7 @@ + <0 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7793_CLK_CMT1>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + renesas,channels-mask = <0xff>; + +@@ -109,6 +111,7 @@ + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7793_CLK_IRQC>; ++ power-domains = <&cpg_clocks>; + }; + + scif0: serial@e6e60000 { +@@ -117,6 +120,7 @@ + interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7793_CLK_SCIF0>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -126,6 +130,7 @@ + interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7793_CLK_SCIF1>; + clock-names = "sci_ick"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -134,6 +139,7 @@ + reg = <0 0xee700000 0 0x400>; + interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7793_CLK_ETHER>; ++ power-domains = <&cpg_clocks>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; +@@ -164,6 +170,7 @@ + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "z", + "rcan", "adsp"; ++ #power-domain-cells = <0>; + }; + + /* Variable factor clocks */ +-- +2.6.2 + diff --git a/patches.renesas/0214-ARM-shmobile-r8a7794-dtsi-Add-CPG-MSTP-Clock-Domain.patch b/patches.renesas/0214-ARM-shmobile-r8a7794-dtsi-Add-CPG-MSTP-Clock-Domain.patch new file mode 100644 index 00000000000000..7c990d67a36d63 --- /dev/null +++ b/patches.renesas/0214-ARM-shmobile-r8a7794-dtsi-Add-CPG-MSTP-Clock-Domain.patch @@ -0,0 +1,262 @@ +From 8fd2495a33b375a03c172a627d06bfa4119f761b Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:13 +0200 +Subject: [PATCH 214/326] ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock + Domain + +Add an appropriate "#power-domain-cells" property to the cpg_clocks +device node, to create the CPG/MSTP Clock Domain. + +Add "power-domains" properties to all device nodes for devices that are +part of the CPG/MSTP Clock Domain and can be power-managed through an +MSTP clock. This applies to most on-SoC devices, which have a +one-to-one mapping from SoC device to DT device node. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 60c0745a80be075bbd4e0925e4b740b3e588a445) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794.dtsi | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi +index 43acf185ecc4..97c8e9ace5eb 100644 +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -57,6 +57,7 @@ + <0 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7794_CLK_CMT0>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + renesas,channels-mask = <0x60>; + +@@ -76,6 +77,7 @@ + <0 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_CMT1>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + + renesas,channels-mask = <0xff>; + +@@ -106,6 +108,7 @@ + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7794_CLK_IRQC>; ++ power-domains = <&cpg_clocks>; + }; + + pfc: pin-controller@e6060000 { +@@ -140,6 +143,7 @@ + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <15>; + }; +@@ -170,6 +174,7 @@ + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; + clock-names = "fck"; ++ power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <15>; + }; +@@ -182,6 +187,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -193,6 +199,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -204,6 +211,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -215,6 +223,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -226,6 +235,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -237,6 +247,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -248,6 +259,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -259,6 +271,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -270,6 +283,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -281,6 +295,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -292,6 +307,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -303,6 +319,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -314,6 +331,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -325,6 +343,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -336,6 +355,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -347,6 +367,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -358,6 +379,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -369,6 +391,7 @@ + clock-names = "sci_ick"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -377,6 +400,7 @@ + reg = <0 0xee700000 0 0x400>; + interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7794_CLK_ETHER>; ++ power-domains = <&cpg_clocks>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; +@@ -390,6 +414,7 @@ + clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; + dma-names = "tx", "rx"; ++ power-domains = <&cpg_clocks>; + reg-io-width = <4>; + status = "disabled"; + }; +@@ -399,6 +424,7 @@ + reg = <0 0xee100000 0 0x200>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -407,6 +433,7 @@ + reg = <0 0xee140000 0 0x100>; + interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -415,6 +442,7 @@ + reg = <0 0xee160000 0 0x100>; + interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; ++ power-domains = <&cpg_clocks>; + status = "disabled"; + }; + +@@ -441,6 +469,7 @@ + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "z"; ++ #power-domain-cells = <0>; + }; + /* Variable factor clocks */ + sd2_clk: sd2_clk@e6150078 { +-- +2.6.2 + diff --git a/patches.renesas/0215-pinctrl-simplify-of_pinctrl_get.patch b/patches.renesas/0215-pinctrl-simplify-of_pinctrl_get.patch new file mode 100644 index 00000000000000..ae2d592a2a64d2 --- /dev/null +++ b/patches.renesas/0215-pinctrl-simplify-of_pinctrl_get.patch @@ -0,0 +1,37 @@ +From daa8152cf6936a0fad6fb2ed78bd59aa3c063ebe Mon Sep 17 00:00:00 2001 +From: Masahiro Yamada <yamada.masahiro@socionext.com> +Date: Thu, 18 Jun 2015 14:42:45 +0900 +Subject: [PATCH 215/326] pinctrl: simplify of_pinctrl_get() + +This commit does not change the logic at all. + +Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit fb00de771b0c35fc42212272596ddb07bf120b21) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/devicetree.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c +index 0bbf7d71b281..fe04e748dfe4 100644 +--- a/drivers/pinctrl/devicetree.c ++++ b/drivers/pinctrl/devicetree.c +@@ -97,13 +97,7 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename, + + struct pinctrl_dev *of_pinctrl_get(struct device_node *np) + { +- struct pinctrl_dev *pctldev; +- +- pctldev = get_pinctrl_dev_from_of_node(np); +- if (!pctldev) +- return NULL; +- +- return pctldev; ++ return get_pinctrl_dev_from_of_node(np); + } + + static int dt_to_map_one_config(struct pinctrl *p, const char *statename, +-- +2.6.2 + diff --git a/patches.renesas/0216-pinctrl-pinconf-Allow-groups-to-be-configured-via-de.patch b/patches.renesas/0216-pinctrl-pinconf-Allow-groups-to-be-configured-via-de.patch new file mode 100644 index 00000000000000..fec5c1f6bea75d --- /dev/null +++ b/patches.renesas/0216-pinctrl-pinconf-Allow-groups-to-be-configured-via-de.patch @@ -0,0 +1,64 @@ +From 7187a35b9cfb037af585b064ec5c733189d86b68 Mon Sep 17 00:00:00 2001 +From: Jon Hunter <jonathanh@nvidia.com> +Date: Tue, 14 Jul 2015 11:17:58 +0100 +Subject: [PATCH 216/326] pinctrl: pinconf: Allow groups to be configured via + debugfs + +The function pinconf_dbg_config_write() currently only supports configuring +a pin configuration mapping via the debugfs. Allow group mappings to also +be configured via the debugfs. + +Signed-off-by: Jon Hunter <jonathanh@nvidia.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 75629981069cf194336426bbbfb03f9c93d7ad67) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/pinconf.c | 20 ++++++++++++++------ + 1 file changed, 14 insertions(+), 6 deletions(-) + +diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c +index 1fc09dc20199..4744d6363dfb 100644 +--- a/drivers/pinctrl/pinconf.c ++++ b/drivers/pinctrl/pinconf.c +@@ -470,10 +470,12 @@ exit: + * pinconf_dbg_config_write() - modify the pinctrl config in the pinctrl + * map, of a dev/pin/state entry based on user entries to pinconf-config + * @user_buf: contains the modification request with expected format: +- * modify config_pin <devicename> <state> <pinname> <newvalue> ++ * modify <config> <devicename> <state> <name> <newvalue> + * modify is literal string, alternatives like add/delete not supported yet +- * config_pin is literal, alternatives like config_mux not supported yet +- * <devicename> <state> <pinname> are values that should match the pinctrl-maps ++ * <config> is the configuration to be changed. Supported configs are ++ * "config_pin" or "config_group", alternatives like config_mux are not ++ * supported yet. ++ * <devicename> <state> <name> are values that should match the pinctrl-maps + * <newvalue> reflects the new config and is driver dependant + */ + static ssize_t pinconf_dbg_config_write(struct file *file, +@@ -511,13 +513,19 @@ static ssize_t pinconf_dbg_config_write(struct file *file, + if (strcmp(token, "modify")) + return -EINVAL; + +- /* Get arg type: "config_pin" type supported so far */ ++ /* ++ * Get arg type: "config_pin" and "config_group" ++ * types are supported so far ++ */ + token = strsep(&b, " "); + if (!token) + return -EINVAL; +- if (strcmp(token, "config_pin")) ++ if (!strcmp(token, "config_pin")) ++ dbg->map_type = PIN_MAP_TYPE_CONFIGS_PIN; ++ else if (!strcmp(token, "config_group")) ++ dbg->map_type = PIN_MAP_TYPE_CONFIGS_GROUP; ++ else + return -EINVAL; +- dbg->map_type = PIN_MAP_TYPE_CONFIGS_PIN; + + /* get arg 'device_name' */ + token = strsep(&b, " "); +-- +2.6.2 + diff --git a/patches.renesas/0217-pinctrl-pinconf-Fix-display-of-configs.patch b/patches.renesas/0217-pinctrl-pinconf-Fix-display-of-configs.patch new file mode 100644 index 00000000000000..16c88771c141a0 --- /dev/null +++ b/patches.renesas/0217-pinctrl-pinconf-Fix-display-of-configs.patch @@ -0,0 +1,146 @@ +From 95b6a0e83bc5f021b0a5548d9af043dd140e7c34 Mon Sep 17 00:00:00 2001 +From: Jon Hunter <jonathanh@nvidia.com> +Date: Tue, 14 Jul 2015 11:17:59 +0100 +Subject: [PATCH 217/326] pinctrl: pinconf: Fix display of configs + +The function pinconf_dbg_config_print() only prints the configuration of +the 1st pin config in an array of pin configurations. Fix this so that +all pin configurations in the array are displayed. + +There are a few places in the code where the pin configs are displayed +and so add a helper function to display the pin configs to simplify the +code. + +Signed-off-by: Jon Hunter <jonathanh@nvidia.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit d96310aeddc692cf1f06861cf722c4843e0a3f28) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/pinconf.c | 64 ++++++++++++++++++++--------------------------- + 1 file changed, 27 insertions(+), 37 deletions(-) + +diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c +index 4744d6363dfb..cbf26a6992a0 100644 +--- a/drivers/pinctrl/pinconf.c ++++ b/drivers/pinctrl/pinconf.c +@@ -202,18 +202,34 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting) + + #ifdef CONFIG_DEBUG_FS + +-void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) ++void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev, ++ unsigned long *configs, unsigned num_configs) + { +- struct pinctrl_dev *pctldev; + const struct pinconf_ops *confops; + int i; + +- pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); + if (pctldev) + confops = pctldev->desc->confops; + else + confops = NULL; + ++ for (i = 0; i < num_configs; i++) { ++ seq_puts(s, "config "); ++ if (confops && confops->pin_config_config_dbg_show) ++ confops->pin_config_config_dbg_show(pctldev, s, ++ configs[i]); ++ else ++ seq_printf(s, "%08lx", configs[i]); ++ seq_puts(s, "\n"); ++ } ++} ++ ++void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) ++{ ++ struct pinctrl_dev *pctldev; ++ ++ pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); ++ + switch (map->type) { + case PIN_MAP_TYPE_CONFIGS_PIN: + seq_printf(s, "pin "); +@@ -227,15 +243,8 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) + + seq_printf(s, "%s\n", map->data.configs.group_or_pin); + +- for (i = 0; i < map->data.configs.num_configs; i++) { +- seq_printf(s, "config "); +- if (confops && confops->pin_config_config_dbg_show) +- confops->pin_config_config_dbg_show(pctldev, s, +- map->data.configs.configs[i]); +- else +- seq_printf(s, "%08lx", map->data.configs.configs[i]); +- seq_printf(s, "\n"); +- } ++ pinconf_show_config(s, pctldev, map->data.configs.configs, ++ map->data.configs.num_configs); + } + + void pinconf_show_setting(struct seq_file *s, +@@ -243,9 +252,7 @@ void pinconf_show_setting(struct seq_file *s, + { + struct pinctrl_dev *pctldev = setting->pctldev; + const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; +- const struct pinconf_ops *confops = pctldev->desc->confops; + struct pin_desc *desc; +- int i; + + switch (setting->type) { + case PIN_MAP_TYPE_CONFIGS_PIN: +@@ -269,17 +276,8 @@ void pinconf_show_setting(struct seq_file *s, + * FIXME: We should really get the pin controler to dump the config + * values, so they can be decoded to something meaningful. + */ +- for (i = 0; i < setting->data.configs.num_configs; i++) { +- seq_printf(s, " "); +- if (confops && confops->pin_config_config_dbg_show) +- confops->pin_config_config_dbg_show(pctldev, s, +- setting->data.configs.configs[i]); +- else +- seq_printf(s, "%08lx", +- setting->data.configs.configs[i]); +- } +- +- seq_printf(s, "\n"); ++ pinconf_show_config(s, pctldev, setting->data.configs.configs, ++ setting->data.configs.num_configs); + } + + static void pinconf_dump_pin(struct pinctrl_dev *pctldev, +@@ -412,10 +410,8 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d) + const struct pinctrl_map *map; + const struct pinctrl_map *found = NULL; + struct pinctrl_dev *pctldev; +- const struct pinconf_ops *confops = NULL; + struct dbg_cfg *dbg = &pinconf_dbg_conf; + int i, j; +- unsigned long config; + + mutex_lock(&pinctrl_maps_mutex); + +@@ -449,16 +445,10 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d) + } + + pctldev = get_pinctrl_dev_from_devname(found->ctrl_dev_name); +- config = *found->data.configs.configs; +- seq_printf(s, "Dev %s has config of %s in state %s: 0x%08lX\n", +- dbg->dev_name, dbg->pin_name, +- dbg->state_name, config); +- +- if (pctldev) +- confops = pctldev->desc->confops; +- +- if (confops && confops->pin_config_config_dbg_show) +- confops->pin_config_config_dbg_show(pctldev, s, config); ++ seq_printf(s, "Dev %s has config of %s in state %s:\n", ++ dbg->dev_name, dbg->pin_name, dbg->state_name); ++ pinconf_show_config(s, pctldev, found->data.configs.configs, ++ found->data.configs.num_configs); + + exit: + mutex_unlock(&pinctrl_maps_mutex); +-- +2.6.2 + diff --git a/patches.renesas/0218-pinctrl-pinconf-pinconf_show_config-can-be-static.patch b/patches.renesas/0218-pinctrl-pinconf-pinconf_show_config-can-be-static.patch new file mode 100644 index 00000000000000..b7a39a4cd8459e --- /dev/null +++ b/patches.renesas/0218-pinctrl-pinconf-pinconf_show_config-can-be-static.patch @@ -0,0 +1,29 @@ +From 193be519143e7b5584250604c6c790d492e06303 Mon Sep 17 00:00:00 2001 +From: kbuild test robot <fengguang.wu@intel.com> +Date: Fri, 17 Jul 2015 21:37:09 +0800 +Subject: [PATCH 218/326] pinctrl: pinconf: pinconf_show_config() can be static + +Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 6de52c15132f6b86030bf3159020e3314ec14952) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/pinconf.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c +index cbf26a6992a0..078e58d74fc0 100644 +--- a/drivers/pinctrl/pinconf.c ++++ b/drivers/pinctrl/pinconf.c +@@ -202,7 +202,7 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting) + + #ifdef CONFIG_DEBUG_FS + +-void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev, ++static void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev, + unsigned long *configs, unsigned num_configs) + { + const struct pinconf_ops *confops; +-- +2.6.2 + diff --git a/patches.renesas/0219-pinctrl-use-dev_err-to-show-message-in-pinctrl_regis.patch b/patches.renesas/0219-pinctrl-use-dev_err-to-show-message-in-pinctrl_regis.patch new file mode 100644 index 00000000000000..bd8edae216e95d --- /dev/null +++ b/patches.renesas/0219-pinctrl-use-dev_err-to-show-message-in-pinctrl_regis.patch @@ -0,0 +1,37 @@ +From 0099f9a36bf6bacf41d1e1da68d6f73d3bcbcf33 Mon Sep 17 00:00:00 2001 +From: Masahiro Yamada <yamada.masahiro@socionext.com> +Date: Tue, 21 Jul 2015 15:25:26 +0900 +Subject: [PATCH 219/326] pinctrl: use dev_err() to show message in + pinctrl_register_one_pin() + +Use dev_err() rather than pr_err() to display the error message. +(Besides, dev_err() is already used 7 lines below in this function.) + +Also, drop the redundant information "on %s" because dev_err() shows +which device the message is related to. + +Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 2b38ca6d1aaf9149f1286c93b131f3e62c3ac63b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/core.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c +index 8b8f3a04c353..69723e07036b 100644 +--- a/drivers/pinctrl/core.c ++++ b/drivers/pinctrl/core.c +@@ -231,8 +231,7 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, + + pindesc = pin_desc_get(pctldev, number); + if (pindesc != NULL) { +- pr_err("pin %d already registered on %s\n", number, +- pctldev->desc->name); ++ dev_err(pctldev->dev, "pin %d already registered\n", number); + return -EINVAL; + } + +-- +2.6.2 + diff --git a/patches.renesas/0220-pinctrl-use-dev_err-to-show-message-in-pinmux_func_n.patch b/patches.renesas/0220-pinctrl-use-dev_err-to-show-message-in-pinmux_func_n.patch new file mode 100644 index 00000000000000..0590f7c2ba40e7 --- /dev/null +++ b/patches.renesas/0220-pinctrl-use-dev_err-to-show-message-in-pinmux_func_n.patch @@ -0,0 +1,36 @@ +From 524aeecdf7903da0701283cda59419d0ae080ebc Mon Sep 17 00:00:00 2001 +From: Masahiro Yamada <yamada.masahiro@socionext.com> +Date: Tue, 21 Jul 2015 15:25:27 +0900 +Subject: [PATCH 220/326] pinctrl: use dev_err() to show message in + pinmux_func_name_to_selector() + +Use dev_err() rather than pr_err() to display the error message. + +pinctrl_dev_get_name(pctldev) is no longer necessary because +dev_err() shows which device the message is related to. + +Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit e324957096dbf5bbf1491231c9912c3f5d0bc216) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/pinmux.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c +index e7ae890dcf1a..67e08cb315c4 100644 +--- a/drivers/pinctrl/pinmux.c ++++ b/drivers/pinctrl/pinmux.c +@@ -322,8 +322,7 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev, + selector++; + } + +- pr_err("%s does not support function %s\n", +- pinctrl_dev_get_name(pctldev), function); ++ dev_err(pctldev->dev, "function '%s' not supported\n", function); + return -EINVAL; + } + +-- +2.6.2 + diff --git a/patches.renesas/0221-pinctrl-join-dev_dbg-strings-into-a-single-line.patch b/patches.renesas/0221-pinctrl-join-dev_dbg-strings-into-a-single-line.patch new file mode 100644 index 00000000000000..96809034a77daa --- /dev/null +++ b/patches.renesas/0221-pinctrl-join-dev_dbg-strings-into-a-single-line.patch @@ -0,0 +1,33 @@ +From da31db9522c067f4efe37fdb1d04646c6ac8282c Mon Sep 17 00:00:00 2001 +From: Masahiro Yamada <yamada.masahiro@socionext.com> +Date: Thu, 30 Jul 2015 17:27:44 +0900 +Subject: [PATCH 221/326] pinctrl: join dev_dbg strings into a single line + +These are user-visible strings, so can exceed 80 columns. + +Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit ca67f10f27b6aace4a87713f038577994ec578af) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/pinconf.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c +index 078e58d74fc0..29a7bb17a42f 100644 +--- a/drivers/pinctrl/pinconf.c ++++ b/drivers/pinctrl/pinconf.c +@@ -61,8 +61,8 @@ int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin, + const struct pinconf_ops *ops = pctldev->desc->confops; + + if (!ops || !ops->pin_config_get) { +- dev_dbg(pctldev->dev, "cannot get pin configuration, missing " +- "pin_config_get() function in driver\n"); ++ dev_dbg(pctldev->dev, ++ "cannot get pin configuration, .pin_config_get missing in driver\n"); + return -ENOTSUPP; + } + +-- +2.6.2 + diff --git a/patches.renesas/0222-media-media-soc_camera-rcar_vin-Add-BT.709-24-bit-RG.patch b/patches.renesas/0222-media-media-soc_camera-rcar_vin-Add-BT.709-24-bit-RG.patch new file mode 100644 index 00000000000000..20494f578988e5 --- /dev/null +++ b/patches.renesas/0222-media-media-soc_camera-rcar_vin-Add-BT.709-24-bit-RG.patch @@ -0,0 +1,88 @@ +From 425682df33f34e74d40c3adc386c17ee8280b0a2 Mon Sep 17 00:00:00 2001 +From: William Towle <william.towle@codethink.co.uk> +Date: Thu, 23 Jul 2015 09:21:36 -0300 +Subject: [PATCH 222/326] [media] media: soc_camera: rcar_vin: Add BT.709 + 24-bit RGB888 input support + +This adds V4L2_MBUS_FMT_RGB888_1X24 input format support +which is used by the ADV7612 chip. + +Modified to use MEDIA_BUS_FMT_* constants + +Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> +Signed-off-by: William Towle <william.towle@codethink.co.uk> +Reviewed-by: Rob Taylor <rob.taylor@codethink.co.uk> +Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit 920a1bf30a361fc2c6d713a26deb3a488639def3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/soc_camera/rcar_vin.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/drivers/media/platform/soc_camera/rcar_vin.c b/drivers/media/platform/soc_camera/rcar_vin.c +index 918390b5a08a..942247fc2ae6 100644 +--- a/drivers/media/platform/soc_camera/rcar_vin.c ++++ b/drivers/media/platform/soc_camera/rcar_vin.c +@@ -98,6 +98,7 @@ + #define VNMC_INF_YUV10_BT656 (2 << 16) + #define VNMC_INF_YUV10_BT601 (3 << 16) + #define VNMC_INF_YUV16 (5 << 16) ++#define VNMC_INF_RGB888 (6 << 16) + #define VNMC_VUP (1 << 10) + #define VNMC_IM_ODD (0 << 3) + #define VNMC_IM_ODD_EVEN (1 << 3) +@@ -589,7 +590,7 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) + struct soc_camera_device *icd = priv->ici.icd; + struct rcar_vin_cam *cam = icd->host_priv; + u32 vnmc, dmr, interrupts; +- bool progressive = false, output_is_yuv = false; ++ bool progressive = false, output_is_yuv = false, input_is_yuv = false; + + switch (priv->field) { + case V4L2_FIELD_TOP: +@@ -623,16 +624,22 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) + case MEDIA_BUS_FMT_YUYV8_1X16: + /* BT.601/BT.1358 16bit YCbCr422 */ + vnmc |= VNMC_INF_YUV16; ++ input_is_yuv = true; + break; + case MEDIA_BUS_FMT_YUYV8_2X8: + /* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */ + vnmc |= priv->pdata_flags & RCAR_VIN_BT656 ? + VNMC_INF_YUV8_BT656 : VNMC_INF_YUV8_BT601; ++ input_is_yuv = true; ++ break; ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ vnmc |= VNMC_INF_RGB888; + break; + case MEDIA_BUS_FMT_YUYV10_2X10: + /* BT.656 10bit YCbCr422 or BT.601 10bit YCbCr422 */ + vnmc |= priv->pdata_flags & RCAR_VIN_BT656 ? + VNMC_INF_YUV10_BT656 : VNMC_INF_YUV10_BT601; ++ input_is_yuv = true; + break; + default: + break; +@@ -676,7 +683,7 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) + vnmc |= VNMC_VUP; + + /* If input and output use the same colorspace, use bypass mode */ +- if (output_is_yuv) ++ if (input_is_yuv == output_is_yuv) + vnmc |= VNMC_BPS; + + /* progressive or interlaced mode */ +@@ -1417,6 +1424,7 @@ static int rcar_vin_get_formats(struct soc_camera_device *icd, unsigned int idx, + case MEDIA_BUS_FMT_YUYV8_1X16: + case MEDIA_BUS_FMT_YUYV8_2X8: + case MEDIA_BUS_FMT_YUYV10_2X10: ++ case MEDIA_BUS_FMT_RGB888_1X24: + if (cam->extra_fmt) + break; + +-- +2.6.2 + diff --git a/patches.renesas/0223-media-media-rcar_vin-fill-in-bus_info-field.patch b/patches.renesas/0223-media-media-rcar_vin-fill-in-bus_info-field.patch new file mode 100644 index 00000000000000..3b75bd83838edb --- /dev/null +++ b/patches.renesas/0223-media-media-rcar_vin-fill-in-bus_info-field.patch @@ -0,0 +1,33 @@ +From bf5dfa6e2175af33ca1e2653189bea227c79754a Mon Sep 17 00:00:00 2001 +From: Rob Taylor <rob.taylor@codethink.co.uk> +Date: Thu, 23 Jul 2015 09:21:42 -0300 +Subject: [PATCH 223/326] [media] media: rcar_vin: fill in bus_info field + +Adapt rcar_vin_querycap() so that cap->bus_info is populated with +something meaningful/unique. + +Signed-off-by: Rob Taylor <rob.taylor@codethink.co.uk> +Signed-off-by: William Towle <william.towle@codethink.co.uk> +Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit 734f3f238587ffb6938700c4495dd5b5a54c4125) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/soc_camera/rcar_vin.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/media/platform/soc_camera/rcar_vin.c b/drivers/media/platform/soc_camera/rcar_vin.c +index 942247fc2ae6..1f080241c2e0 100644 +--- a/drivers/media/platform/soc_camera/rcar_vin.c ++++ b/drivers/media/platform/soc_camera/rcar_vin.c +@@ -1778,6 +1778,7 @@ static int rcar_vin_querycap(struct soc_camera_host *ici, + strlcpy(cap->card, "R_Car_VIN", sizeof(cap->card)); + cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; ++ snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s%d", DRV_NAME, ici->nr); + + return 0; + } +-- +2.6.2 + diff --git a/patches.renesas/0224-media-media-rcar_vin-Reject-videobufs-that-are-too-s.patch b/patches.renesas/0224-media-media-rcar_vin-Reject-videobufs-that-are-too-s.patch new file mode 100644 index 00000000000000..5c3bdbda6d07fa --- /dev/null +++ b/patches.renesas/0224-media-media-rcar_vin-Reject-videobufs-that-are-too-s.patch @@ -0,0 +1,36 @@ +From d53f96c8a5fc89ee531ece2913391cd45f1a13c0 Mon Sep 17 00:00:00 2001 +From: Rob Taylor <rob.taylor@codethink.co.uk> +Date: Thu, 23 Jul 2015 09:21:43 -0300 +Subject: [PATCH 224/326] [media] media: rcar_vin: Reject videobufs that are + too small for current format + +In videobuf_setup reject buffers that are too small for the configured +format. Fixes v4l2-compliance issue. + +Signed-off-by: Rob Taylor <rob.taylor@codethink.co.uk> +Reviewed-by: William Towle <william.towle@codethink.co.uk> +Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit 4284118058b2b4f217a050908a555d0e1ed58641) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/soc_camera/rcar_vin.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/media/platform/soc_camera/rcar_vin.c b/drivers/media/platform/soc_camera/rcar_vin.c +index 1f080241c2e0..2d8cb52188e6 100644 +--- a/drivers/media/platform/soc_camera/rcar_vin.c ++++ b/drivers/media/platform/soc_camera/rcar_vin.c +@@ -541,6 +541,9 @@ static int rcar_vin_videobuf_setup(struct vb2_queue *vq, + unsigned int bytes_per_line; + int ret; + ++ if (fmt->fmt.pix.sizeimage < icd->sizeimage) ++ return -EINVAL; ++ + xlate = soc_camera_xlate_by_fourcc(icd, + fmt->fmt.pix.pixelformat); + if (!xlate) +-- +2.6.2 + diff --git a/patches.renesas/0225-spi-rspi-Drop-variable-error-in-qspi_trigger_transfe.patch b/patches.renesas/0225-spi-rspi-Drop-variable-error-in-qspi_trigger_transfe.patch new file mode 100644 index 00000000000000..0ce94f24321cc5 --- /dev/null +++ b/patches.renesas/0225-spi-rspi-Drop-variable-error-in-qspi_trigger_transfe.patch @@ -0,0 +1,54 @@ +From 7d89b40c489978bd2548c582a53b1f6cd47ce649 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 23 Jun 2015 15:04:28 +0200 +Subject: [PATCH 225/326] spi: rspi: Drop variable "error" in + qspi_trigger_transfer_out_in() + +Just use "ret" instead, for consistency with other similar functions. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 5d4db691ed978080435f4e5aad2ce707294a75b4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/spi/spi-rspi.c | 13 ++++++------- + 1 file changed, 6 insertions(+), 7 deletions(-) + +diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c +index f6bac9e77d06..d780deb45c3d 100644 +--- a/drivers/spi/spi-rspi.c ++++ b/drivers/spi/spi-rspi.c +@@ -728,24 +728,23 @@ static int qspi_trigger_transfer_out_int(struct rspi_data *rspi, const u8 *tx, + u8 *rx, unsigned int len) + { + int i, n, ret; +- int error; + + while (len > 0) { + n = qspi_set_send_trigger(rspi, len); + qspi_set_receive_trigger(rspi, len); + if (n == QSPI_BUFFER_SIZE) { +- error = rspi_wait_for_tx_empty(rspi); +- if (error < 0) { ++ ret = rspi_wait_for_tx_empty(rspi); ++ if (ret < 0) { + dev_err(&rspi->master->dev, "transmit timeout\n"); +- return error; ++ return ret; + } + for (i = 0; i < n; i++) + rspi_write_data(rspi, *tx++); + +- error = rspi_wait_for_rx_full(rspi); +- if (error < 0) { ++ ret = rspi_wait_for_rx_full(rspi); ++ if (ret < 0) { + dev_err(&rspi->master->dev, "receive timeout\n"); +- return error; ++ return ret; + } + for (i = 0; i < n; i++) + *rx++ = rspi_read_data(rspi); +-- +2.6.2 + diff --git a/patches.renesas/0226-spi-rspi-Make-qspi_set_send_trigger-return-unsigned-.patch b/patches.renesas/0226-spi-rspi-Make-qspi_set_send_trigger-return-unsigned-.patch new file mode 100644 index 00000000000000..626a38c8e106f6 --- /dev/null +++ b/patches.renesas/0226-spi-rspi-Make-qspi_set_send_trigger-return-unsigned-.patch @@ -0,0 +1,46 @@ +From 4dc574faf235f624d77472e459fb6a71fcb506e5 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 23 Jun 2015 15:04:29 +0200 +Subject: [PATCH 226/326] spi: rspi: Make qspi_set_send_trigger() return + "unsigned int" + +qspi_set_send_trigger() returns an unsigned value, so make it return +"unsigned int". +Update the loop variables qspi_trigger_transfer_out_int() to match the +above. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit cb76b1ca9174aa29d4c7c0f4aef113be203b600c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/spi/spi-rspi.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c +index d780deb45c3d..5bdacf752ae3 100644 +--- a/drivers/spi/spi-rspi.c ++++ b/drivers/spi/spi-rspi.c +@@ -383,7 +383,8 @@ static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg) + rspi_write8(rspi, data, reg); + } + +-static int qspi_set_send_trigger(struct rspi_data *rspi, unsigned int len) ++static unsigned int qspi_set_send_trigger(struct rspi_data *rspi, ++ unsigned int len) + { + unsigned int n; + +@@ -727,7 +728,8 @@ static int rspi_rz_transfer_one(struct spi_master *master, + static int qspi_trigger_transfer_out_int(struct rspi_data *rspi, const u8 *tx, + u8 *rx, unsigned int len) + { +- int i, n, ret; ++ unsigned int i, n; ++ int ret; + + while (len > 0) { + n = qspi_set_send_trigger(rspi, len); +-- +2.6.2 + diff --git a/patches.renesas/0227-ata-sata_rcar-Remove-obsolete-sata-r8a779-platform_d.patch b/patches.renesas/0227-ata-sata_rcar-Remove-obsolete-sata-r8a779-platform_d.patch new file mode 100644 index 00000000000000..f1d5943d3c5b20 --- /dev/null +++ b/patches.renesas/0227-ata-sata_rcar-Remove-obsolete-sata-r8a779-platform_d.patch @@ -0,0 +1,39 @@ +From a4eaac03d13315d2eed8505e93fd9b2605e3edc3 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 23 Jun 2015 14:55:13 +0200 +Subject: [PATCH 227/326] ata: sata_rcar: Remove obsolete sata-r8a779* + platform_device_id entries + +Since commit a483dcbfa21f919c ("ARM: shmobile: lager: Remove legacy +board support"), R-Car Gen2 SoCs are only supported in generic DT-only +ARM multi-platform builds. The driver doesn't need to match platform +devices by name anymore, hence remove the corresponding +platform_device_id entry. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Tejun Heo <tj@kernel.org> +(cherry picked from commit 5dbc247c2a11f6b9febb854a55be5ae6be720df6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/ata/sata_rcar.c | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c +index d49a5193b7de..8804127b108c 100644 +--- a/drivers/ata/sata_rcar.c ++++ b/drivers/ata/sata_rcar.c +@@ -861,10 +861,6 @@ MODULE_DEVICE_TABLE(of, sata_rcar_match); + static const struct platform_device_id sata_rcar_id_table[] = { + { "sata_rcar", RCAR_GEN1_SATA }, /* Deprecated by "sata-r8a7779" */ + { "sata-r8a7779", RCAR_GEN1_SATA }, +- { "sata-r8a7790", RCAR_GEN2_SATA }, +- { "sata-r8a7790-es1", RCAR_R8A7790_ES1_SATA }, +- { "sata-r8a7791", RCAR_GEN2_SATA }, +- { "sata-r8a7793", RCAR_GEN2_SATA }, + { }, + }; + MODULE_DEVICE_TABLE(platform, sata_rcar_id_table); +-- +2.6.2 + diff --git a/patches.renesas/0228-clockevents-drivers-sh_cmt-Remove-obsolete-sh-cmt-32.patch b/patches.renesas/0228-clockevents-drivers-sh_cmt-Remove-obsolete-sh-cmt-32.patch new file mode 100644 index 00000000000000..9067ff22156922 --- /dev/null +++ b/patches.renesas/0228-clockevents-drivers-sh_cmt-Remove-obsolete-sh-cmt-32.patch @@ -0,0 +1,35 @@ +From bac0249b3c86b4824c67186aff5daef5b41ab7b6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 23 Jun 2015 14:56:28 +0200 +Subject: [PATCH 228/326] clockevents/drivers/sh_cmt: Remove obsolete + sh-cmt-32-fast platform_device_id entry + +Since commit 59b89af1d5551c12 ("ARM: shmobile: sh7372: Remove Legacy C +SoC code"), there are no more users left of the "sh-cmt-32-fast" +platform device name. Hence remove the corresponding platform_device_id +entry from the driver. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 59252d187763ef3675fba1623be6996761fc2400) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clocksource/sh_cmt.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c +index b8ff3c64cc45..0aa6293f6317 100644 +--- a/drivers/clocksource/sh_cmt.c ++++ b/drivers/clocksource/sh_cmt.c +@@ -929,7 +929,6 @@ static int sh_cmt_map_memory(struct sh_cmt_device *cmt) + static const struct platform_device_id sh_cmt_id_table[] = { + { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, + { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, +- { "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] }, + { "sh-cmt-48", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT] }, + { "sh-cmt-48-gen2", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT_GEN2] }, + { } +-- +2.6.2 + diff --git a/patches.renesas/0229-clockevents-drivers-sh_cmt-Remove-obsolete-sh-cmt-48.patch b/patches.renesas/0229-clockevents-drivers-sh_cmt-Remove-obsolete-sh-cmt-48.patch new file mode 100644 index 00000000000000..f478b201a6c552 --- /dev/null +++ b/patches.renesas/0229-clockevents-drivers-sh_cmt-Remove-obsolete-sh-cmt-48.patch @@ -0,0 +1,36 @@ +From fe008d73112202c75ecd57076a5e9d395fde566a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 23 Jun 2015 14:56:29 +0200 +Subject: [PATCH 229/326] clockevents/drivers/sh_cmt: Remove obsolete + sh-cmt-48-gen2 platform_device_id entry + +Since commit 914d7d148411997c ("ARM: shmobile: r8a73a4: Remove legacy +code"), all former users of the "sh-cmt-48-gen2" platform device name +are only supported in generic DT-only ARM multi-platform builds. The +driver doesn't need to match platform devices by name anymore, hence +remove the corresponding platform_device_id entry. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0fae62eafec3c033d49160344228a4fa7d6303bc) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clocksource/sh_cmt.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c +index 0aa6293f6317..d56d4e0e3fb3 100644 +--- a/drivers/clocksource/sh_cmt.c ++++ b/drivers/clocksource/sh_cmt.c +@@ -930,7 +930,6 @@ static const struct platform_device_id sh_cmt_id_table[] = { + { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, + { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, + { "sh-cmt-48", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT] }, +- { "sh-cmt-48-gen2", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT_GEN2] }, + { } + }; + MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); +-- +2.6.2 + diff --git a/patches.renesas/0230-sh-irq-Use-irq-accessor-functions-instead-of-open-co.patch b/patches.renesas/0230-sh-irq-Use-irq-accessor-functions-instead-of-open-co.patch new file mode 100644 index 00000000000000..1865143de205c8 --- /dev/null +++ b/patches.renesas/0230-sh-irq-Use-irq-accessor-functions-instead-of-open-co.patch @@ -0,0 +1,55 @@ +From d4433926560b9259ed00eb82693f0b23bbb83ad2 Mon Sep 17 00:00:00 2001 +From: Jiang Liu <jiang.liu@linux.intel.com> +Date: Mon, 13 Jul 2015 20:51:22 +0000 +Subject: [PATCH 230/326] sh/irq: Use irq accessor functions instead of open + coded access + +This is a preparatory patch for refactoring the internals if irq_data. + +Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> +Cc: Simon Horman <horms@verge.net.au> +Cc: Magnus Damm <magnus.damm@gmail.com> +Link: http://lkml.kernel.org/r/20150713151626.616384365@linutronix.de +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +Signed-off-by: Ingo Molnar <mingo@kernel.org> +(cherry picked from commit d0abe2f3a9a541ded2e30ef7275f057fb7f0335a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/sh/intc/virq.c | 12 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) + +diff --git a/drivers/sh/intc/virq.c b/drivers/sh/intc/virq.c +index f30ac9354ff2..bc0601cf0f8f 100644 +--- a/drivers/sh/intc/virq.c ++++ b/drivers/sh/intc/virq.c +@@ -83,12 +83,11 @@ EXPORT_SYMBOL_GPL(intc_irq_lookup); + + static int add_virq_to_pirq(unsigned int irq, unsigned int virq) + { +- struct intc_virq_list **last, *entry; +- struct irq_data *data = irq_get_irq_data(irq); ++ struct intc_virq_list *entry; ++ struct intc_virq_list **last = NULL; + + /* scan for duplicates */ +- last = (struct intc_virq_list **)&data->handler_data; +- for_each_virq(entry, data->handler_data) { ++ for_each_virq(entry, irq_get_handler_data(irq)) { + if (entry->irq == virq) + return 0; + last = &entry->next; +@@ -102,7 +101,10 @@ static int add_virq_to_pirq(unsigned int irq, unsigned int virq) + + entry->irq = virq; + +- *last = entry; ++ if (last) ++ *last = entry; ++ else ++ irq_set_handler_data(irq, entry); + + return 0; + } +-- +2.6.2 + diff --git a/patches.renesas/0231-sh-intc-Use-irq_desc_get_xxx-to-avoid-redundant-look.patch b/patches.renesas/0231-sh-intc-Use-irq_desc_get_xxx-to-avoid-redundant-look.patch new file mode 100644 index 00000000000000..2781b67d1d71fc --- /dev/null +++ b/patches.renesas/0231-sh-intc-Use-irq_desc_get_xxx-to-avoid-redundant-look.patch @@ -0,0 +1,116 @@ +From 85a5c449cc90a0a04354bef7023097696ea9a909 Mon Sep 17 00:00:00 2001 +From: Jiang Liu <jiang.liu@linux.intel.com> +Date: Mon, 13 Jul 2015 20:51:25 +0000 +Subject: [PATCH 231/326] sh/intc: Use irq_desc_get_xxx() to avoid redundant + lookup of irq_desc + +Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we +already have a pointer to corresponding irq_desc. + +Also replace generic_handle_irq with generic_handle_irq_desc() to avoid +looking up irq_desc again. + +Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> +Cc: Simon Horman <horms@verge.net.au> +Cc: Magnus Damm <magnus.damm@gmail.com> +Link: http://lkml.kernel.org/r/20150713151626.792845830@linutronix.de +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +Signed-off-by: Ingo Molnar <mingo@kernel.org> +(cherry picked from commit 8228a048961a93e871779c658eaa801f747e6c1d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/sh/boards/mach-se/7343/irq.c | 2 +- + arch/sh/boards/mach-se/7722/irq.c | 2 +- + arch/sh/boards/mach-x3proto/gpio.c | 2 +- + drivers/sh/intc/core.c | 2 +- + drivers/sh/intc/virq.c | 14 ++++++++------ + 5 files changed, 12 insertions(+), 10 deletions(-) + +diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c +index 1087dba9b015..6f97a8f0d0d6 100644 +--- a/arch/sh/boards/mach-se/7343/irq.c ++++ b/arch/sh/boards/mach-se/7343/irq.c +@@ -31,7 +31,7 @@ struct irq_domain *se7343_irq_domain; + + static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc) + { +- struct irq_data *data = irq_get_irq_data(irq); ++ struct irq_data *data = irq_desc_get_irq_data(desc); + struct irq_chip *chip = irq_data_get_irq_chip(data); + unsigned long mask; + int bit; +diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c +index 00e699232621..60aebd14ccf8 100644 +--- a/arch/sh/boards/mach-se/7722/irq.c ++++ b/arch/sh/boards/mach-se/7722/irq.c +@@ -30,7 +30,7 @@ struct irq_domain *se7722_irq_domain; + + static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc) + { +- struct irq_data *data = irq_get_irq_data(irq); ++ struct irq_data *data = irq_desc_get_irq_data(desc); + struct irq_chip *chip = irq_data_get_irq_chip(data); + unsigned long mask; + int bit; +diff --git a/arch/sh/boards/mach-x3proto/gpio.c b/arch/sh/boards/mach-x3proto/gpio.c +index f035a7ac6456..24555c364d5b 100644 +--- a/arch/sh/boards/mach-x3proto/gpio.c ++++ b/arch/sh/boards/mach-x3proto/gpio.c +@@ -62,7 +62,7 @@ static int x3proto_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) + + static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) + { +- struct irq_data *data = irq_get_irq_data(irq); ++ struct irq_data *data = irq_desc_get_irq_data(desc); + struct irq_chip *chip = irq_data_get_irq_chip(data); + unsigned long mask; + int pin; +diff --git a/drivers/sh/intc/core.c b/drivers/sh/intc/core.c +index 81f22980b2de..6dc0361aeeeb 100644 +--- a/drivers/sh/intc/core.c ++++ b/drivers/sh/intc/core.c +@@ -67,7 +67,7 @@ void intc_set_prio_level(unsigned int irq, unsigned int level) + + static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc) + { +- generic_handle_irq((unsigned int)irq_get_handler_data(irq)); ++ generic_handle_irq((unsigned int)irq_desc_get_handler_data(desc)); + } + + static void __init intc_register_irq(struct intc_desc *desc, +diff --git a/drivers/sh/intc/virq.c b/drivers/sh/intc/virq.c +index bc0601cf0f8f..bb7e745d4266 100644 +--- a/drivers/sh/intc/virq.c ++++ b/drivers/sh/intc/virq.c +@@ -111,7 +111,7 @@ static int add_virq_to_pirq(unsigned int irq, unsigned int virq) + + static void intc_virq_handler(unsigned int irq, struct irq_desc *desc) + { +- struct irq_data *data = irq_get_irq_data(irq); ++ struct irq_data *data = irq_desc_get_irq_data(desc); + struct irq_chip *chip = irq_data_get_irq_chip(data); + struct intc_virq_list *entry, *vlist = irq_data_get_irq_handler_data(data); + struct intc_desc_int *d = get_intc_desc(irq); +@@ -120,12 +120,14 @@ static void intc_virq_handler(unsigned int irq, struct irq_desc *desc) + + for_each_virq(entry, vlist) { + unsigned long addr, handle; ++ struct irq_desc *vdesc = irq_to_desc(entry->irq); + +- handle = (unsigned long)irq_get_handler_data(entry->irq); +- addr = INTC_REG(d, _INTC_ADDR_E(handle), 0); +- +- if (intc_reg_fns[_INTC_FN(handle)](addr, handle, 0)) +- generic_handle_irq(entry->irq); ++ if (vdesc) { ++ handle = (unsigned long)irq_desc_get_handler_data(vdesc); ++ addr = INTC_REG(d, _INTC_ADDR_E(handle), 0); ++ if (intc_reg_fns[_INTC_FN(handle)](addr, handle, 0)) ++ generic_handle_irq_desc(entry->irq, vdesc); ++ } + } + + chip->irq_unmask(data); +-- +2.6.2 + diff --git a/patches.renesas/0232-sh_eth-propagate-platform_get_irq-error-upstream.patch b/patches.renesas/0232-sh_eth-propagate-platform_get_irq-error-upstream.patch new file mode 100644 index 00000000000000..0ad5126dc16a3c --- /dev/null +++ b/patches.renesas/0232-sh_eth-propagate-platform_get_irq-error-upstream.patch @@ -0,0 +1,37 @@ +From 193b9d726959dff8c8cffcacf69ed0c6ad2b4f92 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 28 Aug 2015 16:56:01 +0300 +Subject: [PATCH 232/326] sh_eth: propagate platform_get_irq() error upstream + +The driver overrides the error returned by platform_get_irq() with -ENODEV +which e.g. precludes the deferred probing from working. Propagate the real +error code to the driver core instead. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 7a468ac624c80bda76957d8cbc28024f4f68e316) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 7fb244f565b2..257ea713b4c1 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -3089,10 +3089,8 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + + ndev->dma = -1; + ret = platform_get_irq(pdev, 0); +- if (ret < 0) { +- ret = -ENODEV; ++ if (ret < 0) + goto out_release; +- } + ndev->irq = ret; + + SET_NETDEV_DEV(ndev, &pdev->dev); +-- +2.6.2 + diff --git a/patches.renesas/0233-mmc-sh_mmcif-Fix-suspend-process.patch b/patches.renesas/0233-mmc-sh_mmcif-Fix-suspend-process.patch new file mode 100644 index 00000000000000..04d65b1154a00f --- /dev/null +++ b/patches.renesas/0233-mmc-sh_mmcif-Fix-suspend-process.patch @@ -0,0 +1,33 @@ +From 32e9182e48324d08a7da5435c907d83009d77987 Mon Sep 17 00:00:00 2001 +From: Koji Matsuoka <koji.matsuoka.xm@renesas.com> +Date: Sun, 23 Aug 2015 21:58:08 +0900 +Subject: [PATCH 233/326] mmc: sh_mmcif: Fix suspend process + +The clock should be enable when SDHI registers are accessed. + +Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> +Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 5afc30fc666165c1c37c246e08b4282bc8c31d98) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mmcif.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c +index 7eff087cf515..f9f93bf5e8fe 100644 +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -1532,7 +1532,9 @@ static int sh_mmcif_suspend(struct device *dev) + { + struct sh_mmcif_host *host = dev_get_drvdata(dev); + ++ pm_runtime_get_sync(dev); + sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); ++ pm_runtime_put(dev); + + return 0; + } +-- +2.6.2 + diff --git a/patches.renesas/0234-mmc-tmio-Fix-timeout-value-for-command-request.patch b/patches.renesas/0234-mmc-tmio-Fix-timeout-value-for-command-request.patch new file mode 100644 index 00000000000000..568f625416e9df --- /dev/null +++ b/patches.renesas/0234-mmc-tmio-Fix-timeout-value-for-command-request.patch @@ -0,0 +1,54 @@ +From 6befad9e7d49b61a69cf921496211fcdbed39a24 Mon Sep 17 00:00:00 2001 +From: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Date: Mon, 20 Jul 2015 01:39:59 +0900 +Subject: [PATCH 234/326] mmc: tmio: Fix timeout value for command request + +Fix the problem which timeout occurs at the time of command request with +several cards. + +The timeout value was insufficient as a verification of several cards, +so it was changed 5 seconds from 2 seconds. + +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 0df9d2eae5e1092b07eaab6b989c2ff14115cab5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index dba7e1c19dd7..988e498467df 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -83,6 +83,8 @@ static int tmio_mmc_next_sg(struct tmio_mmc_host *host) + return --host->sg_len; + } + ++#define CMDREQ_TIMEOUT 5000 ++ + #ifdef CONFIG_MMC_DEBUG + + #define STATUS_TO_TEXT(a, status, i) \ +@@ -230,7 +232,7 @@ static void tmio_mmc_reset_work(struct work_struct *work) + */ + if (IS_ERR_OR_NULL(mrq) + || time_is_after_jiffies(host->last_req_ts + +- msecs_to_jiffies(2000))) { ++ msecs_to_jiffies(CMDREQ_TIMEOUT))) { + spin_unlock_irqrestore(&host->lock, flags); + return; + } +@@ -818,7 +820,7 @@ static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) + ret = tmio_mmc_start_command(host, mrq->cmd); + if (!ret) { + schedule_delayed_work(&host->delayed_reset_work, +- msecs_to_jiffies(2000)); ++ msecs_to_jiffies(CMDREQ_TIMEOUT)); + return; + } + +-- +2.6.2 + diff --git a/patches.renesas/0235-spi-sh-msiof-Remove-obsolete-spi_r8a779x_msiof-platf.patch b/patches.renesas/0235-spi-sh-msiof-Remove-obsolete-spi_r8a779x_msiof-platf.patch new file mode 100644 index 00000000000000..23ecf6bbb1075f --- /dev/null +++ b/patches.renesas/0235-spi-sh-msiof-Remove-obsolete-spi_r8a779x_msiof-platf.patch @@ -0,0 +1,35 @@ +From 433124ce4e3529152af35969cbfbe338462a16a4 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 23 Jun 2015 15:02:44 +0200 +Subject: [PATCH 235/326] spi: sh-msiof: Remove obsolete spi_r8a779x_msiof + platform_device_id entries + +Since commit a483dcbfa21f919c ("ARM: shmobile: lager: Remove legacy +board support"), R-Car Gen2 SoCs are only supported in generic DT-only +ARM multi-platform builds. The driver doesn't need to match platform +devices by name anymore, hence remove the corresponding +platform_device_id entry. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit f6d1b3e20a840a7201ae400a970f42cca96aa17b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/spi/spi-sh-msiof.c | 5 ----- + 1 file changed, 5 deletions(-) + +--- a/drivers/spi/spi-sh-msiof.c ++++ b/drivers/spi/spi-sh-msiof.c +@@ -1268,11 +1268,6 @@ static int sh_msiof_spi_remove(struct pl + + static struct platform_device_id spi_driver_ids[] = { + { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, +- { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data }, +- { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data }, +- { "spi_r8a7792_msiof", (kernel_ulong_t)&r8a779x_data }, +- { "spi_r8a7793_msiof", (kernel_ulong_t)&r8a779x_data }, +- { "spi_r8a7794_msiof", (kernel_ulong_t)&r8a779x_data }, + {}, + }; + MODULE_DEVICE_TABLE(platform, spi_driver_ids); diff --git a/patches.renesas/0237-pinctrl-sh-pfc-Remove-r8a73a4-platform_device_id-ent.patch b/patches.renesas/0237-pinctrl-sh-pfc-Remove-r8a73a4-platform_device_id-ent.patch new file mode 100644 index 00000000000000..8105d58dd89579 --- /dev/null +++ b/patches.renesas/0237-pinctrl-sh-pfc-Remove-r8a73a4-platform_device_id-ent.patch @@ -0,0 +1,39 @@ +From d99fe937bc4a3989ba03ba0430bef233dd52aad6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 28 Apr 2015 12:15:07 +0200 +Subject: [PATCH 237/326] pinctrl: sh-pfc: Remove r8a73a4 platform_device_id + entry + +As of commit 9d07d414d4c33d86 ("ARM: shmobile: r8a73a4: ape6evm: Remove +legacy platform"), r8a73a4 is only supported in generic DT-only ARM +multi-platform builds. The driver doesn't need to match platform +devices by name anymore, hence remove the corresponding +platform_device_id entry. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 592be8d3c1110ae12082399c39eef18ec15c0d1d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index 7b2c9495c383..287a3d048a5e 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -579,9 +579,6 @@ static int sh_pfc_remove(struct platform_device *pdev) + } + + static const struct platform_device_id sh_pfc_id_table[] = { +-#ifdef CONFIG_PINCTRL_PFC_R8A73A4 +- { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info }, +-#endif + #ifdef CONFIG_PINCTRL_PFC_R8A7740 + { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, + #endif +-- +2.6.2 + diff --git a/patches.renesas/0238-pinctrl-sh-pfc-r8a7740-Fix-typo-SCIFAB-in-comment.patch b/patches.renesas/0238-pinctrl-sh-pfc-r8a7740-Fix-typo-SCIFAB-in-comment.patch new file mode 100644 index 00000000000000..22aa6d488aa2e9 --- /dev/null +++ b/patches.renesas/0238-pinctrl-sh-pfc-r8a7740-Fix-typo-SCIFAB-in-comment.patch @@ -0,0 +1,33 @@ +From 417df6f5c589c0d3e8d770b30cf5dce7cff4fd8c Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 4 May 2015 16:40:46 +0200 +Subject: [PATCH 238/326] pinctrl: sh-pfc: r8a7740: Fix typo SCIFAB in comment + +The last serial port is called "SCIFB", not "SCIFAB". + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 992161965f60c4f19176026045f82749f30dafa2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +index b486e9d20cc2..d0bb1459783a 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +@@ -258,7 +258,7 @@ enum { + /* SCIFA7 */ + SCIFA7_TXD_MARK, SCIFA7_RXD_MARK, + +- /* SCIFAB */ ++ /* SCIFB */ + SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */ + SCIFB_RXD_PORT191_MARK, + SCIFB_TXD_PORT192_MARK, +-- +2.6.2 + diff --git a/patches.renesas/0239-pinctrl-sh-pfc-Add-r8a7793-support.patch b/patches.renesas/0239-pinctrl-sh-pfc-Add-r8a7793-support.patch new file mode 100644 index 00000000000000..8f62256a166d51 --- /dev/null +++ b/patches.renesas/0239-pinctrl-sh-pfc-Add-r8a7793-support.patch @@ -0,0 +1,90 @@ +From 767fc9fd1a1675f7621ed100705804993503c5af Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Tue, 12 May 2015 11:13:19 +0200 +Subject: [PATCH 239/326] pinctrl: sh-pfc: Add r8a7793 support + +Regarding pin control, r8a7791 and r8a7793 are identical, so it is +sufficient to add an sh_pfc_soc_info structure to enable r8a7793 support. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 19e1e98fbf68d398bab944244f883ae14535b196) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 6 ++++++ + drivers/pinctrl/sh-pfc/core.h | 1 + + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 23 +++++++++++++++++++++++ + 3 files changed, 30 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index 287a3d048a5e..96556362b28f 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -481,6 +481,12 @@ static const struct of_device_id sh_pfc_of_table[] = { + .data = &r8a7791_pinmux_info, + }, + #endif ++#ifdef CONFIG_PINCTRL_PFC_R8A7793 ++ { ++ .compatible = "renesas,pfc-r8a7793", ++ .data = &r8a7793_pinmux_info, ++ }, ++#endif + #ifdef CONFIG_PINCTRL_PFC_SH73A0 + { + .compatible = "renesas,pfc-sh73a0", +diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h +index 6dc8a6fc2746..b151b771e876 100644 +--- a/drivers/pinctrl/sh-pfc/core.h ++++ b/drivers/pinctrl/sh-pfc/core.h +@@ -71,6 +71,7 @@ extern const struct sh_pfc_soc_info r8a7778_pinmux_info; + extern const struct sh_pfc_soc_info r8a7779_pinmux_info; + extern const struct sh_pfc_soc_info r8a7790_pinmux_info; + extern const struct sh_pfc_soc_info r8a7791_pinmux_info; ++extern const struct sh_pfc_soc_info r8a7793_pinmux_info; + extern const struct sh_pfc_soc_info sh7203_pinmux_info; + extern const struct sh_pfc_soc_info sh7264_pinmux_info; + extern const struct sh_pfc_soc_info sh7269_pinmux_info; +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +index fdd2c8729791..cbf8ec3ae8ab 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -6181,6 +6181,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { }, + }; + ++#ifdef CONFIG_PINCTRL_PFC_R8A7791 + const struct sh_pfc_soc_info r8a7791_pinmux_info = { + .name = "r8a77910_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ +@@ -6199,3 +6200,25 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = { + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), + }; ++#endif ++ ++#ifdef CONFIG_PINCTRL_PFC_R8A7793 ++const struct sh_pfc_soc_info r8a7793_pinmux_info = { ++ .name = "r8a77930_pfc", ++ .unlock_reg = 0xe6060000, /* PMMR */ ++ ++ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, ++ ++ .pins = pinmux_pins, ++ .nr_pins = ARRAY_SIZE(pinmux_pins), ++ .groups = pinmux_groups, ++ .nr_groups = ARRAY_SIZE(pinmux_groups), ++ .functions = pinmux_functions, ++ .nr_functions = ARRAY_SIZE(pinmux_functions), ++ ++ .cfg_regs = pinmux_config_regs, ++ ++ .gpio_data = pinmux_data, ++ .gpio_data_size = ARRAY_SIZE(pinmux_data), ++}; ++#endif +-- +2.6.2 + diff --git a/patches.renesas/0240-pinctrl-sh-pfc-Enable-building-of-r8a7793-PFC-suppor.patch b/patches.renesas/0240-pinctrl-sh-pfc-Enable-building-of-r8a7793-PFC-suppor.patch new file mode 100644 index 00000000000000..463a0cbc249d3a --- /dev/null +++ b/patches.renesas/0240-pinctrl-sh-pfc-Enable-building-of-r8a7793-PFC-suppor.patch @@ -0,0 +1,48 @@ +From e0c6d4042510ebf8d525c0ac22d625bd487151fa Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Tue, 12 May 2015 11:13:20 +0200 +Subject: [PATCH 240/326] pinctrl: sh-pfc: Enable building of r8a7793 PFC + support + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit cb0ba73d09a0deb03b292c39b1c39e1d622e66df) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/Kconfig | 5 +++++ + drivers/pinctrl/sh-pfc/Makefile | 1 + + 2 files changed, 6 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig +index 8c4b3d391823..5d570fdf6065 100644 +--- a/drivers/pinctrl/sh-pfc/Kconfig ++++ b/drivers/pinctrl/sh-pfc/Kconfig +@@ -55,6 +55,11 @@ config PINCTRL_PFC_R8A7791 + depends on ARCH_R8A7791 + select PINCTRL_SH_PFC + ++config PINCTRL_PFC_R8A7793 ++ def_bool y ++ depends on ARCH_R8A7793 ++ select PINCTRL_SH_PFC ++ + config PINCTRL_PFC_SH7203 + def_bool y + depends on CPU_SUBTYPE_SH7203 +diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile +index f4074e166bcf..11eefcb71ec9 100644 +--- a/drivers/pinctrl/sh-pfc/Makefile ++++ b/drivers/pinctrl/sh-pfc/Makefile +@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o + obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o + obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o + obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o ++obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o + obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o + obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o + obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o +-- +2.6.2 + diff --git a/patches.renesas/0241-pinctrl-sh-pfc-Add-renesas-pfc-r8a7793-to-binding-do.patch b/patches.renesas/0241-pinctrl-sh-pfc-Add-renesas-pfc-r8a7793-to-binding-do.patch new file mode 100644 index 00000000000000..8481bc332b406f --- /dev/null +++ b/patches.renesas/0241-pinctrl-sh-pfc-Add-renesas-pfc-r8a7793-to-binding-do.patch @@ -0,0 +1,37 @@ +From 9b43dd3a23896dc1ab667372d4d8de7de9b05aba Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Tue, 12 May 2015 11:13:21 +0200 +Subject: [PATCH 241/326] pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding + documentation + +Also renames "R-Car M2" to "R-Car M2-W" to avoid confusion. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Cc: devicetree@vger.kernel.org +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 7e15a967a2d686bc959a268fd12c50e39d705416) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +index bfe72ec055e3..6bcf851b6779 100644 +--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +@@ -16,7 +16,8 @@ Required Properties: + - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. + - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. + - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. +- - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller. ++ - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. ++ - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. + - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. + + - reg: Base address and length of each memory resource used by the pin +-- +2.6.2 + diff --git a/patches.renesas/0242-pinctrl-sh-pfc-r8a73a4-Remove-obsolete-multi-platfor.patch b/patches.renesas/0242-pinctrl-sh-pfc-r8a73a4-Remove-obsolete-multi-platfor.patch new file mode 100644 index 00000000000000..626e21b47406ed --- /dev/null +++ b/patches.renesas/0242-pinctrl-sh-pfc-r8a73a4-Remove-obsolete-multi-platfor.patch @@ -0,0 +1,39 @@ +From e00ef28265b261e0aa1aabd9a4dde82004268b76 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 28 Apr 2015 12:15:06 +0200 +Subject: [PATCH 242/326] pinctrl: sh-pfc: r8a73a4: Remove obsolete + multi-platform check + +As of commit 9d07d414d4c33d86 ("ARM: shmobile: r8a73a4: ape6evm: Remove +legacy platform"), r8a73a4 is only supported in generic ARM +multi-platform builds. Hence CONFIG_ARCH_MULTIPLATFORM is always set, +and the check can be removed. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit e8e36d2f1873218a2fdaf0b7cd335b84e8be6112) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +index 280a56f97786..ba18d2e65e67 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +@@ -21,10 +21,6 @@ + #include <linux/kernel.h> + #include <linux/pinctrl/pinconf-generic.h> + +-#ifndef CONFIG_ARCH_MULTIPLATFORM +-#include <mach/irqs.h> +-#endif +- + #include "core.h" + #include "sh_pfc.h" + +-- +2.6.2 + diff --git a/patches.renesas/0243-pinctrl-sh-pfc-r8a7790-Add-PWM-pin-groups-and-functi.patch b/patches.renesas/0243-pinctrl-sh-pfc-r8a7790-Add-PWM-pin-groups-and-functi.patch new file mode 100644 index 00000000000000..84cc0c34cc4406 --- /dev/null +++ b/patches.renesas/0243-pinctrl-sh-pfc-r8a7790-Add-PWM-pin-groups-and-functi.patch @@ -0,0 +1,152 @@ +From 9414dc604a8eda379e5c0546a2c47a5e4771976e Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Thu, 14 May 2015 19:48:54 +0900 +Subject: [PATCH 243/326] pinctrl: sh-pfc: r8a7790: Add PWM pin groups and + functions + +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 5c89c15b748c011332d855d13f4159d3e06378d9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 101 +++++++++++++++++++++++++++++++++++ + 1 file changed, 101 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index 22a5470889f5..baab81ead9ff 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -2664,6 +2664,61 @@ static const unsigned int msiof3_tx_b_pins[] = { + static const unsigned int msiof3_tx_b_mux[] = { + MSIOF3_TXD_B_MARK, + }; ++/* - PWM -------------------------------------------------------------------- */ ++static const unsigned int pwm0_pins[] = { ++ RCAR_GP_PIN(5, 29), ++}; ++static const unsigned int pwm0_mux[] = { ++ PWM0_MARK, ++}; ++static const unsigned int pwm0_b_pins[] = { ++ RCAR_GP_PIN(4, 30), ++}; ++static const unsigned int pwm0_b_mux[] = { ++ PWM0_B_MARK, ++}; ++static const unsigned int pwm1_pins[] = { ++ RCAR_GP_PIN(5, 30), ++}; ++static const unsigned int pwm1_mux[] = { ++ PWM1_MARK, ++}; ++static const unsigned int pwm1_b_pins[] = { ++ RCAR_GP_PIN(4, 31), ++}; ++static const unsigned int pwm1_b_mux[] = { ++ PWM1_B_MARK, ++}; ++static const unsigned int pwm2_pins[] = { ++ RCAR_GP_PIN(5, 31), ++}; ++static const unsigned int pwm2_mux[] = { ++ PWM2_MARK, ++}; ++static const unsigned int pwm3_pins[] = { ++ RCAR_GP_PIN(0, 16), ++}; ++static const unsigned int pwm3_mux[] = { ++ PWM3_MARK, ++}; ++static const unsigned int pwm4_pins[] = { ++ RCAR_GP_PIN(0, 17), ++}; ++static const unsigned int pwm4_mux[] = { ++ PWM4_MARK, ++}; ++static const unsigned int pwm5_pins[] = { ++ RCAR_GP_PIN(0, 18), ++}; ++static const unsigned int pwm5_mux[] = { ++ PWM5_MARK, ++}; ++static const unsigned int pwm6_pins[] = { ++ RCAR_GP_PIN(0, 19), ++}; ++static const unsigned int pwm6_mux[] = { ++ PWM6_MARK, ++}; + /* - QSPI ------------------------------------------------------------------- */ + static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ +@@ -4008,6 +4063,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_rx_b), + SH_PFC_PIN_GROUP(msiof3_tx_b), ++ SH_PFC_PIN_GROUP(pwm0), ++ SH_PFC_PIN_GROUP(pwm0_b), ++ SH_PFC_PIN_GROUP(pwm1), ++ SH_PFC_PIN_GROUP(pwm1_b), ++ SH_PFC_PIN_GROUP(pwm2), ++ SH_PFC_PIN_GROUP(pwm3), ++ SH_PFC_PIN_GROUP(pwm4), ++ SH_PFC_PIN_GROUP(pwm5), ++ SH_PFC_PIN_GROUP(pwm6), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), +@@ -4364,6 +4428,36 @@ static const char * const msiof3_groups[] = { + "msiof3_tx_b", + }; + ++static const char * const pwm0_groups[] = { ++ "pwm0", ++ "pwm0_b", ++}; ++ ++static const char * const pwm1_groups[] = { ++ "pwm1", ++ "pwm1_b", ++}; ++ ++static const char * const pwm2_groups[] = { ++ "pwm2", ++}; ++ ++static const char * const pwm3_groups[] = { ++ "pwm3", ++}; ++ ++static const char * const pwm4_groups[] = { ++ "pwm4", ++}; ++ ++static const char * const pwm5_groups[] = { ++ "pwm5", ++}; ++ ++static const char * const pwm6_groups[] = { ++ "pwm6", ++}; ++ + static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", +@@ -4621,6 +4715,13 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), ++ SH_PFC_FUNCTION(pwm0), ++ SH_PFC_FUNCTION(pwm1), ++ SH_PFC_FUNCTION(pwm2), ++ SH_PFC_FUNCTION(pwm3), ++ SH_PFC_FUNCTION(pwm4), ++ SH_PFC_FUNCTION(pwm5), ++ SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), +-- +2.6.2 + diff --git a/patches.renesas/0244-pinctrl-sh-pfc-r8a7791-Add-PWM-pin-groups-and-functi.patch b/patches.renesas/0244-pinctrl-sh-pfc-r8a7791-Add-PWM-pin-groups-and-functi.patch new file mode 100644 index 00000000000000..a6a0265db19ac1 --- /dev/null +++ b/patches.renesas/0244-pinctrl-sh-pfc-r8a7791-Add-PWM-pin-groups-and-functi.patch @@ -0,0 +1,176 @@ +From 0afae3a50ab99253e917a673400f6738edb6e32d Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Mon, 18 May 2015 10:41:05 +0900 +Subject: [PATCH 244/326] pinctrl: sh-pfc: r8a7791: Add PWM pin groups and + functions + +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit f9784298e2b4a95be3bd7200075a2fdc61fd9f3b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 125 +++++++++++++++++++++++++++++++++++ + 1 file changed, 125 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +index cbf8ec3ae8ab..6e9ed6fb087c 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -2928,6 +2928,79 @@ static const unsigned int msiof2_tx_e_pins[] = { + static const unsigned int msiof2_tx_e_mux[] = { + MSIOF2_TXD_E_MARK, + }; ++/* - PWM -------------------------------------------------------------------- */ ++static const unsigned int pwm0_pins[] = { ++ RCAR_GP_PIN(6, 14), ++}; ++static const unsigned int pwm0_mux[] = { ++ PWM0_MARK, ++}; ++static const unsigned int pwm0_b_pins[] = { ++ RCAR_GP_PIN(5, 30), ++}; ++static const unsigned int pwm0_b_mux[] = { ++ PWM0_B_MARK, ++}; ++static const unsigned int pwm1_pins[] = { ++ RCAR_GP_PIN(1, 17), ++}; ++static const unsigned int pwm1_mux[] = { ++ PWM1_MARK, ++}; ++static const unsigned int pwm1_b_pins[] = { ++ RCAR_GP_PIN(6, 15), ++}; ++static const unsigned int pwm1_b_mux[] = { ++ PWM1_B_MARK, ++}; ++static const unsigned int pwm2_pins[] = { ++ RCAR_GP_PIN(1, 18), ++}; ++static const unsigned int pwm2_mux[] = { ++ PWM2_MARK, ++}; ++static const unsigned int pwm2_b_pins[] = { ++ RCAR_GP_PIN(0, 16), ++}; ++static const unsigned int pwm2_b_mux[] = { ++ PWM2_B_MARK, ++}; ++static const unsigned int pwm3_pins[] = { ++ RCAR_GP_PIN(1, 24), ++}; ++static const unsigned int pwm3_mux[] = { ++ PWM3_MARK, ++}; ++static const unsigned int pwm4_pins[] = { ++ RCAR_GP_PIN(3, 26), ++}; ++static const unsigned int pwm4_mux[] = { ++ PWM4_MARK, ++}; ++static const unsigned int pwm4_b_pins[] = { ++ RCAR_GP_PIN(3, 31), ++}; ++static const unsigned int pwm4_b_mux[] = { ++ PWM4_B_MARK, ++}; ++static const unsigned int pwm5_pins[] = { ++ RCAR_GP_PIN(7, 21), ++}; ++static const unsigned int pwm5_mux[] = { ++ PWM5_MARK, ++}; ++static const unsigned int pwm5_b_pins[] = { ++ RCAR_GP_PIN(7, 20), ++}; ++static const unsigned int pwm5_b_mux[] = { ++ PWM5_B_MARK, ++}; ++static const unsigned int pwm6_pins[] = { ++ RCAR_GP_PIN(7, 22), ++}; ++static const unsigned int pwm6_mux[] = { ++ PWM6_MARK, ++}; + /* - QSPI ------------------------------------------------------------------- */ + static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ +@@ -4348,6 +4421,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(msiof2_sync_e), + SH_PFC_PIN_GROUP(msiof2_rx_e), + SH_PFC_PIN_GROUP(msiof2_tx_e), ++ SH_PFC_PIN_GROUP(pwm0), ++ SH_PFC_PIN_GROUP(pwm0_b), ++ SH_PFC_PIN_GROUP(pwm1), ++ SH_PFC_PIN_GROUP(pwm1_b), ++ SH_PFC_PIN_GROUP(pwm2), ++ SH_PFC_PIN_GROUP(pwm2_b), ++ SH_PFC_PIN_GROUP(pwm3), ++ SH_PFC_PIN_GROUP(pwm4), ++ SH_PFC_PIN_GROUP(pwm4_b), ++ SH_PFC_PIN_GROUP(pwm5), ++ SH_PFC_PIN_GROUP(pwm5_b), ++ SH_PFC_PIN_GROUP(pwm6), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), +@@ -4745,6 +4830,39 @@ static const char * const msiof2_groups[] = { + "msiof2_tx_e", + }; + ++static const char * const pwm0_groups[] = { ++ "pwm0", ++ "pwm0_b", ++}; ++ ++static const char * const pwm1_groups[] = { ++ "pwm1", ++ "pwm1_b", ++}; ++ ++static const char * const pwm2_groups[] = { ++ "pwm2", ++ "pwm2_b", ++}; ++ ++static const char * const pwm3_groups[] = { ++ "pwm3", ++}; ++ ++static const char * const pwm4_groups[] = { ++ "pwm4", ++ "pwm4_b", ++}; ++ ++static const char * const pwm5_groups[] = { ++ "pwm5", ++ "pwm5_b", ++}; ++ ++static const char * const pwm6_groups[] = { ++ "pwm6", ++}; ++ + static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", +@@ -4989,6 +5107,13 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), ++ SH_PFC_FUNCTION(pwm0), ++ SH_PFC_FUNCTION(pwm1), ++ SH_PFC_FUNCTION(pwm2), ++ SH_PFC_FUNCTION(pwm3), ++ SH_PFC_FUNCTION(pwm4), ++ SH_PFC_FUNCTION(pwm5), ++ SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), +-- +2.6.2 + diff --git a/patches.renesas/0245-pinctrl-Spelling-s-reseved-reserved.patch b/patches.renesas/0245-pinctrl-Spelling-s-reseved-reserved.patch new file mode 100644 index 00000000000000..55aee1f5dd2892 --- /dev/null +++ b/patches.renesas/0245-pinctrl-Spelling-s-reseved-reserved.patch @@ -0,0 +1,169 @@ +From 0c448d5588d89d0b0dc3152c9cf672379a086599 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 21 May 2015 14:05:10 +0200 +Subject: [PATCH 245/326] pinctrl: Spelling s/reseved/reserved/ + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 5b441eba3ab928ad1a2e9478fae6aa1397048860) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/nomadik/pinctrl-ab8505.c | 2 +- + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 38 ++++++++++++++++---------------- + 2 files changed, 20 insertions(+), 20 deletions(-) + +diff --git a/drivers/pinctrl/nomadik/pinctrl-ab8505.c b/drivers/pinctrl/nomadik/pinctrl-ab8505.c +index bf0ef4ac376f..42c6e1f7886b 100644 +--- a/drivers/pinctrl/nomadik/pinctrl-ab8505.c ++++ b/drivers/pinctrl/nomadik/pinctrl-ab8505.c +@@ -286,7 +286,7 @@ alternate_functions ab8505_alternate_functions[AB8505_GPIO_MAX_NUMBER + 1] = { + ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9, bit 0 reserved */ + ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */ + ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 2 */ +- ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reseved */ ++ ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reserved */ + ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */ + ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(15, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 6 reserved */ +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +index 6e9ed6fb087c..3ddf23ec9f0b 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -6125,7 +6125,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, + 3, 2, 2, 2, 1, 2, 2, 2) { +- /* RESEVED [1] */ ++ /* RESERVED [1] */ + 0, 0, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, +@@ -6152,11 +6152,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, + FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, + 0, 0, 0, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_VI1 [2] */ + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_TMU [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, +@@ -6174,7 +6174,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, + FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, + 0, 0, 0, +- /* RESEVED [1] */ ++ /* RESERVED [1] */ + 0, 0, + /* SEL_SCIF [1] */ + FN_SEL_SCIF_0, FN_SEL_SCIF_1, +@@ -6184,13 +6184,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, +- /* RESEVED [1] */ ++ /* RESERVED [1] */ + 0, 0, + /* SEL_SCIFA2 [1] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + /* SEL_SCIF4 [2] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_ADG [1] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, +@@ -6200,7 +6200,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, 0, + /* SEL_SCIFA5 [2] */ + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, +- /* RESEVED [1] */ ++ /* RESERVED [1] */ + 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, +@@ -6210,7 +6210,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, + /* SEL_SIM [1] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, +- /* RESEVED [1] */ ++ /* RESERVED [1] */ + 0, 0, + /* SEL_SSI8 [1] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, } +@@ -6240,7 +6240,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SEL_MMC_0, FN_SEL_MMC_1, + /* SEL_SCIF5 [1] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_IIC2 [2] */ + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, +@@ -6250,11 +6250,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, +- /* RESEVED [1] */ ++ /* RESERVED [1] */ + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, +@@ -6268,7 +6268,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, + /* SEL_DIS [2] */ + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, +- /* RESEVED [1] */ ++ /* RESERVED [1] */ + 0, 0, + /* SEL_RAD [1] */ + FN_SEL_RAD_0, FN_SEL_RAD_1, +@@ -6280,15 +6280,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, + FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, + 0, 0, 0, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_SOF2 [3] */ + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, + FN_SEL_SOF2_3, FN_SEL_SOF2_4, + 0, 0, 0, +- /* RESEVED [1] */ ++ /* RESERVED [1] */ + 0, 0, + /* SEL_SSI1 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, +@@ -6296,11 +6296,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + /* SEL_SSP [2] */ + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, +- /* RESEVED [2] */ ++ /* RESERVED [2] */ + 0, 0, 0, 0, } + }, + { }, +-- +2.6.2 + diff --git a/patches.renesas/0246-pinctrl-sh-pfc-add-R8A7794-PFC-support.patch b/patches.renesas/0246-pinctrl-sh-pfc-add-R8A7794-PFC-support.patch new file mode 100644 index 00000000000000..aa1331713956db --- /dev/null +++ b/patches.renesas/0246-pinctrl-sh-pfc-add-R8A7794-PFC-support.patch @@ -0,0 +1,4133 @@ +From 68d94f21b84092bca9c33025fa0c0cc0cd751144 Mon Sep 17 00:00:00 2001 +From: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> +Date: Sat, 6 Jun 2015 01:34:48 +0300 +Subject: [PATCH 246/326] pinctrl: sh-pfc: add R8A7794 PFC support + +Add PFC support for the R8A7794 SoC including pin groups for some +on-chip devices such as ETH, I2C, INTC, MSIOF, QSPI, [H]SCIF... + +Sergei: squashed together several patches, fixed the MLB_CLK typo, +added IRQ4.. IRQ9 pin groups, fixed IRQn comments, added ETH B pin +group names, removed stray new line and fixed typos in the comments +in the pinmux_config_regs[] initializer, removed the platform device +ID, took into account limited number of signals in the GPIO1/5/6 +controllers, added reasonable and removed unreasonable +copyrights, modified the bindings document, renamed, added changelog. + +Changes in version 5: +- resolved rejects, refreshed the patch; +- added Laurent Pinchart's ACK. + +Changes in version 4: +- reused the PORT_GP_26() macro to #define PORT_GP_28(). + +Changes in version 3: +- removed the platform device ID; +- added PORT_GP_26() and PORT_GP_28() macros, used them for GPIO1/5/6 in the + CPU_ALL_PORT() macro. + +Changes in version 2: +- rebased the patch. + +Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 43c4436e2f1890a7b28dc0f0d901866cda99a08c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 + + drivers/pinctrl/sh-pfc/Kconfig | 5 + + drivers/pinctrl/sh-pfc/Makefile | 1 + + drivers/pinctrl/sh-pfc/core.c | 6 + + drivers/pinctrl/sh-pfc/core.h | 1 + + drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 4008 ++++++++++++++++++++ + 6 files changed, 4022 insertions(+) + create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7794.c + +diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +index 6bcf851b6779..51cee44fc140 100644 +--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +@@ -18,6 +18,7 @@ Required Properties: + - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. + - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. + - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. ++ - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. + - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. + + - reg: Base address and length of each memory resource used by the pin +diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig +index 5d570fdf6065..8e024c9c9115 100644 +--- a/drivers/pinctrl/sh-pfc/Kconfig ++++ b/drivers/pinctrl/sh-pfc/Kconfig +@@ -60,6 +60,11 @@ config PINCTRL_PFC_R8A7793 + depends on ARCH_R8A7793 + select PINCTRL_SH_PFC + ++config PINCTRL_PFC_R8A7794 ++ def_bool y ++ depends on ARCH_R8A7794 ++ select PINCTRL_SH_PFC ++ + config PINCTRL_PFC_SH7203 + def_bool y + depends on CPU_SUBTYPE_SH7203 +diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile +index 11eefcb71ec9..ea2a60ef122a 100644 +--- a/drivers/pinctrl/sh-pfc/Makefile ++++ b/drivers/pinctrl/sh-pfc/Makefile +@@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o + obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o + obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o + obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o ++obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o + obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o + obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o + obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index 96556362b28f..865d235612c5 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -487,6 +487,12 @@ static const struct of_device_id sh_pfc_of_table[] = { + .data = &r8a7793_pinmux_info, + }, + #endif ++#ifdef CONFIG_PINCTRL_PFC_R8A7794 ++ { ++ .compatible = "renesas,pfc-r8a7794", ++ .data = &r8a7794_pinmux_info, ++ }, ++#endif + #ifdef CONFIG_PINCTRL_PFC_SH73A0 + { + .compatible = "renesas,pfc-sh73a0", +diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h +index b151b771e876..4c3c37bf7161 100644 +--- a/drivers/pinctrl/sh-pfc/core.h ++++ b/drivers/pinctrl/sh-pfc/core.h +@@ -72,6 +72,7 @@ extern const struct sh_pfc_soc_info r8a7779_pinmux_info; + extern const struct sh_pfc_soc_info r8a7790_pinmux_info; + extern const struct sh_pfc_soc_info r8a7791_pinmux_info; + extern const struct sh_pfc_soc_info r8a7793_pinmux_info; ++extern const struct sh_pfc_soc_info r8a7794_pinmux_info; + extern const struct sh_pfc_soc_info sh7203_pinmux_info; + extern const struct sh_pfc_soc_info sh7264_pinmux_info; + extern const struct sh_pfc_soc_info sh7269_pinmux_info; +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +new file mode 100644 +index 000000000000..0e2686a2093c +--- /dev/null ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +@@ -0,0 +1,4008 @@ ++/* ++ * r8a7794 processor support - PFC hardware block. ++ * ++ * Copyright (C) 2014 Renesas Electronics Corporation ++ * Copyright (C) 2015 Renesas Solutions Corp. ++ * Copyright (C) 2015 Cogent Embedded, Inc., <source@cogentembedded.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/platform_data/gpio-rcar.h> ++ ++#include "core.h" ++#include "sh_pfc.h" ++ ++#define PORT_GP_26(bank, fn, sfx) \ ++ PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ ++ PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ ++ PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ ++ PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ ++ PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ ++ PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ ++ PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ ++ PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ ++ PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ ++ PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ ++ PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ ++ PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ ++ PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) ++ ++#define PORT_GP_28(bank, fn, sfx) \ ++ PORT_GP_26(bank, fn, sfx), \ ++ PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx) ++ ++#define CPU_ALL_PORT(fn, sfx) \ ++ PORT_GP_32(0, fn, sfx), \ ++ PORT_GP_26(1, fn, sfx), \ ++ PORT_GP_32(2, fn, sfx), \ ++ PORT_GP_32(3, fn, sfx), \ ++ PORT_GP_32(4, fn, sfx), \ ++ PORT_GP_28(5, fn, sfx), \ ++ PORT_GP_26(6, fn, sfx) ++ ++enum { ++ PINMUX_RESERVED = 0, ++ ++ PINMUX_DATA_BEGIN, ++ GP_ALL(DATA), ++ PINMUX_DATA_END, ++ ++ PINMUX_FUNCTION_BEGIN, ++ GP_ALL(FN), ++ ++ /* GPSR0 */ ++ FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28, ++ FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, ++ FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18, ++ FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27, ++ FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4, ++ FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14, ++ FN_IP2_17_16, ++ ++ /* GPSR1 */ ++ FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30, ++ FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10, ++ FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18, ++ FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31, ++ FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0, ++ ++ /* GPSR2 */ ++ FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12, ++ FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23, ++ FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2, ++ FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14, ++ FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24, ++ FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2, ++ FN_IP6_5_4, FN_IP6_7_6, ++ ++ /* GPSR3 */ ++ FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13, ++ FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20, ++ FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, ++ FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, ++ FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, ++ FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17, ++ FN_IP8_22_20, ++ ++ /* GPSR4 */ ++ FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3, ++ FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17, ++ FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0, ++ FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, ++ FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27, ++ FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8, ++ FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16, ++ ++ /* GPSR5 */ ++ FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, ++ FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13, ++ FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24, ++ FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9, ++ FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21, ++ FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, ++ ++ /* GPSR6 */ ++ FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2, ++ FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD, ++ FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0, ++ FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14, ++ FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20, ++ ++ /* IPSR0 */ ++ FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK, ++ FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1, ++ FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3, ++ FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD, ++ FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, ++ FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B, ++ FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4, ++ FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, ++ ++ /* IPSR1 */ ++ FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1, ++ FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX, ++ FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, ++ FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, ++ FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13, ++ FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD, ++ FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0, ++ FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK, ++ FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, ++ FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, ++ ++ /* IPSR2 */ ++ FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD, ++ FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10, ++ FN_MSIOF1_SCK, FN_IIC1_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, ++ FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2, ++ FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, ++ FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16, ++ FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C, ++ FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, ++ FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, ++ FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4, ++ FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1, ++ ++ /* IPSR3 */ ++ FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5, ++ FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3, ++ FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8, ++ FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N, ++ FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0, ++ FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, ++ FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, ++ FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N, ++ FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK, ++ FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, ++ FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B, ++ FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B, ++ FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N, ++ ++ /* IPSR4 */ ++ FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0, ++ FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0, ++ FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1, ++ FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19, ++ FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5, ++ FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, ++ FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8, ++ FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9, ++ FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10, ++ FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4, ++ FN_LCDOUT12, FN_CC50_STATE12, ++ ++ /* IPSR5 */ ++ FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14, ++ FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0, ++ FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C, ++ FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, ++ FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, ++ FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4, ++ FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6, ++ FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, ++ FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0, ++ FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, ++ FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, ++ ++ /* IPSR6 */ ++ FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, ++ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, ++ FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB, ++ FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0, ++ FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2, ++ FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4, ++ FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6, ++ FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB, ++ FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD, ++ FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N, ++ FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N, ++ FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, ++ FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK, ++ FN_ADIDATA, FN_AD_DI, ++ ++ /* IPSR7 */ ++ FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0, ++ FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, ++ FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3, ++ FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, ++ FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, ++ FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, ++ FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, ++ FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, ++ FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0, ++ FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B, ++ FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, ++ FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, ++ FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD, ++ ++ /* IPSR8 */ ++ FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC, ++ FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, ++ FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX, ++ FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B, ++ FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, ++ FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7, ++ FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B, ++ FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, ++ FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK, ++ FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, ++ FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD, ++ FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, ++ FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B, ++ FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, ++ FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, ++ ++ /* IPSR9 */ ++ FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B, ++ FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0, ++ FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC, ++ FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1, ++ FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B, ++ FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, ++ FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL, ++ FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, ++ FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B, ++ FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, ++ FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, ++ FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B, ++ FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, ++ FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, ++ ++ /* IPSR10 */ ++ FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0, ++ FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B, ++ FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL, ++ FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, ++ FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, ++ FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1, ++ FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4, ++ FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, ++ FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT, ++ FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C, ++ FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD, ++ FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B, ++ FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, ++ FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA, ++ FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9, ++ FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10, ++ ++ /* IPSR11 */ ++ FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, ++ FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, ++ FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B, ++ FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6, ++ FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, ++ FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, ++ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78, ++ FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78, ++ FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7, ++ FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N, ++ FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, ++ FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, ++ FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, ++ FN_ADICLK_B, FN_AD_CLK_B, ++ ++ /* IPSR12 */ ++ FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, ++ FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B, ++ FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3, ++ FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C, ++ FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4, ++ FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT, ++ FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B, ++ FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1, ++ FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D, ++ FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B, ++ FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, ++ FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1, ++ FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, ++ FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B, ++ ++ /* IPSR13 */ ++ FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ, ++ FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, ++ FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, ++ FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N, ++ FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, ++ FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9, ++ FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N, ++ FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, ++ FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, ++ FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, ++ FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC, ++ FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C, ++ FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, ++ FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B, ++ FN_FMIN_E, FN_RDS_DATA_D, ++ ++ /* MOD_SEL */ ++ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, ++ FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1, ++ FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1, ++ FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0, ++ FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1, ++ FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0, ++ FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, ++ FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1, ++ FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0, ++ FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4, ++ FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, ++ FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, ++ FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1, ++ FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1, ++ ++ /* MOD_SEL2 */ ++ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0, ++ FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0, ++ FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0, ++ FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0, ++ FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0, ++ FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0, ++ FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, ++ FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, ++ FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, ++ FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1, ++ FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, ++ FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1, ++ FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1, ++ FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ++ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1, ++ FN_SEL_RDS_2, FN_SEL_RDS_3, ++ ++ /* MOD_SEL3 */ ++ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, ++ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0, ++ FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, ++ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, ++ FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, ++ FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0, ++ FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0, ++ FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0, ++ FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0, ++ FN_SEL_SSI9_1, ++ PINMUX_FUNCTION_END, ++ ++ PINMUX_MARK_BEGIN, ++ A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK, ++ ++ USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, ++ ++ SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK, ++ SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK, ++ ++ SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK, ++ SD1_DATA2_MARK, SD1_DATA3_MARK, ++ ++ /* IPSR0 */ ++ SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK, ++ MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK, ++ SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK, ++ SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK, ++ MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK, ++ CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK, ++ CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK, ++ SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK, ++ SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK, ++ SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK, ++ ++ /* IPSR1 */ ++ D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK, ++ TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK, ++ D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK, ++ HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK, ++ D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK, ++ D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK, ++ D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK, ++ D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK, ++ IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK, ++ SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK, ++ A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK, ++ SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK, ++ ++ /* IPSR2 */ ++ A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK, ++ SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK, ++ A10_MARK, MSIOF1_SCK_MARK, IIC1_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK, ++ IIC1_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK, ++ A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK, ++ HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK, ++ HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK, ++ HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK, ++ TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, ++ CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK, ++ SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK, ++ MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK, ++ SPCLK_MARK, MOUT1_MARK, ++ ++ /* IPSR3 */ ++ A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK, ++ MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK, ++ ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK, ++ ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK, ++ VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK, ++ TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK, ++ PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK, ++ TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK, ++ SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK, ++ BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK, ++ SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK, ++ FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK, ++ SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK, ++ FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK, ++ PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK, ++ ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK, ++ ++ /* IPSR4 */ ++ EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK, ++ DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK, ++ CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, ++ I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK, ++ CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK, ++ DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK, ++ LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK, ++ CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK, ++ DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK, ++ CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, ++ I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK, ++ CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK, ++ DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK, ++ ++ /* IPSR5 */ ++ DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK, ++ LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK, ++ CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, ++ I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK, ++ LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK, ++ CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK, ++ DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK, ++ LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK, ++ CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK, ++ DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK, ++ QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK, ++ QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, ++ CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, ++ CC50_STATE27_MARK, ++ ++ /* IPSR6 */ ++ DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK, ++ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK, ++ DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK, ++ CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, ++ AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, ++ VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK, ++ AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, ++ VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK, ++ AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK, ++ I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK, ++ VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, ++ AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, ++ IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, ++ I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK, ++ VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK, ++ ADIDATA_MARK, AD_DI_MARK, ++ ++ /* IPSR7 */ ++ ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK, ++ AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK, ++ MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK, ++ AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, ++ CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK, ++ ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, ++ AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK, ++ MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK, ++ ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, ++ SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, ++ IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK, ++ VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK, ++ SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, ++ AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK, ++ SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, ++ DREQ0_N_MARK, SCIFB1_RXD_MARK, ++ ++ /* IPSR8 */ ++ ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK, ++ AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK, ++ I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK, ++ HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK, ++ AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK, ++ SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK, ++ HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK, ++ AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK, ++ HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK, ++ I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK, ++ AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK, ++ SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, ++ CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, ++ DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK, ++ I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK, ++ TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK, ++ I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK, ++ FMCLK_C_MARK, RDS_CLK_MARK, ++ ++ /* IPSR9 */ ++ MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK, ++ RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK, ++ MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK, ++ TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, ++ RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, ++ TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK, ++ MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK, ++ RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK, ++ I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK, ++ I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK, ++ PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK, ++ VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, ++ DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK, ++ CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, ++ DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK, ++ SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK, ++ CAN_TXCLK_MARK, CC50_STATE34_MARK, ++ ++ /* IPSR10 */ ++ SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK, ++ CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK, ++ DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK, ++ SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK, ++ USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK, ++ IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK, ++ CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK, ++ DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK, ++ CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, ++ DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK, ++ CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, ++ DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK, ++ RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, ++ DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK, ++ RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, ++ AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK, ++ SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK, ++ SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK, ++ ++ /* IPSR11 */ ++ SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK, ++ CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, ++ DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK, ++ SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK, ++ SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK, ++ DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK, ++ SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, ++ CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK, ++ DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK, ++ DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, ++ AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK, ++ MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK, ++ PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ++ ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, ++ PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK, ++ ++ /* IPSR12 */ ++ SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK, ++ AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK, ++ SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK, ++ SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK, ++ CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK, ++ IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK, ++ SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK, ++ SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK, ++ DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK, ++ IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK, ++ ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK, ++ VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK, ++ SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK, ++ ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, ++ VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK, ++ ++ /* IPSR13 */ ++ SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK, ++ SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK, ++ HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK, ++ ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK, ++ PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK, ++ ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, ++ VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK, ++ SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK, ++ ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, ++ VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK, ++ AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK, ++ TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK, ++ AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK, ++ TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK, ++ AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK, ++ TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, ++ PINMUX_MARK_END, ++}; ++ ++static const u16 pinmux_data[] = { ++ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ ++ ++ PINMUX_DATA(A2_MARK, FN_A2), ++ PINMUX_DATA(WE0_N_MARK, FN_WE0_N), ++ PINMUX_DATA(WE1_N_MARK, FN_WE1_N), ++ PINMUX_DATA(DACK0_MARK, FN_DACK0), ++ PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), ++ PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), ++ PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), ++ PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC), ++ PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK), ++ PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD), ++ PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0), ++ PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1), ++ PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2), ++ PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3), ++ PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD), ++ PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP), ++ PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK), ++ PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD), ++ PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0), ++ PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1), ++ PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2), ++ PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3), ++ ++ /* IPSR0 */ ++ PINMUX_IPSR_DATA(IP0_0, SD1_CD), ++ PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0), ++ PINMUX_IPSR_DATA(IP0_9_8, SD1_WP), ++ PINMUX_IPSR_DATA(IP0_9_8, IRQ7), ++ PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0), ++ PINMUX_IPSR_DATA(IP0_10, MMC_CLK), ++ PINMUX_IPSR_DATA(IP0_10, SD2_CLK), ++ PINMUX_IPSR_DATA(IP0_11, MMC_CMD), ++ PINMUX_IPSR_DATA(IP0_11, SD2_CMD), ++ PINMUX_IPSR_DATA(IP0_12, MMC_D0), ++ PINMUX_IPSR_DATA(IP0_12, SD2_DATA0), ++ PINMUX_IPSR_DATA(IP0_13, MMC_D1), ++ PINMUX_IPSR_DATA(IP0_13, SD2_DATA1), ++ PINMUX_IPSR_DATA(IP0_14, MMC_D2), ++ PINMUX_IPSR_DATA(IP0_14, SD2_DATA2), ++ PINMUX_IPSR_DATA(IP0_15, MMC_D3), ++ PINMUX_IPSR_DATA(IP0_15, SD2_DATA3), ++ PINMUX_IPSR_DATA(IP0_16, MMC_D4), ++ PINMUX_IPSR_DATA(IP0_16, SD2_CD), ++ PINMUX_IPSR_DATA(IP0_17, MMC_D5), ++ PINMUX_IPSR_DATA(IP0_17, SD2_WP), ++ PINMUX_IPSR_DATA(IP0_19_18, MMC_D6), ++ PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0), ++ PINMUX_IPSR_DATA(IP0_21_20, MMC_D7), ++ PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0), ++ PINMUX_IPSR_DATA(IP0_23_22, D0), ++ PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), ++ PINMUX_IPSR_DATA(IP0_23_22, IRQ4), ++ PINMUX_IPSR_DATA(IP0_24, D1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), ++ PINMUX_IPSR_DATA(IP0_25, D2), ++ PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), ++ PINMUX_IPSR_DATA(IP0_27_26, D3), ++ PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), ++ PINMUX_IPSR_DATA(IP0_29_28, D4), ++ PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), ++ PINMUX_IPSR_DATA(IP0_31_30, D5), ++ PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), ++ PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), ++ ++ /* IPSR1 */ ++ PINMUX_IPSR_DATA(IP1_1_0, D6), ++ PINMUX_IPSR_MODSEL_DATA(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1), ++ PINMUX_IPSR_MODSEL_DATA(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3), ++ PINMUX_IPSR_DATA(IP1_3_2, D7), ++ PINMUX_IPSR_DATA(IP1_3_2, IRQ3), ++ PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TCLK1, SEL_TMU_0), ++ PINMUX_IPSR_DATA(IP1_3_2, PWM6_B), ++ PINMUX_IPSR_DATA(IP1_5_4, D8), ++ PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX), ++ PINMUX_IPSR_MODSEL_DATA(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1), ++ PINMUX_IPSR_DATA(IP1_7_6, D9), ++ PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX), ++ PINMUX_IPSR_MODSEL_DATA(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1), ++ PINMUX_IPSR_DATA(IP1_10_8, D10), ++ PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK), ++ PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2), ++ PINMUX_IPSR_DATA(IP1_10_8, IRQ6), ++ PINMUX_IPSR_DATA(IP1_10_8, PWM5_C), ++ PINMUX_IPSR_DATA(IP1_12_11, D11), ++ PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N), ++ PINMUX_IPSR_MODSEL_DATA(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3), ++ PINMUX_IPSR_DATA(IP1_14_13, D12), ++ PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N), ++ PINMUX_IPSR_MODSEL_DATA(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), ++ PINMUX_IPSR_DATA(IP1_17_15, D13), ++ PINMUX_IPSR_MODSEL_DATA(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), ++ PINMUX_IPSR_DATA(IP1_17_15, TANS1), ++ PINMUX_IPSR_DATA(IP1_17_15, PWM2_C), ++ PINMUX_IPSR_MODSEL_DATA(IP1_17_15, TCLK2_B, SEL_TMU_1), ++ PINMUX_IPSR_DATA(IP1_19_18, D14), ++ PINMUX_IPSR_MODSEL_DATA(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1), ++ PINMUX_IPSR_DATA(IP1_21_20, D15), ++ PINMUX_IPSR_MODSEL_DATA(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1), ++ PINMUX_IPSR_DATA(IP1_23_22, A0), ++ PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK), ++ PINMUX_IPSR_DATA(IP1_23_22, PWM3_B), ++ PINMUX_IPSR_DATA(IP1_24, A1), ++ PINMUX_IPSR_DATA(IP1_24, SCIFB1_TXD), ++ PINMUX_IPSR_DATA(IP1_26, A3), ++ PINMUX_IPSR_DATA(IP1_26, SCIFB0_SCK), ++ PINMUX_IPSR_DATA(IP1_27, A4), ++ PINMUX_IPSR_DATA(IP1_27, SCIFB0_TXD), ++ PINMUX_IPSR_DATA(IP1_29_28, A5), ++ PINMUX_IPSR_DATA(IP1_29_28, SCIFB0_RXD), ++ PINMUX_IPSR_DATA(IP1_29_28, PWM4_B), ++ PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C), ++ PINMUX_IPSR_DATA(IP1_31_30, A6), ++ PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N), ++ PINMUX_IPSR_MODSEL_DATA(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1), ++ PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C), ++ ++ /* IPSR2 */ ++ PINMUX_IPSR_DATA(IP2_1_0, A7), ++ PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N), ++ PINMUX_IPSR_MODSEL_DATA(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1), ++ PINMUX_IPSR_DATA(IP2_3_2, A8), ++ PINMUX_IPSR_MODSEL_DATA(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1), ++ PINMUX_IPSR_DATA(IP2_5_4, A9), ++ PINMUX_IPSR_MODSEL_DATA(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1), ++ PINMUX_IPSR_DATA(IP2_7_6, A10), ++ PINMUX_IPSR_MODSEL_DATA(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1), ++ PINMUX_IPSR_DATA(IP2_9_8, A11), ++ PINMUX_IPSR_MODSEL_DATA(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1), ++ PINMUX_IPSR_DATA(IP2_11_10, A12), ++ PINMUX_IPSR_MODSEL_DATA(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1), ++ PINMUX_IPSR_DATA(IP2_13_12, A13), ++ PINMUX_IPSR_MODSEL_DATA(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1), ++ PINMUX_IPSR_DATA(IP2_15_14, A14), ++ PINMUX_IPSR_MODSEL_DATA(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP2_15_14, DREQ1_N, SEL_LBS_0), ++ PINMUX_IPSR_DATA(IP2_17_16, A15), ++ PINMUX_IPSR_MODSEL_DATA(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP2_17_16, DACK1, SEL_LBS_0), ++ PINMUX_IPSR_DATA(IP2_20_18, A16), ++ PINMUX_IPSR_MODSEL_DATA(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP2_20_18, SPEEDIN, SEL_RSP_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_20_18, VSP, SEL_SPDM_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_20_18, CAN_CLK_C, SEL_CAN_2), ++ PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B), ++ PINMUX_IPSR_DATA(IP2_23_21, A17), ++ PINMUX_IPSR_MODSEL_DATA(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), ++ PINMUX_IPSR_MODSEL_DATA(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1), ++ PINMUX_IPSR_DATA(IP2_26_24, A18), ++ PINMUX_IPSR_MODSEL_DATA(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), ++ PINMUX_IPSR_MODSEL_DATA(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1), ++ PINMUX_IPSR_DATA(IP2_29_27, A19), ++ PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), ++ PINMUX_IPSR_DATA(IP2_29_27, PWM4), ++ PINMUX_IPSR_DATA(IP2_29_27, TPUTO2), ++ PINMUX_IPSR_DATA(IP2_29_27, MOUT0), ++ PINMUX_IPSR_DATA(IP2_31_30, A20), ++ PINMUX_IPSR_DATA(IP2_31_30, SPCLK), ++ PINMUX_IPSR_DATA(IP2_29_27, MOUT1), ++ ++ /* IPSR3 */ ++ PINMUX_IPSR_DATA(IP3_1_0, A21), ++ PINMUX_IPSR_DATA(IP3_1_0, MOSI_IO0), ++ PINMUX_IPSR_DATA(IP3_1_0, MOUT2), ++ PINMUX_IPSR_DATA(IP3_3_2, A22), ++ PINMUX_IPSR_DATA(IP3_3_2, MISO_IO1), ++ PINMUX_IPSR_DATA(IP3_3_2, MOUT5), ++ PINMUX_IPSR_DATA(IP3_3_2, ATADIR1_N), ++ PINMUX_IPSR_DATA(IP3_5_4, A23), ++ PINMUX_IPSR_DATA(IP3_5_4, IO2), ++ PINMUX_IPSR_DATA(IP3_5_4, MOUT6), ++ PINMUX_IPSR_DATA(IP3_5_4, ATAWR1_N), ++ PINMUX_IPSR_DATA(IP3_7_6, A24), ++ PINMUX_IPSR_DATA(IP3_7_6, IO3), ++ PINMUX_IPSR_DATA(IP3_7_6, EX_WAIT2), ++ PINMUX_IPSR_DATA(IP3_9_8, A25), ++ PINMUX_IPSR_DATA(IP3_9_8, SSL), ++ PINMUX_IPSR_DATA(IP3_9_8, ATARD1_N), ++ PINMUX_IPSR_DATA(IP3_10, CS0_N), ++ PINMUX_IPSR_DATA(IP3_10, VI1_DATA8), ++ PINMUX_IPSR_DATA(IP3_11, CS1_N_A26), ++ PINMUX_IPSR_DATA(IP3_11, VI1_DATA9), ++ PINMUX_IPSR_DATA(IP3_12, EX_CS0_N), ++ PINMUX_IPSR_DATA(IP3_12, VI1_DATA10), ++ PINMUX_IPSR_DATA(IP3_14_13, EX_CS1_N), ++ PINMUX_IPSR_DATA(IP3_14_13, TPUTO3_B), ++ PINMUX_IPSR_DATA(IP3_14_13, SCIFB2_RXD), ++ PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11), ++ PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N), ++ PINMUX_IPSR_DATA(IP3_17_15, PWM0), ++ PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), ++ PINMUX_IPSR_MODSEL_DATA(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP3_17_15, RIF0_SYNC, SEL_DR0_0), ++ PINMUX_IPSR_DATA(IP3_17_15, TPUTO3), ++ PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD), ++ PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SDATA_B, SEL_FSN_1), ++ PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N), ++ PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), ++ PINMUX_IPSR_MODSEL_DATA(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP3_20_18, RIF0_CLK, SEL_DR0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP3_20_18, BPFCLK, SEL_DARC_0), ++ PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK), ++ PINMUX_IPSR_MODSEL_DATA(IP3_20_18, MDATA_B, SEL_FSN_1), ++ PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N), ++ PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), ++ PINMUX_IPSR_MODSEL_DATA(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP3_23_21, RIF0_D0, SEL_DR0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP3_23_21, FMCLK, SEL_DARC_0), ++ PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N), ++ PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCKZ_B, SEL_FSN_1), ++ PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N), ++ PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), ++ PINMUX_IPSR_MODSEL_DATA(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RIF0_D1, SEL_DR1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP3_26_24, FMIN, SEL_DARC_0), ++ PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N), ++ PINMUX_IPSR_MODSEL_DATA(IP3_26_24, STM_N_B, SEL_FSN_1), ++ PINMUX_IPSR_DATA(IP3_29_27, BS_N), ++ PINMUX_IPSR_DATA(IP3_29_27, DRACK0), ++ PINMUX_IPSR_DATA(IP3_29_27, PWM1_C), ++ PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C), ++ PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N), ++ PINMUX_IPSR_MODSEL_DATA(IP3_29_27, MTS_N_B, SEL_FSN_1), ++ PINMUX_IPSR_DATA(IP3_30, RD_N), ++ PINMUX_IPSR_DATA(IP3_30, ATACS11_N), ++ PINMUX_IPSR_DATA(IP3_31, RD_WR_N), ++ PINMUX_IPSR_DATA(IP3_31, ATAG1_N), ++ ++ /* IPSR4 */ ++ PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0), ++ PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_B, SEL_CAN_1), ++ PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), ++ PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0), ++ PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0), ++ PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16), ++ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), ++ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), ++ PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0), ++ PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1), ++ PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17), ++ PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), ++ PINMUX_IPSR_MODSEL_DATA(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), ++ PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1), ++ PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2), ++ PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18), ++ PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE2), ++ PINMUX_IPSR_DATA(IP4_11_10, DU0_DR3), ++ PINMUX_IPSR_DATA(IP4_11_10, LCDOUT19), ++ PINMUX_IPSR_DATA(IP4_11_10, CC50_STATE3), ++ PINMUX_IPSR_DATA(IP4_13_12, DU0_DR4), ++ PINMUX_IPSR_DATA(IP4_13_12, LCDOUT20), ++ PINMUX_IPSR_DATA(IP4_13_12, CC50_STATE4), ++ PINMUX_IPSR_DATA(IP4_15_14, DU0_DR5), ++ PINMUX_IPSR_DATA(IP4_15_14, LCDOUT21), ++ PINMUX_IPSR_DATA(IP4_15_14, CC50_STATE5), ++ PINMUX_IPSR_DATA(IP4_17_16, DU0_DR6), ++ PINMUX_IPSR_DATA(IP4_17_16, LCDOUT22), ++ PINMUX_IPSR_DATA(IP4_17_16, CC50_STATE6), ++ PINMUX_IPSR_DATA(IP4_19_18, DU0_DR7), ++ PINMUX_IPSR_DATA(IP4_19_18, LCDOUT23), ++ PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7), ++ PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0), ++ PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8), ++ PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), ++ PINMUX_IPSR_MODSEL_DATA(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), ++ PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8), ++ PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1), ++ PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9), ++ PINMUX_IPSR_MODSEL_DATA(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), ++ PINMUX_IPSR_MODSEL_DATA(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), ++ PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9), ++ PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2), ++ PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10), ++ PINMUX_IPSR_DATA(IP4_27_26, CC50_STATE10), ++ PINMUX_IPSR_DATA(IP4_29_28, DU0_DG3), ++ PINMUX_IPSR_DATA(IP4_29_28, LCDOUT11), ++ PINMUX_IPSR_DATA(IP4_29_28, CC50_STATE11), ++ PINMUX_IPSR_DATA(IP4_31_30, DU0_DG4), ++ PINMUX_IPSR_DATA(IP4_31_30, LCDOUT12), ++ PINMUX_IPSR_DATA(IP4_31_30, CC50_STATE12), ++ ++ /* IPSR5 */ ++ PINMUX_IPSR_DATA(IP5_1_0, DU0_DG5), ++ PINMUX_IPSR_DATA(IP5_1_0, LCDOUT13), ++ PINMUX_IPSR_DATA(IP5_1_0, CC50_STATE13), ++ PINMUX_IPSR_DATA(IP5_3_2, DU0_DG6), ++ PINMUX_IPSR_DATA(IP5_3_2, LCDOUT14), ++ PINMUX_IPSR_DATA(IP5_3_2, CC50_STATE14), ++ PINMUX_IPSR_DATA(IP5_5_4, DU0_DG7), ++ PINMUX_IPSR_DATA(IP5_5_4, LCDOUT15), ++ PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15), ++ PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0), ++ PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0), ++ PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), ++ PINMUX_IPSR_MODSEL_DATA(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), ++ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), ++ PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16), ++ PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1), ++ PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1), ++ PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), ++ PINMUX_IPSR_MODSEL_DATA(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), ++ PINMUX_IPSR_MODSEL_DATA(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), ++ PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17), ++ PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2), ++ PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2), ++ PINMUX_IPSR_DATA(IP5_13_12, CC50_STATE18), ++ PINMUX_IPSR_DATA(IP5_15_14, DU0_DB3), ++ PINMUX_IPSR_DATA(IP5_15_14, LCDOUT3), ++ PINMUX_IPSR_DATA(IP5_15_14, CC50_STATE19), ++ PINMUX_IPSR_DATA(IP5_17_16, DU0_DB4), ++ PINMUX_IPSR_DATA(IP5_17_16, LCDOUT4), ++ PINMUX_IPSR_DATA(IP5_17_16, CC50_STATE20), ++ PINMUX_IPSR_DATA(IP5_19_18, DU0_DB5), ++ PINMUX_IPSR_DATA(IP5_19_18, LCDOUT5), ++ PINMUX_IPSR_DATA(IP5_19_18, CC50_STATE21), ++ PINMUX_IPSR_DATA(IP5_21_20, DU0_DB6), ++ PINMUX_IPSR_DATA(IP5_21_20, LCDOUT6), ++ PINMUX_IPSR_DATA(IP5_21_20, CC50_STATE22), ++ PINMUX_IPSR_DATA(IP5_23_22, DU0_DB7), ++ PINMUX_IPSR_DATA(IP5_23_22, LCDOUT7), ++ PINMUX_IPSR_DATA(IP5_23_22, CC50_STATE23), ++ PINMUX_IPSR_DATA(IP5_25_24, DU0_DOTCLKIN), ++ PINMUX_IPSR_DATA(IP5_25_24, QSTVA_QVS), ++ PINMUX_IPSR_DATA(IP5_25_24, CC50_STATE24), ++ PINMUX_IPSR_DATA(IP5_27_26, DU0_DOTCLKOUT0), ++ PINMUX_IPSR_DATA(IP5_27_26, QCLK), ++ PINMUX_IPSR_DATA(IP5_27_26, CC50_STATE25), ++ PINMUX_IPSR_DATA(IP5_29_28, DU0_DOTCLKOUT1), ++ PINMUX_IPSR_DATA(IP5_29_28, QSTVB_QVE), ++ PINMUX_IPSR_DATA(IP5_29_28, CC50_STATE26), ++ PINMUX_IPSR_DATA(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC), ++ PINMUX_IPSR_DATA(IP5_31_30, QSTH_QHS), ++ PINMUX_IPSR_DATA(IP5_31_30, CC50_STATE27), ++ ++ /* IPSR6 */ ++ PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), ++ PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE), ++ PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28), ++ PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), ++ PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE), ++ PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29), ++ PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP), ++ PINMUX_IPSR_DATA(IP6_5_4, QPOLA), ++ PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30), ++ PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE), ++ PINMUX_IPSR_DATA(IP6_7_6, QPOLB), ++ PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31), ++ PINMUX_IPSR_DATA(IP6_8, VI0_CLK), ++ PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK), ++ PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0), ++ PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV), ++ PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1), ++ PINMUX_IPSR_DATA(IP6_10, AVB_RXD0), ++ PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2), ++ PINMUX_IPSR_DATA(IP6_11, AVB_RXD1), ++ PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3), ++ PINMUX_IPSR_DATA(IP6_12, AVB_RXD2), ++ PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4), ++ PINMUX_IPSR_DATA(IP6_13, AVB_RXD3), ++ PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5), ++ PINMUX_IPSR_DATA(IP6_14, AVB_RXD4), ++ PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6), ++ PINMUX_IPSR_DATA(IP6_15, AVB_RXD5), ++ PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7), ++ PINMUX_IPSR_DATA(IP6_16, AVB_RXD6), ++ PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB), ++ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0), ++ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), ++ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2), ++ PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7), ++ PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD), ++ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0), ++ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), ++ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2), ++ PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER), ++ PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N), ++ PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), ++ PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2), ++ PINMUX_IPSR_DATA(IP6_25_23, AVB_COL), ++ PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N), ++ PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), ++ PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), ++ PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN), ++ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0), ++ PINMUX_IPSR_DATA(IP6_31_29, VI0_G0), ++ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), ++ PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK), ++ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0), ++ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0), ++ ++ /* IPSR7 */ ++ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), ++ PINMUX_IPSR_DATA(IP7_2_0, VI0_G1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), ++ PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0), ++ PINMUX_IPSR_DATA(IP7_5_3, VI0_G2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), ++ PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0), ++ PINMUX_IPSR_DATA(IP7_8_6, VI0_G3), ++ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), ++ PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0), ++ PINMUX_IPSR_DATA(IP7_11_9, VI0_G4), ++ PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), ++ PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3), ++ PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0), ++ PINMUX_IPSR_DATA(IP7_14_12, VI0_G5), ++ PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), ++ PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4), ++ PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0), ++ PINMUX_IPSR_DATA(IP7_17_15, VI0_G6), ++ PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), ++ PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5), ++ PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0), ++ PINMUX_IPSR_DATA(IP7_20_18, VI0_G7), ++ PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), ++ PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6), ++ PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0), ++ PINMUX_IPSR_DATA(IP7_23_21, VI0_R0), ++ PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), ++ PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7), ++ PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0), ++ PINMUX_IPSR_DATA(IP7_26_24, VI0_R1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), ++ PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER), ++ PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0), ++ PINMUX_IPSR_DATA(IP7_29_27, VI0_R2), ++ PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), ++ PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), ++ PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK), ++ PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), ++ PINMUX_IPSR_DATA(IP7_31, DREQ0_N), ++ PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD), ++ ++ /* IPSR8 */ ++ PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0), ++ PINMUX_IPSR_DATA(IP8_2_0, VI0_R3), ++ PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), ++ PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), ++ PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC), ++ PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), ++ PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), ++ PINMUX_IPSR_DATA(IP8_5_3, VI0_R4), ++ PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), ++ PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), ++ PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO), ++ PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), ++ PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), ++ PINMUX_IPSR_DATA(IP8_8_6, VI0_R5), ++ PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), ++ PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), ++ PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK), ++ PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), ++ PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N), ++ PINMUX_IPSR_DATA(IP8_11_9, VI0_R6), ++ PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), ++ PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC), ++ PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), ++ PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N), ++ PINMUX_IPSR_DATA(IP8_14_12, VI0_R7), ++ PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), ++ PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT), ++ PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), ++ PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), ++ PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS), ++ PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), ++ PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), ++ PINMUX_IPSR_DATA(IP8_19_17, PWM5), ++ PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1), ++ PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK), ++ PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), ++ PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B), ++ PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), ++ PINMUX_IPSR_DATA(IP8_22_20, TPUTO0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0), ++ PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE), ++ PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), ++ PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), ++ PINMUX_IPSR_DATA(IP8_25_23, PWM5_B), ++ PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), ++ PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B), ++ PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), ++ PINMUX_IPSR_DATA(IP8_28_26, IRQ5), ++ PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1), ++ PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2), ++ PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD), ++ PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), ++ PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), ++ PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2), ++ PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2), ++ PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0), ++ ++ /* IPSR9 */ ++ PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD), ++ PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), ++ PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3), ++ PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RIF1_D1_B, SEL_DR3_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP9_2_0, FMIN_C, SEL_DARC_2), ++ PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RDS_DATA, SEL_RDS_0), ++ PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK), ++ PINMUX_IPSR_DATA(IP9_5_3, IRQ0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_5_3, TS_SDATA, SEL_TSIF0_0), ++ PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4), ++ PINMUX_IPSR_MODSEL_DATA(IP9_5_3, RIF1_SYNC, SEL_DR2_0), ++ PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C), ++ PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC), ++ PINMUX_IPSR_DATA(IP9_8_6, PWM1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_8_6, TS_SCK, SEL_TSIF0_0), ++ PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5), ++ PINMUX_IPSR_MODSEL_DATA(IP9_8_6, RIF1_CLK, SEL_DR2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_8_6, BPFCLK_B, SEL_DARC_1), ++ PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_9, TS_SDEN, SEL_TSIF0_0), ++ PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RIF1_D0, SEL_DR2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_9, FMCLK_B, SEL_DARC_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RDS_CLK_B, SEL_RDS_1), ++ PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2), ++ PINMUX_IPSR_MODSEL_DATA(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), ++ PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7), ++ PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RIF1_D1, SEL_DR3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_14_12, FMIN_B, SEL_DARC_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RDS_DATA_B, SEL_RDS_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_16_15, I2C4_SCL, SEL_I2C04_0), ++ PINMUX_IPSR_DATA(IP9_16_15, PWM6), ++ PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_18_17, I2C4_SDA, SEL_I2C04_0), ++ PINMUX_IPSR_DATA(IP9_18_17, TPUTO1), ++ PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1), ++ PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK), ++ PINMUX_IPSR_DATA(IP9_21_19, PWM2), ++ PINMUX_IPSR_MODSEL_DATA(IP9_21_19, IETX, SEL_IEB_0), ++ PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2), ++ PINMUX_IPSR_MODSEL_DATA(IP9_21_19, REMOCON_B, SEL_RCN_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_21_19, SPEEDIN_B, SEL_RSP_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_21_19, VSP_B, SEL_SPDM_1), ++ PINMUX_IPSR_MODSEL_DATA(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_24_22, IECLK, SEL_IEB_0), ++ PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3), ++ PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), ++ PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER), ++ PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32), ++ PINMUX_IPSR_MODSEL_DATA(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), ++ PINMUX_IPSR_MODSEL_DATA(IP9_27_25, IERX, SEL_IEB_0), ++ PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4), ++ PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), ++ PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0), ++ PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33), ++ PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), ++ PINMUX_IPSR_DATA(IP9_30_28, PWM3), ++ PINMUX_IPSR_MODSEL_DATA(IP9_30_28, TCLK2, SEL_TMU_0), ++ PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5), ++ PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), ++ PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK), ++ PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34), ++ ++ /* IPSR10 */ ++ PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_2_0, IIC0_SCL, SEL_IIC00_0), ++ PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6), ++ PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), ++ PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0), ++ PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35), ++ PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_5_3, IIC0_SDA, SEL_IIC00_0), ++ PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7), ++ PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), ++ PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1), ++ PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36), ++ PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IIC1_SCL, SEL_IIC01_0), ++ PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), ++ PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP), ++ PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2), ++ PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37), ++ PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IIC1_SDA, SEL_IIC01_0), ++ PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1), ++ PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), ++ PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1), ++ PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3), ++ PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38), ++ PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), ++ PINMUX_IPSR_DATA(IP10_14_12, IRQ1), ++ PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2), ++ PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), ++ PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN), ++ PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4), ++ PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39), ++ PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), ++ PINMUX_IPSR_DATA(IP10_17_15, IRQ2), ++ PINMUX_IPSR_MODSEL_DATA(IP10_17_15, BPFCLK_D, SEL_DARC_3), ++ PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3), ++ PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), ++ PINMUX_IPSR_DATA(IP10_17_15, TANS2), ++ PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5), ++ PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT), ++ PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), ++ PINMUX_IPSR_MODSEL_DATA(IP10_20_18, FMCLK_D, SEL_DARC_3), ++ PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4), ++ PINMUX_IPSR_MODSEL_DATA(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), ++ PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), ++ PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6), ++ PINMUX_IPSR_MODSEL_DATA(IP10_20_18, RDS_CLK_C, SEL_RDS_2), ++ PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), ++ PINMUX_IPSR_MODSEL_DATA(IP10_23_21, FMIN_D, SEL_DARC_3), ++ PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5), ++ PINMUX_IPSR_MODSEL_DATA(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), ++ PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), ++ PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7), ++ PINMUX_IPSR_MODSEL_DATA(IP10_23_21, RDS_DATA_C, SEL_RDS_2), ++ PINMUX_IPSR_MODSEL_DATA(IP10_26_24, I2C2_SCL, SEL_I2C02_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), ++ PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6), ++ PINMUX_IPSR_MODSEL_DATA(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), ++ PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), ++ PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8), ++ PINMUX_IPSR_MODSEL_DATA(IP10_29_27, I2C2_SDA, SEL_I2C02_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), ++ PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7), ++ PINMUX_IPSR_MODSEL_DATA(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), ++ PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9), ++ PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SSI_SCK5, SEL_SSI5_0), ++ PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), ++ PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN), ++ PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10), ++ ++ /* IPSR11 */ ++ PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), ++ PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0), ++ PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11), ++ PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), ++ PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1), ++ PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12), ++ PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), ++ PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), ++ PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13), ++ PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), ++ PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), ++ PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14), ++ PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), ++ PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), ++ PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15), ++ PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), ++ PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP), ++ PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), ++ PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE), ++ PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), ++ PINMUX_IPSR_DATA(IP11_20_18, IRQ8), ++ PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), ++ PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3), ++ PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N), ++ PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129), ++ PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), ++ PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1), ++ PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N), ++ PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129), ++ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), ++ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1), ++ PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0), ++ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), ++ PINMUX_IPSR_DATA(IP11_29_27, PWM0_B), ++ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1), ++ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1), ++ ++ /* IPSR12 */ ++ PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34), ++ PINMUX_IPSR_MODSEL_DATA(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP12_2_0, ADICHS0_B, SEL_RAD_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_2_0, AD_NCS_N_B, SEL_ADI_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_2_0, DREQ1_N_B, SEL_LBS_1), ++ PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34), ++ PINMUX_IPSR_MODSEL_DATA(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP12_5_3, ADICHS1_B, SEL_RAD_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_5_3, CAN1_RX_C, SEL_CAN1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP12_5_3, DACK1_B, SEL_LBS_1), ++ PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3), ++ PINMUX_IPSR_MODSEL_DATA(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2), ++ PINMUX_IPSR_MODSEL_DATA(IP12_8_6, ADICHS2_B, SEL_RAD_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_8_6, CAN1_TX_C, SEL_CAN1_2), ++ PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N), ++ PINMUX_IPSR_MODSEL_DATA(IP12_10_9, SSI_SCK4, SEL_SSI4_0), ++ PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK), ++ PINMUX_IPSR_MODSEL_DATA(IP12_10_9, IETX_B, SEL_IEB_1), ++ PINMUX_IPSR_DATA(IP12_10_9, IRD_TX), ++ PINMUX_IPSR_MODSEL_DATA(IP12_12_11, SSI_WS4, SEL_SSI4_0), ++ PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG), ++ PINMUX_IPSR_MODSEL_DATA(IP12_12_11, IECLK_B, SEL_IEB_1), ++ PINMUX_IPSR_DATA(IP12_12_11, IRD_RX), ++ PINMUX_IPSR_MODSEL_DATA(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), ++ PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT), ++ PINMUX_IPSR_MODSEL_DATA(IP12_14_13, IERX_B, SEL_IEB_1), ++ PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK), ++ PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), ++ PINMUX_IPSR_DATA(IP12_17_15, PWM1_B), ++ PINMUX_IPSR_DATA(IP12_17_15, IRQ9), ++ PINMUX_IPSR_MODSEL_DATA(IP12_17_15, REMOCON, SEL_RCN_0), ++ PINMUX_IPSR_DATA(IP12_17_15, DACK2), ++ PINMUX_IPSR_MODSEL_DATA(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SSI_SCK1, SEL_SSI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2), ++ PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK), ++ PINMUX_IPSR_MODSEL_DATA(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SSI_WS1, SEL_SSI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2), ++ PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), ++ PINMUX_IPSR_MODSEL_DATA(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SDATA, SEL_FSN_0), ++ PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N), ++ PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), ++ PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SSI_SCK2, SEL_SSI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2), ++ PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MDATA, SEL_FSN_0), ++ PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N), ++ PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), ++ ++ /* IPSR13 */ ++ PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_WS2, SEL_SSI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), ++ PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3), ++ PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCKZ, SEL_FSN_0), ++ PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N), ++ PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ETH_LINK_B, SEL_ETH_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), ++ PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4), ++ PINMUX_IPSR_MODSEL_DATA(IP13_5_3, STM_N, SEL_FSN_0), ++ PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N), ++ PINMUX_IPSR_MODSEL_DATA(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SSI_SCK9, SEL_SSI9_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), ++ PINMUX_IPSR_DATA(IP13_8_6, PWM2_B), ++ PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5), ++ PINMUX_IPSR_MODSEL_DATA(IP13_8_6, MTS_N, SEL_FSN_0), ++ PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SSI_WS9, SEL_SSI9_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4), ++ PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6), ++ PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N), ++ PINMUX_IPSR_MODSEL_DATA(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SSI_SDATA9, SEL_SSI9_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4), ++ PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7), ++ PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N), ++ PINMUX_IPSR_MODSEL_DATA(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_17_15, AUDIO_CLKA, SEL_ADG_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), ++ PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB), ++ PINMUX_IPSR_MODSEL_DATA(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MODSEL_DATA(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), ++ PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD), ++ PINMUX_IPSR_MODSEL_DATA(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MODSEL_DATA(IP13_20_18, RIF0_CLK_B, SEL_DR0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_20_18, BPFCLK_E, SEL_DARC_4), ++ PINMUX_IPSR_MODSEL_DATA(IP13_20_18, ETH_MDC_B, SEL_ETH_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), ++ PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N), ++ PINMUX_IPSR_MODSEL_DATA(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RIF0_D0_B, SEL_DR0_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_23_21, FMCLK_E, SEL_DARC_4), ++ PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RDS_CLK_D, SEL_RDS_3), ++ PINMUX_IPSR_MODSEL_DATA(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), ++ PINMUX_IPSR_MODSEL_DATA(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), ++ PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N), ++ PINMUX_IPSR_MODSEL_DATA(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RIF0_D1_B, SEL_DR1_1), ++ PINMUX_IPSR_MODSEL_DATA(IP13_26_24, FMIN_E, SEL_DARC_4), ++ PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RDS_DATA_D, SEL_RDS_3), ++}; ++ ++static const struct sh_pfc_pin pinmux_pins[] = { ++ PINMUX_GPIO_GP_ALL(), ++}; ++ ++/* - ETH -------------------------------------------------------------------- */ ++static const unsigned int eth_link_pins[] = { ++ /* LINK */ ++ RCAR_GP_PIN(3, 18), ++}; ++static const unsigned int eth_link_mux[] = { ++ ETH_LINK_MARK, ++}; ++static const unsigned int eth_magic_pins[] = { ++ /* MAGIC */ ++ RCAR_GP_PIN(3, 22), ++}; ++static const unsigned int eth_magic_mux[] = { ++ ETH_MAGIC_MARK, ++}; ++static const unsigned int eth_mdio_pins[] = { ++ /* MDC, MDIO */ ++ RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13), ++}; ++static const unsigned int eth_mdio_mux[] = { ++ ETH_MDC_MARK, ETH_MDIO_MARK, ++}; ++static const unsigned int eth_rmii_pins[] = { ++ /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ ++ RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15), ++ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20), ++ RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19), ++}; ++static const unsigned int eth_rmii_mux[] = { ++ ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, ++ ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, ++}; ++static const unsigned int eth_link_b_pins[] = { ++ /* LINK */ ++ RCAR_GP_PIN(5, 15), ++}; ++static const unsigned int eth_link_b_mux[] = { ++ ETH_LINK_B_MARK, ++}; ++static const unsigned int eth_magic_b_pins[] = { ++ /* MAGIC */ ++ RCAR_GP_PIN(5, 19), ++}; ++static const unsigned int eth_magic_b_mux[] = { ++ ETH_MAGIC_B_MARK, ++}; ++static const unsigned int eth_mdio_b_pins[] = { ++ /* MDC, MDIO */ ++ RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10), ++}; ++static const unsigned int eth_mdio_b_mux[] = { ++ ETH_MDC_B_MARK, ETH_MDIO_B_MARK, ++}; ++static const unsigned int eth_rmii_b_pins[] = { ++ /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ ++ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12), ++ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17), ++ RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16), ++}; ++static const unsigned int eth_rmii_b_mux[] = { ++ ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK, ++ ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK, ++}; ++/* - HSCIF0 ----------------------------------------------------------------- */ ++static const unsigned int hscif0_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), ++}; ++static const unsigned int hscif0_data_mux[] = { ++ HSCIF0_HRX_MARK, HSCIF0_HTX_MARK, ++}; ++static const unsigned int hscif0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 29), ++}; ++static const unsigned int hscif0_clk_mux[] = { ++ HSCIF0_HSCK_MARK, ++}; ++static const unsigned int hscif0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), ++}; ++static const unsigned int hscif0_ctrl_mux[] = { ++ HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK, ++}; ++static const unsigned int hscif0_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31), ++}; ++static const unsigned int hscif0_data_b_mux[] = { ++ HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK, ++}; ++static const unsigned int hscif0_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 0), ++}; ++static const unsigned int hscif0_clk_b_mux[] = { ++ HSCIF0_HSCK_B_MARK, ++}; ++/* - HSCIF1 ----------------------------------------------------------------- */ ++static const unsigned int hscif1_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), ++}; ++static const unsigned int hscif1_data_mux[] = { ++ HSCIF1_HRX_MARK, HSCIF1_HTX_MARK, ++}; ++static const unsigned int hscif1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 10), ++}; ++static const unsigned int hscif1_clk_mux[] = { ++ HSCIF1_HSCK_MARK, ++}; ++static const unsigned int hscif1_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), ++}; ++static const unsigned int hscif1_ctrl_mux[] = { ++ HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK, ++}; ++static const unsigned int hscif1_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), ++}; ++static const unsigned int hscif1_data_b_mux[] = { ++ HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK, ++}; ++static const unsigned int hscif1_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), ++}; ++static const unsigned int hscif1_ctrl_b_mux[] = { ++ HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK, ++}; ++/* - HSCIF2 ----------------------------------------------------------------- */ ++static const unsigned int hscif2_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), ++}; ++static const unsigned int hscif2_data_mux[] = { ++ HSCIF2_HRX_MARK, HSCIF2_HTX_MARK, ++}; ++static const unsigned int hscif2_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 10), ++}; ++static const unsigned int hscif2_clk_mux[] = { ++ HSCIF2_HSCK_MARK, ++}; ++static const unsigned int hscif2_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), ++}; ++static const unsigned int hscif2_ctrl_mux[] = { ++ HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK, ++}; ++/* - I2C0 ------------------------------------------------------------------- */ ++static const unsigned int i2c0_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), ++}; ++static const unsigned int i2c0_mux[] = { ++ I2C0_SCL_MARK, I2C0_SDA_MARK, ++}; ++static const unsigned int i2c0_b_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), ++}; ++static const unsigned int i2c0_b_mux[] = { ++ I2C0_SCL_B_MARK, I2C0_SDA_B_MARK, ++}; ++static const unsigned int i2c0_c_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), ++}; ++static const unsigned int i2c0_c_mux[] = { ++ I2C0_SCL_C_MARK, I2C0_SDA_C_MARK, ++}; ++static const unsigned int i2c0_d_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), ++}; ++static const unsigned int i2c0_d_mux[] = { ++ I2C0_SCL_D_MARK, I2C0_SDA_D_MARK, ++}; ++static const unsigned int i2c0_e_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), ++}; ++static const unsigned int i2c0_e_mux[] = { ++ I2C0_SCL_E_MARK, I2C0_SDA_E_MARK, ++}; ++/* - I2C1 ------------------------------------------------------------------- */ ++static const unsigned int i2c1_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), ++}; ++static const unsigned int i2c1_mux[] = { ++ I2C1_SCL_MARK, I2C1_SDA_MARK, ++}; ++static const unsigned int i2c1_b_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), ++}; ++static const unsigned int i2c1_b_mux[] = { ++ I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, ++}; ++static const unsigned int i2c1_c_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), ++}; ++static const unsigned int i2c1_c_mux[] = { ++ I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, ++}; ++static const unsigned int i2c1_d_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), ++}; ++static const unsigned int i2c1_d_mux[] = { ++ I2C1_SCL_D_MARK, I2C1_SDA_D_MARK, ++}; ++static const unsigned int i2c1_e_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), ++}; ++static const unsigned int i2c1_e_mux[] = { ++ I2C1_SCL_E_MARK, I2C1_SDA_E_MARK, ++}; ++/* - I2C2 ------------------------------------------------------------------- */ ++static const unsigned int i2c2_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), ++}; ++static const unsigned int i2c2_mux[] = { ++ I2C2_SCL_MARK, I2C2_SDA_MARK, ++}; ++static const unsigned int i2c2_b_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), ++}; ++static const unsigned int i2c2_b_mux[] = { ++ I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, ++}; ++static const unsigned int i2c2_c_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), ++}; ++static const unsigned int i2c2_c_mux[] = { ++ I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, ++}; ++static const unsigned int i2c2_d_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), ++}; ++static const unsigned int i2c2_d_mux[] = { ++ I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, ++}; ++static const unsigned int i2c2_e_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), ++}; ++static const unsigned int i2c2_e_mux[] = { ++ I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, ++}; ++/* - I2C3 ------------------------------------------------------------------- */ ++static const unsigned int i2c3_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), ++}; ++static const unsigned int i2c3_mux[] = { ++ I2C3_SCL_MARK, I2C3_SDA_MARK, ++}; ++static const unsigned int i2c3_b_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), ++}; ++static const unsigned int i2c3_b_mux[] = { ++ I2C3_SCL_B_MARK, I2C3_SDA_B_MARK, ++}; ++static const unsigned int i2c3_c_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), ++}; ++static const unsigned int i2c3_c_mux[] = { ++ I2C3_SCL_C_MARK, I2C3_SDA_C_MARK, ++}; ++static const unsigned int i2c3_d_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), ++}; ++static const unsigned int i2c3_d_mux[] = { ++ I2C3_SCL_D_MARK, I2C3_SDA_D_MARK, ++}; ++static const unsigned int i2c3_e_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), ++}; ++static const unsigned int i2c3_e_mux[] = { ++ I2C3_SCL_E_MARK, I2C3_SDA_E_MARK, ++}; ++/* - I2C4 ------------------------------------------------------------------- */ ++static const unsigned int i2c4_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), ++}; ++static const unsigned int i2c4_mux[] = { ++ I2C4_SCL_MARK, I2C4_SDA_MARK, ++}; ++static const unsigned int i2c4_b_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), ++}; ++static const unsigned int i2c4_b_mux[] = { ++ I2C4_SCL_B_MARK, I2C4_SDA_B_MARK, ++}; ++static const unsigned int i2c4_c_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), ++}; ++static const unsigned int i2c4_c_mux[] = { ++ I2C4_SCL_C_MARK, I2C4_SDA_C_MARK, ++}; ++static const unsigned int i2c4_d_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), ++}; ++static const unsigned int i2c4_d_mux[] = { ++ I2C4_SCL_D_MARK, I2C4_SDA_D_MARK, ++}; ++static const unsigned int i2c4_e_pins[] = { ++ /* SCL, SDA */ ++ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), ++}; ++static const unsigned int i2c4_e_mux[] = { ++ I2C4_SCL_E_MARK, I2C4_SDA_E_MARK, ++}; ++/* - INTC ------------------------------------------------------------------- */ ++static const unsigned int intc_irq0_pins[] = { ++ /* IRQ0 */ ++ RCAR_GP_PIN(4, 4), ++}; ++static const unsigned int intc_irq0_mux[] = { ++ IRQ0_MARK, ++}; ++static const unsigned int intc_irq1_pins[] = { ++ /* IRQ1 */ ++ RCAR_GP_PIN(4, 18), ++}; ++static const unsigned int intc_irq1_mux[] = { ++ IRQ1_MARK, ++}; ++static const unsigned int intc_irq2_pins[] = { ++ /* IRQ2 */ ++ RCAR_GP_PIN(4, 19), ++}; ++static const unsigned int intc_irq2_mux[] = { ++ IRQ2_MARK, ++}; ++static const unsigned int intc_irq3_pins[] = { ++ /* IRQ3 */ ++ RCAR_GP_PIN(0, 7), ++}; ++static const unsigned int intc_irq3_mux[] = { ++ IRQ3_MARK, ++}; ++static const unsigned int intc_irq4_pins[] = { ++ /* IRQ4 */ ++ RCAR_GP_PIN(0, 0), ++}; ++static const unsigned int intc_irq4_mux[] = { ++ IRQ4_MARK, ++}; ++static const unsigned int intc_irq5_pins[] = { ++ /* IRQ5 */ ++ RCAR_GP_PIN(4, 1), ++}; ++static const unsigned int intc_irq5_mux[] = { ++ IRQ5_MARK, ++}; ++static const unsigned int intc_irq6_pins[] = { ++ /* IRQ6 */ ++ RCAR_GP_PIN(0, 10), ++}; ++static const unsigned int intc_irq6_mux[] = { ++ IRQ6_MARK, ++}; ++static const unsigned int intc_irq7_pins[] = { ++ /* IRQ7 */ ++ RCAR_GP_PIN(6, 15), ++}; ++static const unsigned int intc_irq7_mux[] = { ++ IRQ7_MARK, ++}; ++static const unsigned int intc_irq8_pins[] = { ++ /* IRQ8 */ ++ RCAR_GP_PIN(5, 0), ++}; ++static const unsigned int intc_irq8_mux[] = { ++ IRQ8_MARK, ++}; ++static const unsigned int intc_irq9_pins[] = { ++ /* IRQ9 */ ++ RCAR_GP_PIN(5, 10), ++}; ++static const unsigned int intc_irq9_mux[] = { ++ IRQ9_MARK, ++}; ++/* - MSIOF0 ----------------------------------------------------------------- */ ++static const unsigned int msiof0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 4), ++}; ++static const unsigned int msiof0_clk_mux[] = { ++ MSIOF0_SCK_MARK, ++}; ++static const unsigned int msiof0_sync_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(4, 5), ++}; ++static const unsigned int msiof0_sync_mux[] = { ++ MSIOF0_SYNC_MARK, ++}; ++static const unsigned int msiof0_ss1_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(4, 6), ++}; ++static const unsigned int msiof0_ss1_mux[] = { ++ MSIOF0_SS1_MARK, ++}; ++static const unsigned int msiof0_ss2_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(4, 7), ++}; ++static const unsigned int msiof0_ss2_mux[] = { ++ MSIOF0_SS2_MARK, ++}; ++static const unsigned int msiof0_rx_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(4, 2), ++}; ++static const unsigned int msiof0_rx_mux[] = { ++ MSIOF0_RXD_MARK, ++}; ++static const unsigned int msiof0_tx_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(4, 3), ++}; ++static const unsigned int msiof0_tx_mux[] = { ++ MSIOF0_TXD_MARK, ++}; ++/* - MSIOF1 ----------------------------------------------------------------- */ ++static const unsigned int msiof1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 26), ++}; ++static const unsigned int msiof1_clk_mux[] = { ++ MSIOF1_SCK_MARK, ++}; ++static const unsigned int msiof1_sync_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(0, 27), ++}; ++static const unsigned int msiof1_sync_mux[] = { ++ MSIOF1_SYNC_MARK, ++}; ++static const unsigned int msiof1_ss1_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(0, 28), ++}; ++static const unsigned int msiof1_ss1_mux[] = { ++ MSIOF1_SS1_MARK, ++}; ++static const unsigned int msiof1_ss2_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(0, 29), ++}; ++static const unsigned int msiof1_ss2_mux[] = { ++ MSIOF1_SS2_MARK, ++}; ++static const unsigned int msiof1_rx_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(0, 24), ++}; ++static const unsigned int msiof1_rx_mux[] = { ++ MSIOF1_RXD_MARK, ++}; ++static const unsigned int msiof1_tx_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(0, 25), ++}; ++static const unsigned int msiof1_tx_mux[] = { ++ MSIOF1_TXD_MARK, ++}; ++static const unsigned int msiof1_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 3), ++}; ++static const unsigned int msiof1_clk_b_mux[] = { ++ MSIOF1_SCK_B_MARK, ++}; ++static const unsigned int msiof1_sync_b_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(5, 4), ++}; ++static const unsigned int msiof1_sync_b_mux[] = { ++ MSIOF1_SYNC_B_MARK, ++}; ++static const unsigned int msiof1_ss1_b_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(5, 5), ++}; ++static const unsigned int msiof1_ss1_b_mux[] = { ++ MSIOF1_SS1_B_MARK, ++}; ++static const unsigned int msiof1_ss2_b_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(5, 6), ++}; ++static const unsigned int msiof1_ss2_b_mux[] = { ++ MSIOF1_SS2_B_MARK, ++}; ++static const unsigned int msiof1_rx_b_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(5, 1), ++}; ++static const unsigned int msiof1_rx_b_mux[] = { ++ MSIOF1_RXD_B_MARK, ++}; ++static const unsigned int msiof1_tx_b_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(5, 2), ++}; ++static const unsigned int msiof1_tx_b_mux[] = { ++ MSIOF1_TXD_B_MARK, ++}; ++/* - MSIOF2 ----------------------------------------------------------------- */ ++static const unsigned int msiof2_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 0), ++}; ++static const unsigned int msiof2_clk_mux[] = { ++ MSIOF2_SCK_MARK, ++}; ++static const unsigned int msiof2_sync_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(1, 1), ++}; ++static const unsigned int msiof2_sync_mux[] = { ++ MSIOF2_SYNC_MARK, ++}; ++static const unsigned int msiof2_ss1_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(1, 2), ++}; ++static const unsigned int msiof2_ss1_mux[] = { ++ MSIOF2_SS1_MARK, ++}; ++static const unsigned int msiof2_ss2_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(1, 3), ++}; ++static const unsigned int msiof2_ss2_mux[] = { ++ MSIOF2_SS2_MARK, ++}; ++static const unsigned int msiof2_rx_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(0, 30), ++}; ++static const unsigned int msiof2_rx_mux[] = { ++ MSIOF2_RXD_MARK, ++}; ++static const unsigned int msiof2_tx_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(0, 31), ++}; ++static const unsigned int msiof2_tx_mux[] = { ++ MSIOF2_TXD_MARK, ++}; ++static const unsigned int msiof2_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 15), ++}; ++static const unsigned int msiof2_clk_b_mux[] = { ++ MSIOF2_SCK_B_MARK, ++}; ++static const unsigned int msiof2_sync_b_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(3, 16), ++}; ++static const unsigned int msiof2_sync_b_mux[] = { ++ MSIOF2_SYNC_B_MARK, ++}; ++static const unsigned int msiof2_ss1_b_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(3, 17), ++}; ++static const unsigned int msiof2_ss1_b_mux[] = { ++ MSIOF2_SS1_B_MARK, ++}; ++static const unsigned int msiof2_ss2_b_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(3, 18), ++}; ++static const unsigned int msiof2_ss2_b_mux[] = { ++ MSIOF2_SS2_B_MARK, ++}; ++static const unsigned int msiof2_rx_b_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(3, 13), ++}; ++static const unsigned int msiof2_rx_b_mux[] = { ++ MSIOF2_RXD_B_MARK, ++}; ++static const unsigned int msiof2_tx_b_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(3, 14), ++}; ++static const unsigned int msiof2_tx_b_mux[] = { ++ MSIOF2_TXD_B_MARK, ++}; ++/* - QSPI ------------------------------------------------------------------- */ ++static const unsigned int qspi_ctrl_pins[] = { ++ /* SPCLK, SSL */ ++ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), ++}; ++static const unsigned int qspi_ctrl_mux[] = { ++ SPCLK_MARK, SSL_MARK, ++}; ++static const unsigned int qspi_data2_pins[] = { ++ /* MOSI_IO0, MISO_IO1 */ ++ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), ++}; ++static const unsigned int qspi_data2_mux[] = { ++ MOSI_IO0_MARK, MISO_IO1_MARK, ++}; ++static const unsigned int qspi_data4_pins[] = { ++ /* MOSI_IO0, MISO_IO1, IO2, IO3 */ ++ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), ++ RCAR_GP_PIN(1, 8), ++}; ++static const unsigned int qspi_data4_mux[] = { ++ MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, ++}; ++/* - SCIF0 ------------------------------------------------------------------ */ ++static const unsigned int scif0_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), ++}; ++static const unsigned int scif0_data_mux[] = { ++ SCIF0_RXD_MARK, SCIF0_TXD_MARK, ++}; ++static const unsigned int scif0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 23), ++}; ++static const unsigned int scif0_clk_mux[] = { ++ SCIF_CLK_MARK, ++}; ++static const unsigned int scif0_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), ++}; ++static const unsigned int scif0_data_b_mux[] = { ++ SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK, ++}; ++static const unsigned int scif0_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 29), ++}; ++static const unsigned int scif0_clk_b_mux[] = { ++ SCIF_CLK_B_MARK, ++}; ++static const unsigned int scif0_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), ++}; ++static const unsigned int scif0_data_c_mux[] = { ++ SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK, ++}; ++static const unsigned int scif0_data_d_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), ++}; ++static const unsigned int scif0_data_d_mux[] = { ++ SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK, ++}; ++/* - SCIF1 ------------------------------------------------------------------ */ ++static const unsigned int scif1_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), ++}; ++static const unsigned int scif1_data_mux[] = { ++ SCIF1_RXD_MARK, SCIF1_TXD_MARK, ++}; ++static const unsigned int scif1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 13), ++}; ++static const unsigned int scif1_clk_mux[] = { ++ SCIF1_SCK_MARK, ++}; ++static const unsigned int scif1_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), ++}; ++static const unsigned int scif1_data_b_mux[] = { ++ SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK, ++}; ++static const unsigned int scif1_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 10), ++}; ++static const unsigned int scif1_clk_b_mux[] = { ++ SCIF1_SCK_B_MARK, ++}; ++static const unsigned int scif1_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), ++}; ++static const unsigned int scif1_data_c_mux[] = { ++ SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK, ++}; ++static const unsigned int scif1_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 10), ++}; ++static const unsigned int scif1_clk_c_mux[] = { ++ SCIF1_SCK_C_MARK, ++}; ++/* - SCIF2 ------------------------------------------------------------------ */ ++static const unsigned int scif2_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), ++}; ++static const unsigned int scif2_data_mux[] = { ++ SCIF2_RXD_MARK, SCIF2_TXD_MARK, ++}; ++static const unsigned int scif2_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 18), ++}; ++static const unsigned int scif2_clk_mux[] = { ++ SCIF2_SCK_MARK, ++}; ++static const unsigned int scif2_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), ++}; ++static const unsigned int scif2_data_b_mux[] = { ++ SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK, ++}; ++static const unsigned int scif2_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 17), ++}; ++static const unsigned int scif2_clk_b_mux[] = { ++ SCIF2_SCK_B_MARK, ++}; ++static const unsigned int scif2_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), ++}; ++static const unsigned int scif2_data_c_mux[] = { ++ SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK, ++}; ++static const unsigned int scif2_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 19), ++}; ++static const unsigned int scif2_clk_c_mux[] = { ++ SCIF2_SCK_C_MARK, ++}; ++/* - SCIF3 ------------------------------------------------------------------ */ ++static const unsigned int scif3_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), ++}; ++static const unsigned int scif3_data_mux[] = { ++ SCIF3_RXD_MARK, SCIF3_TXD_MARK, ++}; ++static const unsigned int scif3_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 19), ++}; ++static const unsigned int scif3_clk_mux[] = { ++ SCIF3_SCK_MARK, ++}; ++static const unsigned int scif3_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), ++}; ++static const unsigned int scif3_data_b_mux[] = { ++ SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK, ++}; ++static const unsigned int scif3_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 22), ++}; ++static const unsigned int scif3_clk_b_mux[] = { ++ SCIF3_SCK_B_MARK, ++}; ++/* - SCIF4 ------------------------------------------------------------------ */ ++static const unsigned int scif4_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), ++}; ++static const unsigned int scif4_data_mux[] = { ++ SCIF4_RXD_MARK, SCIF4_TXD_MARK, ++}; ++static const unsigned int scif4_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), ++}; ++static const unsigned int scif4_data_b_mux[] = { ++ SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK, ++}; ++static const unsigned int scif4_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), ++}; ++static const unsigned int scif4_data_c_mux[] = { ++ SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK, ++}; ++static const unsigned int scif4_data_d_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), ++}; ++static const unsigned int scif4_data_d_mux[] = { ++ SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK, ++}; ++static const unsigned int scif4_data_e_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), ++}; ++static const unsigned int scif4_data_e_mux[] = { ++ SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK, ++}; ++/* - SCIF5 ------------------------------------------------------------------ */ ++static const unsigned int scif5_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), ++}; ++static const unsigned int scif5_data_mux[] = { ++ SCIF5_RXD_MARK, SCIF5_TXD_MARK, ++}; ++static const unsigned int scif5_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), ++}; ++static const unsigned int scif5_data_b_mux[] = { ++ SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK, ++}; ++static const unsigned int scif5_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11), ++}; ++static const unsigned int scif5_data_c_mux[] = { ++ SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK, ++}; ++static const unsigned int scif5_data_d_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), ++}; ++static const unsigned int scif5_data_d_mux[] = { ++ SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK, ++}; ++/* - SCIFA0 ----------------------------------------------------------------- */ ++static const unsigned int scifa0_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), ++}; ++static const unsigned int scifa0_data_mux[] = { ++ SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, ++}; ++static const unsigned int scifa0_data_b_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), ++}; ++static const unsigned int scifa0_data_b_mux[] = { ++ SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK ++}; ++static const unsigned int scifa0_data_c_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), ++}; ++static const unsigned int scifa0_data_c_mux[] = { ++ SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK ++}; ++static const unsigned int scifa0_data_d_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), ++}; ++static const unsigned int scifa0_data_d_mux[] = { ++ SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK ++}; ++/* - SCIFA1 ----------------------------------------------------------------- */ ++static const unsigned int scifa1_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), ++}; ++static const unsigned int scifa1_data_mux[] = { ++ SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, ++}; ++static const unsigned int scifa1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 13), ++}; ++static const unsigned int scifa1_clk_mux[] = { ++ SCIFA1_SCK_MARK, ++}; ++static const unsigned int scifa1_data_b_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), ++}; ++static const unsigned int scifa1_data_b_mux[] = { ++ SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, ++}; ++static const unsigned int scifa1_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 27), ++}; ++static const unsigned int scifa1_clk_b_mux[] = { ++ SCIFA1_SCK_B_MARK, ++}; ++static const unsigned int scifa1_data_c_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), ++}; ++static const unsigned int scifa1_data_c_mux[] = { ++ SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, ++}; ++static const unsigned int scifa1_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 4), ++}; ++static const unsigned int scifa1_clk_c_mux[] = { ++ SCIFA1_SCK_C_MARK, ++}; ++/* - SCIFA2 ----------------------------------------------------------------- */ ++static const unsigned int scifa2_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), ++}; ++static const unsigned int scifa2_data_mux[] = { ++ SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, ++}; ++static const unsigned int scifa2_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 15), ++}; ++static const unsigned int scifa2_clk_mux[] = { ++ SCIFA2_SCK_MARK, ++}; ++static const unsigned int scifa2_data_b_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0), ++}; ++static const unsigned int scifa2_data_b_mux[] = { ++ SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, ++}; ++static const unsigned int scifa2_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 30), ++}; ++static const unsigned int scifa2_clk_b_mux[] = { ++ SCIFA2_SCK_B_MARK, ++}; ++/* - SCIFA3 ----------------------------------------------------------------- */ ++static const unsigned int scifa3_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), ++}; ++static const unsigned int scifa3_data_mux[] = { ++ SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, ++}; ++static const unsigned int scifa3_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(4, 24), ++}; ++static const unsigned int scifa3_clk_mux[] = { ++ SCIFA3_SCK_MARK, ++}; ++static const unsigned int scifa3_data_b_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), ++}; ++static const unsigned int scifa3_data_b_mux[] = { ++ SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK, ++}; ++static const unsigned int scifa3_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 0), ++}; ++static const unsigned int scifa3_clk_b_mux[] = { ++ SCIFA3_SCK_B_MARK, ++}; ++/* - SCIFA4 ----------------------------------------------------------------- */ ++static const unsigned int scifa4_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12), ++}; ++static const unsigned int scifa4_data_mux[] = { ++ SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, ++}; ++static const unsigned int scifa4_data_b_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23), ++}; ++static const unsigned int scifa4_data_b_mux[] = { ++ SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK, ++}; ++static const unsigned int scifa4_data_c_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), ++}; ++static const unsigned int scifa4_data_c_mux[] = { ++ SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK, ++}; ++static const unsigned int scifa4_data_d_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), ++}; ++static const unsigned int scifa4_data_d_mux[] = { ++ SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK, ++}; ++/* - SCIFA5 ----------------------------------------------------------------- */ ++static const unsigned int scifa5_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), ++}; ++static const unsigned int scifa5_data_mux[] = { ++ SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, ++}; ++static const unsigned int scifa5_data_b_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29), ++}; ++static const unsigned int scifa5_data_b_mux[] = { ++ SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK, ++}; ++static const unsigned int scifa5_data_c_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), ++}; ++static const unsigned int scifa5_data_c_mux[] = { ++ SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK, ++}; ++static const unsigned int scifa5_data_d_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), ++}; ++static const unsigned int scifa5_data_d_mux[] = { ++ SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK, ++}; ++/* - SCIFB0 ----------------------------------------------------------------- */ ++static const unsigned int scifb0_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20), ++}; ++static const unsigned int scifb0_data_mux[] = { ++ SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, ++}; ++static const unsigned int scifb0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 19), ++}; ++static const unsigned int scifb0_clk_mux[] = { ++ SCIFB0_SCK_MARK, ++}; ++static const unsigned int scifb0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), ++}; ++static const unsigned int scifb0_ctrl_mux[] = { ++ SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, ++}; ++/* - SCIFB1 ----------------------------------------------------------------- */ ++static const unsigned int scifb1_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17), ++}; ++static const unsigned int scifb1_data_mux[] = { ++ SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, ++}; ++static const unsigned int scifb1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 16), ++}; ++static const unsigned int scifb1_clk_mux[] = { ++ SCIFB1_SCK_MARK, ++}; ++/* - SCIFB2 ----------------------------------------------------------------- */ ++static const unsigned int scifb2_data_pins[] = { ++ /* RXD, TXD */ ++ RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), ++}; ++static const unsigned int scifb2_data_mux[] = { ++ SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, ++}; ++static const unsigned int scifb2_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 15), ++}; ++static const unsigned int scifb2_clk_mux[] = { ++ SCIFB2_SCK_MARK, ++}; ++static const unsigned int scifb2_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), ++}; ++static const unsigned int scifb2_ctrl_mux[] = { ++ SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, ++}; ++ ++static const struct sh_pfc_pin_group pinmux_groups[] = { ++ SH_PFC_PIN_GROUP(eth_link), ++ SH_PFC_PIN_GROUP(eth_magic), ++ SH_PFC_PIN_GROUP(eth_mdio), ++ SH_PFC_PIN_GROUP(eth_rmii), ++ SH_PFC_PIN_GROUP(eth_link_b), ++ SH_PFC_PIN_GROUP(eth_magic_b), ++ SH_PFC_PIN_GROUP(eth_mdio_b), ++ SH_PFC_PIN_GROUP(eth_rmii_b), ++ SH_PFC_PIN_GROUP(hscif0_data), ++ SH_PFC_PIN_GROUP(hscif0_clk), ++ SH_PFC_PIN_GROUP(hscif0_ctrl), ++ SH_PFC_PIN_GROUP(hscif0_data_b), ++ SH_PFC_PIN_GROUP(hscif0_clk_b), ++ SH_PFC_PIN_GROUP(hscif1_data), ++ SH_PFC_PIN_GROUP(hscif1_clk), ++ SH_PFC_PIN_GROUP(hscif1_ctrl), ++ SH_PFC_PIN_GROUP(hscif1_data_b), ++ SH_PFC_PIN_GROUP(hscif1_ctrl_b), ++ SH_PFC_PIN_GROUP(hscif2_data), ++ SH_PFC_PIN_GROUP(hscif2_clk), ++ SH_PFC_PIN_GROUP(hscif2_ctrl), ++ SH_PFC_PIN_GROUP(i2c0), ++ SH_PFC_PIN_GROUP(i2c0_b), ++ SH_PFC_PIN_GROUP(i2c0_c), ++ SH_PFC_PIN_GROUP(i2c0_d), ++ SH_PFC_PIN_GROUP(i2c0_e), ++ SH_PFC_PIN_GROUP(i2c1), ++ SH_PFC_PIN_GROUP(i2c1_b), ++ SH_PFC_PIN_GROUP(i2c1_c), ++ SH_PFC_PIN_GROUP(i2c1_d), ++ SH_PFC_PIN_GROUP(i2c1_e), ++ SH_PFC_PIN_GROUP(i2c2), ++ SH_PFC_PIN_GROUP(i2c2_b), ++ SH_PFC_PIN_GROUP(i2c2_c), ++ SH_PFC_PIN_GROUP(i2c2_d), ++ SH_PFC_PIN_GROUP(i2c2_e), ++ SH_PFC_PIN_GROUP(i2c3), ++ SH_PFC_PIN_GROUP(i2c3_b), ++ SH_PFC_PIN_GROUP(i2c3_c), ++ SH_PFC_PIN_GROUP(i2c3_d), ++ SH_PFC_PIN_GROUP(i2c3_e), ++ SH_PFC_PIN_GROUP(i2c4), ++ SH_PFC_PIN_GROUP(i2c4_b), ++ SH_PFC_PIN_GROUP(i2c4_c), ++ SH_PFC_PIN_GROUP(i2c4_d), ++ SH_PFC_PIN_GROUP(i2c4_e), ++ SH_PFC_PIN_GROUP(intc_irq0), ++ SH_PFC_PIN_GROUP(intc_irq1), ++ SH_PFC_PIN_GROUP(intc_irq2), ++ SH_PFC_PIN_GROUP(intc_irq3), ++ SH_PFC_PIN_GROUP(intc_irq4), ++ SH_PFC_PIN_GROUP(intc_irq5), ++ SH_PFC_PIN_GROUP(intc_irq6), ++ SH_PFC_PIN_GROUP(intc_irq7), ++ SH_PFC_PIN_GROUP(intc_irq8), ++ SH_PFC_PIN_GROUP(intc_irq9), ++ SH_PFC_PIN_GROUP(msiof0_clk), ++ SH_PFC_PIN_GROUP(msiof0_sync), ++ SH_PFC_PIN_GROUP(msiof0_ss1), ++ SH_PFC_PIN_GROUP(msiof0_ss2), ++ SH_PFC_PIN_GROUP(msiof0_rx), ++ SH_PFC_PIN_GROUP(msiof0_tx), ++ SH_PFC_PIN_GROUP(msiof1_clk), ++ SH_PFC_PIN_GROUP(msiof1_sync), ++ SH_PFC_PIN_GROUP(msiof1_ss1), ++ SH_PFC_PIN_GROUP(msiof1_ss2), ++ SH_PFC_PIN_GROUP(msiof1_rx), ++ SH_PFC_PIN_GROUP(msiof1_tx), ++ SH_PFC_PIN_GROUP(msiof1_clk_b), ++ SH_PFC_PIN_GROUP(msiof1_sync_b), ++ SH_PFC_PIN_GROUP(msiof1_ss1_b), ++ SH_PFC_PIN_GROUP(msiof1_ss2_b), ++ SH_PFC_PIN_GROUP(msiof1_rx_b), ++ SH_PFC_PIN_GROUP(msiof1_tx_b), ++ SH_PFC_PIN_GROUP(msiof2_clk), ++ SH_PFC_PIN_GROUP(msiof2_sync), ++ SH_PFC_PIN_GROUP(msiof2_ss1), ++ SH_PFC_PIN_GROUP(msiof2_ss2), ++ SH_PFC_PIN_GROUP(msiof2_rx), ++ SH_PFC_PIN_GROUP(msiof2_tx), ++ SH_PFC_PIN_GROUP(msiof2_clk_b), ++ SH_PFC_PIN_GROUP(msiof2_sync_b), ++ SH_PFC_PIN_GROUP(msiof2_ss1_b), ++ SH_PFC_PIN_GROUP(msiof2_ss2_b), ++ SH_PFC_PIN_GROUP(msiof2_rx_b), ++ SH_PFC_PIN_GROUP(msiof2_tx_b), ++ SH_PFC_PIN_GROUP(qspi_ctrl), ++ SH_PFC_PIN_GROUP(qspi_data2), ++ SH_PFC_PIN_GROUP(qspi_data4), ++ SH_PFC_PIN_GROUP(scif0_data), ++ SH_PFC_PIN_GROUP(scif0_clk), ++ SH_PFC_PIN_GROUP(scif0_data_b), ++ SH_PFC_PIN_GROUP(scif0_clk_b), ++ SH_PFC_PIN_GROUP(scif0_data_c), ++ SH_PFC_PIN_GROUP(scif0_data_d), ++ SH_PFC_PIN_GROUP(scif1_data), ++ SH_PFC_PIN_GROUP(scif1_clk), ++ SH_PFC_PIN_GROUP(scif1_data_b), ++ SH_PFC_PIN_GROUP(scif1_clk_b), ++ SH_PFC_PIN_GROUP(scif1_data_c), ++ SH_PFC_PIN_GROUP(scif1_clk_c), ++ SH_PFC_PIN_GROUP(scif2_data), ++ SH_PFC_PIN_GROUP(scif2_clk), ++ SH_PFC_PIN_GROUP(scif2_data_b), ++ SH_PFC_PIN_GROUP(scif2_clk_b), ++ SH_PFC_PIN_GROUP(scif2_data_c), ++ SH_PFC_PIN_GROUP(scif2_clk_c), ++ SH_PFC_PIN_GROUP(scif3_data), ++ SH_PFC_PIN_GROUP(scif3_clk), ++ SH_PFC_PIN_GROUP(scif3_data_b), ++ SH_PFC_PIN_GROUP(scif3_clk_b), ++ SH_PFC_PIN_GROUP(scif4_data), ++ SH_PFC_PIN_GROUP(scif4_data_b), ++ SH_PFC_PIN_GROUP(scif4_data_c), ++ SH_PFC_PIN_GROUP(scif4_data_d), ++ SH_PFC_PIN_GROUP(scif4_data_e), ++ SH_PFC_PIN_GROUP(scif5_data), ++ SH_PFC_PIN_GROUP(scif5_data_b), ++ SH_PFC_PIN_GROUP(scif5_data_c), ++ SH_PFC_PIN_GROUP(scif5_data_d), ++ SH_PFC_PIN_GROUP(scifa0_data), ++ SH_PFC_PIN_GROUP(scifa0_data_b), ++ SH_PFC_PIN_GROUP(scifa0_data_c), ++ SH_PFC_PIN_GROUP(scifa0_data_d), ++ SH_PFC_PIN_GROUP(scifa1_data), ++ SH_PFC_PIN_GROUP(scifa1_clk), ++ SH_PFC_PIN_GROUP(scifa1_data_b), ++ SH_PFC_PIN_GROUP(scifa1_clk_b), ++ SH_PFC_PIN_GROUP(scifa1_data_c), ++ SH_PFC_PIN_GROUP(scifa1_clk_c), ++ SH_PFC_PIN_GROUP(scifa2_data), ++ SH_PFC_PIN_GROUP(scifa2_clk), ++ SH_PFC_PIN_GROUP(scifa2_data_b), ++ SH_PFC_PIN_GROUP(scifa2_clk_b), ++ SH_PFC_PIN_GROUP(scifa3_data), ++ SH_PFC_PIN_GROUP(scifa3_clk), ++ SH_PFC_PIN_GROUP(scifa3_data_b), ++ SH_PFC_PIN_GROUP(scifa3_clk_b), ++ SH_PFC_PIN_GROUP(scifa4_data), ++ SH_PFC_PIN_GROUP(scifa4_data_b), ++ SH_PFC_PIN_GROUP(scifa4_data_c), ++ SH_PFC_PIN_GROUP(scifa4_data_d), ++ SH_PFC_PIN_GROUP(scifa5_data), ++ SH_PFC_PIN_GROUP(scifa5_data_b), ++ SH_PFC_PIN_GROUP(scifa5_data_c), ++ SH_PFC_PIN_GROUP(scifa5_data_d), ++ SH_PFC_PIN_GROUP(scifb0_data), ++ SH_PFC_PIN_GROUP(scifb0_clk), ++ SH_PFC_PIN_GROUP(scifb0_ctrl), ++ SH_PFC_PIN_GROUP(scifb1_data), ++ SH_PFC_PIN_GROUP(scifb1_clk), ++ SH_PFC_PIN_GROUP(scifb2_data), ++ SH_PFC_PIN_GROUP(scifb2_clk), ++ SH_PFC_PIN_GROUP(scifb2_ctrl), ++}; ++ ++static const char * const eth_groups[] = { ++ "eth_link", ++ "eth_magic", ++ "eth_mdio", ++ "eth_rmii", ++ "eth_link_b", ++ "eth_magic_b", ++ "eth_mdio_b", ++ "eth_rmii_b", ++}; ++ ++static const char * const hscif0_groups[] = { ++ "hscif0_data", ++ "hscif0_clk", ++ "hscif0_ctrl", ++ "hscif0_data_b", ++ "hscif0_clk_b", ++}; ++ ++static const char * const hscif1_groups[] = { ++ "hscif1_data", ++ "hscif1_clk", ++ "hscif1_ctrl", ++ "hscif1_data_b", ++ "hscif1_ctrl_b", ++}; ++ ++static const char * const hscif2_groups[] = { ++ "hscif2_data", ++ "hscif2_clk", ++ "hscif2_ctrl", ++}; ++ ++static const char * const i2c0_groups[] = { ++ "i2c0", ++ "i2c0_b", ++ "i2c0_c", ++ "i2c0_d", ++ "i2c0_e", ++}; ++ ++static const char * const i2c1_groups[] = { ++ "i2c1", ++ "i2c1_b", ++ "i2c1_c", ++ "i2c1_d", ++ "i2c1_e", ++}; ++ ++static const char * const i2c2_groups[] = { ++ "i2c2", ++ "i2c2_b", ++ "i2c2_c", ++ "i2c2_d", ++ "i2c2_e", ++}; ++ ++static const char * const i2c3_groups[] = { ++ "i2c3", ++ "i2c3_b", ++ "i2c3_c", ++ "i2c3_d", ++ "i2c3_e", ++}; ++ ++static const char * const i2c4_groups[] = { ++ "i2c4", ++ "i2c4_b", ++ "i2c4_c", ++ "i2c4_d", ++ "i2c4_e", ++}; ++ ++static const char * const intc_groups[] = { ++ "intc_irq0", ++ "intc_irq1", ++ "intc_irq2", ++ "intc_irq3", ++ "intc_irq4", ++ "intc_irq5", ++ "intc_irq6", ++ "intc_irq7", ++ "intc_irq8", ++ "intc_irq9", ++}; ++ ++static const char * const msiof0_groups[] = { ++ "msiof0_clk", ++ "msiof0_sync", ++ "msiof0_ss1", ++ "msiof0_ss2", ++ "msiof0_rx", ++ "msiof0_tx", ++}; ++ ++static const char * const msiof1_groups[] = { ++ "msiof1_clk", ++ "msiof1_sync", ++ "msiof1_ss1", ++ "msiof1_ss2", ++ "msiof1_rx", ++ "msiof1_tx", ++ "msiof1_clk_b", ++ "msiof1_sync_b", ++ "msiof1_ss1_b", ++ "msiof1_ss2_b", ++ "msiof1_rx_b", ++ "msiof1_tx_b", ++}; ++ ++static const char * const msiof2_groups[] = { ++ "msiof2_clk", ++ "msiof2_sync", ++ "msiof2_ss1", ++ "msiof2_ss2", ++ "msiof2_rx", ++ "msiof2_tx", ++ "msiof2_clk_b", ++ "msiof2_sync_b", ++ "msiof2_ss1_b", ++ "msiof2_ss2_b", ++ "msiof2_rx_b", ++ "msiof2_tx_b", ++}; ++ ++static const char * const qspi_groups[] = { ++ "qspi_ctrl", ++ "qspi_data2", ++ "qspi_data4", ++}; ++ ++static const char * const scif0_groups[] = { ++ "scif0_data", ++ "scif0_clk", ++ "scif0_data_b", ++ "scif0_clk_b", ++ "scif0_data_c", ++ "scif0_data_d", ++}; ++ ++static const char * const scif1_groups[] = { ++ "scif1_data", ++ "scif1_clk", ++ "scif1_data_b", ++ "scif1_clk_b", ++ "scif1_data_c", ++ "scif1_clk_c", ++}; ++ ++static const char * const scif2_groups[] = { ++ "scif2_data", ++ "scif2_clk", ++ "scif2_data_b", ++ "scif2_clk_b", ++ "scif2_data_c", ++ "scif2_clk_c", ++}; ++ ++static const char * const scif3_groups[] = { ++ "scif3_data", ++ "scif3_clk", ++ "scif3_data_b", ++ "scif3_clk_b", ++}; ++ ++static const char * const scif4_groups[] = { ++ "scif4_data", ++ "scif4_data_b", ++ "scif4_data_c", ++ "scif4_data_d", ++ "scif4_data_e", ++}; ++ ++static const char * const scif5_groups[] = { ++ "scif5_data", ++ "scif5_data_b", ++ "scif5_data_c", ++ "scif5_data_d", ++}; ++ ++static const char * const scifa0_groups[] = { ++ "scifa0_data", ++ "scifa0_data_b", ++ "scifa0_data_c", ++ "scifa0_data_d", ++}; ++ ++static const char * const scifa1_groups[] = { ++ "scifa1_data", ++ "scifa1_clk", ++ "scifa1_data_b", ++ "scifa1_clk_b", ++ "scifa1_data_c", ++ "scifa1_clk_c", ++}; ++ ++static const char * const scifa2_groups[] = { ++ "scifa2_data", ++ "scifa2_clk", ++ "scifa2_data_b", ++ "scifa2_clk_b", ++}; ++ ++static const char * const scifa3_groups[] = { ++ "scifa3_data", ++ "scifa3_clk", ++ "scifa3_data_b", ++ "scifa3_clk_b", ++}; ++ ++static const char * const scifa4_groups[] = { ++ "scifa4_data", ++ "scifa4_data_b", ++ "scifa4_data_c", ++ "scifa4_data_d", ++}; ++ ++static const char * const scifa5_groups[] = { ++ "scifa5_data", ++ "scifa5_data_b", ++ "scifa5_data_c", ++ "scifa5_data_d", ++}; ++ ++static const char * const scifb0_groups[] = { ++ "scifb0_data", ++ "scifb0_clk", ++ "scifb0_ctrl", ++}; ++ ++static const char * const scifb1_groups[] = { ++ "scifb1_data", ++ "scifb1_clk", ++}; ++ ++static const char * const scifb2_groups[] = { ++ "scifb2_data", ++ "scifb2_clk", ++ "scifb2_ctrl", ++}; ++ ++static const struct sh_pfc_function pinmux_functions[] = { ++ SH_PFC_FUNCTION(eth), ++ SH_PFC_FUNCTION(hscif0), ++ SH_PFC_FUNCTION(hscif1), ++ SH_PFC_FUNCTION(hscif2), ++ SH_PFC_FUNCTION(i2c0), ++ SH_PFC_FUNCTION(i2c1), ++ SH_PFC_FUNCTION(i2c2), ++ SH_PFC_FUNCTION(i2c3), ++ SH_PFC_FUNCTION(i2c4), ++ SH_PFC_FUNCTION(intc), ++ SH_PFC_FUNCTION(msiof0), ++ SH_PFC_FUNCTION(msiof1), ++ SH_PFC_FUNCTION(msiof2), ++ SH_PFC_FUNCTION(qspi), ++ SH_PFC_FUNCTION(scif0), ++ SH_PFC_FUNCTION(scif1), ++ SH_PFC_FUNCTION(scif2), ++ SH_PFC_FUNCTION(scif3), ++ SH_PFC_FUNCTION(scif4), ++ SH_PFC_FUNCTION(scif5), ++ SH_PFC_FUNCTION(scifa0), ++ SH_PFC_FUNCTION(scifa1), ++ SH_PFC_FUNCTION(scifa2), ++ SH_PFC_FUNCTION(scifa3), ++ SH_PFC_FUNCTION(scifa4), ++ SH_PFC_FUNCTION(scifa5), ++ SH_PFC_FUNCTION(scifb0), ++ SH_PFC_FUNCTION(scifb1), ++ SH_PFC_FUNCTION(scifb2), ++}; ++ ++static const struct pinmux_cfg_reg pinmux_config_regs[] = { ++ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { ++ GP_0_31_FN, FN_IP2_17_16, ++ GP_0_30_FN, FN_IP2_15_14, ++ GP_0_29_FN, FN_IP2_13_12, ++ GP_0_28_FN, FN_IP2_11_10, ++ GP_0_27_FN, FN_IP2_9_8, ++ GP_0_26_FN, FN_IP2_7_6, ++ GP_0_25_FN, FN_IP2_5_4, ++ GP_0_24_FN, FN_IP2_3_2, ++ GP_0_23_FN, FN_IP2_1_0, ++ GP_0_22_FN, FN_IP1_31_30, ++ GP_0_21_FN, FN_IP1_29_28, ++ GP_0_20_FN, FN_IP1_27, ++ GP_0_19_FN, FN_IP1_26, ++ GP_0_18_FN, FN_A2, ++ GP_0_17_FN, FN_IP1_24, ++ GP_0_16_FN, FN_IP1_23_22, ++ GP_0_15_FN, FN_IP1_21_20, ++ GP_0_14_FN, FN_IP1_19_18, ++ GP_0_13_FN, FN_IP1_17_15, ++ GP_0_12_FN, FN_IP1_14_13, ++ GP_0_11_FN, FN_IP1_12_11, ++ GP_0_10_FN, FN_IP1_10_8, ++ GP_0_9_FN, FN_IP1_7_6, ++ GP_0_8_FN, FN_IP1_5_4, ++ GP_0_7_FN, FN_IP1_3_2, ++ GP_0_6_FN, FN_IP1_1_0, ++ GP_0_5_FN, FN_IP0_31_30, ++ GP_0_4_FN, FN_IP0_29_28, ++ GP_0_3_FN, FN_IP0_27_26, ++ GP_0_2_FN, FN_IP0_25, ++ GP_0_1_FN, FN_IP0_24, ++ GP_0_0_FN, FN_IP0_23_22, } ++ }, ++ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_1_25_FN, FN_DACK0, ++ GP_1_24_FN, FN_IP7_31, ++ GP_1_23_FN, FN_IP4_1_0, ++ GP_1_22_FN, FN_WE1_N, ++ GP_1_21_FN, FN_WE0_N, ++ GP_1_20_FN, FN_IP3_31, ++ GP_1_19_FN, FN_IP3_30, ++ GP_1_18_FN, FN_IP3_29_27, ++ GP_1_17_FN, FN_IP3_26_24, ++ GP_1_16_FN, FN_IP3_23_21, ++ GP_1_15_FN, FN_IP3_20_18, ++ GP_1_14_FN, FN_IP3_17_15, ++ GP_1_13_FN, FN_IP3_14_13, ++ GP_1_12_FN, FN_IP3_12, ++ GP_1_11_FN, FN_IP3_11, ++ GP_1_10_FN, FN_IP3_10, ++ GP_1_9_FN, FN_IP3_9_8, ++ GP_1_8_FN, FN_IP3_7_6, ++ GP_1_7_FN, FN_IP3_5_4, ++ GP_1_6_FN, FN_IP3_3_2, ++ GP_1_5_FN, FN_IP3_1_0, ++ GP_1_4_FN, FN_IP2_31_30, ++ GP_1_3_FN, FN_IP2_29_27, ++ GP_1_2_FN, FN_IP2_26_24, ++ GP_1_1_FN, FN_IP2_23_21, ++ GP_1_0_FN, FN_IP2_20_18, } ++ }, ++ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { ++ GP_2_31_FN, FN_IP6_7_6, ++ GP_2_30_FN, FN_IP6_5_4, ++ GP_2_29_FN, FN_IP6_3_2, ++ GP_2_28_FN, FN_IP6_1_0, ++ GP_2_27_FN, FN_IP5_31_30, ++ GP_2_26_FN, FN_IP5_29_28, ++ GP_2_25_FN, FN_IP5_27_26, ++ GP_2_24_FN, FN_IP5_25_24, ++ GP_2_23_FN, FN_IP5_23_22, ++ GP_2_22_FN, FN_IP5_21_20, ++ GP_2_21_FN, FN_IP5_19_18, ++ GP_2_20_FN, FN_IP5_17_16, ++ GP_2_19_FN, FN_IP5_15_14, ++ GP_2_18_FN, FN_IP5_13_12, ++ GP_2_17_FN, FN_IP5_11_9, ++ GP_2_16_FN, FN_IP5_8_6, ++ GP_2_15_FN, FN_IP5_5_4, ++ GP_2_14_FN, FN_IP5_3_2, ++ GP_2_13_FN, FN_IP5_1_0, ++ GP_2_12_FN, FN_IP4_31_30, ++ GP_2_11_FN, FN_IP4_29_28, ++ GP_2_10_FN, FN_IP4_27_26, ++ GP_2_9_FN, FN_IP4_25_23, ++ GP_2_8_FN, FN_IP4_22_20, ++ GP_2_7_FN, FN_IP4_19_18, ++ GP_2_6_FN, FN_IP4_17_16, ++ GP_2_5_FN, FN_IP4_15_14, ++ GP_2_4_FN, FN_IP4_13_12, ++ GP_2_3_FN, FN_IP4_11_10, ++ GP_2_2_FN, FN_IP4_9_8, ++ GP_2_1_FN, FN_IP4_7_5, ++ GP_2_0_FN, FN_IP4_4_2 } ++ }, ++ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { ++ GP_3_31_FN, FN_IP8_22_20, ++ GP_3_30_FN, FN_IP8_19_17, ++ GP_3_29_FN, FN_IP8_16_15, ++ GP_3_28_FN, FN_IP8_14_12, ++ GP_3_27_FN, FN_IP8_11_9, ++ GP_3_26_FN, FN_IP8_8_6, ++ GP_3_25_FN, FN_IP8_5_3, ++ GP_3_24_FN, FN_IP8_2_0, ++ GP_3_23_FN, FN_IP7_29_27, ++ GP_3_22_FN, FN_IP7_26_24, ++ GP_3_21_FN, FN_IP7_23_21, ++ GP_3_20_FN, FN_IP7_20_18, ++ GP_3_19_FN, FN_IP7_17_15, ++ GP_3_18_FN, FN_IP7_14_12, ++ GP_3_17_FN, FN_IP7_11_9, ++ GP_3_16_FN, FN_IP7_8_6, ++ GP_3_15_FN, FN_IP7_5_3, ++ GP_3_14_FN, FN_IP7_2_0, ++ GP_3_13_FN, FN_IP6_31_29, ++ GP_3_12_FN, FN_IP6_28_26, ++ GP_3_11_FN, FN_IP6_25_23, ++ GP_3_10_FN, FN_IP6_22_20, ++ GP_3_9_FN, FN_IP6_19_17, ++ GP_3_8_FN, FN_IP6_16, ++ GP_3_7_FN, FN_IP6_15, ++ GP_3_6_FN, FN_IP6_14, ++ GP_3_5_FN, FN_IP6_13, ++ GP_3_4_FN, FN_IP6_12, ++ GP_3_3_FN, FN_IP6_11, ++ GP_3_2_FN, FN_IP6_10, ++ GP_3_1_FN, FN_IP6_9, ++ GP_3_0_FN, FN_IP6_8 } ++ }, ++ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { ++ GP_4_31_FN, FN_IP11_17_16, ++ GP_4_30_FN, FN_IP11_15_14, ++ GP_4_29_FN, FN_IP11_13_11, ++ GP_4_28_FN, FN_IP11_10_8, ++ GP_4_27_FN, FN_IP11_7_6, ++ GP_4_26_FN, FN_IP11_5_3, ++ GP_4_25_FN, FN_IP11_2_0, ++ GP_4_24_FN, FN_IP10_31_30, ++ GP_4_23_FN, FN_IP10_29_27, ++ GP_4_22_FN, FN_IP10_26_24, ++ GP_4_21_FN, FN_IP10_23_21, ++ GP_4_20_FN, FN_IP10_20_18, ++ GP_4_19_FN, FN_IP10_17_15, ++ GP_4_18_FN, FN_IP10_14_12, ++ GP_4_17_FN, FN_IP10_11_9, ++ GP_4_16_FN, FN_IP10_8_6, ++ GP_4_15_FN, FN_IP10_5_3, ++ GP_4_14_FN, FN_IP10_2_0, ++ GP_4_13_FN, FN_IP9_30_28, ++ GP_4_12_FN, FN_IP9_27_25, ++ GP_4_11_FN, FN_IP9_24_22, ++ GP_4_10_FN, FN_IP9_21_19, ++ GP_4_9_FN, FN_IP9_18_17, ++ GP_4_8_FN, FN_IP9_16_15, ++ GP_4_7_FN, FN_IP9_14_12, ++ GP_4_6_FN, FN_IP9_11_9, ++ GP_4_5_FN, FN_IP9_8_6, ++ GP_4_4_FN, FN_IP9_5_3, ++ GP_4_3_FN, FN_IP9_2_0, ++ GP_4_2_FN, FN_IP8_31_29, ++ GP_4_1_FN, FN_IP8_28_26, ++ GP_4_0_FN, FN_IP8_25_23 } ++ }, ++ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_5_27_FN, FN_USB1_OVC, ++ GP_5_26_FN, FN_USB1_PWEN, ++ GP_5_25_FN, FN_USB0_OVC, ++ GP_5_24_FN, FN_USB0_PWEN, ++ GP_5_23_FN, FN_IP13_26_24, ++ GP_5_22_FN, FN_IP13_23_21, ++ GP_5_21_FN, FN_IP13_20_18, ++ GP_5_20_FN, FN_IP13_17_15, ++ GP_5_19_FN, FN_IP13_14_12, ++ GP_5_18_FN, FN_IP13_11_9, ++ GP_5_17_FN, FN_IP13_8_6, ++ GP_5_16_FN, FN_IP13_5_3, ++ GP_5_15_FN, FN_IP13_2_0, ++ GP_5_14_FN, FN_IP12_29_27, ++ GP_5_13_FN, FN_IP12_26_24, ++ GP_5_12_FN, FN_IP12_23_21, ++ GP_5_11_FN, FN_IP12_20_18, ++ GP_5_10_FN, FN_IP12_17_15, ++ GP_5_9_FN, FN_IP12_14_13, ++ GP_5_8_FN, FN_IP12_12_11, ++ GP_5_7_FN, FN_IP12_10_9, ++ GP_5_6_FN, FN_IP12_8_6, ++ GP_5_5_FN, FN_IP12_5_3, ++ GP_5_4_FN, FN_IP12_2_0, ++ GP_5_3_FN, FN_IP11_29_27, ++ GP_5_2_FN, FN_IP11_26_24, ++ GP_5_1_FN, FN_IP11_23_21, ++ GP_5_0_FN, FN_IP11_20_18 } ++ }, ++ { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_6_25_FN, FN_IP0_21_20, ++ GP_6_24_FN, FN_IP0_19_18, ++ GP_6_23_FN, FN_IP0_17, ++ GP_6_22_FN, FN_IP0_16, ++ GP_6_21_FN, FN_IP0_15, ++ GP_6_20_FN, FN_IP0_14, ++ GP_6_19_FN, FN_IP0_13, ++ GP_6_18_FN, FN_IP0_12, ++ GP_6_17_FN, FN_IP0_11, ++ GP_6_16_FN, FN_IP0_10, ++ GP_6_15_FN, FN_IP0_9_8, ++ GP_6_14_FN, FN_IP0_0, ++ GP_6_13_FN, FN_SD1_DATA3, ++ GP_6_12_FN, FN_SD1_DATA2, ++ GP_6_11_FN, FN_SD1_DATA1, ++ GP_6_10_FN, FN_SD1_DATA0, ++ GP_6_9_FN, FN_SD1_CMD, ++ GP_6_8_FN, FN_SD1_CLK, ++ GP_6_7_FN, FN_SD0_WP, ++ GP_6_6_FN, FN_SD0_CD, ++ GP_6_5_FN, FN_SD0_DATA3, ++ GP_6_4_FN, FN_SD0_DATA2, ++ GP_6_3_FN, FN_SD0_DATA1, ++ GP_6_2_FN, FN_SD0_DATA0, ++ GP_6_1_FN, FN_SD0_CMD, ++ GP_6_0_FN, FN_SD0_CLK } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, ++ 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, ++ 2, 1, 1, 1, 1, 1, 1, 1, 1) { ++ /* IP0_31_30 [2] */ ++ FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, ++ /* IP0_29_28 [2] */ ++ FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0, ++ /* IP0_27_26 [2] */ ++ FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0, ++ /* IP0_25 [1] */ ++ FN_D2, FN_SCIFA3_TXD_B, ++ /* IP0_24 [1] */ ++ FN_D1, FN_SCIFA3_RXD_B, ++ /* IP0_23_22 [2] */ ++ FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0, ++ /* IP0_21_20 [2] */ ++ FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX, ++ /* IP0_19_18 [2] */ ++ FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX, ++ /* IP0_17 [1] */ ++ FN_MMC_D5, FN_SD2_WP, ++ /* IP0_16 [1] */ ++ FN_MMC_D4, FN_SD2_CD, ++ /* IP0_15 [1] */ ++ FN_MMC_D3, FN_SD2_DATA3, ++ /* IP0_14 [1] */ ++ FN_MMC_D2, FN_SD2_DATA2, ++ /* IP0_13 [1] */ ++ FN_MMC_D1, FN_SD2_DATA1, ++ /* IP0_12 [1] */ ++ FN_MMC_D0, FN_SD2_DATA0, ++ /* IP0_11 [1] */ ++ FN_MMC_CMD, FN_SD2_CMD, ++ /* IP0_10 [1] */ ++ FN_MMC_CLK, FN_SD2_CLK, ++ /* IP0_9_8 [2] */ ++ FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0, ++ /* IP0_7 [1] */ ++ 0, 0, ++ /* IP0_6 [1] */ ++ 0, 0, ++ /* IP0_5 [1] */ ++ 0, 0, ++ /* IP0_4 [1] */ ++ 0, 0, ++ /* IP0_3 [1] */ ++ 0, 0, ++ /* IP0_2 [1] */ ++ 0, 0, ++ /* IP0_1 [1] */ ++ 0, 0, ++ /* IP0_0 [1] */ ++ FN_SD1_CD, FN_CAN0_RX, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, ++ 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2, ++ 2, 2) { ++ /* IP1_31_30 [2] */ ++ FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, ++ /* IP1_29_28 [2] */ ++ FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, ++ /* IP1_27 [1] */ ++ FN_A4, FN_SCIFB0_TXD, ++ /* IP1_26 [1] */ ++ FN_A3, FN_SCIFB0_SCK, ++ /* IP1_25 [1] */ ++ 0, 0, ++ /* IP1_24 [1] */ ++ FN_A1, FN_SCIFB1_TXD, ++ /* IP1_23_22 [2] */ ++ FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0, ++ /* IP1_21_20 [2] */ ++ FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, 0, ++ /* IP1_19_18 [2] */ ++ FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B, 0, ++ /* IP1_17_15 [3] */ ++ FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, ++ 0, 0, 0, ++ /* IP1_14_13 [2] */ ++ FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, ++ /* IP1_12_11 [2] */ ++ FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, ++ /* IP1_10_8 [3] */ ++ FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, ++ 0, 0, 0, ++ /* IP1_7_6 [2] */ ++ FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0, ++ /* IP1_5_4 [2] */ ++ FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0, ++ /* IP1_3_2 [2] */ ++ FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, ++ /* IP1_1_0 [2] */ ++ FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, ++ 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) { ++ /* IP2_31_30 [2] */ ++ FN_A20, FN_SPCLK, FN_MOUT1, 0, ++ /* IP2_29_27 [3] */ ++ FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, ++ FN_MOUT0, 0, 0, 0, ++ /* IP2_26_24 [3] */ ++ FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B, ++ FN_AVB_AVTP_MATCH_B, 0, 0, 0, ++ /* IP2_23_21 [3] */ ++ FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, ++ FN_AVB_AVTP_CAPTURE_B, 0, 0, 0, ++ /* IP2_20_18 [3] */ ++ FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, ++ FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0, ++ /* IP2_17_16 [2] */ ++ FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, ++ /* IP2_15_14 [2] */ ++ FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, ++ /* IP2_13_12 [2] */ ++ FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0, ++ /* IP2_11_10 [2] */ ++ FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0, ++ /* IP2_9_8 [2] */ ++ FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, 0, ++ /* IP2_7_6 [2] */ ++ FN_A10, FN_MSIOF1_SCK, FN_IIC1_SCL_B, 0, ++ /* IP2_5_4 [2] */ ++ FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0, ++ /* IP2_3_2 [2] */ ++ FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0, ++ /* IP2_1_0 [2] */ ++ FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, ++ 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) { ++ /* IP3_31 [1] */ ++ FN_RD_WR_N, FN_ATAG1_N, ++ /* IP3_30 [1] */ ++ FN_RD_N, FN_ATACS11_N, ++ /* IP3_29_27 [3] */ ++ FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, ++ FN_MTS_N_B, 0, 0, ++ /* IP3_26_24 [3] */ ++ FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, ++ FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B, ++ /* IP3_23_21 [3] */ ++ FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, ++ FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B, ++ /* IP3_20_18 [3] */ ++ FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, ++ FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, ++ /* IP3_17_15 [3] */ ++ FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, ++ FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B, ++ /* IP3_14_13 [2] */ ++ FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, ++ /* IP3_12 [1] */ ++ FN_EX_CS0_N, FN_VI1_DATA10, ++ /* IP3_11 [1] */ ++ FN_CS1_N_A26, FN_VI1_DATA9, ++ /* IP3_10 [1] */ ++ FN_CS0_N, FN_VI1_DATA8, ++ /* IP3_9_8 [2] */ ++ FN_A25, FN_SSL, FN_ATARD1_N, 0, ++ /* IP3_7_6 [2] */ ++ FN_A24, FN_IO3, FN_EX_WAIT2, 0, ++ /* IP3_5_4 [2] */ ++ FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, ++ /* IP3_3_2 [2] */ ++ FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N, ++ /* IP3_1_0 [2] */ ++ FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, ++ 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) { ++ /* IP4_31_30 [2] */ ++ FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0, ++ /* IP4_29_28 [2] */ ++ FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0, ++ /* IP4_27_26 [2] */ ++ FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0, ++ /* IP4_25_23 [3] */ ++ FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, ++ FN_CC50_STATE9, 0, 0, 0, ++ /* IP4_22_20 [3] */ ++ FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, ++ FN_CC50_STATE8, 0, 0, 0, ++ /* IP4_19_18 [2] */ ++ FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0, ++ /* IP4_17_16 [2] */ ++ FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0, ++ /* IP4_15_14 [2] */ ++ FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0, ++ /* IP4_13_12 [2] */ ++ FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0, ++ /* IP4_11_10 [2] */ ++ FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0, ++ /* IP4_9_8 [2] */ ++ FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0, ++ /* IP4_7_5 [3] */ ++ FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, ++ FN_CC50_STATE1, 0, 0, 0, ++ /* IP4_4_2 [3] */ ++ FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, ++ FN_CC50_STATE0, 0, 0, 0, ++ /* IP4_1_0 [2] */ ++ FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, ++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) { ++ /* IP5_31_30 [2] */ ++ FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0, ++ /* IP5_29_28 [2] */ ++ FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0, ++ /* IP5_27_26 [2] */ ++ FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0, ++ /* IP5_25_24 [2] */ ++ FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0, ++ /* IP5_23_22 [2] */ ++ FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0, ++ /* IP5_21_20 [2] */ ++ FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0, ++ /* IP5_19_18 [2] */ ++ FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0, ++ /* IP5_17_16 [2] */ ++ FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0, ++ /* IP5_15_14 [2] */ ++ FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0, ++ /* IP5_13_12 [2] */ ++ FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0, ++ /* IP5_11_9 [3] */ ++ FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, ++ FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0, ++ /* IP5_8_6 [3] */ ++ FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, ++ FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0, ++ /* IP5_5_4 [2] */ ++ FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0, ++ /* IP5_3_2 [2] */ ++ FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0, ++ /* IP5_1_0 [2] */ ++ FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, ++ 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, ++ 2, 2) { ++ /* IP6_31_29 [3] */ ++ FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, ++ FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0, ++ /* IP6_28_26 [3] */ ++ FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, ++ FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0, ++ /* IP6_25_23 [3] */ ++ FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, ++ FN_AVB_COL, 0, 0, 0, ++ /* IP6_22_20 [3] */ ++ FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, ++ FN_AVB_RX_ER, 0, 0, 0, ++ /* IP6_19_17 [3] */ ++ FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, ++ FN_AVB_RXD7, 0, 0, 0, ++ /* IP6_16 [1] */ ++ FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, ++ /* IP6_15 [1] */ ++ FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, ++ /* IP6_14 [1] */ ++ FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, ++ /* IP6_13 [1] */ ++ FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, ++ /* IP6_12 [1] */ ++ FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, ++ /* IP6_11 [1] */ ++ FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, ++ /* IP6_10 [1] */ ++ FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, ++ /* IP6_9 [1] */ ++ FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, ++ /* IP6_8 [1] */ ++ FN_VI0_CLK, FN_AVB_RX_CLK, ++ /* IP6_7_6 [2] */ ++ FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0, ++ /* IP6_5_4 [2] */ ++ FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0, ++ /* IP6_3_2 [2] */ ++ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, ++ /* IP6_1_0 [2] */ ++ FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, ++ 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { ++ /* IP7_31 [1] */ ++ FN_DREQ0_N, FN_SCIFB1_RXD, ++ /* IP7_30 [1] */ ++ 0, 0, ++ /* IP7_29_27 [3] */ ++ FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, ++ FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0, ++ /* IP7_26_24 [3] */ ++ FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, ++ FN_SSI_SCK6_B, 0, 0, 0, ++ /* IP7_23_21 [3] */ ++ FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D, ++ FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0, ++ /* IP7_20_18 [3] */ ++ FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D, ++ FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0, ++ /* IP7_17_15 [3] */ ++ FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, ++ FN_SSI_SCK5_B, 0, 0, 0, ++ /* IP7_14_12 [3] */ ++ FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, ++ FN_AVB_TXD4, FN_ADICHS2, 0, 0, ++ /* IP7_11_9 [3] */ ++ FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, ++ FN_AVB_TXD3, FN_ADICHS1, 0, 0, ++ /* IP7_8_6 [3] */ ++ FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, ++ FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0, ++ /* IP7_5_3 [3] */ ++ FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, ++ FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0, ++ /* IP7_2_0 [3] */ ++ FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, ++ FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, ++ 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { ++ /* IP8_31_29 [3] */ ++ FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, ++ FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, ++ /* IP8_28_26 [3] */ ++ FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, ++ FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0, ++ /* IP8_25_23 [3] */ ++ FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, ++ FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0, ++ /* IP8_22_20 [3] */ ++ FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, ++ FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0, ++ /* IP8_19_17 [3] */ ++ FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, ++ FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0, ++ /* IP8_16_15 [2] */ ++ FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, ++ /* IP8_14_12 [3] */ ++ FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, ++ FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0, ++ /* IP8_11_9 [3] */ ++ FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, ++ FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0, ++ /* IP8_8_6 [3] */ ++ FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, ++ FN_AVB_LINK, FN_SSI_WS78_B, 0, 0, ++ /* IP8_5_3 [3] */ ++ FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, ++ FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, ++ /* IP8_2_0 [3] */ ++ FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, ++ FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, ++ 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) { ++ /* IP9_31 [1] */ ++ 0, 0, ++ /* IP9_30_28 [3] */ ++ FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, ++ FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0, ++ /* IP9_27_25 [3] */ ++ FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, ++ FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0, ++ /* IP9_24_22 [3] */ ++ FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, ++ FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0, ++ /* IP9_21_19 [3] */ ++ FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, ++ FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0, ++ /* IP9_18_17 [2] */ ++ FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, ++ /* IP9_16_15 [2] */ ++ FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, ++ /* IP9_14_12 [3] */ ++ FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, ++ FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0, ++ /* IP9_11_9 [3] */ ++ FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, ++ FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0, ++ /* IP9_8_6 [3] */ ++ FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, ++ FN_RIF1_CLK, FN_BPFCLK_B, 0, 0, ++ /* IP9_5_3 [3] */ ++ FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, ++ FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0, ++ /* IP9_2_0 [3] */ ++ FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, ++ FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, ++ 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { ++ /* IP10_31_30 [2] */ ++ FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10, ++ /* IP10_29_27 [3] */ ++ FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, ++ FN_CAN_DEBUGOUT9, 0, 0, 0, ++ /* IP10_26_24 [3] */ ++ FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C, ++ FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0, ++ /* IP10_23_21 [3] */ ++ FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, ++ FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, ++ /* IP10_20_18 [3] */ ++ FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, ++ FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, ++ /* IP10_17_15 [3] */ ++ FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, ++ FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT, ++ /* IP10_14_12 [3] */ ++ FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B, ++ FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0, ++ /* IP10_11_9 [3] */ ++ FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, ++ FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0, ++ /* IP10_8_6 [3] */ ++ FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, ++ FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0, ++ /* IP10_5_3 [3] */ ++ FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B, ++ FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0, ++ /* IP10_2_0 [3] */ ++ FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, ++ FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, ++ 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { ++ /* IP11_31_30 [2] */ ++ 0, 0, 0, 0, ++ /* IP11_29_27 [3] */ ++ FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, ++ FN_AD_CLK_B, 0, 0, 0, ++ /* IP11_26_24 [3] */ ++ FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, ++ FN_AD_DO_B, 0, 0, 0, ++ /* IP11_23_21 [3] */ ++ FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, ++ FN_AD_DI_B, FN_PCMWE_N, 0, 0, ++ /* IP11_20_18 [3] */ ++ FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, ++ FN_CAN_CLK_D, FN_PCMOE_N, 0, 0, ++ /* IP11_17_16 [2] */ ++ FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, ++ /* IP11_15_14 [2] */ ++ FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, ++ /* IP11_13_11 [3] */ ++ FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, ++ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0, ++ /* IP11_10_8 [3] */ ++ FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, ++ FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0, ++ /* IP11_7_6 [2] */ ++ FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, ++ FN_CAN_DEBUGOUT13, ++ /* IP11_5_3 [3] */ ++ FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, ++ FN_CAN_DEBUGOUT12, 0, 0, 0, ++ /* IP11_2_0 [3] */ ++ FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, ++ FN_CAN_DEBUGOUT11, 0, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, ++ 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) { ++ /* IP12_31_30 [2] */ ++ 0, 0, 0, 0, ++ /* IP12_29_27 [3] */ ++ FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA, ++ FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0, ++ /* IP12_26_24 [3] */ ++ FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA, ++ FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0, ++ /* IP12_23_21 [3] */ ++ FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0, ++ FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0, ++ /* IP12_20_18 [3] */ ++ FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, ++ FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0, ++ /* IP12_17_15 [3] */ ++ FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, ++ FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0, ++ /* IP12_14_13 [2] */ ++ FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK, ++ /* IP12_12_11 [2] */ ++ FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, ++ /* IP12_10_9 [2] */ ++ FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, ++ /* IP12_8_6 [3] */ ++ FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, ++ FN_CAN1_TX_C, FN_DREQ2_N, 0, 0, ++ /* IP12_5_3 [3] */ ++ FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B, ++ FN_CAN1_RX_C, FN_DACK1_B, 0, 0, ++ /* IP12_2_0 [3] */ ++ FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, ++ FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, ++ 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) { ++ /* IP13_31 [1] */ ++ 0, 0, ++ /* IP13_30 [1] */ ++ 0, 0, ++ /* IP13_29 [1] */ ++ 0, 0, ++ /* IP13_28 [1] */ ++ 0, 0, ++ /* IP13_27 [1] */ ++ 0, 0, ++ /* IP13_26_24 [3] */ ++ FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, ++ FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D, ++ /* IP13_23_21 [3] */ ++ FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, ++ FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, ++ /* IP13_20_18 [3] */ ++ FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, ++ FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, ++ /* IP13_17_15 [3] */ ++ FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB, ++ FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0, ++ /* IP13_14_12 [3] */ ++ FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, ++ FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0, ++ /* IP13_11_9 [3] */ ++ FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, ++ FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0, ++ /* IP13_8_6 [3] */ ++ FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, ++ FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0, ++ /* IP13_5_3 [2] */ ++ FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, ++ FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, ++ /* IP13_2_0 [3] */ ++ FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, ++ FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, } ++ }, ++ { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, ++ 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, ++ 2, 1) { ++ /* SEL_ADG [2] */ ++ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, ++ /* SEL_ADI [1] */ ++ FN_SEL_ADI_0, FN_SEL_ADI_1, ++ /* SEL_CAN [2] */ ++ FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, ++ /* SEL_DARC [3] */ ++ FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, ++ FN_SEL_DARC_4, 0, 0, 0, ++ /* SEL_DR0 [1] */ ++ FN_SEL_DR0_0, FN_SEL_DR0_1, ++ /* SEL_DR1 [1] */ ++ FN_SEL_DR1_0, FN_SEL_DR1_1, ++ /* SEL_DR2 [1] */ ++ FN_SEL_DR2_0, FN_SEL_DR2_1, ++ /* SEL_DR3 [1] */ ++ FN_SEL_DR3_0, FN_SEL_DR3_1, ++ /* SEL_ETH [1] */ ++ FN_SEL_ETH_0, FN_SEL_ETH_1, ++ /* SLE_FSN [1] */ ++ FN_SEL_FSN_0, FN_SEL_FSN_1, ++ /* SEL_IC200 [3] */ ++ FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, ++ FN_SEL_I2C00_4, 0, 0, 0, ++ /* SEL_I2C01 [3] */ ++ FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, ++ FN_SEL_I2C01_4, 0, 0, 0, ++ /* SEL_I2C02 [3] */ ++ FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, ++ FN_SEL_I2C02_4, 0, 0, 0, ++ /* SEL_I2C03 [3] */ ++ FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, ++ FN_SEL_I2C03_4, 0, 0, 0, ++ /* SEL_I2C04 [3] */ ++ FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, ++ FN_SEL_I2C04_4, 0, 0, 0, ++ /* SEL_IIC00 [2] */ ++ FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3, ++ /* SEL_AVB [1] */ ++ FN_SEL_AVB_0, FN_SEL_AVB_1, } ++ }, ++ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, ++ 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, ++ 2, 2, 2, 1, 1, 2) { ++ /* SEL_IEB [2] */ ++ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, ++ /* SEL_IIC0 [2] */ ++ FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, ++ /* SEL_LBS [1] */ ++ FN_SEL_LBS_0, FN_SEL_LBS_1, ++ /* SEL_MSI1 [1] */ ++ FN_SEL_MSI1_0, FN_SEL_MSI1_1, ++ /* SEL_MSI2 [1] */ ++ FN_SEL_MSI2_0, FN_SEL_MSI2_1, ++ /* SEL_RAD [1] */ ++ FN_SEL_RAD_0, FN_SEL_RAD_1, ++ /* SEL_RCN [1] */ ++ FN_SEL_RCN_0, FN_SEL_RCN_1, ++ /* SEL_RSP [1] */ ++ FN_SEL_RSP_0, FN_SEL_RSP_1, ++ /* SEL_SCIFA0 [2] */ ++ FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, ++ FN_SEL_SCIFA0_3, ++ /* SEL_SCIFA1 [2] */ ++ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, ++ /* SEL_SCIFA2 [1] */ ++ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, ++ /* SEL_SCIFA3 [1] */ ++ FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, ++ /* SEL_SCIFA4 [2] */ ++ FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, ++ FN_SEL_SCIFA4_3, ++ /* SEL_SCIFA5 [2] */ ++ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, ++ FN_SEL_SCIFA5_3, ++ /* SEL_SPDM [1] */ ++ FN_SEL_SPDM_0, FN_SEL_SPDM_1, ++ /* SEL_TMU [1] */ ++ FN_SEL_TMU_0, FN_SEL_TMU_1, ++ /* SEL_TSIF0 [2] */ ++ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, ++ /* SEL_CAN0 [2] */ ++ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, ++ /* SEL_CAN1 [2] */ ++ FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, ++ /* SEL_HSCIF0 [1] */ ++ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ++ /* SEL_HSCIF1 [1] */ ++ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, ++ /* SEL_RDS [2] */ ++ FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, } ++ }, ++ { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, ++ 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { ++ /* SEL_SCIF0 [2] */ ++ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, ++ /* SEL_SCIF1 [2] */ ++ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, ++ /* SEL_SCIF2 [2] */ ++ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0, ++ /* SEL_SCIF3 [1] */ ++ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, ++ /* SEL_SCIF4 [3] */ ++ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, ++ FN_SEL_SCIF4_4, 0, 0, 0, ++ /* SEL_SCIF5 [2] */ ++ FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, ++ /* SEL_SSI1 [1] */ ++ FN_SEL_SSI1_0, FN_SEL_SSI1_1, ++ /* SEL_SSI2 [1] */ ++ FN_SEL_SSI2_0, FN_SEL_SSI2_1, ++ /* SEL_SSI4 [1] */ ++ FN_SEL_SSI4_0, FN_SEL_SSI4_1, ++ /* SEL_SSI5 [1] */ ++ FN_SEL_SSI5_0, FN_SEL_SSI5_1, ++ /* SEL_SSI6 [1] */ ++ FN_SEL_SSI6_0, FN_SEL_SSI6_1, ++ /* SEL_SSI7 [1] */ ++ FN_SEL_SSI7_0, FN_SEL_SSI7_1, ++ /* SEL_SSI8 [1] */ ++ FN_SEL_SSI8_0, FN_SEL_SSI8_1, ++ /* SEL_SSI9 [1] */ ++ FN_SEL_SSI9_0, FN_SEL_SSI9_1, ++ /* RESERVED [1] */ ++ 0, 0, ++ /* RESERVED [1] */ ++ 0, 0, ++ /* RESERVED [1] */ ++ 0, 0, ++ /* RESERVED [1] */ ++ 0, 0, ++ /* RESERVED [1] */ ++ 0, 0, ++ /* RESERVED [1] */ ++ 0, 0, ++ /* RESERVED [1] */ ++ 0, 0, ++ /* RESERVED [1] */ ++ 0, 0, ++ /* RESERVED [1] */ ++ 0, 0, ++ /* RESERVED [1] */ ++ 0, 0, ++ /* RESERVED [1] */ ++ 0, 0, ++ /* RESERVED [1] */ ++ 0, 0, } ++ }, ++ { }, ++}; ++ ++const struct sh_pfc_soc_info r8a7794_pinmux_info = { ++ .name = "r8a77940_pfc", ++ .unlock_reg = 0xe6060000, /* PMMR */ ++ ++ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, ++ ++ .pins = pinmux_pins, ++ .nr_pins = ARRAY_SIZE(pinmux_pins), ++ .groups = pinmux_groups, ++ .nr_groups = ARRAY_SIZE(pinmux_groups), ++ .functions = pinmux_functions, ++ .nr_functions = ARRAY_SIZE(pinmux_functions), ++ ++ .cfg_regs = pinmux_config_regs, ++ ++ .gpio_data = pinmux_data, ++ .gpio_data_size = ARRAY_SIZE(pinmux_data), ++}; +-- +2.6.2 + diff --git a/patches.renesas/0247-pinctrl-sh-pfc-r8a7794-add-MMCIF-pin-groups.patch b/patches.renesas/0247-pinctrl-sh-pfc-r8a7794-add-MMCIF-pin-groups.patch new file mode 100644 index 00000000000000..d89bb834546865 --- /dev/null +++ b/patches.renesas/0247-pinctrl-sh-pfc-r8a7794-add-MMCIF-pin-groups.patch @@ -0,0 +1,100 @@ +From afc12d8a8d3d452212d13bb4f6d47a3033b37901 Mon Sep 17 00:00:00 2001 +From: Shinobu Uehara <shinobu.uehara.xc@renesas.com> +Date: Sat, 6 Jun 2015 01:35:54 +0300 +Subject: [PATCH 247/326] pinctrl: sh-pfc: r8a7794: add MMCIF pin groups + +Add MMCIF pin groups to R8A7794 PFC driver. + +Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> +[Sergei: rebased, renamed, added changelog.] +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> + +(cherry picked from commit f1f74b640c952e311aebaa594d9d81fecb72cc17) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 46 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +index 0e2686a2093c..4679ca01f976 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +@@ -1919,6 +1919,40 @@ static const unsigned int intc_irq9_pins[] = { + static const unsigned int intc_irq9_mux[] = { + IRQ9_MARK, + }; ++/* - MMCIF ------------------------------------------------------------------ */ ++static const unsigned int mmc_data1_pins[] = { ++ /* D[0] */ ++ RCAR_GP_PIN(6, 18), ++}; ++static const unsigned int mmc_data1_mux[] = { ++ MMC_D0_MARK, ++}; ++static const unsigned int mmc_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), ++ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int mmc_data4_mux[] = { ++ MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, ++}; ++static const unsigned int mmc_data8_pins[] = { ++ /* D[0:7] */ ++ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), ++ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), ++ RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), ++ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), ++}; ++static const unsigned int mmc_data8_mux[] = { ++ MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, ++ MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, ++}; ++static const unsigned int mmc_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), ++}; ++static const unsigned int mmc_ctrl_mux[] = { ++ MMC_CLK_MARK, MMC_CMD_MARK, ++}; + /* - MSIOF0 ----------------------------------------------------------------- */ + static const unsigned int msiof0_clk_pins[] = { + /* SCK */ +@@ -2683,6 +2717,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(intc_irq7), + SH_PFC_PIN_GROUP(intc_irq8), + SH_PFC_PIN_GROUP(intc_irq9), ++ SH_PFC_PIN_GROUP(mmc_data1), ++ SH_PFC_PIN_GROUP(mmc_data4), ++ SH_PFC_PIN_GROUP(mmc_data8), ++ SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), +@@ -2869,6 +2907,13 @@ static const char * const intc_groups[] = { + "intc_irq9", + }; + ++static const char * const mmc_groups[] = { ++ "mmc_data1", ++ "mmc_data4", ++ "mmc_data8", ++ "mmc_ctrl", ++}; ++ + static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", +@@ -3035,6 +3080,7 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(intc), ++ SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), +-- +2.6.2 + diff --git a/patches.renesas/0248-pinctrl-sh-pfc-r8a7794-add-SDHI-pin-groups.patch b/patches.renesas/0248-pinctrl-sh-pfc-r8a7794-add-SDHI-pin-groups.patch new file mode 100644 index 00000000000000..99c1f14dade28e --- /dev/null +++ b/patches.renesas/0248-pinctrl-sh-pfc-r8a7794-add-SDHI-pin-groups.patch @@ -0,0 +1,208 @@ +From 05fe9248049638e329bf3a7c929baf992126b1fd Mon Sep 17 00:00:00 2001 +From: Shinobu Uehara <shinobu.uehara.xc@renesas.com> +Date: Sat, 6 Jun 2015 01:36:50 +0300 +Subject: [PATCH 248/326] pinctrl: sh-pfc: r8a7794: add SDHI pin groups + +Add SDHI0/1/2 pin groups to R8A7794 PFC driver. + +Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> +[Sergei: renamed SD data pins to match the driver, rebased, renamed, added +changelog.] +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> + +(cherry picked from commit 7ac91bda80a05122ca86240b1da3a68a4cdaa982) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 153 +++++++++++++++++++++++++++++++++++ + 1 file changed, 153 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +index 4679ca01f976..bfdcac4b3bc4 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +@@ -2659,6 +2659,117 @@ static const unsigned int scifb2_ctrl_pins[] = { + static const unsigned int scifb2_ctrl_mux[] = { + SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, + }; ++/* - SDHI0 ------------------------------------------------------------------ */ ++static const unsigned int sdhi0_data1_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(6, 2), ++}; ++static const unsigned int sdhi0_data1_mux[] = { ++ SD0_DATA0_MARK, ++}; ++static const unsigned int sdhi0_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), ++ RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), ++}; ++static const unsigned int sdhi0_data4_mux[] = { ++ SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, ++}; ++static const unsigned int sdhi0_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), ++}; ++static const unsigned int sdhi0_ctrl_mux[] = { ++ SD0_CLK_MARK, SD0_CMD_MARK, ++}; ++static const unsigned int sdhi0_cd_pins[] = { ++ /* CD */ ++ RCAR_GP_PIN(6, 6), ++}; ++static const unsigned int sdhi0_cd_mux[] = { ++ SD0_CD_MARK, ++}; ++static const unsigned int sdhi0_wp_pins[] = { ++ /* WP */ ++ RCAR_GP_PIN(6, 7), ++}; ++static const unsigned int sdhi0_wp_mux[] = { ++ SD0_WP_MARK, ++}; ++/* - SDHI1 ------------------------------------------------------------------ */ ++static const unsigned int sdhi1_data1_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(6, 10), ++}; ++static const unsigned int sdhi1_data1_mux[] = { ++ SD1_DATA0_MARK, ++}; ++static const unsigned int sdhi1_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), ++ RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), ++}; ++static const unsigned int sdhi1_data4_mux[] = { ++ SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, ++}; ++static const unsigned int sdhi1_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), ++}; ++static const unsigned int sdhi1_ctrl_mux[] = { ++ SD1_CLK_MARK, SD1_CMD_MARK, ++}; ++static const unsigned int sdhi1_cd_pins[] = { ++ /* CD */ ++ RCAR_GP_PIN(6, 14), ++}; ++static const unsigned int sdhi1_cd_mux[] = { ++ SD1_CD_MARK, ++}; ++static const unsigned int sdhi1_wp_pins[] = { ++ /* WP */ ++ RCAR_GP_PIN(6, 15), ++}; ++static const unsigned int sdhi1_wp_mux[] = { ++ SD1_WP_MARK, ++}; ++/* - SDHI2 ------------------------------------------------------------------ */ ++static const unsigned int sdhi2_data1_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(6, 18), ++}; ++static const unsigned int sdhi2_data1_mux[] = { ++ SD2_DATA0_MARK, ++}; ++static const unsigned int sdhi2_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), ++ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int sdhi2_data4_mux[] = { ++ SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, ++}; ++static const unsigned int sdhi2_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), ++}; ++static const unsigned int sdhi2_ctrl_mux[] = { ++ SD2_CLK_MARK, SD2_CMD_MARK, ++}; ++static const unsigned int sdhi2_cd_pins[] = { ++ /* CD */ ++ RCAR_GP_PIN(6, 22), ++}; ++static const unsigned int sdhi2_cd_mux[] = { ++ SD2_CD_MARK, ++}; ++static const unsigned int sdhi2_wp_pins[] = { ++ /* WP */ ++ RCAR_GP_PIN(6, 23), ++}; ++static const unsigned int sdhi2_wp_mux[] = { ++ SD2_WP_MARK, ++}; + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), +@@ -2819,6 +2930,21 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), ++ SH_PFC_PIN_GROUP(sdhi0_data1), ++ SH_PFC_PIN_GROUP(sdhi0_data4), ++ SH_PFC_PIN_GROUP(sdhi0_ctrl), ++ SH_PFC_PIN_GROUP(sdhi0_cd), ++ SH_PFC_PIN_GROUP(sdhi0_wp), ++ SH_PFC_PIN_GROUP(sdhi1_data1), ++ SH_PFC_PIN_GROUP(sdhi1_data4), ++ SH_PFC_PIN_GROUP(sdhi1_ctrl), ++ SH_PFC_PIN_GROUP(sdhi1_cd), ++ SH_PFC_PIN_GROUP(sdhi1_wp), ++ SH_PFC_PIN_GROUP(sdhi2_data1), ++ SH_PFC_PIN_GROUP(sdhi2_data4), ++ SH_PFC_PIN_GROUP(sdhi2_ctrl), ++ SH_PFC_PIN_GROUP(sdhi2_cd), ++ SH_PFC_PIN_GROUP(sdhi2_wp), + }; + + static const char * const eth_groups[] = { +@@ -3069,6 +3195,30 @@ static const char * const scifb2_groups[] = { + "scifb2_ctrl", + }; + ++static const char * const sdhi0_groups[] = { ++ "sdhi0_data1", ++ "sdhi0_data4", ++ "sdhi0_ctrl", ++ "sdhi0_cd", ++ "sdhi0_wp", ++}; ++ ++static const char * const sdhi1_groups[] = { ++ "sdhi1_data1", ++ "sdhi1_data4", ++ "sdhi1_ctrl", ++ "sdhi1_cd", ++ "sdhi1_wp", ++}; ++ ++static const char * const sdhi2_groups[] = { ++ "sdhi2_data1", ++ "sdhi2_data4", ++ "sdhi2_ctrl", ++ "sdhi2_cd", ++ "sdhi2_wp", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), +@@ -3100,6 +3250,9 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), ++ SH_PFC_FUNCTION(sdhi0), ++ SH_PFC_FUNCTION(sdhi1), ++ SH_PFC_FUNCTION(sdhi2), + }; + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +2.6.2 + diff --git a/patches.renesas/0249-sh-pfc-r8a7790-remove-non-existing-GPIO-pins.patch b/patches.renesas/0249-sh-pfc-r8a7790-remove-non-existing-GPIO-pins.patch new file mode 100644 index 00000000000000..958b18155a72ba --- /dev/null +++ b/patches.renesas/0249-sh-pfc-r8a7790-remove-non-existing-GPIO-pins.patch @@ -0,0 +1,53 @@ +From 0a137085a31097b4a7991c8e6b114117600f9e20 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 26 Jun 2015 01:42:04 +0300 +Subject: [PATCH 249/326] sh-pfc: r8a7790: remove non-existing GPIO pins + +GPIO banks 1 and 2 are missing pins 30 and 31. Remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit b5599df20f1ee45cef811a7ab1c7358d9faf7bf8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 21 +++++++++++++++++++-- + 1 file changed, 19 insertions(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +index baab81ead9ff..fc344a7c2b53 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +@@ -27,10 +27,27 @@ + #include "core.h" + #include "sh_pfc.h" + ++#define PORT_GP_30(bank, fn, sfx) \ ++ PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ ++ PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ ++ PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ ++ PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ ++ PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ ++ PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ ++ PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ ++ PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ ++ PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ ++ PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ ++ PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ ++ PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ ++ PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ ++ PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ ++ PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx) ++ + #define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ +- PORT_GP_32(1, fn, sfx), \ +- PORT_GP_32(2, fn, sfx), \ ++ PORT_GP_30(1, fn, sfx), \ ++ PORT_GP_30(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_32(5, fn, sfx) +-- +2.6.2 + diff --git a/patches.renesas/0250-sh-pfc-r8a7791-remove-non-existing-GPIO-pins.patch b/patches.renesas/0250-sh-pfc-r8a7791-remove-non-existing-GPIO-pins.patch new file mode 100644 index 00000000000000..6514008af7fcbb --- /dev/null +++ b/patches.renesas/0250-sh-pfc-r8a7791-remove-non-existing-GPIO-pins.patch @@ -0,0 +1,57 @@ +From 765c8732dd68dbdbf43b67f548c769ce213f1abb Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 26 Jun 2015 01:43:07 +0300 +Subject: [PATCH 250/326] sh-pfc: r8a7791: remove non-existing GPIO pins + +GPIO banks 1 and 7 are missing pins 26 to 31. Remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 441f77dcf8defcebb4477fea6db03624259fef42) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 19 +++++++++++++++++-- + 1 file changed, 17 insertions(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +index 3ddf23ec9f0b..25e8117f5a1a 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -14,15 +14,30 @@ + #include "core.h" + #include "sh_pfc.h" + ++#define PORT_GP_26(bank, fn, sfx) \ ++ PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ ++ PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ ++ PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ ++ PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ ++ PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ ++ PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ ++ PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ ++ PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ ++ PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ ++ PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ ++ PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ ++ PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ ++ PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) ++ + #define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ +- PORT_GP_32(1, fn, sfx), \ ++ PORT_GP_26(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_32(5, fn, sfx), \ + PORT_GP_32(6, fn, sfx), \ +- PORT_GP_32(7, fn, sfx) ++ PORT_GP_26(7, fn, sfx) + + enum { + PINMUX_RESERVED = 0, +-- +2.6.2 + diff --git a/patches.renesas/0251-pinctrl-sh-pfc-Accept-standard-function-pins-and-gro.patch b/patches.renesas/0251-pinctrl-sh-pfc-Accept-standard-function-pins-and-gro.patch new file mode 100644 index 00000000000000..5d10442caaa69d --- /dev/null +++ b/patches.renesas/0251-pinctrl-sh-pfc-Accept-standard-function-pins-and-gro.patch @@ -0,0 +1,188 @@ +From 5e438426ea20f62967e4c63343d4f332e0bb6429 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 30 Jun 2015 11:29:57 +0300 +Subject: [PATCH 251/326] pinctrl: sh-pfc: Accept standard function, pins and + groups properties + +The "function", "pins" and "groups" pinmux and pinctrl properties have +been standardized. Support them in addition to the custom "renesas,*" +properties. New-style and old-style properties can't be mixed in DT. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 16ccaf5bb5a52372bfebd3dfbb79dd810ad49c09) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 20 +++++------ + drivers/pinctrl/sh-pfc/pinctrl.c | 42 +++++++++++++++++----- + 2 files changed, 44 insertions(+), 18 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +index 51cee44fc140..e089142cfb14 100644 +--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +@@ -58,12 +58,12 @@ are parsed through phandles and processed purely based on their content. + + Pin Configuration Node Properties: + +-- renesas,pins : An array of strings, each string containing the name of a pin. +-- renesas,groups : An array of strings, each string containing the name of a pin ++- pins : An array of strings, each string containing the name of a pin. ++- groups : An array of strings, each string containing the name of a pin + group. + +-- renesas,function: A string containing the name of the function to mux to the +- pin group(s) specified by the renesas,groups property ++- function: A string containing the name of the function to mux to the pin ++ group(s) specified by the groups property. + + Valid values for pin, group and function names can be found in the group and + function arrays of the PFC data file corresponding to the SoC +@@ -141,19 +141,19 @@ Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps + + mmcif_pins: mmcif { + mux { +- renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; +- renesas,function = "mmc0"; ++ groups = "mmc0_data8_0", "mmc0_ctrl_0"; ++ function = "mmc0"; + }; + cfg { +- renesas,groups = "mmc0_data8_0"; +- renesas,pins = "PORT279"; ++ groups = "mmc0_data8_0"; ++ pins = "PORT279"; + bias-pull-up; + }; + }; + + scifa4_pins: scifa4 { +- renesas,groups = "scifa4_data", "scifa4_ctrl"; +- renesas,function = "scifa4"; ++ groups = "scifa4_data", "scifa4_ctrl"; ++ function = "scifa4"; + }; + }; + +diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c +index ff678966008b..6fe7459f0ccb 100644 +--- a/drivers/pinctrl/sh-pfc/pinctrl.c ++++ b/drivers/pinctrl/sh-pfc/pinctrl.c +@@ -40,6 +40,10 @@ struct sh_pfc_pinctrl { + + struct pinctrl_pin_desc *pins; + struct sh_pfc_pin_config *configs; ++ ++ const char *func_prop_name; ++ const char *groups_prop_name; ++ const char *pins_prop_name; + }; + + static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) +@@ -96,10 +100,13 @@ static int sh_pfc_map_add_config(struct pinctrl_map *map, + return 0; + } + +-static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, ++static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps, unsigned int *index) + { ++ struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); ++ struct device *dev = pmx->pfc->dev; + struct pinctrl_map *maps = *map; + unsigned int nmaps = *num_maps; + unsigned int idx = *index; +@@ -113,10 +120,27 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, + const char *pin; + int ret; + ++ /* Support both the old Renesas-specific properties and the new standard ++ * properties. Mixing old and new properties isn't allowed, neither ++ * inside a subnode nor across subnodes. ++ */ ++ if (!pmx->func_prop_name) { ++ if (of_find_property(np, "groups", NULL) || ++ of_find_property(np, "pins", NULL)) { ++ pmx->func_prop_name = "function"; ++ pmx->groups_prop_name = "groups"; ++ pmx->pins_prop_name = "pins"; ++ } else { ++ pmx->func_prop_name = "renesas,function"; ++ pmx->groups_prop_name = "renesas,groups"; ++ pmx->pins_prop_name = "renesas,pins"; ++ } ++ } ++ + /* Parse the function and configuration properties. At least a function + * or one configuration must be specified. + */ +- ret = of_property_read_string(np, "renesas,function", &function); ++ ret = of_property_read_string(np, pmx->func_prop_name, &function); + if (ret < 0 && ret != -EINVAL) { + dev_err(dev, "Invalid function in DT\n"); + return ret; +@@ -129,11 +153,12 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, + if (!function && num_configs == 0) { + dev_err(dev, + "DT node must contain at least a function or config\n"); ++ ret = -ENODEV; + goto done; + } + + /* Count the number of pins and groups and reallocate mappings. */ +- ret = of_property_count_strings(np, "renesas,pins"); ++ ret = of_property_count_strings(np, pmx->pins_prop_name); + if (ret == -EINVAL) { + num_pins = 0; + } else if (ret < 0) { +@@ -143,7 +168,7 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, + num_pins = ret; + } + +- ret = of_property_count_strings(np, "renesas,groups"); ++ ret = of_property_count_strings(np, pmx->groups_prop_name); + if (ret == -EINVAL) { + num_groups = 0; + } else if (ret < 0) { +@@ -174,7 +199,7 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, + *num_maps = nmaps; + + /* Iterate over pins and groups and create the mappings. */ +- of_property_for_each_string(np, "renesas,groups", prop, group) { ++ of_property_for_each_string(np, pmx->groups_prop_name, prop, group) { + if (function) { + maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; + maps[idx].data.mux.group = group; +@@ -198,7 +223,7 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, + goto done; + } + +- of_property_for_each_string(np, "renesas,pins", prop, pin) { ++ of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) { + ret = sh_pfc_map_add_config(&maps[idx], pin, + PIN_MAP_TYPE_CONFIGS_PIN, + configs, num_configs); +@@ -246,7 +271,7 @@ static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, + index = 0; + + for_each_child_of_node(np, child) { +- ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps, ++ ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps, + &index); + if (ret < 0) + goto done; +@@ -254,7 +279,8 @@ static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, + + /* If no mapping has been found in child nodes try the config node. */ + if (*num_maps == 0) { +- ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index); ++ ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps, ++ &index); + if (ret < 0) + goto done; + } +-- +2.6.2 + diff --git a/patches.renesas/0252-pinctrl-sh-pfc-Convert-to-platform_get_.patch b/patches.renesas/0252-pinctrl-sh-pfc-Convert-to-platform_get_.patch new file mode 100644 index 00000000000000..7626a0e37534ea --- /dev/null +++ b/patches.renesas/0252-pinctrl-sh-pfc-Convert-to-platform_get_.patch @@ -0,0 +1,116 @@ +From 1941ea8aac7287ea40ab9d1a266fe4e3206a84c9 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 25 Jun 2015 11:39:53 +0200 +Subject: [PATCH 252/326] pinctrl: sh-pfc: Convert to platform_get_*() + +If the pin function controller (which can be a GPIO controller) is +instantiated before the interrupt controllers, due to the ordering in +the DTS, the irq domains for the interrupt controllers referenced by its +"interrupts-extended" property cannot be found yet: + + irq: no irq domain found for /interrupt-controller@e61c0000 ! + +As the sh-pfc driver accesses the platform device's resources directly, +it cannot find the (optional) IRQ resources, and thinks no interrupts +are available. This may lead to failures later, when GPIOs are used as +interupts: + + gpio-keys keyboard: Unable to claim irq 0; error -22 + gpio-keys: probe of keyboard failed with error -22 + +To fix this, add support for deferred probing to sh-pfc, by converting +the driver from direct platform device resource access to using the +platform_get_resource() and platform_get_irq() helpers. + +Note that while this fixes the root cause worked around by commit +e4ba0a9bddff3ba5 ("ARM: shmobile: r8a73a4: Move pfc node to work around +probe ordering bug"), I strongly recommend against reverting the +workaround now, as this would lead to lots of probe deferrals in drivers +relying on pinctrl. This may be reconsidered once the DT code starts +taking into account phandle dependencies during device instantation. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit c7977ec4a33633c8e8d9267dd014356cf857351c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 46 ++++++++++++++++++++----------------------- + 1 file changed, 21 insertions(+), 25 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index 865d235612c5..979623895904 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -29,24 +29,25 @@ + static int sh_pfc_map_resources(struct sh_pfc *pfc, + struct platform_device *pdev) + { +- unsigned int num_windows = 0; +- unsigned int num_irqs = 0; ++ unsigned int num_windows, num_irqs; + struct sh_pfc_window *windows; + unsigned int *irqs = NULL; + struct resource *res; + unsigned int i; ++ int irq; + + /* Count the MEM and IRQ resources. */ +- for (i = 0; i < pdev->num_resources; ++i) { +- switch (resource_type(&pdev->resource[i])) { +- case IORESOURCE_MEM: +- num_windows++; ++ for (num_windows = 0;; num_windows++) { ++ res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows); ++ if (!res) + break; +- +- case IORESOURCE_IRQ: +- num_irqs++; ++ } ++ for (num_irqs = 0;; num_irqs++) { ++ irq = platform_get_irq(pdev, num_irqs); ++ if (irq == -EPROBE_DEFER) ++ return irq; ++ if (irq < 0) + break; +- } + } + + if (num_windows == 0) +@@ -72,22 +73,17 @@ static int sh_pfc_map_resources(struct sh_pfc *pfc, + } + + /* Fill them. */ +- for (i = 0, res = pdev->resource; i < pdev->num_resources; i++, res++) { +- switch (resource_type(res)) { +- case IORESOURCE_MEM: +- windows->phys = res->start; +- windows->size = resource_size(res); +- windows->virt = devm_ioremap_resource(pfc->dev, res); +- if (IS_ERR(windows->virt)) +- return -ENOMEM; +- windows++; +- break; +- +- case IORESOURCE_IRQ: +- *irqs++ = res->start; +- break; +- } ++ for (i = 0; i < num_windows; i++) { ++ res = platform_get_resource(pdev, IORESOURCE_MEM, i); ++ windows->phys = res->start; ++ windows->size = resource_size(res); ++ windows->virt = devm_ioremap_resource(pfc->dev, res); ++ if (IS_ERR(windows->virt)) ++ return -ENOMEM; ++ windows++; + } ++ for (i = 0; i < num_irqs; i++) ++ *irqs++ = platform_get_irq(pdev, i); + + return 0; + } +-- +2.6.2 + diff --git a/patches.renesas/0253-dmaengine-shdma-Make-dummy-shdma_chan_filter-always-.patch b/patches.renesas/0253-dmaengine-shdma-Make-dummy-shdma_chan_filter-always-.patch new file mode 100644 index 00000000000000..0f5194cc947f21 --- /dev/null +++ b/patches.renesas/0253-dmaengine-shdma-Make-dummy-shdma_chan_filter-always-.patch @@ -0,0 +1,59 @@ +From 4b83c965ad8e2d2bfc84fe2abbea9a7fac7ee117 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Jul 2015 12:07:25 +0200 +Subject: [PATCH 253/326] dmaengine: shdma: Make dummy shdma_chan_filter() + always return false + +If CONFIG_SH_DMAE_BASE (which is required for DMA engine support for +legacy SH, SH/R-Mobile, and R-Car Gen1, but not for R-Car Gen2) is not +enabled, but CONFIG_RCAR_DMAC (for R-Car Gen2 DMA engine support) is, +and the DTS doesn't provide a "dmas" property for a device, +dma_request_slave_channel_compat() incorrectly succeeds, and returns a +DMA channel. + +However, when trying to use that DMA channel later, it fails with: + + rcar-dmac e6700000.dma-controller: rcar_dmac_prep_slave_sg: bad parameter: len=1, id=-22 + +(Fortunately most drivers can handle this failure, and fall back to +PIO) + +The reason for this is that a NULL legacy filter function is used, which +actually means "all channels are OK", not "do not match". +If CONFIG_SH_DMAE_BASE is enabled (like in shmobile_defconfig, which +supports other SoCs besides R-Car Gen2), shdma_chan_filter() correctly +returns false, as no available channel on R-Car Gen2 matches a +shdma-base channel. +If the DTS does provide a "dmas" property, dma_request_slave_channel() +succeeds, and legacy filter-based matching is not used. + +To fix this, change shdma_chan_filter from being NULL to a dummy +function that always returns false, like is done on other platforms. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Vinod Koul <vinod.koul@intel.com> +(cherry picked from commit 056f6c87028544de934f27caf95aa1545d585767) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/linux/shdma-base.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/include/linux/shdma-base.h b/include/linux/shdma-base.h +index dd0ba502ccb3..d927647e6350 100644 +--- a/include/linux/shdma-base.h ++++ b/include/linux/shdma-base.h +@@ -128,7 +128,10 @@ void shdma_cleanup(struct shdma_dev *sdev); + #if IS_ENABLED(CONFIG_SH_DMAE_BASE) + bool shdma_chan_filter(struct dma_chan *chan, void *arg); + #else +-#define shdma_chan_filter NULL ++static inline bool shdma_chan_filter(struct dma_chan *chan, void *arg) ++{ ++ return false; ++} + #endif + + #endif +-- +2.6.2 + diff --git a/patches.renesas/0254-dmaengine-sort-the-sh-Makefile.patch b/patches.renesas/0254-dmaengine-sort-the-sh-Makefile.patch new file mode 100644 index 00000000000000..757cfe31b5a2b1 --- /dev/null +++ b/patches.renesas/0254-dmaengine-sort-the-sh-Makefile.patch @@ -0,0 +1,30 @@ +From 9032ceae4e9ccafcd76d62de563081913318c67d Mon Sep 17 00:00:00 2001 +From: Vinod Koul <vinod.koul@intel.com> +Date: Mon, 24 Aug 2015 13:43:14 +0530 +Subject: [PATCH 254/326] dmaengine: sort the sh Makefile + +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Vinod Koul <vinod.koul@intel.com> +(cherry picked from commit 8a4ce226b9061fe3ab04f6db34d4b2ae645b9f65) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/dma/sh/Makefile | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/dma/sh/Makefile b/drivers/dma/sh/Makefile +index b8a598066ce2..0133e4658196 100644 +--- a/drivers/dma/sh/Makefile ++++ b/drivers/dma/sh/Makefile +@@ -13,7 +13,7 @@ shdma-$(CONFIG_SH_DMAE_R8A73A4) += shdma-r8a73a4.o + shdma-objs := $(shdma-y) + obj-$(CONFIG_SH_DMAE) += shdma.o + +-obj-$(CONFIG_SUDMAC) += sudmac.o +-obj-$(CONFIG_RCAR_HPB_DMAE) += rcar-hpbdma.o + obj-$(CONFIG_RCAR_DMAC) += rcar-dmac.o ++obj-$(CONFIG_RCAR_HPB_DMAE) += rcar-hpbdma.o + obj-$(CONFIG_RENESAS_USB_DMAC) += usb-dmac.o ++obj-$(CONFIG_SUDMAC) += sudmac.o +-- +2.6.2 + diff --git a/patches.renesas/0255-usb-renesas_usbhs-Replace-deprecated-API-of-extcon.patch b/patches.renesas/0255-usb-renesas_usbhs-Replace-deprecated-API-of-extcon.patch new file mode 100644 index 00000000000000..7ab0f2fee1879d --- /dev/null +++ b/patches.renesas/0255-usb-renesas_usbhs-Replace-deprecated-API-of-extcon.patch @@ -0,0 +1,41 @@ +From 9727315afa9175a86fd0c338f42ff2eeca17e9e7 Mon Sep 17 00:00:00 2001 +From: Chanwoo Choi <cw00.choi@samsung.com> +Date: Wed, 1 Jul 2015 13:11:33 +0900 +Subject: [PATCH 255/326] usb: renesas_usbhs: Replace deprecated API of extcon + +This patch removes the deprecated API of extcon and then use the new extcon API +with the unique id to indicate the each external connector (USB-HOST). +- extcon_get_cable_state(*edev, char *) -> extcon_get_cable_state_(*edev, id) + +Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Cc: Felipe Balbi <balbi@ti.com> +Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Cc: Peter Chen <peter.chen@freescale.com> +Cc: Varka Bhadram <varkab@cdac.in> +Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> +Signed-off-by: Felipe Balbi <balbi@ti.com> +(cherry picked from commit 50297b79b8fd426f678431a8e9dcee59afd33ec8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/renesas_usbhs/common.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c +index 0f7e850fd4aa..da321f034e3c 100644 +--- a/drivers/usb/renesas_usbhs/common.c ++++ b/drivers/usb/renesas_usbhs/common.c +@@ -388,7 +388,7 @@ static void usbhsc_hotplug(struct usbhs_priv *priv) + + if (enable && !mod) { + if (priv->edev) { +- cable = extcon_get_cable_state(priv->edev, "USB-HOST"); ++ cable = extcon_get_cable_state_(priv->edev, EXTCON_USB_HOST); + if ((cable > 0 && id != USBHS_HOST) || + (!cable && id != USBHS_GADGET)) { + dev_info(&pdev->dev, +-- +2.6.2 + diff --git a/patches.renesas/0256-usb-renesas_usbhs-Allow-an-OTG-PHY-driver-to-provide.patch b/patches.renesas/0256-usb-renesas_usbhs-Allow-an-OTG-PHY-driver-to-provide.patch new file mode 100644 index 00000000000000..0cee785af4067f --- /dev/null +++ b/patches.renesas/0256-usb-renesas_usbhs-Allow-an-OTG-PHY-driver-to-provide.patch @@ -0,0 +1,148 @@ +From 7cd47cd5c2de2bcb94d5b04daf808c0b2662294c Mon Sep 17 00:00:00 2001 +From: Phil Edworthy <phil.edworthy@renesas.com> +Date: Mon, 13 Jul 2015 16:30:18 +0100 +Subject: [PATCH 256/326] usb: renesas_usbhs: Allow an OTG PHY driver to + provide VBUS + +These changes allow a PHY driver to trigger a VBUS interrupt and +to provide the value of VBUS. + +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> +Signed-off-by: Felipe Balbi <balbi@ti.com> +(cherry picked from commit b5a2875605cac14a7d7744ec8254547a26c02612) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/renesas_usbhs/mod_gadget.c | 62 ++++++++++++++++++++++++++++++++++ + 1 file changed, 62 insertions(+) + +diff --git a/drivers/usb/renesas_usbhs/mod_gadget.c b/drivers/usb/renesas_usbhs/mod_gadget.c +index dc2aa3261202..494dfe06bb27 100644 +--- a/drivers/usb/renesas_usbhs/mod_gadget.c ++++ b/drivers/usb/renesas_usbhs/mod_gadget.c +@@ -21,6 +21,7 @@ + #include <linux/platform_device.h> + #include <linux/usb/ch9.h> + #include <linux/usb/gadget.h> ++#include <linux/usb/otg.h> + #include "common.h" + + /* +@@ -50,6 +51,8 @@ struct usbhsg_gpriv { + int uep_size; + + struct usb_gadget_driver *driver; ++ struct usb_phy *transceiver; ++ bool vbus_active; + + u32 status; + #define USBHSG_STATUS_STARTED (1 << 0) +@@ -873,6 +876,27 @@ static int usbhsg_try_stop(struct usbhs_priv *priv, u32 status) + } + + /* ++ * VBUS provided by the PHY ++ */ ++static int usbhsm_phy_get_vbus(struct platform_device *pdev) ++{ ++ struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev); ++ struct usbhsg_gpriv *gpriv = usbhsg_priv_to_gpriv(priv); ++ ++ return gpriv->vbus_active; ++} ++ ++static void usbhs_mod_phy_mode(struct usbhs_priv *priv) ++{ ++ struct usbhs_mod_info *info = &priv->mod_info; ++ ++ info->irq_vbus = NULL; ++ priv->pfunc.get_vbus = usbhsm_phy_get_vbus; ++ ++ usbhs_irq_callback_update(priv, NULL); ++} ++ ++/* + * + * linux usb function + * +@@ -882,12 +906,28 @@ static int usbhsg_gadget_start(struct usb_gadget *gadget, + { + struct usbhsg_gpriv *gpriv = usbhsg_gadget_to_gpriv(gadget); + struct usbhs_priv *priv = usbhsg_gpriv_to_priv(gpriv); ++ struct device *dev = usbhs_priv_to_dev(priv); ++ int ret; + + if (!driver || + !driver->setup || + driver->max_speed < USB_SPEED_FULL) + return -EINVAL; + ++ /* connect to bus through transceiver */ ++ if (!IS_ERR_OR_NULL(gpriv->transceiver)) { ++ ret = otg_set_peripheral(gpriv->transceiver->otg, ++ &gpriv->gadget); ++ if (ret) { ++ dev_err(dev, "%s: can't bind to transceiver\n", ++ gpriv->gadget.name); ++ return ret; ++ } ++ ++ /* get vbus using phy versions */ ++ usbhs_mod_phy_mode(priv); ++ } ++ + /* first hook up the driver ... */ + gpriv->driver = driver; + +@@ -900,6 +940,10 @@ static int usbhsg_gadget_stop(struct usb_gadget *gadget) + struct usbhs_priv *priv = usbhsg_gpriv_to_priv(gpriv); + + usbhsg_try_stop(priv, USBHSG_STATUS_REGISTERD); ++ ++ if (!IS_ERR_OR_NULL(gpriv->transceiver)) ++ otg_set_peripheral(gpriv->transceiver->otg, NULL); ++ + gpriv->driver = NULL; + + return 0; +@@ -947,12 +991,26 @@ static int usbhsg_set_selfpowered(struct usb_gadget *gadget, int is_self) + return 0; + } + ++static int usbhsg_vbus_session(struct usb_gadget *gadget, int is_active) ++{ ++ struct usbhsg_gpriv *gpriv = usbhsg_gadget_to_gpriv(gadget); ++ struct usbhs_priv *priv = usbhsg_gpriv_to_priv(gpriv); ++ struct platform_device *pdev = usbhs_priv_to_pdev(priv); ++ ++ gpriv->vbus_active = !!is_active; ++ ++ renesas_usbhs_call_notify_hotplug(pdev); ++ ++ return 0; ++} ++ + static const struct usb_gadget_ops usbhsg_gadget_ops = { + .get_frame = usbhsg_get_frame, + .set_selfpowered = usbhsg_set_selfpowered, + .udc_start = usbhsg_gadget_start, + .udc_stop = usbhsg_gadget_stop, + .pullup = usbhsg_pullup, ++ .vbus_session = usbhsg_vbus_session, + }; + + static int usbhsg_start(struct usbhs_priv *priv) +@@ -994,6 +1052,10 @@ int usbhs_mod_gadget_probe(struct usbhs_priv *priv) + goto usbhs_mod_gadget_probe_err_gpriv; + } + ++ gpriv->transceiver = usb_get_phy(USB_PHY_TYPE_UNDEFINED); ++ dev_info(dev, "%stransceiver found\n", ++ gpriv->transceiver ? "" : "no "); ++ + /* + * CAUTION + * +-- +2.6.2 + diff --git a/patches.renesas/0257-media-media-uapi-vsp1-Use-__u32-instead-of-u32.patch b/patches.renesas/0257-media-media-uapi-vsp1-Use-__u32-instead-of-u32.patch new file mode 100644 index 00000000000000..9cfcd8c0535b78 --- /dev/null +++ b/patches.renesas/0257-media-media-uapi-vsp1-Use-__u32-instead-of-u32.patch @@ -0,0 +1,32 @@ +From 98291c30a87ffe6aa4bd2ddff8455e7c276261bd Mon Sep 17 00:00:00 2001 +From: Joe Perches <joe@perches.com> +Date: Sat, 16 May 2015 15:11:40 -0300 +Subject: [PATCH 257/326] [media] media: uapi: vsp1: Use __u32 instead of u32 + +Don't use the kernel types in uapi headers. + +Signed-off-by: Joe Perches <joe@perches.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit 9aee1ae3312daf0de4c9c614680d06d557133317) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/uapi/linux/vsp1.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/uapi/linux/vsp1.h b/include/uapi/linux/vsp1.h +index e18858f6e865..9a823696d816 100644 +--- a/include/uapi/linux/vsp1.h ++++ b/include/uapi/linux/vsp1.h +@@ -28,7 +28,7 @@ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct vsp1_lut_config) + + struct vsp1_lut_config { +- u32 lut[256]; ++ __u32 lut[256]; + }; + + #endif /* __VSP1_USER_H__ */ +-- +2.6.2 + diff --git a/patches.renesas/0258-media-v4l-vsp1-Fix-VI6_WPF_SZCLIP_SIZE_MASK-macro.patch b/patches.renesas/0258-media-v4l-vsp1-Fix-VI6_WPF_SZCLIP_SIZE_MASK-macro.patch new file mode 100644 index 00000000000000..5357d9534bff9c --- /dev/null +++ b/patches.renesas/0258-media-v4l-vsp1-Fix-VI6_WPF_SZCLIP_SIZE_MASK-macro.patch @@ -0,0 +1,34 @@ +From 4df2e189033ee6b474a2a1589a6041644c0f9915 Mon Sep 17 00:00:00 2001 +From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Date: Wed, 28 Jan 2015 22:53:53 -0200 +Subject: [PATCH 258/326] [media] v4l: vsp1: Fix VI6_WPF_SZCLIP_SIZE_MASK macro + +Clipping size bit of VI6_WPFn _HSZCLIP and VI6_WPFn _VSZCLIP register are from +0 bit to 11 bit. But VI6_WPF_SZCLIP_SIZE_MASK is set to 0x1FFF, this will mask +until the reserve bits. This fixes size for VI6_WPF_SZCLIP_SIZE_MASK. + +Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit 03b36e4dcf422a10da8b67bce2ed00b34ec58aac) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_regs.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h +index da3c573e1efc..f61e1096f9fc 100644 +--- a/drivers/media/platform/vsp1/vsp1_regs.h ++++ b/drivers/media/platform/vsp1/vsp1_regs.h +@@ -238,7 +238,7 @@ + #define VI6_WPF_SZCLIP_EN (1 << 28) + #define VI6_WPF_SZCLIP_OFST_MASK (0xff << 16) + #define VI6_WPF_SZCLIP_OFST_SHIFT 16 +-#define VI6_WPF_SZCLIP_SIZE_MASK (0x1fff << 0) ++#define VI6_WPF_SZCLIP_SIZE_MASK (0xfff << 0) + #define VI6_WPF_SZCLIP_SIZE_SHIFT 0 + + #define VI6_WPF_OUTFMT 0x100c +-- +2.6.2 + diff --git a/patches.renesas/0259-media-v4l-vsp1-Fix-VI6_DPR_ROUTE_FP_MASK-macro.patch b/patches.renesas/0259-media-v4l-vsp1-Fix-VI6_DPR_ROUTE_FP_MASK-macro.patch new file mode 100644 index 00000000000000..7992d84558b1e8 --- /dev/null +++ b/patches.renesas/0259-media-v4l-vsp1-Fix-VI6_DPR_ROUTE_FP_MASK-macro.patch @@ -0,0 +1,34 @@ +From 084b25c7b5d3bd1341277c03fc876c3fb387a13c Mon Sep 17 00:00:00 2001 +From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Date: Wed, 28 Jan 2015 22:53:54 -0200 +Subject: [PATCH 259/326] [media] v4l: vsp1: Fix VI6_DPR_ROUTE_FP_MASK macro + +FP bit of VI6_DPR_mod_ROUTE register is 6bit. But VI6_DPR_ROUTE_FP_MASK is set +to 0xFF, this will mask until the reserve bit. +This fixes size for VI6_DPR_ROUTE_FP_MASK. + +Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit 1aa7890324b497f96f07c20673fae58f26fabfe7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_regs.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h +index f61e1096f9fc..4177f98968d6 100644 +--- a/drivers/media/platform/vsp1/vsp1_regs.h ++++ b/drivers/media/platform/vsp1/vsp1_regs.h +@@ -306,7 +306,7 @@ + #define VI6_DPR_BRU_ROUTE 0x204c + #define VI6_DPR_ROUTE_FXA_MASK (0xff << 8) + #define VI6_DPR_ROUTE_FXA_SHIFT 16 +-#define VI6_DPR_ROUTE_FP_MASK (0xff << 8) ++#define VI6_DPR_ROUTE_FP_MASK (0x3f << 8) + #define VI6_DPR_ROUTE_FP_SHIFT 8 + #define VI6_DPR_ROUTE_RT_MASK (0x3f << 0) + #define VI6_DPR_ROUTE_RT_SHIFT 0 +-- +2.6.2 + diff --git a/patches.renesas/0260-media-v4l-vsp1-Fix-VI6_DPR_ROUTE_FXA_MASK-macro.patch b/patches.renesas/0260-media-v4l-vsp1-Fix-VI6_DPR_ROUTE_FXA_MASK-macro.patch new file mode 100644 index 00000000000000..00a947fa452e52 --- /dev/null +++ b/patches.renesas/0260-media-v4l-vsp1-Fix-VI6_DPR_ROUTE_FXA_MASK-macro.patch @@ -0,0 +1,33 @@ +From f7203d401175a2ea67ae1afc405c94025644f7df Mon Sep 17 00:00:00 2001 +From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Date: Wed, 28 Jan 2015 22:53:55 -0200 +Subject: [PATCH 260/326] [media] v4l: vsp1: Fix VI6_DPR_ROUTE_FXA_MASK macro + +FXA bit of VI6_DPR_mod_ROUTE register starts from 16bit. But VI6_DPR_ROUTE_FXA_MASK +is set to become start from 8bit. This fixes shift size for VI6_DPR_ROUTE_FXA_MASK. + +Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit 45008ee9295b3ae96d7413ab91871907a671ca82) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_regs.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h +index 4177f98968d6..25b48738b147 100644 +--- a/drivers/media/platform/vsp1/vsp1_regs.h ++++ b/drivers/media/platform/vsp1/vsp1_regs.h +@@ -304,7 +304,7 @@ + #define VI6_DPR_HST_ROUTE 0x2044 + #define VI6_DPR_HSI_ROUTE 0x2048 + #define VI6_DPR_BRU_ROUTE 0x204c +-#define VI6_DPR_ROUTE_FXA_MASK (0xff << 8) ++#define VI6_DPR_ROUTE_FXA_MASK (0xff << 16) + #define VI6_DPR_ROUTE_FXA_SHIFT 16 + #define VI6_DPR_ROUTE_FP_MASK (0x3f << 8) + #define VI6_DPR_ROUTE_FP_SHIFT 8 +-- +2.6.2 + diff --git a/patches.renesas/0261-media-v4l-vsp1-Fix-Suspend-to-RAM.patch b/patches.renesas/0261-media-v4l-vsp1-Fix-Suspend-to-RAM.patch new file mode 100644 index 00000000000000..14ae84f53258af --- /dev/null +++ b/patches.renesas/0261-media-v4l-vsp1-Fix-Suspend-to-RAM.patch @@ -0,0 +1,179 @@ +From b2c629e61e960d8a17163f25268b1f757ad8ed94 Mon Sep 17 00:00:00 2001 +From: Sei Fumizono <sei.fumizono.jw@hitachi-solutions.com> +Date: Sun, 15 Mar 2015 11:33:07 -0300 +Subject: [PATCH 261/326] [media] v4l: vsp1: Fix Suspend-to-RAM + +Fix Suspend-to-RAM so that VSP1 driver continues to work after resuming. + +In detail, + - Fix the judgment of ref count in resuming. + - Add stopping VSP1 during suspend. + +[Refactor the suspend and resume code to lower suspend delay] + +Signed-off-by: Sei Fumizono <sei.fumizono.jw@hitachi-solutions.com> +Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> +Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit 139c92866e34bfa4897e644b36147fc86cc7a7a1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_drv.c | 13 ++++-- + drivers/media/platform/vsp1/vsp1_video.c | 70 +++++++++++++++++++++++++++++++- + drivers/media/platform/vsp1/vsp1_video.h | 5 ++- + 3 files changed, 83 insertions(+), 5 deletions(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c +index 913485a90e97..4e61886384e3 100644 +--- a/drivers/media/platform/vsp1/vsp1_drv.c ++++ b/drivers/media/platform/vsp1/vsp1_drv.c +@@ -1,7 +1,7 @@ + /* + * vsp1_drv.c -- R-Car VSP1 Driver + * +- * Copyright (C) 2013-2014 Renesas Electronics Corporation ++ * Copyright (C) 2013-2015 Renesas Electronics Corporation + * + * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) + * +@@ -403,7 +403,10 @@ static int vsp1_pm_suspend(struct device *dev) + if (vsp1->ref_count == 0) + return 0; + ++ vsp1_pipelines_suspend(vsp1); ++ + clk_disable_unprepare(vsp1->clock); ++ + return 0; + } + +@@ -413,10 +416,14 @@ static int vsp1_pm_resume(struct device *dev) + + WARN_ON(mutex_is_locked(&vsp1->lock)); + +- if (vsp1->ref_count) ++ if (vsp1->ref_count == 0) + return 0; + +- return clk_prepare_enable(vsp1->clock); ++ clk_prepare_enable(vsp1->clock); ++ ++ vsp1_pipelines_resume(vsp1); ++ ++ return 0; + } + #endif + +diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c +index d91f19a9e1c1..c4b06214b6c1 100644 +--- a/drivers/media/platform/vsp1/vsp1_video.c ++++ b/drivers/media/platform/vsp1/vsp1_video.c +@@ -1,7 +1,7 @@ + /* + * vsp1_video.c -- R-Car VSP1 Video Node + * +- * Copyright (C) 2013-2014 Renesas Electronics Corporation ++ * Copyright (C) 2013-2015 Renesas Electronics Corporation + * + * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) + * +@@ -703,6 +703,74 @@ void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe, + } + } + ++void vsp1_pipelines_suspend(struct vsp1_device *vsp1) ++{ ++ unsigned long flags; ++ unsigned int i; ++ int ret; ++ ++ /* To avoid increasing the system suspend time needlessly, loop over the ++ * pipelines twice, first to set them all to the stopping state, and then ++ * to wait for the stop to complete. ++ */ ++ for (i = 0; i < vsp1->pdata.wpf_count; ++i) { ++ struct vsp1_rwpf *wpf = vsp1->wpf[i]; ++ struct vsp1_pipeline *pipe; ++ ++ if (wpf == NULL) ++ continue; ++ ++ pipe = to_vsp1_pipeline(&wpf->entity.subdev.entity); ++ if (pipe == NULL) ++ continue; ++ ++ spin_lock_irqsave(&pipe->irqlock, flags); ++ if (pipe->state == VSP1_PIPELINE_RUNNING) ++ pipe->state = VSP1_PIPELINE_STOPPING; ++ spin_unlock_irqrestore(&pipe->irqlock, flags); ++ } ++ ++ for (i = 0; i < vsp1->pdata.wpf_count; ++i) { ++ struct vsp1_rwpf *wpf = vsp1->wpf[i]; ++ struct vsp1_pipeline *pipe; ++ ++ if (wpf == NULL) ++ continue; ++ ++ pipe = to_vsp1_pipeline(&wpf->entity.subdev.entity); ++ if (pipe == NULL) ++ continue; ++ ++ ret = wait_event_timeout(pipe->wq, ++ pipe->state == VSP1_PIPELINE_STOPPED, ++ msecs_to_jiffies(500)); ++ if (ret == 0) ++ dev_warn(vsp1->dev, "pipeline %u stop timeout\n", ++ wpf->entity.index); ++ } ++} ++ ++void vsp1_pipelines_resume(struct vsp1_device *vsp1) ++{ ++ unsigned int i; ++ ++ /* Resume pipeline all running pipelines. */ ++ for (i = 0; i < vsp1->pdata.wpf_count; ++i) { ++ struct vsp1_rwpf *wpf = vsp1->wpf[i]; ++ struct vsp1_pipeline *pipe; ++ ++ if (wpf == NULL) ++ continue; ++ ++ pipe = to_vsp1_pipeline(&wpf->entity.subdev.entity); ++ if (pipe == NULL) ++ continue; ++ ++ if (vsp1_pipeline_ready(pipe)) ++ vsp1_pipeline_run(pipe); ++ } ++} ++ + /* ----------------------------------------------------------------------------- + * videobuf2 Queue Operations + */ +diff --git a/drivers/media/platform/vsp1/vsp1_video.h b/drivers/media/platform/vsp1/vsp1_video.h +index fd2851a82e00..0887a4d2742c 100644 +--- a/drivers/media/platform/vsp1/vsp1_video.h ++++ b/drivers/media/platform/vsp1/vsp1_video.h +@@ -1,7 +1,7 @@ + /* + * vsp1_video.h -- R-Car VSP1 Video Node + * +- * Copyright (C) 2013-2014 Renesas Electronics Corporation ++ * Copyright (C) 2013-2015 Renesas Electronics Corporation + * + * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) + * +@@ -149,4 +149,7 @@ void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe, + struct vsp1_entity *input, + unsigned int alpha); + ++void vsp1_pipelines_suspend(struct vsp1_device *vsp1); ++void vsp1_pipelines_resume(struct vsp1_device *vsp1); ++ + #endif /* __VSP1_VIDEO_H__ */ +-- +2.6.2 + diff --git a/patches.renesas/0262-media-v4l-vsp1-Fix-race-condition-when-stopping-pipe.patch b/patches.renesas/0262-media-v4l-vsp1-Fix-race-condition-when-stopping-pipe.patch new file mode 100644 index 00000000000000..b100fe4b12b45e --- /dev/null +++ b/patches.renesas/0262-media-v4l-vsp1-Fix-race-condition-when-stopping-pipe.patch @@ -0,0 +1,63 @@ +From dfb59febd3e731b2dabb46135491cde31105e13f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 29 Apr 2015 16:54:39 -0300 +Subject: [PATCH 262/326] [media] v4l: vsp1: Fix race condition when stopping + pipeline + +When stopping the pipeline the driver waits for the pipeline state to be +set to VSP1_PIPELINE_STOPPED but fails to lock the pipe irqlock to read +the state variable protected by the lock. Fix it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit 1c991fee30c72ff49bb96558d5f1c14a60230677) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_video.c | 17 ++++++++++++++--- + 1 file changed, 14 insertions(+), 3 deletions(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c +index c4b06214b6c1..c1b5a09b8331 100644 +--- a/drivers/media/platform/vsp1/vsp1_video.c ++++ b/drivers/media/platform/vsp1/vsp1_video.c +@@ -514,6 +514,18 @@ static void vsp1_pipeline_run(struct vsp1_pipeline *pipe) + pipe->buffers_ready = 0; + } + ++bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe) ++{ ++ unsigned long flags; ++ bool stopped; ++ ++ spin_lock_irqsave(&pipe->irqlock, flags); ++ stopped = pipe->state == VSP1_PIPELINE_STOPPED, ++ spin_unlock_irqrestore(&pipe->irqlock, flags); ++ ++ return stopped; ++} ++ + static int vsp1_pipeline_stop(struct vsp1_pipeline *pipe) + { + struct vsp1_entity *entity; +@@ -525,7 +537,7 @@ static int vsp1_pipeline_stop(struct vsp1_pipeline *pipe) + pipe->state = VSP1_PIPELINE_STOPPING; + spin_unlock_irqrestore(&pipe->irqlock, flags); + +- ret = wait_event_timeout(pipe->wq, pipe->state == VSP1_PIPELINE_STOPPED, ++ ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe), + msecs_to_jiffies(500)); + ret = ret == 0 ? -ETIMEDOUT : 0; + +@@ -741,8 +753,7 @@ void vsp1_pipelines_suspend(struct vsp1_device *vsp1) + if (pipe == NULL) + continue; + +- ret = wait_event_timeout(pipe->wq, +- pipe->state == VSP1_PIPELINE_STOPPED, ++ ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe), + msecs_to_jiffies(500)); + if (ret == 0) + dev_warn(vsp1->dev, "pipeline %u stop timeout\n", +-- +2.6.2 + diff --git a/patches.renesas/0263-media-v4l-vsp1-Align-crop-rectangle-to-even-boundary.patch b/patches.renesas/0263-media-v4l-vsp1-Align-crop-rectangle-to-even-boundary.patch new file mode 100644 index 00000000000000..2d1fd88e58715b --- /dev/null +++ b/patches.renesas/0263-media-v4l-vsp1-Align-crop-rectangle-to-even-boundary.patch @@ -0,0 +1,47 @@ +From 6e58b0ae1af6429948f60894db34d64f28f2c4ce Mon Sep 17 00:00:00 2001 +From: Damian Hobson-Garcia <dhobsong@igel.co.jp> +Date: Thu, 28 May 2015 09:59:39 -0300 +Subject: [PATCH 263/326] [media] v4l: vsp1: Align crop rectangle to even + boundary for YUV formats + +Make sure that there are valid values in the crop rectangle to ensure +that the color plane doesn't get shifted when cropping. +Since there is no distinction between 12bit and 16bit YUV formats in +at the subdev level, use the more restrictive 12bit limits for all YUV +formats. + +Signed-off-by: Damian Hobson-Garcia <dhobsong@igel.co.jp> +Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit 85a0638b7855dfb00dc9b66bc2fdd4276d7dc87c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_rwpf.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/media/platform/vsp1/vsp1_rwpf.c b/drivers/media/platform/vsp1/vsp1_rwpf.c +index fa71f4695e16..9688c219b30e 100644 +--- a/drivers/media/platform/vsp1/vsp1_rwpf.c ++++ b/drivers/media/platform/vsp1/vsp1_rwpf.c +@@ -197,6 +197,17 @@ int vsp1_rwpf_set_selection(struct v4l2_subdev *subdev, + */ + format = vsp1_entity_get_pad_format(&rwpf->entity, cfg, RWPF_PAD_SINK, + sel->which); ++ ++ /* Restrict the crop rectangle coordinates to multiples of 2 to avoid ++ * shifting the color plane. ++ */ ++ if (format->code == MEDIA_BUS_FMT_AYUV8_1X32) { ++ sel->r.left = ALIGN(sel->r.left, 2); ++ sel->r.top = ALIGN(sel->r.top, 2); ++ sel->r.width = round_down(sel->r.width, 2); ++ sel->r.height = round_down(sel->r.height, 2); ++ } ++ + sel->r.left = min_t(unsigned int, sel->r.left, format->width - 2); + sel->r.top = min_t(unsigned int, sel->r.top, format->height - 2); + if (rwpf->entity.type == VSP1_ENTITY_WPF) { +-- +2.6.2 + diff --git a/patches.renesas/0264-media-vsp1-declar-vsp1_pipeline_stopped-as-static.patch b/patches.renesas/0264-media-vsp1-declar-vsp1_pipeline_stopped-as-static.patch new file mode 100644 index 00000000000000..ae081024cd3b21 --- /dev/null +++ b/patches.renesas/0264-media-vsp1-declar-vsp1_pipeline_stopped-as-static.patch @@ -0,0 +1,33 @@ +From 7925353d63560e02f3947dd65a247e0ac315e133 Mon Sep 17 00:00:00 2001 +From: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +Date: Fri, 3 Jul 2015 08:35:51 -0300 +Subject: [PATCH 264/326] [media] vsp1: declar vsp1_pipeline_stopped() as + static + +drivers/media/platform/vsp1/vsp1_video.c:517:6: warning: no previous prototype for 'vsp1_pipeline_stopped' [-Wmissing-prototypes] + bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe) + ^ + +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit 41bdc3cf81c4d0f0dfe09f06ff203dd59d422f37) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_video.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c +index c1b5a09b8331..770e08dc03f1 100644 +--- a/drivers/media/platform/vsp1/vsp1_video.c ++++ b/drivers/media/platform/vsp1/vsp1_video.c +@@ -514,7 +514,7 @@ static void vsp1_pipeline_run(struct vsp1_pipeline *pipe) + pipe->buffers_ready = 0; + } + +-bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe) ++static bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe) + { + unsigned long flags; + bool stopped; +-- +2.6.2 + diff --git a/patches.renesas/0265-media-v4l-vsp1-Fix-plane-stride-and-size-checks.patch b/patches.renesas/0265-media-v4l-vsp1-Fix-plane-stride-and-size-checks.patch new file mode 100644 index 00000000000000..ab91929e3db959 --- /dev/null +++ b/patches.renesas/0265-media-v4l-vsp1-Fix-plane-stride-and-size-checks.patch @@ -0,0 +1,35 @@ +From a54ffb63d059f1c3f39b86feb2f73bda9c73c45e Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 19 Jun 2015 08:51:22 -0300 +Subject: [PATCH 265/326] [media] v4l: vsp1: Fix plane stride and size checks + +The checks need to be performed on up to two planes, as the third plane, +if present, must have the same stride and size as the second plane. + +The code incorrectly performs the checks on at least two planes instead +of at most two planes, fix it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit df5c3e7c8a87a4384ff7a0adba16baae9a40a566) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_video.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c +index 770e08dc03f1..3c124c14ce14 100644 +--- a/drivers/media/platform/vsp1/vsp1_video.c ++++ b/drivers/media/platform/vsp1/vsp1_video.c +@@ -245,7 +245,7 @@ static int __vsp1_video_try_format(struct vsp1_video *video, + * the datasheet, strides not aligned to a multiple of 128 bytes result + * in image corruption. + */ +- for (i = 0; i < max(info->planes, 2U); ++i) { ++ for (i = 0; i < min(info->planes, 2U); ++i) { + unsigned int hsub = i > 0 ? info->hsub : 1; + unsigned int vsub = i > 0 ? info->vsub : 1; + unsigned int align = 128; +-- +2.6.2 + diff --git a/patches.renesas/0266-media-v4l-vsp1-Don-t-sleep-in-atomic-context.patch b/patches.renesas/0266-media-v4l-vsp1-Don-t-sleep-in-atomic-context.patch new file mode 100644 index 00000000000000..8c2357a71af6c1 --- /dev/null +++ b/patches.renesas/0266-media-v4l-vsp1-Don-t-sleep-in-atomic-context.patch @@ -0,0 +1,105 @@ +From 7d00fef15d5b02f05a6a3d77b8c3eb35a747194f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 13 Apr 2015 11:43:40 -0300 +Subject: [PATCH 266/326] [media] v4l: vsp1: Don't sleep in atomic context + +The vsp1_entity_is_streaming() function is called in atomic context when +queuing buffers, and sleeps due to a mutex. As the mutex just protects +access to one structure field, fix this by replace the mutex with a +spinlock. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> +(cherry picked from commit adb8963f27e00273c912a53f28f7af5d14cfd32e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_entity.c | 18 +++++++++--------- + drivers/media/platform/vsp1/vsp1_entity.h | 4 ++-- + 2 files changed, 11 insertions(+), 11 deletions(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c +index a453bb4ddd37..fd95a75b04f4 100644 +--- a/drivers/media/platform/vsp1/vsp1_entity.c ++++ b/drivers/media/platform/vsp1/vsp1_entity.c +@@ -24,22 +24,24 @@ + + bool vsp1_entity_is_streaming(struct vsp1_entity *entity) + { ++ unsigned long flags; + bool streaming; + +- mutex_lock(&entity->lock); ++ spin_lock_irqsave(&entity->lock, flags); + streaming = entity->streaming; +- mutex_unlock(&entity->lock); ++ spin_unlock_irqrestore(&entity->lock, flags); + + return streaming; + } + + int vsp1_entity_set_streaming(struct vsp1_entity *entity, bool streaming) + { ++ unsigned long flags; + int ret; + +- mutex_lock(&entity->lock); ++ spin_lock_irqsave(&entity->lock, flags); + entity->streaming = streaming; +- mutex_unlock(&entity->lock); ++ spin_unlock_irqrestore(&entity->lock, flags); + + if (!streaming) + return 0; +@@ -49,9 +51,9 @@ int vsp1_entity_set_streaming(struct vsp1_entity *entity, bool streaming) + + ret = v4l2_ctrl_handler_setup(entity->subdev.ctrl_handler); + if (ret < 0) { +- mutex_lock(&entity->lock); ++ spin_lock_irqsave(&entity->lock, flags); + entity->streaming = false; +- mutex_unlock(&entity->lock); ++ spin_unlock_irqrestore(&entity->lock, flags); + } + + return ret; +@@ -193,7 +195,7 @@ int vsp1_entity_init(struct vsp1_device *vsp1, struct vsp1_entity *entity, + if (i == ARRAY_SIZE(vsp1_routes)) + return -EINVAL; + +- mutex_init(&entity->lock); ++ spin_lock_init(&entity->lock); + + entity->vsp1 = vsp1; + entity->source_pad = num_pads - 1; +@@ -228,6 +230,4 @@ void vsp1_entity_destroy(struct vsp1_entity *entity) + if (entity->subdev.ctrl_handler) + v4l2_ctrl_handler_free(entity->subdev.ctrl_handler); + media_entity_cleanup(&entity->subdev.entity); +- +- mutex_destroy(&entity->lock); + } +diff --git a/drivers/media/platform/vsp1/vsp1_entity.h b/drivers/media/platform/vsp1/vsp1_entity.h +index 62c768d1c6aa..8867a5787c28 100644 +--- a/drivers/media/platform/vsp1/vsp1_entity.h ++++ b/drivers/media/platform/vsp1/vsp1_entity.h +@@ -14,7 +14,7 @@ + #define __VSP1_ENTITY_H__ + + #include <linux/list.h> +-#include <linux/mutex.h> ++#include <linux/spinlock.h> + + #include <media/v4l2-subdev.h> + +@@ -73,7 +73,7 @@ struct vsp1_entity { + + struct vsp1_video *video; + +- struct mutex lock; /* Protects the streaming field */ ++ spinlock_t lock; /* Protects the streaming field */ + bool streaming; + }; + +-- +2.6.2 + diff --git a/patches.renesas/0267-regmap-add-force_write-option-on-_regmap_update_bits.patch b/patches.renesas/0267-regmap-add-force_write-option-on-_regmap_update_bits.patch new file mode 100644 index 00000000000000..9c3939afc597f7 --- /dev/null +++ b/patches.renesas/0267-regmap-add-force_write-option-on-_regmap_update_bits.patch @@ -0,0 +1,96 @@ +From cbd44540cf6a79e65bc3d169395331cb56cd4bdf Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 16 Jun 2015 08:52:22 +0000 +Subject: [PATCH 267/326] regmap: add force_write option on + _regmap_update_bits() + +Sometimes we want to write data even though it doesn't change value. +Then, force_write option on _regmap_update_bits() helps this purpose. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 7ff0589c7bff4ca31b255ac2028f633f14047762) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/base/regmap/regmap.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c +index 1c76dcb502cf..7ede8165485b 100644 +--- a/drivers/base/regmap/regmap.c ++++ b/drivers/base/regmap/regmap.c +@@ -34,7 +34,7 @@ + + static int _regmap_update_bits(struct regmap *map, unsigned int reg, + unsigned int mask, unsigned int val, +- bool *change); ++ bool *change, bool force_write); + + static int _regmap_bus_reg_read(void *context, unsigned int reg, + unsigned int *val); +@@ -1178,7 +1178,7 @@ static int _regmap_select_page(struct regmap *map, unsigned int *reg, + ret = _regmap_update_bits(map, range->selector_reg, + range->selector_mask, + win_page << range->selector_shift, +- &page_chg); ++ &page_chg, false); + + map->work_buf = orig_work_buf; + +@@ -2327,7 +2327,7 @@ EXPORT_SYMBOL_GPL(regmap_bulk_read); + + static int _regmap_update_bits(struct regmap *map, unsigned int reg, + unsigned int mask, unsigned int val, +- bool *change) ++ bool *change, bool force_write) + { + int ret; + unsigned int tmp, orig; +@@ -2339,7 +2339,7 @@ static int _regmap_update_bits(struct regmap *map, unsigned int reg, + tmp = orig & ~mask; + tmp |= val & mask; + +- if (tmp != orig) { ++ if (force_write || (tmp != orig)) { + ret = _regmap_write(map, reg, tmp); + if (change) + *change = true; +@@ -2367,7 +2367,7 @@ int regmap_update_bits(struct regmap *map, unsigned int reg, + int ret; + + map->lock(map->lock_arg); +- ret = _regmap_update_bits(map, reg, mask, val, NULL); ++ ret = _regmap_update_bits(map, reg, mask, val, NULL, false); + map->unlock(map->lock_arg); + + return ret; +@@ -2398,7 +2398,7 @@ int regmap_update_bits_async(struct regmap *map, unsigned int reg, + + map->async = true; + +- ret = _regmap_update_bits(map, reg, mask, val, NULL); ++ ret = _regmap_update_bits(map, reg, mask, val, NULL, false); + + map->async = false; + +@@ -2427,7 +2427,7 @@ int regmap_update_bits_check(struct regmap *map, unsigned int reg, + int ret; + + map->lock(map->lock_arg); +- ret = _regmap_update_bits(map, reg, mask, val, change); ++ ret = _regmap_update_bits(map, reg, mask, val, change, false); + map->unlock(map->lock_arg); + return ret; + } +@@ -2460,7 +2460,7 @@ int regmap_update_bits_check_async(struct regmap *map, unsigned int reg, + + map->async = true; + +- ret = _regmap_update_bits(map, reg, mask, val, change); ++ ret = _regmap_update_bits(map, reg, mask, val, change, false); + + map->async = false; + +-- +2.6.2 + diff --git a/patches.renesas/0268-regmap-add-regmap_fields_force_write.patch b/patches.renesas/0268-regmap-add-regmap_fields_force_write.patch new file mode 100644 index 00000000000000..329d1df1f90004 --- /dev/null +++ b/patches.renesas/0268-regmap-add-regmap_fields_force_write.patch @@ -0,0 +1,57 @@ +From 0a22f2d62bcbc5759d9e3a9faa2a0a4c31454a21 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 16 Jun 2015 08:52:55 +0000 +Subject: [PATCH 268/326] regmap: add regmap_fields_force_write() + +regmap_fields_force_write() is similar to regmap_fields_write(), +but regmap_fields_force_write() write data to register even though +it is same value. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit e874e6c7edc43436f73cf84157d9221f8b807c36) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/base/regmap/regmap.c | 12 ++++++++++++ + include/linux/regmap.h | 2 ++ + 2 files changed, 14 insertions(+) + +diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c +index 7ede8165485b..35b05c2efc16 100644 +--- a/drivers/base/regmap/regmap.c ++++ b/drivers/base/regmap/regmap.c +@@ -1624,6 +1624,18 @@ int regmap_fields_write(struct regmap_field *field, unsigned int id, + } + EXPORT_SYMBOL_GPL(regmap_fields_write); + ++int regmap_fields_force_write(struct regmap_field *field, unsigned int id, ++ unsigned int val) ++{ ++ if (id >= field->id_size) ++ return -EINVAL; ++ ++ return regmap_write_bits(field->regmap, ++ field->reg + (field->id_offset * id), ++ field->mask, val << field->shift); ++} ++EXPORT_SYMBOL_GPL(regmap_fields_force_write); ++ + /** + * regmap_fields_update_bits(): Perform a read/modify/write cycle + * on the register field +diff --git a/include/linux/regmap.h b/include/linux/regmap.h +index 116655d92269..a4b13b4405f1 100644 +--- a/include/linux/regmap.h ++++ b/include/linux/regmap.h +@@ -501,6 +501,8 @@ int regmap_field_update_bits(struct regmap_field *field, + + int regmap_fields_write(struct regmap_field *field, unsigned int id, + unsigned int val); ++int regmap_fields_force_write(struct regmap_field *field, unsigned int id, ++ unsigned int val); + int regmap_fields_read(struct regmap_field *field, unsigned int id, + unsigned int *val); + int regmap_fields_update_bits(struct regmap_field *field, unsigned int id, +-- +2.6.2 + diff --git a/patches.renesas/0269-regmap-add-regmap_write_bits.patch b/patches.renesas/0269-regmap-add-regmap_write_bits.patch new file mode 100644 index 00000000000000..9800ebca2f0496 --- /dev/null +++ b/patches.renesas/0269-regmap-add-regmap_write_bits.patch @@ -0,0 +1,82 @@ +From 42b5e4f23e2df4314c297bf0b7a0a20385ce4198 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 16 Jun 2015 08:52:39 +0000 +Subject: [PATCH 269/326] regmap: add regmap_write_bits() + +regmap_write_bits() is similar to regmap_update_bits(), +but regmap_write_bits() write data to register even though +it is same value. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit fd4b7286ccc469bf5dde22db6b8fcc455c3c4a66) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/base/regmap/regmap.c | 23 +++++++++++++++++++++++ + include/linux/regmap.h | 9 +++++++++ + 2 files changed, 32 insertions(+) + +diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c +index 35b05c2efc16..fc26b61eba6a 100644 +--- a/drivers/base/regmap/regmap.c ++++ b/drivers/base/regmap/regmap.c +@@ -2387,6 +2387,29 @@ int regmap_update_bits(struct regmap *map, unsigned int reg, + EXPORT_SYMBOL_GPL(regmap_update_bits); + + /** ++ * regmap_write_bits: Perform a read/modify/write cycle on the register map ++ * ++ * @map: Register map to update ++ * @reg: Register to update ++ * @mask: Bitmask to change ++ * @val: New value for bitmask ++ * ++ * Returns zero for success, a negative number on error. ++ */ ++int regmap_write_bits(struct regmap *map, unsigned int reg, ++ unsigned int mask, unsigned int val) ++{ ++ int ret; ++ ++ map->lock(map->lock_arg); ++ ret = _regmap_update_bits(map, reg, mask, val, NULL, true); ++ map->unlock(map->lock_arg); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(regmap_write_bits); ++ ++/** + * regmap_update_bits_async: Perform a read/modify/write cycle on the register + * map asynchronously + * +diff --git a/include/linux/regmap.h b/include/linux/regmap.h +index a4b13b4405f1..06206311b1af 100644 +--- a/include/linux/regmap.h ++++ b/include/linux/regmap.h +@@ -424,6 +424,8 @@ int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val, + size_t val_count); + int regmap_update_bits(struct regmap *map, unsigned int reg, + unsigned int mask, unsigned int val); ++int regmap_write_bits(struct regmap *map, unsigned int reg, ++ unsigned int mask, unsigned int val); + int regmap_update_bits_async(struct regmap *map, unsigned int reg, + unsigned int mask, unsigned int val); + int regmap_update_bits_check(struct regmap *map, unsigned int reg, +@@ -645,6 +647,13 @@ static inline int regmap_update_bits(struct regmap *map, unsigned int reg, + return -EINVAL; + } + ++static inline int regmap_write_bits(struct regmap *map, unsigned int reg, ++ unsigned int mask, unsigned int val) ++{ ++ WARN_ONCE(1, "regmap API is disabled"); ++ return -EINVAL; ++} ++ + static inline int regmap_update_bits_async(struct regmap *map, + unsigned int reg, + unsigned int mask, unsigned int val) +-- +2.6.2 + diff --git a/patches.renesas/0270-clockevents-drivers-sh_cmt-Remove-obsolete-sh-cmt-48.patch b/patches.renesas/0270-clockevents-drivers-sh_cmt-Remove-obsolete-sh-cmt-48.patch new file mode 100644 index 00000000000000..3347a61bb88780 --- /dev/null +++ b/patches.renesas/0270-clockevents-drivers-sh_cmt-Remove-obsolete-sh-cmt-48.patch @@ -0,0 +1,37 @@ +From 0309bdd92b8e90e9913cda5c01b53b994708c5ed Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 14 Jul 2015 14:00:47 +0200 +Subject: [PATCH 270/326] clockevents/drivers/sh_cmt: Remove obsolete sh-cmt-48 + platform_device_id entry + +Since the removal of the r8a7740 legacy SoC code in commit +44d88c754e57a6d9 ("ARM: shmobile: Remove legacy SoC code for R-Mobile +A1"), all former users of the "sh-cmt-48-gen2" platform device name are +only supported in generic DT-only ARM multi-platform builds. The driver +doesn't need to match platform devices by name anymore, hence remove the +corresponding platform_device_id entry. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8c436f84800c570ecde517dcd8709258bb34e498) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clocksource/sh_cmt.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c +index d56d4e0e3fb3..7e4cd3473c72 100644 +--- a/drivers/clocksource/sh_cmt.c ++++ b/drivers/clocksource/sh_cmt.c +@@ -929,7 +929,6 @@ static int sh_cmt_map_memory(struct sh_cmt_device *cmt) + static const struct platform_device_id sh_cmt_id_table[] = { + { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, + { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, +- { "sh-cmt-48", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT] }, + { } + }; + MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); +-- +2.6.2 + diff --git a/patches.renesas/0271-pinctrl-sh-pfc-Remove-obsolete-sh73a0-platform_devic.patch b/patches.renesas/0271-pinctrl-sh-pfc-Remove-obsolete-sh73a0-platform_devic.patch new file mode 100644 index 00000000000000..a399d0b663c4a5 --- /dev/null +++ b/patches.renesas/0271-pinctrl-sh-pfc-Remove-obsolete-sh73a0-platform_devic.patch @@ -0,0 +1,39 @@ +From 92f0fccd7d36a6ca7732cb1dc462ef2b5e8804b8 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 14 Jul 2015 13:56:53 +0200 +Subject: [PATCH 271/326] pinctrl: sh-pfc: Remove obsolete sh73a0 + platform_device_id entry + +Since the removal of the sh73a0 legacy SoC code in commit +9a9863987bf7307f ("ARM: shmobile: Remove legacy SoC code for SH-Mobile +AG5"), sh73a0 is only supported in generic DT-only ARM multi-platform +builds. The driver doesn't need to match platform devices by name +anymore, hence remove the corresponding platform_device_id entry. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 39ad6ff12cd54607b64642562ad850bb09176734) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index 979623895904..23b2b3be26fd 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -605,9 +605,6 @@ static const struct platform_device_id sh_pfc_id_table[] = { + #ifdef CONFIG_PINCTRL_PFC_SH7269 + { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, + #endif +-#ifdef CONFIG_PINCTRL_PFC_SH73A0 +- { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info }, +-#endif + #ifdef CONFIG_PINCTRL_PFC_SH7720 + { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info }, + #endif +-- +2.6.2 + diff --git a/patches.renesas/0272-pinctrl-sh-pfc-Remove-obsolete-r8a7740-platform_devi.patch b/patches.renesas/0272-pinctrl-sh-pfc-Remove-obsolete-r8a7740-platform_devi.patch new file mode 100644 index 00000000000000..38d66fdcbae952 --- /dev/null +++ b/patches.renesas/0272-pinctrl-sh-pfc-Remove-obsolete-r8a7740-platform_devi.patch @@ -0,0 +1,39 @@ +From b98300166176e11d1b3b5e3c14d021e91ddd1187 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 14 Jul 2015 13:56:55 +0200 +Subject: [PATCH 272/326] pinctrl: sh-pfc: Remove obsolete r8a7740 + platform_device_id entry + +Since the removal of the r8a7740 legacy SoC code in commit +44d88c754e57a6d9 ("ARM: shmobile: Remove legacy SoC code for R-Mobile +A1"), r8a7740 is only supported in generic DT-only ARM multi-platform +builds. The driver doesn't need to match platform devices by name +anymore, hence remove the corresponding platform_device_id entry. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 03c42c3e5216e2777f8ae819d6a076e94dcdfbdd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index 23b2b3be26fd..fb9c44805234 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -587,9 +587,6 @@ static int sh_pfc_remove(struct platform_device *pdev) + } + + static const struct platform_device_id sh_pfc_id_table[] = { +-#ifdef CONFIG_PINCTRL_PFC_R8A7740 +- { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, +-#endif + #ifdef CONFIG_PINCTRL_PFC_R8A7778 + { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info }, + #endif +-- +2.6.2 + diff --git a/patches.renesas/0273-pinctrl-sh-pfc-Implement-pinconf-power-source-param-.patch b/patches.renesas/0273-pinctrl-sh-pfc-Implement-pinconf-power-source-param-.patch new file mode 100644 index 00000000000000..e3977e9a55353b --- /dev/null +++ b/patches.renesas/0273-pinctrl-sh-pfc-Implement-pinconf-power-source-param-.patch @@ -0,0 +1,156 @@ +From b82cf411b6fcd84540d9ecf45da2bfca76e23290 Mon Sep 17 00:00:00 2001 +From: Ben Hutchings <ben.hutchings@codethink.co.uk> +Date: Tue, 30 Jun 2015 17:53:59 +0100 +Subject: [PATCH 273/326] pinctrl: sh-pfc: Implement pinconf power-source param + for voltage switching + +The pfc in the R8A7790 (and probably others in the R-Car gen 2 family) +supports switching SDHI signals between 3.3V and 1.8V nominal voltage, +and the SD driver should do that when switching to and from UHS modes. + +Add a flag for pins that have configurable I/O voltage and SoC +operations to get and set the nominal voltage. Implement the pinconf +power-source parameter using these operations. + +Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 5b9eaa5659b32cf6c85a492d2e3bfa7a3a413144) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 4 +- + drivers/pinctrl/sh-pfc/pinctrl.c | 44 +++++++++++++++++++++- + drivers/pinctrl/sh-pfc/sh_pfc.h | 5 +++ + 3 files changed, 50 insertions(+), 3 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +index e089142cfb14..9496934528bd 100644 +--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +@@ -71,7 +71,9 @@ Pin Configuration Node Properties: + + The pin configuration parameters use the generic pinconf bindings defined in + pinctrl-bindings.txt in this directory. The supported parameters are +-bias-disable, bias-pull-up and bias-pull-down. ++bias-disable, bias-pull-up, bias-pull-down and power-source. For pins that ++have a configurable I/O voltage, the power-source value should be the ++nominal I/O voltage in millivolts. + + + GPIO +diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c +index 6fe7459f0ccb..863c3e30ce05 100644 +--- a/drivers/pinctrl/sh-pfc/pinctrl.c ++++ b/drivers/pinctrl/sh-pfc/pinctrl.c +@@ -491,6 +491,9 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, + case PIN_CONFIG_BIAS_PULL_DOWN: + return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; + ++ case PIN_CONFIG_POWER_SOURCE: ++ return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE; ++ + default: + return false; + } +@@ -503,7 +506,6 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, + struct sh_pfc *pfc = pmx->pfc; + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned long flags; +- unsigned int bias; + + if (!sh_pfc_pinconf_validate(pfc, _pin, param)) + return -ENOTSUPP; +@@ -511,7 +513,9 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: +- case PIN_CONFIG_BIAS_PULL_DOWN: ++ case PIN_CONFIG_BIAS_PULL_DOWN: { ++ unsigned int bias; ++ + if (!pfc->info->ops || !pfc->info->ops->get_bias) + return -ENOTSUPP; + +@@ -524,6 +528,24 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, + + *config = 0; + break; ++ } ++ ++ case PIN_CONFIG_POWER_SOURCE: { ++ int ret; ++ ++ if (!pfc->info->ops || !pfc->info->ops->get_io_voltage) ++ return -ENOTSUPP; ++ ++ spin_lock_irqsave(&pfc->lock, flags); ++ ret = pfc->info->ops->get_io_voltage(pfc, _pin); ++ spin_unlock_irqrestore(&pfc->lock, flags); ++ ++ if (ret < 0) ++ return ret; ++ ++ *config = ret; ++ break; ++ } + + default: + return -ENOTSUPP; +@@ -560,6 +582,24 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, + + break; + ++ case PIN_CONFIG_POWER_SOURCE: { ++ unsigned int arg = ++ pinconf_to_config_argument(configs[i]); ++ int ret; ++ ++ if (!pfc->info->ops || !pfc->info->ops->set_io_voltage) ++ return -ENOTSUPP; ++ ++ spin_lock_irqsave(&pfc->lock, flags); ++ ret = pfc->info->ops->set_io_voltage(pfc, _pin, arg); ++ spin_unlock_irqrestore(&pfc->lock, flags); ++ ++ if (ret) ++ return ret; ++ ++ break; ++ } ++ + default: + return -ENOTSUPP; + } +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index 0874cfee6889..15afd49fd4e3 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -12,6 +12,7 @@ + #define __SH_PFC_H + + #include <linux/bug.h> ++#include <linux/pinctrl/pinconf-generic.h> + #include <linux/stringify.h> + + enum { +@@ -26,6 +27,7 @@ enum { + #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) + #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) + #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) ++#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) + #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) + + struct sh_pfc_pin { +@@ -121,6 +123,9 @@ struct sh_pfc_soc_operations { + unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); + void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias); ++ int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin); ++ int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin, ++ u16 voltage_mV); + }; + + struct sh_pfc_soc_info { +-- +2.6.2 + diff --git a/patches.renesas/0274-pinctrl-sh-pfc-r8a7794-add-USB-pin-groups.patch b/patches.renesas/0274-pinctrl-sh-pfc-r8a7794-add-USB-pin-groups.patch new file mode 100644 index 00000000000000..d8128e394b976e --- /dev/null +++ b/patches.renesas/0274-pinctrl-sh-pfc-r8a7794-add-USB-pin-groups.patch @@ -0,0 +1,84 @@ +From 576bc8579c4d0f4e2693071a5c368f6b9d86db44 Mon Sep 17 00:00:00 2001 +From: Shinobu Uehara <shinobu.uehara.xc@renesas.com> +Date: Wed, 19 Aug 2015 01:26:55 +0300 +Subject: [PATCH 274/326] pinctrl: sh-pfc: r8a7794: add USB pin groups + +Add USB0/1 pin groups to R8A7794 PFC driver. + +Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> +[Sergei: rebased, renamed, added changelog.] +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> + +(cherry picked from commit 580a7ee93317b901358f497c2de34f7a66066963) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 30 ++++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +index bfdcac4b3bc4..5248685dbb4e 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +@@ -2770,6 +2770,24 @@ static const unsigned int sdhi2_wp_pins[] = { + static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, + }; ++/* - USB0 ------------------------------------------------------------------- */ ++static const unsigned int usb0_pins[] = { ++ RCAR_GP_PIN(5, 24), /* PWEN */ ++ RCAR_GP_PIN(5, 25), /* OVC */ ++}; ++static const unsigned int usb0_mux[] = { ++ USB0_PWEN_MARK, ++ USB0_OVC_MARK, ++}; ++/* - USB1 ------------------------------------------------------------------- */ ++static const unsigned int usb1_pins[] = { ++ RCAR_GP_PIN(5, 26), /* PWEN */ ++ RCAR_GP_PIN(5, 27), /* OVC */ ++}; ++static const unsigned int usb1_mux[] = { ++ USB1_PWEN_MARK, ++ USB1_OVC_MARK, ++}; + + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), +@@ -2945,6 +2963,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), ++ SH_PFC_PIN_GROUP(usb0), ++ SH_PFC_PIN_GROUP(usb1), + }; + + static const char * const eth_groups[] = { +@@ -3219,6 +3239,14 @@ static const char * const sdhi2_groups[] = { + "sdhi2_wp", + }; + ++static const char * const usb0_groups[] = { ++ "usb0", ++}; ++ ++static const char * const usb1_groups[] = { ++ "usb1", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), +@@ -3253,6 +3281,8 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), ++ SH_PFC_FUNCTION(usb0), ++ SH_PFC_FUNCTION(usb1), + }; + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +2.6.2 + diff --git a/patches.renesas/0275-ASoC-core-add-snd_soc_of_parse_audio_prefix.patch b/patches.renesas/0275-ASoC-core-add-snd_soc_of_parse_audio_prefix.patch new file mode 100644 index 00000000000000..701c8eeb496a02 --- /dev/null +++ b/patches.renesas/0275-ASoC-core-add-snd_soc_of_parse_audio_prefix.patch @@ -0,0 +1,61 @@ +From 081296bb8980bb9ec6484d20fc92b2e74a8fae8a Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:07:42 +0000 +Subject: [PATCH 275/326] ASoC: core: add snd_soc_of_parse_audio_prefix() + +Current ASoC can add name_prefix for DAPM, and it is necessary for +route settings. This patch adds snd_soc_of_parse_audio_prefix() for +this purpose. It will be used with snd_soc_of_parse_audio_routing(). + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 5e3cdaa20816dd2fe4dc17d06a9f0dae0abc930c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/sound/soc.h | 4 ++++ + sound/soc/soc-core.c | 20 ++++++++++++++++++++ + 2 files changed, 24 insertions(+) + +--- a/include/sound/soc.h ++++ b/include/sound/soc.h +@@ -1533,6 +1533,10 @@ int snd_soc_of_parse_audio_simple_widget + int snd_soc_of_parse_tdm_slot(struct device_node *np, + unsigned int *slots, + unsigned int *slot_width); ++void snd_soc_of_parse_audio_prefix(struct snd_soc_card *card, ++ struct snd_soc_codec_conf *codec_conf, ++ struct device_node *of_node, ++ const char *propname); + int snd_soc_of_parse_audio_routing(struct snd_soc_card *card, + const char *propname); + unsigned int snd_soc_of_parse_daifmt(struct device_node *np, +--- a/sound/soc/soc-core.c ++++ b/sound/soc/soc-core.c +@@ -3315,6 +3315,26 @@ int snd_soc_of_parse_tdm_slot(struct dev + } + EXPORT_SYMBOL_GPL(snd_soc_of_parse_tdm_slot); + ++void snd_soc_of_parse_audio_prefix(struct snd_soc_card *card, ++ struct snd_soc_codec_conf *codec_conf, ++ struct device_node *of_node, ++ const char *propname) ++{ ++ struct device_node *np = card->dev->of_node; ++ const char *str; ++ int ret; ++ ++ ret = of_property_read_string(np, propname, &str); ++ if (ret < 0) { ++ /* no prefix is not error */ ++ return; ++ } ++ ++ codec_conf->of_node = of_node; ++ codec_conf->name_prefix = str; ++} ++EXPORT_SYMBOL_GPL(snd_soc_of_parse_audio_prefix); ++ + int snd_soc_of_parse_audio_routing(struct snd_soc_card *card, + const char *propname) + { diff --git a/patches.renesas/0276-ASoC-rsnd-gen-add-rsnd_force_write.patch b/patches.renesas/0276-ASoC-rsnd-gen-add-rsnd_force_write.patch new file mode 100644 index 00000000000000..619259f42cee82 --- /dev/null +++ b/patches.renesas/0276-ASoC-rsnd-gen-add-rsnd_force_write.patch @@ -0,0 +1,69 @@ +From a1afd3650ad69f5e5ed1711a2d33d5e443b1c24b Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 16 Jun 2015 08:53:11 +0000 +Subject: [PATCH 276/326] ASoC: rsnd: gen: add rsnd_force_write() + +rsnd_force_write() is similar to rsnd_write(), +but rsnd_force_write() write data to register even though +it is same value. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 7b47ab47b3938e2274834dbde7915df98fc74368) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/gen.c | 16 ++++++++++++++++ + sound/soc/sh/rcar/rsnd.h | 4 ++++ + 2 files changed, 20 insertions(+) + +diff --git a/sound/soc/sh/rcar/gen.c b/sound/soc/sh/rcar/gen.c +index 8c7dc51b1c4f..48f704b1d80e 100644 +--- a/sound/soc/sh/rcar/gen.c ++++ b/sound/soc/sh/rcar/gen.c +@@ -103,6 +103,22 @@ void rsnd_write(struct rsnd_priv *priv, + regmap_fields_write(gen->regs[reg], rsnd_mod_id(mod), data); + } + ++void rsnd_force_write(struct rsnd_priv *priv, ++ struct rsnd_mod *mod, ++ enum rsnd_reg reg, u32 data) ++{ ++ struct device *dev = rsnd_priv_to_dev(priv); ++ struct rsnd_gen *gen = rsnd_priv_to_gen(priv); ++ ++ if (!rsnd_is_accessible_reg(priv, gen, reg)) ++ return; ++ ++ dev_dbg(dev, "w %s[%d] - %4d : %08x\n", ++ rsnd_mod_name(mod), rsnd_mod_id(mod), reg, data); ++ ++ regmap_fields_force_write(gen->regs[reg], rsnd_mod_id(mod), data); ++} ++ + void rsnd_bset(struct rsnd_priv *priv, struct rsnd_mod *mod, + enum rsnd_reg reg, u32 mask, u32 data) + { +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 09fcc54a8ee0..f729646e3d18 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -157,12 +157,16 @@ struct rsnd_dai_stream; + rsnd_read(rsnd_mod_to_priv(m), m, RSND_REG_##r) + #define rsnd_mod_write(m, r, d) \ + rsnd_write(rsnd_mod_to_priv(m), m, RSND_REG_##r, d) ++#define rsnd_mod_force_write(m, r, d) \ ++ rsnd_force_write(rsnd_mod_to_priv(m), m, RSND_REG_##r, d) + #define rsnd_mod_bset(m, r, s, d) \ + rsnd_bset(rsnd_mod_to_priv(m), m, RSND_REG_##r, s, d) + + u32 rsnd_read(struct rsnd_priv *priv, struct rsnd_mod *mod, enum rsnd_reg reg); + void rsnd_write(struct rsnd_priv *priv, struct rsnd_mod *mod, + enum rsnd_reg reg, u32 data); ++void rsnd_force_write(struct rsnd_priv *priv, struct rsnd_mod *mod, ++ enum rsnd_reg reg, u32 data); + void rsnd_bset(struct rsnd_priv *priv, struct rsnd_mod *mod, enum rsnd_reg reg, + u32 mask, u32 data); + u32 rsnd_get_adinr(struct rsnd_mod *mod, struct rsnd_dai_stream *io); +-- +2.6.2 + diff --git a/patches.renesas/0277-ASoC-rsrc-card-use-snd_soc_of_parse_audio_route-pref.patch b/patches.renesas/0277-ASoC-rsrc-card-use-snd_soc_of_parse_audio_route-pref.patch new file mode 100644 index 00000000000000..7cbc4cf368b958 --- /dev/null +++ b/patches.renesas/0277-ASoC-rsrc-card-use-snd_soc_of_parse_audio_route-pref.patch @@ -0,0 +1,94 @@ +From 4769738e07a981f356df3b1c212049ade0171e00 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:08:05 +0000 +Subject: [PATCH 277/326] ASoC: rsrc-card: use + snd_soc_of_parse_audio_route/prefix for routing + +using common audio routing path method makes sense. +Let's use snd_soc_of_parse_audio_route/prefix. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit b7419dd73606118b8797d49b53a9fbe2e2dfa863) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/sound/renesas,rsrc-card.txt | 7 +++++++ + sound/soc/sh/rcar/rsrc-card.c | 22 ++++++++++++++++++---- + 2 files changed, 25 insertions(+), 4 deletions(-) + +diff --git a/Documentation/devicetree/bindings/sound/renesas,rsrc-card.txt b/Documentation/devicetree/bindings/sound/renesas,rsrc-card.txt +index c64155027288..962748a8d919 100644 +--- a/Documentation/devicetree/bindings/sound/renesas,rsrc-card.txt ++++ b/Documentation/devicetree/bindings/sound/renesas,rsrc-card.txt +@@ -6,6 +6,7 @@ Required properties: + + - compatible : "renesas,rsrc-card,<board>" + Examples with soctypes are: ++ - "renesas,rsrc-card" + - "renesas,rsrc-card,lager" + - "renesas,rsrc-card,koelsch" + Optional properties: +@@ -29,6 +30,12 @@ Optional subnode properties: + - frame-inversion : bool property. Add this if the + dai-link uses frame clock inversion. + - convert-rate : platform specified sampling rate convert ++- audio-prefix : see audio-routing ++- audio-routing : A list of the connections between audio components. ++ Each entry is a pair of strings, the first being the connection's sink, ++ the second being the connection's source. Valid names for sources. ++ use audio-prefix if some components is using same sink/sources naming. ++ it can be used if compatible was "renesas,rsrc-card"; + + Required CPU/CODEC subnodes properties: + +diff --git a/sound/soc/sh/rcar/rsrc-card.c b/sound/soc/sh/rcar/rsrc-card.c +index 84e935711e29..d61db9c385ea 100644 +--- a/sound/soc/sh/rcar/rsrc-card.c ++++ b/sound/soc/sh/rcar/rsrc-card.c +@@ -41,6 +41,7 @@ static const struct rsrc_card_of_data routes_of_ssi0_ak4642 = { + static const struct of_device_id rsrc_card_of_match[] = { + { .compatible = "renesas,rsrc-card,lager", .data = &routes_of_ssi0_ak4642 }, + { .compatible = "renesas,rsrc-card,koelsch", .data = &routes_of_ssi0_ak4642 }, ++ { .compatible = "renesas,rsrc-card", }, + {}, + }; + MODULE_DEVICE_TABLE(of, rsrc_card_of_match); +@@ -242,8 +243,15 @@ static int rsrc_card_parse_links(struct device_node *np, + snd_soc_of_get_dai_name(np, &dai_link->codec_dai_name); + + /* additional name prefix */ +- priv->codec_conf.of_node = dai_link->codec_of_node; +- priv->codec_conf.name_prefix = of_data->prefix; ++ if (of_data) { ++ priv->codec_conf.of_node = dai_link->codec_of_node; ++ priv->codec_conf.name_prefix = of_data->prefix; ++ } else { ++ snd_soc_of_parse_audio_prefix(&priv->snd_card, ++ &priv->codec_conf, ++ dai_link->codec_of_node, ++ "audio-prefix"); ++ } + + /* set dai_name */ + snprintf(dai_props->dai_name, DAI_NAME_NUM, "be.%s", +@@ -361,8 +369,14 @@ static int rsrc_card_parse_of(struct device_node *node, + priv->snd_card.num_links = num; + priv->snd_card.codec_conf = &priv->codec_conf; + priv->snd_card.num_configs = 1; +- priv->snd_card.of_dapm_routes = of_data->routes; +- priv->snd_card.num_of_dapm_routes = of_data->num_routes; ++ ++ if (of_data) { ++ priv->snd_card.of_dapm_routes = of_data->routes; ++ priv->snd_card.num_of_dapm_routes = of_data->num_routes; ++ } else { ++ snd_soc_of_parse_audio_routing(&priv->snd_card, ++ "audio-routing"); ++ } + + /* Parse the card name from DT */ + snd_soc_of_parse_card_name(&priv->snd_card, "card-name"); +-- +2.6.2 + diff --git a/patches.renesas/0278-ASoC-rsnd-remove-unnecessary-out-of-memory-message-f.patch b/patches.renesas/0278-ASoC-rsnd-remove-unnecessary-out-of-memory-message-f.patch new file mode 100644 index 00000000000000..7eb6e33a51dc2a --- /dev/null +++ b/patches.renesas/0278-ASoC-rsnd-remove-unnecessary-out-of-memory-message-f.patch @@ -0,0 +1,37 @@ +From 0dedb39e95a50153ad5397183c8af479030adc46 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:08:24 +0000 +Subject: [PATCH 278/326] ASoC: rsnd: remove unnecessary 'out of memory' + message from SSI + +Current checkpatch.pl indicates 'out of memory' message is unnecessary. +Let's remove it + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit afa700729646761f58cc068d86a37e09a70e4cf6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/ssi.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c +index 2fbe59f7f9b5..d45b9a7e324e 100644 +--- a/sound/soc/sh/rcar/ssi.c ++++ b/sound/soc/sh/rcar/ssi.c +@@ -770,10 +770,8 @@ int rsnd_ssi_probe(struct platform_device *pdev, + */ + nr = info->ssi_info_nr; + ssi = devm_kzalloc(dev, sizeof(*ssi) * nr, GFP_KERNEL); +- if (!ssi) { +- dev_err(dev, "SSI allocate failed\n"); ++ if (!ssi) + return -ENOMEM; +- } + + priv->ssi = ssi; + priv->ssi_nr = nr; +-- +2.6.2 + diff --git a/patches.renesas/0279-ASoC-rsnd-remove-unnecessary-out-of-memory-message-f.patch b/patches.renesas/0279-ASoC-rsnd-remove-unnecessary-out-of-memory-message-f.patch new file mode 100644 index 00000000000000..e7f32016ecf48b --- /dev/null +++ b/patches.renesas/0279-ASoC-rsnd-remove-unnecessary-out-of-memory-message-f.patch @@ -0,0 +1,37 @@ +From bb5d029371c27570d35d17509296e98af9d26f4f Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:08:44 +0000 +Subject: [PATCH 279/326] ASoC: rsnd: remove unnecessary 'out of memory' + message from SRC + +Current checkpatch.pl indicates 'out of memory' message is unnecessary. +Let's remove it + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 33363f7a18f3baaa04b678aac8819c43296c8c9c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/src.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c +index c61c17180142..37927ca66162 100644 +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -1047,10 +1047,8 @@ int rsnd_src_probe(struct platform_device *pdev, + return 0; + + src = devm_kzalloc(dev, sizeof(*src) * nr, GFP_KERNEL); +- if (!src) { +- dev_err(dev, "SRC allocate failed\n"); ++ if (!src) + return -ENOMEM; +- } + + priv->src_nr = nr; + priv->src = src; +-- +2.6.2 + diff --git a/patches.renesas/0280-ASoC-rsnd-remove-unnecessary-out-of-memory-message-f.patch b/patches.renesas/0280-ASoC-rsnd-remove-unnecessary-out-of-memory-message-f.patch new file mode 100644 index 00000000000000..07d99c719f8b97 --- /dev/null +++ b/patches.renesas/0280-ASoC-rsnd-remove-unnecessary-out-of-memory-message-f.patch @@ -0,0 +1,37 @@ +From 8dd0d6fa9fa8248aeb47f15b4aaad4d3f9d5174a Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:09:07 +0000 +Subject: [PATCH 280/326] ASoC: rsnd: remove unnecessary 'out of memory' + message from DVC + +Current checkpatch.pl indicates 'out of memory' message is unnecessary. +Let's remove it + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 6abcae32ea68899bfd4b770433860a71f8c3500b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/dvc.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c +index 36fc020cbc18..dbf0da6ce8a5 100644 +--- a/sound/soc/sh/rcar/dvc.c ++++ b/sound/soc/sh/rcar/dvc.c +@@ -354,10 +354,8 @@ int rsnd_dvc_probe(struct platform_device *pdev, + } + + dvc = devm_kzalloc(dev, sizeof(*dvc) * nr, GFP_KERNEL); +- if (!dvc) { +- dev_err(dev, "CMD allocate failed\n"); ++ if (!dvc) + return -ENOMEM; +- } + + priv->dvc_nr = nr; + priv->dvc = dvc; +-- +2.6.2 + diff --git a/patches.renesas/0281-ASoC-rsnd-rename-BUSIF_DALIGN-to-SSI_BUSIF_DALIGN.patch b/patches.renesas/0281-ASoC-rsnd-rename-BUSIF_DALIGN-to-SSI_BUSIF_DALIGN.patch new file mode 100644 index 00000000000000..7612e437183ade --- /dev/null +++ b/patches.renesas/0281-ASoC-rsnd-rename-BUSIF_DALIGN-to-SSI_BUSIF_DALIGN.patch @@ -0,0 +1,60 @@ +From a15f8dc9a529a48fa6c8cc4bfa0668f39f16be8d Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:09:27 +0000 +Subject: [PATCH 281/326] ASoC: rsnd: rename BUSIF_DALIGN to SSI_BUSIF_DALIGN + +based on datasheet + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit cdde84d10d3cb4d35051bc5fdb268f6faf33d1c8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/gen.c | 2 +- + sound/soc/sh/rcar/rsnd.h | 2 +- + sound/soc/sh/rcar/src.c | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/sound/soc/sh/rcar/gen.c b/sound/soc/sh/rcar/gen.c +index 48f704b1d80e..9dc1968d6f37 100644 +--- a/sound/soc/sh/rcar/gen.c ++++ b/sound/soc/sh/rcar/gen.c +@@ -216,7 +216,7 @@ static int rsnd_gen2_probe(struct platform_device *pdev, + /* FIXME: it needs SSI_MODE2/3 in the future */ + RSND_GEN_M_REG(SSI_BUSIF_MODE, 0x0, 0x80), + RSND_GEN_M_REG(SSI_BUSIF_ADINR, 0x4, 0x80), +- RSND_GEN_M_REG(BUSIF_DALIGN, 0x8, 0x80), ++ RSND_GEN_M_REG(SSI_BUSIF_DALIGN,0x8, 0x80), + RSND_GEN_M_REG(SSI_CTRL, 0x10, 0x80), + RSND_GEN_M_REG(INT_ENABLE, 0x18, 0x80), + }; +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index f729646e3d18..f49b0cb1f5a2 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -136,7 +136,7 @@ enum rsnd_reg { + #define RSND_REG_AUDIO_CLK_SEL2 RSND_REG_SHARE19 + #define RSND_REG_CMD_CTRL RSND_REG_SHARE20 + #define RSND_REG_CMDOUT_TIMSEL RSND_REG_SHARE21 +-#define RSND_REG_BUSIF_DALIGN RSND_REG_SHARE22 ++#define RSND_REG_SSI_BUSIF_DALIGN RSND_REG_SHARE22 + #define RSND_REG_DVC_VRCTR RSND_REG_SHARE23 + #define RSND_REG_DVC_VRPDR RSND_REG_SHARE24 + #define RSND_REG_DVC_VRDBR RSND_REG_SHARE25 +diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c +index 37927ca66162..3f6f4df7318d 100644 +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -189,7 +189,7 @@ int rsnd_src_ssiu_start(struct rsnd_mod *ssi_mod, + val |= 0x76543210 & ~mask; + break; + } +- rsnd_mod_write(ssi_mod, BUSIF_DALIGN, val); ++ rsnd_mod_write(ssi_mod, SSI_BUSIF_DALIGN, val); + + } + +-- +2.6.2 + diff --git a/patches.renesas/0282-ASoC-rsnd-rename-INT_ENABLE-to-SSI_INT_ENABLE.patch b/patches.renesas/0282-ASoC-rsnd-rename-INT_ENABLE-to-SSI_INT_ENABLE.patch new file mode 100644 index 00000000000000..e322cf4214b7a3 --- /dev/null +++ b/patches.renesas/0282-ASoC-rsnd-rename-INT_ENABLE-to-SSI_INT_ENABLE.patch @@ -0,0 +1,74 @@ +From 89d31675d0c645ae1192ff570ae22a25f0c9928f Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:09:47 +0000 +Subject: [PATCH 282/326] ASoC: rsnd: rename INT_ENABLE to SSI_INT_ENABLE + +based on datasheet + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit efa991dc9143815179fd55a88e846cc39792608c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/gen.c | 2 +- + sound/soc/sh/rcar/rsnd.h | 2 +- + sound/soc/sh/rcar/src.c | 9 ++++----- + 3 files changed, 6 insertions(+), 7 deletions(-) + +diff --git a/sound/soc/sh/rcar/gen.c b/sound/soc/sh/rcar/gen.c +index 9dc1968d6f37..5d3592dfc382 100644 +--- a/sound/soc/sh/rcar/gen.c ++++ b/sound/soc/sh/rcar/gen.c +@@ -218,7 +218,7 @@ static int rsnd_gen2_probe(struct platform_device *pdev, + RSND_GEN_M_REG(SSI_BUSIF_ADINR, 0x4, 0x80), + RSND_GEN_M_REG(SSI_BUSIF_DALIGN,0x8, 0x80), + RSND_GEN_M_REG(SSI_CTRL, 0x10, 0x80), +- RSND_GEN_M_REG(INT_ENABLE, 0x18, 0x80), ++ RSND_GEN_M_REG(SSI_INT_ENABLE, 0x18, 0x80), + }; + struct rsnd_regmap_field_conf conf_scu[] = { + RSND_GEN_M_REG(SRC_BUSIF_MODE, 0x0, 0x20), +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index f49b0cb1f5a2..9ecd15180184 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -119,7 +119,7 @@ enum rsnd_reg { + #define RSND_REG_SSI_CTRL RSND_REG_SHARE02 + #define RSND_REG_SSI_BUSIF_MODE RSND_REG_SHARE03 + #define RSND_REG_SSI_BUSIF_ADINR RSND_REG_SHARE04 +-#define RSND_REG_INT_ENABLE RSND_REG_SHARE05 ++#define RSND_REG_SSI_INT_ENABLE RSND_REG_SHARE05 + #define RSND_REG_SRC_BSDSR RSND_REG_SHARE06 + #define RSND_REG_SRC_BSISR RSND_REG_SHARE07 + #define RSND_REG_DIV_EN RSND_REG_SHARE08 +diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c +index 3f6f4df7318d..9e11f731a3a1 100644 +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -215,10 +215,9 @@ int rsnd_src_ssi_irq_enable(struct rsnd_mod *ssi_mod) + return 0; + + /* enable SSI interrupt if Gen2 */ +- if (rsnd_ssi_is_dma_mode(ssi_mod)) +- rsnd_mod_write(ssi_mod, INT_ENABLE, 0x0e000000); +- else +- rsnd_mod_write(ssi_mod, INT_ENABLE, 0x0f000000); ++ rsnd_mod_write(ssi_mod, SSI_INT_ENABLE, ++ rsnd_ssi_is_dma_mode(ssi_mod) ? ++ 0x0e000000 : 0x0f000000); + + return 0; + } +@@ -231,7 +230,7 @@ int rsnd_src_ssi_irq_disable(struct rsnd_mod *ssi_mod) + return 0; + + /* disable SSI interrupt if Gen2 */ +- rsnd_mod_write(ssi_mod, INT_ENABLE, 0x00000000); ++ rsnd_mod_write(ssi_mod, SSI_INT_ENABLE, 0x00000000); + + return 0; + } +-- +2.6.2 + diff --git a/patches.renesas/0283-ASoC-rsnd-fixup-each-module-counter-on-__rsnd_mod_ca.patch b/patches.renesas/0283-ASoC-rsnd-fixup-each-module-counter-on-__rsnd_mod_ca.patch new file mode 100644 index 00000000000000..34a3752ee7bea4 --- /dev/null +++ b/patches.renesas/0283-ASoC-rsnd-fixup-each-module-counter-on-__rsnd_mod_ca.patch @@ -0,0 +1,38 @@ +From 3fc3d2bc9f51ff30072a653dff18267fc306cda4 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:10:04 +0000 +Subject: [PATCH 283/326] ASoC: rsnd: fixup each module counter on + __rsnd_mod_call() + +'5451ea443b ("ASoC: rsnd: count each mod (SSI/SRC/DVC)")' counts each +module's callback status, but counts 1st callback only. +This patch fixup it. Otherwise, multi-called function will be trouble + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit a48e3f9747fd62b385221a892cd4726b82dacd11) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index f1e5920654f6..d44bfb79779a 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -242,9 +242,9 @@ u32 rsnd_get_adinr(struct rsnd_mod *mod, struct rsnd_dai_stream *io) + if (val == __rsnd_mod_call_##func) { \ + called = 1; \ + ret = (mod)->ops->func(mod, io, param); \ +- mod->status = (mod->status & ~mask) + \ +- (add << __rsnd_mod_shift_##func); \ + } \ ++ mod->status = (mod->status & ~mask) + \ ++ (add << __rsnd_mod_shift_##func); \ + dev_dbg(dev, "%s[%d] 0x%08x %s\n", \ + rsnd_mod_name(mod), rsnd_mod_id(mod), mod->status, \ + called ? #func : ""); \ +-- +2.6.2 + diff --git a/patches.renesas/0284-ASoC-rsnd-add-workaround-for-SRC-sync-convert-DVC.patch b/patches.renesas/0284-ASoC-rsnd-add-workaround-for-SRC-sync-convert-DVC.patch new file mode 100644 index 00000000000000..dca5297b1427a8 --- /dev/null +++ b/patches.renesas/0284-ASoC-rsnd-add-workaround-for-SRC-sync-convert-DVC.patch @@ -0,0 +1,98 @@ +From d44f36d0a157dd765daac616c6936aa0c89ee944 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:10:22 +0000 +Subject: [PATCH 284/326] ASoC: rsnd: add workaround for SRC sync convert + DVC + +We couldn't use SRC sync convert mode together with DVC, +but we can use workaround for it. +This patch adds workaround and can use SRC sync convert + DVC + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 1a1bf58aafd09b3cb148eead3d709e2d7974a1f3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/src.c | 43 ++++++++++++++++++++++++++++++++----------- + 1 file changed, 32 insertions(+), 11 deletions(-) + +diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c +index 9e11f731a3a1..38d0aba7426e 100644 +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -616,6 +616,14 @@ static void rsnd_src_irq_ctrol_gen2(struct rsnd_mod *mod, int enable) + int_val = 0; + } + ++ /* ++ * WORKAROUND ++ * ++ * ignore over flow error when rsnd_enable_sync_convert() ++ */ ++ if (rsnd_enable_sync_convert(src)) ++ sys_int_val = sys_int_val & 0xffff; ++ + rsnd_mod_write(mod, SRC_INT_ENABLE0, int_val); + rsnd_mod_bset(mod, SCU_SYS_INT_EN0, sys_int_mask, sys_int_val); + rsnd_mod_bset(mod, SCU_SYS_INT_EN1, sys_int_mask, sys_int_val); +@@ -631,11 +639,22 @@ static void rsnd_src_error_clear_gen2(struct rsnd_mod *mod) + + static bool rsnd_src_error_record_gen2(struct rsnd_mod *mod) + { +- u32 val = OUF_SRC(rsnd_mod_id(mod)); ++ struct rsnd_src *src = rsnd_mod_to_src(mod); ++ u32 val0, val1; + bool ret = false; + +- if ((rsnd_mod_read(mod, SCU_SYS_STATUS0) & val) || +- (rsnd_mod_read(mod, SCU_SYS_STATUS1) & val)) { ++ val0 = val1 = OUF_SRC(rsnd_mod_id(mod)); ++ ++ /* ++ * WORKAROUND ++ * ++ * ignore over flow error when rsnd_enable_sync_convert() ++ */ ++ if (rsnd_enable_sync_convert(src)) ++ val0 = val0 & 0xffff; ++ ++ if ((rsnd_mod_read(mod, SCU_SYS_STATUS0) & val0) || ++ (rsnd_mod_read(mod, SCU_SYS_STATUS1) & val1)) { + struct rsnd_src *src = rsnd_mod_to_src(mod); + + src->err++; +@@ -651,7 +670,16 @@ static bool rsnd_src_error_record_gen2(struct rsnd_mod *mod) + static int _rsnd_src_start_gen2(struct rsnd_mod *mod, + struct rsnd_dai_stream *io) + { +- u32 val = rsnd_io_to_mod_dvc(io) ? 0x01 : 0x11; ++ struct rsnd_src *src = rsnd_mod_to_src(mod); ++ u32 val; ++ ++ /* ++ * WORKAROUND ++ * ++ * Enable SRC output if you want to use sync convert together with DVC ++ */ ++ val = (rsnd_io_to_mod_dvc(io) && !rsnd_enable_sync_convert(src)) ? ++ 0x01 : 0x11; + + rsnd_mod_write(mod, SRC_CTRL, val); + +@@ -921,13 +949,6 @@ static int rsnd_src_pcm_new(struct rsnd_mod *mod, + return 0; + + /* +- * We can't use SRC sync convert +- * if it has DVC +- */ +- if (rsnd_io_to_mod_dvc(io)) +- return 0; +- +- /* + * enable sync convert + */ + ret = rsnd_kctrl_new_s(mod, io, rtd, +-- +2.6.2 + diff --git a/patches.renesas/0285-ASoC-rsnd-rsnd_mod_id-return-1-if-mod-was-NULL.patch b/patches.renesas/0285-ASoC-rsnd-rsnd_mod_id-return-1-if-mod-was-NULL.patch new file mode 100644 index 00000000000000..28dd3654556f0f --- /dev/null +++ b/patches.renesas/0285-ASoC-rsnd-rsnd_mod_id-return-1-if-mod-was-NULL.patch @@ -0,0 +1,32 @@ +From 9bc0157fd67b201f2a54ff97d0ddaa8fd68366dd Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:10:43 +0000 +Subject: [PATCH 285/326] ASoC: rsnd: rsnd_mod_id() return -1 if mod was NULL + +enabling to use same method for exception case is useful. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 72413c107e81386a7da438bcf888ee2af5d3b72f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/rsnd.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 9ecd15180184..46eb4daa1461 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -316,7 +316,7 @@ struct rsnd_mod { + + #define rsnd_mod_to_priv(mod) ((mod)->priv) + #define rsnd_mod_to_dma(mod) (&(mod)->dma) +-#define rsnd_mod_id(mod) ((mod)->id) ++#define rsnd_mod_id(mod) ((mod) ? (mod)->id : -1) + #define rsnd_mod_hw_start(mod) clk_enable((mod)->clk) + #define rsnd_mod_hw_stop(mod) clk_disable((mod)->clk) + +-- +2.6.2 + diff --git a/patches.renesas/0286-ASoC-rsnd-move-DVC-specific-macro-into-dvc.c.patch b/patches.renesas/0286-ASoC-rsnd-move-DVC-specific-macro-into-dvc.c.patch new file mode 100644 index 00000000000000..adfea51f892a4e --- /dev/null +++ b/patches.renesas/0286-ASoC-rsnd-move-DVC-specific-macro-into-dvc.c.patch @@ -0,0 +1,44 @@ +From 9fa24f866a1faee4925231114d4327e0243d6903 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:11:02 +0000 +Subject: [PATCH 286/326] ASoC: rsnd: move DVC specific macro into dvc.c + +rsnd_dvc_nr() is used only from dvc.c + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 4f35fabaa30b116d549d95fe7dae907510c71862) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/dvc.c | 1 + + sound/soc/sh/rcar/rsnd.h | 3 --- + 2 files changed, 1 insertion(+), 3 deletions(-) + +diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c +index dbf0da6ce8a5..8a61aa396306 100644 +--- a/sound/soc/sh/rcar/dvc.c ++++ b/sound/soc/sh/rcar/dvc.c +@@ -24,6 +24,7 @@ struct rsnd_dvc { + struct rsnd_kctrl_cfg_s rdown; /* Ramp Rate Down */ + }; + ++#define rsnd_dvc_nr(priv) ((priv)->dvc_nr) + #define rsnd_dvc_of_node(priv) \ + of_get_child_by_name(rsnd_priv_to_dev(priv)->of_node, "rcar_sound,dvc") + +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 46eb4daa1461..8f793f020b08 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -579,7 +579,4 @@ void rsnd_dvc_remove(struct platform_device *pdev, + struct rsnd_priv *priv); + struct rsnd_mod *rsnd_dvc_mod_get(struct rsnd_priv *priv, int id); + +-#define rsnd_dvc_nr(priv) ((priv)->dvc_nr) +- +- + #endif +-- +2.6.2 + diff --git a/patches.renesas/0287-ASoC-rsnd-move-SRC-specific-macro-into-src.c.patch b/patches.renesas/0287-ASoC-rsnd-move-SRC-specific-macro-into-src.c.patch new file mode 100644 index 00000000000000..65d06a5d983174 --- /dev/null +++ b/patches.renesas/0287-ASoC-rsnd-move-SRC-specific-macro-into-src.c.patch @@ -0,0 +1,45 @@ +From 1242f2f30e8acefb31e374e5b9c7e7c5d58edee6 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:11:21 +0000 +Subject: [PATCH 287/326] ASoC: rsnd: move SRC specific macro into src.c + +rsnd_src_nr() is used only from src.c + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit da599fd34b1f2f14f2c387e6b3a909f9ff519c8a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/rsnd.h | 2 -- + sound/soc/sh/rcar/src.c | 1 + + 2 files changed, 1 insertion(+), 2 deletions(-) + +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 8f793f020b08..c8d202939e25 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -554,8 +554,6 @@ int rsnd_src_ssiu_stop(struct rsnd_mod *ssi_mod, + int rsnd_src_ssi_irq_enable(struct rsnd_mod *ssi_mod); + int rsnd_src_ssi_irq_disable(struct rsnd_mod *ssi_mod); + +-#define rsnd_src_nr(priv) ((priv)->src_nr) +- + /* + * R-Car SSI + */ +diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c +index 38d0aba7426e..0b06ac8dbeec 100644 +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -30,6 +30,7 @@ struct rsnd_src { + + #define RSND_SRC_NAME_SIZE 16 + ++#define rsnd_src_nr(priv) ((priv)->src_nr) + #define rsnd_enable_sync_convert(src) ((src)->sen.val) + #define rsnd_src_of_node(priv) \ + of_get_child_by_name(rsnd_priv_to_dev(priv)->of_node, "rcar_sound,src") +-- +2.6.2 + diff --git a/patches.renesas/0288-ASoC-rsnd-dvc-make-sure-DVC-soft-reset.patch b/patches.renesas/0288-ASoC-rsnd-dvc-make-sure-DVC-soft-reset.patch new file mode 100644 index 00000000000000..3f81cb56f2f882 --- /dev/null +++ b/patches.renesas/0288-ASoC-rsnd-dvc-make-sure-DVC-soft-reset.patch @@ -0,0 +1,59 @@ +From 80b546eb89d7e1660e5c5c6e65beed6f80708a87 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:12:00 +0000 +Subject: [PATCH 288/326] ASoC: rsnd: dvc: make sure DVC soft reset + +Renesas SCU (Sampling Rate Convert Unit) includes SRC/CTU/MIX/DVC, +and these have similar register. xxxRSR (Software reset Register) is one +of them. These xxxRSR need be set to 1 to 0 when software reset. +Current rsnd driver has src.c / dvc.c, and we will have mix.c. +It is readable if these have same named function. +This patch adds rsnd_dvc_soft_reset() and make sure it + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 636e4bad5cca947839c09d3e13ad6feeb7fa45da) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/dvc.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c +index 8a61aa396306..24d07634c749 100644 +--- a/sound/soc/sh/rcar/dvc.c ++++ b/sound/soc/sh/rcar/dvc.c +@@ -64,6 +64,12 @@ static const char * const dvc_ramp_rate[] = { + "0.125 dB/8192 steps", /* 10111 */ + }; + ++static void rsnd_dvc_soft_reset(struct rsnd_mod *mod) ++{ ++ rsnd_mod_write(mod, DVC_SWRSR, 0); ++ rsnd_mod_write(mod, DVC_SWRSR, 1); ++} ++ + static void rsnd_dvc_volume_update(struct rsnd_dai_stream *io, + struct rsnd_mod *mod) + { +@@ -160,15 +166,14 @@ static int rsnd_dvc_init(struct rsnd_mod *dvc_mod, + + rsnd_mod_hw_start(dvc_mod); + ++ rsnd_dvc_soft_reset(dvc_mod); ++ + /* + * fixme + * it doesn't support CTU/MIX + */ + rsnd_mod_write(dvc_mod, CMD_ROUTE_SLCT, route[src_id]); + +- rsnd_mod_write(dvc_mod, DVC_SWRSR, 0); +- rsnd_mod_write(dvc_mod, DVC_SWRSR, 1); +- + rsnd_mod_write(dvc_mod, DVC_DVUIR, 1); + + rsnd_mod_write(dvc_mod, DVC_ADINR, rsnd_get_adinr(dvc_mod, io)); +-- +2.6.2 + diff --git a/patches.renesas/0289-ASoC-rsnd-src-make-sure-SRC-soft-reset.patch b/patches.renesas/0289-ASoC-rsnd-src-make-sure-SRC-soft-reset.patch new file mode 100644 index 00000000000000..263dc739b636db --- /dev/null +++ b/patches.renesas/0289-ASoC-rsnd-src-make-sure-SRC-soft-reset.patch @@ -0,0 +1,61 @@ +From 99c52014387512a1383f9b08a7b41921e97dd623 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:12:18 +0000 +Subject: [PATCH 289/326] ASoC: rsnd: src: make sure SRC soft reset + +Renesas SCU (Sampling Rate Convert Unit) includes SRC/CTU/MIX/DVC, +and these have similar register. xxxRSR (Software reset Register) is one +of them. These xxxRSR need be set to 1 to 0 when software reset. +Current rsnd driver has src.c / dvc.c, and we will have mix.c. +It is readable if these have same named function. +This patch adds rsnd_src_soft_reset() and make sure it + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 379febfd2e30ec8db5baccd9f9403bf650c6afa1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/src.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c +index 0b06ac8dbeec..74ab644c688e 100644 +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -118,6 +118,12 @@ struct rsnd_src { + /* + * Gen1/Gen2 common functions + */ ++static void rsnd_src_soft_reset(struct rsnd_mod *mod) ++{ ++ rsnd_mod_write(mod, SRC_SWRSR, 0); ++ rsnd_mod_write(mod, SRC_SWRSR, 1); ++} ++ + static struct dma_chan *rsnd_src_dma_req(struct rsnd_dai_stream *io, + struct rsnd_mod *mod) + { +@@ -294,10 +300,6 @@ static int rsnd_src_set_convert_rate(struct rsnd_mod *mod, + if (convert_rate) + fsrate = 0x0400000 / convert_rate * runtime->rate; + +- /* set/clear soft reset */ +- rsnd_mod_write(mod, SRC_SWRSR, 0); +- rsnd_mod_write(mod, SRC_SWRSR, 1); +- + /* Set channel number and output bit length */ + rsnd_mod_write(mod, SRC_ADINR, rsnd_get_adinr(mod, io)); + +@@ -358,6 +360,8 @@ static int rsnd_src_init(struct rsnd_mod *mod, + + rsnd_mod_hw_start(mod); + ++ rsnd_src_soft_reset(mod); ++ + src->err = 0; + + /* reset sync convert_rate */ +-- +2.6.2 + diff --git a/patches.renesas/0290-ASoC-rsnd-enable-module-multi-connection.patch b/patches.renesas/0290-ASoC-rsnd-enable-module-multi-connection.patch new file mode 100644 index 00000000000000..04a7b82fdd6582 --- /dev/null +++ b/patches.renesas/0290-ASoC-rsnd-enable-module-multi-connection.patch @@ -0,0 +1,41 @@ +From aa61b2d3709ecccdb8e42e3b9de879b30d4b5d8e Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:12:36 +0000 +Subject: [PATCH 290/326] ASoC: rsnd: enable module multi connection + +'8a4e379b54f8("ASoC: rsnd: remove io from rsnd_mod")' removed mod/io +relationship. rsnd_dai_connect() mod/io check is no longer needed + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit d6f8d5b4422a5a391c02df97af9ef7da5a929d71) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 10 ---------- + 1 file changed, 10 deletions(-) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index d44bfb79779a..ff4f15a2666a 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -277,16 +277,6 @@ static int rsnd_dai_connect(struct rsnd_mod *mod, + if (!mod) + return -EIO; + +- if (io->mod[mod->type]) { +- struct rsnd_priv *priv = rsnd_mod_to_priv(mod); +- struct device *dev = rsnd_priv_to_dev(priv); +- +- dev_err(dev, "%s[%d] is not empty\n", +- rsnd_mod_name(mod), +- rsnd_mod_id(mod)); +- return -EIO; +- } +- + io->mod[mod->type] = mod; + + return 0; +-- +2.6.2 + diff --git a/patches.renesas/0291-ASoC-rsnd-rename-rsnd_path_parse-break-into-add-remo.patch b/patches.renesas/0291-ASoC-rsnd-rename-rsnd_path_parse-break-into-add-remo.patch new file mode 100644 index 00000000000000..109e1f25f811b9 --- /dev/null +++ b/patches.renesas/0291-ASoC-rsnd-rename-rsnd_path_parse-break-into-add-remo.patch @@ -0,0 +1,75 @@ +From 3e786be716fd39acb0660d38d30609e60bd62812 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:12:52 +0000 +Subject: [PATCH 291/326] ASoC: rsnd: rename rsnd_path_parse/break() into + add/remove + +parse/break is a little ambiguous/confusable name for rsnd module path. +Especially for CTU/MIX support. It was renamed to add/remove + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit c8cf15f64f8ddb3169987c2f26df3341b8556296) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index ff4f15a2666a..93fed5031c69 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -507,7 +507,7 @@ static const struct snd_soc_dai_ops rsnd_soc_dai_ops = { + .set_fmt = rsnd_soc_dai_set_fmt, + }; + +-#define rsnd_path_parse(priv, io, type) \ ++#define rsnd_path_add(priv, io, type) \ + ({ \ + struct rsnd_mod *mod; \ + int ret = 0; \ +@@ -523,7 +523,7 @@ static const struct snd_soc_dai_ops rsnd_soc_dai_ops = { + ret; \ + }) + +-#define rsnd_path_break(priv, io, type) \ ++#define rsnd_path_remove(priv, io, type) \ + { \ + struct rsnd_mod *mod; \ + int id = -1; \ +@@ -555,17 +555,17 @@ static int rsnd_path_init(struct rsnd_priv *priv, + */ + + /* SRC */ +- ret = rsnd_path_parse(priv, io, src); ++ ret = rsnd_path_add(priv, io, src); + if (ret < 0) + return ret; + + /* SSI */ +- ret = rsnd_path_parse(priv, io, ssi); ++ ret = rsnd_path_add(priv, io, ssi); + if (ret < 0) + return ret; + + /* DVC */ +- ret = rsnd_path_parse(priv, io, dvc); ++ ret = rsnd_path_add(priv, io, dvc); + if (ret < 0) + return ret; + +@@ -1023,8 +1023,8 @@ static int rsnd_rdai_continuance_probe(struct rsnd_priv *priv, + /* + * remove SRC/DVC from DAI, + */ +- rsnd_path_break(priv, io, src); +- rsnd_path_break(priv, io, dvc); ++ rsnd_path_remove(priv, io, src); ++ rsnd_path_remove(priv, io, dvc); + + /* + * fallback +-- +2.6.2 + diff --git a/patches.renesas/0292-ASoC-rsnd-add-rsnd_path_parse-for-CTU-MIX-DVC-route-.patch b/patches.renesas/0292-ASoC-rsnd-add-rsnd_path_parse-for-CTU-MIX-DVC-route-.patch new file mode 100644 index 00000000000000..5946fb45f863f5 --- /dev/null +++ b/patches.renesas/0292-ASoC-rsnd-add-rsnd_path_parse-for-CTU-MIX-DVC-route-.patch @@ -0,0 +1,135 @@ +From 8a980b6c938573e4c69509f0801aec0992ac27b2 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:13:10 +0000 +Subject: [PATCH 292/326] ASoC: rsnd: add rsnd_path_parse() for CTU/MIX/DVC + route setting + +Current sound data route settings is done in dvc.c, and it doesn't care +about CTU/MIX at this poinnt, but we need to care about these. +OTOH, rsnd driver already has rsnd_path_xxx() functions for data path which +are good match for CTU/MIX/DVC path selectio. +This patch adds new rsnd_path_parse() to select sound data route which will +care about CTU/MIX/DVC path. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit e2c08416196bd10a6575057fdd1347a307ce3a15) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 22 ++++++++++++++++++++++ + sound/soc/sh/rcar/dvc.c | 40 +++++++++------------------------------- + sound/soc/sh/rcar/rsnd.h | 2 ++ + 3 files changed, 33 insertions(+), 31 deletions(-) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index 93fed5031c69..cb8206721283 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -537,6 +537,28 @@ static const struct snd_soc_dai_ops rsnd_soc_dai_ops = { + } \ + } + ++void rsnd_path_parse(struct rsnd_priv *priv, ++ struct rsnd_dai_stream *io) ++{ ++ struct rsnd_mod *src = rsnd_io_to_mod_src(io); ++ struct rsnd_mod *dvc = rsnd_io_to_mod_dvc(io); ++ int src_id = rsnd_mod_id(src); ++ u32 path[] = { ++ [0] = 0x30000, ++ [1] = 0x30001, ++ [2] = 0x40000, ++ [3] = 0x10000, ++ [4] = 0x20000, ++ [5] = 0x40100 ++ }; ++ ++ /* Gen1 is not supported */ ++ if (rsnd_is_gen1(priv)) ++ return; ++ ++ rsnd_mod_write(dvc, CMD_ROUTE_SLCT, path[src_id]); ++} ++ + static int rsnd_path_init(struct rsnd_priv *priv, + struct rsnd_dai *rdai, + struct rsnd_dai_stream *io) +diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c +index 24d07634c749..9392507b5651 100644 +--- a/sound/soc/sh/rcar/dvc.c ++++ b/sound/soc/sh/rcar/dvc.c +@@ -142,48 +142,26 @@ static int rsnd_dvc_remove_gen2(struct rsnd_mod *mod, + return 0; + } + +-static int rsnd_dvc_init(struct rsnd_mod *dvc_mod, ++static int rsnd_dvc_init(struct rsnd_mod *mod, + struct rsnd_dai_stream *io, + struct rsnd_priv *priv) + { +- struct rsnd_mod *src_mod = rsnd_io_to_mod_src(io); +- struct device *dev = rsnd_priv_to_dev(priv); +- int dvc_id = rsnd_mod_id(dvc_mod); +- int src_id = rsnd_mod_id(src_mod); +- u32 route[] = { +- [0] = 0x30000, +- [1] = 0x30001, +- [2] = 0x40000, +- [3] = 0x10000, +- [4] = 0x20000, +- [5] = 0x40100 +- }; +- +- if (src_id >= ARRAY_SIZE(route)) { +- dev_err(dev, "DVC%d isn't connected to SRC%d\n", dvc_id, src_id); +- return -EINVAL; +- } +- +- rsnd_mod_hw_start(dvc_mod); ++ rsnd_mod_hw_start(mod); + +- rsnd_dvc_soft_reset(dvc_mod); ++ rsnd_dvc_soft_reset(mod); + +- /* +- * fixme +- * it doesn't support CTU/MIX +- */ +- rsnd_mod_write(dvc_mod, CMD_ROUTE_SLCT, route[src_id]); ++ rsnd_path_parse(priv, io); + +- rsnd_mod_write(dvc_mod, DVC_DVUIR, 1); ++ rsnd_mod_write(mod, DVC_DVUIR, 1); + +- rsnd_mod_write(dvc_mod, DVC_ADINR, rsnd_get_adinr(dvc_mod, io)); ++ rsnd_mod_write(mod, DVC_ADINR, rsnd_get_adinr(mod, io)); + + /* ch0/ch1 Volume */ +- rsnd_dvc_volume_update(io, dvc_mod); ++ rsnd_dvc_volume_update(io, mod); + +- rsnd_mod_write(dvc_mod, DVC_DVUIR, 0); ++ rsnd_mod_write(mod, DVC_DVUIR, 0); + +- rsnd_adg_set_cmd_timsel_gen2(dvc_mod, io); ++ rsnd_adg_set_cmd_timsel_gen2(mod, io); + + return 0; + } +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index c8d202939e25..6a8775787919 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -170,6 +170,8 @@ void rsnd_force_write(struct rsnd_priv *priv, struct rsnd_mod *mod, + void rsnd_bset(struct rsnd_priv *priv, struct rsnd_mod *mod, enum rsnd_reg reg, + u32 mask, u32 data); + u32 rsnd_get_adinr(struct rsnd_mod *mod, struct rsnd_dai_stream *io); ++void rsnd_path_parse(struct rsnd_priv *priv, ++ struct rsnd_dai_stream *io); + + /* + * R-Car DMA +-- +2.6.2 + diff --git a/patches.renesas/0293-ASoC-rsnd-add-rsnd_dvc_initialize_lock-unlock.patch b/patches.renesas/0293-ASoC-rsnd-add-rsnd_dvc_initialize_lock-unlock.patch new file mode 100644 index 00000000000000..5b084c7f38f603 --- /dev/null +++ b/patches.renesas/0293-ASoC-rsnd-add-rsnd_dvc_initialize_lock-unlock.patch @@ -0,0 +1,71 @@ +From 73998d8e58a110d0f791977e35498c6261191de8 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:13:29 +0000 +Subject: [PATCH 293/326] ASoC: rsnd: add rsnd_dvc_initialize_lock/unlock() + +Renesas SCU (Sampling Rate Convert Unit) includes SRC/CTU/MIX/DVC, +and these have similar register. xxxIR (Initialization Register) is one +of them. These xxxIR need be set to 1 during initialization. +Current rsnd driver has src.c / dvc.c, and we will have mix.c. +It is readable if these have same named function. +This patch adds rsnd_dvc_initialize_lock/unlock() and make sure it + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 3bb3d363e50d371289f0bd63b48da771ea807c02) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/dvc.c | 15 +++++++++++---- + 1 file changed, 11 insertions(+), 4 deletions(-) + +diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c +index 9392507b5651..343d44625fa5 100644 +--- a/sound/soc/sh/rcar/dvc.c ++++ b/sound/soc/sh/rcar/dvc.c +@@ -70,6 +70,13 @@ static void rsnd_dvc_soft_reset(struct rsnd_mod *mod) + rsnd_mod_write(mod, DVC_SWRSR, 1); + } + ++#define rsnd_dvc_initialize_lock(mod) __rsnd_dvc_initialize_lock(mod, 1) ++#define rsnd_dvc_initialize_unlock(mod) __rsnd_dvc_initialize_lock(mod, 0) ++static void __rsnd_dvc_initialize_lock(struct rsnd_mod *mod, u32 enable) ++{ ++ rsnd_mod_write(mod, DVC_DVUIR, enable); ++} ++ + static void rsnd_dvc_volume_update(struct rsnd_dai_stream *io, + struct rsnd_mod *mod) + { +@@ -150,17 +157,15 @@ static int rsnd_dvc_init(struct rsnd_mod *mod, + + rsnd_dvc_soft_reset(mod); + +- rsnd_path_parse(priv, io); ++ rsnd_dvc_initialize_lock(mod); + +- rsnd_mod_write(mod, DVC_DVUIR, 1); ++ rsnd_path_parse(priv, io); + + rsnd_mod_write(mod, DVC_ADINR, rsnd_get_adinr(mod, io)); + + /* ch0/ch1 Volume */ + rsnd_dvc_volume_update(io, mod); + +- rsnd_mod_write(mod, DVC_DVUIR, 0); +- + rsnd_adg_set_cmd_timsel_gen2(mod, io); + + return 0; +@@ -179,6 +184,8 @@ static int rsnd_dvc_start(struct rsnd_mod *mod, + struct rsnd_dai_stream *io, + struct rsnd_priv *priv) + { ++ rsnd_dvc_initialize_unlock(mod); ++ + rsnd_mod_write(mod, CMD_CTRL, 0x10); + + return 0; +-- +2.6.2 + diff --git a/patches.renesas/0294-ASoC-rsnd-add-rsnd_src_initialize_lock-unlock.patch b/patches.renesas/0294-ASoC-rsnd-add-rsnd_src_initialize_lock-unlock.patch new file mode 100644 index 00000000000000..fa209a27e14278 --- /dev/null +++ b/patches.renesas/0294-ASoC-rsnd-add-rsnd_src_initialize_lock-unlock.patch @@ -0,0 +1,76 @@ +From c030113054a22dc16df944d5aae90fc5c524bab0 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:13:47 +0000 +Subject: [PATCH 294/326] ASoC: rsnd: add rsnd_src_initialize_lock/unlock() + +Renesas SCU (Sampling Rate Convert Unit) includes SRC/CTU/MIX/DVC, +and these have similar register. xxxIR (Initialization Register) is one +of them. These xxxIR need be set to 1 during initialization. +Current rsnd driver has src.c / dvc.c, and we will have mix.c. +It is readable if these have same named function. +This patch adds rsnd_src_initialize_lock/unlock() and make sure it + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit d1ade514e84ea55cba999edb04cb88daa4da94b8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/src.c | 22 +++++++++++----------- + 1 file changed, 11 insertions(+), 11 deletions(-) + +diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c +index 74ab644c688e..b3d965ee9b77 100644 +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -124,6 +124,14 @@ static void rsnd_src_soft_reset(struct rsnd_mod *mod) + rsnd_mod_write(mod, SRC_SWRSR, 1); + } + ++ ++#define rsnd_src_initialize_lock(mod) __rsnd_src_initialize_lock(mod, 1) ++#define rsnd_src_initialize_unlock(mod) __rsnd_src_initialize_lock(mod, 0) ++static void __rsnd_src_initialize_lock(struct rsnd_mod *mod, u32 enable) ++{ ++ rsnd_mod_write(mod, SRC_SRCIR, enable); ++} ++ + static struct dma_chan *rsnd_src_dma_req(struct rsnd_dai_stream *io, + struct rsnd_mod *mod) + { +@@ -362,17 +370,13 @@ static int rsnd_src_init(struct rsnd_mod *mod, + + rsnd_src_soft_reset(mod); + ++ rsnd_src_initialize_lock(mod); ++ + src->err = 0; + + /* reset sync convert_rate */ + src->sync.val = 0; + +- /* +- * Initialize the operation of the SRC internal circuits +- * see rsnd_src_start() +- */ +- rsnd_mod_write(mod, SRC_SRCIR, 1); +- + return 0; + } + +@@ -399,11 +403,7 @@ static int rsnd_src_quit(struct rsnd_mod *mod, + + static int rsnd_src_start(struct rsnd_mod *mod) + { +- /* +- * Cancel the initialization and operate the SRC function +- * see rsnd_src_init() +- */ +- rsnd_mod_write(mod, SRC_SRCIR, 0); ++ rsnd_src_initialize_unlock(mod); + + return 0; + } +-- +2.6.2 + diff --git a/patches.renesas/0295-ASoC-rsnd-tidyup-ADINR-function-name.patch b/patches.renesas/0295-ASoC-rsnd-tidyup-ADINR-function-name.patch new file mode 100644 index 00000000000000..37af5915d35544 --- /dev/null +++ b/patches.renesas/0295-ASoC-rsnd-tidyup-ADINR-function-name.patch @@ -0,0 +1,92 @@ +From c2aacd6deb084a00f3cddbab9ba38f99f5c68eae Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:14:05 +0000 +Subject: [PATCH 295/326] ASoC: rsnd: tidyup ADINR function name + +Renesas sound IP (= SSIU/SRC/CTU/MIX/DVC) have ADINR +(= Audio Information Register), but some of them (= SSIU/SRC/DVC) +are for audio data bits, some of them (= CTU/MIX) are for audio data +channels. +Current rsnd driver is supporting SSIU/SRC/DVC, and these ADINR were +for bits. This patch rename rsnd_get_adinr() to rsnd_get_adinr_bit(), +and we will have rsnd_get_adinr_chan() for CTU/MIX. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 3023b384d0c9da49028131b91fe64b24b5b84e6d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 4 ++-- + sound/soc/sh/rcar/dvc.c | 2 +- + sound/soc/sh/rcar/rsnd.h | 2 +- + sound/soc/sh/rcar/src.c | 4 ++-- + 4 files changed, 6 insertions(+), 6 deletions(-) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index cb8206721283..0ca6d0268b56 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -203,9 +203,9 @@ int rsnd_io_is_working(struct rsnd_dai_stream *io) + } + + /* +- * settting function ++ * ADINR function + */ +-u32 rsnd_get_adinr(struct rsnd_mod *mod, struct rsnd_dai_stream *io) ++u32 rsnd_get_adinr_bit(struct rsnd_mod *mod, struct rsnd_dai_stream *io) + { + struct rsnd_priv *priv = rsnd_mod_to_priv(mod); + struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); +diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c +index 343d44625fa5..d06e4ee91f8d 100644 +--- a/sound/soc/sh/rcar/dvc.c ++++ b/sound/soc/sh/rcar/dvc.c +@@ -161,7 +161,7 @@ static int rsnd_dvc_init(struct rsnd_mod *mod, + + rsnd_path_parse(priv, io); + +- rsnd_mod_write(mod, DVC_ADINR, rsnd_get_adinr(mod, io)); ++ rsnd_mod_write(mod, DVC_ADINR, rsnd_get_adinr_bit(mod, io)); + + /* ch0/ch1 Volume */ + rsnd_dvc_volume_update(io, mod); +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 6a8775787919..224a4a9eabd7 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -169,7 +169,7 @@ void rsnd_force_write(struct rsnd_priv *priv, struct rsnd_mod *mod, + enum rsnd_reg reg, u32 data); + void rsnd_bset(struct rsnd_priv *priv, struct rsnd_mod *mod, enum rsnd_reg reg, + u32 mask, u32 data); +-u32 rsnd_get_adinr(struct rsnd_mod *mod, struct rsnd_dai_stream *io); ++u32 rsnd_get_adinr_bit(struct rsnd_mod *mod, struct rsnd_dai_stream *io); + void rsnd_path_parse(struct rsnd_priv *priv, + struct rsnd_dai_stream *io); + +diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c +index b3d965ee9b77..c45da610feda 100644 +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -189,7 +189,7 @@ int rsnd_src_ssiu_start(struct rsnd_mod *ssi_mod, + u32 mask = ~0; + + rsnd_mod_write(ssi_mod, SSI_BUSIF_ADINR, +- rsnd_get_adinr(ssi_mod, io)); ++ rsnd_get_adinr_bit(ssi_mod, io)); + rsnd_mod_write(ssi_mod, SSI_BUSIF_MODE, 1); + rsnd_mod_write(ssi_mod, SSI_CTRL, 0x1); + +@@ -309,7 +309,7 @@ static int rsnd_src_set_convert_rate(struct rsnd_mod *mod, + fsrate = 0x0400000 / convert_rate * runtime->rate; + + /* Set channel number and output bit length */ +- rsnd_mod_write(mod, SRC_ADINR, rsnd_get_adinr(mod, io)); ++ rsnd_mod_write(mod, SRC_ADINR, rsnd_get_adinr_bit(mod, io)); + + /* Enable the initial value of IFS */ + if (fsrate) { +-- +2.6.2 + diff --git a/patches.renesas/0296-ASoC-rsnd-add-rsnd_get_adinr_chan.patch b/patches.renesas/0296-ASoC-rsnd-add-rsnd_get_adinr_chan.patch new file mode 100644 index 00000000000000..429d1a2a3324bc --- /dev/null +++ b/patches.renesas/0296-ASoC-rsnd-add-rsnd_get_adinr_chan.patch @@ -0,0 +1,68 @@ +From df02acace53f5fbcf496d6d0ba1ccc797d2c3c54 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:14:29 +0000 +Subject: [PATCH 296/326] ASoC: rsnd: add rsnd_get_adinr_chan() + +Current rsnd driver has rsnd_get_adinr_bit() to get bit settings for +ADINR (= Audio Information Register) of SSIU/SRC/DVC. +This patch adds rsnd_get_adinr_chan() to get channel settings for +ADINR (= Audio Information Register) of CTU/MIX. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit bfe1360d79210f9c1d330a07c26a8d5cb202159d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 22 ++++++++++++++++++++++ + sound/soc/sh/rcar/rsnd.h | 1 + + 2 files changed, 23 insertions(+) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index 0ca6d0268b56..a3637b92b187 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -227,6 +227,28 @@ u32 rsnd_get_adinr_bit(struct rsnd_mod *mod, struct rsnd_dai_stream *io) + return adinr; + } + ++u32 rsnd_get_adinr_chan(struct rsnd_mod *mod, struct rsnd_dai_stream *io) ++{ ++ struct rsnd_priv *priv = rsnd_mod_to_priv(mod); ++ struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); ++ struct device *dev = rsnd_priv_to_dev(priv); ++ u32 chan = runtime->channels; ++ ++ switch (chan) { ++ case 1: ++ case 2: ++ case 4: ++ case 6: ++ case 8: ++ break; ++ default: ++ dev_warn(dev, "not supported channel\n"); ++ chan = 0; ++ break; ++ } ++ ++ return chan; ++} + /* + * rsnd_dai functions + */ +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 224a4a9eabd7..1296b3525fa6 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -170,6 +170,7 @@ void rsnd_force_write(struct rsnd_priv *priv, struct rsnd_mod *mod, + void rsnd_bset(struct rsnd_priv *priv, struct rsnd_mod *mod, enum rsnd_reg reg, + u32 mask, u32 data); + u32 rsnd_get_adinr_bit(struct rsnd_mod *mod, struct rsnd_dai_stream *io); ++u32 rsnd_get_adinr_chan(struct rsnd_mod *mod, struct rsnd_dai_stream *io); + void rsnd_path_parse(struct rsnd_priv *priv, + struct rsnd_dai_stream *io); + +-- +2.6.2 + diff --git a/patches.renesas/0297-ASoC-rsnd-tidyup-data-align-position.patch b/patches.renesas/0297-ASoC-rsnd-tidyup-data-align-position.patch new file mode 100644 index 00000000000000..34dc2fdb84091a --- /dev/null +++ b/patches.renesas/0297-ASoC-rsnd-tidyup-data-align-position.patch @@ -0,0 +1,169 @@ +From 742e8653d61715a65cfec6a179f922eb260b199d Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:14:47 +0000 +Subject: [PATCH 297/326] ASoC: rsnd: tidyup data align position + +Sound L/R order of SSI is different from Linux sound data order. +So current rsnd driver is using DALIGN (= data align) to exchange data +align on SSIU. OTOH, CMD/SRC/SSIU have DALIGN register. Now inverted +sound volume will be exchanged if user used volume control on DVC. +Because SSIU which exchanges data align is located after DVC. + + MEM -> SRC -> DVC -> SSI + +This patch exchanges data align SRC if possible + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 4689032b11d1af10e5eb755eb575f9761a455a72) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 36 ++++++++++++++++++++++++++++++++++++ + sound/soc/sh/rcar/gen.c | 1 + + sound/soc/sh/rcar/rsnd.h | 3 +++ + sound/soc/sh/rcar/src.c | 20 +++++--------------- + 4 files changed, 45 insertions(+), 15 deletions(-) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index a3637b92b187..0f9323f2c049 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -249,6 +249,42 @@ u32 rsnd_get_adinr_chan(struct rsnd_mod *mod, struct rsnd_dai_stream *io) + + return chan; + } ++ ++/* ++ * DALIGN function ++ */ ++u32 rsnd_get_dalign(struct rsnd_mod *mod, struct rsnd_dai_stream *io) ++{ ++ struct rsnd_mod *src = rsnd_io_to_mod_src(io); ++ struct rsnd_mod *ssi = rsnd_io_to_mod_ssi(io); ++ struct rsnd_mod *target = src ? src : ssi; ++ struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); ++ u32 val = 0x76543210; ++ u32 mask = ~0; ++ ++ mask <<= runtime->channels * 4; ++ val = val & mask; ++ ++ switch (runtime->sample_bits) { ++ case 16: ++ val |= 0x67452301 & ~mask; ++ break; ++ case 32: ++ val |= 0x76543210 & ~mask; ++ break; ++ } ++ ++ /* ++ * exchange channeles on SRC if possible, ++ * otherwise, R/L volume settings on DVC ++ * changes inverted channels ++ */ ++ if (mod == target) ++ return val; ++ else ++ return 0x76543210; ++} ++ + /* + * rsnd_dai functions + */ +diff --git a/sound/soc/sh/rcar/gen.c b/sound/soc/sh/rcar/gen.c +index 5d3592dfc382..a2d5df4d5d17 100644 +--- a/sound/soc/sh/rcar/gen.c ++++ b/sound/soc/sh/rcar/gen.c +@@ -222,6 +222,7 @@ static int rsnd_gen2_probe(struct platform_device *pdev, + }; + struct rsnd_regmap_field_conf conf_scu[] = { + RSND_GEN_M_REG(SRC_BUSIF_MODE, 0x0, 0x20), ++ RSND_GEN_M_REG(SRC_BUSIF_DALIGN,0x8, 0x20), + RSND_GEN_M_REG(SRC_ROUTE_MODE0, 0xc, 0x20), + RSND_GEN_M_REG(SRC_CTRL, 0x10, 0x20), + RSND_GEN_M_REG(SRC_INT_ENABLE0, 0x18, 0x20), +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 1296b3525fa6..6c10a8b9210e 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -99,6 +99,7 @@ enum rsnd_reg { + RSND_REG_SHARE26, + RSND_REG_SHARE27, + RSND_REG_SHARE28, ++ RSND_REG_SHARE29, + + RSND_REG_MAX, + }; +@@ -143,6 +144,7 @@ enum rsnd_reg { + #define RSND_REG_SCU_SYS_STATUS1 RSND_REG_SHARE26 + #define RSND_REG_SCU_SYS_INT_EN1 RSND_REG_SHARE27 + #define RSND_REG_SRC_INT_ENABLE0 RSND_REG_SHARE28 ++#define RSND_REG_SRC_BUSIF_DALIGN RSND_REG_SHARE29 + + struct rsnd_of_data; + struct rsnd_priv; +@@ -171,6 +173,7 @@ void rsnd_bset(struct rsnd_priv *priv, struct rsnd_mod *mod, enum rsnd_reg reg, + u32 mask, u32 data); + u32 rsnd_get_adinr_bit(struct rsnd_mod *mod, struct rsnd_dai_stream *io); + u32 rsnd_get_adinr_chan(struct rsnd_mod *mod, struct rsnd_dai_stream *io); ++u32 rsnd_get_dalign(struct rsnd_mod *mod, struct rsnd_dai_stream *io); + void rsnd_path_parse(struct rsnd_priv *priv, + struct rsnd_dai_stream *io); + +diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c +index c45da610feda..89a18e102feb 100644 +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -148,7 +148,6 @@ int rsnd_src_ssiu_start(struct rsnd_mod *ssi_mod, + int use_busif) + { + struct rsnd_dai *rdai = rsnd_io_to_rdai(io); +- struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); + int ssi_id = rsnd_mod_id(ssi_mod); + + /* +@@ -185,27 +184,14 @@ int rsnd_src_ssiu_start(struct rsnd_mod *ssi_mod, + * DMA settings for SSIU + */ + if (use_busif) { +- u32 val = 0x76543210; +- u32 mask = ~0; ++ u32 val = rsnd_get_dalign(ssi_mod, io); + + rsnd_mod_write(ssi_mod, SSI_BUSIF_ADINR, + rsnd_get_adinr_bit(ssi_mod, io)); + rsnd_mod_write(ssi_mod, SSI_BUSIF_MODE, 1); + rsnd_mod_write(ssi_mod, SSI_CTRL, 0x1); + +- mask <<= runtime->channels * 4; +- val = val & mask; +- +- switch (runtime->sample_bits) { +- case 16: +- val |= 0x67452301 & ~mask; +- break; +- case 32: +- val |= 0x76543210 & ~mask; +- break; +- } + rsnd_mod_write(ssi_mod, SSI_BUSIF_DALIGN, val); +- + } + + return 0; +@@ -678,6 +664,10 @@ static int _rsnd_src_start_gen2(struct rsnd_mod *mod, + struct rsnd_src *src = rsnd_mod_to_src(mod); + u32 val; + ++ val = rsnd_get_dalign(mod, io); ++ ++ rsnd_mod_write(mod, SRC_BUSIF_DALIGN, val); ++ + /* + * WORKAROUND + * +-- +2.6.2 + diff --git a/patches.renesas/0298-ASoC-rsnd-show-debug-message-for-SSI-SRC-DVC-connect.patch b/patches.renesas/0298-ASoC-rsnd-show-debug-message-for-SSI-SRC-DVC-connect.patch new file mode 100644 index 00000000000000..db3996cfc013eb --- /dev/null +++ b/patches.renesas/0298-ASoC-rsnd-show-debug-message-for-SSI-SRC-DVC-connect.patch @@ -0,0 +1,43 @@ +From 51f78d3b9110f678c0cb08c550758849dd357edb Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:15:10 +0000 +Subject: [PATCH 298/326] ASoC: rsnd: show debug message for SSI/SRC/DVC + connection + +It can help for connection debug + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 84e95355602c59865be8a3bd18cd2f0b3863b4cb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index 0f9323f2c049..8919afabe48f 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -332,11 +332,18 @@ u32 rsnd_get_dalign(struct rsnd_mod *mod, struct rsnd_dai_stream *io) + static int rsnd_dai_connect(struct rsnd_mod *mod, + struct rsnd_dai_stream *io) + { ++ struct rsnd_priv *priv = rsnd_mod_to_priv(mod); ++ struct device *dev = rsnd_priv_to_dev(priv); ++ + if (!mod) + return -EIO; + + io->mod[mod->type] = mod; + ++ dev_dbg(dev, "%s[%d] is connected to io (%s)\n", ++ rsnd_mod_name(mod), rsnd_mod_id(mod), ++ rsnd_io_is_play(io) ? "Playback" : "Capture"); ++ + return 0; + } + +-- +2.6.2 + diff --git a/patches.renesas/0299-ASoC-rsnd-tidyup-rsnd_dma_ops-definition-place.patch b/patches.renesas/0299-ASoC-rsnd-tidyup-rsnd_dma_ops-definition-place.patch new file mode 100644 index 00000000000000..558abba34a7b0f --- /dev/null +++ b/patches.renesas/0299-ASoC-rsnd-tidyup-rsnd_dma_ops-definition-place.patch @@ -0,0 +1,57 @@ +From 56c93fb6527be379fa747678bca4936353ad5adc Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:15:27 +0000 +Subject: [PATCH 299/326] ASoC: rsnd: tidyup rsnd_dma_ops definition place + +rsnd_dma_ops is used only from dma.c, rsnd.h doesn't need it. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 98d358af07aa6fc4cd6cdfd3256ab792eb3675cd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/dma.c | 8 ++++++++ + sound/soc/sh/rcar/rsnd.h | 7 ------- + 2 files changed, 8 insertions(+), 7 deletions(-) + +diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c +index d306e298c63d..943106136d99 100644 +--- a/sound/soc/sh/rcar/dma.c ++++ b/sound/soc/sh/rcar/dma.c +@@ -27,6 +27,14 @@ struct rsnd_dma_ctrl { + int dmapp_num; + }; + ++struct rsnd_dma_ops { ++ void (*start)(struct rsnd_dai_stream *io, struct rsnd_dma *dma); ++ void (*stop)(struct rsnd_dai_stream *io, struct rsnd_dma *dma); ++ int (*init)(struct rsnd_dai_stream *io, struct rsnd_dma *dma, int id, ++ struct rsnd_mod *mod_from, struct rsnd_mod *mod_to); ++ void (*quit)(struct rsnd_dai_stream *io, struct rsnd_dma *dma); ++}; ++ + #define rsnd_priv_to_dmac(p) ((struct rsnd_dma_ctrl *)(p)->dma) + + /* +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 6c10a8b9210e..705e66f66ab8 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -181,13 +181,6 @@ void rsnd_path_parse(struct rsnd_priv *priv, + * R-Car DMA + */ + struct rsnd_dma; +-struct rsnd_dma_ops { +- void (*start)(struct rsnd_dai_stream *io, struct rsnd_dma *dma); +- void (*stop)(struct rsnd_dai_stream *io, struct rsnd_dma *dma); +- int (*init)(struct rsnd_dai_stream *io, struct rsnd_dma *dma, int id, +- struct rsnd_mod *mod_from, struct rsnd_mod *mod_to); +- void (*quit)(struct rsnd_dai_stream *io, struct rsnd_dma *dma); +-}; + + struct rsnd_dmaen { + struct dma_chan *chan; +-- +2.6.2 + diff --git a/patches.renesas/0300-ASoC-rsnd-check-the-Gen1-at-the-beginning-of-DVC-pro.patch b/patches.renesas/0300-ASoC-rsnd-check-the-Gen1-at-the-beginning-of-DVC-pro.patch new file mode 100644 index 00000000000000..7fa06e7990186d --- /dev/null +++ b/patches.renesas/0300-ASoC-rsnd-check-the-Gen1-at-the-beginning-of-DVC-pro.patch @@ -0,0 +1,49 @@ +From 4355c6b82f1ecaf653080b0c656fe8976bdd508d Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:15:47 +0000 +Subject: [PATCH 300/326] ASoC: rsnd: check the Gen1 at the beginning of DVC + probe + +DVC doesn't support Gen1, check it beginning of probe + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 9469b8b6092d347ef8a5fa9d2d7dde4c857a0994) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/dvc.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c +index d06e4ee91f8d..57796387d482 100644 +--- a/sound/soc/sh/rcar/dvc.c ++++ b/sound/soc/sh/rcar/dvc.c +@@ -332,18 +332,18 @@ int rsnd_dvc_probe(struct platform_device *pdev, + char name[RSND_DVC_NAME_SIZE]; + int i, nr, ret; + +- rsnd_of_parse_dvc(pdev, of_data, priv); +- +- nr = info->dvc_info_nr; +- if (!nr) +- return 0; +- + /* This driver doesn't support Gen1 at this point */ + if (rsnd_is_gen1(priv)) { + dev_warn(dev, "CMD is not supported on Gen1\n"); + return -EINVAL; + } + ++ rsnd_of_parse_dvc(pdev, of_data, priv); ++ ++ nr = info->dvc_info_nr; ++ if (!nr) ++ return 0; ++ + dvc = devm_kzalloc(dev, sizeof(*dvc) * nr, GFP_KERNEL); + if (!dvc) + return -ENOMEM; +-- +2.6.2 + diff --git a/patches.renesas/0301-ASoC-rsnd-dma-add-DMA-name-on-.ops.patch b/patches.renesas/0301-ASoC-rsnd-dma-add-DMA-name-on-.ops.patch new file mode 100644 index 00000000000000..2d5dfe2e7af969 --- /dev/null +++ b/patches.renesas/0301-ASoC-rsnd-dma-add-DMA-name-on-.ops.patch @@ -0,0 +1,79 @@ +From 2acccd224bbb28a8b136d8ea4c96334e3f6052d5 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:16:03 +0000 +Subject: [PATCH 301/326] ASoC: rsnd: dma: add DMA name on .ops + +Current rsnd driver is using Audio DMAC (via DMAEngine) and +Audio DMAC peri peri (via original method), and usage of these DMAC +are different. Indicates its naming is useful for debugging. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit ddea1b2e83c379840aa54fadc587e418cf986ccb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/dma.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c +index 943106136d99..a175863d239c 100644 +--- a/sound/soc/sh/rcar/dma.c ++++ b/sound/soc/sh/rcar/dma.c +@@ -28,6 +28,7 @@ struct rsnd_dma_ctrl { + }; + + struct rsnd_dma_ops { ++ char *name; + void (*start)(struct rsnd_dai_stream *io, struct rsnd_dma *dma); + void (*stop)(struct rsnd_dai_stream *io, struct rsnd_dma *dma); + int (*init)(struct rsnd_dai_stream *io, struct rsnd_dma *dma, int id, +@@ -190,7 +191,8 @@ static int rsnd_dmaen_init(struct rsnd_dai_stream *io, + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + +- dev_dbg(dev, "dma : %pad -> %pad\n", ++ dev_dbg(dev, "%s %pad -> %pad\n", ++ dma->ops->name, + &cfg.src_addr, &cfg.dst_addr); + + ret = dmaengine_slave_config(dmaen->chan, &cfg); +@@ -223,6 +225,7 @@ static void rsnd_dmaen_quit(struct rsnd_dai_stream *io, struct rsnd_dma *dma) + } + + static struct rsnd_dma_ops rsnd_dmaen_ops = { ++ .name = "audmac", + .start = rsnd_dmaen_start, + .stop = rsnd_dmaen_stop, + .init = rsnd_dmaen_init, +@@ -368,6 +371,7 @@ static int rsnd_dmapp_init(struct rsnd_dai_stream *io, + } + + static struct rsnd_dma_ops rsnd_dmapp_ops = { ++ .name = "audmac-pp", + .start = rsnd_dmapp_start, + .stop = rsnd_dmapp_stop, + .init = rsnd_dmapp_init, +@@ -580,6 +584,7 @@ int rsnd_dma_init(struct rsnd_dai_stream *io, struct rsnd_dma *dma, int id) + struct rsnd_mod *mod_to; + struct rsnd_priv *priv = rsnd_io_to_priv(io); + struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv); ++ struct device *dev = rsnd_priv_to_dev(priv); + int is_play = rsnd_io_is_play(io); + + /* +@@ -606,6 +611,11 @@ int rsnd_dma_init(struct rsnd_dai_stream *io, struct rsnd_dma *dma, int id) + if (rsnd_is_gen1(priv)) + dma->ops = &rsnd_dmaen_ops; + ++ dev_dbg(dev, "%s %s[%d] -> %s[%d]\n", ++ dma->ops->name, ++ rsnd_mod_name(mod_from), rsnd_mod_id(mod_from), ++ rsnd_mod_name(mod_to), rsnd_mod_id(mod_to)); ++ + return dma->ops->init(io, dma, id, mod_from, mod_to); + } + +-- +2.6.2 + diff --git a/patches.renesas/0302-ASoC-rsnd-add-rsnd_io_to_mod.patch b/patches.renesas/0302-ASoC-rsnd-add-rsnd_io_to_mod.patch new file mode 100644 index 00000000000000..9e2c35ac9991ec --- /dev/null +++ b/patches.renesas/0302-ASoC-rsnd-add-rsnd_io_to_mod.patch @@ -0,0 +1,39 @@ +From f6a50d0ff3a6c5aa9cb7bef8d9a3899e1adfaca9 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:16:19 +0000 +Subject: [PATCH 302/326] ASoC: rsnd: add rsnd_io_to_mod() + +Sometimes we would like to get each module directly, especially data path +searching. this patch adds rsnd_io_to_mod() macro, and existing +rsnd_io_to_mod_xxx() use it. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 5cbbadd3d507eeb7711266e3932f4c427cbcbd61) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/rsnd.h | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 705e66f66ab8..5f5b8b1118b2 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -348,9 +348,10 @@ struct rsnd_dai_stream { + int byte_per_period; + int next_period_byte; + }; +-#define rsnd_io_to_mod_ssi(io) ((io)->mod[RSND_MOD_SSI]) +-#define rsnd_io_to_mod_src(io) ((io)->mod[RSND_MOD_SRC]) +-#define rsnd_io_to_mod_dvc(io) ((io)->mod[RSND_MOD_DVC]) ++#define rsnd_io_to_mod(io, i) ((i) < RSND_MOD_MAX ? (io)->mod[(i)] : NULL) ++#define rsnd_io_to_mod_ssi(io) rsnd_io_to_mod((io), RSND_MOD_SSI) ++#define rsnd_io_to_mod_src(io) rsnd_io_to_mod((io), RSND_MOD_SRC) ++#define rsnd_io_to_mod_dvc(io) rsnd_io_to_mod((io), RSND_MOD_DVC) + #define rsnd_io_to_rdai(io) ((io)->rdai) + #define rsnd_io_to_priv(io) (rsnd_rdai_to_priv(rsnd_io_to_rdai(io))) + #define rsnd_io_is_play(io) (&rsnd_io_to_rdai(io)->playback == io) +-- +2.6.2 + diff --git a/patches.renesas/0303-ASoC-rsnd-tidyup-SRC-position-on-each-code.patch b/patches.renesas/0303-ASoC-rsnd-tidyup-SRC-position-on-each-code.patch new file mode 100644 index 00000000000000..2207e1b1d1f037 --- /dev/null +++ b/patches.renesas/0303-ASoC-rsnd-tidyup-SRC-position-on-each-code.patch @@ -0,0 +1,123 @@ +From c5e57c13b158c62aa7ed172f8ef43482cf75e216 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:16:37 +0000 +Subject: [PATCH 303/326] ASoC: rsnd: tidyup SRC position on each code + +This is cleanup for CTU/MIX support + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 78edead4494219640d9fdf37d76beae24f79de9e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/Makefile | 2 +- + sound/soc/sh/rcar/core.c | 8 ++++---- + sound/soc/sh/rcar/rsnd.h | 38 +++++++++++++++++++------------------- + 3 files changed, 24 insertions(+), 24 deletions(-) + +diff --git a/sound/soc/sh/rcar/Makefile b/sound/soc/sh/rcar/Makefile +index f1b445173fba..3a274fd3593c 100644 +--- a/sound/soc/sh/rcar/Makefile ++++ b/sound/soc/sh/rcar/Makefile +@@ -1,4 +1,4 @@ +-snd-soc-rcar-objs := core.o gen.o dma.o src.o adg.o ssi.o dvc.o ++snd-soc-rcar-objs := core.o gen.o dma.o adg.o ssi.o src.o dvc.o + obj-$(CONFIG_SND_SOC_RCAR) += snd-soc-rcar.o + + snd-soc-rsrc-card-objs := rsrc-card.o +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index 8919afabe48f..e20d8ea0aafe 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -641,13 +641,13 @@ static int rsnd_path_init(struct rsnd_priv *priv, + * using fixed path. + */ + +- /* SRC */ +- ret = rsnd_path_add(priv, io, src); ++ /* SSI */ ++ ret = rsnd_path_add(priv, io, ssi); + if (ret < 0) + return ret; + +- /* SSI */ +- ret = rsnd_path_add(priv, io, ssi); ++ /* SRC */ ++ ret = rsnd_path_add(priv, io, src); + if (ret < 0) + return ret; + +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 5f5b8b1118b2..7fee2079ba5a 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -441,12 +441,6 @@ struct rsnd_priv { + void *gen; + + /* +- * below value will be filled on rsnd_src_probe() +- */ +- void *src; +- int src_nr; +- +- /* + * below value will be filled on rsnd_adg_probe() + */ + void *adg; +@@ -463,6 +457,12 @@ struct rsnd_priv { + int ssi_nr; + + /* ++ * below value will be filled on rsnd_src_probe() ++ */ ++ void *src; ++ int src_nr; ++ ++ /* + * below value will be filled on rsnd_dvc_probe() + */ + void *dvc; +@@ -535,6 +535,19 @@ int rsnd_kctrl_new_e(struct rsnd_mod *mod, + u32 max); + + /* ++ * R-Car SSI ++ */ ++int rsnd_ssi_probe(struct platform_device *pdev, ++ const struct rsnd_of_data *of_data, ++ struct rsnd_priv *priv); ++void rsnd_ssi_remove(struct platform_device *pdev, ++ struct rsnd_priv *priv); ++struct rsnd_mod *rsnd_ssi_mod_get(struct rsnd_priv *priv, int id); ++int rsnd_ssi_is_pin_sharing(struct rsnd_mod *mod); ++int rsnd_ssi_is_dma_mode(struct rsnd_mod *mod); ++int rsnd_ssi_use_busif(struct rsnd_dai_stream *io, struct rsnd_mod *mod); ++ ++/* + * R-Car SRC + */ + int rsnd_src_probe(struct platform_device *pdev, +@@ -555,19 +568,6 @@ int rsnd_src_ssi_irq_enable(struct rsnd_mod *ssi_mod); + int rsnd_src_ssi_irq_disable(struct rsnd_mod *ssi_mod); + + /* +- * R-Car SSI +- */ +-int rsnd_ssi_probe(struct platform_device *pdev, +- const struct rsnd_of_data *of_data, +- struct rsnd_priv *priv); +-void rsnd_ssi_remove(struct platform_device *pdev, +- struct rsnd_priv *priv); +-struct rsnd_mod *rsnd_ssi_mod_get(struct rsnd_priv *priv, int id); +-int rsnd_ssi_is_pin_sharing(struct rsnd_mod *mod); +-int rsnd_ssi_is_dma_mode(struct rsnd_mod *mod); +-int rsnd_ssi_use_busif(struct rsnd_dai_stream *io, struct rsnd_mod *mod); +- +-/* + * R-Car DVC + */ + int rsnd_dvc_probe(struct platform_device *pdev, +-- +2.6.2 + diff --git a/patches.renesas/0304-ASoC-rsnd-update-Audio-DMA-path-search-method.patch b/patches.renesas/0304-ASoC-rsnd-update-Audio-DMA-path-search-method.patch new file mode 100644 index 00000000000000..001c37eaf84f89 --- /dev/null +++ b/patches.renesas/0304-ASoC-rsnd-update-Audio-DMA-path-search-method.patch @@ -0,0 +1,151 @@ +From dd7acd3130abc9664ae6bd2a00517b3b82c16c05 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:16:56 +0000 +Subject: [PATCH 304/326] ASoC: rsnd: update Audio DMA path search method + +Current rsnd driver is assuming Audio DMAC / Audio DMAC peri peri +are used from SSI/SSIU/SRC/DVC. But we will add CTU/MIX to this driver. +Then, current DMA path searching method is not understandable, and good +enough for this purpose. This patch update DMA path search method, more +simply. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 7dfb49194557ccf27ab99c8c04c021320e7ae458) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/dma.c | 88 +++++++++++++++++++++++++++++-------------------- + 1 file changed, 53 insertions(+), 35 deletions(-) + +diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c +index a175863d239c..23282f48f71f 100644 +--- a/sound/soc/sh/rcar/dma.c ++++ b/sound/soc/sh/rcar/dma.c +@@ -494,7 +494,7 @@ static dma_addr_t rsnd_dma_addr(struct rsnd_dai_stream *io, + return rsnd_gen2_dma_addr(io, mod, is_play, is_from); + } + +-#define MOD_MAX 4 /* MEM/SSI/SRC/DVC */ ++#define MOD_MAX (RSND_MOD_MAX + 1) /* +Memory */ + static void rsnd_dma_of_path(struct rsnd_dma *dma, + struct rsnd_dai_stream *io, + int is_play, +@@ -506,53 +506,71 @@ static void rsnd_dma_of_path(struct rsnd_dma *dma, + struct rsnd_mod *src = rsnd_io_to_mod_src(io); + struct rsnd_mod *dvc = rsnd_io_to_mod_dvc(io); + struct rsnd_mod *mod[MOD_MAX]; +- int i, index; ++ struct rsnd_mod *mod_start, *mod_end; ++ struct rsnd_priv *priv = rsnd_mod_to_priv(this); ++ struct device *dev = rsnd_priv_to_dev(priv); ++ int nr, i; + ++ if (!ssi) ++ return; + +- for (i = 0; i < MOD_MAX; i++) ++ nr = 0; ++ for (i = 0; i < MOD_MAX; i++) { + mod[i] = NULL; ++ nr += !!rsnd_io_to_mod(io, i); ++ } + + /* +- * in play case... ++ * [S] -*-> [E] ++ * [S] -*-> SRC -o-> [E] ++ * [S] -*-> SRC -> DVC -o-> [E] ++ * [S] -*-> SRC -> CTU -> MIX -> DVC -o-> [E] ++ * ++ * playback [S] = mem ++ * [E] = SSI + * +- * src -> dst ++ * capture [S] = SSI ++ * [E] = mem + * +- * mem -> SSI +- * mem -> SRC -> SSI +- * mem -> SRC -> DVC -> SSI ++ * -*-> Audio DMAC ++ * -o-> Audio DMAC peri peri + */ +- mod[0] = NULL; /* for "mem" */ +- index = 1; +- for (i = 1; i < MOD_MAX; i++) { +- if (!src) { +- mod[i] = ssi; +- } else if (!dvc) { +- mod[i] = src; +- src = NULL; +- } else { +- if ((!is_play) && (this == src)) +- this = dvc; ++ mod_start = (is_play) ? NULL : ssi; ++ mod_end = (is_play) ? ssi : NULL; + +- mod[i] = (is_play) ? src : dvc; +- i++; +- mod[i] = (is_play) ? dvc : src; ++ mod[0] = mod_start; ++ for (i = 1; i < nr; i++) { ++ if (src) { ++ mod[i] = src; + src = NULL; ++ } else if (dvc) { ++ mod[i] = dvc; + dvc = NULL; + } +- +- if (mod[i] == this) +- index = i; +- +- if (mod[i] == ssi) +- break; + } ++ mod[i] = mod_end; + +- if (is_play) { +- *mod_from = mod[index - 1]; +- *mod_to = mod[index]; ++ /* ++ * | SSI | SRC | ++ * -------------+-----+-----+ ++ * is_play | o | * | ++ * !is_play | * | o | ++ */ ++ if ((this == ssi) == (is_play)) { ++ *mod_from = mod[nr - 1]; ++ *mod_to = mod[nr]; + } else { +- *mod_from = mod[index]; +- *mod_to = mod[index - 1]; ++ *mod_from = mod[0]; ++ *mod_to = mod[1]; ++ } ++ ++ dev_dbg(dev, "module connection (this is %s[%d])\n", ++ rsnd_mod_name(this), rsnd_mod_id(this)); ++ for (i = 0; i <= nr; i++) { ++ dev_dbg(dev, " %s[%d]%s\n", ++ rsnd_mod_name(mod[i]), rsnd_mod_id(mod[i]), ++ (mod[i] == *mod_from) ? " from" : ++ (mod[i] == *mod_to) ? " to" : ""); + } + } + +@@ -580,8 +598,8 @@ void rsnd_dma_quit(struct rsnd_dai_stream *io, struct rsnd_dma *dma) + + int rsnd_dma_init(struct rsnd_dai_stream *io, struct rsnd_dma *dma, int id) + { +- struct rsnd_mod *mod_from; +- struct rsnd_mod *mod_to; ++ struct rsnd_mod *mod_from = NULL; ++ struct rsnd_mod *mod_to = NULL; + struct rsnd_priv *priv = rsnd_io_to_priv(io); + struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv); + struct device *dev = rsnd_priv_to_dev(priv); +-- +2.6.2 + diff --git a/patches.renesas/0305-ASoC-rsnd-add-CTU-Channel-Transfer-Unit-prototype-su.patch b/patches.renesas/0305-ASoC-rsnd-add-CTU-Channel-Transfer-Unit-prototype-su.patch new file mode 100644 index 00000000000000..be3327220b71b4 --- /dev/null +++ b/patches.renesas/0305-ASoC-rsnd-add-CTU-Channel-Transfer-Unit-prototype-su.patch @@ -0,0 +1,474 @@ +From 0aad802f0729d249b1b54b23aa2ccde06dbedd7d Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:17:17 +0000 +Subject: [PATCH 305/326] ASoC: rsnd: add CTU (Channel Transfer Unit) prototype + support + +This patch adds CTU (Channel Transfer Unit) support for rsnd driver. +But, it does nothing to data at this point, but is required for MIX +support. + +CTU design is a little different from other IPs (CTU0 is including +CTU00 - CTU03, and CTU1 is including CTU10 - CTU13, these have different +register mapping) We need to care about it on this driver. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 9269e3c3cfac277a49b485e27ac6850f9a11a259) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../devicetree/bindings/sound/renesas,rsnd.txt | 14 ++ + include/sound/rcar_snd.h | 7 + + sound/soc/sh/rcar/Makefile | 2 +- + sound/soc/sh/rcar/core.c | 12 +- + sound/soc/sh/rcar/ctu.c | 171 +++++++++++++++++++++ + sound/soc/sh/rcar/dma.c | 13 +- + sound/soc/sh/rcar/gen.c | 2 + + sound/soc/sh/rcar/rsnd.h | 21 +++ + 8 files changed, 236 insertions(+), 6 deletions(-) + create mode 100644 sound/soc/sh/rcar/ctu.c + +diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +index b6b3a786855f..278607de05de 100644 +--- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt ++++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +@@ -18,6 +18,9 @@ Required properties: + - rcar_sound,src : Should contain SRC feature. + The number of SRC subnode should be same as HW. + see below for detail. ++- rcar_sound,ctu : Should contain CTU feature. ++ The number of CTU subnode should be same as HW. ++ see below for detail. + - rcar_sound,dvc : Should contain DVC feature. + The number of DVC subnode should be same as HW. + see below for detail. +@@ -90,6 +93,17 @@ rcar_sound: sound@ec500000 { + }; + }; + ++ rcar_sound,ctu { ++ ctu00: ctu@0 { }; ++ ctu01: ctu@1 { }; ++ ctu02: ctu@2 { }; ++ ctu03: ctu@3 { }; ++ ctu10: ctu@4 { }; ++ ctu11: ctu@5 { }; ++ ctu12: ctu@6 { }; ++ ctu13: ctu@7 { }; ++ }; ++ + rcar_sound,src { + src0: src@0 { + interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; +diff --git a/include/sound/rcar_snd.h b/include/sound/rcar_snd.h +index 4cecd0c175f6..8f9303093ab9 100644 +--- a/include/sound/rcar_snd.h ++++ b/include/sound/rcar_snd.h +@@ -61,6 +61,10 @@ struct rsnd_src_platform_info { + /* + * flags + */ ++struct rsnd_ctu_platform_info { ++ u32 flags; ++}; ++ + struct rsnd_dvc_platform_info { + u32 flags; + }; +@@ -68,6 +72,7 @@ struct rsnd_dvc_platform_info { + struct rsnd_dai_path_info { + struct rsnd_ssi_platform_info *ssi; + struct rsnd_src_platform_info *src; ++ struct rsnd_ctu_platform_info *ctu; + struct rsnd_dvc_platform_info *dvc; + }; + +@@ -93,6 +98,8 @@ struct rcar_snd_info { + int ssi_info_nr; + struct rsnd_src_platform_info *src_info; + int src_info_nr; ++ struct rsnd_ctu_platform_info *ctu_info; ++ int ctu_info_nr; + struct rsnd_dvc_platform_info *dvc_info; + int dvc_info_nr; + struct rsnd_dai_platform_info *dai_info; +diff --git a/sound/soc/sh/rcar/Makefile b/sound/soc/sh/rcar/Makefile +index 3a274fd3593c..7c4730a81c4a 100644 +--- a/sound/soc/sh/rcar/Makefile ++++ b/sound/soc/sh/rcar/Makefile +@@ -1,4 +1,4 @@ +-snd-soc-rcar-objs := core.o gen.o dma.o adg.o ssi.o src.o dvc.o ++snd-soc-rcar-objs := core.o gen.o dma.o adg.o ssi.o src.o ctu.o dvc.o + obj-$(CONFIG_SND_SOC_RCAR) += snd-soc-rcar.o + + snd-soc-rsrc-card-objs := rsrc-card.o +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index e20d8ea0aafe..63ae7bbfd1dc 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -651,6 +651,11 @@ static int rsnd_path_init(struct rsnd_priv *priv, + if (ret < 0) + return ret; + ++ /* CTU */ ++ ret = rsnd_path_add(priv, io, ctu); ++ if (ret < 0) ++ return ret; ++ + /* DVC */ + ret = rsnd_path_add(priv, io, dvc); + if (ret < 0) +@@ -666,13 +671,14 @@ static void rsnd_of_parse_dai(struct platform_device *pdev, + struct device_node *dai_node, *dai_np; + struct device_node *ssi_node, *ssi_np; + struct device_node *src_node, *src_np; ++ struct device_node *ctu_node, *ctu_np; + struct device_node *dvc_node, *dvc_np; + struct device_node *playback, *capture; + struct rsnd_dai_platform_info *dai_info; + struct rcar_snd_info *info = rsnd_priv_to_info(priv); + struct device *dev = &pdev->dev; + int nr, i; +- int dai_i, ssi_i, src_i, dvc_i; ++ int dai_i, ssi_i, src_i, ctu_i, dvc_i; + + if (!of_data) + return; +@@ -698,6 +704,7 @@ static void rsnd_of_parse_dai(struct platform_device *pdev, + + ssi_node = of_get_child_by_name(dev->of_node, "rcar_sound,ssi"); + src_node = of_get_child_by_name(dev->of_node, "rcar_sound,src"); ++ ctu_node = of_get_child_by_name(dev->of_node, "rcar_sound,ctu"); + dvc_node = of_get_child_by_name(dev->of_node, "rcar_sound,dvc"); + + #define mod_parse(name) \ +@@ -734,6 +741,7 @@ if (name##_node) { \ + + mod_parse(ssi); + mod_parse(src); ++ mod_parse(ctu); + mod_parse(dvc); + + of_node_put(playback); +@@ -1146,6 +1154,7 @@ static int rsnd_probe(struct platform_device *pdev) + rsnd_dma_probe, + rsnd_ssi_probe, + rsnd_src_probe, ++ rsnd_ctu_probe, + rsnd_dvc_probe, + rsnd_adg_probe, + rsnd_dai_probe, +@@ -1241,6 +1250,7 @@ static int rsnd_remove(struct platform_device *pdev) + struct rsnd_priv *priv) = { + rsnd_ssi_remove, + rsnd_src_remove, ++ rsnd_ctu_remove, + rsnd_dvc_remove, + }; + int ret = 0, i; +diff --git a/sound/soc/sh/rcar/ctu.c b/sound/soc/sh/rcar/ctu.c +new file mode 100644 +index 000000000000..05edd2009b81 +--- /dev/null ++++ b/sound/soc/sh/rcar/ctu.c +@@ -0,0 +1,171 @@ ++/* ++ * ctu.c ++ * ++ * Copyright (c) 2015 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include "rsnd.h" ++ ++#define CTU_NAME_SIZE 16 ++#define CTU_NAME "ctu" ++ ++struct rsnd_ctu { ++ struct rsnd_ctu_platform_info *info; /* rcar_snd.h */ ++ struct rsnd_mod mod; ++}; ++ ++#define rsnd_ctu_nr(priv) ((priv)->ctu_nr) ++#define for_each_rsnd_ctu(pos, priv, i) \ ++ for ((i) = 0; \ ++ ((i) < rsnd_ctu_nr(priv)) && \ ++ ((pos) = (struct rsnd_ctu *)(priv)->ctu + i); \ ++ i++) ++ ++#define rsnd_ctu_initialize_lock(mod) __rsnd_ctu_initialize_lock(mod, 1) ++#define rsnd_ctu_initialize_unlock(mod) __rsnd_ctu_initialize_lock(mod, 0) ++static void __rsnd_ctu_initialize_lock(struct rsnd_mod *mod, u32 enable) ++{ ++ rsnd_mod_write(mod, CTU_CTUIR, enable); ++} ++ ++static int rsnd_ctu_init(struct rsnd_mod *mod, ++ struct rsnd_dai_stream *io, ++ struct rsnd_priv *priv) ++{ ++ rsnd_mod_hw_start(mod); ++ ++ rsnd_ctu_initialize_lock(mod); ++ ++ rsnd_mod_write(mod, CTU_ADINR, rsnd_get_adinr_chan(mod, io)); ++ ++ rsnd_ctu_initialize_unlock(mod); ++ ++ return 0; ++} ++ ++static int rsnd_ctu_quit(struct rsnd_mod *mod, ++ struct rsnd_dai_stream *io, ++ struct rsnd_priv *priv) ++{ ++ rsnd_mod_hw_stop(mod); ++ ++ return 0; ++} ++ ++static struct rsnd_mod_ops rsnd_ctu_ops = { ++ .name = CTU_NAME, ++ .init = rsnd_ctu_init, ++ .quit = rsnd_ctu_quit, ++}; ++ ++struct rsnd_mod *rsnd_ctu_mod_get(struct rsnd_priv *priv, int id) ++{ ++ if (WARN_ON(id < 0 || id >= rsnd_ctu_nr(priv))) ++ id = 0; ++ ++ return &((struct rsnd_ctu *)(priv->ctu) + id)->mod; ++} ++ ++void rsnd_of_parse_ctu(struct platform_device *pdev, ++ const struct rsnd_of_data *of_data, ++ struct rsnd_priv *priv) ++{ ++ struct device_node *node; ++ struct rsnd_ctu_platform_info *ctu_info; ++ struct rcar_snd_info *info = rsnd_priv_to_info(priv); ++ struct device *dev = &pdev->dev; ++ int nr; ++ ++ if (!of_data) ++ return; ++ ++ node = of_get_child_by_name(dev->of_node, "rcar_sound,ctu"); ++ if (!node) ++ return; ++ ++ nr = of_get_child_count(node); ++ if (!nr) ++ goto rsnd_of_parse_ctu_end; ++ ++ ctu_info = devm_kzalloc(dev, ++ sizeof(struct rsnd_ctu_platform_info) * nr, ++ GFP_KERNEL); ++ if (!ctu_info) { ++ dev_err(dev, "ctu info allocation error\n"); ++ goto rsnd_of_parse_ctu_end; ++ } ++ ++ info->ctu_info = ctu_info; ++ info->ctu_info_nr = nr; ++ ++rsnd_of_parse_ctu_end: ++ of_node_put(node); ++ ++} ++ ++int rsnd_ctu_probe(struct platform_device *pdev, ++ const struct rsnd_of_data *of_data, ++ struct rsnd_priv *priv) ++{ ++ struct rcar_snd_info *info = rsnd_priv_to_info(priv); ++ struct device *dev = rsnd_priv_to_dev(priv); ++ struct rsnd_ctu *ctu; ++ struct clk *clk; ++ char name[CTU_NAME_SIZE]; ++ int i, nr, ret; ++ ++ /* This driver doesn't support Gen1 at this point */ ++ if (rsnd_is_gen1(priv)) { ++ dev_warn(dev, "CTU is not supported on Gen1\n"); ++ return -EINVAL; ++ } ++ ++ rsnd_of_parse_ctu(pdev, of_data, priv); ++ ++ nr = info->ctu_info_nr; ++ if (!nr) ++ return 0; ++ ++ ctu = devm_kzalloc(dev, sizeof(*ctu) * nr, GFP_KERNEL); ++ if (!ctu) ++ return -ENOMEM; ++ ++ priv->ctu_nr = nr; ++ priv->ctu = ctu; ++ ++ for_each_rsnd_ctu(ctu, priv, i) { ++ /* ++ * CTU00, CTU01, CTU02, CTU03 => CTU0 ++ * CTU10, CTU11, CTU12, CTU13 => CTU1 ++ */ ++ snprintf(name, CTU_NAME_SIZE, "%s.%d", ++ CTU_NAME, i / 4); ++ ++ clk = devm_clk_get(dev, name); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ ctu->info = &info->ctu_info[i]; ++ ++ ret = rsnd_mod_init(priv, &ctu->mod, &rsnd_ctu_ops, ++ clk, RSND_MOD_CTU, i); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++void rsnd_ctu_remove(struct platform_device *pdev, ++ struct rsnd_priv *priv) ++{ ++ struct rsnd_ctu *ctu; ++ int i; ++ ++ for_each_rsnd_ctu(ctu, priv, i) { ++ rsnd_mod_quit(&ctu->mod); ++ } ++} +diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c +index 23282f48f71f..229b68d2cf70 100644 +--- a/sound/soc/sh/rcar/dma.c ++++ b/sound/soc/sh/rcar/dma.c +@@ -426,7 +426,8 @@ rsnd_gen2_dma_addr(struct rsnd_dai_stream *io, + phys_addr_t src_reg = rsnd_gen_get_phy_addr(priv, RSND_GEN2_SCU); + int is_ssi = !!(rsnd_io_to_mod_ssi(io) == mod); + int use_src = !!rsnd_io_to_mod_src(io); +- int use_dvc = !!rsnd_io_to_mod_dvc(io); ++ int use_cmd = !!rsnd_io_to_mod_dvc(io) || ++ !!rsnd_io_to_mod_ctu(io); + int id = rsnd_mod_id(mod); + struct dma_addr { + dma_addr_t out_addr; +@@ -464,7 +465,7 @@ rsnd_gen2_dma_addr(struct rsnd_dai_stream *io, + }; + + /* it shouldn't happen */ +- if (use_dvc && !use_src) ++ if (use_cmd && !use_src) + dev_err(dev, "DVC is selected without SRC\n"); + + /* use SSIU or SSI ? */ +@@ -472,8 +473,8 @@ rsnd_gen2_dma_addr(struct rsnd_dai_stream *io, + is_ssi++; + + return (is_from) ? +- dma_addrs[is_ssi][is_play][use_src + use_dvc].out_addr : +- dma_addrs[is_ssi][is_play][use_src + use_dvc].in_addr; ++ dma_addrs[is_ssi][is_play][use_src + use_cmd].out_addr : ++ dma_addrs[is_ssi][is_play][use_src + use_cmd].in_addr; + } + + static dma_addr_t rsnd_dma_addr(struct rsnd_dai_stream *io, +@@ -504,6 +505,7 @@ static void rsnd_dma_of_path(struct rsnd_dma *dma, + struct rsnd_mod *this = rsnd_dma_to_mod(dma); + struct rsnd_mod *ssi = rsnd_io_to_mod_ssi(io); + struct rsnd_mod *src = rsnd_io_to_mod_src(io); ++ struct rsnd_mod *ctu = rsnd_io_to_mod_ctu(io); + struct rsnd_mod *dvc = rsnd_io_to_mod_dvc(io); + struct rsnd_mod *mod[MOD_MAX]; + struct rsnd_mod *mod_start, *mod_end; +@@ -543,6 +545,9 @@ static void rsnd_dma_of_path(struct rsnd_dma *dma, + if (src) { + mod[i] = src; + src = NULL; ++ } else if (ctu) { ++ mod[i] = ctu; ++ ctu = NULL; + } else if (dvc) { + mod[i] = dvc; + dvc = NULL; +diff --git a/sound/soc/sh/rcar/gen.c b/sound/soc/sh/rcar/gen.c +index a2d5df4d5d17..41b75cd4e09b 100644 +--- a/sound/soc/sh/rcar/gen.c ++++ b/sound/soc/sh/rcar/gen.c +@@ -240,6 +240,8 @@ static int rsnd_gen2_probe(struct platform_device *pdev, + RSND_GEN_M_REG(SRC_SRCCR, 0x224, 0x40), + RSND_GEN_M_REG(SRC_BSDSR, 0x22c, 0x40), + RSND_GEN_M_REG(SRC_BSISR, 0x238, 0x40), ++ RSND_GEN_M_REG(CTU_CTUIR, 0x504, 0x100), ++ RSND_GEN_M_REG(CTU_ADINR, 0x508, 0x100), + RSND_GEN_M_REG(DVC_SWRSR, 0xe00, 0x100), + RSND_GEN_M_REG(DVC_DVUIR, 0xe04, 0x100), + RSND_GEN_M_REG(DVC_ADINR, 0xe08, 0x100), +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 7fee2079ba5a..f2128a7cf259 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -47,6 +47,8 @@ enum rsnd_reg { + RSND_REG_SCU_SYS_STATUS0, + RSND_REG_SCU_SYS_INT_EN0, + RSND_REG_CMD_ROUTE_SLCT, ++ RSND_REG_CTU_CTUIR, ++ RSND_REG_CTU_ADINR, + RSND_REG_DVC_SWRSR, + RSND_REG_DVC_DVUIR, + RSND_REG_DVC_ADINR, +@@ -220,6 +222,7 @@ struct dma_chan *rsnd_dma_request_channel(struct device_node *of_node, + */ + enum rsnd_mod_type { + RSND_MOD_DVC = 0, ++ RSND_MOD_CTU, + RSND_MOD_SRC, + RSND_MOD_SSI, + RSND_MOD_MAX, +@@ -351,6 +354,7 @@ struct rsnd_dai_stream { + #define rsnd_io_to_mod(io, i) ((i) < RSND_MOD_MAX ? (io)->mod[(i)] : NULL) + #define rsnd_io_to_mod_ssi(io) rsnd_io_to_mod((io), RSND_MOD_SSI) + #define rsnd_io_to_mod_src(io) rsnd_io_to_mod((io), RSND_MOD_SRC) ++#define rsnd_io_to_mod_ctu(io) rsnd_io_to_mod((io), RSND_MOD_CTU) + #define rsnd_io_to_mod_dvc(io) rsnd_io_to_mod((io), RSND_MOD_DVC) + #define rsnd_io_to_rdai(io) ((io)->rdai) + #define rsnd_io_to_priv(io) (rsnd_rdai_to_priv(rsnd_io_to_rdai(io))) +@@ -463,6 +467,12 @@ struct rsnd_priv { + int src_nr; + + /* ++ * below value will be filled on rsnd_ctu_probe() ++ */ ++ void *ctu; ++ int ctu_nr; ++ ++ /* + * below value will be filled on rsnd_dvc_probe() + */ + void *dvc; +@@ -568,6 +578,17 @@ int rsnd_src_ssi_irq_enable(struct rsnd_mod *ssi_mod); + int rsnd_src_ssi_irq_disable(struct rsnd_mod *ssi_mod); + + /* ++ * R-Car CTU ++ */ ++int rsnd_ctu_probe(struct platform_device *pdev, ++ const struct rsnd_of_data *of_data, ++ struct rsnd_priv *priv); ++ ++void rsnd_ctu_remove(struct platform_device *pdev, ++ struct rsnd_priv *priv); ++struct rsnd_mod *rsnd_ctu_mod_get(struct rsnd_priv *priv, int id); ++ ++/* + * R-Car DVC + */ + int rsnd_dvc_probe(struct platform_device *pdev, +-- +2.6.2 + diff --git a/patches.renesas/0306-ASoC-rsnd-add-MIX-Mixer-support.patch b/patches.renesas/0306-ASoC-rsnd-add-MIX-Mixer-support.patch new file mode 100644 index 00000000000000..595bca2be5696f --- /dev/null +++ b/patches.renesas/0306-ASoC-rsnd-add-MIX-Mixer-support.patch @@ -0,0 +1,611 @@ +From 91949d91db62cb7b7ce9704d37c4b24453d5afc5 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Jul 2015 07:17:36 +0000 +Subject: [PATCH 306/326] ASoC: rsnd: add MIX (Mixer) support + +This patch adds MIX (Mixer) initial support for rsnd driver. +It is assuming that this MIX is used via DPCM. + +This is sample code for playback. + + CPU0 : [MEM] -> [SRC1] -> [CTU02] -+ + | + +-> [MIX0] -> [DVC0] -> [SSI0] + | + CPU1 : [MEM] -> [SRC2] -> [CTU03] -+ + + sound { + compatible = "renesas,rsrc-card"; + + ... + + cpu@0 { + sound-dai = <&rcar_sound 0>; + }; + + cpu@1 { + sound-dai = <&rcar_sound 1>; + }; + + codec { + ... + }; + }; + + rcar_sound { + + ... + + rcar_sound,dai { + dai0 { + playback = <&src1 &ctu02 &mix0 &dvc0 &ssi0>; + }; + dai1 { + playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>; + }; + }; + }; + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 70fb10529f61c31c26397a02091177bedd23217d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../devicetree/bindings/sound/renesas,rsnd.txt | 8 + + include/sound/rcar_snd.h | 7 + + sound/soc/sh/rcar/Makefile | 2 +- + sound/soc/sh/rcar/core.c | 85 +++++++-- + sound/soc/sh/rcar/dma.c | 5 + + sound/soc/sh/rcar/gen.c | 10 ++ + sound/soc/sh/rcar/mix.c | 200 +++++++++++++++++++++ + sound/soc/sh/rcar/rsnd.h | 29 +++ + 8 files changed, 333 insertions(+), 13 deletions(-) + create mode 100644 sound/soc/sh/rcar/mix.c + +diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +index 278607de05de..1173395b5e5c 100644 +--- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt ++++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +@@ -21,6 +21,9 @@ Required properties: + - rcar_sound,ctu : Should contain CTU feature. + The number of CTU subnode should be same as HW. + see below for detail. ++- rcar_sound,mix : Should contain MIX feature. ++ The number of MIX subnode should be same as HW. ++ see below for detail. + - rcar_sound,dvc : Should contain DVC feature. + The number of DVC subnode should be same as HW. + see below for detail. +@@ -93,6 +96,11 @@ rcar_sound: sound@ec500000 { + }; + }; + ++ rcar_sound,mix { ++ mix0: mix@0 { }; ++ mix1: mix@1 { }; ++ }; ++ + rcar_sound,ctu { + ctu00: ctu@0 { }; + ctu01: ctu@1 { }; +diff --git a/include/sound/rcar_snd.h b/include/sound/rcar_snd.h +index 8f9303093ab9..bb7b2ebfee7b 100644 +--- a/include/sound/rcar_snd.h ++++ b/include/sound/rcar_snd.h +@@ -65,6 +65,10 @@ struct rsnd_ctu_platform_info { + u32 flags; + }; + ++struct rsnd_mix_platform_info { ++ u32 flags; ++}; ++ + struct rsnd_dvc_platform_info { + u32 flags; + }; +@@ -73,6 +77,7 @@ struct rsnd_dai_path_info { + struct rsnd_ssi_platform_info *ssi; + struct rsnd_src_platform_info *src; + struct rsnd_ctu_platform_info *ctu; ++ struct rsnd_mix_platform_info *mix; + struct rsnd_dvc_platform_info *dvc; + }; + +@@ -100,6 +105,8 @@ struct rcar_snd_info { + int src_info_nr; + struct rsnd_ctu_platform_info *ctu_info; + int ctu_info_nr; ++ struct rsnd_mix_platform_info *mix_info; ++ int mix_info_nr; + struct rsnd_dvc_platform_info *dvc_info; + int dvc_info_nr; + struct rsnd_dai_platform_info *dai_info; +diff --git a/sound/soc/sh/rcar/Makefile b/sound/soc/sh/rcar/Makefile +index 7c4730a81c4a..8b258501aa35 100644 +--- a/sound/soc/sh/rcar/Makefile ++++ b/sound/soc/sh/rcar/Makefile +@@ -1,4 +1,4 @@ +-snd-soc-rcar-objs := core.o gen.o dma.o adg.o ssi.o src.o ctu.o dvc.o ++snd-soc-rcar-objs := core.o gen.o dma.o adg.o ssi.o src.o ctu.o mix.o dvc.o + obj-$(CONFIG_SND_SOC_RCAR) += snd-soc-rcar.o + + snd-soc-rsrc-card-objs := rsrc-card.o +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index 63ae7bbfd1dc..927a7b02123b 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -605,23 +605,74 @@ static const struct snd_soc_dai_ops rsnd_soc_dai_ops = { + void rsnd_path_parse(struct rsnd_priv *priv, + struct rsnd_dai_stream *io) + { +- struct rsnd_mod *src = rsnd_io_to_mod_src(io); + struct rsnd_mod *dvc = rsnd_io_to_mod_dvc(io); +- int src_id = rsnd_mod_id(src); +- u32 path[] = { +- [0] = 0x30000, +- [1] = 0x30001, +- [2] = 0x40000, +- [3] = 0x10000, +- [4] = 0x20000, +- [5] = 0x40100 +- }; ++ struct rsnd_mod *mix = rsnd_io_to_mod_mix(io); ++ struct rsnd_mod *src = rsnd_io_to_mod_src(io); ++ struct rsnd_mod *cmd; ++ struct device *dev = rsnd_priv_to_dev(priv); ++ u32 data; + + /* Gen1 is not supported */ + if (rsnd_is_gen1(priv)) + return; + +- rsnd_mod_write(dvc, CMD_ROUTE_SLCT, path[src_id]); ++ if (!mix && !dvc) ++ return; ++ ++ if (mix) { ++ struct rsnd_dai *rdai; ++ int i; ++ u32 path[] = { ++ [0] = 0, ++ [1] = 1 << 0, ++ [2] = 0, ++ [3] = 0, ++ [4] = 0, ++ [5] = 1 << 8 ++ }; ++ ++ /* ++ * it is assuming that integrater is well understanding about ++ * data path. Here doesn't check impossible connection, ++ * like src2 + src5 ++ */ ++ data = 0; ++ for_each_rsnd_dai(rdai, priv, i) { ++ io = &rdai->playback; ++ if (mix == rsnd_io_to_mod_mix(io)) ++ data |= path[rsnd_mod_id(src)]; ++ ++ io = &rdai->capture; ++ if (mix == rsnd_io_to_mod_mix(io)) ++ data |= path[rsnd_mod_id(src)]; ++ } ++ ++ /* ++ * We can't use ctu = rsnd_io_ctu() here. ++ * Since, ID of dvc/mix are 0 or 1 (= same as CMD number) ++ * but ctu IDs are 0 - 7 (= CTU00 - CTU13) ++ */ ++ cmd = mix; ++ } else { ++ u32 path[] = { ++ [0] = 0x30000, ++ [1] = 0x30001, ++ [2] = 0x40000, ++ [3] = 0x10000, ++ [4] = 0x20000, ++ [5] = 0x40100 ++ }; ++ ++ data = path[rsnd_mod_id(src)]; ++ ++ cmd = dvc; ++ } ++ ++ dev_dbg(dev, "ctu/mix path = 0x%08x", data); ++ ++ rsnd_mod_write(cmd, CMD_ROUTE_SLCT, data); ++ ++ rsnd_mod_write(cmd, CMD_CTRL, 0x10); + } + + static int rsnd_path_init(struct rsnd_priv *priv, +@@ -656,6 +707,11 @@ static int rsnd_path_init(struct rsnd_priv *priv, + if (ret < 0) + return ret; + ++ /* MIX */ ++ ret = rsnd_path_add(priv, io, mix); ++ if (ret < 0) ++ return ret; ++ + /* DVC */ + ret = rsnd_path_add(priv, io, dvc); + if (ret < 0) +@@ -672,13 +728,14 @@ static void rsnd_of_parse_dai(struct platform_device *pdev, + struct device_node *ssi_node, *ssi_np; + struct device_node *src_node, *src_np; + struct device_node *ctu_node, *ctu_np; ++ struct device_node *mix_node, *mix_np; + struct device_node *dvc_node, *dvc_np; + struct device_node *playback, *capture; + struct rsnd_dai_platform_info *dai_info; + struct rcar_snd_info *info = rsnd_priv_to_info(priv); + struct device *dev = &pdev->dev; + int nr, i; +- int dai_i, ssi_i, src_i, ctu_i, dvc_i; ++ int dai_i, ssi_i, src_i, ctu_i, mix_i, dvc_i; + + if (!of_data) + return; +@@ -705,6 +762,7 @@ static void rsnd_of_parse_dai(struct platform_device *pdev, + ssi_node = of_get_child_by_name(dev->of_node, "rcar_sound,ssi"); + src_node = of_get_child_by_name(dev->of_node, "rcar_sound,src"); + ctu_node = of_get_child_by_name(dev->of_node, "rcar_sound,ctu"); ++ mix_node = of_get_child_by_name(dev->of_node, "rcar_sound,mix"); + dvc_node = of_get_child_by_name(dev->of_node, "rcar_sound,dvc"); + + #define mod_parse(name) \ +@@ -742,6 +800,7 @@ if (name##_node) { \ + mod_parse(ssi); + mod_parse(src); + mod_parse(ctu); ++ mod_parse(mix); + mod_parse(dvc); + + of_node_put(playback); +@@ -1155,6 +1214,7 @@ static int rsnd_probe(struct platform_device *pdev) + rsnd_ssi_probe, + rsnd_src_probe, + rsnd_ctu_probe, ++ rsnd_mix_probe, + rsnd_dvc_probe, + rsnd_adg_probe, + rsnd_dai_probe, +@@ -1251,6 +1311,7 @@ static int rsnd_remove(struct platform_device *pdev) + rsnd_ssi_remove, + rsnd_src_remove, + rsnd_ctu_remove, ++ rsnd_mix_remove, + rsnd_dvc_remove, + }; + int ret = 0, i; +diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c +index 229b68d2cf70..305b12929853 100644 +--- a/sound/soc/sh/rcar/dma.c ++++ b/sound/soc/sh/rcar/dma.c +@@ -427,6 +427,7 @@ rsnd_gen2_dma_addr(struct rsnd_dai_stream *io, + int is_ssi = !!(rsnd_io_to_mod_ssi(io) == mod); + int use_src = !!rsnd_io_to_mod_src(io); + int use_cmd = !!rsnd_io_to_mod_dvc(io) || ++ !!rsnd_io_to_mod_mix(io) || + !!rsnd_io_to_mod_ctu(io); + int id = rsnd_mod_id(mod); + struct dma_addr { +@@ -506,6 +507,7 @@ static void rsnd_dma_of_path(struct rsnd_dma *dma, + struct rsnd_mod *ssi = rsnd_io_to_mod_ssi(io); + struct rsnd_mod *src = rsnd_io_to_mod_src(io); + struct rsnd_mod *ctu = rsnd_io_to_mod_ctu(io); ++ struct rsnd_mod *mix = rsnd_io_to_mod_mix(io); + struct rsnd_mod *dvc = rsnd_io_to_mod_dvc(io); + struct rsnd_mod *mod[MOD_MAX]; + struct rsnd_mod *mod_start, *mod_end; +@@ -548,6 +550,9 @@ static void rsnd_dma_of_path(struct rsnd_dma *dma, + } else if (ctu) { + mod[i] = ctu; + ctu = NULL; ++ } else if (mix) { ++ mod[i] = mix; ++ mix = NULL; + } else if (dvc) { + mod[i] = dvc; + dvc = NULL; +diff --git a/sound/soc/sh/rcar/gen.c b/sound/soc/sh/rcar/gen.c +index 41b75cd4e09b..f04d17bc6e3d 100644 +--- a/sound/soc/sh/rcar/gen.c ++++ b/sound/soc/sh/rcar/gen.c +@@ -242,6 +242,16 @@ static int rsnd_gen2_probe(struct platform_device *pdev, + RSND_GEN_M_REG(SRC_BSISR, 0x238, 0x40), + RSND_GEN_M_REG(CTU_CTUIR, 0x504, 0x100), + RSND_GEN_M_REG(CTU_ADINR, 0x508, 0x100), ++ RSND_GEN_M_REG(MIX_SWRSR, 0xd00, 0x40), ++ RSND_GEN_M_REG(MIX_MIXIR, 0xd04, 0x40), ++ RSND_GEN_M_REG(MIX_ADINR, 0xd08, 0x40), ++ RSND_GEN_M_REG(MIX_MIXMR, 0xd10, 0x40), ++ RSND_GEN_M_REG(MIX_MVPDR, 0xd14, 0x40), ++ RSND_GEN_M_REG(MIX_MDBAR, 0xd18, 0x40), ++ RSND_GEN_M_REG(MIX_MDBBR, 0xd1c, 0x40), ++ RSND_GEN_M_REG(MIX_MDBCR, 0xd20, 0x40), ++ RSND_GEN_M_REG(MIX_MDBDR, 0xd24, 0x40), ++ RSND_GEN_M_REG(MIX_MDBER, 0xd28, 0x40), + RSND_GEN_M_REG(DVC_SWRSR, 0xe00, 0x100), + RSND_GEN_M_REG(DVC_DVUIR, 0xe04, 0x100), + RSND_GEN_M_REG(DVC_ADINR, 0xe08, 0x100), +diff --git a/sound/soc/sh/rcar/mix.c b/sound/soc/sh/rcar/mix.c +new file mode 100644 +index 000000000000..0d5c102db6f5 +--- /dev/null ++++ b/sound/soc/sh/rcar/mix.c +@@ -0,0 +1,200 @@ ++/* ++ * mix.c ++ * ++ * Copyright (c) 2015 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include "rsnd.h" ++ ++#define MIX_NAME_SIZE 16 ++#define MIX_NAME "mix" ++ ++struct rsnd_mix { ++ struct rsnd_mix_platform_info *info; /* rcar_snd.h */ ++ struct rsnd_mod mod; ++}; ++ ++#define rsnd_mix_nr(priv) ((priv)->mix_nr) ++#define for_each_rsnd_mix(pos, priv, i) \ ++ for ((i) = 0; \ ++ ((i) < rsnd_mix_nr(priv)) && \ ++ ((pos) = (struct rsnd_mix *)(priv)->mix + i); \ ++ i++) ++ ++ ++static void rsnd_mix_soft_reset(struct rsnd_mod *mod) ++{ ++ rsnd_mod_write(mod, MIX_SWRSR, 0); ++ rsnd_mod_write(mod, MIX_SWRSR, 1); ++} ++ ++#define rsnd_mix_initialize_lock(mod) __rsnd_mix_initialize_lock(mod, 1) ++#define rsnd_mix_initialize_unlock(mod) __rsnd_mix_initialize_lock(mod, 0) ++static void __rsnd_mix_initialize_lock(struct rsnd_mod *mod, u32 enable) ++{ ++ rsnd_mod_write(mod, MIX_MIXIR, enable); ++} ++ ++static void rsnd_mix_volume_update(struct rsnd_dai_stream *io, ++ struct rsnd_mod *mod) ++{ ++ ++ /* Disable MIX dB setting */ ++ rsnd_mod_write(mod, MIX_MDBER, 0); ++ ++ rsnd_mod_write(mod, MIX_MDBAR, 0); ++ rsnd_mod_write(mod, MIX_MDBBR, 0); ++ rsnd_mod_write(mod, MIX_MDBCR, 0); ++ rsnd_mod_write(mod, MIX_MDBDR, 0); ++ ++ /* Enable MIX dB setting */ ++ rsnd_mod_write(mod, MIX_MDBER, 1); ++} ++ ++static int rsnd_mix_init(struct rsnd_mod *mod, ++ struct rsnd_dai_stream *io, ++ struct rsnd_priv *priv) ++{ ++ rsnd_mod_hw_start(mod); ++ ++ rsnd_mix_soft_reset(mod); ++ ++ rsnd_mix_initialize_lock(mod); ++ ++ rsnd_mod_write(mod, MIX_ADINR, rsnd_get_adinr_chan(mod, io)); ++ ++ rsnd_path_parse(priv, io); ++ ++ /* volume step */ ++ rsnd_mod_write(mod, MIX_MIXMR, 0); ++ rsnd_mod_write(mod, MIX_MVPDR, 0); ++ ++ rsnd_mix_volume_update(io, mod); ++ ++ rsnd_mix_initialize_unlock(mod); ++ ++ return 0; ++} ++ ++static int rsnd_mix_quit(struct rsnd_mod *mod, ++ struct rsnd_dai_stream *io, ++ struct rsnd_priv *priv) ++{ ++ rsnd_mod_hw_stop(mod); ++ ++ return 0; ++} ++ ++static struct rsnd_mod_ops rsnd_mix_ops = { ++ .name = MIX_NAME, ++ .init = rsnd_mix_init, ++ .quit = rsnd_mix_quit, ++}; ++ ++struct rsnd_mod *rsnd_mix_mod_get(struct rsnd_priv *priv, int id) ++{ ++ if (WARN_ON(id < 0 || id >= rsnd_mix_nr(priv))) ++ id = 0; ++ ++ return &((struct rsnd_mix *)(priv->mix) + id)->mod; ++} ++ ++static void rsnd_of_parse_mix(struct platform_device *pdev, ++ const struct rsnd_of_data *of_data, ++ struct rsnd_priv *priv) ++{ ++ struct device_node *node; ++ struct rsnd_mix_platform_info *mix_info; ++ struct rcar_snd_info *info = rsnd_priv_to_info(priv); ++ struct device *dev = &pdev->dev; ++ int nr; ++ ++ if (!of_data) ++ return; ++ ++ node = of_get_child_by_name(dev->of_node, "rcar_sound,mix"); ++ if (!node) ++ return; ++ ++ nr = of_get_child_count(node); ++ if (!nr) ++ goto rsnd_of_parse_mix_end; ++ ++ mix_info = devm_kzalloc(dev, ++ sizeof(struct rsnd_mix_platform_info) * nr, ++ GFP_KERNEL); ++ if (!mix_info) { ++ dev_err(dev, "mix info allocation error\n"); ++ goto rsnd_of_parse_mix_end; ++ } ++ ++ info->mix_info = mix_info; ++ info->mix_info_nr = nr; ++ ++rsnd_of_parse_mix_end: ++ of_node_put(node); ++ ++} ++ ++int rsnd_mix_probe(struct platform_device *pdev, ++ const struct rsnd_of_data *of_data, ++ struct rsnd_priv *priv) ++{ ++ struct rcar_snd_info *info = rsnd_priv_to_info(priv); ++ struct device *dev = rsnd_priv_to_dev(priv); ++ struct rsnd_mix *mix; ++ struct clk *clk; ++ char name[MIX_NAME_SIZE]; ++ int i, nr, ret; ++ ++ /* This driver doesn't support Gen1 at this point */ ++ if (rsnd_is_gen1(priv)) { ++ dev_warn(dev, "MIX is not supported on Gen1\n"); ++ return -EINVAL; ++ } ++ ++ rsnd_of_parse_mix(pdev, of_data, priv); ++ ++ nr = info->mix_info_nr; ++ if (!nr) ++ return 0; ++ ++ mix = devm_kzalloc(dev, sizeof(*mix) * nr, GFP_KERNEL); ++ if (!mix) ++ return -ENOMEM; ++ ++ priv->mix_nr = nr; ++ priv->mix = mix; ++ ++ for_each_rsnd_mix(mix, priv, i) { ++ snprintf(name, MIX_NAME_SIZE, "%s.%d", ++ MIX_NAME, i); ++ ++ clk = devm_clk_get(dev, name); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ mix->info = &info->mix_info[i]; ++ ++ ret = rsnd_mod_init(priv, &mix->mod, &rsnd_mix_ops, ++ clk, RSND_MOD_MIX, i); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++void rsnd_mix_remove(struct platform_device *pdev, ++ struct rsnd_priv *priv) ++{ ++ struct rsnd_mix *mix; ++ int i; ++ ++ for_each_rsnd_mix(mix, priv, i) { ++ rsnd_mod_quit(&mix->mod); ++ } ++} +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index f2128a7cf259..7a0e52b4640a 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -49,6 +49,16 @@ enum rsnd_reg { + RSND_REG_CMD_ROUTE_SLCT, + RSND_REG_CTU_CTUIR, + RSND_REG_CTU_ADINR, ++ RSND_REG_MIX_SWRSR, ++ RSND_REG_MIX_MIXIR, ++ RSND_REG_MIX_ADINR, ++ RSND_REG_MIX_MIXMR, ++ RSND_REG_MIX_MVPDR, ++ RSND_REG_MIX_MDBAR, ++ RSND_REG_MIX_MDBBR, ++ RSND_REG_MIX_MDBCR, ++ RSND_REG_MIX_MDBDR, ++ RSND_REG_MIX_MDBER, + RSND_REG_DVC_SWRSR, + RSND_REG_DVC_DVUIR, + RSND_REG_DVC_ADINR, +@@ -222,6 +232,7 @@ struct dma_chan *rsnd_dma_request_channel(struct device_node *of_node, + */ + enum rsnd_mod_type { + RSND_MOD_DVC = 0, ++ RSND_MOD_MIX, + RSND_MOD_CTU, + RSND_MOD_SRC, + RSND_MOD_SSI, +@@ -355,6 +366,7 @@ struct rsnd_dai_stream { + #define rsnd_io_to_mod_ssi(io) rsnd_io_to_mod((io), RSND_MOD_SSI) + #define rsnd_io_to_mod_src(io) rsnd_io_to_mod((io), RSND_MOD_SRC) + #define rsnd_io_to_mod_ctu(io) rsnd_io_to_mod((io), RSND_MOD_CTU) ++#define rsnd_io_to_mod_mix(io) rsnd_io_to_mod((io), RSND_MOD_MIX) + #define rsnd_io_to_mod_dvc(io) rsnd_io_to_mod((io), RSND_MOD_DVC) + #define rsnd_io_to_rdai(io) ((io)->rdai) + #define rsnd_io_to_priv(io) (rsnd_rdai_to_priv(rsnd_io_to_rdai(io))) +@@ -473,6 +485,12 @@ struct rsnd_priv { + int ctu_nr; + + /* ++ * below value will be filled on rsnd_mix_probe() ++ */ ++ void *mix; ++ int mix_nr; ++ ++ /* + * below value will be filled on rsnd_dvc_probe() + */ + void *dvc; +@@ -589,6 +607,17 @@ void rsnd_ctu_remove(struct platform_device *pdev, + struct rsnd_mod *rsnd_ctu_mod_get(struct rsnd_priv *priv, int id); + + /* ++ * R-Car MIX ++ */ ++int rsnd_mix_probe(struct platform_device *pdev, ++ const struct rsnd_of_data *of_data, ++ struct rsnd_priv *priv); ++ ++void rsnd_mix_remove(struct platform_device *pdev, ++ struct rsnd_priv *priv); ++struct rsnd_mod *rsnd_mix_mod_get(struct rsnd_priv *priv, int id); ++ ++/* + * R-Car DVC + */ + int rsnd_dvc_probe(struct platform_device *pdev, +-- +2.6.2 + diff --git a/patches.renesas/0307-ASoC-rsnd-tidyup-parameter-assignment-position.patch b/patches.renesas/0307-ASoC-rsnd-tidyup-parameter-assignment-position.patch new file mode 100644 index 00000000000000..19ad692365d2f6 --- /dev/null +++ b/patches.renesas/0307-ASoC-rsnd-tidyup-parameter-assignment-position.patch @@ -0,0 +1,44 @@ +From e9ce9c88e7154850b8b37cc8268c5f28e419aa3f Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 21 Jul 2015 00:03:35 +0000 +Subject: [PATCH 307/326] ASoC: rsnd: tidyup parameter assignment position + +84e95355602c("ASoC: rsnd: show debug message for SSI/SRC/DVC connection") +added debug message on rsnd_dai_connect(), but the relationship of +parameter check was absurdity. This patch tidyup it. +It is reported via Smatch/Dan + +Reported-by: Dan Carpenter <dan.carpenter@oracle.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 48725e9cc841da395bfd74e7691bba91613d3517) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index 927a7b02123b..f3feed5ce9b6 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -332,12 +332,15 @@ u32 rsnd_get_dalign(struct rsnd_mod *mod, struct rsnd_dai_stream *io) + static int rsnd_dai_connect(struct rsnd_mod *mod, + struct rsnd_dai_stream *io) + { +- struct rsnd_priv *priv = rsnd_mod_to_priv(mod); +- struct device *dev = rsnd_priv_to_dev(priv); ++ struct rsnd_priv *priv; ++ struct device *dev; + + if (!mod) + return -EIO; + ++ priv = rsnd_mod_to_priv(mod); ++ dev = rsnd_priv_to_dev(priv); ++ + io->mod[mod->type] = mod; + + dev_dbg(dev, "%s[%d] is connected to io (%s)\n", +-- +2.6.2 + diff --git a/patches.renesas/0308-ASoC-rcar-ctu-Staticise-local-symbols.patch b/patches.renesas/0308-ASoC-rcar-ctu-Staticise-local-symbols.patch new file mode 100644 index 00000000000000..3e6e6054ebfdf1 --- /dev/null +++ b/patches.renesas/0308-ASoC-rcar-ctu-Staticise-local-symbols.patch @@ -0,0 +1,36 @@ +From 3e353550ddf056f120fba29e81953635a9c5c84f Mon Sep 17 00:00:00 2001 +From: Lars-Peter Clausen <lars@metafoo.de> +Date: Mon, 27 Jul 2015 10:56:25 +0200 +Subject: [PATCH 308/326] ASoC: rcar ctu: Staticise local symbols + +rsnd_of_parse_ctu() is not used outside this file so it can be static. +Fixes the following sparse warning: + + sound/soc/sh/rcar/ctu.c:72:6: warning: symbol 'rsnd_of_parse_ctu' was + not declared. Should it be static? + +Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit e773c2f964640e103cc75a45aa4555c73ba55c29) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/ctu.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/sh/rcar/ctu.c b/sound/soc/sh/rcar/ctu.c +index 05edd2009b81..05498bba5874 100644 +--- a/sound/soc/sh/rcar/ctu.c ++++ b/sound/soc/sh/rcar/ctu.c +@@ -69,7 +69,7 @@ struct rsnd_mod *rsnd_ctu_mod_get(struct rsnd_priv *priv, int id) + return &((struct rsnd_ctu *)(priv->ctu) + id)->mod; + } + +-void rsnd_of_parse_ctu(struct platform_device *pdev, ++static void rsnd_of_parse_ctu(struct platform_device *pdev, + const struct rsnd_of_data *of_data, + struct rsnd_priv *priv) + { +-- +2.6.2 + diff --git a/patches.renesas/0309-ASoC-rsnd-Silence-DMA-slave-ID-compile-warning-on-64.patch b/patches.renesas/0309-ASoC-rsnd-Silence-DMA-slave-ID-compile-warning-on-64.patch new file mode 100644 index 00000000000000..c86a2504f203c7 --- /dev/null +++ b/patches.renesas/0309-ASoC-rsnd-Silence-DMA-slave-ID-compile-warning-on-64.patch @@ -0,0 +1,42 @@ +From d12dbf8129638d3f5426818403af3c6298a7872b Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 11 Aug 2015 14:47:18 +0200 +Subject: [PATCH 309/326] ASoC: rsnd: Silence DMA slave ID compile warning on + 64-bit + +On arm64: + + sound/soc/sh/rcar/dma.c: In function 'rsnd_dmaen_init': + sound/soc/sh/rcar/dma.c:180:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + (void *)id); + ^ + include/linux/dmaengine.h:1185:75: note: in definition of macro 'dma_request_channel' + #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) + ^ + +Add an intermediate cast to "uintptr_t" to kill the compile warning. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 1af2cc64b18c29f1d774caa7e592c781bee6a7eb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/dma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c +index 305b12929853..bfbb8a5e93bd 100644 +--- a/sound/soc/sh/rcar/dma.c ++++ b/sound/soc/sh/rcar/dma.c +@@ -177,7 +177,7 @@ static int rsnd_dmaen_init(struct rsnd_dai_stream *io, + dma_cap_set(DMA_SLAVE, mask); + + dmaen->chan = dma_request_channel(mask, shdma_chan_filter, +- (void *)id); ++ (void *)(uintptr_t)id); + } + if (IS_ERR_OR_NULL(dmaen->chan)) { + dmaen->chan = NULL; +-- +2.6.2 + diff --git a/patches.renesas/0310-irqchip-renesas-intc-irqpin-Use-a-separate-lockdep-c.patch b/patches.renesas/0310-irqchip-renesas-intc-irqpin-Use-a-separate-lockdep-c.patch new file mode 100644 index 00000000000000..8accfb6493e8e5 --- /dev/null +++ b/patches.renesas/0310-irqchip-renesas-intc-irqpin-Use-a-separate-lockdep-c.patch @@ -0,0 +1,101 @@ +From cda7c40ef23b4f86f4d0abb807344b22bdf9ca7e Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 9 Sep 2015 13:42:54 +0200 +Subject: [PATCH 310/326] irqchip/renesas-intc-irqpin: Use a separate lockdep + class + +The renesas-intc-irqpin interrupt controller is cascaded to the GIC. +Hence when propagating wake-up settings to its parent interrupt +controller, the following lockdep warning is printed: + + ============================================= + [ INFO: possible recursive locking detected ] + 4.2.0-armadillo-10725-g50fcd7643c034198 #781 Not tainted + --------------------------------------------- + s2ram/1179 is trying to acquire lock: + (&irq_desc_lock_class){-.-...}, at: [<c005bb54>] __irq_get_desc_lock+0x78/0x94 + + but task is already holding lock: + (&irq_desc_lock_class){-.-...}, at: [<c005bb54>] __irq_get_desc_lock+0x78/0x94 + + other info that might help us debug this: + Possible unsafe locking scenario: + + CPU0 + ---- + lock(&irq_desc_lock_class); + lock(&irq_desc_lock_class); + + *** DEADLOCK *** + + May be due to missing lock nesting notation + + 7 locks held by s2ram/1179: + #0: (sb_writers#7){.+.+.+}, at: [<c00c9708>] __sb_start_write+0x64/0xb8 + #1: (&of->mutex){+.+.+.}, at: [<c0125a00>] kernfs_fop_write+0x78/0x1a0 + #2: (s_active#23){.+.+.+}, at: [<c0125a08>] kernfs_fop_write+0x80/0x1a0 + #3: (autosleep_lock){+.+.+.}, at: [<c0058244>] pm_autosleep_lock+0x18/0x20 + #4: (pm_mutex){+.+.+.}, at: [<c0057e50>] pm_suspend+0x54/0x248 + #5: (&dev->mutex){......}, at: [<c0243a20>] __device_suspend+0xdc/0x240 + #6: (&irq_desc_lock_class){-.-...}, at: [<c005bb54>] __irq_get_desc_lock+0x78/0x94 + + stack backtrace: + CPU: 0 PID: 1179 Comm: s2ram Not tainted 4.2.0-armadillo-10725-g50fcd7643c034198 + + Hardware name: Generic R8A7740 (Flattened Device Tree) + [<c00129f4>] (dump_backtrace) from [<c0012bec>] (show_stack+0x18/0x1c) + [<c0012bd4>] (show_stack) from [<c03f5d94>] (dump_stack+0x20/0x28) + [<c03f5d74>] (dump_stack) from [<c00514d4>] (__lock_acquire+0x67c/0x1b88) + [<c0050e58>] (__lock_acquire) from [<c0052df8>] (lock_acquire+0x9c/0xbc) + [<c0052d5c>] (lock_acquire) from [<c03fb068>] (_raw_spin_lock_irqsave+0x44/0x58) + [<c03fb024>] (_raw_spin_lock_irqsave) from [<c005bb54>] (__irq_get_desc_lock+0x78/0x94 + [<c005badc>] (__irq_get_desc_lock) from [<c005c3d8>] (irq_set_irq_wake+0x28/0x100) + [<c005c3b0>] (irq_set_irq_wake) from [<c01e50d0>] (intc_irqpin_irq_set_wake+0x24/0x4c) + [<c01e50ac>] (intc_irqpin_irq_set_wake) from [<c005c17c>] (set_irq_wake_real+0x3c/0x50 + [<c005c140>] (set_irq_wake_real) from [<c005c414>] (irq_set_irq_wake+0x64/0x100) + [<c005c3b0>] (irq_set_irq_wake) from [<c02a19b4>] (gpio_keys_suspend+0x60/0xa0) + [<c02a1954>] (gpio_keys_suspend) from [<c023b750>] (platform_pm_suspend+0x3c/0x5c) + +Avoid this false positive by using a separate lockdep class for INTC +External IRQ Pin interrupts. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Cc: Grygorii Strashko <grygorii.strashko@ti.com> +Cc: Magnus Damm <magnus.damm@gmail.com> +Cc: Jason Cooper <jason@lakedaemon.net> +Link: http://lkml.kernel.org/r/1441798974-25716-3-git-send-email-geert%2Brenesas@glider.be +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +(cherry picked from commit 769b5cf78e6c653c2f513649ee6c4e7a06723872) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/irqchip/irq-renesas-intc-irqpin.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c +index 0670ab4e3897..67797eebbd5e 100644 +--- a/drivers/irqchip/irq-renesas-intc-irqpin.c ++++ b/drivers/irqchip/irq-renesas-intc-irqpin.c +@@ -332,6 +332,12 @@ static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id) + return status; + } + ++/* ++ * This lock class tells lockdep that INTC External IRQ Pin irqs are in a ++ * different category than their parents, so it won't report false recursion. ++ */ ++static struct lock_class_key intc_irqpin_irq_lock_class; ++ + static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) + { +@@ -342,6 +348,7 @@ static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, + + intc_irqpin_dbg(&p->irq[hw], "map"); + irq_set_chip_data(virq, h->host_data); ++ irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class); + irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); + set_irq_flags(virq, IRQF_VALID); /* kill me now */ + return 0; +-- +2.6.2 + diff --git a/patches.renesas/0311-irqchip-renesas-intc-irqpin-Propagate-wake-up-settin.patch b/patches.renesas/0311-irqchip-renesas-intc-irqpin-Propagate-wake-up-settin.patch new file mode 100644 index 00000000000000..0f6c5cbcebe6ee --- /dev/null +++ b/patches.renesas/0311-irqchip-renesas-intc-irqpin-Propagate-wake-up-settin.patch @@ -0,0 +1,51 @@ +From b456c0fc8d6e0aa4d1fdddbefc83b240074b5c42 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 8 Sep 2015 19:00:35 +0200 +Subject: [PATCH 311/326] irqchip/renesas-intc-irqpin: Propagate wake-up + settings to parent + +The renesas-intc-irqpin interrupt controller is cascaded to the GIC, but +its driver doesn't propagate wake-up settings to the parent interrupt +controller. + +Since commit aec89ef72ba6c944 ("irqchip/gic: Enable SKIP_SET_WAKE and +MASK_ON_SUSPEND"), the GIC driver masks interrupts during suspend, and +wake-up through gpio-keys now fails on r8a7740/armadillo and +sh73a0/kzm9g. + +Fix this by propagating wake-up settings to the parent interrupt +controller. There's no need to handle irq_set_irq_wake() failures, as +the renesas-intc-irqpin interrupt controller is always cascaded to a +GIC, and the GIC driver always sets SKIP_SET_WAKE since the +aforementioned commit. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Cc: Sudeep Holla <sudeep.holla@arm.com> +Cc: Magnus Damm <magnus.damm@gmail.com> +Cc: Jason Cooper <jason@lakedaemon.net> +Cc: Marc Zyngier <marc.zyngier@arm.com> +Link: http://lkml.kernel.org/r/1441731636-17610-2-git-send-email-geert%2Brenesas@glider.be +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +(cherry picked from commit f4e209cdc7a00f934007f40cf885471799073b0d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/irqchip/irq-renesas-intc-irqpin.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c +index 67797eebbd5e..d3546a6f4978 100644 +--- a/drivers/irqchip/irq-renesas-intc-irqpin.c ++++ b/drivers/irqchip/irq-renesas-intc-irqpin.c +@@ -283,6 +283,9 @@ static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type) + static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on) + { + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); ++ int hw_irq = irqd_to_hwirq(d); ++ ++ irq_set_irq_wake(p->irq[hw_irq].requested_irq, on); + + if (!p->clk) + return 0; +-- +2.6.2 + diff --git a/patches.renesas/0312-irqchip-renesas-irqc-Use-a-separate-lockdep-class.patch b/patches.renesas/0312-irqchip-renesas-irqc-Use-a-separate-lockdep-class.patch new file mode 100644 index 00000000000000..09bea28fb81c0f --- /dev/null +++ b/patches.renesas/0312-irqchip-renesas-irqc-Use-a-separate-lockdep-class.patch @@ -0,0 +1,97 @@ +From b861d48955a0aaf81f0a20e750c1c9c1bb414adb Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 9 Sep 2015 13:42:53 +0200 +Subject: [PATCH 312/326] irqchip/renesas-irqc: Use a separate lockdep class + +The renesas-irqc interrupt controller is cascaded to the GIC. Hence when +propagating wake-up settings to its parent interrupt controller, the +following lockdep warning is printed: + + ============================================= + [ INFO: possible recursive locking detected ] + 4.2.0-ape6evm-10725-g50fcd7643c034198 #280 Not tainted + --------------------------------------------- + s2ram/1072 is trying to acquire lock: + (&irq_desc_lock_class){-.-...}, at: [<c008d3fc>] __irq_get_desc_lock+0x58/0x98 + + but task is already holding lock: + (&irq_desc_lock_class){-.-...}, at: [<c008d3fc>] __irq_get_desc_lock+0x58/0x98 + + other info that might help us debug this: + Possible unsafe locking scenario: + + CPU0 + ---- + lock(&irq_desc_lock_class); + lock(&irq_desc_lock_class); + + *** DEADLOCK *** + + May be due to missing lock nesting notation + + 6 locks held by s2ram/1072: + #0: (sb_writers#7){.+.+.+}, at: [<c012eb14>] __sb_start_write+0xa0/0xa8 + #1: (&of->mutex){+.+.+.}, at: [<c019396c>] kernfs_fop_write+0x4c/0x1bc + #2: (s_active#24){.+.+.+}, at: [<c0193974>] kernfs_fop_write+0x54/0x1bc + #3: (pm_mutex){+.+.+.}, at: [<c008213c>] pm_suspend+0x10c/0x510 + #4: (&dev->mutex){......}, at: [<c02af3c4>] __device_suspend+0xdc/0x2cc + #5: (&irq_desc_lock_class){-.-...}, at: [<c008d3fc>] __irq_get_desc_lock+0x58/0x98 + + stack backtrace: + CPU: 0 PID: 1072 Comm: s2ram Not tainted 4.2.0-ape6evm-10725-g50fcd7643c034198 #280 + Hardware name: Generic R8A73A4 (Flattened Device Tree) + [<c0018078>] (unwind_backtrace) from [<c00144f0>] (show_stack+0x10/0x14) + [<c00144f0>] (show_stack) from [<c0451f14>] (dump_stack+0x88/0x98) + [<c0451f14>] (dump_stack) from [<c007b29c>] (__lock_acquire+0x15cc/0x20e4) + [<c007b29c>] (__lock_acquire) from [<c007c6e0>] (lock_acquire+0xac/0x12c) + [<c007c6e0>] (lock_acquire) from [<c0457c00>] (_raw_spin_lock_irqsave+0x40/0x54) + [<c0457c00>] (_raw_spin_lock_irqsave) from [<c008d3fc>] (__irq_get_desc_lock+0x58/0x98) + [<c008d3fc>] (__irq_get_desc_lock) from [<c008ebbc>] (irq_set_irq_wake+0x20/0xf8) + [<c008ebbc>] (irq_set_irq_wake) from [<c0260770>] (irqc_irq_set_wake+0x20/0x4c) + [<c0260770>] (irqc_irq_set_wake) from [<c008ec28>] (irq_set_irq_wake+0x8c/0xf8) + [<c008ec28>] (irq_set_irq_wake) from [<c02cb8c0>] (gpio_keys_suspend+0x74/0xc0) + [<c02cb8c0>] (gpio_keys_suspend) from [<c02ae8cc>] (dpm_run_callback+0x54/0x124) + +Avoid this false positive by using a separate lockdep class for IRQC +interrupts. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Cc: Grygorii Strashko <grygorii.strashko@ti.com> +Cc: Magnus Damm <magnus.damm@gmail.com> +Cc: Jason Cooper <jason@lakedaemon.net> +Link: http://lkml.kernel.org/r/1441798974-25716-2-git-send-email-geert%2Brenesas@glider.be +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +(cherry picked from commit b1370658804510f6a1c0517a8ff1c9534d371edd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/irqchip/irq-renesas-irqc.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c +index 2aa3add711a6..4652cc385d39 100644 +--- a/drivers/irqchip/irq-renesas-irqc.c ++++ b/drivers/irqchip/irq-renesas-irqc.c +@@ -150,6 +150,12 @@ static irqreturn_t irqc_irq_handler(int irq, void *dev_id) + return IRQ_NONE; + } + ++/* ++ * This lock class tells lockdep that IRQC irqs are in a different ++ * category than their parents, so it won't report false recursion. ++ */ ++static struct lock_class_key irqc_irq_lock_class; ++ + static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) + { +@@ -157,6 +163,7 @@ static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq, + + irqc_dbg(&p->irq[hw], "map"); + irq_set_chip_data(virq, h->host_data); ++ irq_set_lockdep_class(virq, &irqc_irq_lock_class); + irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); + return 0; + } +-- +2.6.2 + diff --git a/patches.renesas/0313-irqchip-renesas-irqc-Propagate-wake-up-settings-to-p.patch b/patches.renesas/0313-irqchip-renesas-irqc-Propagate-wake-up-settings-to-p.patch new file mode 100644 index 00000000000000..d2b0e95cf79c1b --- /dev/null +++ b/patches.renesas/0313-irqchip-renesas-irqc-Propagate-wake-up-settings-to-p.patch @@ -0,0 +1,50 @@ +From e2a4578679bd975f2f010f3eb5f1f8cd99026825 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 8 Sep 2015 19:00:36 +0200 +Subject: [PATCH 313/326] irqchip/renesas-irqc: Propagate wake-up settings to + parent + +The renesas-irqc interrupt controller is cascaded to the GIC, but its +driver doesn't propagate wake-up settings to the parent interrupt +controller. + +Since commit aec89ef72ba6c944 ("irqchip/gic: Enable SKIP_SET_WAKE and +MASK_ON_SUSPEND"), the GIC driver masks interrupts during suspend, and +wake-up through gpio-keys now fails on r8a73a4/ape6evm. + +Fix this by propagating wake-up settings to the parent interrupt +controller. There's no need to handle irq_set_irq_wake() failures, as +the renesas-irqc interrupt controller is always cascaded to a GIC, and +the GIC driver always sets SKIP_SET_WAKE since the aforementioned +commit. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Cc: Sudeep Holla <sudeep.holla@arm.com> +Cc: Magnus Damm <magnus.damm@gmail.com> +Cc: Jason Cooper <jason@lakedaemon.net> +Cc: Marc Zyngier <marc.zyngier@arm.com> +Link: http://lkml.kernel.org/r/1441731636-17610-3-git-send-email-geert%2Brenesas@glider.be +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +(cherry picked from commit 4cd7863ecb90010533c178fba6ecc84d5529b402) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/irqchip/irq-renesas-irqc.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c +index 4652cc385d39..35bf97ba4a3d 100644 +--- a/drivers/irqchip/irq-renesas-irqc.c ++++ b/drivers/irqchip/irq-renesas-irqc.c +@@ -121,6 +121,9 @@ static int irqc_irq_set_type(struct irq_data *d, unsigned int type) + static int irqc_irq_set_wake(struct irq_data *d, unsigned int on) + { + struct irqc_priv *p = irq_data_get_irq_chip_data(d); ++ int hw_irq = irqd_to_hwirq(d); ++ ++ irq_set_irq_wake(p->irq[hw_irq].requested_irq, on); + + if (!p->clk) + return 0; +-- +2.6.2 + diff --git a/patches.renesas/0314-pinctrl-join-lines-that-can-be-a-single-line-within-.patch b/patches.renesas/0314-pinctrl-join-lines-that-can-be-a-single-line-within-.patch new file mode 100644 index 00000000000000..265a9721aeab52 --- /dev/null +++ b/patches.renesas/0314-pinctrl-join-lines-that-can-be-a-single-line-within-.patch @@ -0,0 +1,33 @@ +From cb9fdeee0ddeba1195c20a17679a1f4b30258d89 Mon Sep 17 00:00:00 2001 +From: Masahiro Yamada <yamada.masahiro@socionext.com> +Date: Sat, 1 Aug 2015 13:22:38 +0900 +Subject: [PATCH 314/326] pinctrl: join lines that can be a single line within + 80 columns + +There is no reason to break a line shorter than 80 columns. + +Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 163dc9f39a26b41fc49319fce4145b35f9705789) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/pinmux.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c +index 67e08cb315c4..29984b36926a 100644 +--- a/drivers/pinctrl/pinmux.c ++++ b/drivers/pinctrl/pinmux.c +@@ -313,8 +313,7 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev, + + /* See if this pctldev has this function */ + while (selector < nfuncs) { +- const char *fname = ops->get_function_name(pctldev, +- selector); ++ const char *fname = ops->get_function_name(pctldev, selector); + + if (!strcmp(function, fname)) + return selector; +-- +2.6.2 + diff --git a/patches.renesas/0315-pinctrl-core-Warn-about-NULL-gpio_chip-in-pinctrl_re.patch b/patches.renesas/0315-pinctrl-core-Warn-about-NULL-gpio_chip-in-pinctrl_re.patch new file mode 100644 index 00000000000000..be28a1e1bb9e2b --- /dev/null +++ b/patches.renesas/0315-pinctrl-core-Warn-about-NULL-gpio_chip-in-pinctrl_re.patch @@ -0,0 +1,36 @@ +From 47ff9e7421632c0dbcf57caecd96f81aa4d1de6e Mon Sep 17 00:00:00 2001 +From: Tony Lindgren <tony@atomide.com> +Date: Thu, 3 Sep 2015 10:34:30 -0700 +Subject: [PATCH 315/326] pinctrl: core: Warn about NULL gpio_chip in + pinctrl_ready_for_gpio_range() + +If the gpio driver is confused about the numbers for gpio-ranges, +pinctrl_ready_for_gpio_range() may get called with invalid GPIO +causing a NULL pointer exception. Let's instead provide a warning +that allows fixing the problem and return with error. + +Signed-off-by: Tony Lindgren <tony@atomide.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 942cde724075f840ded89390b10dce1a47a4d712) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/core.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c +index 69723e07036b..9638a00c67c2 100644 +--- a/drivers/pinctrl/core.c ++++ b/drivers/pinctrl/core.c +@@ -349,6 +349,9 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio) + struct pinctrl_gpio_range *range = NULL; + struct gpio_chip *chip = gpio_to_chip(gpio); + ++ if (WARN(!chip, "no gpio_chip for gpio%i?", gpio)) ++ return false; ++ + mutex_lock(&pinctrldev_list_mutex); + + /* Loop over the pin controllers */ +-- +2.6.2 + diff --git a/patches.renesas/0316-PCI-rcar-Add-R8A7794-support.patch b/patches.renesas/0316-PCI-rcar-Add-R8A7794-support.patch new file mode 100644 index 00000000000000..0c3fa97f421d35 --- /dev/null +++ b/patches.renesas/0316-PCI-rcar-Add-R8A7794-support.patch @@ -0,0 +1,46 @@ +From 3da2201e3f77db03f49d3f6b132265100ec8d3e0 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sat, 12 Sep 2015 02:06:09 +0300 +Subject: [PATCH 316/326] PCI: rcar: Add R8A7794 support + +Add Renesas R8A7794 SoC support to the Renesas R-Car gen2 PCI driver. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Bjorn Helgaas <helgaas@kernel.org> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit de24c18c0faca5ebd618e1cb87f5489745e40475) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt | 3 ++- + drivers/pci/host/pci-rcar-gen2.c | 1 + + 2 files changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt +index d8ef5bf50f11..7fab84b33531 100644 +--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt ++++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt +@@ -7,7 +7,8 @@ OHCI and EHCI controllers. + + Required properties: + - compatible: "renesas,pci-r8a7790" for the R8A7790 SoC; +- "renesas,pci-r8a7791" for the R8A7791 SoC. ++ "renesas,pci-r8a7791" for the R8A7791 SoC; ++ "renesas,pci-r8a7794" for the R8A7794 SoC. + - reg: A list of physical regions to access the device: the first is + the operational registers for the OHCI/EHCI controllers and the + second is for the bridge configuration and control registers. +diff --git a/drivers/pci/host/pci-rcar-gen2.c b/drivers/pci/host/pci-rcar-gen2.c +index 367e28fa7564..c4f64bfee551 100644 +--- a/drivers/pci/host/pci-rcar-gen2.c ++++ b/drivers/pci/host/pci-rcar-gen2.c +@@ -362,6 +362,7 @@ static int rcar_pci_probe(struct platform_device *pdev) + static struct of_device_id rcar_pci_of_match[] = { + { .compatible = "renesas,pci-r8a7790", }, + { .compatible = "renesas,pci-r8a7791", }, ++ { .compatible = "renesas,pci-r8a7794", }, + { }, + }; + +-- +2.6.2 + diff --git a/patches.renesas/0317-drivers-sh-Disable-legacy-default-PM-Domain-on-emev2.patch b/patches.renesas/0317-drivers-sh-Disable-legacy-default-PM-Domain-on-emev2.patch new file mode 100644 index 00000000000000..bfeabee7f75def --- /dev/null +++ b/patches.renesas/0317-drivers-sh-Disable-legacy-default-PM-Domain-on-emev2.patch @@ -0,0 +1,36 @@ +From b06dbb5126c9dc4317fc1dae1924513618559705 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:14 +0200 +Subject: [PATCH 317/326] drivers: sh: Disable legacy default PM Domain on + emev2 + +EMMA Mobile EV2 doesn't have MSTP clocks. All its device drivers manage +clocks explicitly, without relying on Runtime PM, so it doesn't need the +legacy default PM Domain. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9b302c1acf4114d51b7f0962df0b0ddee0dc75cd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/sh/pm_runtime.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c +index fe8875f0d7be..c1e7f26c143f 100644 +--- a/drivers/sh/pm_runtime.c ++++ b/drivers/sh/pm_runtime.c +@@ -78,8 +78,7 @@ static struct pm_clk_notifier_block platform_bus_notifier = { + static int __init sh_pm_runtime_init(void) + { + if (IS_ENABLED(CONFIG_ARCH_SHMOBILE_MULTI)) { +- if (!of_machine_is_compatible("renesas,emev2") && +- !of_machine_is_compatible("renesas,r7s72100") && ++ if (!of_machine_is_compatible("renesas,r7s72100") && + #ifndef CONFIG_PM_GENERIC_DOMAINS_OF + !of_machine_is_compatible("renesas,r8a73a4") && + !of_machine_is_compatible("renesas,r8a7740") && +-- +2.6.2 + diff --git a/patches.renesas/0318-drivers-sh-Disable-PM-runtime-for-multi-platform-ARM.patch b/patches.renesas/0318-drivers-sh-Disable-PM-runtime-for-multi-platform-ARM.patch new file mode 100644 index 00000000000000..62517460d3d705 --- /dev/null +++ b/patches.renesas/0318-drivers-sh-Disable-PM-runtime-for-multi-platform-ARM.patch @@ -0,0 +1,70 @@ +From 7afde3c3cc889fed813fd62159eae19078b799d9 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 4 Aug 2015 14:28:15 +0200 +Subject: [PATCH 318/326] drivers: sh: Disable PM runtime for multi-platform + ARM with genpd + +If the default PM Domain using PM_CLK is used for PM runtime, the real +Clock Domain cannot be registered from DT later. + +Hence do not enable it when running a multi-platform kernel with genpd +support on R-Car or RZ. The CPG/MSTP Clock Domain driver will take care +of PM runtime management of the module clocks. + +Now most multi-platform ARM shmobile platforms (SH-Mobile, R-Mobile, +R-Car, RZ) use DT-based PM Domains to take care of PM runtime management +of the module clocks, simplify the platform logic by replacing the +explicit SoC checks by a single check for the presence of MSTP clocks in +DT. + +Backwards-compatiblity with old DTs (mainly for R-Car Gen2) is provided +by checking for the presence of a "#power-domain-cells" property in DT. + +The default PM Domain is still needed for: + - backwards-compatibility with old DTs that lack PM Domain properties, + - the CONFIG_PM=n case, + - legacy (non-DT) ARM/shmobile platforms without genpd support + (r8a7778, r8a7779), + - legacy SuperH. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cbc41d0a761bffb3166a413a3c77100a737c0cd7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/sh/pm_runtime.c | 18 +++++------------- + 1 file changed, 5 insertions(+), 13 deletions(-) + +diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c +index c1e7f26c143f..4612b73ba321 100644 +--- a/drivers/sh/pm_runtime.c ++++ b/drivers/sh/pm_runtime.c +@@ -78,19 +78,11 @@ static struct pm_clk_notifier_block platform_bus_notifier = { + static int __init sh_pm_runtime_init(void) + { + if (IS_ENABLED(CONFIG_ARCH_SHMOBILE_MULTI)) { +- if (!of_machine_is_compatible("renesas,r7s72100") && +-#ifndef CONFIG_PM_GENERIC_DOMAINS_OF +- !of_machine_is_compatible("renesas,r8a73a4") && +- !of_machine_is_compatible("renesas,r8a7740") && +- !of_machine_is_compatible("renesas,sh73a0") && +-#endif +- !of_machine_is_compatible("renesas,r8a7778") && +- !of_machine_is_compatible("renesas,r8a7779") && +- !of_machine_is_compatible("renesas,r8a7790") && +- !of_machine_is_compatible("renesas,r8a7791") && +- !of_machine_is_compatible("renesas,r8a7792") && +- !of_machine_is_compatible("renesas,r8a7793") && +- !of_machine_is_compatible("renesas,r8a7794")) ++ if (!of_find_compatible_node(NULL, NULL, ++ "renesas,cpg-mstp-clocks")) ++ return 0; ++ if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS_OF) && ++ of_find_node_with_property(NULL, "#power-domain-cells")) + return 0; + } + +-- +2.6.2 + diff --git a/patches.renesas/0319-ARM-shmobile-r8a7790-dtsi-Add-CPG-MSTP-Clock-Domain-.patch b/patches.renesas/0319-ARM-shmobile-r8a7790-dtsi-Add-CPG-MSTP-Clock-Domain-.patch new file mode 100644 index 00000000000000..eeb656ecad23ea --- /dev/null +++ b/patches.renesas/0319-ARM-shmobile-r8a7790-dtsi-Add-CPG-MSTP-Clock-Domain-.patch @@ -0,0 +1,36 @@ +From d9033ddef1ceec512f60c64e74044be59b9bb117 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 20 Aug 2015 01:24:44 +0000 +Subject: [PATCH 319/326] ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock + Domain for sound + +484adb005886 ("ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain") +added CPG/MSTP clock-cells domain support, but it was missing sound +support. This patch adds it. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +[horms: Updated commit id referred to in changelog] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 6507c4efd2ca4a3dccedbc5b4724f9faabf97fca) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index a0b2a79cbfbd..4624d0f2a754 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -1627,6 +1627,7 @@ + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; ++ power-domains = <&cpg_clocks>; + + status = "disabled"; + +-- +2.6.2 + diff --git a/patches.renesas/0320-ARM-shmobile-r8a7791-dtsi-Add-CPG-MSTP-Clock-Domain-.patch b/patches.renesas/0320-ARM-shmobile-r8a7791-dtsi-Add-CPG-MSTP-Clock-Domain-.patch new file mode 100644 index 00000000000000..1e6564b5352807 --- /dev/null +++ b/patches.renesas/0320-ARM-shmobile-r8a7791-dtsi-Add-CPG-MSTP-Clock-Domain-.patch @@ -0,0 +1,36 @@ +From cf1db7fc10c892fffa517dee9f4c4e7f26eaacb1 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 20 Aug 2015 01:25:20 +0000 +Subject: [PATCH 320/326] ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock + Domain for sound + +797a0626e08c ("ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain") +added CPG/MSTP clock-cells domain support, but it was missing sound +support. This patch adds it. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +[horms: updated commit id referred to in changelog] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 56e86dd4bbeb66a7ad67e20fa045c6f51b4da571) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi +index 831525dd39a6..1666c8a6b143 100644 +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -1677,6 +1677,7 @@ + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; ++ power-domains = <&cpg_clocks>; + + status = "disabled"; + +-- +2.6.2 + diff --git a/patches.renesas/0321-spi-sh-msiof-Match-renesas-rx-fifo-size-in-DT-bindin.patch b/patches.renesas/0321-spi-sh-msiof-Match-renesas-rx-fifo-size-in-DT-bindin.patch new file mode 100644 index 00000000000000..4b120127608140 --- /dev/null +++ b/patches.renesas/0321-spi-sh-msiof-Match-renesas-rx-fifo-size-in-DT-bindin.patch @@ -0,0 +1,34 @@ +From ea4f9cecacff1adb8f3ee0c85f2cdcc6ef5579d6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 28 Sep 2015 15:28:03 +0200 +Subject: [PATCH 321/326] spi: sh-msiof: Match renesas,rx-fifo-size in DT + bindings doc with driver + +Commit fe78d0b7691c0274 ("spi: sh-msiof: Fix FIFO size to 64 word from +256 word") changed the default RX FIFO size on R-Car Gen2 SoCs in the +driver code, but forgot to update the DT bindings documentation. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit eb8d0ac4afd8b15ac88f8a50342b32774ff881ed) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/spi/sh-msiof.txt | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt +index 8f771441be60..705075da2f10 100644 +--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt ++++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt +@@ -51,7 +51,7 @@ Optional properties, deprecated for soctype-specific bindings: + - renesas,tx-fifo-size : Overrides the default tx fifo size given in words + (default is 64) + - renesas,rx-fifo-size : Overrides the default rx fifo size given in words +- (default is 64, or 256 on R-Car Gen2) ++ (default is 64) + + Pinctrl properties might be needed, too. See + Documentation/devicetree/bindings/pinctrl/renesas,*. +-- +2.6.2 + diff --git a/patches.renesas/0322-usb-renesas_usbhs-Change-USBHS_TYPE_R8A779x-to-USBHS.patch b/patches.renesas/0322-usb-renesas_usbhs-Change-USBHS_TYPE_R8A779x-to-USBHS.patch new file mode 100644 index 00000000000000..75d1d72d1caf90 --- /dev/null +++ b/patches.renesas/0322-usb-renesas_usbhs-Change-USBHS_TYPE_R8A779x-to-USBHS.patch @@ -0,0 +1,80 @@ +From ded3e9a9ab6dfd1f41079ba20955bcbc2f84f3a7 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Mon, 18 May 2015 20:04:14 +0900 +Subject: [PATCH 322/326] usb: renesas_usbhs: Change USBHS_TYPE_R8A779x to + USBHS_TYPE_RCAR_GEN2 + +Since the HSUSB controllers of R-Car Gen2 are the same specification +(they have 16 pipes and usb-dmac), this patch changes USBHS_TYPE_R8A7790 +and USBHS_TYPE_R8A7791 to USBHS_TYPE_RCAR_GEN2. + +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Felipe Balbi <balbi@ti.com> +(cherry picked from commit e0213bc5467ca5fe44ab04527f0e47998f30c046) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/renesas_usbhs/common.c | 15 ++++----------- + include/linux/usb/renesas_usbhs.h | 3 +-- + 2 files changed, 5 insertions(+), 13 deletions(-) + +diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c +index da321f034e3c..8442805b3753 100644 +--- a/drivers/usb/renesas_usbhs/common.c ++++ b/drivers/usb/renesas_usbhs/common.c +@@ -466,11 +466,11 @@ static int usbhsc_drvcllbck_notify_hotplug(struct platform_device *pdev) + static const struct of_device_id usbhs_of_match[] = { + { + .compatible = "renesas,usbhs-r8a7790", +- .data = (void *)USBHS_TYPE_R8A7790, ++ .data = (void *)USBHS_TYPE_RCAR_GEN2, + }, + { + .compatible = "renesas,usbhs-r8a7791", +- .data = (void *)USBHS_TYPE_R8A7791, ++ .data = (void *)USBHS_TYPE_RCAR_GEN2, + }, + { }, + }; +@@ -497,14 +497,8 @@ static struct renesas_usbhs_platform_info *usbhs_parse_dt(struct device *dev) + if (gpio > 0) + dparam->enable_gpio = gpio; + +- switch (dparam->type) { +- case USBHS_TYPE_R8A7790: +- case USBHS_TYPE_R8A7791: ++ if (dparam->type == USBHS_TYPE_RCAR_GEN2) + dparam->has_usb_dmac = 1; +- break; +- default: +- break; +- } + + return info; + } +@@ -559,8 +553,7 @@ static int usbhs_probe(struct platform_device *pdev) + sizeof(struct renesas_usbhs_driver_param)); + + switch (priv->dparam.type) { +- case USBHS_TYPE_R8A7790: +- case USBHS_TYPE_R8A7791: ++ case USBHS_TYPE_RCAR_GEN2: + priv->pfunc = usbhs_rcar2_ops; + if (!priv->dparam.pipe_type) { + priv->dparam.pipe_type = usbhsc_new_pipe_type; +diff --git a/include/linux/usb/renesas_usbhs.h b/include/linux/usb/renesas_usbhs.h +index f06529c14141..3dd5a781da99 100644 +--- a/include/linux/usb/renesas_usbhs.h ++++ b/include/linux/usb/renesas_usbhs.h +@@ -169,8 +169,7 @@ struct renesas_usbhs_driver_param { + #define USBHS_USB_DMAC_XFER_SIZE 32 /* hardcode the xfer size */ + }; + +-#define USBHS_TYPE_R8A7790 1 +-#define USBHS_TYPE_R8A7791 2 ++#define USBHS_TYPE_RCAR_GEN2 1 + + /* + * option: +-- +2.6.2 + diff --git a/patches.renesas/0323-usb-renesas_usbhs-Add-support-for-R-Car-E2.patch b/patches.renesas/0323-usb-renesas_usbhs-Add-support-for-R-Car-E2.patch new file mode 100644 index 00000000000000..81ebedb6dd453c --- /dev/null +++ b/patches.renesas/0323-usb-renesas_usbhs-Add-support-for-R-Car-E2.patch @@ -0,0 +1,47 @@ +From 6c53f7bb78f7ad02a0ee42a62d895de89b2fea28 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Mon, 18 May 2015 20:04:15 +0900 +Subject: [PATCH 323/326] usb: renesas_usbhs: Add support for R-Car E2 + +This patch adds a compatible string to support for R-Car E2. + +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>" in patch 2 +Signed-off-by: Felipe Balbi <balbi@ti.com> +(cherry picked from commit af6e613bb1b60fcbfe48c893b76c104c8952b599) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 1 + + drivers/usb/renesas_usbhs/common.c | 4 ++++ + 2 files changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt +index ddbe304beb21..64a4ca6cf96f 100644 +--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt ++++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt +@@ -4,6 +4,7 @@ Required properties: + - compatible: Must contain one of the following: + - "renesas,usbhs-r8a7790" + - "renesas,usbhs-r8a7791" ++ - "renesas,usbhs-r8a7794" + - reg: Base address and length of the register for the USBHS + - interrupts: Interrupt specifier for the USBHS + - clocks: A list of phandle + clock specifier pairs +diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c +index 8442805b3753..7b98e1d9194c 100644 +--- a/drivers/usb/renesas_usbhs/common.c ++++ b/drivers/usb/renesas_usbhs/common.c +@@ -472,6 +472,10 @@ static const struct of_device_id usbhs_of_match[] = { + .compatible = "renesas,usbhs-r8a7791", + .data = (void *)USBHS_TYPE_RCAR_GEN2, + }, ++ { ++ .compatible = "renesas,usbhs-r8a7794", ++ .data = (void *)USBHS_TYPE_RCAR_GEN2, ++ }, + { }, + }; + MODULE_DEVICE_TABLE(of, usbhs_of_match); +-- +2.6.2 + diff --git a/patches.renesas/0324-usb-renesas_usbhs-fix-build-warning-if-64-bit-archit.patch b/patches.renesas/0324-usb-renesas_usbhs-fix-build-warning-if-64-bit-archit.patch new file mode 100644 index 00000000000000..f8b7b34d360440 --- /dev/null +++ b/patches.renesas/0324-usb-renesas_usbhs-fix-build-warning-if-64-bit-archit.patch @@ -0,0 +1,50 @@ +From 77d3b0683e752579dabc75fc243bc6ab85d8c0a0 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Tue, 29 Sep 2015 18:21:18 +0900 +Subject: [PATCH 324/326] usb: renesas_usbhs: fix build warning if 64-bit + architecture + +This patch fixes the following warning if 64-bit architecture environment: + +./drivers/usb/renesas_usbhs/common.c:496:25: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + dparam->type = of_id ? (u32)of_id->data : 0; + +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Felipe Balbi <balbi@ti.com> +(cherry picked from commit 9ae7ce00cc1353155b1914bfc40e8362efef7d1c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/renesas_usbhs/common.c | 2 +- + include/linux/usb/renesas_usbhs.h | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c +index 7b98e1d9194c..0ce398c5482e 100644 +--- a/drivers/usb/renesas_usbhs/common.c ++++ b/drivers/usb/renesas_usbhs/common.c +@@ -493,7 +493,7 @@ static struct renesas_usbhs_platform_info *usbhs_parse_dt(struct device *dev) + return NULL; + + dparam = &info->driver_param; +- dparam->type = of_id ? (u32)of_id->data : 0; ++ dparam->type = of_id ? (uintptr_t)of_id->data : 0; + if (!of_property_read_u32(dev->of_node, "renesas,buswait", &tmp)) + dparam->buswait_bwait = tmp; + gpio = of_get_named_gpio_flags(dev->of_node, "renesas,enable-gpio", 0, +diff --git a/include/linux/usb/renesas_usbhs.h b/include/linux/usb/renesas_usbhs.h +index 3dd5a781da99..bfb74723f151 100644 +--- a/include/linux/usb/renesas_usbhs.h ++++ b/include/linux/usb/renesas_usbhs.h +@@ -157,7 +157,7 @@ struct renesas_usbhs_driver_param { + */ + int pio_dma_border; /* default is 64byte */ + +- u32 type; ++ uintptr_t type; + u32 enable_gpio; + + /* +-- +2.6.2 + diff --git a/patches.renesas/0325-usb-renesas_usbhs-Add-support-for-R-Car-H3.patch b/patches.renesas/0325-usb-renesas_usbhs-Add-support-for-R-Car-H3.patch new file mode 100644 index 00000000000000..234a39a5180173 --- /dev/null +++ b/patches.renesas/0325-usb-renesas_usbhs-Add-support-for-R-Car-H3.patch @@ -0,0 +1,45 @@ +From 7da7809999ed59bd003299ce718e1d98992713bf Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Tue, 29 Sep 2015 18:21:19 +0900 +Subject: [PATCH 325/326] usb: renesas_usbhs: Add support for R-Car H3 + +This patch adds a compatible string to support for R-Car H3. + +Since the HS-USB controller of R-Car H3 is almost the same specification +with R-Car Gen2 (these have 16 pipes and usb-dmac), this patch +sets the "type" of renesas_usbhs_driver_param to USBHS_TYPE_RCAR_GEN2. + +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Felipe Balbi <balbi@ti.com> +(cherry picked from commit f5f6afa85aa82a8ee59072f2d09f2b381f24c871) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 1 + + drivers/usb/renesas_usbhs/common.c | 5 +++++ + 2 files changed, 6 insertions(+) + +--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt ++++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt +@@ -5,6 +5,7 @@ Required properties: + - "renesas,usbhs-r8a7790" + - "renesas,usbhs-r8a7791" + - "renesas,usbhs-r8a7794" ++ - "renesas,usbhs-r8a7795" + - reg: Base address and length of the register for the USBHS + - interrupts: Interrupt specifier for the USBHS + - clocks: A list of phandle + clock specifier pairs +--- a/drivers/usb/renesas_usbhs/common.c ++++ b/drivers/usb/renesas_usbhs/common.c +@@ -476,6 +476,11 @@ static const struct of_device_id usbhs_o + .compatible = "renesas,usbhs-r8a7794", + .data = (void *)USBHS_TYPE_RCAR_GEN2, + }, ++ { ++ /* Gen3 is compatible with Gen2 */ ++ .compatible = "renesas,usbhs-r8a7795", ++ .data = (void *)USBHS_TYPE_RCAR_GEN2, ++ }, + { }, + }; + MODULE_DEVICE_TABLE(of, usbhs_of_match); @@ -157,6 +157,202 @@ patches.renesas/0126-ASoC-rsnd-don-t-use-rsnd_mod_to_io-on-snd_kcontrol.patch patches.renesas/0127-ASoC-rsnd-move-rsnd_mod_is_working-to-rsnd_io_is_wor.patch patches.renesas/0128-ASoC-rsnd-remove-io-from-rsnd_mod.patch patches.renesas/0129-ASoC-rsrc-card-remove-unused-ret.patch +patches.renesas/00130-clk-shmobile-Remove-unneeded-include-linux-clkdev.h.patch +patches.renesas/00131-clk-shmobile-emev2-deassert-reset-for-IIC0-1.patch +patches.renesas/00132-clk-shmobile-Add-CPG-MSTP-Clock-Domain-support.patch +patches.renesas/00133-clk-shmobile-r8a7778-Add-CPG-MSTP-Clock-Domain-suppo.patch +patches.renesas/00134-clk-shmobile-r8a7779-Add-CPG-MSTP-Clock-Domain-suppo.patch +patches.renesas/00135-clk-shmobile-rcar-gen2-Add-CPG-MSTP-Clock-Domain-sup.patch +patches.renesas/00136-clk-shmobile-rz-Add-CPG-MSTP-Clock-Domain-support.patch +patches.renesas/00137-regulator-da9210-Add-optional-interrupt-support.patch +patches.renesas/00138-gpio-rcar-Fine-grained-Runtime-PM-support.patch +patches.renesas/00139-gpio-rcar-Add-r8a7795-R-Car-H3-support.patch +patches.renesas/00140-irqchip-renesas-irqc-Get-rid-of-IRQF_VALID.patch +patches.renesas/00141-irqchip-renesas-irqc-Use-linear-IRQ-domain.patch +patches.renesas/00142-irqchip-renesas-irqc-Make-use-of-irq_find_mapping.patch +patches.renesas/00143-ARM-shmobile-R-Mobile-Move-to_rmobile_pd-from-header.patch +patches.renesas/00144-ARM-shmobile-R-Mobile-Use-BIT-macro-instead-of-open-.patch +patches.renesas/00145-ARM-shmobile-r8a7779-Remove-GENPD_FLAG_PM_CLK-flag.patch +patches.renesas/00146-ARM-shmobile-Remove-legacy-board-code-for-KZM-A9-GT.patch +patches.renesas/00147-ARM-shmobile-Remove-legacy-kzm9g_defconfig.patch +patches.renesas/00148-ARM-shmobile-Drop-sh73a0-kzm9g.dtb-for-legacy-builds.patch +patches.renesas/00149-ARM-shmobile-Remove-legacy-SoC-code-for-SH-Mobile-AG.patch +patches.renesas/00150-ARM-shmobile-Remove-legacy-board-code-for-Armadillo-.patch +patches.renesas/00151-ARM-shmobile-Remove-legacy-armadillo800eva_defconfig.patch +patches.renesas/00152-ARM-shmobile-Drop-r8a7740-armadillo800eva.dtb-for-le.patch +patches.renesas/00153-ARM-shmobile-Remove-legacy-SoC-code-for-R-Mobile-A1.patch +patches.renesas/00154-ARM-shmobile-Remove-unused-dma-register.h.patch +patches.renesas/00155-ARM-shmobile-R-Mobile-Remove-legacy-PM-Domain-code.patch +patches.renesas/00156-ARM-shmobile-Remove-obsolete-zboot-support.patch +patches.renesas/00157-ARM-shmobile-R-Car-Gen2-CONFIG_ARCH_SHMOBILE_MULTI-i.patch +patches.renesas/00158-ARM-shmobile-timer-r8a73a4-and-r8a7790-are-multi-pla.patch +patches.renesas/00159-ARM-shmobile-Enable-gose-board-in-multiplatform-defc.patch +patches.renesas/00160-ARM-shmobile-add-r8a7793-minimal-SoC-device-tree.patch +patches.renesas/00161-ARM-shmobile-r8a7793-add-minimal-Gose-board-device-t.patch +patches.renesas/00162-ARM-shmobile-r8a7790-add-EtherAVB-clocks.patch +patches.renesas/00163-ARM-shmobile-r8a7790-add-EtherAVB-DT-support.patch +patches.renesas/00164-ARM-shmobile-armadillo800eva-dts-Add-pinctrl-and-gpi.patch +patches.renesas/00165-ARM-shmobile-r8a73a4-dtsi-Use-arm-gic-400-for-GIC.patch +patches.renesas/00166-ARM-shmobile-r8a7790-dtsi-Use-arm-gic-400-for-GIC.patch +patches.renesas/00167-ARM-shmobile-r8a7791-dtsi-Use-arm-gic-400-for-GIC.patch +patches.renesas/00168-ARM-shmobile-r8a7793-dtsi-Use-arm-gic-400-for-GIC.patch +patches.renesas/00169-ARM-shmobile-r8a7794-dtsi-Use-arm-gic-400-for-GIC.patch +patches.renesas/00170-ARM-shmobile-r8a7779-Configure-IRLM-mode-via-DT.patch +patches.renesas/00171-ARM-shmobile-R-Car-Improve-documentation.patch +patches.renesas/00172-ARM-shmobile-R-Car-Shrink-rcar_sysc_ch-size.patch +patches.renesas/00173-ARM-shmobile-R-Car-Break-infinite-loop.patch +patches.renesas/00174-ARM-shmobile-R-Car-Make-struct-rcar_sysc_ch-paramete.patch +patches.renesas/00175-ARM-shmobile-R-Car-Use-BIT-macro-instead-of-open-cod.patch +patches.renesas/00176-ARM-shmobile-R-Car-Get-rid-of-on_off_fn-function-poi.patch +patches.renesas/00177-ARM-shmobile-r8a7779-Make-struct-rcar_sysc_ch-const.patch +patches.renesas/00178-ARM-shmobile-r8a7790-Make-struct-rcar_sysc_ch-const.patch +patches.renesas/00179-ARM-shmobile-Basic-r8a7793-SoC-support.patch +patches.renesas/00180-ARM-shmobile-gose-enable-R-Car-Gen2-regulator-quirk.patch +patches.renesas/00181-ARM-shmobile-apmu-silence-build-warnings.patch +patches.renesas/00182-ARM-shmobile-r8a7779-Generic-CCF-and-timer-support.patch +patches.renesas/00183-ARM-shmobile-r8a7779-Generic-SMP-ops.patch +patches.renesas/00184-ARM-shmobile-emev2-add-IIC-cores-to-dtsi.patch +patches.renesas/00185-ARM-shmobile-emev2-kzm9d-enable-IIC-busses.patch +patches.renesas/00186-ARM-shmobile-lager-add-sound-label-on-DTS.patch +patches.renesas/00187-ARM-shmobile-koelsch-add-sound-label-on-DTS.patch +patches.renesas/00188-ARM-shmobile-defconfig-add-Renesas-DPCM-Sound-Card.patch +patches.renesas/00189-ARM-shmobile-Remove-marzen_defconfig.patch +patches.renesas/00190-ARM-shmobile-lager-Fix-adv7511-IRQ-sensing.patch +patches.renesas/00191-ARM-shmobile-r8a7790-Add-Audio-CTU-support-on-DTSI.patch +patches.renesas/00192-ARM-shmobile-r8a7790-Add-Audio-MIX-support-on-DTSI.patch +patches.renesas/00193-ARM-shmobile-r8a7791-Add-Audio-CTU-support-on-DTSI.patch +patches.renesas/00194-ARM-shmobile-r8a7791-Add-Audio-MIX-support-on-DTSI.patch +patches.renesas/00195-ARM-shmobile-Enable-fixed-voltage-regulator-in-shmob.patch +patches.renesas/00196-ARM-shmobile-marzen-reference-Remove-C-board-code.patch +patches.renesas/00197-ARM-shmobile-r8a7779-Cleanup-header-file.patch +patches.renesas/00198-ARM-shmobile-marzen-Remove-legacy-board-code.patch +patches.renesas/00199-ARM-shmobile-r8a7779-Remove-legacy-SoC-code.patch +patches.renesas/00200-ARM-shmobile-r8a7790-Add-JPU-device-node.patch +patches.renesas/00201-ARM-shmobile-r8a7791-Add-JPU-device-node.patch +patches.renesas/00202-ARM-shmobile-r8a7794-add-PFC-DT-support.patch +patches.renesas/00203-ARM-shmobile-silk-initial-device-tree.patch +patches.renesas/00204-ARM-shmobile-r8a7794-add-MMCIF-DT-support.patch +patches.renesas/00205-ARM-shmobile-r8a73a4-dtsi-Add-missing-gpio-ranges-to.patch +patches.renesas/00206-ARM-shmobile-r8a7740-dtsi-Add-missing-gpio-ranges-to.patch +patches.renesas/00207-ARM-shmobile-sh73a0-dtsi-Add-missing-gpio-ranges-to-.patch +patches.renesas/00208-ARM-shmobile-r7s72100-dtsi-Add-CPG-MSTP-Clock-Domain.patch +patches.renesas/00209-ARM-shmobile-r8a7778-dtsi-Add-CPG-MSTP-Clock-Domain.patch +patches.renesas/00210-ARM-shmobile-r8a7779-dtsi-Add-CPG-MSTP-Clock-Domain.patch +patches.renesas/00211-ARM-shmobile-r8a7790-dtsi-Add-CPG-MSTP-Clock-Domain.patch +patches.renesas/00212-ARM-shmobile-r8a7791-dtsi-Add-CPG-MSTP-Clock-Domain.patch +patches.renesas/00213-ARM-shmobile-r8a7793-dtsi-Add-CPG-MSTP-Clock-Domain.patch +patches.renesas/00214-ARM-shmobile-r8a7794-dtsi-Add-CPG-MSTP-Clock-Domain.patch +patches.renesas/00215-pinctrl-simplify-of_pinctrl_get.patch +patches.renesas/00216-pinctrl-pinconf-Allow-groups-to-be-configured-via-de.patch +patches.renesas/00217-pinctrl-pinconf-Fix-display-of-configs.patch +patches.renesas/00218-pinctrl-pinconf-pinconf_show_config-can-be-static.patch +patches.renesas/00219-pinctrl-use-dev_err-to-show-message-in-pinctrl_regis.patch +patches.renesas/00220-pinctrl-use-dev_err-to-show-message-in-pinmux_func_n.patch +patches.renesas/00221-pinctrl-join-dev_dbg-strings-into-a-single-line.patch +patches.renesas/00222-media-media-soc_camera-rcar_vin-Add-BT.709-24-bit-RG.patch +patches.renesas/00223-media-media-rcar_vin-fill-in-bus_info-field.patch +patches.renesas/00224-media-media-rcar_vin-Reject-videobufs-that-are-too-s.patch +patches.renesas/00225-spi-rspi-Drop-variable-error-in-qspi_trigger_transfe.patch +patches.renesas/00226-spi-rspi-Make-qspi_set_send_trigger-return-unsigned-.patch +patches.renesas/00227-ata-sata_rcar-Remove-obsolete-sata-r8a779-platform_d.patch +patches.renesas/00228-clockevents-drivers-sh_cmt-Remove-obsolete-sh-cmt-32.patch +patches.renesas/00229-clockevents-drivers-sh_cmt-Remove-obsolete-sh-cmt-48.patch +patches.renesas/00230-sh-irq-Use-irq-accessor-functions-instead-of-open-co.patch +patches.renesas/00231-sh-intc-Use-irq_desc_get_xxx-to-avoid-redundant-look.patch +patches.renesas/00232-sh_eth-propagate-platform_get_irq-error-upstream.patch +patches.renesas/00233-mmc-sh_mmcif-Fix-suspend-process.patch +patches.renesas/00234-mmc-tmio-Fix-timeout-value-for-command-request.patch +patches.renesas/00235-spi-sh-msiof-Remove-obsolete-spi_r8a779x_msiof-platf.patch +patches.renesas/00237-pinctrl-sh-pfc-Remove-r8a73a4-platform_device_id-ent.patch +patches.renesas/00238-pinctrl-sh-pfc-r8a7740-Fix-typo-SCIFAB-in-comment.patch +patches.renesas/00239-pinctrl-sh-pfc-Add-r8a7793-support.patch +patches.renesas/00240-pinctrl-sh-pfc-Enable-building-of-r8a7793-PFC-suppor.patch +patches.renesas/00241-pinctrl-sh-pfc-Add-renesas-pfc-r8a7793-to-binding-do.patch +patches.renesas/00242-pinctrl-sh-pfc-r8a73a4-Remove-obsolete-multi-platfor.patch +patches.renesas/00243-pinctrl-sh-pfc-r8a7790-Add-PWM-pin-groups-and-functi.patch +patches.renesas/00244-pinctrl-sh-pfc-r8a7791-Add-PWM-pin-groups-and-functi.patch +patches.renesas/00245-pinctrl-Spelling-s-reseved-reserved.patch +patches.renesas/00246-pinctrl-sh-pfc-add-R8A7794-PFC-support.patch +patches.renesas/00247-pinctrl-sh-pfc-r8a7794-add-MMCIF-pin-groups.patch +patches.renesas/00248-pinctrl-sh-pfc-r8a7794-add-SDHI-pin-groups.patch +patches.renesas/00249-sh-pfc-r8a7790-remove-non-existing-GPIO-pins.patch +patches.renesas/00250-sh-pfc-r8a7791-remove-non-existing-GPIO-pins.patch +patches.renesas/00251-pinctrl-sh-pfc-Accept-standard-function-pins-and-gro.patch +patches.renesas/00252-pinctrl-sh-pfc-Convert-to-platform_get_.patch +patches.renesas/00253-dmaengine-shdma-Make-dummy-shdma_chan_filter-always-.patch +patches.renesas/00254-dmaengine-sort-the-sh-Makefile.patch +patches.renesas/00255-usb-renesas_usbhs-Replace-deprecated-API-of-extcon.patch +patches.renesas/00256-usb-renesas_usbhs-Allow-an-OTG-PHY-driver-to-provide.patch +patches.renesas/00257-media-media-uapi-vsp1-Use-__u32-instead-of-u32.patch +patches.renesas/00258-media-v4l-vsp1-Fix-VI6_WPF_SZCLIP_SIZE_MASK-macro.patch +patches.renesas/00259-media-v4l-vsp1-Fix-VI6_DPR_ROUTE_FP_MASK-macro.patch +patches.renesas/00260-media-v4l-vsp1-Fix-VI6_DPR_ROUTE_FXA_MASK-macro.patch +patches.renesas/00261-media-v4l-vsp1-Fix-Suspend-to-RAM.patch +patches.renesas/00262-media-v4l-vsp1-Fix-race-condition-when-stopping-pipe.patch +patches.renesas/00263-media-v4l-vsp1-Align-crop-rectangle-to-even-boundary.patch +patches.renesas/00264-media-vsp1-declar-vsp1_pipeline_stopped-as-static.patch +patches.renesas/00265-media-v4l-vsp1-Fix-plane-stride-and-size-checks.patch +patches.renesas/00266-media-v4l-vsp1-Don-t-sleep-in-atomic-context.patch +patches.renesas/00267-regmap-add-force_write-option-on-_regmap_update_bits.patch +patches.renesas/00268-regmap-add-regmap_fields_force_write.patch +patches.renesas/00269-regmap-add-regmap_write_bits.patch +patches.renesas/00270-clockevents-drivers-sh_cmt-Remove-obsolete-sh-cmt-48.patch +patches.renesas/00271-pinctrl-sh-pfc-Remove-obsolete-sh73a0-platform_devic.patch +patches.renesas/00272-pinctrl-sh-pfc-Remove-obsolete-r8a7740-platform_devi.patch +patches.renesas/00273-pinctrl-sh-pfc-Implement-pinconf-power-source-param-.patch +patches.renesas/00274-pinctrl-sh-pfc-r8a7794-add-USB-pin-groups.patch +patches.renesas/00275-ASoC-core-add-snd_soc_of_parse_audio_prefix.patch +patches.renesas/00276-ASoC-rsnd-gen-add-rsnd_force_write.patch +patches.renesas/00277-ASoC-rsrc-card-use-snd_soc_of_parse_audio_route-pref.patch +patches.renesas/00278-ASoC-rsnd-remove-unnecessary-out-of-memory-message-f.patch +patches.renesas/00279-ASoC-rsnd-remove-unnecessary-out-of-memory-message-f.patch +patches.renesas/00280-ASoC-rsnd-remove-unnecessary-out-of-memory-message-f.patch +patches.renesas/00281-ASoC-rsnd-rename-BUSIF_DALIGN-to-SSI_BUSIF_DALIGN.patch +patches.renesas/00282-ASoC-rsnd-rename-INT_ENABLE-to-SSI_INT_ENABLE.patch +patches.renesas/00283-ASoC-rsnd-fixup-each-module-counter-on-__rsnd_mod_ca.patch +patches.renesas/00284-ASoC-rsnd-add-workaround-for-SRC-sync-convert-DVC.patch +patches.renesas/00285-ASoC-rsnd-rsnd_mod_id-return-1-if-mod-was-NULL.patch +patches.renesas/00286-ASoC-rsnd-move-DVC-specific-macro-into-dvc.c.patch +patches.renesas/00287-ASoC-rsnd-move-SRC-specific-macro-into-src.c.patch +patches.renesas/00288-ASoC-rsnd-dvc-make-sure-DVC-soft-reset.patch +patches.renesas/00289-ASoC-rsnd-src-make-sure-SRC-soft-reset.patch +patches.renesas/00290-ASoC-rsnd-enable-module-multi-connection.patch +patches.renesas/00291-ASoC-rsnd-rename-rsnd_path_parse-break-into-add-remo.patch +patches.renesas/00292-ASoC-rsnd-add-rsnd_path_parse-for-CTU-MIX-DVC-route-.patch +patches.renesas/00293-ASoC-rsnd-add-rsnd_dvc_initialize_lock-unlock.patch +patches.renesas/00294-ASoC-rsnd-add-rsnd_src_initialize_lock-unlock.patch +patches.renesas/00295-ASoC-rsnd-tidyup-ADINR-function-name.patch +patches.renesas/00296-ASoC-rsnd-add-rsnd_get_adinr_chan.patch +patches.renesas/00297-ASoC-rsnd-tidyup-data-align-position.patch +patches.renesas/00298-ASoC-rsnd-show-debug-message-for-SSI-SRC-DVC-connect.patch +patches.renesas/00299-ASoC-rsnd-tidyup-rsnd_dma_ops-definition-place.patch +patches.renesas/00300-ASoC-rsnd-check-the-Gen1-at-the-beginning-of-DVC-pro.patch +patches.renesas/00301-ASoC-rsnd-dma-add-DMA-name-on-.ops.patch +patches.renesas/00302-ASoC-rsnd-add-rsnd_io_to_mod.patch +patches.renesas/00303-ASoC-rsnd-tidyup-SRC-position-on-each-code.patch +patches.renesas/00304-ASoC-rsnd-update-Audio-DMA-path-search-method.patch +patches.renesas/00305-ASoC-rsnd-add-CTU-Channel-Transfer-Unit-prototype-su.patch +patches.renesas/00306-ASoC-rsnd-add-MIX-Mixer-support.patch +patches.renesas/00307-ASoC-rsnd-tidyup-parameter-assignment-position.patch +patches.renesas/00308-ASoC-rcar-ctu-Staticise-local-symbols.patch +patches.renesas/00309-ASoC-rsnd-Silence-DMA-slave-ID-compile-warning-on-64.patch +patches.renesas/00310-irqchip-renesas-intc-irqpin-Use-a-separate-lockdep-c.patch +patches.renesas/00311-irqchip-renesas-intc-irqpin-Propagate-wake-up-settin.patch +patches.renesas/00312-irqchip-renesas-irqc-Use-a-separate-lockdep-class.patch +patches.renesas/00313-irqchip-renesas-irqc-Propagate-wake-up-settings-to-p.patch +patches.renesas/00314-pinctrl-join-lines-that-can-be-a-single-line-within-.patch +patches.renesas/00315-pinctrl-core-Warn-about-NULL-gpio_chip-in-pinctrl_re.patch +patches.renesas/00316-PCI-rcar-Add-R8A7794-support.patch +patches.renesas/00317-drivers-sh-Disable-legacy-default-PM-Domain-on-emev2.patch +patches.renesas/00318-drivers-sh-Disable-PM-runtime-for-multi-platform-ARM.patch +patches.renesas/00319-ARM-shmobile-r8a7790-dtsi-Add-CPG-MSTP-Clock-Domain-.patch +patches.renesas/00320-ARM-shmobile-r8a7791-dtsi-Add-CPG-MSTP-Clock-Domain-.patch +patches.renesas/00321-spi-sh-msiof-Match-renesas-rx-fifo-size-in-DT-bindin.patch +patches.renesas/00322-usb-renesas_usbhs-Change-USBHS_TYPE_R8A779x-to-USBHS.patch +patches.renesas/00323-usb-renesas_usbhs-Add-support-for-R-Car-E2.patch +patches.renesas/00324-usb-renesas_usbhs-fix-build-warning-if-64-bit-archit.patch +patches.renesas/00325-usb-renesas_usbhs-Add-support-for-R-Car-H3.patch + ############################################################################# # fixes that go after all of the above |