diff options
Diffstat (limited to 'include/asm-ia64')
120 files changed, 1889 insertions, 24701 deletions
diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h index 5f23c350b9951..a277c8ff9595c 100644 --- a/include/asm-ia64/machvec.h +++ b/include/asm-ia64/machvec.h @@ -74,8 +74,6 @@ extern void machvec_memory_fence (void); # include <asm/machvec_dig.h> # elif defined (CONFIG_IA64_HP_ZX1) # include <asm/machvec_hpzx1.h> -# elif defined (CONFIG_IA64_SGI_SN1) -# include <asm/machvec_sn1.h> # elif defined (CONFIG_IA64_SGI_SN2) # include <asm/machvec_sn2.h> # elif defined (CONFIG_IA64_GENERIC) diff --git a/include/asm-ia64/nodedata.h b/include/asm-ia64/nodedata.h index 0e9c624369188..9acdcb7ffe58a 100644 --- a/include/asm-ia64/nodedata.h +++ b/include/asm-ia64/nodedata.h @@ -22,6 +22,7 @@ struct pglist_data; struct ia64_node_data { + short active_cpu_count; short node; struct pglist_data *pg_data_ptrs[NR_NODES]; struct page *bank_mem_map_base[NR_BANKS]; diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h index fa31d2fff5ff0..7b3f5d8614eea 100644 --- a/include/asm-ia64/sn/addrs.h +++ b/include/asm-ia64/sn/addrs.h @@ -1,26 +1,17 @@ - /* - * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1992-1999,2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 1992-1999,2001-2003 Silicon Graphics, Inc. All rights reserved. */ - #ifndef _ASM_IA64_SN_ADDRS_H #define _ASM_IA64_SN_ADDRS_H #include <linux/config.h> -#if defined (CONFIG_IA64_SGI_SN1) -#include <asm/sn/sn1/addrs.h> -#elif defined (CONFIG_IA64_SGI_SN2) #include <asm/sn/sn2/addrs.h> -#else -#error <<<BOMB! addrs.h defined only for SN1, or SN2 >>> -#endif /* !SN1 && !SN2 */ #ifndef __ASSEMBLY__ #include <asm/sn/types.h> @@ -30,11 +21,7 @@ #define PS_UINT_CAST (__psunsigned_t) #define UINT64_CAST (uint64_t) -#ifdef CONFIG_IA64_SGI_SN2 #define HUBREG_CAST (volatile mmr_t *) -#else -#define HUBREG_CAST (volatile hubreg_t *) -#endif #elif __ASSEMBLY__ @@ -52,11 +39,7 @@ * node's address space. */ -#ifdef CONFIG_IA64_SGI_SN2 /* SN2 has an extra AS field between node offset and node id (nasid) */ #define NODE_OFFSET(_n) (UINT64_CAST (_n) << NASID_SHFT) -#else -#define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS) -#endif #define NODE_CAC_BASE(_n) (CAC_BASE + NODE_OFFSET(_n)) #define NODE_HSPEC_BASE(_n) (HSPEC_BASE + NODE_OFFSET(_n)) @@ -83,7 +66,7 @@ */ #define SWIN_SIZE_BITS 24 -#define SWIN_SIZE (UINT64_CAST 1 << 24) +#define SWIN_SIZE (1UL<<24) #define SWIN_SIZEMASK (SWIN_SIZE - 1) #define SWIN_WIDGET_MASK 0xF @@ -119,44 +102,13 @@ * references to the local hub's registers. */ -#if defined CONFIG_IA64_SGI_SN1 -#define LREG_BASE (HSPEC_BASE + 0x10000000) -#define LREG_SIZE 0x8000000 /* 128 MB */ -#define LREG_LIMIT (LREG_BASE + LREG_SIZE) -#define LBOOT_BASE (LREG_LIMIT) -#define LBOOT_SIZE 0x8000000 /* 128 MB */ -#define LBOOT_LIMIT (LBOOT_BASE + LBOOT_SIZE) -#define LBOOT_STRIDE 0x2000000 /* two PROMs, on 32M boundaries */ -#endif - #define HUB_REGISTER_WIDGET 1 -#ifdef CONFIG_IA64_SGI_SN2 #define IALIAS_BASE LOCAL_SWIN_BASE(HUB_REGISTER_WIDGET) -#else -#define IALIAS_BASE NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET) -#endif #define IALIAS_SIZE 0x800000 /* 8 Megabytes */ #define IS_IALIAS(_a) (((_a) >= IALIAS_BASE) && \ ((_a) < (IALIAS_BASE + IALIAS_SIZE))) /* - * Macro for referring to Hub's RBOOT space - */ - -#if defined CONFIG_IA64_SGI_SN1 - -#define NODE_LREG_BASE(_n) (NODE_HSPEC_BASE(_n) + 0x30000000) -#define NODE_LREG_LIMIT(_n) (NODE_LREG_BASE(_n) + LREG_SIZE) -#define RREG_BASE(_n) (NODE_LREG_BASE(_n)) -#define RREG_LIMIT(_n) (NODE_LREG_LIMIT(_n)) -#define RBOOT_SIZE 0x8000000 /* 128 Megabytes */ -#define NODE_RBOOT_BASE(_n) (NODE_HSPEC_BASE(_n) + 0x38000000) -#define NODE_RBOOT_LIMIT(_n) (NODE_RBOOT_BASE(_n) + RBOOT_SIZE) - -#endif - - -/* * The following macros produce the correct base virtual address for * the hub registers. The LOCAL_HUB_* macros produce the appropriate * address for the local registers. The REMOTE_HUB_* macro produce @@ -166,11 +118,10 @@ */ -#ifdef CONFIG_IA64_SGI_SN2 /* - * SN2 has II mmr's located inside small window space like SN0 & SN1, - * but has all other non-II mmr's located at the top of big window - * space, unlike SN0 & SN1. + * SN2 has II mmr's located inside small window space. + * As all other non-II mmr's located at the top of big window + * space. */ #define LOCAL_HUB_BASE(_x) (LOCAL_MMR_ADDR(_x) | (((~(_x)) & BWIN_TOP)>>8)) #define REMOTE_HUB_BASE(_x) \ @@ -182,18 +133,6 @@ #define REMOTE_HUB(_n, _x) \ (HUBREG_CAST (REMOTE_HUB_BASE(_x) | ((((long)(_n))<<NASID_SHFT)))) -#else /* not CONFIG_IA64_SGI_SN2 */ - -#define LOCAL_HUB(_x) (HUBREG_CAST (IALIAS_BASE + (_x))) -#define REMOTE_HUB(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ - 0x800000 + (_x))) -#endif - -#ifdef CONFIG_IA64_SGI_SN1 -#define LOCAL_HSPEC(_x) (HUBREG_CAST (LREG_BASE + (_x))) -#define REMOTE_HSPEC(_n, _x) (HUBREG_CAST (RREG_BASE(_n) + (_x))) -#endif /* CONFIG_IA64_SGI_SN1 */ - /* * WARNING: @@ -203,27 +142,12 @@ * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S(). * They're always safe. */ -#ifdef CONFIG_IA64_SGI_SN2 #define LOCAL_HUB_ADDR(_x) \ (((_x) & BWIN_TOP) ? (HUBREG_CAST (LOCAL_MMR_ADDR(_x))) \ : (HUBREG_CAST (IALIAS_BASE + (_x)))) #define REMOTE_HUB_ADDR(_n, _x) \ (((_x) & BWIN_TOP) ? (HUBREG_CAST (GLOBAL_MMR_ADDR(_n, _x))) \ : (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + 0x800000 + (_x)))) -#else -#define LOCAL_HUB_ADDR(_x) (HUBREG_CAST (IALIAS_BASE + (_x))) -#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ - 0x800000 + (_x))) -#endif -#if CONFIG_IA64_SGI_SN1 -#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ - 0x800000 + PIREG(_x, _sn))) -#endif - -#ifdef CONFIG_IA64_SGI_SN1 -#define LOCAL_HSPEC_ADDR(_x) (HUBREG_CAST (LREG_BASE + (_x))) -#define REMOTE_HSPEC_ADDR(_n, _x) (HUBREG_CAST (RREG_BASE(_n) + (_x))) -#endif /* CONFIG_IA64_SGI_SN1 */ #ifndef __ASSEMBLY__ @@ -237,13 +161,6 @@ #define REMOTE_HUB_PI_L(_n, _sn, _r) HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r))) #define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d)) -#ifdef CONFIG_IA64_SGI_SN1 -#define LOCAL_HSPEC_L(_r) HUB_L(LOCAL_HSPEC_ADDR(_r)) -#define LOCAL_HSPEC_S(_r, _d) HUB_S(LOCAL_HSPEC_ADDR(_r), (_d)) -#define REMOTE_HSPEC_L(_n, _r) HUB_L(REMOTE_HSPEC_ADDR((_n), (_r))) -#define REMOTE_HSPEC_S(_n, _r, _d) HUB_S(REMOTE_HSPEC_ADDR((_n), (_r)), (_d)) -#endif /* CONFIG_IA64_SGI_SN1 */ - #endif /* __ASSEMBLY__ */ /* @@ -311,12 +228,7 @@ #define KLD_KERN_XP(nasid) (KLD_BASE(nasid) + KLI_KERN_XP) #define KLD_KERN_PARTID(nasid) (KLD_BASE(nasid) + KLI_KERN_PARTID) -#ifndef CONFIG_IA64_SGI_SN2 -#define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset -#else -#define KLCONFIG_OFFSET(nasid) \ - ia64_sn_get_klconfig_addr(nasid) -#endif /* CONFIG_IA64_SGI_SN2 */ +#define KLCONFIG_OFFSET(nasid) ia64_sn_get_klconfig_addr(nasid) #define KLCONFIG_ADDR(nasid) \ TO_NODE_CAC((nasid), KLCONFIG_OFFSET(nasid)) diff --git a/include/asm-ia64/sn/alenlist.h b/include/asm-ia64/sn/alenlist.h index 81243e7c24450..5853ee9307571 100644 --- a/include/asm-ia64/sn/alenlist.h +++ b/include/asm-ia64/sn/alenlist.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_ALENLIST_H #define _ASM_IA64_SN_ALENLIST_H diff --git a/include/asm-ia64/sn/arc/hinv.h b/include/asm-ia64/sn/arc/hinv.h index 9ae8feb80de78..b2ebb3f31b6a4 100644 --- a/include/asm-ia64/sn/arc/hinv.h +++ b/include/asm-ia64/sn/arc/hinv.h @@ -1,13 +1,11 @@ /* - * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. */ - /* $Id$ * * ARCS hardware/memory inventory/configuration and system ID definitions. diff --git a/include/asm-ia64/sn/arc/types.h b/include/asm-ia64/sn/arc/types.h index 53c5d4d8186c4..fff10f87856ee 100644 --- a/include/asm-ia64/sn/arc/types.h +++ b/include/asm-ia64/sn/arc/types.h @@ -3,8 +3,8 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * + * Copyright (c) 1999,2001-2003 Silicon Graphics, Inc. All Rights Reserved. * Copyright 1999 Ralf Baechle (ralf@gnu.org) - * Copyright 1999,2001 Silicon Graphics, Inc. */ #ifndef _ASM_SN_ARC_TYPES_H #define _ASM_SN_ARC_TYPES_H diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h index 85fadf519f997..a22d12db3e9ab 100644 --- a/include/asm-ia64/sn/arch.h +++ b/include/asm-ia64/sn/arch.h @@ -6,7 +6,7 @@ * * SGI specific setup. * - * Copyright (C) 1995-1997,1999,2001-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1995-1997,1999,2001-2003 Silicon Graphics, Inc. All rights reserved. * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) */ #ifndef _ASM_IA64_SN_ARCH_H @@ -17,23 +17,12 @@ #include <linux/mmzone.h> #include <asm/sn/types.h> -#if defined(CONFIG_IA64_SGI_SN1) -#include <asm/sn/sn1/arch.h> -#elif defined(CONFIG_IA64_SGI_SN2) #include <asm/sn/sn2/arch.h> -#endif - -#if defined(CONFIG_IA64_SGI_SN1) -typedef u64 bdrkreg_t; -#elif defined(CONFIG_IA64_SGI_SN2) typedef u64 shubreg_t; -#endif - typedef u64 hubreg_t; typedef u64 mmr_t; typedef u64 nic_t; -typedef char cnodeid_t; #define CNODE_TO_CPU_BASE(_cnode) (NODEPDA(_cnode)->node_first_cpu) diff --git a/include/asm-ia64/sn/ate_utils.h b/include/asm-ia64/sn/ate_utils.h index 02bd7cd678c66..d2bc0b8209506 100644 --- a/include/asm-ia64/sn/ate_utils.h +++ b/include/asm-ia64/sn/ate_utils.h @@ -7,7 +7,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ /* diff --git a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h index 5cc1eb60b48bb..0a17504d62b94 100644 --- a/include/asm-ia64/sn/bte.h +++ b/include/asm-ia64/sn/bte.h @@ -1,7 +1,7 @@ /* * * - * Copyright (c) 2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (c) 2000-2003 Silicon Graphics, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License @@ -36,11 +36,28 @@ #ifndef _ASM_IA64_SN_BTE_H #define _ASM_IA64_SN_BTE_H -#ident "$Revision: 1.1 $" - +#include <linux/timer.h> #include <linux/spinlock.h> #include <linux/cache.h> #include <asm/sn/io.h> +#include <asm/delay.h> + + +/* #define BTE_DEBUG */ +/* #define BTE_DEBUG_VERBOSE */ + +#ifdef BTE_DEBUG +# define BTE_PRINTK(x) printk x /* Terse */ +# ifdef BTE_DEBUG_VERBOSE +# define BTE_PRINTKV(x) printk x /* Verbose */ +# else +# define BTE_PRINTKV(x) +# endif /* BTE_DEBUG_VERBOSE */ +#else +# define BTE_PRINTK(x) +# define BTE_PRINTKV(x) +#endif /* BTE_DEBUG */ + /* BTE status register only supports 16 bits for length field */ #define BTE_LEN_BITS (16) @@ -48,40 +65,60 @@ #define BTE_MAX_XFER ((1 << BTE_LEN_BITS) * L1_CACHE_BYTES) -/* - * Constants used in determining the best and worst case transfer - * times. To help explain the two, the following graph of transfer - * status vs time may help. - * - * active +------------------:-+ : - * status | : | : - * idle +__________________:_+======= - * 0 Time MaxT MinT - * - * Therefore, MaxT is the maximum thoeretical rate for transfering - * the request block (assuming ideal circumstances) - * - * MinT is the minimum theoretical rate for transferring the - * requested block (assuming maximum link distance and contention) - * - * The following defines are the inverse of the above. They are - * used for calculating the MaxT time and MinT time given the - * number of lines in the transfer. - */ -#define BTE_MAXT_LINES_PER_SECOND 800 -#define BTE_MINT_LINES_PER_SECOND 600 - - /* Define hardware */ #define BTES_PER_NODE 2 + /* Define hardware modes */ #define BTE_NOTIFY (IBCT_NOTIFY) #define BTE_NORMAL BTE_NOTIFY #define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE) - /* Use a reserved bit to let the caller specify a wait for any BTE */ #define BTE_WACQUIRE (0x4000) +/* macro to force the IBCT0 value valid */ +#define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE)) + + +/* + * Handle locking of the bte interfaces. + * + * All transfers spinlock the interface before setting up the SHUB + * registers. Sync transfers hold the lock until all processing is + * complete. Async transfers release the lock as soon as the transfer + * is initiated. + * + * To determine if an interface is available, we must check both the + * busy bit and the spinlock for that interface. + */ +#define BTE_LOCK_IF_AVAIL(_x) (\ + (*pda->cpu_bte_if[_x]->most_rcnt_na & (IBLS_BUSY | IBLS_ERROR)) && \ + (!(spin_trylock(&(pda->cpu_bte_if[_x]->spinlock)))) \ + ) + +/* + * Some macros to simplify reading. + * Start with macros to locate the BTE control registers. + */ +#define BTEREG_LNSTAT_ADDR ((u64 *)(bte->bte_base_addr)) +#define BTEREG_SRC_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_SRC)) +#define BTEREG_DEST_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_DEST)) +#define BTEREG_CTRL_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_CTRL)) +#define BTEREG_NOTIF_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_NOTIFY)) + + +/* Possible results from bte_copy and bte_unaligned_copy */ +typedef enum { + BTE_SUCCESS, /* 0 is success */ + BTEFAIL_NOTAVAIL, /* BTE not available */ + BTEFAIL_POISON, /* poison page */ + BTEFAIL_PROT, /* Protection violation */ + BTEFAIL_ACCESS, /* access error */ + BTEFAIL_TOUT, /* Time out */ + BTEFAIL_XTERR, /* Diretory error */ + BTEFAIL_DIR, /* Diretory error */ + BTEFAIL_ERROR, /* Generic error */ +} bte_result_t; + /* * Structure defining a bte. An instance of this @@ -90,28 +127,41 @@ * This structure contains everything necessary * to work with a BTE. */ -typedef struct bteinfo_s { +struct bteinfo_s { u64 volatile notify ____cacheline_aligned; char *bte_base_addr ____cacheline_aligned; spinlock_t spinlock; - u64 ideal_xfr_tmo; /* Time out */ - u64 ideal_xfr_tmo_cnt; - /* u64 most_recent_src; - * u64 most_recent_dest; - * u64 most_recent_len; - * u64 most_recent_mode; */ + cnodeid_t bte_cnode; /* cnode */ + int bte_error_count; /* Number of errors encountered */ + int bte_num; /* 0 --> BTE0, 1 --> BTE1 */ + int cleanup_active; /* Interface is locked for cleanup */ + volatile bte_result_t bh_error; /* error while processing */ u64 volatile *most_rcnt_na; - void *bte_test_buf; -} bteinfo_t; + void *scratch_buf; /* Node local scratch buffer */ +}; -/* Possible results from bte_copy and bte_unaligned_copy */ -typedef enum { - BTE_SUCCESS, /* 0 is success */ - BTEFAIL_NOTAVAIL, /* BTE not available */ - BTEFAIL_ERROR, /* Generic error */ - BTEFAIL_DIR /* Diretory error */ -} bte_result_t; -void bte_reset_nasid(nasid_t); +/* + * Function prototypes (functions defined in bte.c, used elsewhere) + */ +extern bte_result_t bte_copy(u64, u64, u64, u64, void *); +extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64); +extern void bte_error_handler(unsigned long); + + +/* + * The following is the prefered way of calling bte_unaligned_copy + * If the copy is fully cache line aligned, then bte_copy is + * used instead. Since bte_copy is inlined, this saves a call + * stack. NOTE: bte_copy is called synchronously and does block + * until the transfer is complete. In order to get the asynch + * version of bte_copy, you must perform this check yourself. + */ +#define BTE_UNALIGNED_COPY(src, dest, len, mode) \ + (((len & L1_CACHE_MASK) || (src & L1_CACHE_MASK) || \ + (dest & L1_CACHE_MASK)) ? \ + bte_unaligned_copy(src, dest, len, mode) : \ + bte_copy(src, dest, len, mode, NULL)) + -#endif /* _ASM_IA64_SN_BTE_H */ +#endif /* _ASM_IA64_SN_BTE_H */ diff --git a/include/asm-ia64/sn/bte_copy.h b/include/asm-ia64/sn/bte_copy.h deleted file mode 100644 index 51c45ea152693..0000000000000 --- a/include/asm-ia64/sn/bte_copy.h +++ /dev/null @@ -1,385 +0,0 @@ -/* - * - * - * Copyright (c) 2000-2002 Silicon Graphics, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it would be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Further, this software is distributed without any warranty that it is - * free of the rightful claim of any third person regarding infringement - * or the like. Any license provided herein, whether implied or - * otherwise, applies only to this software file. Patent licenses, if - * any, provided herein do not apply to combinations of this program with - * other software, or any other product whatsoever. - * - * You should have received a copy of the GNU General Public - * License along with this program; if not, write the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, - * Mountain View, CA 94043, or: - * - * http://www.sgi.com - * - * For further information regarding this notice, see: - * - * http://oss.sgi.com/projects/GenInfo/NoticeExplan - */ - -#ifndef _ASM_IA64_SN_BTE_COPY_H -#define _ASM_IA64_SN_BTE_COPY_H - -#ident "$Revision: 1.1 $" - -#include <linux/timer.h> -#include <linux/cache.h> -#include <asm/sn/bte.h> -#include <asm/sn/sgi.h> -#include <asm/sn/pda.h> -#include <asm/delay.h> - -#define L1_CACHE_MASK (L1_CACHE_BYTES - 1) - -/* - * BTE_LOCKING support - When CONFIG_IA64_SGI_BTE_LOCKING is - * not defined, the bte_copy code supports one bte per cpu in - * synchronous mode. Even if bte_copy is called with a - * notify address, the bte will spin and wait for the transfer - * to complete. By defining the following, spin_locks and - * busy checks are placed around the initiation of a BTE - * transfer and multiple bte's per cpu are supported. - */ -#if 0 -#define CONFIG_IA64_SGI_BTE_LOCKING 1 -#endif - -/* - * Handle locking of the bte interfaces. - * - * All transfers spinlock the interface before setting up the SHUB - * registers. Sync transfers hold the lock until all processing is - * complete. Async transfers release the lock as soon as the transfer - * is initiated. - * - * To determine if an interface is available, we must check both the - * busy bit and the spinlock for that interface. - */ -#define BTE_LOCK_IF_AVAIL(_x) (\ - (*pda.cpu_bte_if[_x]->most_rcnt_na & IBLS_BUSY) && \ - (!(spin_trylock(&(pda.cpu_bte_if[_x]->spinlock)))) \ - ) - -/* - * Some macros to simplify reading. - * - * Start with macros to locate the BTE control registers. - */ - -#define BTEREG_LNSTAT_ADDR ((u64 *)(bte->bte_base_addr)) -#define BTEREG_SRC_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_SRC)) -#define BTEREG_DEST_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_DEST)) -#define BTEREG_CTRL_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_CTRL)) -#define BTEREG_NOTIF_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_NOTIFY)) - -/* Some macros to force the IBCT0 value valid. */ - -#define BTE_VALID_MODES BTE_NOTIFY -#define BTE_VLD_MODE(x) (x & BTE_VALID_MODES) - -// #define BTE_DEBUG -// #define BTE_DEBUG_VERBOSE -// #define BTE_TIME - -#ifdef BTE_DEBUG -# define BTE_PRINTK(x) printk x /* Terse */ -# ifdef BTE_DEBUG_VERBOSE -# define BTE_PRINTKV(x) printk x /* Verbose */ -# else -# define BTE_PRINTKV(x) -# endif /* BTE_DEBUG_VERBOSE */ -#else -# define BTE_PRINTK(x) -# define BTE_PRINTKV(x) -#endif /* BTE_DEBUG */ - -#define BTE_IDEAL_TMO(x) (jiffies + \ - (HZ / BTE_MAXT_LINES_PER_SECOND * x)) - -#ifdef BTE_TIME -volatile extern u64 bte_setup_time; -volatile extern u64 bte_transfer_time; -volatile extern u64 bte_tear_down_time; -volatile extern u64 bte_execute_time; - -#define BTE_TIME_DECLARE() \ - u64 btcp_strt_tm = 0; \ - u64 btcp_cplt_tm = 0; \ - u64 xfr_strt_tm = 0; \ - u64 xfr_cplt_tm = 0; \ - -#define BTE_TIME_START() \ - btcp_strt_tm = xfr_strt_tm = xfr_cplt_tm = ia64_get_itc(); - -#define BTE_TIME_XFR_START() \ - xfr_strt_tm = ia64_get_itc(); - -#define BTE_TIME_XFR_STOP() \ - xfr_cplt_tm = ia64_get_itc(); - -#define BTE_TIME_STOP() \ - btcp_cplt_tm = ia64_get_itc(); \ - bte_setup_time = xfr_strt_tm - btcp_strt_tm; \ - bte_transfer_time = xfr_cplt_tm - xfr_strt_tm; \ - bte_tear_down_time = btcp_cplt_tm - xfr_cplt_tm; \ - bte_execute_time = btcp_cplt_tm - btcp_strt_tm; \ - -#else /* BTE_TIME */ -#define BTE_TIME_DECLARE() -#define BTE_TIME_START() -#define BTE_TIME_XFR_START() -#define BTE_TIME_XFR_STOP() -#define BTE_TIME_STOP() -#endif /* BTE_TIME */ - -/* - * bte_copy(src, dest, len, mode, notification) - * - * use the block transfer engine to move kernel - * memory from src to dest using the assigned mode. - * - * Paramaters: - * src - physical address of the transfer source. - * dest - physical address of the transfer destination. - * len - number of bytes to transfer from source to dest. - * mode - hardware defined. See reference information - * for IBCT0/1 in the SHUB Programmers Reference - * notification - kernel virtual address of the notification cache - * line. If NULL, the default is used and - * the bte_copy is synchronous. - * - * NOTE: This function requires src, dest, and len to - * be cache line aligned. - */ -extern __inline__ bte_result_t -bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification) -{ -#ifdef CONFIG_IA64_SGI_BTE_LOCKING - int bte_to_use; -#endif /* CONFIG_IA64_SGI_BTE_LOCKING */ - u64 transfer_size; - u64 lines_remaining; - bteinfo_t *bte; - BTE_TIME_DECLARE(); - - BTE_TIME_START(); - - BTE_PRINTK(("bte_copy (0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx)\n", - src, dest, len, mode, notification)); - - if (len == 0) { - BTE_TIME_STOP(); - return (BTE_SUCCESS); - } - - ASSERT(!((len & L1_CACHE_MASK) || - (src & L1_CACHE_MASK) || (dest & L1_CACHE_MASK))); - - ASSERT(len < ((BTE_LEN_MASK + 1) << L1_CACHE_SHIFT)); - -#ifdef CONFIG_IA64_SGI_BTE_LOCKING - { - bte_to_use = 0; - - /* Attempt to lock one of the BTE interfaces */ - while ((bte_to_use < BTES_PER_NODE) && - BTE_LOCK_IF_AVAIL(bte_to_use)) { - - bte_to_use++; - } - - if ((bte_to_use >= BTES_PER_NODE) && - !(mode & BTE_WACQUIRE)) { - BTE_TIME_STOP(); - return (BTEFAIL_NOTAVAIL); - } - - /* Wait until a bte is available. */ - } - while (bte_to_use >= BTES_PER_NODE); - - bte = pda.cpu_bte_if[bte_to_use]; - BTE_PRINTKV(("Got a lock on bte %d\n", bte_to_use)); -#else - /* Assuming one BTE per CPU. */ - bte = pda->cpu_bte_if[0]; -#endif /* CONFIG_IA64_SGI_BTE_LOCKING */ - - /* - * The following are removed for optimization but is - * available in the event that the SHUB exhibits - * notification problems similar to the hub, bedrock et al. - * - * bte->mostRecentSrc = src; - * bte->mostRecentDest = dest; - * bte->mostRecentLen = len; - * bte->mostRecentMode = mode; - */ - if (notification == NULL) { - /* User does not want to be notified. */ - bte->most_rcnt_na = &bte->notify; - } else { - bte->most_rcnt_na = notification; - } - - /* Calculate the number of cache lines to transfer. */ - transfer_size = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK); - - BTE_PRINTKV(("Calculated transfer size of %d cache lines\n", - transfer_size)); - - /* Initialize the notification to a known value. */ - *bte->most_rcnt_na = -1L; - - - BTE_PRINTKV(("Before, status is 0x%lx and notify is 0x%lx\n", - HUB_L(BTEREG_LNSTAT_ADDR), - *bte->most_rcnt_na)); - - /* Set the status reg busy bit and transfer length */ - BTE_PRINTKV(("IBLS - HUB_S(0x%lx, 0x%lx)\n", - BTEREG_LNSTAT_ADDR, IBLS_BUSY | transfer_size)); - HUB_S(BTEREG_LNSTAT_ADDR, (IBLS_BUSY | transfer_size)); - - /* Set the source and destination registers */ - BTE_PRINTKV(("IBSA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_SRC_ADDR, - (TO_PHYS(src)))); - HUB_S(BTEREG_SRC_ADDR, (TO_PHYS(src))); - BTE_PRINTKV(("IBDA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_DEST_ADDR, - (TO_PHYS(dest)))); - HUB_S(BTEREG_DEST_ADDR, (TO_PHYS(dest))); - - /* Set the notification register */ - BTE_PRINTKV(("IBNA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_NOTIF_ADDR, - (TO_PHYS(__pa(bte->most_rcnt_na))))); - HUB_S(BTEREG_NOTIF_ADDR, (TO_PHYS(__pa(bte->most_rcnt_na)))); - - /* Initiate the transfer */ - BTE_PRINTKV(("IBCT - HUB_S(0x%lx, 0x%lx)\n", BTEREG_CTRL_ADDR, mode)); - BTE_TIME_XFR_START(); - HUB_S(BTEREG_CTRL_ADDR, BTE_VLD_MODE(mode)); - - BTE_PRINTKV(("Initiated, status is 0x%lx and notify is 0x%lx\n", - HUB_L(BTEREG_LNSTAT_ADDR), - *bte->most_rcnt_na)); - - if (notification == NULL) { - /* - * Calculate our timeout - * - * What are we doing here? We are trying to determine - * the fastest time the BTE could have transfered our - * block of data. By takine the clock frequency (ticks/sec) - * divided by the BTE MaxT Transfer Rate (lines/sec) - * times the transfer size (lines), we get a tick - * offset from current time that the transfer should - * complete. - * - * Why do this? We are watching for a notification - * failure from the BTE. This behaviour has been - * seen in the SN0 and SN1 hardware on rare circumstances - * and is expected in SN2. By checking at the - * ideal transfer timeout, we minimize our time - * delay from hardware completing our request and - * our detecting the failure. - */ - bte->ideal_xfr_tmo = BTE_IDEAL_TMO(transfer_size); - - while (bte->notify == -1UL) { - /* - * Notification Workaround: When the max - * theoretical time has elapsed, read the hub - * status register into the notification area. - * This fakes the shub performing the copy. - */ - BTE_PRINTKV((" Timing. IBLS = 0x%lx, " - "notify= 0x%lx\n", - HUB_L(BTEREG_LNSTAT_ADDR), - bte->notify)); - if (time_after(jiffies, bte->ideal_xfr_tmo)) { - lines_remaining = HUB_L(BTEREG_LNSTAT_ADDR) & - BTE_LEN_MASK; - bte->ideal_xfr_tmo_cnt++; - bte->ideal_xfr_tmo = - BTE_IDEAL_TMO(lines_remaining); - - BTE_PRINTKV((" Timeout. cpu %d " - "IBLS = 0x%lx, " - "notify= 0x%lx, " - "Lines remaining = %d. " - "New timeout = %d.\n", - smp_processor_id(), - HUB_L(BTEREG_LNSTAT_ADDR), - bte->notify, - lines_remaining, - bte->ideal_xfr_tmo)); - } - } - BTE_PRINTKV((" Delay Done. IBLS = 0x%lx, notify= 0x%lx\n", - HUB_L(BTEREG_LNSTAT_ADDR), - bte->notify)); - BTE_TIME_XFR_STOP(); - if (bte->notify & IBLS_ERROR) { - /* >>> Need to do real error checking. */ - transfer_size = 0; - -#ifdef CONFIG_IA64_SGI_BTE_LOCKING - spin_unlock(&(bte->spinlock)); -#endif /* CONFIG_IA64_SGI_BTE_LOCKING */ - BTE_PRINTKV(("Erroring status is 0x%lx and " - "notify is 0x%lx\n", - HUB_L(BTEREG_LNSTAT_ADDR), - bte->notify)); - - BTE_TIME_STOP(); - bte->notify = 0L; - return (BTEFAIL_ERROR); - } - - } -#ifdef CONFIG_IA64_SGI_BTE_LOCKING - spin_unlock(&(bte->spinlock)); -#endif /* CONFIG_IA64_SGI_BTE_LOCKING */ - BTE_TIME_STOP(); - BTE_PRINTKV(("Returning status is 0x%lx and notify is 0x%lx\n", - HUB_L(BTEREG_LNSTAT_ADDR), - *bte->most_rcnt_na)); - - return (BTE_SUCCESS); -} - -/* - * Define the bte_unaligned_copy as an extern. - */ -extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64); - -/* - * The following is the prefered way of calling bte_unaligned_copy - * If the copy is fully cache line aligned, then bte_copy is - * used instead. Since bte_copy is inlined, this saves a call - * stack. NOTE: bte_copy is called synchronously and does block - * until the transfer is complete. In order to get the asynch - * version of bte_copy, you must perform this check yourself. - */ -#define BTE_UNALIGNED_COPY(src, dest, len, mode) \ - (((len & L1_CACHE_MASK) || (src & L1_CACHE_MASK) || \ - (dest & L1_CACHE_MASK)) ? \ - bte_unaligned_copy(src, dest, len, mode) : \ - bte_copy(src, dest, len, mode, NULL)) - -#endif /* _ASM_IA64_SN_BTE_COPY_H */ diff --git a/include/asm-ia64/sn/cdl.h b/include/asm-ia64/sn/cdl.h index 35c7f8ec37b23..6f551e1ca85a3 100644 --- a/include/asm-ia64/sn/cdl.h +++ b/include/asm-ia64/sn/cdl.h @@ -4,13 +4,20 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_CDL_H #define _ASM_IA64_SN_CDL_H #include <asm/sn/sgi.h> +struct cdl { + int part_num; /* Part part number */ + int mfg_num; /* Part MFG number */ + int (*attach)(vertex_hdl_t); /* Attach routine */ +}; + + /* * cdl: connection/driver list * @@ -21,175 +28,14 @@ typedef struct cdl *cdl_p; /* - * cdl_itr_f is the type for the functions - * that are handled by cdl_iterate. - */ - -typedef void -cdl_iter_f (devfs_handle_t vhdl); - -/* - * cdl_drv_f is the type for the functions - * that are called by cdl_add_driver and - * cdl_del_driver. - */ - -typedef void -cdl_drv_f (devfs_handle_t vhdl, int key1, int key2, int error); - -/* - * If CDL_PRI_HI is specified in the flags - * parameter for cdl_add_driver, then that driver's - * attach routine will be called for future connect - * points before any (non-CDL_PRI_HI) drivers. - * - * The IOC3 driver uses this facility to make sure - * that the ioc3_attach() function is called before - * the attach routines of any subdevices. - * - * Drivers for bridge-based crosstalk cards that - * are almost but not quite generic can use it to - * arrange that their attach() functions get called - * before the generic bridge drivers, so they can - * leave behind "hint" structures that will - * properly configure the generic driver. - */ -#define CDL_PRI_HI 0x0001 - -/* - * cdl_new: construct a new connection/driver list - * - * Called once for each "kind" of bus. Returns an - * opaque cookie representing the particular list - * that will be operated on by the other calls. - */ -extern cdl_p cdl_new(char *, char *, char *); - -/* - * cdl_del: destroy a connection/driver list. - * - * Releases all dynamically allocated resources - * associated with the specified list. Forgets what - * drivers might be involved in this kind of bus, - * forgets what connection points have been noticed - * on this kind of bus. - */ -extern void cdl_del(cdl_p reg); - -/* - * cdl_add_driver: register a device driver - * - * Calls the driver's attach routine with all - * connection points on the list that have the same - * key information as the driver; call-back the - * specified function to notify the driver of the - * attach status for each device. Place the driver - * on the list so that any connection points - * discovered in the future that match the driver - * can be handed off to the driver's attach - * routine. - * - * CDL_PRI_HI may be specified (see above). - */ - -extern int cdl_add_driver(cdl_p reg, - int key1, - int key2, - char *prefix, - int flags, - cdl_drv_f *func); - -/* - * cdl_del_driver: remove a device driver - * - * Calls the driver's detach routine with all - * connection points on the list that match the - * driver; call-back the specified function to - * notify the driver of the detach status for each - * device. Then forget about the driver. Future - * calls to cdl_add_connpt with connections that - * would match this driver no longer trigger calls - * to the driver's attach routine. - * - * NOTE: Yes, I said CONNECTION POINTS, not - * verticies that the driver has been attached to - * with hwgraph_driver_add(); this gives the driver - * a chance to clean up anything it did to the - * connection point in its attach routine. Also, - * this is done whether or not the attach routine - * was successful. - */ -extern void cdl_del_driver(cdl_p reg, - char *prefix, - cdl_drv_f *func); - -/* * cdl_add_connpt: add a connection point * * Calls the attach routines of all the drivers on * the list that match this connection point, in - * the order that they were added to the list, - * except that CDL_PRI_HI drivers are called first. - * - * Then the vertex is added to the list, so it can - * be presented to any matching drivers that may be - * subsequently added to the list. + * the order that they were added to the list. */ -extern int cdl_add_connpt(cdl_p reg, - int key1, +extern int cdl_add_connpt(int key1, int key2, - devfs_handle_t conn, + vertex_hdl_t conn, int drv_flags); - -/* - * cdl_del_connpt: delete a connection point - * - * Calls the detach routines of all matching - * drivers for this connection point, in the same - * order that the attach routines were called; then - * forgets about this vertex, so drivers added in - * the future will not be told about it. - * - * NOTE: Same caveat here about the detach calls as - * in the cdl_del_driver() comment above. - */ -extern int cdl_del_connpt(cdl_p reg, - int key1, - int key2, - devfs_handle_t conn, - int drv_flags); - -/* - * cdl_iterate: find all verticies in the registry - * corresponding to the named driver and call them - * with the specified function (giving the vertex - * as the parameter). - */ - -extern void cdl_iterate(cdl_p reg, - char *prefix, - cdl_iter_f *func); - -/* - * An INFO_LBL_ASYNC_ATTACH label is attached to a vertex, pointing to - * an instance of async_attach_s to indicate that asynchronous - * attachment may be applied to that device ... if the corresponding - * driver allows it. - */ - -struct async_attach_s { - struct semaphore async_sema; - int async_count; -}; -typedef struct async_attach_s *async_attach_t; - -async_attach_t async_attach_new(void); -void async_attach_free(async_attach_t); -async_attach_t async_attach_get_info(devfs_handle_t); -void async_attach_add_info(devfs_handle_t, async_attach_t); -void async_attach_del_info(devfs_handle_t); -void async_attach_signal_start(async_attach_t); -void async_attach_signal_done(async_attach_t); -void async_attach_waitall(async_attach_t); - #endif /* _ASM_IA64_SN_CDL_H */ diff --git a/include/asm-ia64/sn/clksupport.h b/include/asm-ia64/sn/clksupport.h index 633ebb1e03197..f619c692c8117 100644 --- a/include/asm-ia64/sn/clksupport.h +++ b/include/asm-ia64/sn/clksupport.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. */ /* @@ -31,28 +31,10 @@ typedef long clkreg_t; extern unsigned long sn_rtc_cycles_per_second; - -#if defined(CONFIG_IA64_SGI_SN1) -#include <asm/sn/sn1/bedrock.h> -#include <asm/sn/sn1/hubpi_next.h> - -extern nasid_t master_nasid; - -#define RTC_MASK 0x007fffffffffffffUL -/* clocks are not synchronized yet on SN1 - used node 0 (problem if no NASID 0) */ -#define RTC_COUNTER_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_COUNTER)) -#define RTC_COMPARE_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_COMPARE_A)) -#define RTC_COMPARE_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_COMPARE_B)) -#define RTC_INT_PENDING_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_INT_PEND_A)) -#define RTC_INT_PENDING_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_INT_PEND_B)) -#define RTC_INT_ENABLED_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_INT_EN_A)) -#define RTC_INT_ENABLED_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_INT_EN_B)) -#else /* !CONFIG_IA64_SGI_SN1 */ #include <asm/sn/addrs.h> #include <asm/sn/sn2/addrs.h> #include <asm/sn/sn2/shubio.h> #include <asm/sn/sn2/shub_mmr.h> -#define RTC_MASK SH_RTC_MASK #define RTC_COUNTER_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #define RTC_COMPARE_A_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #define RTC_COMPARE_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) @@ -60,7 +42,6 @@ extern nasid_t master_nasid; #define RTC_INT_PENDING_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #define RTC_INT_ENABLED_A_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #define RTC_INT_ENABLED_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) -#endif /* CONFIG_IA64_SGI_SN1 */ #define GET_RTC_COUNTER() (*RTC_COUNTER_ADDR) #define rtc_time() GET_RTC_COUNTER() diff --git a/include/asm-ia64/sn/dmamap.h b/include/asm-ia64/sn/dmamap.h index 6f56cac7f86ac..2f34eda46bf75 100644 --- a/include/asm-ia64/sn/dmamap.h +++ b/include/asm-ia64/sn/dmamap.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_DMAMAP_H #define _ASM_IA64_SN_DMAMAP_H @@ -54,9 +54,6 @@ extern void dma_mapfree(dmamap_t *); extern int dma_map(dmamap_t *, caddr_t, int); extern int dma_map2(dmamap_t *, caddr_t, caddr_t, int); extern paddr_t dma_mapaddr(dmamap_t *, caddr_t); -#ifdef LATER -extern int dma_mapbp(dmamap_t *, buf_t *, int); -#endif extern int dma_map_alenlist(dmamap_t *, struct alenlist_s *, size_t); extern uint ev_kvtoiopnum(caddr_t); diff --git a/include/asm-ia64/sn/driver.h b/include/asm-ia64/sn/driver.h index 17a76381d6b78..c23e70d92aec5 100644 --- a/include/asm-ia64/sn/driver.h +++ b/include/asm-ia64/sn/driver.h @@ -4,12 +4,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_DRIVER_H #define _ASM_IA64_SN_DRIVER_H -#include <linux/devfs_fs_kernel.h> +#include <asm/sn/sgi.h> #include <asm/types.h> /* @@ -75,7 +75,7 @@ typedef struct device_desc_s { /* TBD: allocated badwidth requirements */ /* interrupt description */ - devfs_handle_t intr_target; /* Hardware locator string */ + vertex_hdl_t intr_target; /* Hardware locator string */ int intr_policy; /* TBD */ ilvl_t intr_swlevel; /* software level for blocking intr */ char *intr_name; /* name of interrupt, if any */ diff --git a/include/asm-ia64/sn/eeprom.h b/include/asm-ia64/sn/eeprom.h deleted file mode 100644 index cc358591dd349..0000000000000 --- a/include/asm-ia64/sn/eeprom.h +++ /dev/null @@ -1,384 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Public interface for reading Atmel EEPROMs via L1 system controllers - * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_EEPROM_H -#define _ASM_IA64_SN_EEPROM_H - -#include <linux/config.h> -#include <asm/sn/sgi.h> -#include <asm/sn/vector.h> -#include <asm/sn/xtalk/xbow.h> -#include <asm/sn/pci/bridge.h> -#include <asm/sn/nic.h> - -/* - * The following structures are an implementation of the EEPROM info - * areas described in the SN1 EEPROM spec and the IPMI FRU Information - * Storage definition - */ - -/* Maximum lengths for EEPROM fields - */ -#define EEPROM_PARTNUM_LEN 20 -#define EEPROM_SERNUM_LEN 10 -#define EEPROM_MANUF_NAME_LEN 10 -#define EEPROM_PROD_NAME_LEN 14 - - - -/* The EEPROM "common header", which contains offsets to the other - * info areas in the EEPROM - */ -typedef struct eeprom_common_hdr_t -{ - uchar_t format; /* common header format byte */ - uchar_t internal_use; /* offsets to various info areas */ - uchar_t chassis; /* (in doubleword units) */ - uchar_t board; - uchar_t product; - uchar_t multi_record; - uchar_t pad; - uchar_t checksum; -} eeprom_common_hdr_t; - - -/* The chassis (brick) info area - */ -typedef struct eeprom_chassis_ia_t -{ - uchar_t format; /* format byte */ - uchar_t length; /* info area length in doublewords */ - uchar_t type; /* chassis type (always 0x17 "rack mount") */ - uchar_t part_num_tl; /* type/length of part number field */ - - char part_num[EEPROM_PARTNUM_LEN]; - /* ASCII part number */ - - uchar_t serial_num_tl; /* type/length of serial number field */ - - char serial_num[EEPROM_SERNUM_LEN]; - /* ASCII serial number */ - - uchar_t checksum; - -} eeprom_chassis_ia_t; - - -/* The board info area - */ -typedef struct eeprom_board_ia_t -{ - uchar_t format; /* format byte */ - uchar_t length; /* info area length in doublewords */ - uchar_t language; /* language code, always 0x00 "English" */ - int mfg_date; /* date & time of manufacture, in minutes - since 0:00 1/1/96 */ - uchar_t manuf_tl; /* type/length of manufacturer name field */ - - char manuf[EEPROM_MANUF_NAME_LEN]; - /* ASCII manufacturer name */ - - uchar_t product_tl; /* type/length of product name field */ - - char product[EEPROM_PROD_NAME_LEN]; - /* ASCII product name */ - - uchar_t serial_num_tl; /* type/length of board serial number */ - - char serial_num[EEPROM_SERNUM_LEN]; - /* ASCII serial number */ - - uchar_t part_num_tl; /* type/length of board part number */ - - char part_num[EEPROM_PARTNUM_LEN]; - /* ASCII part number */ - - /* - * "custom" fields -- see SN1 EEPROM Spec - */ - uchar_t board_rev_tl; /* type/length of board rev (always 0xC2) */ - - char board_rev[2]; /* ASCII board revision */ - - uchar_t eeprom_size_tl; /* type/length of eeprom size field */ - uchar_t eeprom_size; /* size code for eeprom */ - uchar_t temp_waiver_tl; /* type/length of temp waiver field (0xC2) */ - char temp_waiver[2]; /* temp waiver */ - - - /* - * these fields only appear in main boards' EEPROMs - */ - uchar_t ekey_G_tl; /* type/length of encryption key "G" */ - uint32_t ekey_G; /* encryption key "G" */ - uchar_t ekey_P_tl; /* type/length of encryption key "P" */ - uint32_t ekey_P; /* encryption key "P" */ - uchar_t ekey_Y_tl; /* type/length of encryption key "Y" */ - uint32_t ekey_Y; /* encryption key "Y" */ - - - /* - * these fields are used for I bricks only - */ - uchar_t mac_addr_tl; /* type/length of MAC address */ - char mac_addr[12]; /* MAC address */ - uchar_t ieee1394_cfg_tl; /* type/length of IEEE 1394 info */ - uchar_t ieee1394_cfg[32]; /* IEEE 1394 config info */ - - - /* - * all boards have a checksum - */ - uchar_t checksum; - -} eeprom_board_ia_t; - -/* given a pointer to the three-byte little-endian EEPROM representation - * of date-of-manufacture, this function translates to a big-endian - * integer format - */ -int eeprom_xlate_board_mfr_date( uchar_t *src ); - - -/* EEPROM Serial Presence Detect record (used for DIMMs in IP35) - */ -typedef struct eeprom_spd_t -{ - /* 0*/ uchar_t spd_used; /* # of bytes written to serial memory by manufacturer */ - /* 1*/ uchar_t spd_size; /* Total # of bytes of SPD memory device */ - /* 2*/ uchar_t mem_type; /* Fundamental memory type (FPM, EDO, SDRAM..) */ - /* 3*/ uchar_t num_rows; /* # of row addresses on this assembly */ - /* 4*/ uchar_t num_cols; /* # Column Addresses on this assembly */ - /* 5*/ uchar_t mod_rows; /* # Module Rows on this assembly */ - /* 6*/ uchar_t data_width[2]; /* Data Width of this assembly (16b little-endian) */ - /* 8*/ uchar_t volt_if; /* Voltage interface standard of this assembly */ - /* 9*/ uchar_t cyc_time; /* SDRAM Cycle time, CL=X (highest CAS latency) */ - /* A*/ uchar_t acc_time; /* SDRAM Access from Clock (highest CAS latency) */ - /* B*/ uchar_t dimm_cfg; /* DIMM Configuration type (non-parity, ECC) */ - /* C*/ uchar_t refresh_rt; /* Refresh Rate/Type */ - /* D*/ uchar_t prim_width; /* Primary SDRAM Width */ - /* E*/ uchar_t ec_width; /* Error Checking SDRAM width */ - /* F*/ uchar_t min_delay; /* Min Clock Delay Back to Back Random Col Address */ - /*10*/ uchar_t burst_len; /* Burst Lengths Supported */ - /*11*/ uchar_t num_banks; /* # of Banks on Each SDRAM Device */ - /*12*/ uchar_t cas_latencies; /* CAS# Latencies Supported */ - /*13*/ uchar_t cs_latencies; /* CS# Latencies Supported */ - /*14*/ uchar_t we_latencies; /* Write Latencies Supported */ - /*15*/ uchar_t mod_attrib; /* SDRAM Module Attributes */ - /*16*/ uchar_t dev_attrib; /* SDRAM Device Attributes: General */ - /*17*/ uchar_t cyc_time2; /* Min SDRAM Cycle time at CL X-1 (2nd highest CAS latency) */ - /*18*/ uchar_t acc_time2; /* SDRAM Access from Clock at CL X-1 (2nd highest CAS latency) */ - /*19*/ uchar_t cyc_time3; /* Min SDRAM Cycle time at CL X-2 (3rd highest CAS latency) */ - /*1A*/ uchar_t acc_time3; /* Max SDRAM Access from Clock at CL X-2 (3nd highest CAS latency) */ - /*1B*/ uchar_t min_row_prechg; /* Min Row Precharge Time (Trp) */ - /*1C*/ uchar_t min_ra_to_ra; /* Min Row Active to Row Active (Trrd) */ - /*1D*/ uchar_t min_ras_to_cas; /* Min RAS to CAS Delay (Trcd) */ - /*1E*/ uchar_t min_ras_pulse; /* Minimum RAS Pulse Width (Tras) */ - /*1F*/ uchar_t row_density; /* Density of each row on module */ - /*20*/ uchar_t ca_setup; /* Command and Address signal input setup time */ - /*21*/ uchar_t ca_hold; /* Command and Address signal input hold time */ - /*22*/ uchar_t d_setup; /* Data signal input setup time */ - /*23*/ uchar_t d_hold; /* Data signal input hold time */ - - /*24*/ uchar_t pad0[26]; /* unused */ - - /*3E*/ uchar_t data_rev; /* SPD Data Revision Code */ - /*3F*/ uchar_t checksum; /* Checksum for bytes 0-62 */ - /*40*/ uchar_t jedec_id[8]; /* Manufacturer's JEDEC ID code */ - - /*48*/ uchar_t mfg_loc; /* Manufacturing Location */ - /*49*/ uchar_t part_num[18]; /* Manufacturer's Part Number */ - - /*5B*/ uchar_t rev_code[2]; /* Revision Code */ - - /*5D*/ uchar_t mfg_date[2]; /* Manufacturing Date */ - - /*5F*/ uchar_t ser_num[4]; /* Assembly Serial Number */ - - /*63*/ uchar_t manuf_data[27]; /* Manufacturer Specific Data */ - - /*7E*/ uchar_t intel_freq; /* Intel specification frequency */ - /*7F*/ uchar_t intel_100MHz; /* Intel spec details for 100MHz support */ - -} eeprom_spd_t; - - -#define EEPROM_SPD_RECORD_MAXLEN 256 - -typedef union eeprom_spd_u -{ - eeprom_spd_t fields; - char bytes[EEPROM_SPD_RECORD_MAXLEN]; - -} eeprom_spd_u; - - -/* EEPROM board record - */ -typedef struct eeprom_brd_record_t -{ - eeprom_chassis_ia_t *chassis_ia; - eeprom_board_ia_t *board_ia; - eeprom_spd_u *spd; - -} eeprom_brd_record_t; - - -/* End-of-fields marker - */ -#define EEPROM_EOF 0xc1 - - -/* masks for dissecting the type/length bytes - */ -#define FIELD_FORMAT_MASK 0xc0 -#define FIELD_LENGTH_MASK 0x3f - - -/* field format codes (used in type/length bytes) - */ -#define FIELD_FORMAT_BINARY 0x00 /* binary format */ -#define FIELD_FORMAT_BCD 0x40 /* BCD */ -#define FIELD_FORMAT_PACKED 0x80 /* packed 6-bit ASCII */ -#define FIELD_FORMAT_ASCII 0xC0 /* 8-bit ASCII */ - - - - -/* codes specifying brick and board type - */ -#define C_BRICK 0x100 - -#define C_PIMM (C_BRICK | 0x10) -#define C_PIMM_0 (C_PIMM) /* | 0x0 */ -#define C_PIMM_1 (C_PIMM | 0x1) - -#define C_DIMM (C_BRICK | 0x20) -#define C_DIMM_0 (C_DIMM) /* | 0x0 */ -#define C_DIMM_1 (C_DIMM | 0x1) -#define C_DIMM_2 (C_DIMM | 0x2) -#define C_DIMM_3 (C_DIMM | 0x3) -#define C_DIMM_4 (C_DIMM | 0x4) -#define C_DIMM_5 (C_DIMM | 0x5) -#define C_DIMM_6 (C_DIMM | 0x6) -#define C_DIMM_7 (C_DIMM | 0x7) - -#define R_BRICK 0x200 -#define R_POWER (R_BRICK | 0x10) - -#define VECTOR 0x300 /* used in vector ops when the destination - * could be a cbrick or an rbrick */ - -#define IO_BRICK 0x400 -#define IO_POWER (IO_BRICK | 0x10) - -#define BRICK_MASK 0xf00 -#define SUBORD_MASK 0xf0 /* AND with component specification; if the - the result is non-zero, then the component - is a subordinate board of some kind */ -#define COMPT_MASK 0xf /* if there's more than one instance of a - particular type of subordinate board, this - masks out which one we're talking about */ - - - -/* functions & macros for obtaining "NIC-like" strings from EEPROMs - */ - -#ifdef CONFIG_IA64_SGI_SN1 - -int eeprom_str( char *nic_str, nasid_t nasid, int component ); -int vector_eeprom_str( char *nic_str, nasid_t nasid, - int component, net_vec_t path ); - -#define CBRICK_EEPROM_STR(s,n) eeprom_str((s),(n),C_BRICK) -#define IOBRICK_EEPROM_STR(s,n) eeprom_str((s),(n),IO_BRICK) -#define RBRICK_EEPROM_STR(s,n,p) vector_eeprom_str((s),(n),R_BRICK,p) -#define VECTOR_EEPROM_STR(s,n,p) vector_eeprom_str((s),(n),VECTOR,p) - -#endif /* CONFIG_IA64_SGI_SN1 */ - - -/* functions for obtaining formatted records from EEPROMs - */ - -int cbrick_eeprom_read( eeprom_brd_record_t *buf, nasid_t nasid, - int component ); -int iobrick_eeprom_read( eeprom_brd_record_t *buf, nasid_t nasid, - int component ); -int vector_eeprom_read( eeprom_brd_record_t *buf, nasid_t nasid, - net_vec_t path, int component ); - - - -/* retrieve the ethernet MAC address for an I-brick - */ - -int ibrick_mac_addr_get( nasid_t nasid, char *eaddr ); - - -/* error codes - */ - -#define EEP_OK 0 -#define EEP_L1 1 -#define EEP_FAIL 2 -#define EEP_BAD_CHECKSUM 3 -#define EEP_NICIFY 4 -#define EEP_PARAM 6 -#define EEP_NOMEM 7 - - - -/* given a hardware graph vertex and an indication of the brick type, - * brick and board to be read, this functions reads the eeprom and - * attaches a "NIC"-format string of manufacturing information to the - * vertex. If the vertex already has the string, just returns the - * string. If component is not VECTOR or R_BRICK, the path parameter - * is ignored. - */ - -#ifdef LATER -char *eeprom_vertex_info_set( int component, int nasid, devfs_handle_t v, - net_vec_t path ); -#endif - - - -/* We may need to differentiate between an XBridge and other types of - * bridges during discovery to tell whether the bridge in question - * is part of an IO brick. The following function reads the WIDGET_ID - * register of the bridge under examination and returns a positive value - * if the part and mfg numbers stored there indicate that this widget - * is an XBridge (and so must be part of a brick). - */ -#ifdef LATER -int is_iobrick( int nasid, int widget_num ); -#endif - -/* the following macro derives the widget number from the register - * address passed to it and uses is_iobrick to determine whether - * the widget in question is part of an SN1 IO brick. - */ -#define IS_IOBRICK(rg) is_iobrick( NASID_GET((rg)), SWIN_WIDGETNUM((rg)) ) - - - -/* macros for NIC compatibility */ -/* always invoked on "this" cbrick */ -#define HUB_VERTEX_MFG_INFO(v) \ - eeprom_vertex_info_set( C_BRICK, get_nasid(), (v), 0 ) - -#define BRIDGE_VERTEX_MFG_INFO(v, r) \ - ( IS_IOBRICK((r)) ? eeprom_vertex_info_set \ - ( IO_BRICK, NASID_GET((r)), (v), 0 ) \ - : nic_bridge_vertex_info((v), (r)) ) - -#endif /* _ASM_IA64_SN_EEPROM_H */ diff --git a/include/asm-ia64/sn/fetchop.h b/include/asm-ia64/sn/fetchop.h index 53b7b4f3fbb47..9a5b9a06b5b14 100644 --- a/include/asm-ia64/sn/fetchop.h +++ b/include/asm-ia64/sn/fetchop.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_FETCHOP_H @@ -39,28 +39,10 @@ #ifdef __KERNEL__ /* - * Initialize a FETCHOP line. The argument should point to the beginning - * of the line. - * SN1 - region mask is in word 0, data in word 1 - * SN2 - no region mask. Data in word 0 - */ -#ifdef CONFIG_IA64_SGI_SN1 -#define FETCHOP_INIT_LINE(p) *(p) = 0xffffffffffffffffUL -#elif CONFIG_IA64_SGI_SN2 -#define FETCHOP_INIT_LINE(p) -#endif - -/* - * Convert a region 7 (kaddr) address to the address of the fetchop variable + * Convert a region 6 (kaddr) address to the address of the fetchop variable */ #define FETCHOP_KADDR_TO_MSPEC_ADDR(kaddr) TO_MSPEC(kaddr) -/* - * Convert a page struct (page) address to the address of the first - * fetchop variable in the page - */ -#define FETCHOP_PAGE_TO_MSPEC_ADDR(page) FETCHOP_KADDR_TO_MSPEC_ADDR(__pa(page_address(page))) - /* * Each Atomic Memory Operation (AMO formerly known as fetchop) @@ -80,21 +62,21 @@ * inconsistency. */ typedef struct { - -#ifdef CONFIG_IA64_SGI_SN1 - u64 permissions; -#endif u64 variable; - -#ifdef CONFIG_IA64_SGI_SN1 - u64 unused[6]; -#else u64 unused[7]; -#endif - } AMO_t; +/* + * The following APIs are externalized to the kernel to allocate/free fetchop variables. + * fetchop_kalloc_one - Allocate/initialize 1 fetchop variable on the specified cnode. + * fetchop_kfree_one - Free a previously allocated fetchop variable + */ + +unsigned long fetchop_kalloc_one(int nid); +void fetchop_kfree_one(unsigned long maddr); + + #endif /* __KERNEL__ */ #endif /* _ASM_IA64_SN_FETCHOP_H */ diff --git a/include/asm-ia64/sn/gda.h b/include/asm-ia64/sn/gda.h deleted file mode 100644 index d57b89a7e880c..0000000000000 --- a/include/asm-ia64/sn/gda.h +++ /dev/null @@ -1,109 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Derived from IRIX <sys/SN/gda.h>. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - * - * gda.h -- Contains the data structure for the global data area, - * The GDA contains information communicated between the - * PROM, SYMMON, and the kernel. - */ -#ifndef _ASM_IA64_SN_GDA_H -#define _ASM_IA64_SN_GDA_H - -#include <asm/sn/addrs.h> -#include <asm/sn/sn_cpuid.h> - -#define GDA_MAGIC 0x58464552 - -/* - * GDA Version History - * - * Version # | Change - * -------------+------------------------------------------------------- - * 1 | Initial IP27 version - * 2 | Prom sets g_partid field to the partition number. 0 IS - * | a valid partition #. - */ - -#define GDA_VERSION 2 /* Current GDA version # */ - -#define G_MAGICOFF 0 -#define G_VERSIONOFF 4 -#define G_PROMOPOFF 6 -#define G_MASTEROFF 8 -#define G_VDSOFF 12 -#define G_HKDNORMOFF 16 -#define G_HKDUTLBOFF 24 -#define G_HKDXUTLBOFF 32 -#define G_PARTIDOFF 40 -#define G_TABLEOFF 128 - -#ifndef __ASSEMBLY__ - -typedef struct gda { - u32 g_magic; /* GDA magic number */ - u16 g_version; /* Version of this structure */ - u16 g_masterid; /* The NASID:CPUNUM of the master cpu */ - u32 g_promop; /* Passes requests from the kernel to prom */ - u32 g_vds; /* Store the virtual dipswitches here */ - void **g_hooked_norm;/* ptr to pda loc for norm hndlr */ - void **g_hooked_utlb;/* ptr to pda loc for utlb hndlr */ - void **g_hooked_xtlb;/* ptr to pda loc for xtlb hndlr */ - int g_partid; /* partition id */ - int g_symmax; /* Max symbols in name table. */ - void *g_dbstab; /* Address of idbg symbol table */ - char *g_nametab; /* Address of idbg name table */ - void *g_ktext_repmask; - /* Pointer to a mask of nodes with copies - * of the kernel. */ - char g_padding[56]; /* pad out to 128 bytes */ - nasid_t g_nasidtable[MAX_COMPACT_NODES+1]; /* NASID of each node, - * indexed by cnodeid. - */ -} gda_t; - -#define GDA ((gda_t*) GDA_ADDR(get_nasid())) - -#endif /* __ASSEMBLY__ */ -/* - * Define: PART_GDA_VERSION - * Purpose: Define the minimum version of the GDA required, lower - * revisions assume GDA is NOT set up, and read partition - * information from the board info. - */ -#define PART_GDA_VERSION 2 - -/* - * The following requests can be sent to the PROM during startup. - */ - -#define PROMOP_MAGIC 0x0ead0000 -#define PROMOP_MAGIC_MASK 0x0fff0000 - -#define PROMOP_BIST_SHIFT 11 -#define PROMOP_BIST_MASK (0x3 << 11) - -#define PROMOP_REG PI_ERR_STACK_ADDR_A - -#define PROMOP_INVALID (PROMOP_MAGIC | 0x00) -#define PROMOP_HALT (PROMOP_MAGIC | 0x10) -#define PROMOP_POWERDOWN (PROMOP_MAGIC | 0x20) -#define PROMOP_RESTART (PROMOP_MAGIC | 0x30) -#define PROMOP_REBOOT (PROMOP_MAGIC | 0x40) -#define PROMOP_IMODE (PROMOP_MAGIC | 0x50) - -#define PROMOP_CMD_MASK 0x00f0 -#define PROMOP_OPTIONS_MASK 0xfff0 - -#define PROMOP_SKIP_DIAGS 0x0100 /* don't bother running diags */ -#define PROMOP_SKIP_MEMINIT 0x0200 /* don't bother initing memory */ -#define PROMOP_SKIP_DEVINIT 0x0400 /* don't bother initing devices */ -#define PROMOP_BIST1 0x0800 /* keep track of which BIST ran */ -#define PROMOP_BIST2 0x1000 /* keep track of which BIST ran */ - -#endif /* _ASM_IA64_SN_GDA_H */ diff --git a/include/asm-ia64/sn/geo.h b/include/asm-ia64/sn/geo.h index 130d0b64cbf86..cf4a2f7452f6e 100644 --- a/include/asm-ia64/sn/geo.h +++ b/include/asm-ia64/sn/geo.h @@ -17,15 +17,7 @@ * GEO_MAX_LEN: The maximum length of a geoid, formatted for printing */ -#include <linux/config.h> - -#ifdef CONFIG_IA64_SGI_SN2 #include <asm/sn/sn2/geo.h> -#else - -#error <<BOMB! need geo.h for this platform >> - -#endif /* !SN2 && ... */ /* Declarations applicable to all platforms */ diff --git a/include/asm-ia64/sn/hack.h b/include/asm-ia64/sn/hack.h deleted file mode 100644 index b4f8a8f289318..0000000000000 --- a/include/asm-ia64/sn/hack.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ - - -#ifndef _ASM_IA64_SN_HACK_H -#define _ASM_IA64_SN_HACK_H - -#include <linux/mmzone.h> -#include <asm/sn/arch.h> -#include <asm/sn/types.h> -#include <asm/uaccess.h> /* for copy_??_user */ - -/****************************************** - * Definitions that do not exist in linux * - ******************************************/ - -typedef int cred_t; /* This is for compilation reasons */ -struct cred { int x; }; - - -/* - * Hardware Graph routines that are currently stubbed! - */ -#include <linux/devfs_fs_kernel.h> - -#define DELAY(a) - -/************************************************ - * Routines redefined to use linux equivalents. * - ************************************************/ - -/* #define FIXME(s) printk("FIXME: [ %s ] in %s at %s:%d\n", s, __FUNCTION__, __FILE__, __LINE__) */ - -#define FIXME(s) - -extern devfs_handle_t dummy_vrtx; -#define cpuid_to_vertex(cpuid) dummy_vrtx /* (pdaindr[cpuid].pda->p_vertex) */ - -#define PUTBUF_LOCK(a) { FIXME("PUTBUF_LOCK"); } -#define PUTBUF_UNLOCK(a) { FIXME("PUTBUF_UNLOCK"); } - -typedef int (*splfunc_t)(void); - -/* move to stubs.c yet */ -#define dev_to_vhdl(dev) 0 -#define get_timestamp() 0 -#define us_delay(a) -#define v_mapphys(a,b,c) 0 // printk("Fixme: v_mapphys - soft->base 0x%p\n", b); -#define splhi() 0 -#define spl7 splhi() -#define splx(s) - -extern void * snia_kmem_alloc_node(register size_t, register int, cnodeid_t); -extern void * snia_kmem_zalloc(size_t, int); -extern void * snia_kmem_zalloc_node(register size_t, register int, cnodeid_t ); -extern void * snia_kmem_zone_alloc(register struct zone *, int); -extern struct zone * snia_kmem_zone_init(register int , char *); -extern void snia_kmem_zone_free(register struct zone *, void *); -extern int is_specified(char *); -extern int cap_able(uint64_t); -extern int compare_and_swap_ptr(void **, void *, void *); - -#endif /* _ASM_IA64_SN_HACK_H */ diff --git a/include/asm-ia64/sn/hcl.h b/include/asm-ia64/sn/hcl.h index 2c91163420d2c..34aa4d3a0a3d4 100644 --- a/include/asm-ia64/sn/hcl.h +++ b/include/asm-ia64/sn/hcl.h @@ -4,18 +4,15 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_HCL_H #define _ASM_IA64_SN_HCL_H #include <asm/sn/sgi.h> -#include <asm/sn/invent.h> -#include <linux/devfs_fs_kernel.h> -extern devfs_handle_t hcl_handle; /* HCL driver */ -extern devfs_handle_t hwgraph_root; -extern devfs_handle_t linux_busnum; +extern vertex_hdl_t hwgraph_root; +extern vertex_hdl_t linux_busnum; typedef long labelcl_info_place_t; @@ -58,58 +55,56 @@ struct invplace_s; /* * External declarations of EXPORTED SYMBOLS in hcl.c */ -extern devfs_handle_t hwgraph_register(devfs_handle_t, const char *, +extern vertex_hdl_t hwgraph_register(vertex_hdl_t, const char *, unsigned int, unsigned int, unsigned int, unsigned int, umode_t, uid_t, gid_t, struct file_operations *, void *); -extern int hwgraph_mk_symlink(devfs_handle_t, const char *, unsigned int, - unsigned int, const char *, unsigned int, devfs_handle_t *, void *); +extern int hwgraph_mk_symlink(vertex_hdl_t, const char *, unsigned int, + unsigned int, const char *, unsigned int, vertex_hdl_t *, void *); -extern int hwgraph_vertex_destroy(devfs_handle_t); +extern int hwgraph_vertex_destroy(vertex_hdl_t); -extern int hwgraph_edge_add(devfs_handle_t, devfs_handle_t, char *); -extern int hwgraph_edge_get(devfs_handle_t, char *, devfs_handle_t *); +extern int hwgraph_edge_add(vertex_hdl_t, vertex_hdl_t, char *); +extern int hwgraph_edge_get(vertex_hdl_t, char *, vertex_hdl_t *); -extern arbitrary_info_t hwgraph_fastinfo_get(devfs_handle_t); -extern void hwgraph_fastinfo_set(devfs_handle_t, arbitrary_info_t ); -extern devfs_handle_t hwgraph_mk_dir(devfs_handle_t, const char *, unsigned int, void *); +extern arbitrary_info_t hwgraph_fastinfo_get(vertex_hdl_t); +extern void hwgraph_fastinfo_set(vertex_hdl_t, arbitrary_info_t ); +extern vertex_hdl_t hwgraph_mk_dir(vertex_hdl_t, const char *, unsigned int, void *); -extern int hwgraph_connectpt_set(devfs_handle_t, devfs_handle_t); -extern devfs_handle_t hwgraph_connectpt_get(devfs_handle_t); -extern int hwgraph_edge_get_next(devfs_handle_t, char *, devfs_handle_t *, uint *); -extern graph_error_t hwgraph_edge_remove(devfs_handle_t, char *, devfs_handle_t *); +extern int hwgraph_connectpt_set(vertex_hdl_t, vertex_hdl_t); +extern vertex_hdl_t hwgraph_connectpt_get(vertex_hdl_t); +extern int hwgraph_edge_get_next(vertex_hdl_t, char *, vertex_hdl_t *, uint *); +extern graph_error_t hwgraph_edge_remove(vertex_hdl_t, char *, vertex_hdl_t *); -extern graph_error_t hwgraph_traverse(devfs_handle_t, char *, devfs_handle_t *); +extern graph_error_t hwgraph_traverse(vertex_hdl_t, char *, vertex_hdl_t *); -extern int hwgraph_vertex_get_next(devfs_handle_t *, devfs_handle_t *); -extern int hwgraph_inventory_get_next(devfs_handle_t, invplace_t *, +extern int hwgraph_vertex_get_next(vertex_hdl_t *, vertex_hdl_t *); +extern int hwgraph_inventory_get_next(vertex_hdl_t, invplace_t *, inventory_t **); -extern int hwgraph_inventory_add(devfs_handle_t, int, int, major_t, minor_t, int); -extern int hwgraph_inventory_remove(devfs_handle_t, int, int, major_t, minor_t, int); -extern int hwgraph_controller_num_get(devfs_handle_t); -extern void hwgraph_controller_num_set(devfs_handle_t, int); -extern int hwgraph_path_ad(devfs_handle_t, char *, devfs_handle_t *); -extern devfs_handle_t hwgraph_path_to_vertex(char *); -extern devfs_handle_t hwgraph_path_to_dev(char *); -extern devfs_handle_t hwgraph_block_device_get(devfs_handle_t); -extern devfs_handle_t hwgraph_char_device_get(devfs_handle_t); -extern graph_error_t hwgraph_char_device_add(devfs_handle_t, char *, char *, devfs_handle_t *); -extern int hwgraph_path_add(devfs_handle_t, char *, devfs_handle_t *); -extern int hwgraph_info_add_LBL(devfs_handle_t, char *, arbitrary_info_t); -extern int hwgraph_info_get_LBL(devfs_handle_t, char *, arbitrary_info_t *); -extern int hwgraph_info_replace_LBL(devfs_handle_t, char *, arbitrary_info_t, +extern int hwgraph_inventory_add(vertex_hdl_t, int, int, major_t, minor_t, int); +extern int hwgraph_inventory_remove(vertex_hdl_t, int, int, major_t, minor_t, int); +extern int hwgraph_controller_num_get(vertex_hdl_t); +extern void hwgraph_controller_num_set(vertex_hdl_t, int); +extern int hwgraph_path_ad(vertex_hdl_t, char *, vertex_hdl_t *); +extern vertex_hdl_t hwgraph_path_to_vertex(char *); +extern vertex_hdl_t hwgraph_path_to_dev(char *); +extern vertex_hdl_t hwgraph_block_device_get(vertex_hdl_t); +extern vertex_hdl_t hwgraph_char_device_get(vertex_hdl_t); +extern graph_error_t hwgraph_char_device_add(vertex_hdl_t, char *, char *, vertex_hdl_t *); +extern int hwgraph_path_add(vertex_hdl_t, char *, vertex_hdl_t *); +extern int hwgraph_info_add_LBL(vertex_hdl_t, char *, arbitrary_info_t); +extern int hwgraph_info_get_LBL(vertex_hdl_t, char *, arbitrary_info_t *); +extern int hwgraph_info_replace_LBL(vertex_hdl_t, char *, arbitrary_info_t, arbitrary_info_t *); -extern int hwgraph_info_get_exported_LBL(devfs_handle_t, char *, int *, arbitrary_info_t *); -extern int hwgraph_info_get_next_LBL(devfs_handle_t, char *, arbitrary_info_t *, +extern int hwgraph_info_get_exported_LBL(vertex_hdl_t, char *, int *, arbitrary_info_t *); +extern int hwgraph_info_get_next_LBL(vertex_hdl_t, char *, arbitrary_info_t *, labelcl_info_place_t *); - -extern int hwgraph_path_lookup(devfs_handle_t, char *, devfs_handle_t *, char **); -extern int hwgraph_info_export_LBL(devfs_handle_t, char *, int); -extern int hwgraph_info_unexport_LBL(devfs_handle_t, char *); -extern int hwgraph_info_remove_LBL(devfs_handle_t, char *, arbitrary_info_t *); -extern char * vertex_to_name(devfs_handle_t, char *, uint); -extern graph_error_t hwgraph_vertex_unref(devfs_handle_t); - +extern int hwgraph_path_lookup(vertex_hdl_t, char *, vertex_hdl_t *, char **); +extern int hwgraph_info_export_LBL(vertex_hdl_t, char *, int); +extern int hwgraph_info_unexport_LBL(vertex_hdl_t, char *); +extern int hwgraph_info_remove_LBL(vertex_hdl_t, char *, arbitrary_info_t *); +extern char * vertex_to_name(vertex_hdl_t, char *, uint); +extern graph_error_t hwgraph_vertex_unref(vertex_hdl_t); #endif /* _ASM_IA64_SN_HCL_H */ diff --git a/include/asm-ia64/sn/hcl_util.h b/include/asm-ia64/sn/hcl_util.h index 781b4ccbec0e5..5a083a1693f5e 100644 --- a/include/asm-ia64/sn/hcl_util.h +++ b/include/asm-ia64/sn/hcl_util.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_HCL_UTIL_H @@ -12,11 +12,11 @@ #include <linux/devfs_fs_kernel.h> -extern char * dev_to_name(devfs_handle_t, char *, uint); -extern int device_master_set(devfs_handle_t, devfs_handle_t); -extern devfs_handle_t device_master_get(devfs_handle_t); -extern cnodeid_t master_node_get(devfs_handle_t); -extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t); -extern void mark_nodevertex_as_node(devfs_handle_t, cnodeid_t); +extern char * dev_to_name(vertex_hdl_t, char *, uint); +extern int device_master_set(vertex_hdl_t, vertex_hdl_t); +extern vertex_hdl_t device_master_get(vertex_hdl_t); +extern cnodeid_t master_node_get(vertex_hdl_t); +extern cnodeid_t nodevertex_to_cnodeid(vertex_hdl_t); +extern void mark_nodevertex_as_node(vertex_hdl_t, cnodeid_t); #endif /* _ASM_IA64_SN_HCL_UTIL_H */ diff --git a/include/asm-ia64/sn/hires_clock.h b/include/asm-ia64/sn/hires_clock.h deleted file mode 100644 index d85f8547bbd1d..0000000000000 --- a/include/asm-ia64/sn/hires_clock.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved. - * - * SGI Hi Resolution Clock - * - * SGI SN platforms provide a high resolution clock that is - * synchronized across all nodes. The clock can be memory mapped - * and directly read from user space. - * - * Access to the clock is thru the following: - * (error checking not shown) - * - * (Note: should library routines be provided to encapsulate this??) - * - * int fd: - * volatile long *clk; - * - * fd = open (HIRES_FULLNAME, O_RDONLY); - * clk = mmap(0, getpagesize(), PROT_READ, MAP_SHARED, fd, 0); - * clk += ioctl(fd, HIRES_IOCQGETOFFSET, 0); - * - * At this point, clk is a pointer to the high resolution clock. - * - * The clock period can be obtained via: - * - * long picosec_per_tick; - * picosec_per_tick = ioctl(fd, HIRES_IOCQGETPICOSEC, 0); - */ - -#ifndef _ASM_IA64_SN_HIRES_CLOCK_H -#define _ASM_IA64_SN_HIRES_CLOCK_H - - -#define HIRES_BASENAME "sgi_hires_clock" -#define HIRES_FULLNAME "/dev/sgi_hires_clock" -#define HIRES_IOC_BASE 's' - - -/* Get page offset of hires timer */ -#define HIRES_IOCQGETOFFSET _IO( HIRES_IOC_BASE, 0 ) - -/* get clock period in picoseconds per tick */ -#define HIRES_IOCQGETPICOSEC _IO( HIRES_IOC_BASE, 1 ) - -/* get number of significant bits in clock counter */ -#define HIRES_IOCQGETCLOCKBITS _IO( HIRES_IOC_BASE, 2 ) - -#endif /* _ASM_IA64_SN_HIRES_CLOCK_H */ diff --git a/include/asm-ia64/sn/hwgfs.h b/include/asm-ia64/sn/hwgfs.h new file mode 100644 index 0000000000000..6ca93f4510e6c --- /dev/null +++ b/include/asm-ia64/sn/hwgfs.h @@ -0,0 +1,37 @@ +#ifndef _ASM_IA64_SN_HWGFS_H +#define _ASM_IA64_SN_HWGFS_H + +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. + */ + +#define DEVFS_FL_AUTO_DEVNUM 0 + +typedef struct dentry *hwgfs_handle_t; + +extern hwgfs_handle_t hwgfs_register(hwgfs_handle_t dir, const char *name, + unsigned int flags, + unsigned int major, unsigned int minor, + umode_t mode, void *ops, void *info); +extern int hwgfs_mk_symlink(hwgfs_handle_t dir, const char *name, + unsigned int flags, const char *link, + hwgfs_handle_t *handle, void *info); +extern hwgfs_handle_t hwgfs_mk_dir(hwgfs_handle_t dir, const char *name, + void *info); +extern void hwgfs_unregister(hwgfs_handle_t de); + +extern hwgfs_handle_t hwgfs_find_handle(hwgfs_handle_t dir, const char *name, + unsigned int major,unsigned int minor, + char type, int traverse_symlinks); +extern hwgfs_handle_t hwgfs_get_parent(hwgfs_handle_t de); +extern int hwgfs_generate_path(hwgfs_handle_t de, char *path, int buflen); + +extern void *hwgfs_get_info(hwgfs_handle_t de); +extern int hwgfs_set_info(hwgfs_handle_t de, void *info); + +#endif diff --git a/include/asm-ia64/sn/ifconfig_net.h b/include/asm-ia64/sn/ifconfig_net.h index 8eb976c35fd9e..183c93bfa0040 100644 --- a/include/asm-ia64/sn/ifconfig_net.h +++ b/include/asm-ia64/sn/ifconfig_net.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_IFCONFIG_NET_H diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h index 36e3af325cc94..021141586f91a 100644 --- a/include/asm-ia64/sn/intr.h +++ b/include/asm-ia64/sn/intr.h @@ -4,21 +4,18 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_INTR_H #define _ASM_IA64_SN_INTR_H #include <linux/config.h> - -#if defined(CONFIG_IA64_SGI_SN1) -#include <asm/sn/sn1/intr.h> -#elif defined(CONFIG_IA64_SGI_SN2) #include <asm/sn/sn2/intr.h> -#endif extern void sn_send_IPI_phys(long, int, int); -#define CPU_VECTOR_TO_IRQ(cpuid,vector) ((cpuid) << 8 | (vector)) +#define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector) +#define SN_CPU_FROM_IRQ(irq) (0) +#define SN_IVEC_FROM_IRQ(irq) (irq) #endif /* _ASM_IA64_SN_INTR_H */ diff --git a/include/asm-ia64/sn/intr_public.h b/include/asm-ia64/sn/intr_public.h deleted file mode 100644 index 44367a4580cfc..0000000000000 --- a/include/asm-ia64/sn/intr_public.h +++ /dev/null @@ -1,19 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_INTR_PUBLIC_H -#define _ASM_IA64_SN_INTR_PUBLIC_H - -#include <linux/config.h> - -#if defined(CONFIG_IA64_SGI_SN1) -#include <asm/sn/sn1/intr_public.h> -#elif defined(CONFIG_IA64_SGI_SN2) -#endif - -#endif /* _ASM_IA64_SN_INTR_PUBLIC_H */ diff --git a/include/asm-ia64/sn/invent.h b/include/asm-ia64/sn/invent.h index e75c156d843b0..a495e6f2bd027 100644 --- a/include/asm-ia64/sn/invent.h +++ b/include/asm-ia64/sn/invent.h @@ -4,14 +4,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_INVENT_H #define _ASM_IA64_SN_INVENT_H #include <linux/types.h> -#include <linux/devfs_fs_kernel.h> - +#include <asm/sn/sgi.h> /* * sys/sn/invent.h -- Kernel Hardware Inventory * @@ -31,7 +30,7 @@ #define minor_t int #define app32_ptr_t unsigned long #define graph_vertex_place_t long -#define GRAPH_VERTEX_NONE ((devfs_handle_t)-1) +#define GRAPH_VERTEX_NONE ((vertex_hdl_t)-1) #define GRAPH_EDGE_PLACE_NONE ((graph_edge_place_t)0) #define GRAPH_INFO_PLACE_NONE ((graph_info_place_t)0) #define GRAPH_VERTEX_PLACE_NONE ((graph_vertex_place_t)0) @@ -713,8 +712,8 @@ typedef struct irix5_inventory_s { } irix5_inventory_t; typedef struct invplace_s { - devfs_handle_t invplace_vhdl; /* current vertex */ - devfs_handle_t invplace_vplace; /* place in vertex list */ + vertex_hdl_t invplace_vhdl; /* current vertex */ + vertex_hdl_t invplace_vplace; /* place in vertex list */ inventory_t *invplace_inv; /* place in inv list on vertex */ } invplace_t; /* Magic cookie placeholder in inventory list */ @@ -730,7 +729,7 @@ extern inventory_t *find_inventory(inventory_t *, int, int, int, int, int); extern int scaninvent(int (*)(inventory_t *, void *), void *); extern int get_sizeof_inventory(int); -extern void device_inventory_add( devfs_handle_t device, +extern void device_inventory_add( vertex_hdl_t device, int class, int type, major_t ctlr, @@ -738,11 +737,11 @@ extern void device_inventory_add( devfs_handle_t device, int state); -extern inventory_t *device_inventory_get_next( devfs_handle_t device, +extern inventory_t *device_inventory_get_next( vertex_hdl_t device, invplace_t *); -extern void device_controller_num_set( devfs_handle_t, +extern void device_controller_num_set( vertex_hdl_t, int); -extern int device_controller_num_get( devfs_handle_t); +extern int device_controller_num_get( vertex_hdl_t); #endif /* __KERNEL__ */ #endif /* _ASM_IA64_SN_INVENT_H */ diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h index 6d1f8668a161a..2aee7cf8cbc55 100644 --- a/include/asm-ia64/sn/io.h +++ b/include/asm-ia64/sn/io.h @@ -56,27 +56,8 @@ (_x) : \ (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) -#if defined(CONFIG_IA64_SGI_SN1) -#include <asm/sn/sn1/bedrock.h> -#include <asm/sn/sn1/hubio.h> -#include <asm/sn/sn1/hubio_next.h> -#include <asm/sn/sn1/hubmd.h> -#include <asm/sn/sn1/hubmd_next.h> -#include <asm/sn/sn1/hubpi.h> -#include <asm/sn/sn1/hubpi_next.h> -#include <asm/sn/sn1/hublb.h> -#include <asm/sn/sn1/hublb_next.h> -#include <asm/sn/sn1/hubni.h> -#include <asm/sn/sn1/hubni_next.h> -#include <asm/sn/sn1/hubxb.h> -#include <asm/sn/sn1/hubxb_next.h> -#include <asm/sn/sn1/hubstat.h> -#include <asm/sn/sn1/hubdev.h> -#include <asm/sn/sn1/synergy.h> -#elif defined(CONFIG_IA64_SGI_SN2) #include <asm/sn/sn2/shub.h> #include <asm/sn/sn2/shubio.h> -#endif /* * Used to ensure write ordering (like mb(), but for I/O space) diff --git a/include/asm-ia64/sn/ioc3.h b/include/asm-ia64/sn/ioc3.h index 26afbf127cdfe..379b632eb1d40 100644 --- a/include/asm-ia64/sn/ioc3.h +++ b/include/asm-ia64/sn/ioc3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2002 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (c) 2002-2003 Silicon Graphics, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License diff --git a/include/asm-ia64/sn/ioc4.h b/include/asm-ia64/sn/ioc4.h new file mode 100644 index 0000000000000..7df3cea7e149f --- /dev/null +++ b/include/asm-ia64/sn/ioc4.h @@ -0,0 +1,801 @@ +/* + * Copyright (c) 2002-2003 Silicon Graphics, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: + * + * http://www.sgi.com + * + */ + +#ifndef _ASM_IA64_SN_IOC4_H +#define _ASM_IA64_SN_IOC4_H + +#if 0 + +/* + * ioc4.h - IOC4 chip header file + */ + +/* Notes: + * The IOC4 chip is a 32-bit PCI device that provides 4 serial ports, + * an IDE bus interface, a PC keyboard/mouse interface, and a real-time + * external interrupt interface. + * + * It includes an optimized DMA buffer management, and a store-and-forward + * buffer RAM. + * + * All IOC4 registers are 32 bits wide. + */ +typedef __uint32_t ioc4reg_t; + +/* + * PCI Configuration Space Register Address Map, use offset from IOC4 PCI + * configuration base such that this can be used for multiple IOC4s + */ +#define IOC4_PCI_ID 0x0 /* ID */ + +#define IOC4_VENDOR_ID_NUM 0x10A9 +#define IOC4_DEVICE_ID_NUM 0x100A +#define IOC4_ADDRSPACE_MASK 0xfff00000ULL + +#define IOC4_PCI_SCR 0x4 /* Status/Command */ +#define IOC4_PCI_REV 0x8 /* Revision */ +#define IOC4_PCI_LAT 0xC /* Latency Timer */ +#define IOC4_PCI_BAR0 0x10 /* IOC4 base address 0 */ +#define IOC4_PCI_SIDV 0x2c /* Subsys ID and vendor */ +#define IOC4_PCI_CAP 0x34 /* Capability pointer */ +#define IOC4_PCI_LATGNTINT 0x3c /* Max_lat, min_gnt, int_pin, int_line */ + +/* + * PCI Memory Space Map + */ +#define IOC4_PCI_ERR_ADDR_L 0x000 /* Low Error Address */ +#define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0) +#define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1) +#define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5) +#define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6) + +/* Master IDs contained in PCI_ERR_ADDR_MST_ID_MSK */ +#define IOC4_MST_ID_S0_TX 0 +#define IOC4_MST_ID_S0_RX 1 +#define IOC4_MST_ID_S1_TX 2 +#define IOC4_MST_ID_S1_RX 3 +#define IOC4_MST_ID_S2_TX 4 +#define IOC4_MST_ID_S2_RX 5 +#define IOC4_MST_ID_S3_TX 6 +#define IOC4_MST_ID_S3_RX 7 +#define IOC4_MST_ID_ATA 8 + +#define IOC4_PCI_ERR_ADDR_H 0x004 /* High Error Address */ + +#define IOC4_SIO_IR 0x008 /* SIO Interrupt Register */ +#define IOC4_OTHER_IR 0x00C /* Other Interrupt Register */ + +/* These registers are read-only for general kernel code. To modify + * them use the functions in ioc4.c + */ +#define IOC4_SIO_IES_RO 0x010 /* SIO Interrupt Enable Set Reg */ +#define IOC4_OTHER_IES_RO 0x014 /* Other Interrupt Enable Set Reg */ +#define IOC4_SIO_IEC_RO 0x018 /* SIO Interrupt Enable Clear Reg */ +#define IOC4_OTHER_IEC_RO 0x01C /* Other Interrupt Enable Clear Reg */ + +#define IOC4_SIO_CR 0x020 /* SIO Control Reg */ +#define IOC4_INT_OUT 0x028 /* INT_OUT Reg (realtime interrupt) */ +#define IOC4_GPCR_S 0x030 /* GenericPIO Cntrl Set Register */ +#define IOC4_GPCR_C 0x034 /* GenericPIO Cntrl Clear Register */ +#define IOC4_GPDR 0x038 /* GenericPIO Data Register */ +#define IOC4_GPPR_0 0x040 /* GenericPIO Pin Registers */ +#define IOC4_GPPR_OFF 0x4 +#define IOC4_GPPR(x) (IOC4_GPPR_0+(x)*IOC4_GPPR_OFF) + +/* ATAPI Registers */ +#define IOC4_ATA_0 0x100 /* Data w/timing */ +#define IOC4_ATA_1 0x104 /* Error/Features w/timing */ +#define IOC4_ATA_2 0x108 /* Sector Count w/timing */ +#define IOC4_ATA_3 0x10C /* Sector Number w/timing */ +#define IOC4_ATA_4 0x110 /* Cyliner Low w/timing */ +#define IOC4_ATA_5 0x114 /* Cylinder High w/timing */ +#define IOC4_ATA_6 0x118 /* Device/Head w/timing */ +#define IOC4_ATA_7 0x11C /* Status/Command w/timing */ +#define IOC4_ATA_0_AUX 0x120 /* Aux Status/Device Cntrl w/timing */ +#define IOC4_ATA_TIMING 0x140 /* Timing value register 0 */ +#define IOC4_ATA_DMA_PTR_L 0x144 /* Low Memory Pointer to DMA List */ +#define IOC4_ATA_DMA_PTR_H 0x148 /* High Memory Pointer to DMA List */ +#define IOC4_ATA_DMA_ADDR_L 0x14C /* Low Memory DMA Address */ +#define IOC4_ATA_DMA_ADDR_H 0x150 /* High Memory DMA Addresss */ +#define IOC4_ATA_BC_DEV 0x154 /* DMA Byte Count at Device */ +#define IOC4_ATA_BC_MEM 0x158 /* DMA Byte Count at Memory */ +#define IOC4_ATA_DMA_CTRL 0x15C /* DMA Control/Status */ + +/* Keyboard and Mouse Registers */ +#define IOC4_KM_CSR 0x200 /* Kbd and Mouse Cntrl/Status Reg */ +#define IOC4_K_RD 0x204 /* Kbd Read Data Register */ +#define IOC4_M_RD 0x208 /* Mouse Read Data Register */ +#define IOC4_K_WD 0x20C /* Kbd Write Data Register */ +#define IOC4_M_WD 0x210 /* Mouse Write Data Register */ + +/* Serial Port Registers used for DMA mode serial I/O */ +#define IOC4_SBBR01_H 0x300 /* Serial Port Ring Buffers + Base Reg High for Channels 0 1*/ +#define IOC4_SBBR01_L 0x304 /* Serial Port Ring Buffers + Base Reg Low for Channels 0 1 */ +#define IOC4_SBBR23_H 0x308 /* Serial Port Ring Buffers + Base Reg High for Channels 2 3*/ +#define IOC4_SBBR23_L 0x30C /* Serial Port Ring Buffers + Base Reg Low for Channels 2 3 */ + +#define IOC4_SSCR_0 0x310 /* Serial Port 0 Control */ +#define IOC4_STPIR_0 0x314 /* Serial Port 0 TX Produce */ +#define IOC4_STCIR_0 0x318 /* Serial Port 0 TX Consume */ +#define IOC4_SRPIR_0 0x31C /* Serial Port 0 RX Produce */ +#define IOC4_SRCIR_0 0x320 /* Serial Port 0 RX Consume */ +#define IOC4_SRTR_0 0x324 /* Serial Port 0 Receive Timer Reg */ +#define IOC4_SHADOW_0 0x328 /* Serial Port 0 16550 Shadow Reg */ + +#define IOC4_SSCR_1 0x32C /* Serial Port 1 Control */ +#define IOC4_STPIR_1 0x330 /* Serial Port 1 TX Produce */ +#define IOC4_STCIR_1 0x334 /* Serial Port 1 TX Consume */ +#define IOC4_SRPIR_1 0x338 /* Serial Port 1 RX Produce */ +#define IOC4_SRCIR_1 0x33C /* Serial Port 1 RX Consume */ +#define IOC4_SRTR_1 0x340 /* Serial Port 1 Receive Timer Reg */ +#define IOC4_SHADOW_1 0x344 /* Serial Port 1 16550 Shadow Reg */ + +#define IOC4_SSCR_2 0x348 /* Serial Port 2 Control */ +#define IOC4_STPIR_2 0x34C /* Serial Port 2 TX Produce */ +#define IOC4_STCIR_2 0x350 /* Serial Port 2 TX Consume */ +#define IOC4_SRPIR_2 0x354 /* Serial Port 2 RX Produce */ +#define IOC4_SRCIR_2 0x358 /* Serial Port 2 RX Consume */ +#define IOC4_SRTR_2 0x35C /* Serial Port 2 Receive Timer Reg */ +#define IOC4_SHADOW_2 0x360 /* Serial Port 2 16550 Shadow Reg */ + +#define IOC4_SSCR_3 0x364 /* Serial Port 3 Control */ +#define IOC4_STPIR_3 0x368 /* Serial Port 3 TX Produce */ +#define IOC4_STCIR_3 0x36C /* Serial Port 3 TX Consume */ +#define IOC4_SRPIR_3 0x370 /* Serial Port 3 RX Produce */ +#define IOC4_SRCIR_3 0x374 /* Serial Port 3 RX Consume */ +#define IOC4_SRTR_3 0x378 /* Serial Port 3 Receive Timer Reg */ +#define IOC4_SHADOW_3 0x37C /* Serial Port 3 16550 Shadow Reg */ + +#define IOC4_UART0_BASE 0x380 /* UART 0 */ +#define IOC4_UART1_BASE 0x388 /* UART 1 */ +#define IOC4_UART2_BASE 0x390 /* UART 2 */ +#define IOC4_UART3_BASE 0x398 /* UART 3 */ + +/* Private page address aliases for usermode mapping */ +#define IOC4_INT_OUT_P 0x04000 /* INT_OUT Reg */ + +#define IOC4_SSCR_0_P 0x08000 /* Serial Port 0 */ +#define IOC4_STPIR_0_P 0x08004 +#define IOC4_STCIR_0_P 0x08008 /* (read-only) */ +#define IOC4_SRPIR_0_P 0x0800C /* (read-only) */ +#define IOC4_SRCIR_0_P 0x08010 +#define IOC4_SRTR_0_P 0x08014 +#define IOC4_UART_LSMSMCR_0_P 0x08018 /* (read-only) */ + +#define IOC4_SSCR_1_P 0x0C000 /* Serial Port 1 */ +#define IOC4_STPIR_1_P 0x0C004 +#define IOC4_STCIR_1_P 0x0C008 /* (read-only) */ +#define IOC4_SRPIR_1_P 0x0C00C /* (read-only) */ +#define IOC4_SRCIR_1_P 0x0C010 +#define IOC4_SRTR_1_P 0x0C014 +#define IOC4_UART_LSMSMCR_1_P 0x0C018 /* (read-only) */ + +#define IOC4_SSCR_2_P 0x10000 /* Serial Port 2 */ +#define IOC4_STPIR_2_P 0x10004 +#define IOC4_STCIR_2_P 0x10008 /* (read-only) */ +#define IOC4_SRPIR_2_P 0x1000C /* (read-only) */ +#define IOC4_SRCIR_2_P 0x10010 +#define IOC4_SRTR_2_P 0x10014 +#define IOC4_UART_LSMSMCR_2_P 0x10018 /* (read-only) */ + +#define IOC4_SSCR_3_P 0x14000 /* Serial Port 3 */ +#define IOC4_STPIR_3_P 0x14004 +#define IOC4_STCIR_3_P 0x14008 /* (read-only) */ +#define IOC4_SRPIR_3_P 0x1400C /* (read-only) */ +#define IOC4_SRCIR_3_P 0x14010 +#define IOC4_SRTR_3_P 0x14014 +#define IOC4_UART_LSMSMCR_3_P 0x14018 /* (read-only) */ + +#define IOC4_ALIAS_PAGE_SIZE 0x4000 + +/* Interrupt types */ +typedef enum ioc4_intr_type_e { + ioc4_sio_intr_type, + ioc4_other_intr_type, + ioc4_num_intr_types +} ioc4_intr_type_t; +#define ioc4_first_intr_type ioc4_sio_intr_type + +/* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES */ +#define IOC4_SIO_IR_S0_TX_MT 0x00000001 /* Serial port 0 TX empty */ +#define IOC4_SIO_IR_S0_RX_FULL 0x00000002 /* Port 0 RX buf full */ +#define IOC4_SIO_IR_S0_RX_HIGH 0x00000004 /* Port 0 RX hiwat */ +#define IOC4_SIO_IR_S0_RX_TIMER 0x00000008 /* Port 0 RX timeout */ +#define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010 /* Port 0 delta DCD */ +#define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020 /* Port 0 delta CTS */ +#define IOC4_SIO_IR_S0_INT 0x00000040 /* Port 0 pass-thru intr */ +#define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080 /* Port 0 explicit TX thru */ +#define IOC4_SIO_IR_S1_TX_MT 0x00000100 /* Serial port 1 */ +#define IOC4_SIO_IR_S1_RX_FULL 0x00000200 /* */ +#define IOC4_SIO_IR_S1_RX_HIGH 0x00000400 /* */ +#define IOC4_SIO_IR_S1_RX_TIMER 0x00000800 /* */ +#define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000 /* */ +#define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000 /* */ +#define IOC4_SIO_IR_S1_INT 0x00004000 /* */ +#define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000 /* */ +#define IOC4_SIO_IR_S2_TX_MT 0x00010000 /* Serial port 2 */ +#define IOC4_SIO_IR_S2_RX_FULL 0x00020000 /* */ +#define IOC4_SIO_IR_S2_RX_HIGH 0x00040000 /* */ +#define IOC4_SIO_IR_S2_RX_TIMER 0x00080000 /* */ +#define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000 /* */ +#define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000 /* */ +#define IOC4_SIO_IR_S2_INT 0x00400000 /* */ +#define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000 /* */ +#define IOC4_SIO_IR_S3_TX_MT 0x01000000 /* Serial port 3 */ +#define IOC4_SIO_IR_S3_RX_FULL 0x02000000 /* */ +#define IOC4_SIO_IR_S3_RX_HIGH 0x04000000 /* */ +#define IOC4_SIO_IR_S3_RX_TIMER 0x08000000 /* */ +#define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000 /* */ +#define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000 /* */ +#define IOC4_SIO_IR_S3_INT 0x40000000 /* */ +#define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000 /* */ + +/* Per device interrupt masks */ +#define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \ + IOC4_SIO_IR_S0_RX_FULL | \ + IOC4_SIO_IR_S0_RX_HIGH | \ + IOC4_SIO_IR_S0_RX_TIMER | \ + IOC4_SIO_IR_S0_DELTA_DCD | \ + IOC4_SIO_IR_S0_DELTA_CTS | \ + IOC4_SIO_IR_S0_INT | \ + IOC4_SIO_IR_S0_TX_EXPLICIT) +#define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \ + IOC4_SIO_IR_S1_RX_FULL | \ + IOC4_SIO_IR_S1_RX_HIGH | \ + IOC4_SIO_IR_S1_RX_TIMER | \ + IOC4_SIO_IR_S1_DELTA_DCD | \ + IOC4_SIO_IR_S1_DELTA_CTS | \ + IOC4_SIO_IR_S1_INT | \ + IOC4_SIO_IR_S1_TX_EXPLICIT) +#define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \ + IOC4_SIO_IR_S2_RX_FULL | \ + IOC4_SIO_IR_S2_RX_HIGH | \ + IOC4_SIO_IR_S2_RX_TIMER | \ + IOC4_SIO_IR_S2_DELTA_DCD | \ + IOC4_SIO_IR_S2_DELTA_CTS | \ + IOC4_SIO_IR_S2_INT | \ + IOC4_SIO_IR_S2_TX_EXPLICIT) +#define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \ + IOC4_SIO_IR_S3_RX_FULL | \ + IOC4_SIO_IR_S3_RX_HIGH | \ + IOC4_SIO_IR_S3_RX_TIMER | \ + IOC4_SIO_IR_S3_DELTA_DCD | \ + IOC4_SIO_IR_S3_DELTA_CTS | \ + IOC4_SIO_IR_S3_INT | \ + IOC4_SIO_IR_S3_TX_EXPLICIT) + +/* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES */ +#define IOC4_OTHER_IR_ATA_INT 0x00000001 /* ATAPI intr pass-thru */ +#define IOC4_OTHER_IR_ATA_MEMERR 0x00000002 /* ATAPI DMA PCI error */ +#define IOC4_OTHER_IR_S0_MEMERR 0x00000004 /* Port 0 PCI error */ +#define IOC4_OTHER_IR_S1_MEMERR 0x00000008 /* Port 1 PCI error */ +#define IOC4_OTHER_IR_S2_MEMERR 0x00000010 /* Port 2 PCI error */ +#define IOC4_OTHER_IR_S3_MEMERR 0x00000020 /* Port 3 PCI error */ +#define IOC4_OTHER_IR_KBD_INT 0x00000040 /* Kbd/mouse intr */ +#define IOC4_OTHER_IR_ATA_DMAINT 0x00000089 /* ATAPI DMA intr */ +#define IOC4_OTHER_IR_RT_INT 0x00800000 /* RT output pulse */ +#define IOC4_OTHER_IR_GEN_INT1 0x02000000 /* RT input pulse */ +#define IOC4_OTHER_IR_GEN_INT_SHIFT 25 + +/* Per device interrupt masks */ +#define IOC4_OTHER_IR_ATA (IOC4_OTHER_IR_ATA_INT | \ + IOC4_OTHER_IR_ATA_MEMERR | \ + IOC4_OTHER_IR_ATA_DMAINT) +#define IOC4_OTHER_IR_RT (IOC4_OTHER_IR_RT_INT | IOC4_OTHER_IR_GEN_INT1) + +/* Macro to load pending interrupts */ +#define IOC4_PENDING_SIO_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \ + PCI_INW(&((mem)->sio_ies_ro))) +#define IOC4_PENDING_OTHER_INTRS(mem) (PCI_INW(&((mem)->other_ir)) & \ + PCI_INW(&((mem)->other_ies_ro))) + +/* Bitmasks for IOC4_SIO_CR */ +#define IOC4_SIO_SR_CMD_PULSE 0x00000004 /* Byte bus strobe length */ +#define IOC4_SIO_CR_CMD_PULSE_SHIFT 0 +#define IOC4_SIO_CR_ARB_DIAG 0x00000070 /* Current non-ATA PCI bus + requester (ro) */ +#define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000 +#define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010 +#define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020 +#define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030 +#define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040 +#define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050 +#define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060 +#define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070 +#define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080 /* 0 -> active request among + serial ports (ro) */ +#define IOC4_SIO_CR_ATA_DIAG_IDLE 0x00000100 /* 0 -> active request from + ATA port */ +#define IOC4_SIO_CR_ATA_DIAG_ACTIVE 0x00000200 /* 1 -> ATA request is winner */ + +/* Bitmasks for IOC4_INT_OUT */ +#define IOC4_INT_OUT_COUNT 0x0000ffff /* Pulse interval timer */ +#define IOC4_INT_OUT_MODE 0x00070000 /* Mode mask */ +#define IOC4_INT_OUT_MODE_0 0x00000000 /* Set output to 0 */ +#define IOC4_INT_OUT_MODE_1 0x00040000 /* Set output to 1 */ +#define IOC4_INT_OUT_MODE_1PULSE 0x00050000 /* Send 1 pulse */ +#define IOC4_INT_OUT_MODE_PULSES 0x00060000 /* Send 1 pulse every interval */ +#define IOC4_INT_OUT_MODE_SQW 0x00070000 /* Toggle output every interval */ +#define IOC4_INT_OUT_DIAG 0x40000000 /* Diag mode */ +#define IOC4_INT_OUT_INT_OUT 0x80000000 /* Current state of INT_OUT */ + +/* Time constants for IOC4_INT_OUT */ +#define IOC4_INT_OUT_NS_PER_TICK (15 * 520) /* 15 ns PCI clock, multi=520 */ +#define IOC4_INT_OUT_TICKS_PER_PULSE 3 /* Outgoing pulse lasts 3 + ticks */ +#define IOC4_INT_OUT_US_TO_COUNT(x) /* Convert uS to a count value */ \ + (((x) * 10 + IOC4_INT_OUT_NS_PER_TICK / 200) * \ + 100 / IOC4_INT_OUT_NS_PER_TICK - 1) +#define IOC4_INT_OUT_COUNT_TO_US(x) /* Convert count value to uS */ \ + (((x) + 1) * IOC4_INT_OUT_NS_PER_TICK / 1000) +#define IOC4_INT_OUT_MIN_TICKS 3 /* Min period is width of + pulse in "ticks" */ +#define IOC4_INT_OUT_MAX_TICKS IOC4_INT_OUT_COUNT /* Largest possible count */ + +/* Bitmasks for IOC4_GPCR */ +#define IOC4_GPCR_DIR 0x000000ff /* Tristate pin in or out */ +#define IOC4_GPCR_DIR_PIN(x) (1<<(x)) /* Access one of the DIR bits */ +#define IOC4_GPCR_EDGE 0x0000ff00 /* Extint edge or level + sensitive */ +#define IOC4_GPCR_EDGE_PIN(x) (1<<((x)+7 )) /* Access one of the EDGE bits */ + +/* Values for IOC4_GPCR */ +#define IOC4_GPCR_INT_OUT_EN 0x00100000 /* Enable INT_OUT to pin 0 */ +#define IOC4_GPCR_DIR_SER0_XCVR 0x00000010 /* Port 0 Transceiver select + enable */ +#define IOC4_GPCR_DIR_SER1_XCVR 0x00000020 /* Port 1 Transceiver select + enable */ +#define IOC4_GPCR_DIR_SER2_XCVR 0x00000040 /* Port 2 Transceiver select + enable */ +#define IOC4_GPCR_DIR_SER3_XCVR 0x00000080 /* Port 3 Transceiver select + enable */ + +/* Defs for some of the generic I/O pins */ +#define IOC4_GPCR_UART0_MODESEL 0x10 /* Pin is output to port 0 + mode sel */ +#define IOC4_GPCR_UART1_MODESEL 0x20 /* Pin is output to port 1 + mode sel */ +#define IOC4_GPCR_UART2_MODESEL 0x40 /* Pin is output to port 2 + mode sel */ +#define IOC4_GPCR_UART3_MODESEL 0x80 /* Pin is output to port 3 + mode sel */ + +#define IOC4_GPPR_UART0_MODESEL_PIN 4 /* GIO pin controlling + uart 0 mode select */ +#define IOC4_GPPR_UART1_MODESEL_PIN 5 /* GIO pin controlling + uart 1 mode select */ +#define IOC4_GPPR_UART2_MODESEL_PIN 6 /* GIO pin controlling + uart 2 mode select */ +#define IOC4_GPPR_UART3_MODESEL_PIN 7 /* GIO pin controlling + uart 3 mode select */ + +/* Bitmasks for IOC4_ATA_TIMING */ +#define IOC4_ATA_TIMING_ADR_SETUP 0x00000003 /* Clocks of addr set-up */ +#define IOC4_ATA_TIMING_PULSE_WIDTH 0x000001f8 /* Clocks of read or write + pulse width */ +#define IOC4_ATA_TIMING_RECOVERY 0x0000fe00 /* Clocks before next read + or write */ +#define IOC4_ATA_TIMING_USE_IORDY 0x00010000 /* PIO uses IORDY */ + +/* Bitmasks for address list elements pointed to by IOC4_ATA_DMA_PTR_<L|H> */ +#define IOC4_ATA_ALE_DMA_ADDRESS 0xfffffffffffffffe + +/* Bitmasks for byte count list elements pointed to by IOC4_ATA_DMA_PTR_<L|H> */ +#define IOC4_ATA_BCLE_BYTE_COUNT 0x000000000000fffe +#define IOC4_ATA_BCLE_LIST_END 0x0000000080000000 + +/* Bitmasks for IOC4_ATA_BC_<DEV|MEM> */ +#define IOC4_ATA_BC_BYTE_CNT 0x0001fffe /* Byte count */ + +/* Bitmasks for IOC4_ATA_DMA_CTRL */ +#define IOC4_ATA_DMA_CTRL_STRAT 0x00000001 /* 1 -> start DMA engine */ +#define IOC4_ATA_DMA_CTRL_STOP 0x00000002 /* 1 -> stop DMA engine */ +#define IOC4_ATA_DMA_CTRL_DIR 0x00000004 /* 1 -> ATA bus data copied + to memory */ +#define IOC4_ATA_DMA_CTRL_ACTIVE 0x00000008 /* DMA channel is active */ +#define IOC4_ATA_DMA_CTRL_MEM_ERROR 0x00000010 /* DMA engine encountered + a PCI error */ +/* Bitmasks for IOC4_KM_CSR */ +#define IOC4_KM_CSR_K_WRT_PEND 0x00000001 /* Kbd port xmitting or resetting */ +#define IOC4_KM_CSR_M_WRT_PEND 0x00000002 /* Mouse port xmitting or resetting */ +#define IOC4_KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */ +#define IOC4_KM_CSR_M_LCB 0x00000008 /* Same for mouse */ +#define IOC4_KM_CSR_K_DATA 0x00000010 /* State of kbd data line */ +#define IOC4_KM_CSR_K_CLK 0x00000020 /* State of kbd clock line */ +#define IOC4_KM_CSR_K_PULL_DATA 0x00000040 /* Pull kbd data line low */ +#define IOC4_KM_CSR_K_PULL_CLK 0x00000080 /* Pull kbd clock line low */ +#define IOC4_KM_CSR_M_DATA 0x00000100 /* State of mouse data line */ +#define IOC4_KM_CSR_M_CLK 0x00000200 /* State of mouse clock line */ +#define IOC4_KM_CSR_M_PULL_DATA 0x00000400 /* Pull mouse data line low */ +#define IOC4_KM_CSR_M_PULL_CLK 0x00000800 /* Pull mouse clock line low */ +#define IOC4_KM_CSR_EMM_MODE 0x00001000 /* Emulation mode */ +#define IOC4_KM_CSR_SIM_MODE 0x00002000 /* Clock X8 */ +#define IOC4_KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */ +#define IOC4_KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */ +#define IOC4_KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */ +#define IOC4_KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */ +#define IOC4_KM_CSR_K_TO_EN 0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN = + cause SIO_IR to assert */ +#define IOC4_KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = + cause SIO_IR to assert */ +#define IOC4_KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */ +#define IOC4_KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */ +#define IOC4_KM_CSR_K_CLAMP_THREE \ + 0x00400000 /* Pull K_CLK low after rec. three chars */ +#define IOC4_KM_CSR_M_CLAMP_THREE \ + 0x00800000 /* Pull M_CLK low after rec. three char */ + +/* Bitmasks for IOC4_K_RD and IOC4_M_RD */ +#define IOC4_KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */ +#define IOC4_KM_RD_DATA_2_SHIFT 0 +#define IOC4_KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */ +#define IOC4_KM_RD_DATA_1_SHIFT 8 +#define IOC4_KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */ +#define IOC4_KM_RD_DATA_0_SHIFT 16 +#define IOC4_KM_RD_FRAME_ERR_2 0x01000000 /* Framing or parity error in byte 2 */ +#define IOC4_KM_RD_FRAME_ERR_1 0x02000000 /* Same for byte 1 */ +#define IOC4_KM_RD_FRAME_ERR_0 0x04000000 /* Same for byte 0 */ + +#define IOC4_KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */ +#define IOC4_KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */ +#define IOC4_KM_RD_VALID_2 0x20000000 /* DATA_2 valid */ +#define IOC4_KM_RD_VALID_1 0x40000000 /* DATA_1 valid */ +#define IOC4_KM_RD_VALID_0 0x80000000 /* DATA_0 valid */ +#define IOC4_KM_RD_VALID_ALL (IOC4_KM_RD_VALID_0 | IOC4_KM_RD_VALID_1 | \ + IOC4_KM_RD_VALID_2) + +/* Bitmasks for IOC4_K_WD & IOC4_M_WD */ +#define IOC4_KM_WD_WRT_DATA 0x000000ff /* Write to keyboard/mouse port */ +#define IOC4_KM_WD_WRT_DATA_SHIFT 0 + +/* Bitmasks for serial RX status byte */ +#define IOC4_RXSB_OVERRUN 0x01 /* Char(s) lost */ +#define IOC4_RXSB_PAR_ERR 0x02 /* Parity error */ +#define IOC4_RXSB_FRAME_ERR 0x04 /* Framing error */ +#define IOC4_RXSB_BREAK 0x08 /* Break character */ +#define IOC4_RXSB_CTS 0x10 /* State of CTS */ +#define IOC4_RXSB_DCD 0x20 /* State of DCD */ +#define IOC4_RXSB_MODEM_VALID 0x40 /* DCD, CTS, and OVERRUN are valid */ +#define IOC4_RXSB_DATA_VALID 0x80 /* Data byte, FRAME_ERR PAR_ERR & BREAK valid */ + +/* Bitmasks for serial TX control byte */ +#define IOC4_TXCB_INT_WHEN_DONE 0x20 /* Interrupt after this byte is sent */ +#define IOC4_TXCB_INVALID 0x00 /* Byte is invalid */ +#define IOC4_TXCB_VALID 0x40 /* Byte is valid */ +#define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control register */ +#define IOC4_TXCB_DELAY 0xc0 /* Delay data<7:0> mSec */ + +/* Bitmasks for IOC4_SBBR_L */ +#define IOC4_SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */ +#define IOC4_SBBR_L_BASE 0xfffff000 /* Lower serial ring base addr */ + +/* Bitmasks for IOC4_SSCR_<3:0> */ +#define IOC4_SSCR_RX_THRESHOLD 0x000001ff /* Hiwater mark */ +#define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */ +#define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */ +#define IOC4_SSCR_RX_RING_DCD 0x00040000 /* Post RX record on delta-DCD */ +#define IOC4_SSCR_RX_RING_CTS 0x00080000 /* Post RX record on delta-CTS */ +#define IOC4_SSCR_DIAG 0x00200000 /* Bypass clock divider for sim */ +#define IOC4_SSCR_RX_DRAIN 0x08000000 /* Drain RX buffer to memory */ +#define IOC4_SSCR_DMA_EN 0x10000000 /* Enable ring buffer DMA */ +#define IOC4_SSCR_DMA_PAUSE 0x20000000 /* Pause DMA */ +#define IOC4_SSCR_PAUSE_STATE 0x40000000 /* Sets when PAUSE takes effect */ +#define IOC4_SSCR_RESET 0x80000000 /* Reset DMA channels */ + +/* All producer/comsumer pointers are the same bitfield */ +#define IOC4_PROD_CONS_PTR_4K 0x00000ff8 /* For 4K buffers */ +#define IOC4_PROD_CONS_PTR_1K 0x000003f8 /* For 1K buffers */ +#define IOC4_PROD_CONS_PTR_OFF 3 + +/* Bitmasks for IOC4_STPIR_<3:0> */ +/* Reserved for future register definitions */ + +/* Bitmasks for IOC4_STCIR_<3:0> */ +#define IOC4_STCIR_BYTE_CNT 0x0f000000 /* Bytes in unpacker */ +#define IOC4_STCIR_BYTE_CNT_SHIFT 24 + +/* Bitmasks for IOC4_SRPIR_<3:0> */ +#define IOC4_SRPIR_BYTE_CNT 0x0f000000 /* Bytes in packer */ +#define IOC4_SRPIR_BYTE_CNT_SHIFT 24 + +/* Bitmasks for IOC4_SRCIR_<3:0> */ +#define IOC4_SRCIR_ARM 0x80000000 /* Arm RX timer */ + +/* Bitmasks for IOC4_SHADOW_<3:0> */ +#define IOC4_SHADOW_DR 0x00000001 /* Data ready */ +#define IOC4_SHADOW_OE 0x00000002 /* Overrun error */ +#define IOC4_SHADOW_PE 0x00000004 /* Parity error */ +#define IOC4_SHADOW_FE 0x00000008 /* Framing error */ +#define IOC4_SHADOW_BI 0x00000010 /* Break interrupt */ +#define IOC4_SHADOW_THRE 0x00000020 /* Xmit holding register empty */ +#define IOC4_SHADOW_TEMT 0x00000040 /* Xmit shift register empty */ +#define IOC4_SHADOW_RFCE 0x00000080 /* Char in RX fifo has an error */ +#define IOC4_SHADOW_DCTS 0x00010000 /* Delta clear to send */ +#define IOC4_SHADOW_DDCD 0x00080000 /* Delta data carrier detect */ +#define IOC4_SHADOW_CTS 0x00100000 /* Clear to send */ +#define IOC4_SHADOW_DCD 0x00800000 /* Data carrier detect */ +#define IOC4_SHADOW_DTR 0x01000000 /* Data terminal ready */ +#define IOC4_SHADOW_RTS 0x02000000 /* Request to send */ +#define IOC4_SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */ +#define IOC4_SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */ +#define IOC4_SHADOW_LOOP 0x10000000 /* Loopback enabled */ + +/* Bitmasks for IOC4_SRTR_<3:0> */ +#define IOC4_SRTR_CNT 0x00000fff /* Reload value for RX timer */ +#define IOC4_SRTR_CNT_VAL 0x0fff0000 /* Current value of RX timer */ +#define IOC4_SRTR_CNT_VAL_SHIFT 16 +#define IOC4_SRTR_HZ 16000 /* SRTR clock frequency */ + +/* Serial port register map used for DMA and PIO serial I/O */ +typedef volatile struct ioc4_serialregs { + ioc4reg_t sscr; + ioc4reg_t stpir; + ioc4reg_t stcir; + ioc4reg_t srpir; + ioc4reg_t srcir; + ioc4reg_t srtr; + ioc4reg_t shadow; +} ioc4_sregs_t; + +/* IOC4 UART register map */ +typedef volatile struct ioc4_uartregs { + union { + char rbr; /* read only, DLAB == 0 */ + char thr; /* write only, DLAB == 0 */ + char dll; /* DLAB == 1 */ + } u1; + union { + char ier; /* DLAB == 0 */ + char dlm; /* DLAB == 1 */ + } u2; + union { + char iir; /* read only */ + char fcr; /* write only */ + } u3; + char i4u_lcr; + char i4u_mcr; + char i4u_lsr; + char i4u_msr; + char i4u_scr; +} ioc4_uart_t; + +#define i4u_rbr u1.rbr +#define i4u_thr u1.thr +#define i4u_dll u1.dll +#define i4u_ier u2.ier +#define i4u_dlm u2.dlm +#define i4u_iir u3.iir +#define i4u_fcr u3.fcr + +/* PCI config space register map */ +typedef volatile struct ioc4_configregs { + ioc4reg_t pci_id; + ioc4reg_t pci_scr; + ioc4reg_t pci_rev; + ioc4reg_t pci_lat; + ioc4reg_t pci_bar0; + ioc4reg_t pci_bar1; + ioc4reg_t pci_bar2_not_implemented; + ioc4reg_t pci_cis_ptr_not_implemented; + ioc4reg_t pci_sidv; + ioc4reg_t pci_rom_bar_not_implemented; + ioc4reg_t pci_cap; + ioc4reg_t pci_rsv; + ioc4reg_t pci_latgntint; + + char pci_fill1[0x58 - 0x3c - 4]; + + ioc4reg_t pci_pcix; + ioc4reg_t pci_pcixstatus; +} ioc4_cfg_t; + +/* PCI memory space register map addressed using pci_bar0 */ +typedef volatile struct ioc4_memregs { + + /* Miscellaneous IOC4 registers */ + ioc4reg_t pci_err_addr_l; + ioc4reg_t pci_err_addr_h; + ioc4reg_t sio_ir; + ioc4reg_t other_ir; + + /* These registers are read-only for general kernel code. To + * modify them use the functions in ioc4.c. + */ + ioc4reg_t sio_ies_ro; + ioc4reg_t other_ies_ro; + ioc4reg_t sio_iec_ro; + ioc4reg_t other_iec_ro; + ioc4reg_t sio_cr; + ioc4reg_t misc_fill1; + ioc4reg_t int_out; + ioc4reg_t misc_fill2; + ioc4reg_t gpcr_s; + ioc4reg_t gpcr_c; + ioc4reg_t gpdr; + ioc4reg_t misc_fill3; + ioc4reg_t gppr_0; + ioc4reg_t gppr_1; + ioc4reg_t gppr_2; + ioc4reg_t gppr_3; + ioc4reg_t gppr_4; + ioc4reg_t gppr_5; + ioc4reg_t gppr_6; + ioc4reg_t gppr_7; + + char misc_fill4[0x100 - 0x5C - 4]; + + /* ATA/ATAP registers */ + ioc4reg_t ata_0; + ioc4reg_t ata_1; + ioc4reg_t ata_2; + ioc4reg_t ata_3; + ioc4reg_t ata_4; + ioc4reg_t ata_5; + ioc4reg_t ata_6; + ioc4reg_t ata_7; + ioc4reg_t ata_aux; + + char ata_fill1[0x140 - 0x120 - 4]; + + ioc4reg_t ata_timing; + ioc4reg_t ata_dma_ptr_l; + ioc4reg_t ata_dma_ptr_h; + ioc4reg_t ata_dma_addr_l; + ioc4reg_t ata_dma_addr_h; + ioc4reg_t ata_bc_dev; + ioc4reg_t ata_bc_mem; + ioc4reg_t ata_dma_ctrl; + + char ata_fill2[0x200 - 0x15C - 4]; + + /* Keyboard and mouse registers */ + ioc4reg_t km_csr; + ioc4reg_t k_rd; + ioc4reg_t m_rd; + ioc4reg_t k_wd; + ioc4reg_t m_wd; + + char km_fill1[0x300 - 0x210 - 4]; + + /* Serial port registers used for DMA serial I/O */ + ioc4reg_t sbbr01_l; + ioc4reg_t sbbr01_h; + ioc4reg_t sbbr23_l; + ioc4reg_t sbbr23_h; + + ioc4_sregs_t port_0; + ioc4_sregs_t port_1; + ioc4_sregs_t port_2; + ioc4_sregs_t port_3; + + ioc4_uart_t uart_0; + ioc4_uart_t uart_1; + ioc4_uart_t uart_2; + ioc4_uart_t uart_3; +} ioc4_mem_t; + +#endif /* 0 */ + +/* + * Bytebus device space + */ +#define IOC4_BYTEBUS_DEV0 0x80000L /* Addressed using pci_bar0 */ +#define IOC4_BYTEBUS_DEV1 0xA0000L /* Addressed using pci_bar0 */ +#define IOC4_BYTEBUS_DEV2 0xC0000L /* Addressed using pci_bar0 */ +#define IOC4_BYTEBUS_DEV3 0xE0000L /* Addressed using pci_bar0 */ + +#if 0 +/* UART clock speed */ +#define IOC4_SER_XIN_CLK 66000000 + +typedef enum ioc4_subdevs_e { + ioc4_subdev_generic, + ioc4_subdev_kbms, + ioc4_subdev_tty0, + ioc4_subdev_tty1, + ioc4_subdev_tty2, + ioc4_subdev_tty3, + ioc4_subdev_rt, + ioc4_nsubdevs +} ioc4_subdev_t; + +/* Subdevice disable bits, + * from the standard INFO_LBL_SUBDEVS + */ +#define IOC4_SDB_TTY0 (1 << ioc4_subdev_tty0) +#define IOC4_SDB_TTY1 (1 << ioc4_subdev_tty1) +#define IOC4_SDB_TTY2 (1 << ioc4_subdev_tty2) +#define IOC4_SDB_TTY3 (1 << ioc4_subdev_tty3) +#define IOC4_SDB_KBMS (1 << ioc4_subdev_kbms) +#define IOC4_SDB_RT (1 << ioc4_subdev_rt) +#define IOC4_SDB_GENERIC (1 << ioc4_subdev_generic) + +#define IOC4_ALL_SUBDEVS ((1 << ioc4_nsubdevs) - 1) + +#define IOC4_SDB_SERIAL (IOC4_SDB_TTY0 | IOC4_SDB_TTY1 | IOC4_SDB_TTY2 | IOC4_SDB_TTY3) + +#define IOC4_STD_SUBDEVS IOC4_ALL_SUBDEVS + +#define IOC4_INTA_SUBDEVS (IOC4_SDB_SERIAL | IOC4_SDB_KBMS | IOC4_SDB_RT | IOC4_SDB_GENERIC) + +extern int ioc4_subdev_enabled(vertex_hdl_t, ioc4_subdev_t); +extern void ioc4_subdev_enables(vertex_hdl_t, ulong_t); +extern void ioc4_subdev_enable(vertex_hdl_t, ioc4_subdev_t); +extern void ioc4_subdev_disable(vertex_hdl_t, ioc4_subdev_t); + +/* Macros to read and write the SIO_IEC and SIO_IES registers (see the + * comments in ioc4.c for details on why this is necessary + */ +#define IOC4_W_IES 0 +#define IOC4_W_IEC 1 +extern void ioc4_write_ireg(void *, ioc4reg_t, int, ioc4_intr_type_t); + +#define IOC4_WRITE_IES(ioc4, val, type) ioc4_write_ireg(ioc4, val, IOC4_W_IES, type) +#define IOC4_WRITE_IEC(ioc4, val, type) ioc4_write_ireg(ioc4, val, IOC4_W_IEC, type) + +typedef void +ioc4_intr_func_f (intr_arg_t, ioc4reg_t); + +typedef void +ioc4_intr_connect_f (vertex_hdl_t conn_vhdl, + ioc4_intr_type_t, + ioc4reg_t, + ioc4_intr_func_f *, + intr_arg_t info, + vertex_hdl_t owner_vhdl, + vertex_hdl_t intr_dev_vhdl, + int (*)(intr_arg_t)); + +typedef void +ioc4_intr_disconnect_f (vertex_hdl_t conn_vhdl, + ioc4_intr_type_t, + ioc4reg_t, + ioc4_intr_func_f *, + intr_arg_t info, + vertex_hdl_t owner_vhdl); + +ioc4_intr_disconnect_f ioc4_intr_disconnect; +ioc4_intr_connect_f ioc4_intr_connect; + +extern int ioc4_is_console(vertex_hdl_t conn_vhdl); + +extern void ioc4_mlreset(ioc4_cfg_t *, ioc4_mem_t *); + +extern intr_func_f ioc4_intr; + +extern ioc4_mem_t *ioc4_mem_ptr(void *ioc4_fastinfo); + +typedef ioc4_intr_func_f *ioc4_intr_func_t; + +#endif /* 0 */ +#endif /* _ASM_IA64_SN_IOC4_H */ diff --git a/include/asm-ia64/sn/ioerror.h b/include/asm-ia64/sn/ioerror.h index f8260c8ccec31..f7e90b5cbc966 100644 --- a/include/asm-ia64/sn/ioerror.h +++ b/include/asm-ia64/sn/ioerror.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_IOERROR_H #define _ASM_IA64_SN_IOERROR_H @@ -108,7 +108,7 @@ * we have a single structure, and the appropriate fields get filled in * at each layer. * - This provides a way to dump all error related information in any layer - * of error handling (debugging aid). + * of erorr handling (debugging aid). * * A second possibility is to allow each layer to define its own error * data structure, and fill in the proper fields. This has the advantage diff --git a/include/asm-ia64/sn/ioerror_handling.h b/include/asm-ia64/sn/ioerror_handling.h index 401aaf3625966..171b37dc64eb9 100644 --- a/include/asm-ia64/sn/ioerror_handling.h +++ b/include/asm-ia64/sn/ioerror_handling.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_IOERROR_HANDLING_H #define _ASM_IA64_SN_IOERROR_HANDLING_H @@ -207,26 +207,17 @@ typedef uint64_t error_priority_t; /* Error state interfaces */ #if defined(CONFIG_SGI_IO_ERROR_HANDLING) -extern error_return_code_t error_state_set(devfs_handle_t,error_state_t); -extern error_state_t error_state_get(devfs_handle_t); +extern error_return_code_t error_state_set(vertex_hdl_t,error_state_t); +extern error_state_t error_state_get(vertex_hdl_t); #endif -/* System critical graph interfaces */ - -extern boolean_t is_sys_critical_vertex(devfs_handle_t); -extern devfs_handle_t sys_critical_first_child_get(devfs_handle_t); -extern devfs_handle_t sys_critical_next_child_get(devfs_handle_t); -extern devfs_handle_t sys_critical_parent_get(devfs_handle_t); -extern error_return_code_t sys_critical_graph_vertex_add(devfs_handle_t, - devfs_handle_t new); - /* Error action interfaces */ -extern error_return_code_t error_action_set(devfs_handle_t, +extern error_return_code_t error_action_set(vertex_hdl_t, error_action_f, error_context_t, error_priority_t); -extern error_return_code_t error_action_perform(devfs_handle_t); +extern error_return_code_t error_action_perform(vertex_hdl_t); #define INFO_LBL_ERROR_SKIP_ENV "error_skip_env" @@ -243,14 +234,14 @@ hwgraph_info_get_LBL(v, INFO_LBL_ERROR_SKIP_ENV, (arbitrary_info_t *)&l) hwgraph_info_remove_LBL(v, INFO_LBL_ERROR_SKIP_ENV, 0) /* Skip point interfaces */ -extern error_return_code_t error_skip_point_jump(devfs_handle_t, boolean_t); -extern error_return_code_t error_skip_point_clear(devfs_handle_t); +extern error_return_code_t error_skip_point_jump(vertex_hdl_t, boolean_t); +extern error_return_code_t error_skip_point_clear(vertex_hdl_t); /* REFERENCED */ #if defined(CONFIG_SGI_IO_ERROR_HANDLING) inline static int -error_skip_point_mark(devfs_handle_t v) +error_skip_point_mark(vertex_hdl_t v) { label_t *error_env = NULL; int code = 0; @@ -283,10 +274,10 @@ error_skip_point_mark(devfs_handle_t v) typedef uint64_t counter_t; -extern counter_t error_retry_count_get(devfs_handle_t); -extern error_return_code_t error_retry_count_set(devfs_handle_t,counter_t); -extern counter_t error_retry_count_increment(devfs_handle_t); -extern counter_t error_retry_count_decrement(devfs_handle_t); +extern counter_t error_retry_count_get(vertex_hdl_t); +extern error_return_code_t error_retry_count_set(vertex_hdl_t,counter_t); +extern counter_t error_retry_count_increment(vertex_hdl_t); +extern counter_t error_retry_count_decrement(vertex_hdl_t); /* Except for the PIO Read error typically the other errors are handled in * the context of an asynchronous error interrupt. @@ -298,7 +289,7 @@ extern counter_t error_retry_count_decrement(devfs_handle_t); * thru the calls the io error handling layer. */ #if defined(CONFIG_SGI_IO_ERROR_HANDLING) -extern boolean_t is_device_shutdown(devfs_handle_t); +extern boolean_t is_device_shutdown(vertex_hdl_t); #define IS_DEVICE_SHUTDOWN(_d) (is_device_shutdown(_d)) #endif diff --git a/include/asm-ia64/sn/iograph.h b/include/asm-ia64/sn/iograph.h index d6a6f62ba3470..f686631eb2d54 100644 --- a/include/asm-ia64/sn/iograph.h +++ b/include/asm-ia64/sn/iograph.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_IOGRAPH_H #define _ASM_IA64_SN_IOGRAPH_H @@ -77,7 +77,7 @@ #define EDGE_LBL_IOC3 "ioc3" #define EDGE_LBL_LUN "lun" #define EDGE_LBL_LINUX "linux" -#define EDGE_LBL_LINUX_BUS EDGE_LBL_LINUX "/busnum" +#define EDGE_LBL_LINUX_BUS EDGE_LBL_LINUX "/bus/pci-x" #define EDGE_LBL_MACE "mace" /* O2 mace */ #define EDGE_LBL_MACHDEP "machdep" /* Platform depedent devices */ #define EDGE_LBL_MASTER ".master" @@ -127,8 +127,12 @@ #define EDGE_LBL_XBOX_RPS "xbox_rps" /* redundant power supply for xbox unit */ #define EDGE_LBL_IOBRICK "iobrick" #define EDGE_LBL_PBRICK "Pbrick" +#define EDGE_LBL_PEBRICK "PEbrick" +#define EDGE_LBL_PXBRICK "PXbrick" +#define EDGE_LBL_IXBRICK "IXbrick" #define EDGE_LBL_IBRICK "Ibrick" #define EDGE_LBL_XBRICK "Xbrick" +#define EDGE_LBL_CGBRICK "CGbrick" #define EDGE_LBL_CPUBUS "cpubus" /* CPU Interfaces (SysAd) */ /* vertex info labels in hwgraph */ @@ -211,7 +215,7 @@ void init_all_devices(void); #include <asm/sn/xtalk/xbow.h> /* For get MAX_PORT_NUM */ int io_brick_map_widget(int, int); -int io_path_map_widget(devfs_handle_t); +int io_path_map_widget(vertex_hdl_t); /* * Map a brick's widget number to a meaningful int diff --git a/include/asm-ia64/sn/klclock.h b/include/asm-ia64/sn/klclock.h index 702460435f688..a288d7fd0bb72 100644 --- a/include/asm-ia64/sn/klclock.h +++ b/include/asm-ia64/sn/klclock.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1996, 2001-2003 Silicon Graphics, Inc. All rights reserved. * Copyright (C) 2001 by Ralf Baechle */ #ifndef _ASM_IA64_SN_KLCLOCK_H diff --git a/include/asm-ia64/sn/klconfig.h b/include/asm-ia64/sn/klconfig.h index 2bfc1708ac145..dee79cd85b87f 100644 --- a/include/asm-ia64/sn/klconfig.h +++ b/include/asm-ia64/sn/klconfig.h @@ -6,7 +6,7 @@ * * Derived from IRIX <sys/SN/klconfig.h>. * - * Copyright (C) 1992-1997,1999,2001-2002 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (C) 1992-1997,1999,2001-2003 Silicon Graphics, Inc. All Rights Reserved. * Copyright (C) 1999 by Ralf Baechle */ #ifndef _ASM_IA64_SN_KLCONFIG_H @@ -46,18 +46,8 @@ #include <asm/sn/xtalk/xtalk.h> #include <asm/sn/kldir.h> #include <asm/sn/sn_fru.h> - -#ifdef CONFIG_IA64_SGI_SN1 -#include <asm/sn/sn1/hubmd_next.h> -#endif - -#ifdef CONFIG_IA64_SGI_SN2 #include <asm/sn/sn2/shub_md.h> -#endif - -#ifdef CONFIG_IA64_SGI_SN2 #include <asm/sn/geo.h> -#endif #define KLCFGINFO_MAGIC 0xbeedbabe @@ -398,6 +388,12 @@ typedef struct kl_config_hdr { #define KLTYPE_IBRICK (KLCLASS_IOBRICK | 0x1) #define KLTYPE_PBRICK (KLCLASS_IOBRICK | 0x2) #define KLTYPE_XBRICK (KLCLASS_IOBRICK | 0x3) +#define KLTYPE_NBRICK (KLCLASS_IOBRICK | 0x4) +#define KLTYPE_PEBRICK (KLCLASS_IOBRICK | 0x5) +#define KLTYPE_PXBRICK (KLCLASS_IOBRICK | 0x6) +#define KLTYPE_IXBRICK (KLCLASS_IOBRICK | 0x7) +#define KLTYPE_CGBRICK (KLCLASS_IOBRICK | 0x8) + #define KLTYPE_PBRICK_BRIDGE KLTYPE_PBRICK @@ -437,11 +433,7 @@ typedef struct lboard_s { unsigned char brd_flags; /* Enabled, Disabled etc */ unsigned char brd_slot; /* slot number */ unsigned short brd_debugsw; /* Debug switches */ -#ifdef CONFIG_IA64_SGI_SN2 geoid_t brd_geoid; /* geo id */ -#else - moduleid_t brd_module; /* module to which it belongs */ -#endif partid_t brd_partition; /* Partition number */ unsigned short brd_diagval; /* diagnostic value */ unsigned short brd_diagparm; /* diagnostic parameter */ @@ -452,13 +444,11 @@ typedef struct lboard_s { klconf_off_t brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */ klconf_off_t brd_errinfo; /* Board's error information */ struct lboard_s *brd_parent; /* Logical parent for this brd */ - devfs_handle_t brd_graph_link; /* vertex hdl to connect extern compts */ + vertex_hdl_t brd_graph_link; /* vertex hdl to connect extern compts */ confidence_t brd_confidence; /* confidence that the board is bad */ nasid_t brd_owner; /* who owns this board */ unsigned char brd_nic_flags; /* To handle 8 more NICs */ -#ifdef CONFIG_IA64_SGI_SN2 char pad[32]; /* future expansion */ -#endif char brd_name[32]; } lboard_t; @@ -491,7 +481,8 @@ typedef struct lboard_s { ((_brd)->brd_next ? \ (NODE_OFFSET_TO_LBOARD(NASID_GET(_brd), (_brd)->brd_next)): NULL) #define KLCF_COMP(_brd, _ndx) \ - (NODE_OFFSET_TO_KLINFO(NASID_GET(_brd), (_brd)->brd_compts[(_ndx)])) + ((((_brd)->brd_compts[(_ndx)]) == 0) ? 0 : \ + (NODE_OFFSET_TO_KLINFO(NASID_GET(_brd), (_brd)->brd_compts[(_ndx)]))) #define KLCF_COMP_ERROR(_brd, _comp) \ (NODE_OFFSET_TO_K0(NASID_GET(_brd), (_comp)->errinfo)) @@ -626,9 +617,7 @@ typedef struct klport_s { nasid_t port_nasid; unsigned char port_flag; klconf_off_t port_offset; -#ifdef CONFIG_IA64_SGI_SN2 short port_num; -#endif } klport_t; typedef struct klcpu_s { /* CPU */ @@ -638,9 +627,7 @@ typedef struct klcpu_s { /* CPU */ unsigned short cpu_speed; /* Speed in MHZ */ unsigned short cpu_scachesz; /* secondary cache size in MB */ unsigned short cpu_scachespeed;/* secondary cache speed in MHz */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klcpu_t ; #define CPU_STRUCT_VERSION 2 @@ -648,28 +635,20 @@ typedef struct klcpu_s { /* CPU */ typedef struct klhub_s { /* HUB */ klinfo_t hub_info; uint hub_flags; /* PCFG_HUB_xxx flags */ -#ifdef CONFIG_IA64_SGI_SN2 #define MAX_NI_PORTS 2 klport_t hub_port[MAX_NI_PORTS + 1];/* hub is connected to this */ -#else - klport_t hub_port; /* hub is connected to this */ -#endif nic_t hub_box_nic; /* nic of containing box */ klconf_off_t hub_mfg_nic; /* MFG NIC string */ u64 hub_speed; /* Speed of hub in HZ */ -#ifdef CONFIG_IA64_SGI_SN2 moduleid_t hub_io_module; /* attached io module */ unsigned long pad; -#endif } klhub_t ; typedef struct klhub_uart_s { /* HUB */ klinfo_t hubuart_info; uint hubuart_flags; /* PCFG_HUB_xxx flags */ nic_t hubuart_box_nic; /* nic of containing box */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klhub_uart_t ; #define MEMORY_STRUCT_VERSION 2 @@ -680,9 +659,7 @@ typedef struct klmembnk_s { /* MEMORY BANK */ short membnk_dimm_select; /* bank to physical addr mapping*/ short membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */ short membnk_attr; -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klmembnk_t ; #define KLCONFIG_MEMBNK_SIZE(_info, _bank) \ @@ -701,9 +678,7 @@ typedef struct klmod_serial_num_s { char snum_str[MAX_SERIAL_NUM_SIZE]; unsigned long long snum_int; } snum; -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klmod_serial_num_t; /* Macros needed to access serial number structure in lboard_t. @@ -721,9 +696,7 @@ typedef struct klxbow_s { /* XBOW */ klport_t xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */ int xbow_master_hub_link; /* type of brd connected+component struct ptr+flags */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klxbow_t ; #define MAX_PCI_SLOTS 8 @@ -742,9 +715,7 @@ typedef struct klbri_s { /* BRIDGE */ pci_t pci_specific ; /* PCI Board config info */ klpci_device_t bri_devices[MAX_PCI_DEVS] ; /* PCI IDs */ klconf_off_t bri_mfg_nic ; -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klbri_t ; #define MAX_IOC3_TTY 2 @@ -758,9 +729,7 @@ typedef struct klioc3_s { /* IOC3 */ klinfo_t ioc3_enet ; klconf_off_t ioc3_enet_off ; klconf_off_t ioc3_kbd_off ; -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klioc3_t ; #define MAX_VME_SLOTS 8 @@ -769,18 +738,14 @@ typedef struct klvmeb_s { /* VME BRIDGE - PCI CTLR */ klinfo_t vmeb_info ; vmeb_t vmeb_specific ; klconf_off_t vmeb_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klvmeb_t ; typedef struct klvmed_s { /* VME DEVICE - VME BOARD */ klinfo_t vmed_info ; vmed_t vmed_specific ; klconf_off_t vmed_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klvmed_t ; #define ROUTER_VECTOR_VERS 2 @@ -793,9 +758,7 @@ typedef struct klrou_s { /* ROUTER */ klport_t rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */ klconf_off_t rou_mfg_nic ; /* MFG NIC string */ u64 rou_vector; /* vector from master node */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klrou_t ; /* @@ -820,25 +783,19 @@ typedef struct klgfx_s { /* GRAPHICS Device */ graphics_t gfx_specific; klconf_off_t pad0; /* for compatibility with older proms */ klconf_off_t gfx_mfg_nic; -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klgfx_t; typedef struct klxthd_s { klinfo_t xthd_info ; klconf_off_t xthd_mfg_nic ; /* MFG NIC string */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klxthd_t ; typedef struct kltpu_s { /* TPU board */ klinfo_t tpu_info ; klconf_off_t tpu_mfg_nic ; /* MFG NIC string */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } kltpu_t ; typedef struct klgsn_s { /* GSN board */ @@ -860,9 +817,7 @@ typedef struct klscsi_s { /* SCSI Bus */ scsi_t scsi_specific ; unsigned char scsi_numdevs ; klconf_off_t scsi_devinfo[MAX_SCSI_DEVS] ; -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klscsi_t ; typedef struct klscctl_s { /* SCSI Controller */ @@ -870,49 +825,37 @@ typedef struct klscctl_s { /* SCSI Controller */ uint type; uint scsi_buscnt; /* # busses this cntlr */ void *scsi_bus[2]; /* Pointer to 2 klscsi_t's */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klscctl_t ; typedef struct klscdev_s { /* SCSI device */ klinfo_t scdev_info ; struct scsidisk_data *scdev_cfg ; /* driver fills up this */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klscdev_t ; typedef struct klttydev_s { /* TTY device */ klinfo_t ttydev_info ; struct terminal_data *ttydev_cfg ; /* driver fills up this */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klttydev_t ; typedef struct klenetdev_s { /* ENET device */ klinfo_t enetdev_info ; struct net_data *enetdev_cfg ; /* driver fills up this */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klenetdev_t ; typedef struct klkbddev_s { /* KBD device */ klinfo_t kbddev_info ; struct keyboard_data *kbddev_cfg ; /* driver fills up this */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klkbddev_t ; typedef struct klmsdev_s { /* mouse device */ klinfo_t msdev_info ; void *msdev_cfg ; -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klmsdev_t ; #define MAX_FDDI_DEVS 10 /* XXX Is this true */ @@ -921,17 +864,13 @@ typedef struct klfddi_s { /* FDDI */ klinfo_t fddi_info ; fddi_t fddi_specific ; klconf_off_t fddi_devinfo[MAX_FDDI_DEVS] ; -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klfddi_t ; typedef struct klmio_s { /* MIO */ klinfo_t mio_info ; mio_t mio_specific ; -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klmio_t ; /* @@ -942,9 +881,7 @@ typedef struct klusb_s { klinfo_t usb_info; /* controller info */ void *usb_bus; /* handle to usb_bus_t */ uint64_t usb_controller; /* ptr to controller info */ -#ifdef CONFIG_IA64_SGI_SN2 unsigned long pad; -#endif } klusb_t ; typedef union klcomp_s { @@ -1028,37 +965,18 @@ extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type); extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int); -extern xwidgetnum_t nodevertex_widgetnum_get(devfs_handle_t node_vtx); -extern devfs_handle_t nodevertex_xbow_peer_get(devfs_handle_t node_vtx); extern lboard_t *find_gfxpipe(int pipenum); -extern void setup_gfxpipe_link(devfs_handle_t vhdl,int pipenum); extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class); -#ifdef CONFIG_IA64_SGI_SN2 -extern lboard_t *find_lboard_module_class(lboard_t *start, geoid_t geoid, - unsigned char brd_class); -#else -extern lboard_t *find_lboard_module_class(lboard_t *start, moduleid_t mod, - unsigned char brd_class); -#endif extern lboard_t *find_nic_lboard(lboard_t *, nic_t); extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t); -#ifdef CONFIG_IA64_SGI_SN2 extern lboard_t *find_lboard_modslot(lboard_t *start, geoid_t geoid); extern lboard_t *find_lboard_module(lboard_t *start, geoid_t geoid); -extern lboard_t *get_board_name(nasid_t nasid, geoid_t geoid, slotid_t slot, char *name); -#else -extern lboard_t *find_lboard_modslot(lboard_t *start, moduleid_t mod, slotid_t slot); -extern lboard_t *find_lboard_module(lboard_t *start, moduleid_t mod); -extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, char *name); -#endif extern int config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**); extern int config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**); extern int config_find_xbow(nasid_t, lboard_t **, klxbow_t**); extern int update_klcfg_cpuinfo(nasid_t, int); extern void board_to_path(lboard_t *brd, char *path); -#ifdef CONFIG_IA64_SGI_SN2 extern moduleid_t get_module_id(nasid_t nasid); -#endif extern void nic_name_convert(char *old_name, char *new_name); extern int module_brds(nasid_t nasid, lboard_t **module_brds, int n); extern lboard_t *brd_from_key(uint64_t key); diff --git a/include/asm-ia64/sn/kldir.h b/include/asm-ia64/sn/kldir.h index 2f6f644a20903..c49174494ce3b 100644 --- a/include/asm-ia64/sn/kldir.h +++ b/include/asm-ia64/sn/kldir.h @@ -5,7 +5,7 @@ * * Derived from IRIX <sys/SN/kldir.h>, revision 1.21. * - * Copyright (C) 1992-1997,1999,2001-2002 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (C) 1992-1997,1999,2001-2003 Silicon Graphics, Inc. All Rights Reserved. * Copyright (C) 1999 by Ralf Baechle */ #ifndef _ASM_IA64_SN_KLDIR_H diff --git a/include/asm-ia64/sn/ksys/elsc.h b/include/asm-ia64/sn/ksys/elsc.h index 40ba043febb6e..aa8272ad85804 100644 --- a/include/asm-ia64/sn/ksys/elsc.h +++ b/include/asm-ia64/sn/ksys/elsc.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_KSYS_ELSC_H #define _ASM_SN_KSYS_ELSC_H @@ -12,82 +12,6 @@ #include <linux/config.h> #include <asm/sn/ksys/l1.h> -#ifdef CONFIG_IA64_SGI_SN1 - -#define ELSC_ACP_MAX 86 /* 84+cr+lf */ -#define ELSC_LINE_MAX (ELSC_ACP_MAX - 2) - -typedef sc_cq_t elsc_cq_t; - -/* - * ELSC structure passed around as handle - */ - -typedef l1sc_t elsc_t; - -void elsc_init(elsc_t *e, nasid_t nasid); - -int elsc_process(elsc_t *e); -int elsc_msg_check(elsc_t *e, char *msg, int msg_max); -int elsc_msg_callback(elsc_t *e, - void (*callback)(void *callback_data, char *msg), - void *callback_data); -char *elsc_errmsg(int code); - -int elsc_nvram_write(elsc_t *e, int addr, char *buf, int len); -int elsc_nvram_read(elsc_t *e, int addr, char *buf, int len); -int elsc_nvram_magic(elsc_t *e); -int elsc_command(elsc_t *e, int only_if_message); -int elsc_parse(elsc_t *e, char *p1, char *p2, char *p3); -int elsc_ust_write(elsc_t *e, uchar_t c); -int elsc_ust_read(elsc_t *e, char *c); - - - -/* - * System controller commands - */ - -int elsc_version(elsc_t *e, char *result); -int elsc_debug_set(elsc_t *e, u_char byte1, u_char byte2); -int elsc_debug_get(elsc_t *e, u_char *byte1, u_char *byte2); -int elsc_module_set(elsc_t *e, int module); -int elsc_module_get(elsc_t *e); -int elsc_partition_set(elsc_t *e, int partition); -int elsc_partition_get(elsc_t *e); -int elsc_domain_set(elsc_t *e, int domain); -int elsc_domain_get(elsc_t *e); -int elsc_cluster_set(elsc_t *e, int cluster); -int elsc_cluster_get(elsc_t *e); -int elsc_cell_set(elsc_t *e, int cell); -int elsc_cell_get(elsc_t *e); -int elsc_bist_set(elsc_t *e, char bist_status); -char elsc_bist_get(elsc_t *e); -int elsc_lock(elsc_t *e, int retry_interval_usec, int timeout_usec, u_char lock_val); -int elsc_unlock(elsc_t *e); -int elsc_display_char(elsc_t *e, int led, int chr); -int elsc_display_digit(elsc_t *e, int led, int num, int l_case); -int elsc_display_mesg(elsc_t *e, char *chr); /* 8-char input */ -int elsc_password_set(elsc_t *e, char *password); /* 4-char input */ -int elsc_password_get(elsc_t *e, char *password); /* 4-char output */ -int elsc_rpwr_query(elsc_t *e, int is_master); -int elsc_power_query(elsc_t *e); -int elsc_power_down(elsc_t *e, int sec); -int elsc_power_cycle(elsc_t *e); -int elsc_system_reset(elsc_t *e); -int elsc_dip_switches(elsc_t *e); - -int _elsc_hbt(elsc_t *e, int ival, int rdly); - -#define elsc_hbt_enable(e, ival, rdly) _elsc_hbt(e, ival, rdly) -#define elsc_hbt_disable(e) _elsc_hbt(e, 0, 0) -#define elsc_hbt_send(e) _elsc_hbt(e, 0, 1) - -elsc_t *get_elsc(void); - -#endif /* CONFIG_IA64_SGI_SN1 */ - - /* * Error codes * diff --git a/include/asm-ia64/sn/ksys/l1.h b/include/asm-ia64/sn/ksys/l1.h index d3f1be0655470..6016bb73b86ec 100644 --- a/include/asm-ia64/sn/ksys/l1.h +++ b/include/asm-ia64/sn/ksys/l1.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992-1997,2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_KSYS_L1_H @@ -16,162 +16,6 @@ #include <asm/atomic.h> #include <asm/sn/sv.h> - -#ifdef CONFIG_IA64_SGI_SN1 - -#define BRL1_QSIZE 128 /* power of 2 is more efficient */ -#define BRL1_BUFSZ 264 /* needs to be large enough - * to hold 2 flags, escaped - * CRC, type/subchannel byte, - * and escaped payload - */ - -#define BRL1_IQS 32 -#define BRL1_OQS 4 - - -typedef struct sc_cq_s { - u_char buf[BRL1_QSIZE]; - int ipos, opos, tent_next; -} sc_cq_t; - -/* An l1sc_t struct can be associated with the local (C-brick) L1 or an L1 - * on an R-brick. In the R-brick case, the l1sc_t records a vector path - * to the R-brick's junk bus UART. In the C-brick case, we just use the - * following flag to denote the local uart. - * - * This value can't be confused with a network vector because the least- - * significant nibble of a network vector cannot be greater than 8. - */ -#define BRL1_LOCALHUB_UART ((net_vec_t)0xf) - -/* L1<->Bedrock reserved subchannels */ - -/* console channels */ -#define SC_CONS_CPU0 0x00 -#define SC_CONS_CPU1 0x01 -#define SC_CONS_CPU2 0x02 -#define SC_CONS_CPU3 0x03 - -#define L1_ELSCUART_SUBCH(p) (p) -#define L1_ELSCUART_CPU(ch) (ch) - -#define SC_CONS_SYSTEM CPUS_PER_NODE - -/* mapping subchannels to queues */ -#define MAP_IQ(s) (s) -#define MAP_OQ(s) (s) - -#define BRL1_NUM_SUBCHANS 32 -#define BRL1_CMD_SUBCH 16 -#define BRL1_EVENT_SUBCH (BRL1_NUM_SUBCHANS - 1) -#define BRL1_SUBCH_RSVD 0 -#define BRL1_SUBCH_FREE (-1) - -/* constants for L1 hwgraph vertex info */ -#define CBRICK_L1 (__psint_t)1 -#define IOBRICK_L1 (__psint_t)2 -#define RBRICK_L1 (__psint_t)3 - - -struct l1sc_s; -/* Saved off interrupt frame */ -typedef struct brl1_intr_frame { - int bf_irq; /* irq received */ - void *bf_dev_id; /* device information */ - struct pt_regs *bf_regs; /* register frame */ -} brl1_intr_frame_t; - -typedef void (*brl1_notif_t)(int, void *, struct pt_regs *, struct l1sc_s *, int); -typedef int (*brl1_uartf_t)(struct l1sc_s *); - -/* structure for controlling a subchannel */ -typedef struct brl1_sch_s { - int use; /* if this subchannel is free, - * use == BRL1_SUBCH_FREE */ - uint target; /* type, rack and slot of component to - * which this subchannel is directed */ - atomic_t packet_arrived; /* true if packet arrived on - * this subchannel */ - sc_cq_t * iqp; /* input queue for this subchannel */ - sv_t arrive_sv; /* used to wait for a packet */ - spinlock_t data_lock; /* synchronize access to input queues and - * other fields of the brl1_sch_s struct */ - brl1_notif_t tx_notify; /* notify higher layer that transmission may - * continue */ - brl1_notif_t rx_notify; /* notify higher layer that a packet has been - * received */ - brl1_intr_frame_t irq_frame; /* saved off irq information */ -} brl1_sch_t; - -/* br<->l1 protocol states */ -#define BRL1_IDLE 0 -#define BRL1_FLAG 1 -#define BRL1_HDR 2 -#define BRL1_BODY 3 -#define BRL1_ESC 4 -#define BRL1_RESET 7 - - -/* - * l1sc_t structure-- tracks protocol state, open subchannels, etc. - */ -typedef struct l1sc_s { - nasid_t nasid; /* nasid with which this instance - * of the structure is associated */ - moduleid_t modid; /* module id of this brick */ - u_char verbose; /* non-zero if elscuart routines should - * prefix output */ - net_vec_t uart; /* vector path to UART, or BRL1_LOCALUART */ - int sent; /* number of characters sent */ - int send_len; /* number of characters in send buf */ - brl1_uartf_t putc_f; /* pointer to UART putc function */ - brl1_uartf_t getc_f; /* pointer to UART getc function */ - - spinlock_t send_lock; /* arbitrates send synchronization */ - spinlock_t recv_lock; /* arbitrates uart receive access */ - spinlock_t subch_lock; /* arbitrates subchannel allocation */ - cpuid_t intr_cpu; /* cpu that receives L1 interrupts */ - - u_char send_in_use; /* non-zero if send buffer contains an - * unsent or partially-sent packet */ - u_char fifo_space; /* current depth of UART send FIFO */ - - u_char brl1_state; /* current state of the receive side */ - u_char brl1_last_hdr; /* last header byte received */ - - char send[BRL1_BUFSZ]; /* send buffer */ - - int sol; /* "start of line" (see elscuart routines) */ - int cons_listen; /* non-zero if the elscuart interface should - * also check the system console subchannel */ - brl1_sch_t subch[BRL1_NUM_SUBCHANS]; - /* subchannels provided by link */ - - sc_cq_t garbage_q; /* a place to put unsolicited packets */ - sc_cq_t oq[BRL1_OQS]; /* elscuart output queues */ -} l1sc_t; - - -/* error codes */ -#define BRL1_VALID 0 -#define BRL1_FULL_Q (-1) -#define BRL1_CRC (-2) -#define BRL1_PROTOCOL (-3) -#define BRL1_NO_MESSAGE (-4) -#define BRL1_LINK (-5) -#define BRL1_BUSY (-6) - -#define SC_SUCCESS BRL1_VALID -#define SC_NMSG BRL1_NO_MESSAGE -#define SC_BUSY BRL1_BUSY -#define SC_NOPEN (-7) -#define SC_BADSUBCH (-8) -#define SC_TIMEDOUT (-9) -#define SC_NSUBCH (-10) - -#endif /* CONFIG_IA64_SGI_SN1 */ - /* L1 Target Addresses */ /* * L1 commands and responses use source/target addresses that are @@ -181,39 +25,11 @@ typedef struct l1sc_s { * id (L1 functionality is divided into several independent "tasks" * that can each receive command requests and transmit responses) */ -#ifdef CONFIG_IA64_SGI_SN1 -#define L1_ADDR_TYPE_SHFT 28 -#define L1_ADDR_TYPE_MASK 0xF0000000 -#else -#define L1_ADDR_TYPE_SHFT 8 -#define L1_ADDR_TYPE_MASK 0xFF00 -#endif /* CONFIG_IA64_SGI_SN1 */ #define L1_ADDR_TYPE_L1 0x00 /* L1 system controller */ #define L1_ADDR_TYPE_L2 0x01 /* L2 system controller */ #define L1_ADDR_TYPE_L3 0x02 /* L3 system controller */ #define L1_ADDR_TYPE_CBRICK 0x03 /* attached C brick */ #define L1_ADDR_TYPE_IOBRICK 0x04 /* attached I/O brick */ - -#ifdef CONFIG_IA64_SGI_SN1 -#define L1_ADDR_RACK_SHFT 18 -#define L1_ADDR_RACK_MASK 0x0FFC0000 -#define L1_ADDR_RACK_LOCAL 0x3ff /* local brick's rack */ -#else -#define L1_ADDR_RACK_SHFT 16 -#define L1_ADDR_RACK_MASK 0xFFFF00 -#define L1_ADDR_RACK_LOCAL 0xffff /* local brick's rack */ -#endif /* CONFIG_IA64_SGI_SN1 */ - -#ifdef CONFIG_IA64_SGI_SN1 -#define L1_ADDR_BAY_SHFT 12 -#define L1_ADDR_BAY_MASK 0x0003F000 -#define L1_ADDR_BAY_LOCAL 0x3f /* local brick's bay */ -#else -#define L1_ADDR_BAY_SHFT 0 -#define L1_ADDR_BAY_MASK 0xFF -#define L1_ADDR_BAY_LOCAL 0xff /* local brick's bay */ -#endif /* CONFIG_IA64_SGI_SN1 */ - #define L1_ADDR_TASK_SHFT 0 #define L1_ADDR_TASK_MASK 0x0000001F #define L1_ADDR_TASK_INVALID 0x00 /* invalid task */ @@ -296,7 +112,9 @@ typedef struct l1sc_s { #define L1_BRICKTYPE_X 0x58 /* X */ #define L1_BRICKTYPE_X2 0x59 /* Y */ #define L1_BRICKTYPE_N 0x4e /* N */ +#define L1_BRICKTYPE_PE 0x25 /* % */ #define L1_BRICKTYPE_PX 0x23 /* # */ +#define L1_BRICKTYPE_IX 0x3d /* = */ /* EEPROM codes (for the "read EEPROM" request) */ /* c brick */ @@ -339,50 +157,10 @@ typedef uint32_t l1addr_t; #define bzero(d, n) memset((d), 0, (n)) -#ifdef CONFIG_IA64_SGI_SN1 - -#define SC_EVENT_CLASS_MASK ((unsigned short)0xff00) - -/* public interfaces to L1 system controller */ - -int sc_open( l1sc_t *sc, uint target ); -int sc_close( l1sc_t *sc, int ch ); -int sc_construct_msg( l1sc_t *sc, int ch, - char *msg, int msg_len, - uint addr_task, short req_code, - int req_nargs, ... ); -int sc_interpret_resp( char *resp, int resp_nargs, ... ); -int sc_send( l1sc_t *sc, int ch, char *msg, int len, int wait ); -int sc_recv( l1sc_t *sc, int ch, char *msg, int *len, uint64_t block ); -int sc_command( l1sc_t *sc, int ch, char *cmd, char *resp, int *len ); -int sc_command_kern( l1sc_t *sc, int ch, char *cmd, char *resp, int *len ); -int sc_poll( l1sc_t *sc, int ch ); -void sc_init( l1sc_t *sc, nasid_t nasid, net_vec_t uart ); -void sc_intr_enable( l1sc_t *sc ); - -int elsc_rack_bay_get(l1sc_t *e, uint *rack, uint *bay); -int elsc_rack_bay_type_get(l1sc_t *e, uint *rack, - uint *bay, uint *brick_type); -int elsc_cons_subch(l1sc_t *e, uint ch); -int elsc_cons_node(l1sc_t *e); -int elsc_display_line(l1sc_t *e, char *line, int lnum); - -extern l1sc_t *get_elsc( void ); -#define get_l1sc get_elsc -#define get_master_l1sc get_l1sc - -int iobrick_rack_bay_type_get( l1sc_t *sc, uint *rack, - uint *bay, uint *brick_type ); -int iobrick_module_get( l1sc_t *sc ); -int iobrick_pci_slot_pwr( l1sc_t *sc, int bus, int slot, int up ); -int iobrick_pci_bus_pwr( l1sc_t *sc, int bus, int up ); -int iobrick_sc_version( l1sc_t *sc, char *result ); -#else int elsc_display_line(nasid_t nasid, char *line, int lnum); int iobrick_rack_bay_type_get( nasid_t nasid, uint *rack, uint *bay, uint *brick_type ); int iobrick_module_get( nasid_t nasid ); -#endif /* CONFIG_IA64_SGI_SN1 */ #endif /* _ASM_SN_KSYS_L1_H */ diff --git a/include/asm-ia64/sn/labelcl.h b/include/asm-ia64/sn/labelcl.h index b08f52a4e627e..488245f721b3c 100644 --- a/include/asm-ia64/sn/labelcl.h +++ b/include/asm-ia64/sn/labelcl.h @@ -4,13 +4,11 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_LABELCL_H #define _ASM_IA64_SN_LABELCL_H -#include <asm/sn/hcl.h> - #define LABELCL_MAGIC 0x4857434c /* 'HWLC' */ #define LABEL_LENGTH_MAX 256 /* Includes NULL char */ #define INFO_DESC_PRIVATE (-1) /* default */ @@ -77,18 +75,18 @@ struct string_table { extern labelcl_info_t *labelcl_info_create(void); extern int labelcl_info_destroy(labelcl_info_t *); -extern int labelcl_info_add_LBL(struct devfs_entry *, char *, arb_info_desc_t, arbitrary_info_t); -extern int labelcl_info_remove_LBL(struct devfs_entry *, char *, arb_info_desc_t *, arbitrary_info_t *); -extern int labelcl_info_replace_LBL(struct devfs_entry *, char *, arb_info_desc_t, +extern int labelcl_info_add_LBL(vertex_hdl_t, char *, arb_info_desc_t, arbitrary_info_t); +extern int labelcl_info_remove_LBL(vertex_hdl_t, char *, arb_info_desc_t *, arbitrary_info_t *); +extern int labelcl_info_replace_LBL(vertex_hdl_t, char *, arb_info_desc_t, arbitrary_info_t, arb_info_desc_t *, arbitrary_info_t *); -extern int labelcl_info_get_LBL(struct devfs_entry *, char *, arb_info_desc_t *, +extern int labelcl_info_get_LBL(vertex_hdl_t, char *, arb_info_desc_t *, arbitrary_info_t *); -extern int labelcl_info_get_next_LBL(struct devfs_entry *, char *, arb_info_desc_t *, +extern int labelcl_info_get_next_LBL(vertex_hdl_t, char *, arb_info_desc_t *, arbitrary_info_t *, labelcl_info_place_t *); -extern int labelcl_info_replace_IDX(struct devfs_entry *, int, arbitrary_info_t, +extern int labelcl_info_replace_IDX(vertex_hdl_t, int, arbitrary_info_t, arbitrary_info_t *); -extern int labelcl_info_connectpt_set(struct devfs_entry *, struct devfs_entry *); -extern int labelcl_info_get_IDX(struct devfs_entry *, int, arbitrary_info_t *); -extern struct devfs_entry *device_info_connectpt_get(struct devfs_entry *); +extern int labelcl_info_connectpt_set(vertex_hdl_t, vertex_hdl_t); +extern int labelcl_info_get_IDX(vertex_hdl_t, int, arbitrary_info_t *); +extern struct devfs_handle_t device_info_connectpt_get(vertex_hdl_t); #endif /* _ASM_IA64_SN_LABELCL_H */ diff --git a/include/asm-ia64/sn/leds.h b/include/asm-ia64/sn/leds.h index 040b117f4b6c6..095d26106e9db 100644 --- a/include/asm-ia64/sn/leds.h +++ b/include/asm-ia64/sn/leds.h @@ -5,7 +5,7 @@ * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #include <linux/config.h> @@ -13,25 +13,14 @@ #include <asm/sn/addrs.h> #include <asm/sn/sn_cpuid.h> #include <asm/sn/pda.h> - -#ifdef CONFIG_IA64_SGI_SN1 -#define LED0 0xc0000b00100000c0LL -#define LED_CPU_SHIFT 3 -#else #include <asm/sn/sn2/shub.h> + #define LED0 (LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0)) #define LED_CPU_SHIFT 16 -#endif #define LED_CPU_HEARTBEAT 0x01 #define LED_CPU_ACTIVITY 0x02 -#ifdef LED_WAR -#define LED_ALWAYS_SET 0x64 /* SN2 hw workaround: always set 0x60 */ -#define LED_MASK_AUTOTEST 0x9e -#else /* LED_WAR */ #define LED_ALWAYS_SET 0x00 -#define LED_MASK_AUTOTEST 0xfe -#endif /* LED_WAR */ /* * Basic macros for flashing the LEDS on an SGI, SN1. @@ -40,14 +29,8 @@ static __inline__ void set_led_bits(u8 value, u8 mask) { -#if 0 - pda.led_state = (pda.led_state & ~mask) | (value & mask); -#ifdef CONFIG_IA64_SGI_SN1 - *pda.led_address = (long) pda.led_state; -#else - *pda.led_address = (short) pda.led_state; -#endif -#endif + pda->led_state = (pda->led_state & ~mask) | (value & mask); + *pda->led_address = (short) pda->led_state; } #endif /* _ASM_IA64_SN_LEDS_H */ diff --git a/include/asm-ia64/sn/mca.h b/include/asm-ia64/sn/mca.h deleted file mode 100644 index 4c17af4701a9b..0000000000000 --- a/include/asm-ia64/sn/mca.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * File: mca.h - * Purpose: Machine check handling specific to the SN platform defines - * - * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it would be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Further, this software is distributed without any warranty that it is - * free of the rightful claim of any third person regarding infringement - * or the like. Any license provided herein, whether implied or - * otherwise, applies only to this software file. Patent licenses, if - * any, provided herein do not apply to combinations of this program with - * other software, or any other product whatsoever. - * - * You should have received a copy of the GNU General Public - * License along with this program; if not, write the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, - * Mountain View, CA 94043, or: - * - * http://www.sgi.com - * - * For further information regarding this notice, see: - * - * http://oss.sgi.com/projects/GenInfo/NoticeExplan - */ - -#include <linux/config.h> -#include <linux/types.h> -#include <asm/sal.h> -#include <asm/mca.h> - -#ifdef CONFIG_IA64_SGI_SN - -typedef u64 __uint64_t; - -typedef struct { - __uint64_t sh_event_occurred; - __uint64_t sh_first_error; - __uint64_t sh_event_overflow; - __uint64_t sh_pi_first_error; - __uint64_t sh_pi_error_summary; - __uint64_t sh_pi_error_overflow; - __uint64_t sh_pi_error_detail_1; - __uint64_t sh_pi_error_detail_2; - __uint64_t sh_pi_hw_time_stamp; - __uint64_t sh_pi_uncorrected_detail_1; - __uint64_t sh_pi_uncorrected_detail_2; - __uint64_t sh_pi_uncorrected_detail_3; - __uint64_t sh_pi_uncorrected_detail_4; - __uint64_t sh_pi_uncor_time_stamp; - __uint64_t sh_pi_corrected_detail_1; - __uint64_t sh_pi_corrected_detail_2; - __uint64_t sh_pi_corrected_detail_3; - __uint64_t sh_pi_corrected_detail_4; - __uint64_t sh_pi_cor_time_stamp; - __uint64_t sh_mem_error_summary; - __uint64_t sh_mem_error_overflow; - __uint64_t sh_misc_err_hdr_lower; - __uint64_t sh_misc_err_hdr_upper; - __uint64_t sh_dir_uc_err_hdr_lower; - __uint64_t sh_dir_uc_err_hdr_upper; - __uint64_t sh_dir_cor_err_hdr_lower; - __uint64_t sh_dir_cor_err_hdr_upper; - __uint64_t sh_mem_error_mask; - __uint64_t sh_md_uncor_time_stamp; - __uint64_t sh_md_cor_time_stamp; - __uint64_t sh_md_hw_time_stamp; - __uint64_t sh_xn_error_summary; - __uint64_t sh_xn_first_error; - __uint64_t sh_xn_error_overflow; - __uint64_t sh_xniilb_error_summary; - __uint64_t sh_xniilb_first_error; - __uint64_t sh_xniilb_error_overflow; - __uint64_t sh_xniilb_error_detail_1; - __uint64_t sh_xniilb_error_detail_2; - __uint64_t sh_xniilb_error_detail_3; - __uint64_t sh_xnpi_error_summary; - __uint64_t sh_xnpi_first_error; - __uint64_t sh_xnpi_error_overflow; - __uint64_t sh_xnpi_error_detail_1; - __uint64_t sh_xnmd_error_summary; - __uint64_t sh_xnmd_first_error; - __uint64_t sh_xnmd_error_overflow; - __uint64_t sh_xnmd_ecc_err_report; - __uint64_t sh_xnmd_error_detail_1; - __uint64_t sh_lb_error_summary; - __uint64_t sh_lb_first_error; - __uint64_t sh_lb_error_overflow; - __uint64_t sh_lb_error_detail_1; - __uint64_t sh_lb_error_detail_2; - __uint64_t sh_lb_error_detail_3; - __uint64_t sh_lb_error_detail_4; - __uint64_t sh_lb_error_detail_5; -} sal_log_shub_state_t; - -typedef struct { -sal_log_section_hdr_t header; - struct - { - __uint64_t err_status : 1, - guid : 1, - oem_data : 1, - reserved : 61; - } valid; - __uint64_t err_status; - efi_guid_t guid; - __uint64_t shub_nic; - sal_log_shub_state_t shub_state; -} sal_log_plat_info_t; - - -extern void sal_log_plat_print(int header_len, int sect_len, u8 *p_data, prfunc_t prfunc); - -#ifdef platform_plat_specific_err_print -#undef platform_plat_specific_err_print -#endif -#define platform_plat_specific_err_print sal_log_plat_print - -#endif /* CONFIG_IA64_SGI_SN */ diff --git a/include/asm-ia64/sn/mmtimer_private.h b/include/asm-ia64/sn/mmtimer_private.h index 72ead52c7eb4e..e8ba8e0b40cc9 100644 --- a/include/asm-ia64/sn/mmtimer_private.h +++ b/include/asm-ia64/sn/mmtimer_private.h @@ -5,7 +5,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. * * Helper file for the SN implementation of mmtimers * diff --git a/include/asm-ia64/sn/module.h b/include/asm-ia64/sn/module.h index 9e3b73818a3ea..df95417bf33c9 100644 --- a/include/asm-ia64/sn/module.h +++ b/include/asm-ia64/sn/module.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_MODULE_H #define _ASM_IA64_SN_MODULE_H @@ -32,9 +32,6 @@ extern "C" { #define MODULE_FORMAT_BRIEF 1 #define MODULE_FORMAT_LONG 2 - -#ifdef CONFIG_IA64_SGI_SN2 - /* * Module id format * @@ -141,6 +138,7 @@ extern char brick_types[]; #define MODULE_NBRICK 7 #define MODULE_PEBRICK 8 #define MODULE_PXBRICK 9 +#define MODULE_IXBRICK 10 /* * Moduleid_t comparison macros @@ -150,118 +148,6 @@ extern char brick_types[]; ((_m2)&(MODULE_RACK_MASK|MODULE_BPOS_MASK))) #define MODULE_MATCH(_m1, _m2) (MODULE_CMP((_m1),(_m2)) == 0) - -#else -#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) - -/* - * Module id format - * - * 15-12 Brick type (enumerated) - * 11-6 Rack ID (encoded class, group, number) - * 5-0 Brick position in rack (0-63) - */ -/* - * Macros for getting the brick type - */ -#define MODULE_BTYPE_MASK 0xf000 -#define MODULE_BTYPE_SHFT 12 -#define MODULE_GET_BTYPE(_m) (((_m) & MODULE_BTYPE_MASK) >> MODULE_BTYPE_SHFT) -#define MODULE_BT_TO_CHAR(_b) (brick_types[(_b)]) -#define MODULE_GET_BTCHAR(_m) (MODULE_BT_TO_CHAR(MODULE_GET_BTYPE(_m))) - -/* - * Macros for getting the rack ID. - */ -#define MODULE_RACK_MASK 0x0fc0 -#define MODULE_RACK_SHFT 6 -#define MODULE_GET_RACK(_m) (((_m) & MODULE_RACK_MASK) >> MODULE_RACK_SHFT) - -/* - * Macros for getting the brick position - */ -#define MODULE_BPOS_MASK 0x003f -#define MODULE_BPOS_SHFT 0 -#define MODULE_GET_BPOS(_m) (((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT) - -/* - * Macros for constructing moduleid_t's - */ -#define RBT_TO_MODULE(_r, _b, _t) ((_r) << MODULE_RACK_SHFT | \ - (_b) << MODULE_BPOS_SHFT | \ - (_t) << MODULE_BTYPE_SHFT) - -/* - * Macros for encoding and decoding rack IDs - * A rack number consists of three parts: - * class 1 bit, 0==CPU/mixed, 1==I/O - * group 2 bits for CPU/mixed, 3 bits for I/O - * number 3 bits for CPU/mixed, 2 bits for I/O (1 based) - */ -#define RACK_GROUP_BITS(_r) (RACK_GET_CLASS(_r) ? 3 : 2) -#define RACK_NUM_BITS(_r) (RACK_GET_CLASS(_r) ? 2 : 3) - -#define RACK_CLASS_MASK(_r) 0x20 -#define RACK_CLASS_SHFT(_r) 5 -#define RACK_GET_CLASS(_r) \ - (((_r) & RACK_CLASS_MASK(_r)) >> RACK_CLASS_SHFT(_r)) -#define RACK_ADD_CLASS(_r, _c) \ - ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r)) - -#define RACK_GROUP_SHFT(_r) RACK_NUM_BITS(_r) -#define RACK_GROUP_MASK(_r) \ - ( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) ) -#define RACK_GET_GROUP(_r) \ - (((_r) & RACK_GROUP_MASK(_r)) >> RACK_GROUP_SHFT(_r)) -#define RACK_ADD_GROUP(_r, _g) \ - ((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r)) - -#define RACK_NUM_SHFT(_r) 0 -#define RACK_NUM_MASK(_r) \ - ( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) ) -#define RACK_GET_NUM(_r) \ - ( (((_r) & RACK_NUM_MASK(_r)) >> RACK_NUM_SHFT(_r)) + 1 ) -#define RACK_ADD_NUM(_r, _n) \ - ((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r)) - -/* - * Brick type definitions - */ -#define MAX_BRICK_TYPES 16 /* 1 << (MODULE_RACK_SHFT - MODULE_BTYPE_SHFT */ - -extern char brick_types[]; - -#define MODULE_CBRICK 0 -#define MODULE_RBRICK 1 -#define MODULE_IBRICK 2 -#define MODULE_KBRICK 3 -#define MODULE_XBRICK 4 -#define MODULE_DBRICK 5 -#define MODULE_PBRICK 6 -#define MODULE_NBRICK 7 -#define MODULE_PEBRICK 8 -#define MODULE_PXBRICK 9 - -/* - * Moduleid_t comparison macros - */ -/* Don't compare the brick type: only the position is significant */ -#define MODULE_CMP(_m1, _m2) (((_m1)&(MODULE_RACK_MASK|MODULE_BPOS_MASK)) -\ - ((_m2)&(MODULE_RACK_MASK|MODULE_BPOS_MASK))) -#define MODULE_MATCH(_m1, _m2) (MODULE_CMP((_m1),(_m2)) == 0) - -#else - -/* - * Some code that uses this macro will not be conditionally compiled. - */ -#define MODULE_GET_BTCHAR(_m) ('?') -#define MODULE_CMP(_m1, _m2) ((_m1) - (_m2)) -#define MODULE_MATCH(_m1, _m2) (MODULE_CMP((_m1),(_m2)) == 0) - -#endif /* SN1 */ -#endif /* SN2 */ - typedef struct module_s module_t; struct module_s { @@ -271,23 +157,15 @@ struct module_s { /* List of nodes in this module */ cnodeid_t nodes[MODULE_MAX_NODES]; -#ifdef CONFIG_IA64_SGI_SN2 geoid_t geoid[MODULE_MAX_NODES]; struct { char moduleid[8]; } io[MODULE_MAX_NODES]; -#endif int nodecnt; /* Number of nodes in array */ - /* Fields for Module System Controller */ int mesgpend; /* Message pending */ int shutdown; /* Shutdown in progress */ struct semaphore thdcnt; /* Threads finished counter */ - -#ifdef CONFIG_IA64_SGI_SN1 - elsc_t elsc; - spinlock_t elsclock; -#endif time_t intrhist[MODULE_HIST_CNT]; int histptr; @@ -315,10 +193,6 @@ extern int nummodules; extern module_t *module_lookup(moduleid_t id); -#if defined(CONFIG_IA64_SGI_SN1) -extern elsc_t *get_elsc(void); -#endif - extern int get_kmod_info(cmoduleid_t cmod, module_info_t *mod_info); extern int get_kmod_sys_snum(cmoduleid_t cmod, diff --git a/include/asm-ia64/sn/nag.h b/include/asm-ia64/sn/nag.h index f1380f7c78737..10a15a8a26175 100644 --- a/include/asm-ia64/sn/nag.h +++ b/include/asm-ia64/sn/nag.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. */ diff --git a/include/asm-ia64/sn/nic.h b/include/asm-ia64/sn/nic.h deleted file mode 100644 index 44eedb02f7daa..0000000000000 --- a/include/asm-ia64/sn/nic.h +++ /dev/null @@ -1,129 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_NIC_H -#define _ASM_IA64_SN_NIC_H - -#include <asm/types.h> -#include <asm/sn/types.h> -#include <linux/devfs_fs_kernel.h> - -#define MCR_DATA(x) ((int) ((x) & 1)) -#define MCR_DONE(x) ((x) & 2) -#define MCR_PACK(pulse, sample) ((pulse) << 10 | (sample) << 2) - -typedef __psunsigned_t nic_data_t; - -typedef int -nic_access_f(nic_data_t data, - int pulse, int sample, int delay); - -typedef nic_access_f *nic_access_t; - -typedef struct nic_vmce_s *nic_vmce_t; -typedef void nic_vmc_func(devfs_handle_t v); - -/* - * PRIVATE data for Dallas NIC - */ - -typedef struct nic_state_t { - nic_access_t access; - nic_data_t data; - int last_disc; - int done; - int bit_index; - int disc_marker; - uchar_t bits[64]; -} nic_state_t; - -/* - * Public interface for Dallas NIC - * - * - * Access Routine - * - * nic_setup requires an access routine that pulses the NIC line for a - * specified duration, samples the NIC line after a specified duration, - * then delays for a third specified duration (for precharge). - * - * This general scheme allows us to access NICs through any medium - * (e.g. hub regs, bridge regs, vector writes, system ctlr commands). - * - * The access routine should return the sample value 0 or 1, or if an - * error occurs, return a negative error code. Negative error codes from - * the access routine will abort the NIC operation and be propagated - * through out of the top-level NIC call. - */ - -#define NIC_OK 0 -#define NIC_DONE 1 -#define NIC_FAIL 2 -#define NIC_BAD_CRC 3 -#define NIC_NOT_PRESENT 4 -#define NIC_REDIR_LOOP 5 -#define NIC_PARAM 6 -#define NIC_NOMEM 7 - -uint64_t nic_get_phase_bits(void); - -extern int nic_setup(nic_state_t *ns, - nic_access_t access, - nic_data_t data); - -extern int nic_next(nic_state_t *ns, - char *serial, - char *family, - char *crc); - -extern int nic_read_one_page(nic_state_t *ns, - char *family, - char *serial, - char *crc, - int start, - uchar_t *redirect, - uchar_t *byte); - -extern int nic_read_mfg(nic_state_t *ns, - char *family, - char *serial, - char *crc, - uchar_t *pageA, - uchar_t *pageB); - -extern int nic_info_get(nic_access_t access, - nic_data_t data, - char *info); - -extern int nic_item_info_get(char *buf, char *item, char **item_info); - -nic_access_f nic_access_mcr32; - -extern char *nic_vertex_info_get(devfs_handle_t v); - -extern char *nic_vertex_info_set(nic_access_t access, - nic_data_t data, - devfs_handle_t v); - -extern int nic_vertex_info_match(devfs_handle_t vertex, - char *name); - -extern char *nic_bridge_vertex_info(devfs_handle_t vertex, - nic_data_t data); -extern char *nic_hq4_vertex_info(devfs_handle_t vertex, - nic_data_t data); -extern char *nic_ioc3_vertex_info(devfs_handle_t vertex, - nic_data_t data, - int32_t *gpcr_s); - -extern char *nic_hub_vertex_info(devfs_handle_t vertex); - -extern nic_vmce_t nic_vmc_add(char *, nic_vmc_func *); -extern void nic_vmc_del(nic_vmce_t); - -#endif /* _ASM_IA64_SN_NIC_H */ diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h index f9aa614ddb170..a53b50cae4b60 100644 --- a/include/asm-ia64/sn/nodepda.h +++ b/include/asm-ia64/sn/nodepda.h @@ -3,27 +3,21 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_NODEPDA_H #define _ASM_IA64_SN_NODEPDA_H #include <linux/config.h> +#include <asm/sn/sgi.h> #include <asm/irq.h> #include <asm/sn/intr.h> #include <asm/sn/router.h> -#if defined(CONFIG_IA64_SGI_SN1) -#include <asm/sn/sn1/synergy.h> -#endif #include <asm/sn/pda.h> #include <asm/sn/module.h> #include <asm/sn/bte.h> -#if defined(CONFIG_IA64_SGI_SN1) -#include <asm/sn/sn1/hubstat.h> -#endif - /* * NUMA Node-Specific Data structures are defined in this file. * In particular, this is the location of the node PDA. @@ -31,23 +25,6 @@ */ /* - * Subnode PDA structures. Each node needs a few data structures that - * correspond to the PIs on the HUB chip that supports the node. - */ -#if defined(CONFIG_IA64_SGI_SN1) -struct subnodepda_s { - intr_vecblk_t intr_dispatch0; - intr_vecblk_t intr_dispatch1; -}; - -typedef struct subnodepda_s subnode_pda_t; - - -struct synergy_perf_s; -#endif - - -/* * Node-specific data structure. * * One of these structures is allocated on each node of a NUMA system. @@ -66,24 +43,20 @@ struct nodepda_s { /* the second cpu on a node is */ /* node_first_cpu+1. */ - devfs_handle_t xbow_vhdl; + vertex_hdl_t xbow_vhdl; nasid_t xbow_peer; /* NASID of our peer hub on xbow */ struct semaphore xbow_sema; /* Sema for xbow synchronization */ slotid_t slotdesc; -#ifdef CONFIG_IA64_SGI_SN2 geoid_t geoid; -#else - moduleid_t module_id; /* Module ID (redundant local copy) */ -#endif module_t *module; /* Pointer to containing module */ xwidgetnum_t basew_id; - devfs_handle_t basew_xc; + vertex_hdl_t basew_xc; int hubticks; int num_routers; /* XXX not setup! Total routers in the system */ char *hwg_node_name; /* hwgraph node name */ - devfs_handle_t node_vertex; /* Hwgraph vertex for this node */ + vertex_hdl_t node_vertex; /* Hwgraph vertex for this node */ void *pdinfo; /* Platform-dependent per-node info */ @@ -95,27 +68,9 @@ struct nodepda_s { /* * The BTEs on this node are shared by the local cpus */ - bteinfo_t bte_if[BTES_PER_NODE]; /* Virtual Interface */ - char bte_cleanup[5 * L1_CACHE_BYTES] ____cacheline_aligned; - -#if defined(CONFIG_IA64_SGI_SN1) - subnode_pda_t snpda[NUM_SUBNODES]; - /* - * New extended memory reference counters - */ - void *migr_refcnt_counterbase; - void *migr_refcnt_counterbuffer; - size_t migr_refcnt_cbsize; - int migr_refcnt_numsets; - hubstat_t hubstats; - int synergy_perf_enabled; - int synergy_perf_freq; - spinlock_t synergy_perf_lock; - uint64_t synergy_inactive_intervals; - uint64_t synergy_active_intervals; - struct synergy_perf_s *synergy_perf_data; - struct synergy_perf_s *synergy_perf_first; /* reporting consistency .. */ -#endif /* CONFIG_IA64_SGI_SN1 */ + struct bteinfo_s bte_if[BTES_PER_NODE]; /* Virtual Interface */ + struct timer_list bte_recovery_timer; + spinlock_t bte_recovery_lock; /* * Array of pointers to the nodepdas for each node. @@ -126,18 +81,16 @@ struct nodepda_s { typedef struct nodepda_s nodepda_t; -#ifdef CONFIG_IA64_SGI_SN2 -#define NR_IVECS 256 struct irqpda_s { int num_irq_used; - char irq_flags[NR_IVECS]; + char irq_flags[NR_IRQS]; + struct pci_dev *device_dev[NR_IRQS]; + char share_count[NR_IRQS]; + struct pci_dev *current; }; typedef struct irqpda_s irqpda_t; -#endif /* CONFIG_IA64_SGI_SN2 */ - - /* * Access Functions for node PDA. @@ -156,21 +109,11 @@ typedef struct irqpda_s irqpda_t; #define nodepda pda->p_nodepda /* Ptr to this node's PDA */ #define NODEPDA(cnode) (nodepda->pernode_pdaindr[cnode]) -#if defined(CONFIG_IA64_SGI_SN1) -#define subnodepda pda.p_subnodepda /* Ptr to this node's subnode PDA */ -#define SUBNODEPDA(cnode,sn) (&(NODEPDA(cnode)->snpda[sn])) -#define SNPDA(npda,sn) (&(npda)->snpda[sn]) -#endif - /* * Macros to access data structures inside nodepda */ -#ifdef CONFIG_IA64_SGI_SN2 #define NODE_MODULEID(cnode) geo_module((NODEPDA(cnode)->geoid)) -#else -#define NODE_MODULEID(cnode) (NODEPDA(cnode)->module_id) -#endif #define NODE_SLOTID(cnode) (NODEPDA(cnode)->slotdesc) @@ -184,8 +127,8 @@ typedef struct irqpda_s irqpda_t; * Check if given a compact node id the corresponding node has all the * cpus disabled. */ -#define is_headless_node(cnode) 0 /*((cnode == CNODEID_NONE) || \ - (node_data(cnode)->active_cpu_count == 0)) */ +#define is_headless_node(cnode) ((cnode == CNODEID_NONE) || \ + (node_data(cnode)->active_cpu_count == 0)) /* * Check if given a node vertex handle the corresponding node has all the diff --git a/include/asm-ia64/sn/pci/bridge.h b/include/asm-ia64/sn/pci/bridge.h index ebbc59ad0d1b0..bc021e657f72d 100644 --- a/include/asm-ia64/sn/pci/bridge.h +++ b/include/asm-ia64/sn/pci/bridge.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_BRIDGE_H #define _ASM_SN_PCI_BRIDGE_H @@ -36,7 +36,6 @@ #include <linux/config.h> #include <asm/sn/xtalk/xwidget.h> -#ifndef CONFIG_IA64_SGI_SN1 #include <asm/sn/pci/pic.h> extern int io_get_sh_swapper(nasid_t); @@ -45,7 +44,6 @@ extern int io_get_sh_swapper(nasid_t); #define BRIDGE_REG_SET32(reg) \ *(volatile uint32_t *) (((uint64_t)reg)^4) -#endif /* CONFIG_IA64_SGI_SN1 */ /* I/O page size */ @@ -111,7 +109,6 @@ typedef volatile bridge_ate_t *bridge_ate_p; * Generated from Bridge spec dated 04oct95 */ -#ifndef CONFIG_IA64_SGI_SN1 /* * pic_widget_cfg_s is a local definition of widget_cfg_t but with @@ -605,292 +602,6 @@ typedef volatile struct bridge_s { } b_external_flash; } bridge_t; -#else /* CONFIG_IA64_SGI_SN1 */ - - -typedef volatile struct bridge_s { - - /* Local Registers 0x000000-0x00FFFF */ - - /* standard widget configuration 0x000000-0x000057 */ - widget_cfg_t b_widget; /* 0x000000 */ - - /* helper fieldnames for accessing bridge widget */ - -#define b_wid_id b_widget.w_id -#define b_wid_stat b_widget.w_status -#define b_wid_err_upper b_widget.w_err_upper_addr -#define b_wid_err_lower b_widget.w_err_lower_addr -#define b_wid_control b_widget.w_control -#define b_wid_req_timeout b_widget.w_req_timeout -#define b_wid_int_upper b_widget.w_intdest_upper_addr -#define b_wid_int_lower b_widget.w_intdest_lower_addr -#define b_wid_err_cmdword b_widget.w_err_cmd_word -#define b_wid_llp b_widget.w_llp_cfg -#define b_wid_tflush b_widget.w_tflush - - /* - * we access these through synergy unswizzled space, so the address - * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) - * That's why we put the register first and filler second. - */ - /* bridge-specific widget configuration 0x000058-0x00007F */ - bridgereg_t b_wid_aux_err; /* 0x00005C */ - bridgereg_t _pad_000058; - - bridgereg_t b_wid_resp_upper; /* 0x000064 */ - bridgereg_t _pad_000060; - - bridgereg_t b_wid_resp_lower; /* 0x00006C */ - bridgereg_t _pad_000068; - - bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ - bridgereg_t _pad_000070; - - bridgereg_t _pad_000078[2]; - - /* PMU & Map 0x000080-0x00008F */ - bridgereg_t b_dir_map; /* 0x000084 */ - bridgereg_t _pad_000080; - bridgereg_t _pad_000088[2]; - - /* SSRAM 0x000090-0x00009F */ - bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */ - bridgereg_t _pad_000090; -#define b_ram_perr b_ram_perr_or_map_fault /* Bridge */ -#define b_map_fault b_ram_perr_or_map_fault /* Xbridge */ - bridgereg_t _pad_000098[2]; - - /* Arbitration 0x0000A0-0x0000AF */ - bridgereg_t b_arb; /* 0x0000A4 */ - bridgereg_t _pad_0000A0; - bridgereg_t _pad_0000A8[2]; - - /* Number In A Can 0x0000B0-0x0000BF */ - bridgereg_t b_nic; /* 0x0000B4 */ - bridgereg_t _pad_0000B0; - bridgereg_t _pad_0000B8[2]; - - /* PCI/GIO 0x0000C0-0x0000FF */ - bridgereg_t b_bus_timeout; /* 0x0000C4 */ - bridgereg_t _pad_0000C0; -#define b_pci_bus_timeout b_bus_timeout - - bridgereg_t b_pci_cfg; /* 0x0000CC */ - bridgereg_t _pad_0000C8; - - bridgereg_t b_pci_err_upper; /* 0x0000D4 */ - bridgereg_t _pad_0000D0; - - bridgereg_t b_pci_err_lower; /* 0x0000DC */ - bridgereg_t _pad_0000D8; - bridgereg_t _pad_0000E0[8]; -#define b_gio_err_lower b_pci_err_lower -#define b_gio_err_upper b_pci_err_upper - - /* Interrupt 0x000100-0x0001FF */ - bridgereg_t b_int_status; /* 0x000104 */ - bridgereg_t _pad_000100; - - bridgereg_t b_int_enable; /* 0x00010C */ - bridgereg_t _pad_000108; - - bridgereg_t b_int_rst_stat; /* 0x000114 */ - bridgereg_t _pad_000110; - - bridgereg_t b_int_mode; /* 0x00011C */ - bridgereg_t _pad_000118; - - bridgereg_t b_int_device; /* 0x000124 */ - bridgereg_t _pad_000120; - - bridgereg_t b_int_host_err; /* 0x00012C */ - bridgereg_t _pad_000128; - - struct { - bridgereg_t addr; /* 0x0001{34,,,6C} */ - bridgereg_t __pad; /* 0x0001{30,,,68} */ - } b_int_addr[8]; /* 0x000130 */ - - bridgereg_t b_err_int_view; /* 0x000174 */ - bridgereg_t _pad_000170; - - bridgereg_t b_mult_int; /* 0x00017c */ - bridgereg_t _pad_000178; - - struct { - bridgereg_t intr; /* 0x0001{84,,,BC} */ - bridgereg_t __pad; /* 0x0001{80,,,B8} */ - } b_force_always[8]; /* 0x000180 */ - - struct { - bridgereg_t intr; /* 0x0001{C4,,,FC} */ - bridgereg_t __pad; /* 0x0001{C0,,,F8} */ - } b_force_pin[8]; /* 0x0001C0 */ - - /* Device 0x000200-0x0003FF */ - struct { - bridgereg_t reg; /* 0x0002{04,,,3C} */ - bridgereg_t __pad; /* 0x0002{00,,,38} */ - } b_device[8]; /* 0x000200 */ - - struct { - bridgereg_t reg; /* 0x0002{44,,,7C} */ - bridgereg_t __pad; /* 0x0002{40,,,78} */ - } b_wr_req_buf[8]; /* 0x000240 */ - - struct { - bridgereg_t reg; /* 0x0002{84,,,8C} */ - bridgereg_t __pad; /* 0x0002{80,,,88} */ - } b_rrb_map[2]; /* 0x000280 */ -#define b_even_resp b_rrb_map[0].reg /* 0x000284 */ -#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ - - bridgereg_t b_resp_status; /* 0x000294 */ - bridgereg_t _pad_000290; - - bridgereg_t b_resp_clear; /* 0x00029C */ - bridgereg_t _pad_000298; - - bridgereg_t _pad_0002A0[24]; - - /* Xbridge only */ - struct { - bridgereg_t upper; /* 0x0003{04,,,F4} */ - bridgereg_t __pad1; /* 0x0003{00,,,F0} */ - bridgereg_t lower; /* 0x0003{0C,,,FC} */ - bridgereg_t __pad2; /* 0x0003{08,,,F8} */ - } b_buf_addr_match[16]; - - /* Performance Monitor Registers (even only) */ - struct { - bridgereg_t flush_w_touch; /* 0x000404,,,5C4 */ - bridgereg_t __pad1; /* 0x000400,,,5C0 */ - - bridgereg_t flush_wo_touch; /* 0x00040C,,,5CC */ - bridgereg_t __pad2; /* 0x000408,,,5C8 */ - - bridgereg_t inflight; /* 0x000414,,,5D4 */ - bridgereg_t __pad3; /* 0x000410,,,5D0 */ - - bridgereg_t prefetch; /* 0x00041C,,,5DC */ - bridgereg_t __pad4; /* 0x000418,,,5D8 */ - - bridgereg_t total_pci_retry; /* 0x000424,,,5E4 */ - bridgereg_t __pad5; /* 0x000420,,,5E0 */ - - bridgereg_t max_pci_retry; /* 0x00042C,,,5EC */ - bridgereg_t __pad6; /* 0x000428,,,5E8 */ - - bridgereg_t max_latency; /* 0x000434,,,5F4 */ - bridgereg_t __pad7; /* 0x000430,,,5F0 */ - - bridgereg_t clear_all; /* 0x00043C,,,5FC */ - bridgereg_t __pad8; /* 0x000438,,,5F8 */ - } b_buf_count[8]; - - char _pad_000600[0x010000 - 0x000600]; - - /* - * The Xbridge has 1024 internal ATE's and the Bridge has 128. - * Make enough room for the Xbridge ATE's and depend on runtime - * checks to limit access to bridge ATE's. - */ - - /* Internal Address Translation Entry RAM 0x010000-0x011fff */ - union { - bridge_ate_t wr; /* write-only */ - struct { - bridgereg_t rd; /* read-only */ - bridgereg_t _p_pad; - } hi; - } b_int_ate_ram[XBRIDGE_INTERNAL_ATES]; - -#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd - - /* the xbridge read path for internal ates starts at 0x12000. - * I don't believe we ever try to read the ates. - */ - /* Internal Address Translation Entry RAM LOW 0x012000-0x013fff */ - struct { - bridgereg_t rd; - bridgereg_t _p_pad; - } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES]; - - char _pad_014000[0x20000 - 0x014000]; - - /* PCI Device Configuration Spaces 0x020000-0x027FFF */ - union { /* make all access sizes available. */ - uchar_t c[0x1000 / 1]; - uint16_t s[0x1000 / 2]; - uint32_t l[0x1000 / 4]; - uint64_t d[0x1000 / 8]; - union { - uchar_t c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; - } f[8]; - } b_type0_cfg_dev[8]; /* 0x020000 */ - - /* PCI Type 1 Configuration Space 0x028000-0x028FFF */ - union { /* make all access sizes available. */ - uchar_t c[0x1000 / 1]; - uint16_t s[0x1000 / 2]; - uint32_t l[0x1000 / 4]; - uint64_t d[0x1000 / 8]; - union { - uchar_t c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; - } f[8]; - } b_type1_cfg; /* 0x028000-0x029000 */ - - char _pad_029000[0x007000]; /* 0x029000-0x030000 */ - - /* PCI Interrupt Acknowledge Cycle 0x030000 */ - union { - uchar_t c[8 / 1]; - uint16_t s[8 / 2]; - uint32_t l[8 / 4]; - uint64_t d[8 / 8]; - } b_pci_iack; /* 0x030000 */ - - uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ - - /* External Address Translation Entry RAM 0x080000-0x0FFFFF */ - bridge_ate_t b_ext_ate_ram[0x10000]; - - /* Reserved 0x100000-0x1FFFFF */ - char _pad_100000[0x200000-0x100000]; - - /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */ - union { /* make all access sizes available. */ - uchar_t c[0x100000 / 1]; - uint16_t s[0x100000 / 2]; - uint32_t l[0x100000 / 4]; - uint64_t d[0x100000 / 8]; - } b_devio_raw[10]; /* 0x200000 */ - - /* b_devio macro is a bit strange; it reflects the - * fact that the Bridge ASIC provides 2M for the - * first two DevIO windows and 1M for the other six. - */ -#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] - - /* External Flash Proms 1,0 0xC00000-0xFFFFFF */ - union { /* make all access sizes available. */ - uchar_t c[0x400000 / 1]; /* read-only */ - uint16_t s[0x400000 / 2]; /* read-write */ - uint32_t l[0x400000 / 4]; /* read-only */ - uint64_t d[0x400000 / 8]; /* read-only */ - } b_external_flash; /* 0xC00000 */ -} bridge_t; - -#endif /* CONFIG_IA64_SGI_SN1 */ - - #define berr_field berr_un.berr_st #endif /* __ASSEMBLY__ */ @@ -1428,8 +1139,7 @@ typedef volatile struct bridge_s { #define BRIDGE_ISR_ERRORS \ (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \ BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ - BRIDGE_ISR_PMU_ESIZE_FAULT|PIC_ISR_PCIX_ARB_ERR| \ - PIC_ISR_INT_RAM_PERR) + BRIDGE_ISR_PMU_ESIZE_FAULT|PIC_ISR_INT_RAM_PERR) /* * List of Errors which are fatal and kill the sytem @@ -1598,22 +1308,6 @@ typedef volatile struct bridge_s { #define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff -#ifdef SN0 -/* - * The NASID should be shifted by this amount and stored into the - * interrupt(x) register. - */ -#define BRIDGE_INT_ADDR_NASID_SHFT 8 - -/* - * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to - * memory. - */ -#define BRIDGE_INT_ADDR_DEST_IO (1 << 17) -#define BRIDGE_INT_ADDR_DEST_MEM 0 -#define BRIDGE_INT_ADDR_MASK (1 << 17) -#endif - /* Bridge device(x) register bits definition */ #define BRIDGE_DEV_ERR_LOCK_EN (1ull << 28) #define BRIDGE_DEV_PAGE_CHK_DIS (1ull << 27) @@ -1728,6 +1422,38 @@ typedef volatile struct bridge_s { #define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT /* + * Macros for Xtalk to Bridge bus (PCI) PIO + * refer to section 5.2.1 Figure 4 of the "PCI Interface Chip (PIC) Volume II + * Programmer's Reference" (Revision 0.8 as of this writing). + * + * These are PIC bridge specific. A separate set of macros was defined + * because PIC deviates from Bridge/Xbridge by not supporting a big-window + * alias for PCI I/O space, and also redefines XTALK addresses + * 0x0000C0000000L and 0x000100000000L to be PCI MEM aliases for the second + * bus. + */ + +/* XTALK addresses that map into PIC Bridge Bus addr space */ +#define PICBRIDGE0_PIO32_XTALK_ALIAS_BASE 0x000040000000L +#define PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL +#define PICBRIDGE0_PIO64_XTALK_ALIAS_BASE 0x000080000000L +#define PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL +#define PICBRIDGE1_PIO32_XTALK_ALIAS_BASE 0x0000C0000000L +#define PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT 0x0000FFFFFFFFL +#define PICBRIDGE1_PIO64_XTALK_ALIAS_BASE 0x000100000000L +#define PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT 0x00013FFFFFFFL + +/* XTALK addresses that map into PCI addresses */ +#define PICBRIDGE0_PCI_MEM32_BASE PICBRIDGE0_PIO32_XTALK_ALIAS_BASE +#define PICBRIDGE0_PCI_MEM32_LIMIT PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT +#define PICBRIDGE0_PCI_MEM64_BASE PICBRIDGE0_PIO64_XTALK_ALIAS_BASE +#define PICBRIDGE0_PCI_MEM64_LIMIT PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT +#define PICBRIDGE1_PCI_MEM32_BASE PICBRIDGE1_PIO32_XTALK_ALIAS_BASE +#define PICBRIDGE1_PCI_MEM32_LIMIT PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT +#define PICBRIDGE1_PCI_MEM64_BASE PICBRIDGE1_PIO64_XTALK_ALIAS_BASE +#define PICBRIDGE1_PCI_MEM64_LIMIT PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT + +/* * Macros for Bridge bus (PCI/GIO) to Xtalk DMA */ /* Bridge Bus DMA addresses */ @@ -1845,9 +1571,6 @@ typedef union ate_u { #define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT)) #define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT)) -#define is_xbridge(bridge) IS_XBRIDGE(bridge->b_wid_id) -#define is_pic(bridge) IS_PIC_BRIDGE(bridge->b_wid_id) - /* extern declarations */ #ifndef __ASSEMBLY__ diff --git a/include/asm-ia64/sn/pci/pci_bus_cvlink.h b/include/asm-ia64/sn/pci/pci_bus_cvlink.h index 6c4e2dfc21563..517acefde8b2f 100644 --- a/include/asm-ia64/sn/pci/pci_bus_cvlink.h +++ b/include/asm-ia64/sn/pci/pci_bus_cvlink.h @@ -4,13 +4,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_CVLINK_H #define _ASM_SN_PCI_CVLINK_H #include <asm/sn/types.h> -#include <asm/sn/hack.h> #include <asm/sn/sgi.h> #include <asm/sn/driver.h> #include <asm/sn/iograph.h> @@ -50,11 +49,11 @@ (((struct sn_widget_sysdata *)((pci_bus)->sysdata))->vhdl) struct sn_widget_sysdata { - devfs_handle_t vhdl; + vertex_hdl_t vhdl; }; struct sn_device_sysdata { - devfs_handle_t vhdl; + vertex_hdl_t vhdl; int isa64; int isPIC; volatile unsigned int *dma_buf_sync; diff --git a/include/asm-ia64/sn/pci/pci_defs.h b/include/asm-ia64/sn/pci/pci_defs.h index 2df7888e56169..73dbb4b81a0d3 100644 --- a/include/asm-ia64/sn/pci/pci_defs.h +++ b/include/asm-ia64/sn/pci/pci_defs.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCI_DEFS_H #define _ASM_SN_PCI_PCI_DEFS_H @@ -321,6 +321,112 @@ extern void pci_write(void * address, int data, int type); #ifndef __ASSEMBLY__ +#ifdef LITTLE_ENDIAN + +/* + * PCI config space definition + */ +typedef volatile struct pci_cfg_s { + uint16_t vendor_id; + uint16_t dev_id; + uint16_t cmd; + uint16_t status; + uchar_t rev; + uchar_t prog_if; + uchar_t sub_class; + uchar_t class; + uchar_t line_size; + uchar_t lt; + uchar_t hdr_type; + uchar_t bist; + uint32_t bar[6]; + uint32_t cardbus; + uint16_t subsys_vendor_id; + uint16_t subsys_dev_id; + uint32_t exp_rom; + uint32_t res[2]; + uchar_t int_line; + uchar_t int_pin; + uchar_t min_gnt; + uchar_t max_lat; +} pci_cfg_t; + +/* + * PCI Type 1 config space definition for PCI to PCI Bridges (PPBs) + */ +typedef volatile struct pci_cfg1_s { + uint16_t vendor_id; + uint16_t dev_id; + uint16_t cmd; + uint16_t status; + uchar_t rev; + uchar_t prog_if; + uchar_t sub_class; + uchar_t class; + uchar_t line_size; + uchar_t lt; + uchar_t hdr_type; + uchar_t bist; + uint32_t bar[2]; + uchar_t pri_bus_num; + uchar_t snd_bus_num; + uchar_t sub_bus_num; + uchar_t slt; + uchar_t io_base; + uchar_t io_limit; + uint16_t snd_status; + uint16_t mem_base; + uint16_t mem_limit; + uint16_t pmem_base; + uint16_t pmem_limit; + uint32_t pmem_base_upper; + uint32_t pmem_limit_upper; + uint16_t io_base_upper; + uint16_t io_limit_upper; + uint32_t res; + uint32_t exp_rom; + uchar_t int_line; + uchar_t int_pin; + uint16_t ppb_control; + +} pci_cfg1_t; + +/* + * PCI-X Capability + */ +typedef volatile struct cap_pcix_cmd_reg_s { + uint16_t data_parity_enable: 1, + enable_relaxed_order: 1, + max_mem_read_cnt: 2, + max_split: 3, + reserved1: 9; +} cap_pcix_cmd_reg_t; + +typedef volatile struct cap_pcix_stat_reg_s { + uint32_t func_num: 3, + dev_num: 5, + bus_num: 8, + bit64_device: 1, + mhz133_capable: 1, + split_complt_discard: 1, + unexpect_split_complt: 1, + device_complex: 1, + max_mem_read_cnt: 2, + max_out_split: 3, + max_cum_read: 3, + split_complt_err: 1, + reserved1: 2; +} cap_pcix_stat_reg_t; + +typedef volatile struct cap_pcix_type0_s { + uchar_t pcix_cap_id; + uchar_t pcix_cap_nxt; + cap_pcix_cmd_reg_t pcix_type0_command; + cap_pcix_stat_reg_t pcix_type0_status; +} cap_pcix_type0_t; + +#else + /* * PCI config space definition */ @@ -388,6 +494,8 @@ typedef volatile struct pci_cfg1_s { uchar_t int_line; } pci_cfg1_t; + + /* * PCI-X Capability */ @@ -422,5 +530,6 @@ typedef volatile struct cap_pcix_type0_s { cap_pcix_stat_reg_t pcix_type0_status; } cap_pcix_type0_t; +#endif #endif /* __ASSEMBLY__ */ #endif /* _ASM_SN_PCI_PCI_DEFS_H */ diff --git a/include/asm-ia64/sn/pci/pciba.h b/include/asm-ia64/sn/pci/pciba.h index f8b16a2033e99..fd62d78c57a32 100644 --- a/include/asm-ia64/sn/pci/pciba.h +++ b/include/asm-ia64/sn/pci/pciba.h @@ -3,7 +3,7 @@ * Public License. See the file "COPYING" in the main directory of * this archive for more details. * - * Copyright (C) 1997, 2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1997, 2001-2003 Silicon Graphics, Inc. All rights reserved. * */ diff --git a/include/asm-ia64/sn/pci/pcibr.h b/include/asm-ia64/sn/pci/pcibr.h index c29d13c49fb73..c9153ea71e9e4 100644 --- a/include/asm-ia64/sn/pci/pcibr.h +++ b/include/asm-ia64/sn/pci/pcibr.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCIBR_H #define _ASM_SN_PCI_PCIBR_H @@ -59,9 +59,7 @@ typedef struct pcibr_intr_s *pcibr_intr_t; * code and part number registered by pcibr_init(). */ -extern void pcibr_init(void); - -extern int pcibr_attach(devfs_handle_t); +extern int pcibr_attach(vertex_hdl_t); /* ===================================================================== * bus provider function table @@ -94,7 +92,7 @@ extern pciio_provider_t pci_pic_provider; * smarts on the part of the compilation system). */ -extern pcibr_piomap_t pcibr_piomap_alloc(devfs_handle_t dev, +extern pcibr_piomap_t pcibr_piomap_alloc(vertex_hdl_t dev, device_desc_t dev_desc, pciio_space_t space, iopaddr_t pci_addr, @@ -110,24 +108,24 @@ extern caddr_t pcibr_piomap_addr(pcibr_piomap_t piomap, extern void pcibr_piomap_done(pcibr_piomap_t piomap); -extern caddr_t pcibr_piotrans_addr(devfs_handle_t dev, +extern caddr_t pcibr_piotrans_addr(vertex_hdl_t dev, device_desc_t dev_desc, pciio_space_t space, iopaddr_t pci_addr, size_t byte_count, unsigned flags); -extern iopaddr_t pcibr_piospace_alloc(devfs_handle_t dev, +extern iopaddr_t pcibr_piospace_alloc(vertex_hdl_t dev, device_desc_t dev_desc, pciio_space_t space, size_t byte_count, size_t alignment); -extern void pcibr_piospace_free(devfs_handle_t dev, +extern void pcibr_piospace_free(vertex_hdl_t dev, pciio_space_t space, iopaddr_t pciaddr, size_t byte_count); -extern pcibr_dmamap_t pcibr_dmamap_alloc(devfs_handle_t dev, +extern pcibr_dmamap_t pcibr_dmamap_alloc(vertex_hdl_t dev, device_desc_t dev_desc, size_t byte_count_max, unsigned flags); @@ -150,109 +148,97 @@ extern void pcibr_dmamap_done(pcibr_dmamap_t dmamap); * (This node id can be different for each PCI bus.) */ -extern cnodeid_t pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl); +extern cnodeid_t pcibr_get_dmatrans_node(vertex_hdl_t pconn_vhdl); -extern iopaddr_t pcibr_dmatrans_addr(devfs_handle_t dev, +extern iopaddr_t pcibr_dmatrans_addr(vertex_hdl_t dev, device_desc_t dev_desc, paddr_t paddr, size_t byte_count, unsigned flags); -extern alenlist_t pcibr_dmatrans_list(devfs_handle_t dev, +extern alenlist_t pcibr_dmatrans_list(vertex_hdl_t dev, device_desc_t dev_desc, alenlist_t palenlist, unsigned flags); extern void pcibr_dmamap_drain(pcibr_dmamap_t map); -extern void pcibr_dmaaddr_drain(devfs_handle_t vhdl, +extern void pcibr_dmaaddr_drain(vertex_hdl_t vhdl, paddr_t addr, size_t bytes); -extern void pcibr_dmalist_drain(devfs_handle_t vhdl, +extern void pcibr_dmalist_drain(vertex_hdl_t vhdl, alenlist_t list); typedef unsigned pcibr_intr_ibit_f(pciio_info_t info, pciio_intr_line_t lines); -extern void pcibr_intr_ibit_set(devfs_handle_t, pcibr_intr_ibit_f *); +extern void pcibr_intr_ibit_set(vertex_hdl_t, pcibr_intr_ibit_f *); -extern pcibr_intr_t pcibr_intr_alloc(devfs_handle_t dev, +extern pcibr_intr_t pcibr_intr_alloc(vertex_hdl_t dev, device_desc_t dev_desc, pciio_intr_line_t lines, - devfs_handle_t owner_dev); + vertex_hdl_t owner_dev); extern void pcibr_intr_free(pcibr_intr_t intr); -#ifdef CONFIG_IA64_SGI_SN1 -extern int pcibr_intr_connect(pcibr_intr_t intr); -#else extern int pcibr_intr_connect(pcibr_intr_t intr, intr_func_t, intr_arg_t); -#endif extern void pcibr_intr_disconnect(pcibr_intr_t intr); -extern devfs_handle_t pcibr_intr_cpu_get(pcibr_intr_t intr); +extern vertex_hdl_t pcibr_intr_cpu_get(pcibr_intr_t intr); -extern void pcibr_provider_startup(devfs_handle_t pcibr); +extern void pcibr_provider_startup(vertex_hdl_t pcibr); -extern void pcibr_provider_shutdown(devfs_handle_t pcibr); +extern void pcibr_provider_shutdown(vertex_hdl_t pcibr); -extern int pcibr_reset(devfs_handle_t dev); +extern int pcibr_reset(vertex_hdl_t dev); -extern int pcibr_write_gather_flush(devfs_handle_t dev); +extern int pcibr_write_gather_flush(vertex_hdl_t dev); -extern pciio_endian_t pcibr_endian_set(devfs_handle_t dev, +extern pciio_endian_t pcibr_endian_set(vertex_hdl_t dev, pciio_endian_t device_end, pciio_endian_t desired_end); -extern pciio_priority_t pcibr_priority_set(devfs_handle_t dev, +extern pciio_priority_t pcibr_priority_set(vertex_hdl_t dev, pciio_priority_t device_prio); -extern uint64_t pcibr_config_get(devfs_handle_t conn, +extern uint64_t pcibr_config_get(vertex_hdl_t conn, unsigned reg, unsigned size); -extern void pcibr_config_set(devfs_handle_t conn, +extern void pcibr_config_set(vertex_hdl_t conn, unsigned reg, unsigned size, uint64_t value); -extern int pcibr_error_devenable(devfs_handle_t pconn_vhdl, +extern int pcibr_error_devenable(vertex_hdl_t pconn_vhdl, int error_code); -#ifdef PIC_LATER -extern pciio_slot_t pcibr_error_extract(devfs_handle_t pcibr_vhdl, - pciio_space_t *spacep, - iopaddr_t *addrp); -#endif - -extern int pcibr_wrb_flush(devfs_handle_t pconn_vhdl); -extern int pcibr_rrb_check(devfs_handle_t pconn_vhdl, +extern int pcibr_wrb_flush(vertex_hdl_t pconn_vhdl); +extern int pcibr_rrb_check(vertex_hdl_t pconn_vhdl, int *count_vchan0, int *count_vchan1, int *count_reserved, int *count_pool); -#ifndef CONFIG_IA64_SGI_SN1 -extern int pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd, +extern int pcibr_alloc_all_rrbs(vertex_hdl_t vhdl, int even_odd, int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2, int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4); -#endif typedef void -rrb_alloc_funct_f (devfs_handle_t xconn_vhdl, +rrb_alloc_funct_f (vertex_hdl_t xconn_vhdl, int *vendor_list); typedef rrb_alloc_funct_f *rrb_alloc_funct_t; -void pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, +void pcibr_set_rrb_callback(vertex_hdl_t xconn_vhdl, rrb_alloc_funct_f *func); -extern int pcibr_device_unregister(devfs_handle_t); -extern int pcibr_dma_enabled(devfs_handle_t); +extern int pcibr_device_unregister(vertex_hdl_t); +extern int pcibr_dma_enabled(vertex_hdl_t); /* * Bridge-specific flags that can be set via pcibr_device_flags_set * and cleared via pcibr_device_flags_clear. Other flags are @@ -320,7 +306,7 @@ typedef int pcibr_device_flags_t; * "flags" are defined above. NOTE: this includes turning * things *OFF* as well as turning them *ON* ... */ -extern int pcibr_device_flags_set(devfs_handle_t dev, +extern int pcibr_device_flags_set(vertex_hdl_t dev, pcibr_device_flags_t flags); /* @@ -331,7 +317,7 @@ extern int pcibr_device_flags_set(devfs_handle_t dev, * <0 on failure, which occurs when we're unable to allocate any * buffers to a channel that desires at least one buffer. */ -extern int pcibr_rrb_alloc(devfs_handle_t pconn_vhdl, +extern int pcibr_rrb_alloc(vertex_hdl_t pconn_vhdl, int *count_vchan0, int *count_vchan1); @@ -345,19 +331,15 @@ extern iopaddr_t pcibr_dmamap_pciaddr_get(pcibr_dmamap_t); extern xwidget_intr_preset_f pcibr_xintr_preset; -extern void pcibr_hints_fix_rrbs(devfs_handle_t); -extern void pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t); -extern void pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong); -extern void pcibr_hints_handsoff(devfs_handle_t); +extern void pcibr_hints_fix_rrbs(vertex_hdl_t); +extern void pcibr_hints_dualslot(vertex_hdl_t, pciio_slot_t, pciio_slot_t); +extern void pcibr_hints_subdevs(vertex_hdl_t, pciio_slot_t, ulong); +extern void pcibr_hints_handsoff(vertex_hdl_t); -#ifdef CONFIG_IA64_SGI_SN1 -typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t); -#else typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t, int); -#endif -extern void pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *); +extern void pcibr_hints_intr_bits(vertex_hdl_t, pcibr_intr_bits_f *); -extern int pcibr_asic_rev(devfs_handle_t); +extern int pcibr_asic_rev(vertex_hdl_t); #endif /* __ASSEMBLY__ */ #endif /* #if defined(__KERNEL__) */ @@ -433,7 +415,7 @@ struct pcibr_slot_info_resp_s { short resp_bs_bridge_mode; int resp_has_host; char resp_host_slot; - devfs_handle_t resp_slot_conn; + vertex_hdl_t resp_slot_conn; char resp_slot_conn_name[MAXDEVNAME]; int resp_slot_status; int resp_l1_bus_num; @@ -460,10 +442,8 @@ struct pcibr_slot_info_resp_s { bridgereg_t resp_b_int_device; bridgereg_t resp_b_int_enable; bridgereg_t resp_b_int_host; -#ifndef CONFIG_IA64_SGI_SN1 picreg_t resp_p_int_enable; picreg_t resp_p_int_host; -#endif struct pcibr_slot_func_info_resp_s { int resp_f_status; char resp_f_slot_name[MAXDEVNAME]; diff --git a/include/asm-ia64/sn/pci/pcibr_private.h b/include/asm-ia64/sn/pci/pcibr_private.h index 569aba5e2b35d..86c7ba6918423 100644 --- a/include/asm-ia64/sn/pci/pcibr_private.h +++ b/include/asm-ia64/sn/pci/pcibr_private.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCIBR_PRIVATE_H #define _ASM_SN_PCI_PCIBR_PRIVATE_H @@ -16,6 +16,7 @@ */ #include <linux/config.h> +#include <linux/pci.h> #include <asm/sn/pci/pcibr.h> #include <asm/sn/pci/pciio_private.h> #include <asm/sn/ksys/l1.h> @@ -45,7 +46,7 @@ cfg_p pcibr_slot_config_addr(bridge_t *, pciio_slot_t, int); cfg_p pcibr_func_config_addr(bridge_t *, pciio_bus_t bus, pciio_slot_t, pciio_function_t, int); unsigned pcibr_slot_config_get(bridge_t *, pciio_slot_t, int); unsigned pcibr_func_config_get(bridge_t *, pciio_slot_t, pciio_function_t, int); -void pcibr_debug(uint32_t, devfs_handle_t, char *, ...); +void pcibr_debug(uint32_t, vertex_hdl_t, char *, ...); void pcibr_slot_config_set(bridge_t *, pciio_slot_t, int, unsigned); void pcibr_func_config_set(bridge_t *, pciio_slot_t, pciio_function_t, int, unsigned); @@ -171,6 +172,7 @@ struct pcibr_intr_s { unsigned bi_ibits; /* which Bridge interrupt bit(s) */ pcibr_soft_t bi_soft; /* shortcut to soft info */ struct pcibr_intr_cbuf_s bi_ibuf; /* circular buffer of wrap ptrs */ + unsigned bi_last_intr; /* For Shub lb lost intr. bug */ }; @@ -254,11 +256,7 @@ struct pcibr_intr_list_s { struct pcibr_intr_wrap_s { pcibr_soft_t iw_soft; /* which bridge */ volatile bridgereg_t *iw_stat; /* ptr to b_int_status */ -#ifdef CONFIG_IA64_SGI_SN1 - bridgereg_t iw_intr; /* bit in b_int_status */ -#else bridgereg_t iw_ibit; /* bit in b_int_status */ -#endif pcibr_intr_list_t iw_list; /* ghostbusters! */ int iw_hdlrcnt; /* running handler count */ int iw_shared; /* if Bridge bit is shared */ @@ -293,6 +291,8 @@ struct pcibr_intr_wrap_s { #define PCIBR_BRIDGETYPE_PIC 2 #define IS_XBRIDGE_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_XBRIDGE) #define IS_PIC_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_PIC) +#define IS_PIC_BUSNUM_SOFT(ps, bus) \ + (IS_PIC_SOFT(ps) && ((ps)->bs_busnum == (bus))) #define IS_BRIDGE_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_BRIDGE) #define IS_XBRIDGE_OR_PIC_SOFT(ps) (IS_XBRIDGE_SOFT(ps) || IS_PIC_SOFT(ps)) @@ -348,13 +348,13 @@ struct pcibr_intr_wrap_s { */ struct pcibr_soft_s { - devfs_handle_t bs_conn; /* xtalk connection point */ - devfs_handle_t bs_vhdl; /* vertex owned by pcibr */ + vertex_hdl_t bs_conn; /* xtalk connection point */ + vertex_hdl_t bs_vhdl; /* vertex owned by pcibr */ uint64_t bs_int_enable; /* Mask of enabled intrs */ bridge_t *bs_base; /* PIO pointer to Bridge chip */ char *bs_name; /* hw graph name */ xwidgetnum_t bs_xid; /* Bridge's xtalk ID number */ - devfs_handle_t bs_master; /* xtalk master vertex */ + vertex_hdl_t bs_master; /* xtalk master vertex */ xwidgetnum_t bs_mxid; /* master's xtalk ID number */ pciio_slot_t bs_first_slot; /* first existing slot */ pciio_slot_t bs_last_slot; /* last existing slot */ @@ -372,9 +372,6 @@ struct pcibr_soft_s { short bs_int_ate_size; /* number of internal ates */ short bs_bridge_type; /* see defines above */ short bs_bridge_mode; /* see defines above */ -#ifdef CONFIG_IA64_SGI_SN1 -#define bs_xbridge bs_bridge_type -#endif int bs_rev_num; /* revision number of Bridge */ /* bs_dma_flags are the forced dma flags used on all DMAs. Used for @@ -382,9 +379,6 @@ struct pcibr_soft_s { */ unsigned bs_dma_flags; /* forced DMA flags */ -#ifdef CONFIG_IA64_SGI_SN1 - l1sc_t *bs_l1sc; /* io brick l1 system cntr */ -#endif moduleid_t bs_moduleid; /* io brick moduleid */ short bs_bricktype; /* io brick type */ @@ -394,7 +388,7 @@ struct pcibr_soft_s { */ spinlock_t bs_lock; - devfs_handle_t bs_noslot_conn; /* NO-SLOT connection point */ + vertex_hdl_t bs_noslot_conn; /* NO-SLOT connection point */ pcibr_info_t bs_noslot_info; struct pcibr_soft_slot_s { /* information we keep about each CFG slot */ @@ -411,7 +405,7 @@ struct pcibr_soft_s { */ int has_host; pciio_slot_t host_slot; - devfs_handle_t slot_conn; + vertex_hdl_t slot_conn; /* PCI Hot-Plug status word */ int slot_status; @@ -531,13 +525,8 @@ struct pcibr_soft_s { int bs_rrb_avail[2]; int bs_rrb_res[8]; int bs_rrb_res_dflt[8]; -#ifdef CONFIG_IA64_SGI_SN1 - int bs_rrb_valid[16]; - int bs_rrb_valid_dflt[16]; -#else int bs_rrb_valid[8][4]; int bs_rrb_valid_dflt[8][4]; -#endif struct { /* Each Bridge interrupt bit has a single XIO * interrupt channel allocated. @@ -578,7 +567,7 @@ struct pcibr_soft_s { #ifdef LATER toid_t bserr_toutid; /* Timeout started by errintr */ #endif /* LATER */ - iopaddr_t bserr_addr; /* Address where error occurred */ + iopaddr_t bserr_addr; /* Address where error occured */ uint64_t bserr_intstat; /* interrupts active at error dump */ } bs_errinfo; @@ -599,16 +588,6 @@ struct pcibr_soft_s { * in Megabytes), and they generally tend to take once and never * release. */ -#ifdef CONFIG_IA64_SGI_SN1 - struct br_pcisp_info { - iopaddr_t pci_io_base; - iopaddr_t pci_io_last; - iopaddr_t pci_swin_base; - iopaddr_t pci_swin_last; - iopaddr_t pci_mem_base; - iopaddr_t pci_mem_last; - } bs_spinfo; -#endif /* CONFIG_IA64_SGI_SN1 */ struct pciio_win_map_s bs_io_win_map; /* I/O addr space */ struct pciio_win_map_s bs_swin_map; /* Small window addr space */ struct pciio_win_map_s bs_mem_win_map; /* Memory addr space */ @@ -655,8 +634,6 @@ struct pcibr_hints_s { pcibr_intr_bits_f *ph_intr_bits; /* map PCI INT[ABCD] to Bridge Int(n) */ }; -extern int pcibr_prefetch_enable_rev, pcibr_wg_enable_rev; - /* * Number of bridge non-fatal error interrupts we can see before * we decide to disable that interrupt. @@ -689,7 +666,6 @@ extern int pcibr_prefetch_enable_rev, pcibr_wg_enable_rev; #define NEW(ptr) NEWA(ptr,1) #define DEL(ptr) DELA(ptr,1) -#ifndef CONFIG_IA64_SGI_SN1 /* * Additional PIO spaces per slot are * recorded in this structure. @@ -701,7 +677,6 @@ struct pciio_piospace_s { iopaddr_t start; /* Starting address of the PIO space */ size_t count; /* size of PIO space */ }; -#endif /* CONFIG_IA64_SGI_SN1 */ /* Use io spin locks. This ensures that all the PIO writes from a particular * CPU to a particular IO device are synched before the start of the next @@ -715,11 +690,9 @@ struct pciio_piospace_s { #define pcibr_unlock(pcibr_soft, s) #endif /* PCI_LATER */ -#ifndef CONFIG_IA64_SGI_SN1 #define PCIBR_VALID_SLOT(ps, s) (s < PCIBR_NUM_SLOTS(ps)) #define PCIBR_D64_BASE_UNSET (0xFFFFFFFFFFFFFFFF) #define PCIBR_D32_BASE_UNSET (0xFFFFFFFF) -#endif #define INFO_LBL_PCIBR_ASIC_REV "_pcibr_asic_rev" #define PCIBR_SOFT_LIST 1 @@ -728,8 +701,35 @@ typedef struct pcibr_list_s *pcibr_list_p; struct pcibr_list_s { pcibr_list_p bl_next; pcibr_soft_t bl_soft; - devfs_handle_t bl_vhdl; + vertex_hdl_t bl_vhdl; }; #endif /* PCIBR_SOFT_LIST */ + +// Devices per widget: 2 buses, 2 slots per bus, 8 functions per slot. +#define DEV_PER_WIDGET (2*2*8) + +struct sn_flush_device_list { + int bus; + int pin; + struct bar_list { + unsigned long start; + unsigned long end; + } bar_list[PCI_ROM_RESOURCE]; + unsigned long force_int_addr; + volatile unsigned long flush_addr; + spinlock_t flush_lock; +}; + +struct sn_flush_nasid_entry { + struct sn_flush_device_list **widget_p; + unsigned long iio_itte1; + unsigned long iio_itte2; + unsigned long iio_itte3; + unsigned long iio_itte4; + unsigned long iio_itte5; + unsigned long iio_itte6; + unsigned long iio_itte7; +}; + #endif /* _ASM_SN_PCI_PCIBR_PRIVATE_H */ diff --git a/include/asm-ia64/sn/pci/pciio.h b/include/asm-ia64/sn/pci/pciio.h index b48737b2800b8..e7f47d3240bc5 100644 --- a/include/asm-ia64/sn/pci/pciio.h +++ b/include/asm-ia64/sn/pci/pciio.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCIIO_H #define _ASM_SN_PCI_PCIIO_H @@ -277,7 +277,7 @@ typedef struct pciio_win_alloc_s *pciio_win_alloc_t; #define PCIIO_PIOMAP_WIN(n) (0x8+(n)) typedef pciio_piomap_t -pciio_piomap_alloc_f (devfs_handle_t dev, /* set up mapping for this device */ +pciio_piomap_alloc_f (vertex_hdl_t dev, /* set up mapping for this device */ device_desc_t dev_desc, /* device descriptor */ pciio_space_t space, /* which address space */ iopaddr_t pcipio_addr, /* starting address */ @@ -297,7 +297,7 @@ typedef void pciio_piomap_done_f (pciio_piomap_t pciio_piomap); typedef caddr_t -pciio_piotrans_addr_f (devfs_handle_t dev, /* translate for this device */ +pciio_piotrans_addr_f (vertex_hdl_t dev, /* translate for this device */ device_desc_t dev_desc, /* device descriptor */ pciio_space_t space, /* which address space */ iopaddr_t pciio_addr, /* starting address */ @@ -305,7 +305,7 @@ pciio_piotrans_addr_f (devfs_handle_t dev, /* translate for this device */ unsigned flags); typedef caddr_t -pciio_pio_addr_f (devfs_handle_t dev, /* translate for this device */ +pciio_pio_addr_f (vertex_hdl_t dev, /* translate for this device */ device_desc_t dev_desc, /* device descriptor */ pciio_space_t space, /* which address space */ iopaddr_t pciio_addr, /* starting address */ @@ -314,14 +314,14 @@ pciio_pio_addr_f (devfs_handle_t dev, /* translate for this device */ unsigned flags); typedef iopaddr_t -pciio_piospace_alloc_f (devfs_handle_t dev, /* PIO space for this device */ +pciio_piospace_alloc_f (vertex_hdl_t dev, /* PIO space for this device */ device_desc_t dev_desc, /* Device descriptor */ pciio_space_t space, /* which address space */ size_t byte_count, /* Number of bytes of space */ size_t alignment); /* Alignment of allocation */ typedef void -pciio_piospace_free_f (devfs_handle_t dev, /* Device freeing space */ +pciio_piospace_free_f (vertex_hdl_t dev, /* Device freeing space */ pciio_space_t space, /* Which space is freed */ iopaddr_t pci_addr, /* Address being freed */ size_t size); /* Size freed */ @@ -329,7 +329,7 @@ pciio_piospace_free_f (devfs_handle_t dev, /* Device freeing space */ /* DMA MANAGEMENT */ typedef pciio_dmamap_t -pciio_dmamap_alloc_f (devfs_handle_t dev, /* set up mappings for this device */ +pciio_dmamap_alloc_f (vertex_hdl_t dev, /* set up mappings for this device */ device_desc_t dev_desc, /* device descriptor */ size_t byte_count_max, /* max size of a mapping */ unsigned flags); /* defined in dma.h */ @@ -342,123 +342,107 @@ pciio_dmamap_addr_f (pciio_dmamap_t dmamap, /* use these mapping resources paddr_t paddr, /* map for this address */ size_t byte_count); /* map this many bytes */ -typedef alenlist_t -pciio_dmamap_list_f (pciio_dmamap_t dmamap, /* use these mapping resources */ - alenlist_t alenlist, /* map this address/length list */ - unsigned flags); - typedef void pciio_dmamap_done_f (pciio_dmamap_t dmamap); typedef iopaddr_t -pciio_dmatrans_addr_f (devfs_handle_t dev, /* translate for this device */ +pciio_dmatrans_addr_f (vertex_hdl_t dev, /* translate for this device */ device_desc_t dev_desc, /* device descriptor */ paddr_t paddr, /* system physical address */ size_t byte_count, /* length */ unsigned flags); /* defined in dma.h */ -typedef alenlist_t -pciio_dmatrans_list_f (devfs_handle_t dev, /* translate for this device */ - device_desc_t dev_desc, /* device descriptor */ - alenlist_t palenlist, /* system address/length list */ - unsigned flags); /* defined in dma.h */ - typedef void pciio_dmamap_drain_f (pciio_dmamap_t map); typedef void -pciio_dmaaddr_drain_f (devfs_handle_t vhdl, +pciio_dmaaddr_drain_f (vertex_hdl_t vhdl, paddr_t addr, size_t bytes); typedef void -pciio_dmalist_drain_f (devfs_handle_t vhdl, +pciio_dmalist_drain_f (vertex_hdl_t vhdl, alenlist_t list); /* INTERRUPT MANAGEMENT */ typedef pciio_intr_t -pciio_intr_alloc_f (devfs_handle_t dev, /* which PCI device */ +pciio_intr_alloc_f (vertex_hdl_t dev, /* which PCI device */ device_desc_t dev_desc, /* device descriptor */ pciio_intr_line_t lines, /* which line(s) will be used */ - devfs_handle_t owner_dev); /* owner of this intr */ + vertex_hdl_t owner_dev); /* owner of this intr */ typedef void pciio_intr_free_f (pciio_intr_t intr_hdl); -#ifdef CONFIG_IA64_SGI_SN1 -typedef int -pciio_intr_connect_f (pciio_intr_t intr_hdl); /* pciio intr resource handle */ -#else typedef int pciio_intr_connect_f (pciio_intr_t intr_hdl, intr_func_t intr_func, intr_arg_t intr_arg); /* pciio intr resource handle */ -#endif typedef void pciio_intr_disconnect_f (pciio_intr_t intr_hdl); -typedef devfs_handle_t +typedef vertex_hdl_t pciio_intr_cpu_get_f (pciio_intr_t intr_hdl); /* pciio intr resource handle */ /* CONFIGURATION MANAGEMENT */ typedef void -pciio_provider_startup_f (devfs_handle_t pciio_provider); +pciio_provider_startup_f (vertex_hdl_t pciio_provider); typedef void -pciio_provider_shutdown_f (devfs_handle_t pciio_provider); +pciio_provider_shutdown_f (vertex_hdl_t pciio_provider); typedef int -pciio_reset_f (devfs_handle_t conn); /* pci connection point */ +pciio_reset_f (vertex_hdl_t conn); /* pci connection point */ typedef int -pciio_write_gather_flush_f (devfs_handle_t dev); /* Device flushing buffers */ +pciio_write_gather_flush_f (vertex_hdl_t dev); /* Device flushing buffers */ typedef pciio_endian_t /* actual endianness */ -pciio_endian_set_f (devfs_handle_t dev, /* specify endianness for this device */ +pciio_endian_set_f (vertex_hdl_t dev, /* specify endianness for this device */ pciio_endian_t device_end, /* endianness of device */ pciio_endian_t desired_end); /* desired endianness */ typedef pciio_priority_t -pciio_priority_set_f (devfs_handle_t pcicard, +pciio_priority_set_f (vertex_hdl_t pcicard, pciio_priority_t device_prio); typedef uint64_t -pciio_config_get_f (devfs_handle_t conn, /* pci connection point */ +pciio_config_get_f (vertex_hdl_t conn, /* pci connection point */ unsigned reg, /* register byte offset */ unsigned size); /* width in bytes (1..4) */ typedef void -pciio_config_set_f (devfs_handle_t conn, /* pci connection point */ +pciio_config_set_f (vertex_hdl_t conn, /* pci connection point */ unsigned reg, /* register byte offset */ unsigned size, /* width in bytes (1..4) */ uint64_t value); /* value to store */ typedef int -pciio_error_devenable_f (devfs_handle_t pconn_vhdl, int error_code); +pciio_error_devenable_f (vertex_hdl_t pconn_vhdl, int error_code); typedef pciio_slot_t -pciio_error_extract_f (devfs_handle_t vhdl, +pciio_error_extract_f (vertex_hdl_t vhdl, pciio_space_t *spacep, iopaddr_t *addrp); typedef void -pciio_driver_reg_callback_f (devfs_handle_t conn, +pciio_driver_reg_callback_f (vertex_hdl_t conn, int key1, int key2, int error); typedef void -pciio_driver_unreg_callback_f (devfs_handle_t conn, /* pci connection point */ +pciio_driver_unreg_callback_f (vertex_hdl_t conn, /* pci connection point */ int key1, int key2, int error); typedef int -pciio_device_unregister_f (devfs_handle_t conn); +pciio_device_unregister_f (vertex_hdl_t conn); typedef int -pciio_dma_enabled_f (devfs_handle_t conn); +pciio_dma_enabled_f (vertex_hdl_t conn); /* * Adapters that provide a PCI interface adhere to this software interface. @@ -477,10 +461,8 @@ typedef struct pciio_provider_s { pciio_dmamap_alloc_f *dmamap_alloc; pciio_dmamap_free_f *dmamap_free; pciio_dmamap_addr_f *dmamap_addr; - pciio_dmamap_list_f *dmamap_list; pciio_dmamap_done_f *dmamap_done; pciio_dmatrans_addr_f *dmatrans_addr; - pciio_dmatrans_list_f *dmatrans_list; pciio_dmamap_drain_f *dmamap_drain; pciio_dmaaddr_drain_f *dmaaddr_drain; pciio_dmalist_drain_f *dmalist_drain; @@ -525,10 +507,8 @@ extern pciio_piospace_free_f pciio_piospace_free; extern pciio_dmamap_alloc_f pciio_dmamap_alloc; extern pciio_dmamap_free_f pciio_dmamap_free; extern pciio_dmamap_addr_f pciio_dmamap_addr; -extern pciio_dmamap_list_f pciio_dmamap_list; extern pciio_dmamap_done_f pciio_dmamap_done; extern pciio_dmatrans_addr_f pciio_dmatrans_addr; -extern pciio_dmatrans_list_f pciio_dmatrans_list; extern pciio_dmamap_drain_f pciio_dmamap_drain; extern pciio_dmaaddr_drain_f pciio_dmaaddr_drain; extern pciio_dmalist_drain_f pciio_dmalist_drain; @@ -580,34 +560,31 @@ pciio_driver_register (pciio_vendor_id_t vendor_id, /* card's vendor number */ unsigned flags); extern void -pciio_error_register (devfs_handle_t pconn, /* which slot */ +pciio_error_register (vertex_hdl_t pconn, /* which slot */ error_handler_f *efunc, /* function to call */ error_handler_arg_t einfo); /* first parameter */ extern void pciio_driver_unregister(char *driver_prefix); -typedef void pciio_iter_f(devfs_handle_t pconn); /* a connect point */ - -extern void pciio_iterate(char *driver_prefix, - pciio_iter_f *func); +typedef void pciio_iter_f(vertex_hdl_t pconn); /* a connect point */ /* Interfaces used by PCI Bus Providers to talk to * the Generic PCI layer. */ -extern devfs_handle_t -pciio_device_register (devfs_handle_t connectpt, /* vertex at center of bus */ - devfs_handle_t master, /* card's master ASIC (pci provider) */ +extern vertex_hdl_t +pciio_device_register (vertex_hdl_t connectpt, /* vertex at center of bus */ + vertex_hdl_t master, /* card's master ASIC (pci provider) */ pciio_slot_t slot, /* card's slot (0..?) */ pciio_function_t func, /* card's func (0..?) */ pciio_vendor_id_t vendor, /* card's vendor number */ pciio_device_id_t device); /* card's device number */ extern void -pciio_device_unregister(devfs_handle_t connectpt); +pciio_device_unregister(vertex_hdl_t connectpt); extern pciio_info_t pciio_device_info_new (pciio_info_t pciio_info, /* preallocated info struct */ - devfs_handle_t master, /* card's master ASIC (pci provider) */ + vertex_hdl_t master, /* card's master ASIC (pci provider) */ pciio_slot_t slot, /* card's slot (0..?) */ pciio_function_t func, /* card's func (0..?) */ pciio_vendor_id_t vendor, /* card's vendor number */ @@ -616,24 +593,24 @@ pciio_device_info_new (pciio_info_t pciio_info, /* preallocated info struct */ extern void pciio_device_info_free(pciio_info_t pciio_info); -extern devfs_handle_t +extern vertex_hdl_t pciio_device_info_register( - devfs_handle_t connectpt, /* vertex at center of bus */ + vertex_hdl_t connectpt, /* vertex at center of bus */ pciio_info_t pciio_info); /* details about conn point */ extern void pciio_device_info_unregister( - devfs_handle_t connectpt, /* vertex at center of bus */ + vertex_hdl_t connectpt, /* vertex at center of bus */ pciio_info_t pciio_info); /* details about conn point */ extern int pciio_device_attach( - devfs_handle_t pcicard, /* vertex created by pciio_device_register */ + vertex_hdl_t pcicard, /* vertex created by pciio_device_register */ int drv_flags); extern int pciio_device_detach( - devfs_handle_t pcicard, /* vertex created by pciio_device_register */ + vertex_hdl_t pcicard, /* vertex created by pciio_device_register */ int drv_flags); @@ -654,20 +631,12 @@ pciio_device_win_populate(pciio_win_map_t win_map, /* win map */ size_t size); /* size of free range */ /* allocate window from mapping resource */ -#ifdef CONFIG_IA64_SGI_SN1 -extern iopaddr_t -pciio_device_win_alloc(pciio_win_map_t win_map, /* win map */ - pciio_win_alloc_t win_alloc, /* opaque allocation cookie */ - size_t size, /* size of allocation */ - size_t align); /* alignment of allocation */ -#else extern iopaddr_t pciio_device_win_alloc(pciio_win_map_t win_map, /* win map */ pciio_win_alloc_t win_alloc, /* opaque allocation cookie */ size_t start, /* start unit, or 0 */ size_t size, /* size of allocation */ size_t align); /* alignment of allocation */ -#endif /* free previously allocated window */ extern void @@ -680,11 +649,11 @@ pciio_device_win_free(pciio_win_alloc_t win_alloc); /* opaque allocation cookie */ /* Generic PCI interrupt interfaces */ -extern devfs_handle_t pciio_intr_dev_get(pciio_intr_t pciio_intr); -extern devfs_handle_t pciio_intr_cpu_get(pciio_intr_t pciio_intr); +extern vertex_hdl_t pciio_intr_dev_get(pciio_intr_t pciio_intr); +extern vertex_hdl_t pciio_intr_cpu_get(pciio_intr_t pciio_intr); /* Generic PCI pio interfaces */ -extern devfs_handle_t pciio_pio_dev_get(pciio_piomap_t pciio_piomap); +extern vertex_hdl_t pciio_pio_dev_get(pciio_piomap_t pciio_piomap); extern pciio_slot_t pciio_pio_slot_get(pciio_piomap_t pciio_piomap); extern pciio_space_t pciio_pio_space_get(pciio_piomap_t pciio_piomap); extern iopaddr_t pciio_pio_pciaddr_get(pciio_piomap_t pciio_piomap); @@ -692,26 +661,26 @@ extern ulong pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap); extern caddr_t pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap); /* Generic PCI dma interfaces */ -extern devfs_handle_t pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap); +extern vertex_hdl_t pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap); /* Register/unregister PCI providers and get implementation handle */ -extern void pciio_provider_register(devfs_handle_t provider, pciio_provider_t *pciio_fns); -extern void pciio_provider_unregister(devfs_handle_t provider); -extern pciio_provider_t *pciio_provider_fns_get(devfs_handle_t provider); +extern void pciio_provider_register(vertex_hdl_t provider, pciio_provider_t *pciio_fns); +extern void pciio_provider_unregister(vertex_hdl_t provider); +extern pciio_provider_t *pciio_provider_fns_get(vertex_hdl_t provider); /* Generic pci slot information access interface */ -extern pciio_info_t pciio_info_chk(devfs_handle_t vhdl); -extern pciio_info_t pciio_info_get(devfs_handle_t vhdl); -extern pciio_info_t pciio_hostinfo_get(devfs_handle_t vhdl); -extern void pciio_info_set(devfs_handle_t vhdl, pciio_info_t widget_info); -extern devfs_handle_t pciio_info_dev_get(pciio_info_t pciio_info); -extern devfs_handle_t pciio_info_hostdev_get(pciio_info_t pciio_info); +extern pciio_info_t pciio_info_chk(vertex_hdl_t vhdl); +extern pciio_info_t pciio_info_get(vertex_hdl_t vhdl); +extern pciio_info_t pciio_hostinfo_get(vertex_hdl_t vhdl); +extern void pciio_info_set(vertex_hdl_t vhdl, pciio_info_t widget_info); +extern vertex_hdl_t pciio_info_dev_get(pciio_info_t pciio_info); +extern vertex_hdl_t pciio_info_hostdev_get(pciio_info_t pciio_info); extern pciio_bus_t pciio_info_bus_get(pciio_info_t pciio_info); extern pciio_slot_t pciio_info_slot_get(pciio_info_t pciio_info); extern pciio_function_t pciio_info_function_get(pciio_info_t pciio_info); extern pciio_vendor_id_t pciio_info_vendor_id_get(pciio_info_t pciio_info); extern pciio_device_id_t pciio_info_device_id_get(pciio_info_t pciio_info); -extern devfs_handle_t pciio_info_master_get(pciio_info_t pciio_info); +extern vertex_hdl_t pciio_info_master_get(pciio_info_t pciio_info); extern arbitrary_info_t pciio_info_mfast_get(pciio_info_t pciio_info); extern pciio_provider_t *pciio_info_pops_get(pciio_info_t pciio_info); extern error_handler_f *pciio_info_efunc_get(pciio_info_t); @@ -722,8 +691,8 @@ extern size_t pciio_info_bar_size_get(pciio_info_t, int); extern iopaddr_t pciio_info_rom_base_get(pciio_info_t); extern size_t pciio_info_rom_size_get(pciio_info_t); extern int pciio_info_type1_get(pciio_info_t); -extern int pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *); -extern int pciio_dma_enabled(devfs_handle_t); +extern int pciio_error_handler(vertex_hdl_t, int, ioerror_mode_t, ioerror_t *); +extern int pciio_dma_enabled(vertex_hdl_t); #endif /* C or C++ */ #endif /* _ASM_SN_PCI_PCIIO_H */ diff --git a/include/asm-ia64/sn/pci/pciio_private.h b/include/asm-ia64/sn/pci/pciio_private.h index 57fbd9787152d..4ae63322d60c8 100644 --- a/include/asm-ia64/sn/pci/pciio_private.h +++ b/include/asm-ia64/sn/pci/pciio_private.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCIIO_PRIVATE_H #define _ASM_SN_PCI_PCIIO_PRIVATE_H @@ -24,7 +24,7 @@ */ struct pciio_piomap_s { unsigned pp_flags; /* PCIIO_PIOMAP flags */ - devfs_handle_t pp_dev; /* associated pci card */ + vertex_hdl_t pp_dev; /* associated pci card */ pciio_slot_t pp_slot; /* which slot the card is in */ pciio_space_t pp_space; /* which address space */ iopaddr_t pp_pciaddr; /* starting offset of mapping */ @@ -37,7 +37,7 @@ struct pciio_piomap_s { */ struct pciio_dmamap_s { unsigned pd_flags; /* PCIIO_DMAMAP flags */ - devfs_handle_t pd_dev; /* associated pci card */ + vertex_hdl_t pd_dev; /* associated pci card */ pciio_slot_t pd_slot; /* which slot the card is in */ }; @@ -47,7 +47,7 @@ struct pciio_dmamap_s { struct pciio_intr_s { unsigned pi_flags; /* PCIIO_INTR flags */ - devfs_handle_t pi_dev; /* associated pci card */ + vertex_hdl_t pi_dev; /* associated pci card */ device_desc_t pi_dev_desc; /* override device descriptor */ pciio_intr_line_t pi_lines; /* which interrupt line(s) */ intr_func_t pi_func; /* handler function (when connected) */ @@ -100,13 +100,13 @@ struct pciio_win_alloc_s { struct pciio_info_s { char *c_fingerprint; - devfs_handle_t c_vertex; /* back pointer to vertex */ + vertex_hdl_t c_vertex; /* back pointer to vertex */ pciio_bus_t c_bus; /* which bus the card is in */ pciio_slot_t c_slot; /* which slot the card is in */ pciio_function_t c_func; /* which func (on multi-func cards) */ pciio_vendor_id_t c_vendor; /* PCI card "vendor" code */ pciio_device_id_t c_device; /* PCI card "device" code */ - devfs_handle_t c_master; /* PCI bus provider */ + vertex_hdl_t c_master; /* PCI bus provider */ arbitrary_info_t c_mfast; /* cached fastinfo from c_master */ pciio_provider_t *c_pops; /* cached provider from c_master */ error_handler_f *c_efunc; /* error handling function */ diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h index a6e5c30461377..6c605727ea214 100644 --- a/include/asm-ia64/sn/pda.h +++ b/include/asm-ia64/sn/pda.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_PDA_H #define _ASM_IA64_SN_PDA_H @@ -26,15 +26,6 @@ * all SN per-cpu data structures. */ -#ifdef BUS_INT_WAR -#define POLL_ENTRIES 50 -typedef struct { - int irq; - int interval; - short tick; -} sn_poll_entry_t; -#endif - typedef struct pda_s { /* Having a pointer in the begining of PDA tends to increase @@ -48,31 +39,27 @@ typedef struct pda_s { /* * Support for SN LEDs */ -#ifdef CONFIG_IA64_SGI_SN1 - volatile long *led_address; -#else volatile short *led_address; -#endif u8 led_state; u8 hb_state; /* supports blinking heartbeat leds */ + u8 shub_1_1_found; unsigned int hb_count; unsigned int idle_flag; -#ifdef CONFIG_IA64_SGI_SN2 - struct irqpda_s *p_irqpda; /* Pointer to CPU irq data */ -#endif volatile unsigned long *bedrock_rev_id; volatile unsigned long *pio_write_status_addr; volatile unsigned long *pio_shub_war_cam_addr; volatile unsigned long *mem_write_status_addr; - bteinfo_t *cpu_bte_if[BTES_PER_NODE]; /* cpu interface order */ + struct bteinfo_s *cpu_bte_if[BTES_PER_NODE]; /* cpu interface order */ -#ifdef BUS_INT_WAR - sn_poll_entry_t pda_poll_entries[POLL_ENTRIES]; - int pda_poll_entry_count; -#endif + unsigned long sn_soft_irr[4]; + unsigned long sn_in_service_ivecs[4]; + short cnodeid_to_nasid_table[NR_NODES]; + int sn_lb_int_war_ticks; + int sn_last_irq; + int sn_first_irq; } pda_t; @@ -96,5 +83,9 @@ DECLARE_PER_CPU(struct pda_s, pda_percpu); #define pdacpu(cpu) (&per_cpu(pda_percpu, cpu)) +/* + * Use this macro to test if shub 1.1 wars should be enabled + */ +#define enable_shub_wars_1_1() (pda->shub_1_1_found) #endif /* _ASM_IA64_SN_PDA_H */ diff --git a/include/asm-ia64/sn/pio.h b/include/asm-ia64/sn/pio.h index b1a0402972ced..3db61abb95008 100644 --- a/include/asm-ia64/sn/pio.h +++ b/include/asm-ia64/sn/pio.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_PIO_H #define _ASM_IA64_SN_PIO_H @@ -32,19 +32,11 @@ typedef volatile ulong* pioaddr_t; typedef struct piomap { uint pio_bus; uint pio_adap; -#ifdef LATER - iospace_t pio_iospace; -#endif int pio_flag; int pio_reg; char pio_name[7]; /* to identify the mapped device */ struct piomap *pio_next; /* dlist to link active piomap's */ struct piomap *pio_prev; /* for debug and error reporting */ -#ifdef LATER - void (*pio_errfunc)(); /* Pointer to an error function */ - /* Used only for piomaps allocated - * in user level vme driver */ -#endif iopaddr_t pio_iopmask; /* valid iop address bit mask */ iobush_t pio_bushandle; /* bus-level handle */ } piomap_t; @@ -60,54 +52,6 @@ typedef struct piomap { /* - * pio_mapalloc() - allocates a handle that specifies a mapping from kernel - * virtual to io space. The returned handle piomap is used - * with the access functions to make sure that the mapping - * to the iospace exists. - * pio_mapfree() - frees the mapping as specified in the piomap handle. - * pio_mapaddr() - returns the kv address that maps to piomap'ed io address. - */ -#ifdef LATER -extern piomap_t *pio_mapalloc(uint,uint,iospace_t*,int,char*); -extern void pio_mapfree(piomap_t*); -extern caddr_t pio_mapaddr(piomap_t*,iopaddr_t); -extern piomap_t *pio_ioaddr(int, iobush_t, iopaddr_t, piomap_t *); - -/* - * PIO access functions. - */ -extern int pio_badaddr(piomap_t*,iopaddr_t,int); -extern int pio_badaddr_val(piomap_t*,iopaddr_t,int,void*); -extern int pio_wbadaddr(piomap_t*,iopaddr_t,int); -extern int pio_wbadaddr_val(piomap_t*,iopaddr_t,int,int); -extern int pio_bcopyin(piomap_t*,iopaddr_t,void *,int, int, int); -extern int pio_bcopyout(piomap_t*,iopaddr_t,void *,int, int, int); - - -/* - * PIO RMW functions using piomap. - */ -extern void pio_orb_rmw(piomap_t*, iopaddr_t, unsigned char); -extern void pio_orh_rmw(piomap_t*, iopaddr_t, unsigned short); -extern void pio_orw_rmw(piomap_t*, iopaddr_t, unsigned long); -extern void pio_andb_rmw(piomap_t*, iopaddr_t, unsigned char); -extern void pio_andh_rmw(piomap_t*, iopaddr_t, unsigned short); -extern void pio_andw_rmw(piomap_t*, iopaddr_t, unsigned long); - - -/* - * Old RMW function interface - */ -extern void orb_rmw(volatile void*, unsigned int); -extern void orh_rmw(volatile void*, unsigned int); -extern void orw_rmw(volatile void*, unsigned int); -extern void andb_rmw(volatile void*, unsigned int); -extern void andh_rmw(volatile void*, unsigned int); -extern void andw_rmw(volatile void*, unsigned int); -#endif /* LATER */ - - -/* * piomap_t type defines */ diff --git a/include/asm-ia64/sn/pio_flush.h b/include/asm-ia64/sn/pio_flush.h deleted file mode 100644 index 194348c75c360..0000000000000 --- a/include/asm-ia64/sn/pio_flush.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved. - */ - - -#include <linux/config.h> - -#ifndef _ASM_IA64_PIO_FLUSH_H -#define _ASM_IA64_PIO_FLUSH_H - -/* - * This macro flushes all outstanding PIOs performed by this cpu to the - * intended destination SHUB. This in essence ensures that all PIO's - * issues by this cpu has landed at it's destination. - * - * This macro expects the caller: - * 1. The thread is locked. - * 2. All prior PIO operations has been fenced. - * - */ - -#if defined (CONFIG_IA64_SGI_SN) - -#include <asm/sn/pda.h> - -#if defined (CONFIG_IA64_SGI_SN2) - -#define PIO_FLUSH() \ - { \ - while ( !((volatile unsigned long) (*pda.pio_write_status_addr)) & 0x8000000000000000) { \ - udelay(5); \ - } \ - __ia64_mf_a(); \ - } - -#elif defined (CONFIG_IA64_SGI_SN1) - -/* - * For SN1 we need to first read any local Bedrock's MMR and then poll on the - * Synergy MMR. - */ -#define PIO_FLUSH() \ - { \ - (volatile unsigned long) (*pda.bedrock_rev_id); \ - while (!(volatile unsigned long) (*pda.pio_write_status_addr)) { \ - udelay(5); \ - } \ - __ia64_mf_a(); \ - } -#endif -#else -/* - * For all ARCHITECTURE type, this is a NOOP. - */ - -#define PIO_FLUSH() - -#endif - -#endif /* _ASM_IA64_PIO_FLUSH_H */ diff --git a/include/asm-ia64/sn/prio.h b/include/asm-ia64/sn/prio.h index d1f24449e676c..76b8037e5c1b9 100644 --- a/include/asm-ia64/sn/prio.h +++ b/include/asm-ia64/sn/prio.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_PRIO_H #define _ASM_IA64_SN_PRIO_H diff --git a/include/asm-ia64/sn/router.h b/include/asm-ia64/sn/router.h index 689ec31a0070e..1c280988539f5 100644 --- a/include/asm-ia64/sn/router.h +++ b/include/asm-ia64/sn/router.h @@ -5,7 +5,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_ROUTER_H @@ -494,7 +494,7 @@ typedef struct router_info_s { slotid_t ri_slotnum; /* Which slot are we in? */ router_reg_t ri_glbl_parms[GLBL_PARMS_REGS]; /* Global parms0&1 register contents*/ - devfs_handle_t ri_vertex; /* hardware graph vertex */ + vertex_hdl_t ri_vertex; /* hardware graph vertex */ router_reg_t ri_prot_conf; /* protection config. register */ int64_t ri_per_minute; /* Ticks per minute */ @@ -506,7 +506,7 @@ typedef struct router_info_s { * the bottom of the structure, below the user stuff. */ char ri_hist_type; /* histogram type */ - devfs_handle_t ri_guardian; /* guardian node for the router */ + vertex_hdl_t ri_guardian; /* guardian node for the router */ int64_t ri_last_print; /* When did we last print */ char ri_print; /* Should we print */ char ri_just_blink; /* Should we blink the LEDs */ @@ -549,7 +549,7 @@ typedef struct router_info_s { * Router info hanging in the nodepda */ typedef struct nodepda_router_info_s { - devfs_handle_t router_vhdl; /* vertex handle of the router */ + vertex_hdl_t router_vhdl; /* vertex handle of the router */ short router_port; /* port thru which we entered */ short router_portmask; moduleid_t router_module; /* module in which router is there */ @@ -593,9 +593,9 @@ typedef struct router_elt_s { */ struct { /* vertex handle for the router */ - devfs_handle_t vhdl; + vertex_hdl_t vhdl; /* guardian for this router */ - devfs_handle_t guard; + vertex_hdl_t guard; /* vector router from the guardian to the router */ net_vec_t vec; } k_elt; @@ -648,8 +648,7 @@ typedef struct router_queue_s { int router_reg_read(router_info_t *rip, int regno, router_reg_t *val); int router_reg_write(router_info_t *rip, int regno, router_reg_t val); -int router_get_info(devfs_handle_t routerv, router_info_t *, int); -int router_init(cnodeid_t cnode,int writeid, nodepda_router_info_t *npda_rip); +int router_get_info(vertex_hdl_t routerv, router_info_t *, int); int router_set_leds(router_info_t *rip); void router_print_state(router_info_t *rip, int level, void (*pf)(int, char *, ...),int print_where); @@ -658,7 +657,7 @@ void capture_router_stats(router_info_t *rip); int probe_routers(void); void get_routername(unsigned char brd_type,char *rtrname); -void router_guardians_set(devfs_handle_t hwgraph_root); +void router_guardians_set(vertex_hdl_t hwgraph_root); int router_hist_reselect(router_info_t *, int64_t); #endif /* __ASSEMBLY__ */ diff --git a/include/asm-ia64/sn/sgi.h b/include/asm-ia64/sn/sgi.h index cb716f0c6d2c2..ca9686ce5c823 100644 --- a/include/asm-ia64/sn/sgi.h +++ b/include/asm-ia64/sn/sgi.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. */ @@ -17,6 +17,13 @@ #include <asm/uaccess.h> /* for copy_??_user */ #include <linux/mm.h> #include <linux/devfs_fs_kernel.h> +#ifdef CONFIG_HWGFS_FS +#include <linux/fs.h> +#include <asm/sn/hwgfs.h> +typedef hwgfs_handle_t vertex_hdl_t; +#else +typedef devfs_handle_t vertex_hdl_t; +#endif typedef int64_t __psint_t; /* needed by klgraph.c */ @@ -50,9 +57,8 @@ typedef enum graph_error_e { typedef uint64_t vhandl_t; -#ifndef NBPP -#define NBPP 4096 -#endif +#define NBPP PAGE_SIZE +#define _PAGESZ PAGE_SIZE #ifndef D_MP #define D_MP 1 @@ -66,10 +72,6 @@ typedef uint64_t vhandl_t; #define NBPC 0 #endif -#ifndef _PAGESZ -#define _PAGESZ 4096 -#endif - typedef uint64_t mrlock_t; /* needed by devsupport.c */ #define HUB_PIO_CONVEYOR 0x1 @@ -141,12 +143,6 @@ mutex_spinlock(spinlock_t *sem) { #define PRINT_PANIC panic -#ifdef CONFIG_SMP -#define cpu_enabled(cpu) (test_bit(cpu, &cpu_online_map)) -#else -#define cpu_enabled(cpu) (1) -#endif - /* print_register() defs */ /* @@ -172,6 +168,35 @@ struct reg_desc { extern void print_register(unsigned long long, struct reg_desc *); -#include <asm/sn/hack.h> /* for now */ +/****************************************** + * Definitions that do not exist in linux * + ******************************************/ + +typedef int cred_t; /* This is for compilation reasons */ +struct cred { int x; }; + + +#define DELAY(a) + +/************************************************ + * Routines redefined to use linux equivalents. * + ************************************************/ + +/* #define FIXME(s) printk("FIXME: [ %s ] in %s at %s:%d\n", s, __FUNCTION__, __FILE__, __LINE__) */ + +#define FIXME(s) + +/* move to stubs.c yet */ +#define dev_to_vhdl(dev) 0 +#define get_timestamp() 0 +#define us_delay(a) +#define v_mapphys(a,b,c) 0 // printk("Fixme: v_mapphys - soft->base 0x%p\n", b); +#define splhi() 0 +#define splx(s) + +extern void * snia_kmem_alloc_node(register size_t, register int, cnodeid_t); +extern void * snia_kmem_zalloc(size_t, int); +extern void * snia_kmem_zalloc_node(register size_t, register int, cnodeid_t ); +extern int is_specified(char *); #endif /* _ASM_IA64_SN_SGI_H */ diff --git a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h index b66624df64933..82bc2cb203502 100644 --- a/include/asm-ia64/sn/simulator.h +++ b/include/asm-ia64/sn/simulator.h @@ -5,7 +5,7 @@ * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #include <linux/config.h> diff --git a/include/asm-ia64/sn/slotnum.h b/include/asm-ia64/sn/slotnum.h index 680ae79fb94f5..dff21f3fb6b92 100644 --- a/include/asm-ia64/sn/slotnum.h +++ b/include/asm-ia64/sn/slotnum.h @@ -4,23 +4,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SLOTNUM_H #define _ASM_IA64_SN_SLOTNUM_H -#include <linux/config.h> typedef unsigned char slotid_t; -#if defined (CONFIG_IA64_SGI_SN1) -#include <asm/sn/sn1/slotnum.h> -#elif defined (CONFIG_IA64_SGI_SN2) #include <asm/sn/sn2/slotnum.h> -#else - -#error <<BOMB! slotnum defined only for SN0 and SN1 >> - -#endif /* !CONFIG_IA64_SGI_SN1 */ #endif /* _ASM_IA64_SN_SLOTNUM_H */ diff --git a/include/asm-ia64/sn/sn1/addrs.h b/include/asm-ia64/sn/sn1/addrs.h deleted file mode 100644 index 3f12cb5da8e46..0000000000000 --- a/include/asm-ia64/sn/sn1/addrs.h +++ /dev/null @@ -1,275 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_SN1_ADDRS_H -#define _ASM_IA64_SN_SN1_ADDRS_H - -#include <linux/config.h> - -#ifdef CONFIG_IA64_SGI_SN1 -/* - * SN1 (on a TRex) Address map - * - * This file contains a set of definitions and macros which are used - * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC, - * and UNCAC) used by the SN1 architecture. It also contains addresses - * for "major" statically locatable PROM/Kernel data structures, such as - * the partition table, the configuration data structure, etc. - * We make an implicit assumption that the processor using this file - * follows the R12K's provisions for specifying uncached attributes; - * should this change, the base registers may very well become processor- - * dependent. - * - * For more information on the address spaces, see the "Local Resources" - * chapter of the Hub specification. - * - * NOTE: This header file is included both by C and by assembler source - * files. Please bracket any language-dependent definitions - * appropriately. - */ - - -/* - * Some of the macros here need to be casted to appropriate types when used - * from C. They definitely must not be casted from assembly language so we - * use some new ANSI preprocessor stuff to paste these on where needed. - */ - -#define CACHEABLE_MEM_SPACE 0xe000000000000000 -#define CAC_BASE CACHEABLE_MEM_SPACE -#define HSPEC_BASE 0xc0000b0000000000 -#define HSPEC_SWIZ_BASE 0xc000030000000000 -#define IO_BASE 0xc0000a0000000000 -#define IO_SWIZ_BASE 0xc000020000000000 -#define MSPEC_BASE 0xc000090000000000 -#define UNCAC_BASE 0xc000000000000000 -#define TO_PHYS_MASK 0x000000ffffffffff - -#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) - - -/* - * The following couple of definitions will eventually need to be variables, - * since the amount of address space assigned to each node depends on - * whether the system is running in N-mode (more nodes with less memory) - * or M-mode (fewer nodes with more memory). We expect that it will - * be a while before we need to make this decision dynamically, though, - * so for now we just use defines bracketed by an ifdef. - */ - -#if defined(N_MODE) - -#define NODE_SIZE_BITS 32 -#define BWIN_SIZE_BITS 28 - -#define NASID_BITS 8 -#define NASID_BITMASK (0xffLL) -#define NASID_SHFT 32 -#define NASID_META_BITS 1 -#define NASID_LOCAL_BITS 7 - -#define BDDIR_UPPER_MASK (UINT64_CAST 0x1ffffff << 4) -#define BDECC_UPPER_MASK (UINT64_CAST 0x1fffffff ) - -#else /* !defined(N_MODE), assume that M-mode is desired */ - -#define NODE_SIZE_BITS 33 -#define BWIN_SIZE_BITS 29 - -#define NASID_BITMASK (0x7fLL) -#define NASID_BITS 7 -#define NASID_SHFT 33 -#define NASID_META_BITS 0 -#define NASID_LOCAL_BITS 7 - -#define BDDIR_UPPER_MASK (UINT64_CAST 0x3ffffff << 4) -#define BDECC_UPPER_MASK (UINT64_CAST 0x3fffffff) - -#endif /* defined(N_MODE) */ - -#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS) - -#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT) -#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ - NASID_SHFT) & NASID_BITMASK) - -#ifndef __ASSEMBLY__ -#define NODE_SWIN_BASE(nasid, widget) \ - ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ - : RAW_NODE_SWIN_BASE(nasid, widget)) -#else -#define NODE_SWIN_BASE(nasid, widget) \ - (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) -#endif /* __ASSEMBLY__ */ - -/* - * The following definitions pertain to the IO special address - * space. They define the location of the big and little windows - * of any given node. - */ - -#define BWIN_INDEX_BITS 3 -#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS) -#define BWIN_SIZEMASK (BWIN_SIZE - 1) -#define BWIN_WIDGET_MASK 0x7 -#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) -#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ - (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) - -#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) -#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) -/* - * Verify if addr belongs to large window address of node with "nasid" - * - * - * NOTE: "addr" is expected to be XKPHYS address, and NOT physical - * address - * - * - */ - -#define NODE_BWIN_ADDR(nasid, addr) \ - (((addr) >= NODE_BWIN_BASE0(nasid)) && \ - ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \ - BWIN_SIZE))) - -/* - * The following define the major position-independent aliases used - * in SN1. - * CALIAS -- Varies in size, points to the first n bytes of memory - * on the reader's node. - */ - -#define CALIAS_BASE CAC_BASE - - - -#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \ - ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) - -#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid))) - - - -/* - * needed by symmon so it needs to be outside #if PROM - * (see also POD_ELSCSIZE) - */ -#define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x020e0000) -#define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x020e0800) -#define IP27PROM_ELSC_BASE_C PHYS_TO_K0(0x020e1000) -#define IP27PROM_ELSC_BASE_D PHYS_TO_K0(0x020e1800) -#define IP27PROM_ELSC_SHFT 11 -#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT) - -#define FREEMEM_BASE PHYS_TO_K0(0x4000000) - -#define IO6PROM_STACK_SHFT 14 /* stack per cpu */ -#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT) - - -#define KL_UART_BASE LOCAL_HSPEC(HSPEC_UART_0) /* base of UART regs */ -#define KL_UART_CMD LOCAL_HSPEC(HSPEC_UART_0) /* UART command reg */ -#define KL_UART_DATA LOCAL_HSPEC(HSPEC_UART_1) /* UART data reg */ - -#if !__ASSEMBLY__ -/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc - * CACHE_ERR_SP_PTR could either contain an address to the stack, or - * the stack could start at CACHE_ERR_SP_PTR - */ -#define CACHE_ERR_EFRAME 0x400 - -#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE) -#define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */ -#define CACHE_ERR_IBASE_PTR (0x1000 - 40) -#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16) -#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME) - -#endif /* !__ASSEMBLY__ */ - - - -#define _ARCSPROM - -#ifdef _STANDALONE - -/* - * The PROM needs to pass the device base address and the - * device pci cfg space address to the device drivers during - * install. The COMPONENT->Key field is used for this purpose. - * Macros needed by SN1 device drivers to convert the - * COMPONENT->Key field to the respective base address. - * Key field looks as follows: - * - * +----------------------------------------------------+ - * |devnasid | widget |pciid |hubwidid|hstnasid | adap | - * | 2 | 1 | 1 | 1 | 2 | 1 | - * +----------------------------------------------------+ - * | | | | | | | - * 64 48 40 32 24 8 0 - * - * These are used by standalone drivers till the io infrastructure - * is in place. - */ - -#ifndef __ASSEMBLY__ - -#define uchar unsigned char - -#define KEY_DEVNASID_SHFT 48 -#define KEY_WIDID_SHFT 40 -#define KEY_PCIID_SHFT 32 -#define KEY_HUBWID_SHFT 24 -#define KEY_HSTNASID_SHFT 8 - -#define MK_SN0_KEY(nasid, widid, pciid) \ - ((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\ - ((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\ - ((__psunsigned_t)pciid) << KEY_PCIID_SHFT) - -#define ADD_HUBWID_KEY(key,hubwid)\ - (key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT)) - -#define ADD_HSTNASID_KEY(key,hstnasid)\ - (key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT)) - -#define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT)) -#define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT)) -#define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT)) -#define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT)) -#define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT)) - -#define PCI_64_TARGID_SHFT 60 - -#define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ - GET_WIDID_FROM_KEY(key))\ - | BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key))) - -#define GET_PCICFGBASE_FROM_KEY(key) \ - (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ - GET_WIDID_FROM_KEY(key))\ - | BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key))) - -#define GET_WIDBASE_FROM_KEY(key) \ - (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ - GET_WIDID_FROM_KEY(key))) - -#define PUT_INSTALL_STATUS(c,s) c->Revision = s -#define GET_INSTALL_STATUS(c) c->Revision - -#endif /* __ASSEMBLY__ */ - -#endif /* _STANDALONE */ -#endif /* CONFIG_IA64_SGI_SN1 */ - -#endif /* _ASM_IA64_SN_SN1_ADDRS_H */ diff --git a/include/asm-ia64/sn/sn1/arch.h b/include/asm-ia64/sn/sn1/arch.h deleted file mode 100644 index a91b4bcbee14f..0000000000000 --- a/include/asm-ia64/sn/sn1/arch.h +++ /dev/null @@ -1,89 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_ARCH_H -#define _ASM_IA64_SN_SN1_ARCH_H - -#if defined(N_MODE) -#error "ERROR constants defined only for M-mode" -#endif - -#include <linux/threads.h> -#include <asm/types.h> - -#define CPUS_PER_NODE 4 /* CPUs on a single hub */ -#define CPUS_PER_SUBNODE 2 /* CPUs on a single hub PI */ - -/* - * This is the maximum number of NASIDS that can be present in a system. - * This include ALL nodes in ALL partitions connected via NUMALINK. - * (Highest NASID plus one.) - */ -#define MAX_NASIDS 128 - -/* - * This is the maximum number of nodes that can be part of a kernel. - * Effectively, it's the maximum number of compact node ids (cnodeid_t). - * This is not necessarily the same as MAX_NASIDS. - */ -#define MAX_COMPACT_NODES 128 - -/* - * MAX_REGIONS refers to the maximum number of hardware partitioned regions. - */ -#define MAX_REGIONS 64 -#define MAX_NONPREMIUM_REGIONS 16 -#define MAX_PREMIUM_REGIONS MAX_REGIONS - -/* - * Slot constants for IP35 - */ - -#define MAX_MEM_SLOTS 8 /* max slots per node */ - -#if defined(N_MODE) -#error "N-mode not supported" -#endif - -#define SLOT_SHIFT (30) -#define SLOT_MIN_MEM_SIZE (64*1024*1024) - - -/* - * MAX_PARITIONS refers to the maximum number of logically defined - * partitions the system can support. - */ -#define MAX_PARTITIONS MAX_REGIONS - - -#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8) - -/* - * New stuff in here from Irix sys/pfdat.h. - */ -#define SLOT_PFNSHIFT (SLOT_SHIFT - PAGE_SHIFT) -#define PFN_NASIDSHFT (NASID_SHFT - PAGE_SHIFT) -#define slot_getbasepfn(node,slot) (mkpfn(COMPACT_TO_NASID_NODEID(node), slot<<SLOT_PFNSHIFT)) -#define mkpfn(nasid, off) (((pfn_t)(nasid) << PFN_NASIDSHFT) | (off)) - - - -/* - * two PIs per bedrock, two CPUs per PI - */ -#define NUM_SUBNODES 2 -#define SUBNODE_SHFT 1 -#define SUBNODE_MASK (0x1 << SUBNODE_SHFT) -#define LOCALCPU_SHFT 0 -#define LOCALCPU_MASK (0x1 << LOCALCPU_SHFT) -#define SUBNODE(slice) (((slice) & SUBNODE_MASK) >> SUBNODE_SHFT) -#define LOCALCPU(slice) (((slice) & LOCALCPU_MASK) >> LOCALCPU_SHFT) -#define TO_SLICE(subn, local) (((subn) << SUBNODE_SHFT) | \ - ((local) << LOCALCPU_SHFT)) - -#endif /* _ASM_IA64_SN_SN1_ARCH_H */ diff --git a/include/asm-ia64/sn/sn1/bedrock.h b/include/asm-ia64/sn/sn1/bedrock.h deleted file mode 100644 index d2e8e04079640..0000000000000 --- a/include/asm-ia64/sn/sn1/bedrock.h +++ /dev/null @@ -1,74 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_SN1_BEDROCK_H -#define _ASM_IA64_SN_SN1_BEDROCK_H - - -/* The secret password; used to release protection */ -#define HUB_PASSWORD 0x53474972756c6573ull - -#define CHIPID_HUB 0x3012 -#define CHIPID_ROUTER 0x3017 - -#define BEDROCK_REV_1_0 1 -#define BEDROCK_REV_1_1 2 - -#define MAX_HUB_PATH 80 - -#include <asm/sn/arch.h> -#include <asm/sn/sn1/addrs.h> -#include <asm/sn/sn1/hubpi.h> -#include <asm/sn/sn1/hubmd.h> -#include <asm/sn/sn1/hubio.h> -#include <asm/sn/sn1/hubni.h> -#include <asm/sn/sn1/hublb.h> -#include <asm/sn/sn1/hubxb.h> -#include <asm/sn/sn1/hubpi_next.h> -#include <asm/sn/sn1/hubmd_next.h> -#include <asm/sn/sn1/hubio_next.h> -#include <asm/sn/sn1/hubni_next.h> -#include <asm/sn/sn1/hublb_next.h> -#include <asm/sn/sn1/hubxb_next.h> - -/* Translation of uncached attributes */ -#define UATTR_HSPEC 0 -#define UATTR_IO 1 -#define UATTR_MSPEC 2 -#define UATTR_UNCAC 3 - -#if __ASSEMBLY__ - -/* - * Get nasid into register, r (uses at) - */ -#define GET_NASID_ASM(r) \ - dli r, LOCAL_HUB_ADDR(LB_REV_ID); \ - ld r, (r); \ - and r, LRI_NODEID_MASK; \ - dsrl r, LRI_NODEID_SHFT - -#endif /* __ASSEMBLY__ */ - -#ifndef __ASSEMBLY__ - -#include <asm/sn/xtalk/xwidget.h> - -/* hub-as-widget iograph info, labelled by INFO_LBL_XWIDGET */ -typedef struct v_hub_s *v_hub_t; -typedef uint64_t rtc_time_t; - -struct nodepda_s; -int hub_check_pci_equiv(void *addra, void *addrb); -void capture_hub_stats(cnodeid_t, struct nodepda_s *); -void init_hub_stats(cnodeid_t, struct nodepda_s *); - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_IA64_SN_SN1_BEDROCK_H */ diff --git a/include/asm-ia64/sn/sn1/hubdev.h b/include/asm-ia64/sn/sn1/hubdev.h deleted file mode 100644 index d2108402ea959..0000000000000 --- a/include/asm-ia64/sn/sn1/hubdev.h +++ /dev/null @@ -1,21 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_SN1_HUBDEV_H -#define _ASM_IA64_SN_SN1_HUBDEV_H - -extern void hubdev_init(void); -extern void hubdev_register(int (*attach_method)(devfs_handle_t)); -extern int hubdev_unregister(int (*attach_method)(devfs_handle_t)); -extern int hubdev_docallouts(devfs_handle_t hub); - -extern caddr_t hubdev_prombase_get(devfs_handle_t hub); -extern cnodeid_t hubdev_cnodeid_get(devfs_handle_t hub); - -#endif /* _ASM_IA64_SN_SN1_HUBDEV_H */ diff --git a/include/asm-ia64/sn/sn1/hubio.h b/include/asm-ia64/sn/sn1/hubio.h deleted file mode 100644 index 7851fe4f7aac6..0000000000000 --- a/include/asm-ia64/sn/sn1/hubio.h +++ /dev/null @@ -1,5016 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ - -/************************************************************************ - * * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * - * * - * This file is created by an automated script. Any (minimal) changes * - * made manually to this file should be made with care. * - * * - * MAKE ALL ADDITIONS TO THE END OF THIS FILE * - * * - ************************************************************************/ - - -#ifndef _ASM_IA64_SN_SN1_HUBIO_H -#define _ASM_IA64_SN_SN1_HUBIO_H - - -#define IIO_WID 0x00400000 /* - * Crosstalk Widget - * Identification This - * register is also - * accessible from - * Crosstalk at - * address 0x0. - */ - - - -#define IIO_WSTAT 0x00400008 /* - * Crosstalk Widget - * Status - */ - - - -#define IIO_WCR 0x00400020 /* - * Crosstalk Widget - * Control Register - */ - - - -#define IIO_ILAPR 0x00400100 /* - * IO Local Access - * Protection Register - */ - - - -#define IIO_ILAPO 0x00400108 /* - * IO Local Access - * Protection Override - */ - - - -#define IIO_IOWA 0x00400110 /* - * IO Outbound Widget - * Access - */ - - - -#define IIO_IIWA 0x00400118 /* - * IO Inbound Widget - * Access - */ - - - -#define IIO_IIDEM 0x00400120 /* - * IO Inbound Device - * Error Mask - */ - - - -#define IIO_ILCSR 0x00400128 /* - * IO LLP Control and - * Status Register - */ - - - -#define IIO_ILLR 0x00400130 /* IO LLP Log Register */ - - - -#define IIO_IIDSR 0x00400138 /* - * IO Interrupt - * Destination - */ - - - -#define IIO_IGFX0 0x00400140 /* - * IO Graphics - * Node-Widget Map 0 - */ - - - -#define IIO_IGFX1 0x00400148 /* - * IO Graphics - * Node-Widget Map 1 - */ - - - -#define IIO_ISCR0 0x00400150 /* - * IO Scratch Register - * 0 - */ - - - -#define IIO_ISCR1 0x00400158 /* - * IO Scratch Register - * 1 - */ - - - -#define IIO_ITTE1 0x00400160 /* - * IO Translation - * Table Entry 1 - */ - - - -#define IIO_ITTE2 0x00400168 /* - * IO Translation - * Table Entry 2 - */ - - - -#define IIO_ITTE3 0x00400170 /* - * IO Translation - * Table Entry 3 - */ - - - -#define IIO_ITTE4 0x00400178 /* - * IO Translation - * Table Entry 4 - */ - - - -#define IIO_ITTE5 0x00400180 /* - * IO Translation - * Table Entry 5 - */ - - - -#define IIO_ITTE6 0x00400188 /* - * IO Translation - * Table Entry 6 - */ - - - -#define IIO_ITTE7 0x00400190 /* - * IO Translation - * Table Entry 7 - */ - - - -#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */ - - - -#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */ - - - -#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */ - - - -#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */ - - - -#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */ - - - -#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */ - - - -#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */ - - - -#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */ - - - -#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */ - - - -#define IIO_IXCC 0x004001E0 /* - * IO Crosstalk Credit - * Count Timeout - */ - - - -#define IIO_IMEM 0x004001E8 /* - * IO Miscellaneous - * Error Mask - */ - - - -#define IIO_IXTT 0x004001F0 /* - * IO Crosstalk - * Timeout Threshold - */ - - - -#define IIO_IECLR 0x004001F8 /* - * IO Error Clear - * Register - */ - - - -#define IIO_IBCR 0x00400200 /* - * IO BTE Control - * Register - */ - - - -#define IIO_IXSM 0x00400208 /* - * IO Crosstalk - * Spurious Message - */ - - - -#define IIO_IXSS 0x00400210 /* - * IO Crosstalk - * Spurious Sideband - */ - - - -#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */ - - - -#define IIO_IIEPH1 0x00400220 /* - * IO Incoming Error - * Packet Header, Part - * 1 - */ - - - -#define IIO_IIEPH2 0x00400228 /* - * IO Incoming Error - * Packet Header, Part - * 2 - */ - - - -#define IIO_IPCA 0x00400300 /* - * IO PRB Counter - * Adjust - */ - - - -#define IIO_IPRTE0 0x00400308 /* - * IO PIO Read Address - * Table Entry 0 - */ - - - -#define IIO_IPRTE1 0x00400310 /* - * IO PIO Read Address - * Table Entry 1 - */ - - - -#define IIO_IPRTE2 0x00400318 /* - * IO PIO Read Address - * Table Entry 2 - */ - - - -#define IIO_IPRTE3 0x00400320 /* - * IO PIO Read Address - * Table Entry 3 - */ - - - -#define IIO_IPRTE4 0x00400328 /* - * IO PIO Read Address - * Table Entry 4 - */ - - - -#define IIO_IPRTE5 0x00400330 /* - * IO PIO Read Address - * Table Entry 5 - */ - - - -#define IIO_IPRTE6 0x00400338 /* - * IO PIO Read Address - * Table Entry 6 - */ - - - -#define IIO_IPRTE7 0x00400340 /* - * IO PIO Read Address - * Table Entry 7 - */ - - - -#define IIO_IPDR 0x00400388 /* - * IO PIO Deallocation - * Register - */ - - - -#define IIO_ICDR 0x00400390 /* - * IO CRB Entry - * Deallocation - * Register - */ - - - -#define IIO_IFDR 0x00400398 /* - * IO IOQ FIFO Depth - * Register - */ - - - -#define IIO_IIAP 0x004003A0 /* - * IO IIQ Arbitration - * Parameters - */ - - - -#define IIO_ICMR 0x004003A8 /* - * IO CRB Management - * Register - */ - - - -#define IIO_ICCR 0x004003B0 /* - * IO CRB Control - * Register - */ - - - -#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */ - - - -#define IIO_ICTP 0x004003C0 /* - * IO CRB Timeout - * Prescalar - */ - - - -#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */ - - - -#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */ - - - -#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */ - - - -#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */ - - - -#define IIO_ICRB1_A 0x00400420 /* IO CRB Entry 1_A */ - - - -#define IIO_ICRB1_B 0x00400428 /* IO CRB Entry 1_B */ - - - -#define IIO_ICRB1_C 0x00400430 /* IO CRB Entry 1_C */ - - - -#define IIO_ICRB1_D 0x00400438 /* IO CRB Entry 1_D */ - - - -#define IIO_ICRB2_A 0x00400440 /* IO CRB Entry 2_A */ - - - -#define IIO_ICRB2_B 0x00400448 /* IO CRB Entry 2_B */ - - - -#define IIO_ICRB2_C 0x00400450 /* IO CRB Entry 2_C */ - - - -#define IIO_ICRB2_D 0x00400458 /* IO CRB Entry 2_D */ - - - -#define IIO_ICRB3_A 0x00400460 /* IO CRB Entry 3_A */ - - - -#define IIO_ICRB3_B 0x00400468 /* IO CRB Entry 3_B */ - - - -#define IIO_ICRB3_C 0x00400470 /* IO CRB Entry 3_C */ - - - -#define IIO_ICRB3_D 0x00400478 /* IO CRB Entry 3_D */ - - - -#define IIO_ICRB4_A 0x00400480 /* IO CRB Entry 4_A */ - - - -#define IIO_ICRB4_B 0x00400488 /* IO CRB Entry 4_B */ - - - -#define IIO_ICRB4_C 0x00400490 /* IO CRB Entry 4_C */ - - - -#define IIO_ICRB4_D 0x00400498 /* IO CRB Entry 4_D */ - - - -#define IIO_ICRB5_A 0x004004A0 /* IO CRB Entry 5_A */ - - - -#define IIO_ICRB5_B 0x004004A8 /* IO CRB Entry 5_B */ - - - -#define IIO_ICRB5_C 0x004004B0 /* IO CRB Entry 5_C */ - - - -#define IIO_ICRB5_D 0x004004B8 /* IO CRB Entry 5_D */ - - - -#define IIO_ICRB6_A 0x004004C0 /* IO CRB Entry 6_A */ - - - -#define IIO_ICRB6_B 0x004004C8 /* IO CRB Entry 6_B */ - - - -#define IIO_ICRB6_C 0x004004D0 /* IO CRB Entry 6_C */ - - - -#define IIO_ICRB6_D 0x004004D8 /* IO CRB Entry 6_D */ - - - -#define IIO_ICRB7_A 0x004004E0 /* IO CRB Entry 7_A */ - - - -#define IIO_ICRB7_B 0x004004E8 /* IO CRB Entry 7_B */ - - - -#define IIO_ICRB7_C 0x004004F0 /* IO CRB Entry 7_C */ - - - -#define IIO_ICRB7_D 0x004004F8 /* IO CRB Entry 7_D */ - - - -#define IIO_ICRB8_A 0x00400500 /* IO CRB Entry 8_A */ - - - -#define IIO_ICRB8_B 0x00400508 /* IO CRB Entry 8_B */ - - - -#define IIO_ICRB8_C 0x00400510 /* IO CRB Entry 8_C */ - - - -#define IIO_ICRB8_D 0x00400518 /* IO CRB Entry 8_D */ - - - -#define IIO_ICRB9_A 0x00400520 /* IO CRB Entry 9_A */ - - - -#define IIO_ICRB9_B 0x00400528 /* IO CRB Entry 9_B */ - - - -#define IIO_ICRB9_C 0x00400530 /* IO CRB Entry 9_C */ - - - -#define IIO_ICRB9_D 0x00400538 /* IO CRB Entry 9_D */ - - - -#define IIO_ICRBA_A 0x00400540 /* IO CRB Entry A_A */ - - - -#define IIO_ICRBA_B 0x00400548 /* IO CRB Entry A_B */ - - - -#define IIO_ICRBA_C 0x00400550 /* IO CRB Entry A_C */ - - - -#define IIO_ICRBA_D 0x00400558 /* IO CRB Entry A_D */ - - - -#define IIO_ICRBB_A 0x00400560 /* IO CRB Entry B_A */ - - - -#define IIO_ICRBB_B 0x00400568 /* IO CRB Entry B_B */ - - - -#define IIO_ICRBB_C 0x00400570 /* IO CRB Entry B_C */ - - - -#define IIO_ICRBB_D 0x00400578 /* IO CRB Entry B_D */ - - - -#define IIO_ICRBC_A 0x00400580 /* IO CRB Entry C_A */ - - - -#define IIO_ICRBC_B 0x00400588 /* IO CRB Entry C_B */ - - - -#define IIO_ICRBC_C 0x00400590 /* IO CRB Entry C_C */ - - - -#define IIO_ICRBC_D 0x00400598 /* IO CRB Entry C_D */ - - - -#define IIO_ICRBD_A 0x004005A0 /* IO CRB Entry D_A */ - - - -#define IIO_ICRBD_B 0x004005A8 /* IO CRB Entry D_B */ - - - -#define IIO_ICRBD_C 0x004005B0 /* IO CRB Entry D_C */ - - - -#define IIO_ICRBD_D 0x004005B8 /* IO CRB Entry D_D */ - - - -#define IIO_ICRBE_A 0x004005C0 /* IO CRB Entry E_A */ - - - -#define IIO_ICRBE_B 0x004005C8 /* IO CRB Entry E_B */ - - - -#define IIO_ICRBE_C 0x004005D0 /* IO CRB Entry E_C */ - - - -#define IIO_ICRBE_D 0x004005D8 /* IO CRB Entry E_D */ - - - -#define IIO_ICSML 0x00400600 /* - * IO CRB Spurious - * Message Low - */ - - - -#define IIO_ICSMH 0x00400608 /* - * IO CRB Spurious - * Message High - */ - - - -#define IIO_IDBSS 0x00400610 /* - * IO Debug Submenu - * Select - */ - - - -#define IIO_IBLS0 0x00410000 /* - * IO BTE Length - * Status 0 - */ - - - -#define IIO_IBSA0 0x00410008 /* - * IO BTE Source - * Address 0 - */ - - - -#define IIO_IBDA0 0x00410010 /* - * IO BTE Destination - * Address 0 - */ - - - -#define IIO_IBCT0 0x00410018 /* - * IO BTE Control - * Terminate 0 - */ - - - -#define IIO_IBNA0 0x00410020 /* - * IO BTE Notification - * Address 0 - */ - - - -#define IIO_IBIA0 0x00410028 /* - * IO BTE Interrupt - * Address 0 - */ - - - -#define IIO_IBLS1 0x00420000 /* - * IO BTE Length - * Status 1 - */ - - - -#define IIO_IBSA1 0x00420008 /* - * IO BTE Source - * Address 1 - */ - - - -#define IIO_IBDA1 0x00420010 /* - * IO BTE Destination - * Address 1 - */ - - - -#define IIO_IBCT1 0x00420018 /* - * IO BTE Control - * Terminate 1 - */ - - - -#define IIO_IBNA1 0x00420020 /* - * IO BTE Notification - * Address 1 - */ - - - -#define IIO_IBIA1 0x00420028 /* - * IO BTE Interrupt - * Address 1 - */ - - - -#define IIO_IPCR 0x00430000 /* - * IO Performance - * Control - */ - - - -#define IIO_IPPR 0x00430008 /* - * IO Performance - * Profiling - */ - - - - - -#ifndef __ASSEMBLY__ - -/************************************************************************ - * * - * Description: This register echoes some information from the * - * LB_REV_ID register. It is available through Crosstalk as described * - * above. The REV_NUM and MFG_NUM fields receive their values from * - * the REVISION and MANUFACTURER fields in the LB_REV_ID register. * - * The PART_NUM field's value is the Crosstalk device ID number that * - * Steve Miller assigned to the Bedrock chip. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_wid_u { - bdrkreg_t ii_wid_regval; - struct { - bdrkreg_t w_rsvd_1 : 1; - bdrkreg_t w_mfg_num : 11; - bdrkreg_t w_part_num : 16; - bdrkreg_t w_rev_num : 4; - bdrkreg_t w_rsvd : 32; - } ii_wid_fld_s; -} ii_wid_u_t; - -#else - -typedef union ii_wid_u { - bdrkreg_t ii_wid_regval; - struct { - bdrkreg_t w_rsvd : 32; - bdrkreg_t w_rev_num : 4; - bdrkreg_t w_part_num : 16; - bdrkreg_t w_mfg_num : 11; - bdrkreg_t w_rsvd_1 : 1; - } ii_wid_fld_s; -} ii_wid_u_t; - -#endif - - - - -/************************************************************************ - * * - * The fields in this register are set upon detection of an error * - * and cleared by various mechanisms, as explained in the * - * description. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_wstat_u { - bdrkreg_t ii_wstat_regval; - struct { - bdrkreg_t w_pending : 4; - bdrkreg_t w_xt_crd_to : 1; - bdrkreg_t w_xt_tail_to : 1; - bdrkreg_t w_rsvd_3 : 3; - bdrkreg_t w_tx_mx_rty : 1; - bdrkreg_t w_rsvd_2 : 6; - bdrkreg_t w_llp_tx_cnt : 8; - bdrkreg_t w_rsvd_1 : 8; - bdrkreg_t w_crazy : 1; - bdrkreg_t w_rsvd : 31; - } ii_wstat_fld_s; -} ii_wstat_u_t; - -#else - -typedef union ii_wstat_u { - bdrkreg_t ii_wstat_regval; - struct { - bdrkreg_t w_rsvd : 31; - bdrkreg_t w_crazy : 1; - bdrkreg_t w_rsvd_1 : 8; - bdrkreg_t w_llp_tx_cnt : 8; - bdrkreg_t w_rsvd_2 : 6; - bdrkreg_t w_tx_mx_rty : 1; - bdrkreg_t w_rsvd_3 : 3; - bdrkreg_t w_xt_tail_to : 1; - bdrkreg_t w_xt_crd_to : 1; - bdrkreg_t w_pending : 4; - } ii_wstat_fld_s; -} ii_wstat_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This is a read-write enabled register. It controls * - * various aspects of the Crosstalk flow control. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_wcr_u { - bdrkreg_t ii_wcr_regval; - struct { - bdrkreg_t w_wid : 4; - bdrkreg_t w_tag : 1; - bdrkreg_t w_rsvd_1 : 8; - bdrkreg_t w_dst_crd : 3; - bdrkreg_t w_f_bad_pkt : 1; - bdrkreg_t w_dir_con : 1; - bdrkreg_t w_e_thresh : 5; - bdrkreg_t w_rsvd : 41; - } ii_wcr_fld_s; -} ii_wcr_u_t; - -#else - -typedef union ii_wcr_u { - bdrkreg_t ii_wcr_regval; - struct { - bdrkreg_t w_rsvd : 41; - bdrkreg_t w_e_thresh : 5; - bdrkreg_t w_dir_con : 1; - bdrkreg_t w_f_bad_pkt : 1; - bdrkreg_t w_dst_crd : 3; - bdrkreg_t w_rsvd_1 : 8; - bdrkreg_t w_tag : 1; - bdrkreg_t w_wid : 4; - } ii_wcr_fld_s; -} ii_wcr_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This register's value is a bit vector that guards * - * access to local registers within the II as well as to external * - * Crosstalk widgets. Each bit in the register corresponds to a * - * particular region in the system; a region consists of one, two or * - * four nodes (depending on the value of the REGION_SIZE field in the * - * LB_REV_ID register, which is documented in Section 8.3.1.1). The * - * protection provided by this register applies to PIO read * - * operations as well as PIO write operations. The II will perform a * - * PIO read or write request only if the bit for the requestor's * - * region is set; otherwise, the II will not perform the requested * - * operation and will return an error response. When a PIO read or * - * write request targets an external Crosstalk widget, then not only * - * must the bit for the requestor's region be set in the ILAPR, but * - * also the target widget's bit in the IOWA register must be set in * - * order for the II to perform the requested operation; otherwise, * - * the II will return an error response. Hence, the protection * - * provided by the IOWA register supplements the protection provided * - * by the ILAPR for requests that target external Crosstalk widgets. * - * This register itself can be accessed only by the nodes whose * - * region ID bits are enabled in this same register. It can also be * - * accessed through the IAlias space by the local processors. * - * The reset value of this register allows access by all nodes. * - * * - ************************************************************************/ - - - - -typedef union ii_ilapr_u { - bdrkreg_t ii_ilapr_regval; - struct { - bdrkreg_t i_region : 64; - } ii_ilapr_fld_s; -} ii_ilapr_u_t; - - - - -/************************************************************************ - * * - * Description: A write to this register of the 64-bit value * - * "SGIrules" in ASCII, will cause the bit in the ILAPR register * - * corresponding to the region of the requestor to be set (allow * - * access). A write of any other value will be ignored. Access * - * protection for this register is "SGIrules". * - * This register can also be accessed through the IAlias space. * - * However, this access will not change the access permissions in the * - * ILAPR. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ilapo_u { - bdrkreg_t ii_ilapo_regval; - struct { - bdrkreg_t i_io_ovrride : 9; - bdrkreg_t i_rsvd : 55; - } ii_ilapo_fld_s; -} ii_ilapo_u_t; - -#else - -typedef union ii_ilapo_u { - bdrkreg_t ii_ilapo_regval; - struct { - bdrkreg_t i_rsvd : 55; - bdrkreg_t i_io_ovrride : 9; - } ii_ilapo_fld_s; -} ii_ilapo_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register qualifies all the PIO and Graphics writes launched * - * from the Bedrock towards a widget. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iowa_u { - bdrkreg_t ii_iowa_regval; - struct { - bdrkreg_t i_w0_oac : 1; - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_wx_oac : 8; - bdrkreg_t i_rsvd : 48; - } ii_iowa_fld_s; -} ii_iowa_u_t; - -#else - -typedef union ii_iowa_u { - bdrkreg_t ii_iowa_regval; - struct { - bdrkreg_t i_rsvd : 48; - bdrkreg_t i_wx_oac : 8; - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_w0_oac : 1; - } ii_iowa_fld_s; -} ii_iowa_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This register qualifies all the requests launched * - * from a widget towards the Bedrock. This register is intended to be * - * used by software in case of misbehaving widgets. * - * * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iiwa_u { - bdrkreg_t ii_iiwa_regval; - struct { - bdrkreg_t i_w0_iac : 1; - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_wx_iac : 8; - bdrkreg_t i_rsvd : 48; - } ii_iiwa_fld_s; -} ii_iiwa_u_t; - -#else - -typedef union ii_iiwa_u { - bdrkreg_t ii_iiwa_regval; - struct { - bdrkreg_t i_rsvd : 48; - bdrkreg_t i_wx_iac : 8; - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_w0_iac : 1; - } ii_iiwa_fld_s; -} ii_iiwa_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This register qualifies all the operations launched * - * from a widget towards the Bedrock. It allows individual access * - * control for up to 8 devices per widget. A device refers to * - * individual DMA master hosted by a widget. * - * The bits in each field of this register are cleared by the Bedrock * - * upon detection of an error which requires the device to be * - * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric * - * Crosstalk). Whether or not a device has access rights to this * - * Bedrock is determined by an AND of the device enable bit in the * - * appropriate field of this register and the corresponding bit in * - * the Wx_IAC field (for the widget which this device belongs to). * - * The bits in this field are set by writing a 1 to them. Incoming * - * replies from Crosstalk are not subject to this access control * - * mechanism. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iidem_u { - bdrkreg_t ii_iidem_regval; - struct { - bdrkreg_t i_w8_dxs : 8; - bdrkreg_t i_w9_dxs : 8; - bdrkreg_t i_wa_dxs : 8; - bdrkreg_t i_wb_dxs : 8; - bdrkreg_t i_wc_dxs : 8; - bdrkreg_t i_wd_dxs : 8; - bdrkreg_t i_we_dxs : 8; - bdrkreg_t i_wf_dxs : 8; - } ii_iidem_fld_s; -} ii_iidem_u_t; - -#else - -typedef union ii_iidem_u { - bdrkreg_t ii_iidem_regval; - struct { - bdrkreg_t i_wf_dxs : 8; - bdrkreg_t i_we_dxs : 8; - bdrkreg_t i_wd_dxs : 8; - bdrkreg_t i_wc_dxs : 8; - bdrkreg_t i_wb_dxs : 8; - bdrkreg_t i_wa_dxs : 8; - bdrkreg_t i_w9_dxs : 8; - bdrkreg_t i_w8_dxs : 8; - } ii_iidem_fld_s; -} ii_iidem_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the various programmable fields necessary * - * for controlling and observing the LLP signals. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ilcsr_u { - bdrkreg_t ii_ilcsr_regval; - struct { - bdrkreg_t i_nullto : 6; - bdrkreg_t i_rsvd_4 : 2; - bdrkreg_t i_wrmrst : 1; - bdrkreg_t i_rsvd_3 : 1; - bdrkreg_t i_llp_en : 1; - bdrkreg_t i_bm8 : 1; - bdrkreg_t i_llp_stat : 2; - bdrkreg_t i_remote_power : 1; - bdrkreg_t i_rsvd_2 : 1; - bdrkreg_t i_maxrtry : 10; - bdrkreg_t i_d_avail_sel : 2; - bdrkreg_t i_rsvd_1 : 4; - bdrkreg_t i_maxbrst : 10; - bdrkreg_t i_rsvd : 22; - - } ii_ilcsr_fld_s; -} ii_ilcsr_u_t; - -#else - -typedef union ii_ilcsr_u { - bdrkreg_t ii_ilcsr_regval; - struct { - bdrkreg_t i_rsvd : 22; - bdrkreg_t i_maxbrst : 10; - bdrkreg_t i_rsvd_1 : 4; - bdrkreg_t i_d_avail_sel : 2; - bdrkreg_t i_maxrtry : 10; - bdrkreg_t i_rsvd_2 : 1; - bdrkreg_t i_remote_power : 1; - bdrkreg_t i_llp_stat : 2; - bdrkreg_t i_bm8 : 1; - bdrkreg_t i_llp_en : 1; - bdrkreg_t i_rsvd_3 : 1; - bdrkreg_t i_wrmrst : 1; - bdrkreg_t i_rsvd_4 : 2; - bdrkreg_t i_nullto : 6; - } ii_ilcsr_fld_s; -} ii_ilcsr_u_t; - -#endif - - - - -/************************************************************************ - * * - * This is simply a status registers that monitors the LLP error * - * rate. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_illr_u { - bdrkreg_t ii_illr_regval; - struct { - bdrkreg_t i_sn_cnt : 16; - bdrkreg_t i_cb_cnt : 16; - bdrkreg_t i_rsvd : 32; - } ii_illr_fld_s; -} ii_illr_u_t; - -#else - -typedef union ii_illr_u { - bdrkreg_t ii_illr_regval; - struct { - bdrkreg_t i_rsvd : 32; - bdrkreg_t i_cb_cnt : 16; - bdrkreg_t i_sn_cnt : 16; - } ii_illr_fld_s; -} ii_illr_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: All II-detected non-BTE error interrupts are * - * specified via this register. * - * NOTE: The PI interrupt register address is hardcoded in the II. If * - * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI * - * packet) to address offset 0x0180_0090 within the local register * - * address space of PI0 on the node specified by the NODE field. If * - * PI_ID==1, then the II sends the interrupt request to address * - * offset 0x01A0_0090 within the local register address space of PI1 * - * on the node specified by the NODE field. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iidsr_u { - bdrkreg_t ii_iidsr_regval; - struct { - bdrkreg_t i_level : 7; - bdrkreg_t i_rsvd_4 : 1; - bdrkreg_t i_pi_id : 1; - bdrkreg_t i_node : 8; - bdrkreg_t i_rsvd_3 : 7; - bdrkreg_t i_enable : 1; - bdrkreg_t i_rsvd_2 : 3; - bdrkreg_t i_int_sent : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_pi0_forward_int : 1; - bdrkreg_t i_pi1_forward_int : 1; - bdrkreg_t i_rsvd : 30; - } ii_iidsr_fld_s; -} ii_iidsr_u_t; - -#else - -typedef union ii_iidsr_u { - bdrkreg_t ii_iidsr_regval; - struct { - bdrkreg_t i_rsvd : 30; - bdrkreg_t i_pi1_forward_int : 1; - bdrkreg_t i_pi0_forward_int : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_int_sent : 1; - bdrkreg_t i_rsvd_2 : 3; - bdrkreg_t i_enable : 1; - bdrkreg_t i_rsvd_3 : 7; - bdrkreg_t i_node : 8; - bdrkreg_t i_pi_id : 1; - bdrkreg_t i_rsvd_4 : 1; - bdrkreg_t i_level : 7; - } ii_iidsr_fld_s; -} ii_iidsr_u_t; - -#endif - - - - -/************************************************************************ - * * - * There are two instances of this register. This register is used * - * for matching up the incoming responses from the graphics widget to * - * the processor that initiated the graphics operation. The * - * write-responses are converted to graphics credits and returned to * - * the processor so that the processor interface can manage the flow * - * control. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_igfx0_u { - bdrkreg_t ii_igfx0_regval; - struct { - bdrkreg_t i_w_num : 4; - bdrkreg_t i_pi_id : 1; - bdrkreg_t i_n_num : 8; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_p_num : 1; - bdrkreg_t i_rsvd : 47; - } ii_igfx0_fld_s; -} ii_igfx0_u_t; - -#else - -typedef union ii_igfx0_u { - bdrkreg_t ii_igfx0_regval; - struct { - bdrkreg_t i_rsvd : 47; - bdrkreg_t i_p_num : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_n_num : 8; - bdrkreg_t i_pi_id : 1; - bdrkreg_t i_w_num : 4; - } ii_igfx0_fld_s; -} ii_igfx0_u_t; - -#endif - - - - -/************************************************************************ - * * - * There are two instances of this register. This register is used * - * for matching up the incoming responses from the graphics widget to * - * the processor that initiated the graphics operation. The * - * write-responses are converted to graphics credits and returned to * - * the processor so that the processor interface can manage the flow * - * control. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_igfx1_u { - bdrkreg_t ii_igfx1_regval; - struct { - bdrkreg_t i_w_num : 4; - bdrkreg_t i_pi_id : 1; - bdrkreg_t i_n_num : 8; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_p_num : 1; - bdrkreg_t i_rsvd : 47; - } ii_igfx1_fld_s; -} ii_igfx1_u_t; - -#else - -typedef union ii_igfx1_u { - bdrkreg_t ii_igfx1_regval; - struct { - bdrkreg_t i_rsvd : 47; - bdrkreg_t i_p_num : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_n_num : 8; - bdrkreg_t i_pi_id : 1; - bdrkreg_t i_w_num : 4; - } ii_igfx1_fld_s; -} ii_igfx1_u_t; - -#endif - - - - -/************************************************************************ - * * - * There are two instances of this registers. These registers are * - * used as scratch registers for software use. * - * * - ************************************************************************/ - - - - -typedef union ii_iscr0_u { - bdrkreg_t ii_iscr0_regval; - struct { - bdrkreg_t i_scratch : 64; - } ii_iscr0_fld_s; -} ii_iscr0_u_t; - - - - -/************************************************************************ - * * - * There are two instances of this registers. These registers are * - * used as scratch registers for software use. * - * * - ************************************************************************/ - - - - -typedef union ii_iscr1_u { - bdrkreg_t ii_iscr1_regval; - struct { - bdrkreg_t i_scratch : 64; - } ii_iscr1_fld_s; -} ii_iscr1_u_t; - - - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a Bedrock Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the Bedrock is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the Bedrock is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_itte1_u { - bdrkreg_t ii_itte1_regval; - struct { - bdrkreg_t i_offset : 5; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_rsvd : 51; - } ii_itte1_fld_s; -} ii_itte1_u_t; - -#else - -typedef union ii_itte1_u { - bdrkreg_t ii_itte1_regval; - struct { - bdrkreg_t i_rsvd : 51; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_offset : 5; - } ii_itte1_fld_s; -} ii_itte1_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a Bedrock Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the Bedrock is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the Bedrock is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_itte2_u { - bdrkreg_t ii_itte2_regval; - struct { - bdrkreg_t i_offset : 5; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_rsvd : 51; - } ii_itte2_fld_s; -} ii_itte2_u_t; - -#else -typedef union ii_itte2_u { - bdrkreg_t ii_itte2_regval; - struct { - bdrkreg_t i_rsvd : 51; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_offset : 5; - } ii_itte2_fld_s; -} ii_itte2_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a Bedrock Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the Bedrock is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the Bedrock is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_itte3_u { - bdrkreg_t ii_itte3_regval; - struct { - bdrkreg_t i_offset : 5; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_rsvd : 51; - } ii_itte3_fld_s; -} ii_itte3_u_t; - -#else - -typedef union ii_itte3_u { - bdrkreg_t ii_itte3_regval; - struct { - bdrkreg_t i_rsvd : 51; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_offset : 5; - } ii_itte3_fld_s; -} ii_itte3_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a Bedrock Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the Bedrock is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the Bedrock is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_itte4_u { - bdrkreg_t ii_itte4_regval; - struct { - bdrkreg_t i_offset : 5; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_rsvd : 51; - } ii_itte4_fld_s; -} ii_itte4_u_t; - -#else - -typedef union ii_itte4_u { - bdrkreg_t ii_itte4_regval; - struct { - bdrkreg_t i_rsvd : 51; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_offset : 5; - } ii_itte4_fld_s; -} ii_itte4_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a Bedrock Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the Bedrock is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the Bedrock is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_itte5_u { - bdrkreg_t ii_itte5_regval; - struct { - bdrkreg_t i_offset : 5; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_rsvd : 51; - } ii_itte5_fld_s; -} ii_itte5_u_t; - -#else - -typedef union ii_itte5_u { - bdrkreg_t ii_itte5_regval; - struct { - bdrkreg_t i_rsvd : 51; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_offset : 5; - } ii_itte5_fld_s; -} ii_itte5_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a Bedrock Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the Bedrock is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the Bedrock is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_itte6_u { - bdrkreg_t ii_itte6_regval; - struct { - bdrkreg_t i_offset : 5; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_rsvd : 51; - } ii_itte6_fld_s; -} ii_itte6_u_t; - -#else - -typedef union ii_itte6_u { - bdrkreg_t ii_itte6_regval; - struct { - bdrkreg_t i_rsvd : 51; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_offset : 5; - } ii_itte6_fld_s; -} ii_itte6_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a Bedrock Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the Bedrock is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the Bedrock is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_itte7_u { - bdrkreg_t ii_itte7_regval; - struct { - bdrkreg_t i_offset : 5; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_rsvd : 51; - } ii_itte7_fld_s; -} ii_itte7_u_t; - -#else - -typedef union ii_itte7_u { - bdrkreg_t ii_itte7_regval; - struct { - bdrkreg_t i_rsvd : 51; - bdrkreg_t i_iosp : 1; - bdrkreg_t i_w_num : 4; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_offset : 5; - } ii_itte7_fld_s; -} ii_itte7_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of Bedrock and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprb0_u { - bdrkreg_t ii_iprb0_regval; - struct { - bdrkreg_t i_c : 8; - bdrkreg_t i_na : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_m : 2; - bdrkreg_t i_f : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_error : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_mult_err : 1; - } ii_iprb0_fld_s; -} ii_iprb0_u_t; - -#else - -typedef union ii_iprb0_u { - bdrkreg_t ii_iprb0_regval; - struct { - bdrkreg_t i_mult_err : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_error : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_f : 1; - bdrkreg_t i_m : 2; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_na : 14; - bdrkreg_t i_c : 8; - } ii_iprb0_fld_s; -} ii_iprb0_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of Bedrock and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprb8_u { - bdrkreg_t ii_iprb8_regval; - struct { - bdrkreg_t i_c : 8; - bdrkreg_t i_na : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_m : 2; - bdrkreg_t i_f : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_error : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_mult_err : 1; - } ii_iprb8_fld_s; -} ii_iprb8_u_t; - -#else - - -typedef union ii_iprb8_u { - bdrkreg_t ii_iprb8_regval; - struct { - bdrkreg_t i_mult_err : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_error : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_f : 1; - bdrkreg_t i_m : 2; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_na : 14; - bdrkreg_t i_c : 8; - } ii_iprb8_fld_s; -} ii_iprb8_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of Bedrock and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprb9_u { - bdrkreg_t ii_iprb9_regval; - struct { - bdrkreg_t i_c : 8; - bdrkreg_t i_na : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_m : 2; - bdrkreg_t i_f : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_error : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_mult_err : 1; - } ii_iprb9_fld_s; -} ii_iprb9_u_t; - -#else - -typedef union ii_iprb9_u { - bdrkreg_t ii_iprb9_regval; - struct { - bdrkreg_t i_mult_err : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_error : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_f : 1; - bdrkreg_t i_m : 2; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_na : 14; - bdrkreg_t i_c : 8; - } ii_iprb9_fld_s; -} ii_iprb9_u_t; - -#endif - - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of Bedrock and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprba_u { - bdrkreg_t ii_iprba_regval; - struct { - bdrkreg_t i_c : 8; - bdrkreg_t i_na : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_m : 2; - bdrkreg_t i_f : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_error : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_mult_err : 1; - } ii_iprba_fld_s; -} ii_iprba_u_t; - -#else - -typedef union ii_iprba_u { - bdrkreg_t ii_iprba_regval; - struct { - bdrkreg_t i_mult_err : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_error : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_f : 1; - bdrkreg_t i_m : 2; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_na : 14; - bdrkreg_t i_c : 8; - } ii_iprba_fld_s; -} ii_iprba_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of Bedrock and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprbb_u { - bdrkreg_t ii_iprbb_regval; - struct { - bdrkreg_t i_c : 8; - bdrkreg_t i_na : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_m : 2; - bdrkreg_t i_f : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_error : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_mult_err : 1; - } ii_iprbb_fld_s; -} ii_iprbb_u_t; - -#else - -typedef union ii_iprbb_u { - bdrkreg_t ii_iprbb_regval; - struct { - bdrkreg_t i_mult_err : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_error : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_f : 1; - bdrkreg_t i_m : 2; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_na : 14; - bdrkreg_t i_c : 8; - } ii_iprbb_fld_s; -} ii_iprbb_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of Bedrock and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprbc_u { - bdrkreg_t ii_iprbc_regval; - struct { - bdrkreg_t i_c : 8; - bdrkreg_t i_na : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_m : 2; - bdrkreg_t i_f : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_error : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_mult_err : 1; - } ii_iprbc_fld_s; -} ii_iprbc_u_t; - -#else - -typedef union ii_iprbc_u { - bdrkreg_t ii_iprbc_regval; - struct { - bdrkreg_t i_mult_err : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_error : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_f : 1; - bdrkreg_t i_m : 2; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_na : 14; - bdrkreg_t i_c : 8; - } ii_iprbc_fld_s; -} ii_iprbc_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of Bedrock and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprbd_u { - bdrkreg_t ii_iprbd_regval; - struct { - bdrkreg_t i_c : 8; - bdrkreg_t i_na : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_m : 2; - bdrkreg_t i_f : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_error : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_mult_err : 1; - } ii_iprbd_fld_s; -} ii_iprbd_u_t; - -#else - -typedef union ii_iprbd_u { - bdrkreg_t ii_iprbd_regval; - struct { - bdrkreg_t i_mult_err : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_error : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_f : 1; - bdrkreg_t i_m : 2; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_na : 14; - bdrkreg_t i_c : 8; - } ii_iprbd_fld_s; -} ii_iprbd_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of Bedrock and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprbe_u { - bdrkreg_t ii_iprbe_regval; - struct { - bdrkreg_t i_c : 8; - bdrkreg_t i_na : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_m : 2; - bdrkreg_t i_f : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_error : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_mult_err : 1; - } ii_iprbe_fld_s; -} ii_iprbe_u_t; - -#else - -typedef union ii_iprbe_u { - bdrkreg_t ii_iprbe_regval; - struct { - bdrkreg_t i_mult_err : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_error : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_f : 1; - bdrkreg_t i_m : 2; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_na : 14; - bdrkreg_t i_c : 8; - } ii_iprbe_fld_s; -} ii_iprbe_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of Bedrock and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprbf_u { - bdrkreg_t ii_iprbf_regval; - struct { - bdrkreg_t i_c : 8; - bdrkreg_t i_na : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_m : 2; - bdrkreg_t i_f : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_error : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_mult_err : 1; - } ii_iprbe_fld_s; -} ii_iprbf_u_t; - -#else - -typedef union ii_iprbf_u { - bdrkreg_t ii_iprbf_regval; - struct { - bdrkreg_t i_mult_err : 1; - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_spur_rd : 1; - bdrkreg_t i_spur_wr : 1; - bdrkreg_t i_rd_to : 1; - bdrkreg_t i_error : 1; - bdrkreg_t i_of_cnt : 5; - bdrkreg_t i_f : 1; - bdrkreg_t i_m : 2; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_nb : 14; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_na : 14; - bdrkreg_t i_c : 8; - } ii_iprbf_fld_s; -} ii_iprbf_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register specifies the timeout value to use for monitoring * - * Crosstalk credits which are used outbound to Crosstalk. An * - * internal counter called the Crosstalk Credit Timeout Counter * - * increments every 128 II clocks. The counter starts counting * - * anytime the credit count drops below a threshold, and resets to * - * zero (stops counting) anytime the credit count is at or above the * - * threshold. The threshold is 1 credit in direct connect mode and 2 * - * in Crossbow connect mode. When the internal Crosstalk Credit * - * Timeout Counter reaches the value programmed in this register, a * - * Crosstalk Credit Timeout has occurred. The internal counter is not * - * readable from software, and stops counting at its maximum value, * - * so it cannot cause more than one interrupt. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ixcc_u { - bdrkreg_t ii_ixcc_regval; - struct { - bdrkreg_t i_time_out : 26; - bdrkreg_t i_rsvd : 38; - } ii_ixcc_fld_s; -} ii_ixcc_u_t; - -#else - -typedef union ii_ixcc_u { - bdrkreg_t ii_ixcc_regval; - struct { - bdrkreg_t i_rsvd : 38; - bdrkreg_t i_time_out : 26; - } ii_ixcc_fld_s; -} ii_ixcc_u_t; - -#endif - - - -/************************************************************************ - * * - * Description: This register qualifies all the PIO and DMA * - * operations launched from widget 0 towards the Bedrock. In * - * addition, it also qualifies accesses by the BTE streams. * - * The bits in each field of this register are cleared by the Bedrock * - * upon detection of an error which requires widget 0 or the BTE * - * streams to be terminated. Whether or not widget x has access * - * rights to this Bedrock is determined by an AND of the device * - * enable bit in the appropriate field of this register and bit 0 in * - * the Wx_IAC field. The bits in this field are set by writing a 1 to * - * them. Incoming replies from Crosstalk are not subject to this * - * access control mechanism. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_imem_u { - bdrkreg_t ii_imem_regval; - struct { - bdrkreg_t i_w0_esd : 1; - bdrkreg_t i_rsvd_3 : 3; - bdrkreg_t i_b0_esd : 1; - bdrkreg_t i_rsvd_2 : 3; - bdrkreg_t i_b1_esd : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_clr_precise : 1; - bdrkreg_t i_rsvd : 51; - } ii_imem_fld_s; -} ii_imem_u_t; - -#else - -typedef union ii_imem_u { - bdrkreg_t ii_imem_regval; - struct { - bdrkreg_t i_rsvd : 51; - bdrkreg_t i_clr_precise : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_b1_esd : 1; - bdrkreg_t i_rsvd_2 : 3; - bdrkreg_t i_b0_esd : 1; - bdrkreg_t i_rsvd_3 : 3; - bdrkreg_t i_w0_esd : 1; - } ii_imem_fld_s; -} ii_imem_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This register specifies the timeout value to use for * - * monitoring Crosstalk tail flits coming into the Bedrock in the * - * TAIL_TO field. An internal counter associated with this register * - * is incremented every 128 II internal clocks (7 bits). The counter * - * starts counting anytime a header micropacket is received and stops * - * counting (and resets to zero) any time a micropacket with a Tail * - * bit is received. Once the counter reaches the threshold value * - * programmed in this register, it generates an interrupt to the * - * processor that is programmed into the IIDSR. The counter saturates * - * (does not roll over) at its maximum value, so it cannot cause * - * another interrupt until after it is cleared. * - * The register also contains the Read Response Timeout values. The * - * Prescalar is 23 bits, and counts II clocks. An internal counter * - * increments on every II clock and when it reaches the value in the * - * Prescalar field, all IPRTE registers with their valid bits set * - * have their Read Response timers bumped. Whenever any of them match * - * the value in the RRSP_TO field, a Read Response Timeout has * - * occurred, and error handling occurs as described in the Error * - * Handling section of this document. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ixtt_u { - bdrkreg_t ii_ixtt_regval; - struct { - bdrkreg_t i_tail_to : 26; - bdrkreg_t i_rsvd_1 : 6; - bdrkreg_t i_rrsp_ps : 23; - bdrkreg_t i_rrsp_to : 5; - bdrkreg_t i_rsvd : 4; - } ii_ixtt_fld_s; -} ii_ixtt_u_t; - -#else - -typedef union ii_ixtt_u { - bdrkreg_t ii_ixtt_regval; - struct { - bdrkreg_t i_rsvd : 4; - bdrkreg_t i_rrsp_to : 5; - bdrkreg_t i_rrsp_ps : 23; - bdrkreg_t i_rsvd_1 : 6; - bdrkreg_t i_tail_to : 26; - } ii_ixtt_fld_s; -} ii_ixtt_u_t; - -#endif - - - - -/************************************************************************ - * * - * Writing a 1 to the fields of this register clears the appropriate * - * error bits in other areas of Bedrock_II. Note that when the * - * E_PRB_x bits are used to clear error bits in PRB registers, * - * SPUR_RD and SPUR_WR may persist, because they require additional * - * action to clear them. See the IPRBx and IXSS Register * - * specifications. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ieclr_u { - bdrkreg_t ii_ieclr_regval; - struct { - bdrkreg_t i_e_prb_0 : 1; - bdrkreg_t i_rsvd : 7; - bdrkreg_t i_e_prb_8 : 1; - bdrkreg_t i_e_prb_9 : 1; - bdrkreg_t i_e_prb_a : 1; - bdrkreg_t i_e_prb_b : 1; - bdrkreg_t i_e_prb_c : 1; - bdrkreg_t i_e_prb_d : 1; - bdrkreg_t i_e_prb_e : 1; - bdrkreg_t i_e_prb_f : 1; - bdrkreg_t i_e_crazy : 1; - bdrkreg_t i_e_bte_0 : 1; - bdrkreg_t i_e_bte_1 : 1; - bdrkreg_t i_reserved_1 : 9; - bdrkreg_t i_ii_internal : 1; - bdrkreg_t i_spur_rd_hdr : 1; - bdrkreg_t i_pi0_forward_int : 1; - bdrkreg_t i_pi1_forward_int : 1; - bdrkreg_t i_reserved : 32; - } ii_ieclr_fld_s; -} ii_ieclr_u_t; - -#else - -typedef union ii_ieclr_u { - bdrkreg_t ii_ieclr_regval; - struct { - bdrkreg_t i_reserved : 32; - bdrkreg_t i_pi1_forward_int : 1; - bdrkreg_t i_pi0_forward_int : 1; - bdrkreg_t i_spur_rd_hdr : 1; - bdrkreg_t i_ii_internal : 1; - bdrkreg_t i_reserved_1 : 9; - bdrkreg_t i_e_bte_1 : 1; - bdrkreg_t i_e_bte_0 : 1; - bdrkreg_t i_e_crazy : 1; - bdrkreg_t i_e_prb_f : 1; - bdrkreg_t i_e_prb_e : 1; - bdrkreg_t i_e_prb_d : 1; - bdrkreg_t i_e_prb_c : 1; - bdrkreg_t i_e_prb_b : 1; - bdrkreg_t i_e_prb_a : 1; - bdrkreg_t i_e_prb_9 : 1; - bdrkreg_t i_e_prb_8 : 1; - bdrkreg_t i_rsvd : 7; - bdrkreg_t i_e_prb_0 : 1; - } ii_ieclr_fld_s; -} ii_ieclr_u_t; - -#endif - - - - - -/************************************************************************ - * * - * This register controls both BTEs. SOFT_RESET is intended for * - * recovery after an error. COUNT controls the total number of CRBs * - * that both BTEs (combined) can use, which affects total BTE * - * bandwidth. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ibcr_u { - bdrkreg_t ii_ibcr_regval; - struct { - bdrkreg_t i_count : 4; - bdrkreg_t i_rsvd_1 : 4; - bdrkreg_t i_soft_reset : 1; - bdrkreg_t i_rsvd : 55; - } ii_ibcr_fld_s; -} ii_ibcr_u_t; - -#else - -typedef union ii_ibcr_u { - bdrkreg_t ii_ibcr_regval; - struct { - bdrkreg_t i_rsvd : 55; - bdrkreg_t i_soft_reset : 1; - bdrkreg_t i_rsvd_1 : 4; - bdrkreg_t i_count : 4; - } ii_ibcr_fld_s; -} ii_ibcr_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the header of a spurious read response * - * received from Crosstalk. A spurious read response is defined as a * - * read response received by II from a widget for which (1) the SIDN * - * has a value between 1 and 7, inclusive (II never sends requests to * - * these widgets (2) there is no valid IPRTE register which * - * corresponds to the TNUM, or (3) the widget indicated in SIDN is * - * not the same as the widget recorded in the IPRTE register * - * referenced by the TNUM. If this condition is true, and if the * - * IXSS[VALID] bit is clear, then the header of the spurious read * - * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The * - * errant header is thereby captured, and no further spurious read * - * respones are captured until IXSS[VALID] is cleared by setting the * - * appropriate bit in IECLR.Everytime a spurious read response is * - * detected, the SPUR_RD bit of the PRB corresponding to the incoming * - * message's SIDN field is set. This always happens, regarless of * - * whether a header is captured. The programmer should check * - * IXSM[SIDN] to determine which widget sent the spurious response, * - * because there may be more than one SPUR_RD bit set in the PRB * - * registers. The widget indicated by IXSM[SIDN] was the first * - * spurious read response to be received since the last time * - * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB * - * will be set. Any SPUR_RD bits in any other PRB registers indicate * - * spurious messages from other widets which were detected after the * - * header was captured.. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ixsm_u { - bdrkreg_t ii_ixsm_regval; - struct { - bdrkreg_t i_byte_en : 32; - bdrkreg_t i_reserved : 1; - bdrkreg_t i_tag : 3; - bdrkreg_t i_alt_pactyp : 4; - bdrkreg_t i_bo : 1; - bdrkreg_t i_error : 1; - bdrkreg_t i_vbpm : 1; - bdrkreg_t i_gbr : 1; - bdrkreg_t i_ds : 2; - bdrkreg_t i_ct : 1; - bdrkreg_t i_tnum : 5; - bdrkreg_t i_pactyp : 4; - bdrkreg_t i_sidn : 4; - bdrkreg_t i_didn : 4; - } ii_ixsm_fld_s; -} ii_ixsm_u_t; - -#else - -typedef union ii_ixsm_u { - bdrkreg_t ii_ixsm_regval; - struct { - bdrkreg_t i_didn : 4; - bdrkreg_t i_sidn : 4; - bdrkreg_t i_pactyp : 4; - bdrkreg_t i_tnum : 5; - bdrkreg_t i_ct : 1; - bdrkreg_t i_ds : 2; - bdrkreg_t i_gbr : 1; - bdrkreg_t i_vbpm : 1; - bdrkreg_t i_error : 1; - bdrkreg_t i_bo : 1; - bdrkreg_t i_alt_pactyp : 4; - bdrkreg_t i_tag : 3; - bdrkreg_t i_reserved : 1; - bdrkreg_t i_byte_en : 32; - } ii_ixsm_fld_s; -} ii_ixsm_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the sideband bits of a spurious read * - * response received from Crosstalk. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ixss_u { - bdrkreg_t ii_ixss_regval; - struct { - bdrkreg_t i_sideband : 8; - bdrkreg_t i_rsvd : 55; - bdrkreg_t i_valid : 1; - } ii_ixss_fld_s; -} ii_ixss_u_t; - -#else - -typedef union ii_ixss_u { - bdrkreg_t ii_ixss_regval; - struct { - bdrkreg_t i_valid : 1; - bdrkreg_t i_rsvd : 55; - bdrkreg_t i_sideband : 8; - } ii_ixss_fld_s; -} ii_ixss_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register enables software to access the II LLP's test port. * - * Refer to the LLP 2.5 documentation for an explanation of the test * - * port. Software can write to this register to program the values * - * for the control fields (TestErrCapture, TestClear, TestFlit, * - * TestMask and TestSeed). Similarly, software can read from this * - * register to obtain the values of the test port's status outputs * - * (TestCBerr, TestValid and TestData). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ilct_u { - bdrkreg_t ii_ilct_regval; - struct { - bdrkreg_t i_test_seed : 20; - bdrkreg_t i_test_mask : 8; - bdrkreg_t i_test_data : 20; - bdrkreg_t i_test_valid : 1; - bdrkreg_t i_test_cberr : 1; - bdrkreg_t i_test_flit : 3; - bdrkreg_t i_test_clear : 1; - bdrkreg_t i_test_err_capture : 1; - bdrkreg_t i_rsvd : 9; - } ii_ilct_fld_s; -} ii_ilct_u_t; - -#else - -typedef union ii_ilct_u { - bdrkreg_t ii_ilct_regval; - struct { - bdrkreg_t i_rsvd : 9; - bdrkreg_t i_test_err_capture : 1; - bdrkreg_t i_test_clear : 1; - bdrkreg_t i_test_flit : 3; - bdrkreg_t i_test_cberr : 1; - bdrkreg_t i_test_valid : 1; - bdrkreg_t i_test_data : 20; - bdrkreg_t i_test_mask : 8; - bdrkreg_t i_test_seed : 20; - } ii_ilct_fld_s; -} ii_ilct_u_t; - -#endif - - - - -/************************************************************************ - * * - * If the II detects an illegal incoming Duplonet packet (request or * - * reply) when VALID==0 in the IIEPH1 register, then it saves the * - * contents of the packet's header flit in the IIEPH1 and IIEPH2 * - * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, * - * and assigns a value to the ERR_TYPE field which indicates the * - * specific nature of the error. The II recognizes four different * - * types of errors: short request packets (ERR_TYPE==2), short reply * - * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long * - * reply packets (ERR_TYPE==5). The encodings for these types of * - * errors were chosen to be consistent with the same types of errors * - * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in * - * the LB unit). If the II detects an illegal incoming Duplonet * - * packet when VALID==1 in the IIEPH1 register, then it merely sets * - * the OVERRUN bit to indicate that a subsequent error has happened, * - * and does nothing further. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iieph1_u { - bdrkreg_t ii_iieph1_regval; - struct { - bdrkreg_t i_command : 7; - bdrkreg_t i_rsvd_5 : 1; - bdrkreg_t i_suppl : 11; - bdrkreg_t i_rsvd_4 : 1; - bdrkreg_t i_source : 11; - bdrkreg_t i_rsvd_3 : 1; - bdrkreg_t i_err_type : 4; - bdrkreg_t i_rsvd_2 : 4; - bdrkreg_t i_overrun : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_valid : 1; - bdrkreg_t i_rsvd : 19; - } ii_iieph1_fld_s; -} ii_iieph1_u_t; - -#else - -typedef union ii_iieph1_u { - bdrkreg_t ii_iieph1_regval; - struct { - bdrkreg_t i_rsvd : 19; - bdrkreg_t i_valid : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_overrun : 1; - bdrkreg_t i_rsvd_2 : 4; - bdrkreg_t i_err_type : 4; - bdrkreg_t i_rsvd_3 : 1; - bdrkreg_t i_source : 11; - bdrkreg_t i_rsvd_4 : 1; - bdrkreg_t i_suppl : 11; - bdrkreg_t i_rsvd_5 : 1; - bdrkreg_t i_command : 7; - } ii_iieph1_fld_s; -} ii_iieph1_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register holds the Address field from the header flit of an * - * incoming erroneous Duplonet packet, along with the tail bit which * - * accompanied this header flit. This register is essentially an * - * extension of IIEPH1. Two registers were necessary because the 64 * - * bits available in only a single register were insufficient to * - * capture the entire header flit of an erroneous packet. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iieph2_u { - bdrkreg_t ii_iieph2_regval; - struct { - bdrkreg_t i_address : 38; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_tail : 1; - bdrkreg_t i_rsvd : 23; - } ii_iieph2_fld_s; -} ii_iieph2_u_t; - -#else - -typedef union ii_iieph2_u { - bdrkreg_t ii_iieph2_regval; - struct { - bdrkreg_t i_rsvd : 23; - bdrkreg_t i_tail : 1; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_address : 38; - } ii_iieph2_fld_s; -} ii_iieph2_u_t; - -#endif - - - - -/************************************************************************ - * * - * A write to this register causes a particular field in the * - * corresponding widget's PRB entry to be adjusted up or down by 1. * - * This counter should be used when recovering from error and reset * - * conditions. Note that software would be capable of causing * - * inadvertent overflow or underflow of these counters. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ipca_u { - bdrkreg_t ii_ipca_regval; - struct { - bdrkreg_t i_wid : 4; - bdrkreg_t i_adjust : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_field : 2; - bdrkreg_t i_rsvd : 54; - } ii_ipca_fld_s; -} ii_ipca_u_t; - -#else - -typedef union ii_ipca_u { - bdrkreg_t ii_ipca_regval; - struct { - bdrkreg_t i_rsvd : 54; - bdrkreg_t i_field : 2; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_adjust : 1; - bdrkreg_t i_wid : 4; - } ii_ipca_fld_s; -} ii_ipca_u_t; - -#endif - - - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprte0_u { - bdrkreg_t ii_iprte0_regval; - struct { - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_init : 3; - bdrkreg_t i_source : 8; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_widget : 4; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_vld : 1; - } ii_iprte0_fld_s; -} ii_iprte0_u_t; - -#else - -typedef union ii_iprte0_u { - bdrkreg_t ii_iprte0_regval; - struct { - bdrkreg_t i_vld : 1; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_widget : 4; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_source : 8; - bdrkreg_t i_init : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_rsvd_1 : 3; - } ii_iprte0_fld_s; -} ii_iprte0_u_t; - -#endif - - - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprte1_u { - bdrkreg_t ii_iprte1_regval; - struct { - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_init : 3; - bdrkreg_t i_source : 8; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_widget : 4; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_vld : 1; - } ii_iprte1_fld_s; -} ii_iprte1_u_t; - -#else - -typedef union ii_iprte1_u { - bdrkreg_t ii_iprte1_regval; - struct { - bdrkreg_t i_vld : 1; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_widget : 4; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_source : 8; - bdrkreg_t i_init : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_rsvd_1 : 3; - } ii_iprte1_fld_s; -} ii_iprte1_u_t; - -#endif - - - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprte2_u { - bdrkreg_t ii_iprte2_regval; - struct { - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_init : 3; - bdrkreg_t i_source : 8; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_widget : 4; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_vld : 1; - } ii_iprte2_fld_s; -} ii_iprte2_u_t; - -#else - -typedef union ii_iprte2_u { - bdrkreg_t ii_iprte2_regval; - struct { - bdrkreg_t i_vld : 1; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_widget : 4; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_source : 8; - bdrkreg_t i_init : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_rsvd_1 : 3; - } ii_iprte2_fld_s; -} ii_iprte2_u_t; - -#endif - - - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprte3_u { - bdrkreg_t ii_iprte3_regval; - struct { - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_init : 3; - bdrkreg_t i_source : 8; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_widget : 4; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_vld : 1; - } ii_iprte3_fld_s; -} ii_iprte3_u_t; - -#else - -typedef union ii_iprte3_u { - bdrkreg_t ii_iprte3_regval; - struct { - bdrkreg_t i_vld : 1; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_widget : 4; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_source : 8; - bdrkreg_t i_init : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_rsvd_1 : 3; - } ii_iprte3_fld_s; -} ii_iprte3_u_t; - -#endif - - - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprte4_u { - bdrkreg_t ii_iprte4_regval; - struct { - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_init : 3; - bdrkreg_t i_source : 8; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_widget : 4; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_vld : 1; - } ii_iprte4_fld_s; -} ii_iprte4_u_t; - -#else - -typedef union ii_iprte4_u { - bdrkreg_t ii_iprte4_regval; - struct { - bdrkreg_t i_vld : 1; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_widget : 4; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_source : 8; - bdrkreg_t i_init : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_rsvd_1 : 3; - } ii_iprte4_fld_s; -} ii_iprte4_u_t; - -#endif - - - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprte5_u { - bdrkreg_t ii_iprte5_regval; - struct { - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_init : 3; - bdrkreg_t i_source : 8; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_widget : 4; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_vld : 1; - } ii_iprte5_fld_s; -} ii_iprte5_u_t; - -#else - -typedef union ii_iprte5_u { - bdrkreg_t ii_iprte5_regval; - struct { - bdrkreg_t i_vld : 1; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_widget : 4; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_source : 8; - bdrkreg_t i_init : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_rsvd_1 : 3; - } ii_iprte5_fld_s; -} ii_iprte5_u_t; - -#endif - - - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprte6_u { - bdrkreg_t ii_iprte6_regval; - struct { - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_init : 3; - bdrkreg_t i_source : 8; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_widget : 4; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_vld : 1; - } ii_iprte6_fld_s; -} ii_iprte6_u_t; - -#else - -typedef union ii_iprte6_u { - bdrkreg_t ii_iprte6_regval; - struct { - bdrkreg_t i_vld : 1; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_widget : 4; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_source : 8; - bdrkreg_t i_init : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_rsvd_1 : 3; - } ii_iprte6_fld_s; -} ii_iprte6_u_t; - -#endif - - - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iprte7_u { - bdrkreg_t ii_iprte7_regval; - struct { - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_init : 3; - bdrkreg_t i_source : 8; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_widget : 4; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_vld : 1; - } ii_iprte7_fld_s; -} ii_iprte7_u_t; - -#else - -typedef union ii_iprte7_u { - bdrkreg_t ii_iprte7_regval; - struct { - bdrkreg_t i_vld : 1; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_widget : 4; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_source : 8; - bdrkreg_t i_init : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_rsvd_1 : 3; - } ii_iprte7_fld_s; -} ii_iprte7_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: Bedrock_II contains a feature which did not exist in * - * the Hub which automatically cleans up after a Read Response * - * timeout, including deallocation of the IPRTE and recovery of IBuf * - * space. The inclusion of this register in Bedrock is for backward * - * compatibility * - * A write to this register causes an entry from the table of * - * outstanding PIO Read Requests to be freed and returned to the * - * stack of free entries. This register is used in handling the * - * timeout errors that result in a PIO Reply never returning from * - * Crosstalk. * - * Note that this register does not affect the contents of the IPRTE * - * registers. The Valid bits in those registers have to be * - * specifically turned off by software. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ipdr_u { - bdrkreg_t ii_ipdr_regval; - struct { - bdrkreg_t i_te : 3; - bdrkreg_t i_rsvd_1 : 1; - bdrkreg_t i_pnd : 1; - bdrkreg_t i_init_rpcnt : 1; - bdrkreg_t i_rsvd : 58; - } ii_ipdr_fld_s; -} ii_ipdr_u_t; - -#else - -typedef union ii_ipdr_u { - bdrkreg_t ii_ipdr_regval; - struct { - bdrkreg_t i_rsvd : 58; - bdrkreg_t i_init_rpcnt : 1; - bdrkreg_t i_pnd : 1; - bdrkreg_t i_rsvd_1 : 1; - bdrkreg_t i_te : 3; - } ii_ipdr_fld_s; -} ii_ipdr_u_t; - -#endif - - - - -/************************************************************************ - * * - * A write to this register causes a CRB entry to be returned to the * - * queue of free CRBs. The entry should have previously been cleared * - * (mark bit) via backdoor access to the pertinent CRB entry. This * - * register is used in the last step of handling the errors that are * - * captured and marked in CRB entries. Briefly: 1) first error for * - * DMA write from a particular device, and first error for a * - * particular BTE stream, lead to a marked CRB entry, and processor * - * interrupt, 2) software reads the error information captured in the * - * CRB entry, and presumably takes some corrective action, 3) * - * software clears the mark bit, and finally 4) software writes to * - * the ICDR register to return the CRB entry to the list of free CRB * - * entries. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_icdr_u { - bdrkreg_t ii_icdr_regval; - struct { - bdrkreg_t i_crb_num : 4; - bdrkreg_t i_pnd : 1; - bdrkreg_t i_rsvd : 59; - } ii_icdr_fld_s; -} ii_icdr_u_t; - -#else - -typedef union ii_icdr_u { - bdrkreg_t ii_icdr_regval; - struct { - bdrkreg_t i_rsvd : 59; - bdrkreg_t i_pnd : 1; - bdrkreg_t i_crb_num : 4; - } ii_icdr_fld_s; -} ii_icdr_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register provides debug access to two FIFOs inside of II. * - * Both IOQ_MAX* fields of this register contain the instantaneous * - * depth (in units of the number of available entries) of the * - * associated IOQ FIFO. A read of this register will return the * - * number of free entries on each FIFO at the time of the read. So * - * when a FIFO is idle, the associated field contains the maximum * - * depth of the FIFO. This register is writable for debug reasons * - * and is intended to be written with the maximum desired FIFO depth * - * while the FIFO is idle. Software must assure that II is idle when * - * this register is written. If there are any active entries in any * - * of these FIFOs when this register is written, the results are * - * undefined. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ifdr_u { - bdrkreg_t ii_ifdr_regval; - struct { - bdrkreg_t i_ioq_max_rq : 7; - bdrkreg_t i_set_ioq_rq : 1; - bdrkreg_t i_ioq_max_rp : 7; - bdrkreg_t i_set_ioq_rp : 1; - bdrkreg_t i_rsvd : 48; - } ii_ifdr_fld_s; -} ii_ifdr_u_t; - -#else - -typedef union ii_ifdr_u { - bdrkreg_t ii_ifdr_regval; - struct { - bdrkreg_t i_rsvd : 48; - bdrkreg_t i_set_ioq_rp : 1; - bdrkreg_t i_ioq_max_rp : 7; - bdrkreg_t i_set_ioq_rq : 1; - bdrkreg_t i_ioq_max_rq : 7; - } ii_ifdr_fld_s; -} ii_ifdr_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register allows the II to become sluggish in removing * - * messages from its inbound queue (IIQ). This will cause messages to * - * back up in either virtual channel. Disabling the "molasses" mode * - * subsequently allows the II to be tested under stress. In the * - * sluggish ("Molasses") mode, the localized effects of congestion * - * can be observed. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iiap_u { - bdrkreg_t ii_iiap_regval; - struct { - bdrkreg_t i_rq_mls : 6; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_rp_mls : 6; - bdrkreg_t i_rsvd : 50; - } ii_iiap_fld_s; -} ii_iiap_u_t; - -#else - -typedef union ii_iiap_u { - bdrkreg_t ii_iiap_regval; - struct { - bdrkreg_t i_rsvd : 50; - bdrkreg_t i_rp_mls : 6; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_rq_mls : 6; - } ii_iiap_fld_s; -} ii_iiap_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register allows several parameters of CRB operation to be * - * set. Note that writing to this register can have catastrophic side * - * effects, if the CRB is not quiescent, i.e. if the CRB is * - * processing protocol messages when the write occurs. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_icmr_u { - bdrkreg_t ii_icmr_regval; - struct { - bdrkreg_t i_sp_msg : 1; - bdrkreg_t i_rd_hdr : 1; - bdrkreg_t i_rsvd_4 : 2; - bdrkreg_t i_c_cnt : 4; - bdrkreg_t i_rsvd_3 : 4; - bdrkreg_t i_clr_rqpd : 1; - bdrkreg_t i_clr_rppd : 1; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_fc_cnt : 4; - bdrkreg_t i_crb_vld : 15; - bdrkreg_t i_crb_mark : 15; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_precise : 1; - bdrkreg_t i_rsvd : 11; - } ii_icmr_fld_s; -} ii_icmr_u_t; - -#else - -typedef union ii_icmr_u { - bdrkreg_t ii_icmr_regval; - struct { - bdrkreg_t i_rsvd : 11; - bdrkreg_t i_precise : 1; - bdrkreg_t i_rsvd_1 : 2; - bdrkreg_t i_crb_mark : 15; - bdrkreg_t i_crb_vld : 15; - bdrkreg_t i_fc_cnt : 4; - bdrkreg_t i_rsvd_2 : 2; - bdrkreg_t i_clr_rppd : 1; - bdrkreg_t i_clr_rqpd : 1; - bdrkreg_t i_rsvd_3 : 4; - bdrkreg_t i_c_cnt : 4; - bdrkreg_t i_rsvd_4 : 2; - bdrkreg_t i_rd_hdr : 1; - bdrkreg_t i_sp_msg : 1; - } ii_icmr_fld_s; -} ii_icmr_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register allows control of the table portion of the CRB * - * logic via software. Control operations from this register have * - * priority over all incoming Crosstalk or BTE requests. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_iccr_u { - bdrkreg_t ii_iccr_regval; - struct { - bdrkreg_t i_crb_num : 4; - bdrkreg_t i_rsvd_1 : 4; - bdrkreg_t i_cmd : 8; - bdrkreg_t i_pending : 1; - bdrkreg_t i_rsvd : 47; - } ii_iccr_fld_s; -} ii_iccr_u_t; - -#else - -typedef union ii_iccr_u { - bdrkreg_t ii_iccr_regval; - struct { - bdrkreg_t i_rsvd : 47; - bdrkreg_t i_pending : 1; - bdrkreg_t i_cmd : 8; - bdrkreg_t i_rsvd_1 : 4; - bdrkreg_t i_crb_num : 4; - } ii_iccr_fld_s; -} ii_iccr_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register allows the maximum timeout value to be programmed. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_icto_u { - bdrkreg_t ii_icto_regval; - struct { - bdrkreg_t i_timeout : 8; - bdrkreg_t i_rsvd : 56; - } ii_icto_fld_s; -} ii_icto_u_t; - -#else - -typedef union ii_icto_u { - bdrkreg_t ii_icto_regval; - struct { - bdrkreg_t i_rsvd : 56; - bdrkreg_t i_timeout : 8; - } ii_icto_fld_s; -} ii_icto_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register allows the timeout prescalar to be programmed. An * - * internal counter is associated with this register. When the * - * internal counter reaches the value of the PRESCALE field, the * - * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] * - * field). The internal counter resets to zero, and then continues * - * counting. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ictp_u { - bdrkreg_t ii_ictp_regval; - struct { - bdrkreg_t i_prescale : 24; - bdrkreg_t i_rsvd : 40; - } ii_ictp_fld_s; -} ii_ictp_u_t; - -#else - -typedef union ii_ictp_u { - bdrkreg_t ii_ictp_regval; - struct { - bdrkreg_t i_rsvd : 40; - bdrkreg_t i_prescale : 24; - } ii_ictp_fld_s; -} ii_ictp_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * - * used for Crosstalk operations (both cacheline and partial * - * operations) or BTE/IO. Because the CRB entries are very wide, four * - * registers (_A to _D) are required to read and write each entry. * - * The CRB Entry registers can be conceptualized as rows and columns * - * (illustrated in the table above). Each row contains the 4 * - * registers required for a single CRB Entry. The first doubleword * - * (column) for each entry is labeled A, and the second doubleword * - * (higher address) is labeled B, the third doubleword is labeled C, * - * and the fourth doubleword is labeled D. All CRB entries have their * - * addresses on a quarter cacheline aligned boundary. * - * Upon reset, only the following fields are initialized: valid * - * (VLD), priority count, timeout, timeout valid, and context valid. * - * All other bits should be cleared by software before use (after * - * recovering any potential error state from before the reset). * - * The following four tables summarize the format for the four * - * registers that are used for each ICRB# Entry. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_icrb0_a_u { - bdrkreg_t ii_icrb0_a_regval; - struct { - bdrkreg_t ia_iow : 1; - bdrkreg_t ia_vld : 1; - bdrkreg_t ia_addr : 38; - bdrkreg_t ia_tnum : 5; - bdrkreg_t ia_sidn : 4; - bdrkreg_t ia_xt_err : 1; - bdrkreg_t ia_mark : 1; - bdrkreg_t ia_ln_uce : 1; - bdrkreg_t ia_errcode : 3; - bdrkreg_t ia_error : 1; - bdrkreg_t ia_stall__bte_1 : 1; - bdrkreg_t ia_stall__bte_0 : 1; - bdrkreg_t ia_rsvd : 6; - } ii_icrb0_a_fld_s; -} ii_icrb0_a_u_t; - -#else - -typedef union ii_icrb0_a_u { - bdrkreg_t ii_icrb0_a_regval; - struct { - bdrkreg_t ia_rsvd : 6; - bdrkreg_t ia_stall__bte_0 : 1; - bdrkreg_t ia_stall__bte_1 : 1; - bdrkreg_t ia_error : 1; - bdrkreg_t ia_errcode : 3; - bdrkreg_t ia_ln_uce : 1; - bdrkreg_t ia_mark : 1; - bdrkreg_t ia_xt_err : 1; - bdrkreg_t ia_sidn : 4; - bdrkreg_t ia_tnum : 5; - bdrkreg_t ia_addr : 38; - bdrkreg_t ia_vld : 1; - bdrkreg_t ia_iow : 1; - } ii_icrb0_a_fld_s; -} ii_icrb0_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * - * used for Crosstalk operations (both cacheline and partial * - * operations) or BTE/IO. Because the CRB entries are very wide, four * - * registers (_A to _D) are required to read and write each entry. * - * * - ************************************************************************/ - - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_icrb0_b_u { - bdrkreg_t ii_icrb0_b_regval; - struct { - bdrkreg_t ib_stall__intr : 1; - bdrkreg_t ib_stall_ib : 1; - bdrkreg_t ib_intvn : 1; - bdrkreg_t ib_wb : 1; - bdrkreg_t ib_hold : 1; - bdrkreg_t ib_ack : 1; - bdrkreg_t ib_resp : 1; - bdrkreg_t ib_ack_cnt : 11; - bdrkreg_t ib_rsvd_1 : 7; - bdrkreg_t ib_exc : 5; - bdrkreg_t ib_init : 3; - bdrkreg_t ib_imsg : 8; - bdrkreg_t ib_imsgtype : 2; - bdrkreg_t ib_use_old : 1; - bdrkreg_t ib_source : 12; - bdrkreg_t ib_size : 2; - bdrkreg_t ib_ct : 1; - bdrkreg_t ib_bte_num : 1; - bdrkreg_t ib_rsvd : 4; - } ii_icrb0_b_fld_s; -} ii_icrb0_b_u_t; - -#else - -typedef union ii_icrb0_b_u { - bdrkreg_t ii_icrb0_b_regval; - struct { - bdrkreg_t ib_rsvd : 4; - bdrkreg_t ib_bte_num : 1; - bdrkreg_t ib_ct : 1; - bdrkreg_t ib_size : 2; - bdrkreg_t ib_source : 12; - bdrkreg_t ib_use_old : 1; - bdrkreg_t ib_imsgtype : 2; - bdrkreg_t ib_imsg : 8; - bdrkreg_t ib_init : 3; - bdrkreg_t ib_exc : 5; - bdrkreg_t ib_rsvd_1 : 7; - bdrkreg_t ib_ack_cnt : 11; - bdrkreg_t ib_resp : 1; - bdrkreg_t ib_ack : 1; - bdrkreg_t ib_hold : 1; - bdrkreg_t ib_wb : 1; - bdrkreg_t ib_intvn : 1; - bdrkreg_t ib_stall_ib : 1; - bdrkreg_t ib_stall__intr : 1; - } ii_icrb0_b_fld_s; -} ii_icrb0_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * - * used for Crosstalk operations (both cacheline and partial * - * operations) or BTE/IO. Because the CRB entries are very wide, four * - * registers (_A to _D) are required to read and write each entry. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_icrb0_c_u { - bdrkreg_t ii_icrb0_c_regval; - struct { - bdrkreg_t ic_gbr : 1; - bdrkreg_t ic_resprqd : 1; - bdrkreg_t ic_bo : 1; - bdrkreg_t ic_suppl : 12; - bdrkreg_t ic_pa_be : 34; - bdrkreg_t ic_bte_op : 1; - bdrkreg_t ic_pr_psc : 4; - bdrkreg_t ic_pr_cnt : 4; - bdrkreg_t ic_sleep : 1; - bdrkreg_t ic_rsvd : 5; - } ii_icrb0_c_fld_s; -} ii_icrb0_c_u_t; - -#else - -typedef union ii_icrb0_c_u { - bdrkreg_t ii_icrb0_c_regval; - struct { - bdrkreg_t ic_rsvd : 5; - bdrkreg_t ic_sleep : 1; - bdrkreg_t ic_pr_cnt : 4; - bdrkreg_t ic_pr_psc : 4; - bdrkreg_t ic_bte_op : 1; - bdrkreg_t ic_pa_be : 34; - bdrkreg_t ic_suppl : 12; - bdrkreg_t ic_bo : 1; - bdrkreg_t ic_resprqd : 1; - bdrkreg_t ic_gbr : 1; - } ii_icrb0_c_fld_s; -} ii_icrb0_c_u_t; - -#endif - - - -/************************************************************************ - * * - * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * - * used for Crosstalk operations (both cacheline and partial * - * operations) or BTE/IO. Because the CRB entries are very wide, four * - * registers (_A to _D) are required to read and write each entry. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_icrb0_d_u { - bdrkreg_t ii_icrb0_d_regval; - struct { - bdrkreg_t id_timeout : 8; - bdrkreg_t id_context : 15; - bdrkreg_t id_rsvd_1 : 1; - bdrkreg_t id_tvld : 1; - bdrkreg_t id_cvld : 1; - bdrkreg_t id_rsvd : 38; - } ii_icrb0_d_fld_s; -} ii_icrb0_d_u_t; - -#else - -typedef union ii_icrb0_d_u { - bdrkreg_t ii_icrb0_d_regval; - struct { - bdrkreg_t id_rsvd : 38; - bdrkreg_t id_cvld : 1; - bdrkreg_t id_tvld : 1; - bdrkreg_t id_rsvd_1 : 1; - bdrkreg_t id_context : 15; - bdrkreg_t id_timeout : 8; - } ii_icrb0_d_fld_s; -} ii_icrb0_d_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the lower 64 bits of the header of the * - * spurious message captured by II. Valid when the SP_MSG bit in ICMR * - * register is set. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_icsml_u { - bdrkreg_t ii_icsml_regval; - struct { - bdrkreg_t i_tt_addr : 38; - bdrkreg_t i_tt_ack_cnt : 11; - bdrkreg_t i_newsuppl_ex : 11; - bdrkreg_t i_reserved : 3; - bdrkreg_t i_overflow : 1; - } ii_icsml_fld_s; -} ii_icsml_u_t; - -#else - -typedef union ii_icsml_u { - bdrkreg_t ii_icsml_regval; - struct { - bdrkreg_t i_overflow : 1; - bdrkreg_t i_reserved : 3; - bdrkreg_t i_newsuppl_ex : 11; - bdrkreg_t i_tt_ack_cnt : 11; - bdrkreg_t i_tt_addr : 38; - } ii_icsml_fld_s; -} ii_icsml_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the microscopic state, all the inputs to * - * the protocol table, captured with the spurious message. Valid when * - * the SP_MSG bit in the ICMR register is set. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_icsmh_u { - bdrkreg_t ii_icsmh_regval; - struct { - bdrkreg_t i_tt_vld : 1; - bdrkreg_t i_xerr : 1; - bdrkreg_t i_ft_cwact_o : 1; - bdrkreg_t i_ft_wact_o : 1; - bdrkreg_t i_ft_active_o : 1; - bdrkreg_t i_sync : 1; - bdrkreg_t i_mnusg : 1; - bdrkreg_t i_mnusz : 1; - bdrkreg_t i_plusz : 1; - bdrkreg_t i_plusg : 1; - bdrkreg_t i_tt_exc : 5; - bdrkreg_t i_tt_wb : 1; - bdrkreg_t i_tt_hold : 1; - bdrkreg_t i_tt_ack : 1; - bdrkreg_t i_tt_resp : 1; - bdrkreg_t i_tt_intvn : 1; - bdrkreg_t i_g_stall_bte1 : 1; - bdrkreg_t i_g_stall_bte0 : 1; - bdrkreg_t i_g_stall_il : 1; - bdrkreg_t i_g_stall_ib : 1; - bdrkreg_t i_tt_imsg : 8; - bdrkreg_t i_tt_imsgtype : 2; - bdrkreg_t i_tt_use_old : 1; - bdrkreg_t i_tt_respreqd : 1; - bdrkreg_t i_tt_bte_num : 1; - bdrkreg_t i_cbn : 1; - bdrkreg_t i_match : 1; - bdrkreg_t i_rpcnt_lt_34 : 1; - bdrkreg_t i_rpcnt_ge_34 : 1; - bdrkreg_t i_rpcnt_lt_18 : 1; - bdrkreg_t i_rpcnt_ge_18 : 1; - bdrkreg_t i_rpcnt_lt_2 : 1; - bdrkreg_t i_rpcnt_ge_2 : 1; - bdrkreg_t i_rqcnt_lt_18 : 1; - bdrkreg_t i_rqcnt_ge_18 : 1; - bdrkreg_t i_rqcnt_lt_2 : 1; - bdrkreg_t i_rqcnt_ge_2 : 1; - bdrkreg_t i_tt_device : 7; - bdrkreg_t i_tt_init : 3; - bdrkreg_t i_reserved : 5; - } ii_icsmh_fld_s; -} ii_icsmh_u_t; - -#else - -typedef union ii_icsmh_u { - bdrkreg_t ii_icsmh_regval; - struct { - bdrkreg_t i_reserved : 5; - bdrkreg_t i_tt_init : 3; - bdrkreg_t i_tt_device : 7; - bdrkreg_t i_rqcnt_ge_2 : 1; - bdrkreg_t i_rqcnt_lt_2 : 1; - bdrkreg_t i_rqcnt_ge_18 : 1; - bdrkreg_t i_rqcnt_lt_18 : 1; - bdrkreg_t i_rpcnt_ge_2 : 1; - bdrkreg_t i_rpcnt_lt_2 : 1; - bdrkreg_t i_rpcnt_ge_18 : 1; - bdrkreg_t i_rpcnt_lt_18 : 1; - bdrkreg_t i_rpcnt_ge_34 : 1; - bdrkreg_t i_rpcnt_lt_34 : 1; - bdrkreg_t i_match : 1; - bdrkreg_t i_cbn : 1; - bdrkreg_t i_tt_bte_num : 1; - bdrkreg_t i_tt_respreqd : 1; - bdrkreg_t i_tt_use_old : 1; - bdrkreg_t i_tt_imsgtype : 2; - bdrkreg_t i_tt_imsg : 8; - bdrkreg_t i_g_stall_ib : 1; - bdrkreg_t i_g_stall_il : 1; - bdrkreg_t i_g_stall_bte0 : 1; - bdrkreg_t i_g_stall_bte1 : 1; - bdrkreg_t i_tt_intvn : 1; - bdrkreg_t i_tt_resp : 1; - bdrkreg_t i_tt_ack : 1; - bdrkreg_t i_tt_hold : 1; - bdrkreg_t i_tt_wb : 1; - bdrkreg_t i_tt_exc : 5; - bdrkreg_t i_plusg : 1; - bdrkreg_t i_plusz : 1; - bdrkreg_t i_mnusz : 1; - bdrkreg_t i_mnusg : 1; - bdrkreg_t i_sync : 1; - bdrkreg_t i_ft_active_o : 1; - bdrkreg_t i_ft_wact_o : 1; - bdrkreg_t i_ft_cwact_o : 1; - bdrkreg_t i_xerr : 1; - bdrkreg_t i_tt_vld : 1; - } ii_icsmh_fld_s; -} ii_icsmh_u_t; - -#endif - - -/************************************************************************ - * * - * The Bedrock DEBUG unit provides a 3-bit selection signal to the * - * II unit, thus allowing a choice of one set of debug signal outputs * - * from a menu of 8 options. Each option is limited to 32 bits in * - * size. There are more signals of interest than can be accommodated * - * in this 8*32 framework, so the IDBSS register has been defined to * - * extend the range of choices available. For each menu option * - * available to the DEBUG unit, the II provides a "submenu" of * - * several options. The value of the SUBMENU field in the IDBSS * - * register selects the desired submenu. Hence, the particular debug * - * signals provided by the II are determined by the 3-bit selection * - * signal from the DEBUG unit and the value of the SUBMENU field * - * within the IDBSS register. For a detailed description of the * - * available menus and submenus for II debug signals, refer to the * - * documentation in ii_interface.doc.. * - * * - ************************************************************************/ - - - - -#ifdef LIITLE_ENDIAN - -typedef union ii_idbss_u { - bdrkreg_t ii_idbss_regval; - struct { - bdrkreg_t i_submenu : 3; - bdrkreg_t i_rsvd : 61; - } ii_idbss_fld_s; -} ii_idbss_u_t; - -#else - -typedef union ii_idbss_u { - bdrkreg_t ii_idbss_regval; - struct { - bdrkreg_t i_rsvd : 61; - bdrkreg_t i_submenu : 3; - } ii_idbss_fld_s; -} ii_idbss_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This register is used to set up the length for a * - * transfer and then to monitor the progress of that transfer. This * - * register needs to be initialized before a transfer is started. A * - * legitimate write to this register will set the Busy bit, clear the * - * Error bit, and initialize the length to the value desired. * - * While the transfer is in progress, hardware will decrement the * - * length field with each successful block that is copied. Once the * - * transfer completes, hardware will clear the Busy bit. The length * - * field will also contain the number of cache lines left to be * - * transferred. * - * * - ************************************************************************/ - - - - -#ifdef LIITLE_ENDIAN - -typedef union ii_ibls0_u { - bdrkreg_t ii_ibls0_regval; - struct { - bdrkreg_t i_length : 16; - bdrkreg_t i_error : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_busy : 1; - bdrkreg_t i_rsvd : 43; - } ii_ibls0_fld_s; -} ii_ibls0_u_t; - -#else - -typedef union ii_ibls0_u { - bdrkreg_t ii_ibls0_regval; - struct { - bdrkreg_t i_rsvd : 43; - bdrkreg_t i_busy : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_error : 1; - bdrkreg_t i_length : 16; - } ii_ibls0_fld_s; -} ii_ibls0_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register should be loaded before a transfer is started. The * - * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * - * address as described in Section 1.3, Figure2 and Figure3. Since * - * the bottom 7 bits of the address are always taken to be zero, BTE * - * transfers are always cacheline-aligned. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ibsa0_u { - bdrkreg_t ii_ibsa0_regval; - struct { - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_addr : 33; - bdrkreg_t i_rsvd : 24; - } ii_ibsa0_fld_s; -} ii_ibsa0_u_t; - -#else - -typedef union ii_ibsa0_u { - bdrkreg_t ii_ibsa0_regval; - struct { - bdrkreg_t i_rsvd : 24; - bdrkreg_t i_addr : 33; - bdrkreg_t i_rsvd_1 : 7; - } ii_ibsa0_fld_s; -} ii_ibsa0_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register should be loaded before a transfer is started. The * - * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * - * address as described in Section 1.3, Figure2 and Figure3. Since * - * the bottom 7 bits of the address are always taken to be zero, BTE * - * transfers are always cacheline-aligned. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ibda0_u { - bdrkreg_t ii_ibda0_regval; - struct { - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_addr : 33; - bdrkreg_t i_rsvd : 24; - } ii_ibda0_fld_s; -} ii_ibda0_u_t; - -#else - -typedef union ii_ibda0_u { - bdrkreg_t ii_ibda0_regval; - struct { - bdrkreg_t i_rsvd : 24; - bdrkreg_t i_addr : 33; - bdrkreg_t i_rsvd_1 : 7; - } ii_ibda0_fld_s; -} ii_ibda0_u_t; - -#endif - - - - -/************************************************************************ - * * - * Writing to this register sets up the attributes of the transfer * - * and initiates the transfer operation. Reading this register has * - * the side effect of terminating any transfer in progress. Note: * - * stopping a transfer midstream could have an adverse impact on the * - * other BTE. If a BTE stream has to be stopped (due to error * - * handling for example), both BTE streams should be stopped and * - * their transfers discarded. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ibct0_u { - bdrkreg_t ii_ibct0_regval; - struct { - bdrkreg_t i_zerofill : 1; - bdrkreg_t i_rsvd_2 : 3; - bdrkreg_t i_notify : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_poison : 1; - bdrkreg_t i_rsvd : 55; - } ii_ibct0_fld_s; -} ii_ibct0_u_t; - -#else - -typedef union ii_ibct0_u { - bdrkreg_t ii_ibct0_regval; - struct { - bdrkreg_t i_rsvd : 55; - bdrkreg_t i_poison : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_notify : 1; - bdrkreg_t i_rsvd_2 : 3; - bdrkreg_t i_zerofill : 1; - } ii_ibct0_fld_s; -} ii_ibct0_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the address to which the WINV is sent. * - * This address has to be cache line aligned. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ibna0_u { - bdrkreg_t ii_ibna0_regval; - struct { - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_addr : 33; - bdrkreg_t i_rsvd : 24; - } ii_ibna0_fld_s; -} ii_ibna0_u_t; - -#else - -typedef union ii_ibna0_u { - bdrkreg_t ii_ibna0_regval; - struct { - bdrkreg_t i_rsvd : 24; - bdrkreg_t i_addr : 33; - bdrkreg_t i_rsvd_1 : 7; - } ii_ibna0_fld_s; -} ii_ibna0_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the programmable level as well as the node * - * ID and PI unit of the processor to which the interrupt will be * - * sent. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ibia0_u { - bdrkreg_t ii_ibia0_regval; - struct { - bdrkreg_t i_pi_id : 1; - bdrkreg_t i_node_id : 8; - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_level : 7; - bdrkreg_t i_rsvd : 41; - } ii_ibia0_fld_s; -} ii_ibia0_u_t; - -#else - -typedef union ii_ibia0_u { - bdrkreg_t ii_ibia0_regval; - struct { - bdrkreg_t i_rsvd : 41; - bdrkreg_t i_level : 7; - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_node_id : 8; - bdrkreg_t i_pi_id : 1; - } ii_ibia0_fld_s; -} ii_ibia0_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This register is used to set up the length for a * - * transfer and then to monitor the progress of that transfer. This * - * register needs to be initialized before a transfer is started. A * - * legitimate write to this register will set the Busy bit, clear the * - * Error bit, and initialize the length to the value desired. * - * While the transfer is in progress, hardware will decrement the * - * length field with each successful block that is copied. Once the * - * transfer completes, hardware will clear the Busy bit. The length * - * field will also contain the number of cache lines left to be * - * transferred. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ibls1_u { - bdrkreg_t ii_ibls1_regval; - struct { - bdrkreg_t i_length : 16; - bdrkreg_t i_error : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_busy : 1; - bdrkreg_t i_rsvd : 43; - } ii_ibls1_fld_s; -} ii_ibls1_u_t; - -#else - -typedef union ii_ibls1_u { - bdrkreg_t ii_ibls1_regval; - struct { - bdrkreg_t i_rsvd : 43; - bdrkreg_t i_busy : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_error : 1; - bdrkreg_t i_length : 16; - } ii_ibls1_fld_s; -} ii_ibls1_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register should be loaded before a transfer is started. The * - * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * - * address as described in Section 1.3, Figure2 and Figure3. Since * - * the bottom 7 bits of the address are always taken to be zero, BTE * - * transfers are always cacheline-aligned. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ibsa1_u { - bdrkreg_t ii_ibsa1_regval; - struct { - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_addr : 33; - bdrkreg_t i_rsvd : 24; - } ii_ibsa1_fld_s; -} ii_ibsa1_u_t; - -#else - -typedef union ii_ibsa1_u { - bdrkreg_t ii_ibsa1_regval; - struct { - bdrkreg_t i_rsvd : 24; - bdrkreg_t i_addr : 33; - bdrkreg_t i_rsvd_1 : 7; - } ii_ibsa1_fld_s; -} ii_ibsa1_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register should be loaded before a transfer is started. The * - * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * - * address as described in Section 1.3, Figure2 and Figure3. Since * - * the bottom 7 bits of the address are always taken to be zero, BTE * - * transfers are always cacheline-aligned. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ibda1_u { - bdrkreg_t ii_ibda1_regval; - struct { - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_addr : 33; - bdrkreg_t i_rsvd : 24; - } ii_ibda1_fld_s; -} ii_ibda1_u_t; - -#else - -typedef union ii_ibda1_u { - bdrkreg_t ii_ibda1_regval; - struct { - bdrkreg_t i_rsvd : 24; - bdrkreg_t i_addr : 33; - bdrkreg_t i_rsvd_1 : 7; - } ii_ibda1_fld_s; -} ii_ibda1_u_t; - -#endif - - - - -/************************************************************************ - * * - * Writing to this register sets up the attributes of the transfer * - * and initiates the transfer operation. Reading this register has * - * the side effect of terminating any transfer in progress. Note: * - * stopping a transfer midstream could have an adverse impact on the * - * other BTE. If a BTE stream has to be stopped (due to error * - * handling for example), both BTE streams should be stopped and * - * their transfers discarded. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ibct1_u { - bdrkreg_t ii_ibct1_regval; - struct { - bdrkreg_t i_zerofill : 1; - bdrkreg_t i_rsvd_2 : 3; - bdrkreg_t i_notify : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_poison : 1; - bdrkreg_t i_rsvd : 55; - } ii_ibct1_fld_s; -} ii_ibct1_u_t; - -#else - -typedef union ii_ibct1_u { - bdrkreg_t ii_ibct1_regval; - struct { - bdrkreg_t i_rsvd : 55; - bdrkreg_t i_poison : 1; - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_notify : 1; - bdrkreg_t i_rsvd_2 : 3; - bdrkreg_t i_zerofill : 1; - } ii_ibct1_fld_s; -} ii_ibct1_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the address to which the WINV is sent. * - * This address has to be cache line aligned. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ibna1_u { - bdrkreg_t ii_ibna1_regval; - struct { - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_addr : 33; - bdrkreg_t i_rsvd : 24; - } ii_ibna1_fld_s; -} ii_ibna1_u_t; - -#else - -typedef union ii_ibna1_u { - bdrkreg_t ii_ibna1_regval; - struct { - bdrkreg_t i_rsvd : 24; - bdrkreg_t i_addr : 33; - bdrkreg_t i_rsvd_1 : 7; - } ii_ibna1_fld_s; -} ii_ibna1_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the programmable level as well as the node * - * ID and PI unit of the processor to which the interrupt will be * - * sent. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ibia1_u { - bdrkreg_t ii_ibia1_regval; - struct { - bdrkreg_t i_pi_id : 1; - bdrkreg_t i_node_id : 8; - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_level : 7; - bdrkreg_t i_rsvd : 41; - } ii_ibia1_fld_s; -} ii_ibia1_u_t; - -#else - -typedef union ii_ibia1_u { - bdrkreg_t ii_ibia1_regval; - struct { - bdrkreg_t i_rsvd : 41; - bdrkreg_t i_level : 7; - bdrkreg_t i_rsvd_1 : 7; - bdrkreg_t i_node_id : 8; - bdrkreg_t i_pi_id : 1; - } ii_ibia1_fld_s; -} ii_ibia1_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register defines the resources that feed information into * - * the two performance counters located in the IO Performance * - * Profiling Register. There are 17 different quantities that can be * - * measured. Given these 17 different options, the two performance * - * counters have 15 of them in common; menu selections 0 through 0xE * - * are identical for each performance counter. As for the other two * - * options, one is available from one performance counter and the * - * other is available from the other performance counter. Hence, the * - * II supports all 17*16=272 possible combinations of quantities to * - * measure. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ipcr_u { - bdrkreg_t ii_ipcr_regval; - struct { - bdrkreg_t i_ippr0_c : 4; - bdrkreg_t i_ippr1_c : 4; - bdrkreg_t i_icct : 8; - bdrkreg_t i_rsvd : 48; - } ii_ipcr_fld_s; -} ii_ipcr_u_t; - -#else - -typedef union ii_ipcr_u { - bdrkreg_t ii_ipcr_regval; - struct { - bdrkreg_t i_rsvd : 48; - bdrkreg_t i_icct : 8; - bdrkreg_t i_ippr1_c : 4; - bdrkreg_t i_ippr0_c : 4; - } ii_ipcr_fld_s; -} ii_ipcr_u_t; - -#endif - - - - -/************************************************************************ - * * - * * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ii_ippr_u { - bdrkreg_t ii_ippr_regval; - struct { - bdrkreg_t i_ippr0 : 32; - bdrkreg_t i_ippr1 : 32; - } ii_ippr_fld_s; -} ii_ippr_u_t; - -#else - -typedef union ii_ippr_u { - bdrkreg_t ii_ippr_regval; - struct { - bdrkreg_t i_ippr1 : 32; - bdrkreg_t i_ippr0 : 32; - } ii_ippr_fld_s; -} ii_ippr_u_t; - -#endif - - - - - - -#endif /* __ASSEMBLY__ */ - -/************************************************************************ - * * - * The following defines which were not formed into structures are * - * probably indentical to another register, and the name of the * - * register is provided against each of these registers. This * - * information needs to be checked carefully * - * * - * IIO_ICRB1_A IIO_ICRB0_A * - * IIO_ICRB1_B IIO_ICRB0_B * - * IIO_ICRB1_C IIO_ICRB0_C * - * IIO_ICRB1_D IIO_ICRB0_D * - * IIO_ICRB2_A IIO_ICRB0_A * - * IIO_ICRB2_B IIO_ICRB0_B * - * IIO_ICRB2_C IIO_ICRB0_C * - * IIO_ICRB2_D IIO_ICRB0_D * - * IIO_ICRB3_A IIO_ICRB0_A * - * IIO_ICRB3_B IIO_ICRB0_B * - * IIO_ICRB3_C IIO_ICRB0_C * - * IIO_ICRB3_D IIO_ICRB0_D * - * IIO_ICRB4_A IIO_ICRB0_A * - * IIO_ICRB4_B IIO_ICRB0_B * - * IIO_ICRB4_C IIO_ICRB0_C * - * IIO_ICRB4_D IIO_ICRB0_D * - * IIO_ICRB5_A IIO_ICRB0_A * - * IIO_ICRB5_B IIO_ICRB0_B * - * IIO_ICRB5_C IIO_ICRB0_C * - * IIO_ICRB5_D IIO_ICRB0_D * - * IIO_ICRB6_A IIO_ICRB0_A * - * IIO_ICRB6_B IIO_ICRB0_B * - * IIO_ICRB6_C IIO_ICRB0_C * - * IIO_ICRB6_D IIO_ICRB0_D * - * IIO_ICRB7_A IIO_ICRB0_A * - * IIO_ICRB7_B IIO_ICRB0_B * - * IIO_ICRB7_C IIO_ICRB0_C * - * IIO_ICRB7_D IIO_ICRB0_D * - * IIO_ICRB8_A IIO_ICRB0_A * - * IIO_ICRB8_B IIO_ICRB0_B * - * IIO_ICRB8_C IIO_ICRB0_C * - * IIO_ICRB8_D IIO_ICRB0_D * - * IIO_ICRB9_A IIO_ICRB0_A * - * IIO_ICRB9_B IIO_ICRB0_B * - * IIO_ICRB9_C IIO_ICRB0_C * - * IIO_ICRB9_D IIO_ICRB0_D * - * IIO_ICRBA_A IIO_ICRB0_A * - * IIO_ICRBA_B IIO_ICRB0_B * - * IIO_ICRBA_C IIO_ICRB0_C * - * IIO_ICRBA_D IIO_ICRB0_D * - * IIO_ICRBB_A IIO_ICRB0_A * - * IIO_ICRBB_B IIO_ICRB0_B * - * IIO_ICRBB_C IIO_ICRB0_C * - * IIO_ICRBB_D IIO_ICRB0_D * - * IIO_ICRBC_A IIO_ICRB0_A * - * IIO_ICRBC_B IIO_ICRB0_B * - * IIO_ICRBC_C IIO_ICRB0_C * - * IIO_ICRBC_D IIO_ICRB0_D * - * IIO_ICRBD_A IIO_ICRB0_A * - * IIO_ICRBD_B IIO_ICRB0_B * - * IIO_ICRBD_C IIO_ICRB0_C * - * IIO_ICRBD_D IIO_ICRB0_D * - * IIO_ICRBE_A IIO_ICRB0_A * - * IIO_ICRBE_B IIO_ICRB0_B * - * IIO_ICRBE_C IIO_ICRB0_C * - * IIO_ICRBE_D IIO_ICRB0_D * - * * - ************************************************************************/ - - -/************************************************************************ - * * - * MAKE ALL ADDITIONS AFTER THIS LINE * - * * - ************************************************************************/ - - - - - -#endif /* _ASM_IA64_SN_SN1_HUBIO_H */ diff --git a/include/asm-ia64/sn/sn1/hubio_next.h b/include/asm-ia64/sn/sn1/hubio_next.h deleted file mode 100644 index 037d3bae307d2..0000000000000 --- a/include/asm-ia64/sn/sn1/hubio_next.h +++ /dev/null @@ -1,762 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_HUBIO_NEXT_H -#define _ASM_IA64_SN_SN1_HUBIO_NEXT_H - -/* - * Slightly friendlier names for some common registers. - */ -#define IIO_WIDGET IIO_WID /* Widget identification */ -#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */ -#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */ -#define IIO_PROTECT IIO_ILAPR /* IO interface protection */ -#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */ -#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */ -#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */ -#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */ -#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */ -#define IIO_LLP_LOG IIO_ILLR /* LLP log */ -#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/ -#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */ -#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */ -#define IIO_IGFX_0 IIO_IGFX0 -#define IIO_IGFX_1 IIO_IGFX1 -#define IIO_IBCT_0 IIO_IBCT0 -#define IIO_IBCT_1 IIO_IBCT1 -#define IIO_IBLS_0 IIO_IBLS0 -#define IIO_IBLS_1 IIO_IBLS1 -#define IIO_IBSA_0 IIO_IBSA0 -#define IIO_IBSA_1 IIO_IBSA1 -#define IIO_IBDA_0 IIO_IBDA0 -#define IIO_IBDA_1 IIO_IBDA1 -#define IIO_IBNA_0 IIO_IBNA0 -#define IIO_IBNA_1 IIO_IBNA1 -#define IIO_IBIA_0 IIO_IBIA0 -#define IIO_IBIA_1 IIO_IBIA1 -#define IIO_IOPRB_0 IIO_IPRB0 -#define IIO_PRTE_0 IIO_IPRTE0 /* PIO Read address table entry 0 */ -#define IIO_PRTE(_x) (IIO_PRTE_0 + (8 * (_x))) -#define IIO_NUM_IPRBS (9) -#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */ - -#define IIO_LLP_CSR_IS_UP 0x00002000 -#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000 -#define IIO_LLP_CSR_LLP_STAT_SHFT 12 - -#define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */ -#define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */ - -/* key to IIO_PROTECT_OVRRD */ -#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */ - -/* BTE register names */ -#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */ -#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ -#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */ -#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */ -#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ -#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ -#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ -#define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */ - -/* BTE register offsets from base */ -#define BTEOFF_STAT 0 -#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0) -#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0) -#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0) -#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0) -#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0) - - -/* names used in hub_diags.c; carried over from SN0 */ -#define IIO_BASE_BTE0 IIO_IBLS_0 -#define IIO_BASE_BTE1 IIO_IBLS_1 - -/* - * Macro which takes the widget number, and returns the - * IO PRB address of that widget. - * value _x is expected to be a widget number in the range - * 0, 8 - 0xF - */ -#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ - (_x) : \ - (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) - - -/* GFX Flow Control Node/Widget Register */ -#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */ -#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1) -#define IIO_IGFX_W_NUM_SHIFT 0 -#define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */ -#define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1) -#define IIO_IGFX_PI_NUM_SHIFT 4 -#define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */ -#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1) -#define IIO_IGFX_N_NUM_SHIFT 5 -#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */ -#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1) -#define IIO_IGFX_P_NUM_SHIFT 16 -#define IIO_IGFX_INIT(widget, pi, node, cpu) (\ - (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \ - (((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)| \ - (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \ - (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT)) - - -/* Scratch registers (all bits available) */ -#define IIO_SCRATCH_REG0 IIO_ISCR0 -#define IIO_SCRATCH_REG1 IIO_ISCR1 -#define IIO_SCRATCH_MASK 0xffffffffffffffff - -#define IIO_SCRATCH_BIT0_0 0x0000000000000001 -#define IIO_SCRATCH_BIT0_1 0x0000000000000002 -#define IIO_SCRATCH_BIT0_2 0x0000000000000004 -#define IIO_SCRATCH_BIT0_3 0x0000000000000008 -#define IIO_SCRATCH_BIT0_4 0x0000000000000010 -#define IIO_SCRATCH_BIT0_5 0x0000000000000020 -#define IIO_SCRATCH_BIT0_6 0x0000000000000040 -#define IIO_SCRATCH_BIT0_7 0x0000000000000080 -#define IIO_SCRATCH_BIT0_8 0x0000000000000100 -#define IIO_SCRATCH_BIT0_9 0x0000000000000200 -#define IIO_SCRATCH_BIT0_A 0x0000000000000400 - -#define IIO_SCRATCH_BIT1_0 0x0000000000000001 -#define IIO_SCRATCH_BIT1_1 0x0000000000000002 -/* IO Translation Table Entries */ -#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */ - /* Hw manuals number them 1..7! */ -/* - * IIO_IMEM Register fields. - */ -#define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */ -#define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */ -#define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */ - -/* - * As a permanent workaround for a bug in the PI side of the hub, we've - * redefined big window 7 as small window 0. - XXX does this still apply for SN1?? - */ -#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) - -/* - * Use the top big window as a surrogate for the first small window - */ -#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW - -#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */ - -#define ILCSR_WARM_RESET 0x100 - -/* - * CRB manipulation macros - * The CRB macros are slightly complicated, since there are up to - * four registers associated with each CRB entry. - */ -#define IIO_NUM_CRBS 15 /* Number of CRBs */ -#define IIO_NUM_NORMAL_CRBS 12 /* Number of regular CRB entries */ -#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ -#define IIO_ICRB_OFFSET 8 -#define IIO_ICRB_0 IIO_ICRB0_A -#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ -/* XXX - This is now tuneable: - #define IIO_FIRST_PC_ENTRY 12 - */ - -#define IIO_ICRB_A(_x) (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x))) -#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET) -#define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET) -#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET) - -#define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7) - -/* - * values for "ecode" field - */ -#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ -#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ -#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access - * e.g. WINV to a Read only line. */ -#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ -#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ -#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ -#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ -#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ - -/* - * Number of credits Hub widget has while sending req/response to - * xbow. - * Value of 3 is required by Xbow 1.1 - * We may be able to increase this to 4 with Xbow 1.2. - */ -#define HUBII_XBOW_CREDIT 3 -#define HUBII_XBOW_REV2_CREDIT 4 - -/* - * Number of credits that xtalk devices should use when communicating - * with a Bedrock (depth of Bedrock's queue). - */ -#define HUB_CREDIT 4 - -/* - * Some IIO_PRB fields - */ -#define IIO_PRB_MULTI_ERR (1LL << 63) -#define IIO_PRB_SPUR_RD (1LL << 51) -#define IIO_PRB_SPUR_WR (1LL << 50) -#define IIO_PRB_RD_TO (1LL << 49) -#define IIO_PRB_ERROR (1LL << 48) - -/************************************************************************* - - Some of the IIO field masks and shifts are defined here. - This is in order to maintain compatibility in SN0 and SN1 code - -**************************************************************************/ - -/* - * ICMR register fields - * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not - * present in Bedrock) - */ - -#define IIO_ICMR_CRB_VLD_SHFT 20 -#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT) - -#define IIO_ICMR_FC_CNT_SHFT 16 -#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT) - -#define IIO_ICMR_C_CNT_SHFT 4 -#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT) - -#define IIO_ICMR_PRECISE (1UL << 52) -#define IIO_ICMR_CLR_RPPD (1UL << 13) -#define IIO_ICMR_CLR_RQPD (1UL << 12) - -/* - * IIO PIO Deallocation register field masks : (IIO_IPDR) - XXX present but not needed in bedrock? See the manual. - */ -#define IIO_IPDR_PND (1 << 4) - -/* - * IIO CRB deallocation register field masks: (IIO_ICDR) - */ -#define IIO_ICDR_PND (1 << 4) - -/* - * IO BTE Length/Status (IIO_IBLS) register bit field definitions - */ -#define IBLS_BUSY (0x1 << 20) -#define IBLS_ERROR_SHFT 16 -#define IBLS_ERROR (0x1 << IBLS_ERROR_SHFT) -#define IBLS_LENGTH_MASK 0xffff - -/* - * IO BTE Control/Terminate register (IBCT) register bit field definitions - */ -#define IBCT_POISON (0x1 << 8) -#define IBCT_NOTIFY (0x1 << 4) -#define IBCT_ZFIL_MODE (0x1 << 0) - -/* - * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2) - */ -#define IIEPH1_VALID (1 << 44) -#define IIEPH1_OVERRUN (1 << 40) -#define IIEPH1_ERR_TYPE_SHFT 32 -#define IIEPH1_ERR_TYPE_MASK 0xf -#define IIEPH1_SOURCE_SHFT 20 -#define IIEPH1_SOURCE_MASK 11 -#define IIEPH1_SUPPL_SHFT 8 -#define IIEPH1_SUPPL_MASK 11 -#define IIEPH1_CMD_SHFT 0 -#define IIEPH1_CMD_MASK 7 - -#define IIEPH2_TAIL (1 << 40) -#define IIEPH2_ADDRESS_SHFT 0 -#define IIEPH2_ADDRESS_MASK 38 - -#define IIEPH1_ERR_SHORT_REQ 2 -#define IIEPH1_ERR_SHORT_REPLY 3 -#define IIEPH1_ERR_LONG_REQ 4 -#define IIEPH1_ERR_LONG_REPLY 5 - -/* - * IO Error Clear register bit field definitions - */ -#define IECLR_PI1_FWD_INT (1 << 31) /* clear PI1_FORWARD_INT in iidsr */ -#define IECLR_PI0_FWD_INT (1 << 30) /* clear PI0_FORWARD_INT in iidsr */ -#define IECLR_SPUR_RD_HDR (1 << 29) /* clear valid bit in ixss reg */ -#define IECLR_BTE1 (1 << 18) /* clear bte error 1 */ -#define IECLR_BTE0 (1 << 17) /* clear bte error 0 */ -#define IECLR_CRAZY (1 << 16) /* clear crazy bit in wstat reg */ -#define IECLR_PRB_F (1 << 15) /* clear err bit in PRB_F reg */ -#define IECLR_PRB_E (1 << 14) /* clear err bit in PRB_E reg */ -#define IECLR_PRB_D (1 << 13) /* clear err bit in PRB_D reg */ -#define IECLR_PRB_C (1 << 12) /* clear err bit in PRB_C reg */ -#define IECLR_PRB_B (1 << 11) /* clear err bit in PRB_B reg */ -#define IECLR_PRB_A (1 << 10) /* clear err bit in PRB_A reg */ -#define IECLR_PRB_9 (1 << 9) /* clear err bit in PRB_9 reg */ -#define IECLR_PRB_8 (1 << 8) /* clear err bit in PRB_8 reg */ -#define IECLR_PRB_0 (1 << 0) /* clear err bit in PRB_0 reg */ - -/* - * IIO CRB control register Fields: IIO_ICCR - */ -#define IIO_ICCR_PENDING (0x10000) -#define IIO_ICCR_CMD_MASK (0xFF) -#define IIO_ICCR_CMD_SHFT (7) -#define IIO_ICCR_CMD_NOP (0x0) /* No Op */ -#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */ -#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */ -#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory - * via a WB - */ -#define IIO_ICCR_CMD_FLUSH (0x800) - -/* - * - * CRB Register description. - * - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * - * Many of the fields in CRB are status bits used by hardware - * for implementation of the protocol. It's very dangerous to - * mess around with the CRB registers. - * - * It's OK to read the CRB registers and try to make sense out of the - * fields in CRB. - * - * Updating CRB requires all activities in Hub IIO to be quiesced. - * otherwise, a write to CRB could corrupt other CRB entries. - * CRBs are here only as a back door peek to hub IIO's status. - * Quiescing implies no dmas no PIOs - * either directly from the cpu or from sn0net. - * this is not something that can be done easily. So, AVOID updating - * CRBs. - */ - -#ifndef __ASSEMBLY__ - -/* - * Easy access macros for CRBs, all 4 registers (A-D) - */ -typedef ii_icrb0_a_u_t icrba_t; /* what it was called on SN0/hub */ -#define a_error ii_icrb0_a_fld_s.ia_error -#define a_ecode ii_icrb0_a_fld_s.ia_errcode -#define a_lnetuce ii_icrb0_a_fld_s.ia_ln_uce -#define a_mark ii_icrb0_a_fld_s.ia_mark -#define a_xerr ii_icrb0_a_fld_s.ia_xt_err -#define a_sidn ii_icrb0_a_fld_s.ia_sidn -#define a_tnum ii_icrb0_a_fld_s.ia_tnum -#define a_addr ii_icrb0_a_fld_s.ia_addr -#define a_valid ii_icrb0_a_fld_s.ia_vld -#define a_iow ii_icrb0_a_fld_s.ia_iow -#define a_regvalue ii_icrb0_a_regval - -typedef ii_icrb0_b_u_t icrbb_t; -#define b_btenum ii_icrb0_b_fld_s.ib_bte_num -#define b_cohtrans ii_icrb0_b_fld_s.ib_ct -#define b_xtsize ii_icrb0_b_fld_s.ib_size -#define b_source ii_icrb0_b_fld_s.ib_source -#define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype -#define b_imsg ii_icrb0_b_fld_s.ib_imsg -#define b_initiator ii_icrb0_b_fld_s.ib_init -#define b_regvalue ii_icrb0_b_regval - -typedef ii_icrb0_c_u_t icrbc_t; -#define c_pricnt ii_icrb0_c_fld_s.ic_pr_cnt -#define c_pripsc ii_icrb0_c_fld_s.ic_pr_psc -#define c_bteop ii_icrb0_c_fld_s.ic_bte_op -#define c_bteaddr ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/ -#define c_benable ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/ -#define c_suppl ii_icrb0_c_fld_s.ic_suppl -#define c_barrop ii_icrb0_c_fld_s.ic_bo -#define c_doresp ii_icrb0_c_fld_s.ic_resprqd -#define c_gbr ii_icrb0_c_fld_s.ic_gbr -#define c_regvalue ii_icrb0_c_regval - -typedef ii_icrb0_d_u_t icrbd_t; -#define icrbd_ctxtvld ii_icrb0_d_fld_s.id_cvld -#define icrbd_toutvld ii_icrb0_d_fld_s.id_tvld -#define icrbd_context ii_icrb0_d_fld_s.id_context -#define d_regvalue ii_icrb0_d_regval - -#endif /* __ASSEMBLY__ */ - -/* Number of widgets supported by hub */ -#define HUB_NUM_WIDGET 9 -#define HUB_WIDGET_ID_MIN 0x8 -#define HUB_WIDGET_ID_MAX 0xf - -#define HUB_WIDGET_PART_NUM 0xc110 -#define MAX_HUBS_PER_XBOW 2 - -#ifndef __ASSEMBLY__ -/* A few more #defines for backwards compatibility */ -#define iprb_t ii_iprb0_u_t -#define iprb_regval ii_iprb0_regval -#define iprb_mult_err ii_iprb0_fld_s.i_mult_err -#define iprb_spur_rd ii_iprb0_fld_s.i_spur_rd -#define iprb_spur_wr ii_iprb0_fld_s.i_spur_wr -#define iprb_rd_to ii_iprb0_fld_s.i_rd_to -#define iprb_ovflow ii_iprb0_fld_s.i_of_cnt -#define iprb_error ii_iprb0_fld_s.i_error -#define iprb_ff ii_iprb0_fld_s.i_f -#define iprb_mode ii_iprb0_fld_s.i_m -#define iprb_bnakctr ii_iprb0_fld_s.i_nb -#define iprb_anakctr ii_iprb0_fld_s.i_na -#define iprb_xtalkctr ii_iprb0_fld_s.i_c -#endif - -#define LNK_STAT_WORKING 0x2 - -#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ -#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ -#define IIO_WSTAT_TXRETRY_MASK (0x7F) /* should be 0xFF?? */ -#define IIO_WSTAT_TXRETRY_SHFT (16) -#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ - IIO_WSTAT_TXRETRY_MASK) - -/* Number of II perf. counters we can multiplex at once */ - -#define IO_PERF_SETS 32 - -#if __KERNEL__ -#ifndef __ASSEMBLY__ -/* XXX moved over from SN/SN0/hubio.h -- each should be checked for SN1 */ -#include <asm/sn/alenlist.h> -#include <asm/sn/dmamap.h> -#include <asm/sn/driver.h> -#include <asm/sn/xtalk/xtalk.h> - -/* Bit for the widget in inbound access register */ -#define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) -/* Bit for the widget in outbound access register */ -#define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) - -/* NOTE: The following define assumes that we are going to get - * widget numbers from 8 thru F and the device numbers within - * widget from 0 thru 7. - */ -#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) - -/* IO Interrupt Destination Register */ -#define IIO_IIDSR_SENT_SHIFT 28 -#define IIO_IIDSR_SENT_MASK 0x10000000 -#define IIO_IIDSR_ENB_SHIFT 24 -#define IIO_IIDSR_ENB_MASK 0x01000000 -#define IIO_IIDSR_NODE_SHIFT 8 -#define IIO_IIDSR_NODE_MASK 0x0000ff00 -#define IIO_IIDSR_PI_ID_SHIFT 8 -#define IIO_IIDSR_PI_ID_MASK 0x00000010 -#define IIO_IIDSR_LVL_SHIFT 0 -#define IIO_IIDSR_LVL_MASK 0x0000007f - -/* Xtalk timeout threshhold register (IIO_IXTT) */ -#define IXTT_RRSP_TO_SHFT 55 /* read response timeout */ -#define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT) -#define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */ -#define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT) -#define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */ -#define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT) - -/* - * The IO LLP control status register and widget control register - */ - -#ifdef LITTLE_ENDIAN - -typedef union hubii_wcr_u { - uint64_t wcr_reg_value; - struct { - uint64_t wcr_widget_id: 4, /* LLP crossbar credit */ - wcr_tag_mode: 1, /* Tag mode */ - wcr_rsvd1: 8, /* Reserved */ - wcr_xbar_crd: 3, /* LLP crossbar credit */ - wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */ - wcr_dir_con: 1, /* widget direct connect */ - wcr_e_thresh: 5, /* elasticity threshold */ - wcr_rsvd: 41; /* unused */ - } wcr_fields_s; -} hubii_wcr_t; - -#else - -typedef union hubii_wcr_u { - uint64_t wcr_reg_value; - struct { - uint64_t wcr_rsvd: 41, /* unused */ - wcr_e_thresh: 5, /* elasticity threshold */ - wcr_dir_con: 1, /* widget direct connect */ - wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */ - wcr_xbar_crd: 3, /* LLP crossbar credit */ - wcr_rsvd1: 8, /* Reserved */ - wcr_tag_mode: 1, /* Tag mode */ - wcr_widget_id: 4; /* LLP crossbar credit */ - } wcr_fields_s; -} hubii_wcr_t; - -#endif - -#define iwcr_dir_con wcr_fields_s.wcr_dir_con - -/* The structures below are defined to extract and modify the ii -performance registers */ - -/* io_perf_sel allows the caller to specify what tests will be - performed */ -#ifdef LITTLE_ENDIAN - -typedef union io_perf_sel { - uint64_t perf_sel_reg; - struct { - uint64_t perf_ippr0 : 4, - perf_ippr1 : 4, - perf_icct : 8, - perf_rsvd : 48; - } perf_sel_bits; -} io_perf_sel_t; - -#else - -typedef union io_perf_sel { - uint64_t perf_sel_reg; - struct { - uint64_t perf_rsvd : 48, - perf_icct : 8, - perf_ippr1 : 4, - perf_ippr0 : 4; - } perf_sel_bits; -} io_perf_sel_t; - -#endif - -/* io_perf_cnt is to extract the count from the hub registers. Due to - hardware problems there is only one counter, not two. */ - -#ifdef LITTLE_ENDIAN - -typedef union io_perf_cnt { - uint64_t perf_cnt; - struct { - uint64_t perf_cnt : 20, - perf_rsvd2 : 12, - perf_rsvd1 : 32; - } perf_cnt_bits; - -} io_perf_cnt_t; - -#else - -typedef union io_perf_cnt { - uint64_t perf_cnt; - struct { - uint64_t perf_rsvd1 : 32, - perf_rsvd2 : 12, - perf_cnt : 20; - } perf_cnt_bits; - -} io_perf_cnt_t; - -#endif - -#ifdef LITTLE_ENDIAN - -typedef union iprte_a { - bdrkreg_t entry; - struct { - bdrkreg_t i_rsvd_1 : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_init : 3; - bdrkreg_t i_source : 8; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_widget : 4; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_vld : 1; - } iprte_fields; -} iprte_a_t; - -#else - -typedef union iprte_a { - bdrkreg_t entry; - struct { - bdrkreg_t i_vld : 1; - bdrkreg_t i_to_cnt : 5; - bdrkreg_t i_widget : 4; - bdrkreg_t i_rsvd : 2; - bdrkreg_t i_source : 8; - bdrkreg_t i_init : 3; - bdrkreg_t i_addr : 38; - bdrkreg_t i_rsvd_1 : 3; - } iprte_fields; -} iprte_a_t; - -#endif - -/* PIO MANAGEMENT */ -typedef struct hub_piomap_s *hub_piomap_t; - -extern hub_piomap_t -hub_piomap_alloc(devfs_handle_t dev, /* set up mapping for this device */ - device_desc_t dev_desc, /* device descriptor */ - iopaddr_t xtalk_addr, /* map for this xtalk_addr range */ - size_t byte_count, - size_t byte_count_max, /* maximum size of a mapping */ - unsigned flags); /* defined in sys/pio.h */ - -extern void hub_piomap_free(hub_piomap_t hub_piomap); - -extern caddr_t -hub_piomap_addr(hub_piomap_t hub_piomap, /* mapping resources */ - iopaddr_t xtalk_addr, /* map for this xtalk addr */ - size_t byte_count); /* map this many bytes */ - -extern void -hub_piomap_done(hub_piomap_t hub_piomap); - -extern caddr_t -hub_piotrans_addr( devfs_handle_t dev, /* translate to this device */ - device_desc_t dev_desc, /* device descriptor */ - iopaddr_t xtalk_addr, /* Crosstalk address */ - size_t byte_count, /* map this many bytes */ - unsigned flags); /* (currently unused) */ - -/* DMA MANAGEMENT */ -typedef struct hub_dmamap_s *hub_dmamap_t; - -extern hub_dmamap_t -hub_dmamap_alloc( devfs_handle_t dev, /* set up mappings for dev */ - device_desc_t dev_desc, /* device descriptor */ - size_t byte_count_max, /* max size of a mapping */ - unsigned flags); /* defined in dma.h */ - -extern void -hub_dmamap_free(hub_dmamap_t dmamap); - -extern iopaddr_t -hub_dmamap_addr( hub_dmamap_t dmamap, /* use mapping resources */ - paddr_t paddr, /* map for this address */ - size_t byte_count); /* map this many bytes */ - -extern alenlist_t -hub_dmamap_list( hub_dmamap_t dmamap, /* use mapping resources */ - alenlist_t alenlist, /* map this Addr/Length List */ - unsigned flags); - -extern void -hub_dmamap_done( hub_dmamap_t dmamap); /* done w/ mapping resources */ - -extern iopaddr_t -hub_dmatrans_addr( devfs_handle_t dev, /* translate for this device */ - device_desc_t dev_desc, /* device descriptor */ - paddr_t paddr, /* system physical address */ - size_t byte_count, /* length */ - unsigned flags); /* defined in dma.h */ - -extern alenlist_t -hub_dmatrans_list( devfs_handle_t dev, /* translate for this device */ - device_desc_t dev_desc, /* device descriptor */ - alenlist_t palenlist, /* system addr/length list */ - unsigned flags); /* defined in dma.h */ - -extern void -hub_dmamap_drain( hub_dmamap_t map); - -extern void -hub_dmaaddr_drain( devfs_handle_t vhdl, - paddr_t addr, - size_t bytes); - -extern void -hub_dmalist_drain( devfs_handle_t vhdl, - alenlist_t list); - - -/* INTERRUPT MANAGEMENT */ -typedef struct hub_intr_s *hub_intr_t; - -extern hub_intr_t -hub_intr_alloc( devfs_handle_t dev, /* which device */ - device_desc_t dev_desc, /* device descriptor */ - devfs_handle_t owner_dev); /* owner of this interrupt */ - -extern hub_intr_t -hub_intr_alloc_nothd(devfs_handle_t dev, /* which device */ - device_desc_t dev_desc, /* device descriptor */ - devfs_handle_t owner_dev); /* owner of this interrupt */ - -extern void -hub_intr_free(hub_intr_t intr_hdl); - -extern int -hub_intr_connect( hub_intr_t intr_hdl, /* xtalk intr resource hndl */ - xtalk_intr_setfunc_t setfunc, - /* func to set intr hw */ - void *setfunc_arg); /* arg to setfunc */ - -extern void -hub_intr_disconnect(hub_intr_t intr_hdl); - -extern devfs_handle_t -hub_intr_cpu_get(hub_intr_t intr_hdl); - -/* CONFIGURATION MANAGEMENT */ - -extern void -hub_provider_startup(devfs_handle_t hub); - -extern void -hub_provider_shutdown(devfs_handle_t hub); - -#define HUB_PIO_CONVEYOR 0x1 /* PIO in conveyor belt mode */ -#define HUB_PIO_FIRE_N_FORGET 0x2 /* PIO in fire-and-forget mode */ - -/* Flags that make sense to hub_widget_flags_set */ -#define HUB_WIDGET_FLAGS ( \ - HUB_PIO_CONVEYOR | \ - HUB_PIO_FIRE_N_FORGET \ - ) - - -typedef int hub_widget_flags_t; - -/* Set the PIO mode for a widget. These two functions perform the - * same operation, but hub_device_flags_set() takes a hardware graph - * vertex while hub_widget_flags_set() takes a nasid and widget - * number. In most cases, hub_device_flags_set() should be used. - */ -extern int hub_widget_flags_set(nasid_t nasid, - xwidgetnum_t widget_num, - hub_widget_flags_t flags); - -/* Depending on the flags set take the appropriate actions */ -extern int hub_device_flags_set(devfs_handle_t widget_dev, - hub_widget_flags_t flags); - - -/* Error Handling. */ -extern int hub_ioerror_handler(devfs_handle_t, int, int, struct io_error_s *); -extern int kl_ioerror_handler(cnodeid_t, cnodeid_t, cpuid_t, - int, paddr_t, caddr_t, ioerror_mode_t); -extern void hub_widget_reset(devfs_handle_t, xwidgetnum_t); -extern int hub_error_devenable(devfs_handle_t, int, int); -extern void hub_widgetdev_enable(devfs_handle_t, int); -extern void hub_widgetdev_shutdown(devfs_handle_t, int); -extern int hub_dma_enabled(devfs_handle_t); - -#endif /* __ASSEMBLY__ */ -#endif /* _KERNEL */ -#endif /* _ASM_IA64_SN_SN1_HUBIO_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hublb.h b/include/asm-ia64/sn/sn1/hublb.h deleted file mode 100644 index 60082cafac5dd..0000000000000 --- a/include/asm-ia64/sn/sn1/hublb.h +++ /dev/null @@ -1,1607 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ - -/************************************************************************ - * * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * - * * - * This file is created by an automated script. Any (minimal) changes * - * made manually to this file should be made with care. * - * * - * MAKE ALL ADDITIONS TO THE END OF THIS FILE * - * * - ************************************************************************/ - - -#ifndef _ASM_IA64_SN_SN1_HUBLB_H -#define _ASM_IA64_SN_SN1_HUBLB_H - - -#define LB_REV_ID 0x00600000 /* - * Bedrock Revision - * and ID - */ - - - -#define LB_CPU_PERMISSION 0x00604000 /* - * CPU PIO access - * permission bits - */ - - - -#define LB_CPU_PERM_OVRRD 0x00604008 /* - * CPU PIO access - * permission bit - * override - */ - - - -#define LB_IO_PERMISSION 0x00604010 /* - * IO PIO access - * permission bits - */ - - - -#define LB_SOFT_RESET 0x00604018 /* - * Soft reset the - * Bedrock chip - */ - - - -#define LB_REGION_PRESENT 0x00604020 /* - * Regions Present for - * Invalidates - */ - - - -#define LB_NODES_ABSENT 0x00604028 /* - * Nodes Absent for - * Invalidates - */ - - - -#define LB_MICROLAN_CTL 0x00604030 /* - * Microlan Control - * (NIC) - */ - - - -#define LB_ERROR_BITS 0x00604040 /* - * Local Block error - * bits - */ - - - -#define LB_ERROR_MASK_CLR 0x00604048 /* - * Bit mask write to - * clear error bits - */ - - - -#define LB_ERROR_HDR1 0x00604050 /* - * Source, Suppl and - * Cmd fields - */ - - - -#define LB_ERROR_HDR2 0x00604058 /* - * Address field from - * first error - */ - - - -#define LB_ERROR_DATA 0x00604060 /* - * Data flit (if any) - * from first error - */ - - - -#define LB_DEBUG_SELECT 0x00604100 /* - * Choice of debug - * signals from chip - */ - - - -#define LB_DEBUG_PINS 0x00604108 /* - * Value on the chip's - * debug pins - */ - - - -#define LB_RT_LOCAL_CTRL 0x00604200 /* - * Local generation of - * real-time clock - */ - - - -#define LB_RT_FILTER_CTRL 0x00604208 /* - * Control of - * filtering of global - * clock - */ - - - -#define LB_SCRATCH_REG0 0x00608000 /* Scratch Register 0 */ - - - -#define LB_SCRATCH_REG1 0x00608008 /* Scratch Register 1 */ - - - -#define LB_SCRATCH_REG2 0x00608010 /* Scratch Register 2 */ - - - -#define LB_SCRATCH_REG3 0x00608018 /* Scratch Register 3 */ - - - -#define LB_SCRATCH_REG4 0x00608020 /* Scratch Register 4 */ - - - -#define LB_SCRATCH_REG0_WZ 0x00608040 /* - * Scratch Register 0 - * (WZ alias) - */ - - - -#define LB_SCRATCH_REG1_WZ 0x00608048 /* - * Scratch Register 1 - * (WZ alias) - */ - - - -#define LB_SCRATCH_REG2_WZ 0x00608050 /* - * Scratch Register 2 - * (WZ alias) - */ - - - -#define LB_SCRATCH_REG3_RZ 0x00608058 /* - * Scratch Register 3 - * (RZ alias) - */ - - - -#define LB_SCRATCH_REG4_RZ 0x00608060 /* - * Scratch Register 4 - * (RZ alias) - */ - - - -#define LB_VECTOR_PARMS 0x0060C000 /* - * Vector PIO - * parameters - */ - - - -#define LB_VECTOR_ROUTE 0x0060C008 /* - * Vector PIO Vector - * Route - */ - - - -#define LB_VECTOR_DATA 0x0060C010 /* - * Vector PIO Write - * Data - */ - - - -#define LB_VECTOR_STATUS 0x0060C020 /* - * Vector PIO Return - * Status - */ - - - -#define LB_VECTOR_RETURN 0x0060C028 /* - * Vector PIO Return - * Route - */ - - - -#define LB_VECTOR_READ_DATA 0x0060C030 /* - * Vector PIO Read - * Data - */ - - - -#define LB_VECTOR_STATUS_CLEAR 0x0060C038 /* - * Clear Vector PIO - * Return Status - */ - - - - - -#ifndef __ASSEMBLY__ - -/************************************************************************ - * * - * Description: This register contains information that allows * - * exploratory software to probe for chip type. This is also the * - * register that sets this node's ID and the size of each region * - * (which affects the maximum possible system size). IBM assigns the * - * values for the REVISION, PART_NUMBER and MANUFACTURER fields, in * - * accordance with the IEEE 1149.1 standard; SGI is not at liberty to * - * unilaterally change the values of these fields. * - * . * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_rev_id_u { - bdrkreg_t lb_rev_id_regval; - struct { - bdrkreg_t ri_reserved_2 : 1; - bdrkreg_t ri_manufacturer : 11; - bdrkreg_t ri_part_number : 16; - bdrkreg_t ri_revision : 4; - bdrkreg_t ri_node_id : 8; - bdrkreg_t ri_reserved_1 : 6; - bdrkreg_t ri_region_size : 2; - bdrkreg_t ri_reserved : 16; - } lb_rev_id_fld_s; -} lb_rev_id_u_t; - -#else - -typedef union lb_rev_id_u { - bdrkreg_t lb_rev_id_regval; - struct { - bdrkreg_t ri_reserved : 16; - bdrkreg_t ri_region_size : 2; - bdrkreg_t ri_reserved_1 : 6; - bdrkreg_t ri_node_id : 8; - bdrkreg_t ri_revision : 4; - bdrkreg_t ri_part_number : 16; - bdrkreg_t ri_manufacturer : 11; - bdrkreg_t ri_reserved_2 : 1; - } lb_rev_id_fld_s; -} lb_rev_id_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the PI-access-rights bit-vector for the * - * LB, NI, XB and MD portions of the Bedrock local register space. If * - * a bit in the bit-vector is set, the region corresponding to that * - * bit has read/write permission on the LB, NI, XB and MD local * - * registers. If the bit is clear, that region has no write access to * - * the local registers and no read access if the read will cause any * - * state change. If a write or a read with side effects is attempted * - * by a PI in a region for which access is restricted, the LB will * - * not perform the operation and will send back a reply which * - * indicates an error. * - * * - ************************************************************************/ - - - - -typedef union lb_cpu_permission_u { - bdrkreg_t lb_cpu_permission_regval; - struct { - bdrkreg_t cp_cpu_access : 64; - } lb_cpu_permission_fld_s; -} lb_cpu_permission_u_t; - - - - -/************************************************************************ - * * - * A write to this register of the 64-bit value "SGIrules" will * - * cause the bit in the LB_CPU_PROTECT register corresponding to the * - * region of the requester to be set. * - * * - ************************************************************************/ - - - - -typedef union lb_cpu_perm_ovrrd_u { - bdrkreg_t lb_cpu_perm_ovrrd_regval; - struct { - bdrkreg_t cpo_cpu_perm_ovr : 64; - } lb_cpu_perm_ovrrd_fld_s; -} lb_cpu_perm_ovrrd_u_t; - - - - -/************************************************************************ - * * - * This register contains the II-access-rights bit-vector for the * - * LB, NI, XB and MD portions of the Bedrock local register space. If * - * a bit in the bit-vector is set, the region corresponding to that * - * bit has read/write permission on the LB, NI, XB and MD local * - * registers. If the bit is clear, then that region has no write * - * access to the local registers and no read access if the read * - * results in any state change. If a write or a read with side * - * effects is attempted by an II in a region for which access is * - * restricted, the LB will not perform the operation and will send * - * back a reply which indicates an error. * - * * - ************************************************************************/ - - - - -typedef union lb_io_permission_u { - bdrkreg_t lb_io_permission_regval; - struct { - bdrkreg_t ip_io_permission : 64; - } lb_io_permission_fld_s; -} lb_io_permission_u_t; - - - - -/************************************************************************ - * * - * A write to this bit resets the Bedrock chip with a soft reset. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_soft_reset_u { - bdrkreg_t lb_soft_reset_regval; - struct { - bdrkreg_t sr_soft_reset : 1; - bdrkreg_t sr_reserved : 63; - } lb_soft_reset_fld_s; -} lb_soft_reset_u_t; - -#else - -typedef union lb_soft_reset_u { - bdrkreg_t lb_soft_reset_regval; - struct { - bdrkreg_t sr_reserved : 63; - bdrkreg_t sr_soft_reset : 1; - } lb_soft_reset_fld_s; -} lb_soft_reset_u_t; - -#endif - - - -/************************************************************************ - * * - * This register indicates which regions are present and capable of * - * receiving an invalidate (INVAL) request. The LB samples this * - * register at the start of processing each LINVAL. When an LINVAL * - * indicates that a particular PI unit might hold a shared copy of a * - * cache block but this PI is in a region which is not present (i.e., * - * its bit in LB_REGION_PRESENT is clear), then the LB sends an IVACK * - * reply packet on behalf of this PI. The REGION_SIZE field in the * - * LB_REV_ID register determines the number of nodes per region (and * - * hence, the number of PI units which share a common bit in the * - * LB_REGION_PRESENT register). * - * * - ************************************************************************/ - - - - -typedef union lb_region_present_u { - bdrkreg_t lb_region_present_regval; - struct { - bdrkreg_t rp_present_bits : 64; - } lb_region_present_fld_s; -} lb_region_present_u_t; - - - - -/************************************************************************ - * * - * Description: This register indicates which nodes are absent and * - * not capable of receiving an invalidate (INVAL) request. The LB * - * samples this register at the start of processing each LINVAL. When * - * an LINVAL indicates that a particular PI unit might hold a shared * - * copy of a cache block but this PI unit's node is not present * - * (i.e., its node ID is listed in the LB_NODES_ABSENT register), * - * then the LB sends an IVACK reply packet on behalf of this PI. * - * * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_nodes_absent_u { - bdrkreg_t lb_nodes_absent_regval; - struct { - bdrkreg_t na_node_0 : 8; - bdrkreg_t na_reserved_3 : 7; - bdrkreg_t na_node_0_valid : 1; - bdrkreg_t na_node_1 : 8; - bdrkreg_t na_reserved_2 : 7; - bdrkreg_t na_node_1_valid : 1; - bdrkreg_t na_node_2 : 8; - bdrkreg_t na_reserved_1 : 7; - bdrkreg_t na_node_2_valid : 1; - bdrkreg_t na_node_3 : 8; - bdrkreg_t na_reserved : 7; - bdrkreg_t na_node_3_valid : 1; - } lb_nodes_absent_fld_s; -} lb_nodes_absent_u_t; - -#else - -typedef union lb_nodes_absent_u { - bdrkreg_t lb_nodes_absent_regval; - struct { - bdrkreg_t na_node_3_valid : 1; - bdrkreg_t na_reserved : 7; - bdrkreg_t na_node_3 : 8; - bdrkreg_t na_node_2_valid : 1; - bdrkreg_t na_reserved_1 : 7; - bdrkreg_t na_node_2 : 8; - bdrkreg_t na_node_1_valid : 1; - bdrkreg_t na_reserved_2 : 7; - bdrkreg_t na_node_1 : 8; - bdrkreg_t na_node_0_valid : 1; - bdrkreg_t na_reserved_3 : 7; - bdrkreg_t na_node_0 : 8; - } lb_nodes_absent_fld_s; -} lb_nodes_absent_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register provides access to the Number-In-a-Can add-only * - * serial PROM that is used to store node board serial number and * - * configuration information. (Refer to NIC datasheet Dallas 1990A * - * that is viewable at * - * URL::http://www.dalsemi.com/DocControl/PDFs/pdfindex.html). Data * - * comes from this interface LSB first. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_microlan_ctl_u { - bdrkreg_t lb_microlan_ctl_regval; - struct { - bdrkreg_t mc_rd_data : 1; - bdrkreg_t mc_done : 1; - bdrkreg_t mc_sample : 8; - bdrkreg_t mc_pulse : 10; - bdrkreg_t mc_clkdiv_phi0 : 7; - bdrkreg_t mc_clkdiv_phi1 : 7; - bdrkreg_t mc_reserved : 30; - } lb_microlan_ctl_fld_s; -} lb_microlan_ctl_u_t; - -#else - -typedef union lb_microlan_ctl_u { - bdrkreg_t lb_microlan_ctl_regval; - struct { - bdrkreg_t mc_reserved : 30; - bdrkreg_t mc_clkdiv_phi1 : 7; - bdrkreg_t mc_clkdiv_phi0 : 7; - bdrkreg_t mc_pulse : 10; - bdrkreg_t mc_sample : 8; - bdrkreg_t mc_done : 1; - bdrkreg_t mc_rd_data : 1; - } lb_microlan_ctl_fld_s; -} lb_microlan_ctl_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This register contains the LB error status bits. * - * Whenever a particular type of error occurs, the LB sets its bit in * - * this register so that software will be aware that such an event * - * has happened. Reads from this register are non-destructive and the * - * contents of this register remain intact across reset operations. * - * Whenever any of these bits is set, the LB will assert its * - * interrupt request output signals that go to the PI units. * - * Software can simulate the occurrence of an error by first writing * - * appropriate values into the LB_ERROR_HDR1, LB_ERROR_HDR2 and * - * LB_ERROR_DATA registers, and then writing to the LB_ERROR_BITS * - * register to set the error bits in a particular way. Setting one or * - * more error bits will cause the LB to interrupt a processor and * - * invoke error-handling software. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_error_bits_u { - bdrkreg_t lb_error_bits_regval; - struct { - bdrkreg_t eb_rq_bad_cmd : 1; - bdrkreg_t eb_rp_bad_cmd : 1; - bdrkreg_t eb_rq_short : 1; - bdrkreg_t eb_rp_short : 1; - bdrkreg_t eb_rq_long : 1; - bdrkreg_t eb_rp_long : 1; - bdrkreg_t eb_rq_bad_data : 1; - bdrkreg_t eb_rp_bad_data : 1; - bdrkreg_t eb_rq_bad_addr : 1; - bdrkreg_t eb_rq_bad_linval : 1; - bdrkreg_t eb_gclk_drop : 1; - bdrkreg_t eb_reserved : 53; - } lb_error_bits_fld_s; -} lb_error_bits_u_t; - -#else - -typedef union lb_error_bits_u { - bdrkreg_t lb_error_bits_regval; - struct { - bdrkreg_t eb_reserved : 53; - bdrkreg_t eb_gclk_drop : 1; - bdrkreg_t eb_rq_bad_linval : 1; - bdrkreg_t eb_rq_bad_addr : 1; - bdrkreg_t eb_rp_bad_data : 1; - bdrkreg_t eb_rq_bad_data : 1; - bdrkreg_t eb_rp_long : 1; - bdrkreg_t eb_rq_long : 1; - bdrkreg_t eb_rp_short : 1; - bdrkreg_t eb_rq_short : 1; - bdrkreg_t eb_rp_bad_cmd : 1; - bdrkreg_t eb_rq_bad_cmd : 1; - } lb_error_bits_fld_s; -} lb_error_bits_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register lets software clear some of the bits in the * - * LB_ERROR_BITS register without affecting other bits. Essentially, * - * it provides bit mask functionality. When software writes to the * - * LB_ERROR_MASK_CLR register, the bits which are set in the data * - * value indicate which bits are to be cleared in LB_ERROR_BITS. If a * - * bit is clear in the data value written to the LB_ERROR_MASK_CLR * - * register, then its corresponding bit in the LB_ERROR_BITS register * - * is not affected. Hence, software can atomically clear any subset * - * of the error bits in the LB_ERROR_BITS register. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_error_mask_clr_u { - bdrkreg_t lb_error_mask_clr_regval; - struct { - bdrkreg_t emc_clr_rq_bad_cmd : 1; - bdrkreg_t emc_clr_rp_bad_cmd : 1; - bdrkreg_t emc_clr_rq_short : 1; - bdrkreg_t emc_clr_rp_short : 1; - bdrkreg_t emc_clr_rq_long : 1; - bdrkreg_t emc_clr_rp_long : 1; - bdrkreg_t emc_clr_rq_bad_data : 1; - bdrkreg_t emc_clr_rp_bad_data : 1; - bdrkreg_t emc_clr_rq_bad_addr : 1; - bdrkreg_t emc_clr_rq_bad_linval : 1; - bdrkreg_t emc_clr_gclk_drop : 1; - bdrkreg_t emc_reserved : 53; - } lb_error_mask_clr_fld_s; -} lb_error_mask_clr_u_t; - -#else - -typedef union lb_error_mask_clr_u { - bdrkreg_t lb_error_mask_clr_regval; - struct { - bdrkreg_t emc_reserved : 53; - bdrkreg_t emc_clr_gclk_drop : 1; - bdrkreg_t emc_clr_rq_bad_linval : 1; - bdrkreg_t emc_clr_rq_bad_addr : 1; - bdrkreg_t emc_clr_rp_bad_data : 1; - bdrkreg_t emc_clr_rq_bad_data : 1; - bdrkreg_t emc_clr_rp_long : 1; - bdrkreg_t emc_clr_rq_long : 1; - bdrkreg_t emc_clr_rp_short : 1; - bdrkreg_t emc_clr_rq_short : 1; - bdrkreg_t emc_clr_rp_bad_cmd : 1; - bdrkreg_t emc_clr_rq_bad_cmd : 1; - } lb_error_mask_clr_fld_s; -} lb_error_mask_clr_u_t; - -#endif - - - - -/************************************************************************ - * * - * If the LB detects an error when VALID==0 in the LB_ERROR_HDR1 * - * register, then it saves the contents of the offending packet's * - * header flit in the LB_ERROR_HDR1 and LB_ERROR_HDR2 registers, sets * - * the VALID bit in LB_ERROR_HDR1 and clears the OVERRUN bit in * - * LB_ERROR_HDR1 (and it will also set the corresponding bit in the * - * LB_ERROR_BITS register). The ERR_TYPE field indicates specifically * - * what kind of error occurred. Its encoding corresponds to the bit * - * positions in the LB_ERROR_BITS register (e.g., ERR_TYPE==5 * - * indicates a RP_LONG error). If an error (of any type except * - * GCLK_DROP) subsequently happens while VALID==1, then the LB sets * - * the OVERRUN bit in LB_ERROR_HDR1. This register is not relevant * - * when a GCLK_DROP error occurs; the LB does not even attempt to * - * change the ERR_TYPE, VALID or OVERRUN field when a GCLK_DROP error * - * happens. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_error_hdr1_u { - bdrkreg_t lb_error_hdr1_regval; - struct { - bdrkreg_t eh_command : 7; - bdrkreg_t eh_reserved_5 : 1; - bdrkreg_t eh_suppl : 11; - bdrkreg_t eh_reserved_4 : 1; - bdrkreg_t eh_source : 11; - bdrkreg_t eh_reserved_3 : 1; - bdrkreg_t eh_err_type : 4; - bdrkreg_t eh_reserved_2 : 4; - bdrkreg_t eh_overrun : 1; - bdrkreg_t eh_reserved_1 : 3; - bdrkreg_t eh_valid : 1; - bdrkreg_t eh_reserved : 19; - } lb_error_hdr1_fld_s; -} lb_error_hdr1_u_t; - -#else - -typedef union lb_error_hdr1_u { - bdrkreg_t lb_error_hdr1_regval; - struct { - bdrkreg_t eh_reserved : 19; - bdrkreg_t eh_valid : 1; - bdrkreg_t eh_reserved_1 : 3; - bdrkreg_t eh_overrun : 1; - bdrkreg_t eh_reserved_2 : 4; - bdrkreg_t eh_err_type : 4; - bdrkreg_t eh_reserved_3 : 1; - bdrkreg_t eh_source : 11; - bdrkreg_t eh_reserved_4 : 1; - bdrkreg_t eh_suppl : 11; - bdrkreg_t eh_reserved_5 : 1; - bdrkreg_t eh_command : 7; - } lb_error_hdr1_fld_s; -} lb_error_hdr1_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contents of the Address field from header flit of first packet * - * that causes an error. This register is not relevant when a * - * GCLK_DROP error occurs. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_error_hdr2_u { - bdrkreg_t lb_error_hdr2_regval; - struct { - bdrkreg_t eh_address : 38; - bdrkreg_t eh_reserved : 26; - } lb_error_hdr2_fld_s; -} lb_error_hdr2_u_t; - -#else - -typedef union lb_error_hdr2_u { - bdrkreg_t lb_error_hdr2_regval; - struct { - bdrkreg_t eh_reserved : 26; - bdrkreg_t eh_address : 38; - } lb_error_hdr2_fld_s; -} lb_error_hdr2_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This register accompanies the LB_ERROR_HDR1 and * - * LB_ERROR_HDR2 registers. The LB updates the value in this * - * register when an incoming packet with a data flit causes an error * - * while VALID==0 in the LB_ERROR_HDR1 register. This register * - * retains the contents of the data flit from the incoming packet * - * that caused the error. This register is relevant for the following * - * types of errors: * - * <UL > * - * <UL > * - * <UL > * - * <UL > * - * <UL > * - * <LI >RQ_BAD_LINVAL for a LINVAL request. * - * <LI >RQ_BAD_ADDR for a normal or vector PIO request. * - * <LI >RP_BAD_DATA for a vector PIO reply. * - * <LI >RQ_BAD DATA for an incoming request with data. * - * <LI >RP_LONG for a vector PIO reply. * - * <LI >RQ_LONG for an incoming request with expected data. * - * <BLOCKQUOTE > * - * In the case of RQ_BAD_LINVAL, the register retains the 64-bit data * - * value that followed the header flit. In the case of RQ_BAD_ADDR * - * or RQ_BAD_DATA, the register retains the incoming packet's 64-bit * - * data value (i.e., 2nd flit in the packet for a normal PIO write or * - * an LINVAL, 3rd flit for a vector PIO read or write). In the case * - * of RP_BAD_DATA, the register retains the 64-bit data value in the * - * 3rd flit of the packet. When a RP_LONG or RQ_LONG error occurs, * - * the LB loads the LB_ERROR_DATA register with the contents of the * - * expected data flit (i.e., the 3rd flit in the packet for a vector * - * PIO request or reply, the 2nd flit for other packets), if any. The * - * contents of the LB_ERROR_DATA register are undefined after a * - * RP_SHORT, RQ_SHORT, RP_BAD_CMD or RQ_BAD_CMD error. The contents * - * of the LB_ERROR_DATA register are also undefined after an incoming * - * normal PIO read request which encounters a RQ_LONG error. * - * * - ************************************************************************/ - - - - -typedef union lb_error_data_u { - bdrkreg_t lb_error_data_regval; - struct { - bdrkreg_t ed_data : 64; - } lb_error_data_fld_s; -} lb_error_data_u_t; - - - - -/************************************************************************ - * * - * This register enables software to control what internal Bedrock * - * signals are visible on the chip's debug pins. The LB provides the * - * 6-bit value in this register to Bedrock's DEBUG unit. The JTAG * - * unit provides a similar 6-bit selection input to the DEBUG unit, * - * along with another signal that tells the DEBUG unit whether to use * - * the selection signal from the LB or the JTAG unit. For a * - * description of the menu of choices for debug signals, refer to the * - * documentation for the DEBUG unit. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_debug_select_u { - bdrkreg_t lb_debug_select_regval; - struct { - bdrkreg_t ds_debug_sel : 6; - bdrkreg_t ds_reserved : 58; - } lb_debug_select_fld_s; -} lb_debug_select_u_t; - -#else - -typedef union lb_debug_select_u { - bdrkreg_t lb_debug_select_regval; - struct { - bdrkreg_t ds_reserved : 58; - bdrkreg_t ds_debug_sel : 6; - } lb_debug_select_fld_s; -} lb_debug_select_u_t; - -#endif - - - - -/************************************************************************ - * * - * A PIO read from this register returns the 32-bit value that is * - * currently on the Bedrock chip's debug pins. This register allows * - * software to observe debug pin output values which do not change * - * frequently (i.e., they remain constant over a period of many * - * cycles). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_debug_pins_u { - bdrkreg_t lb_debug_pins_regval; - struct { - bdrkreg_t dp_debug_pins : 32; - bdrkreg_t dp_reserved : 32; - } lb_debug_pins_fld_s; -} lb_debug_pins_u_t; - -#else - -typedef union lb_debug_pins_u { - bdrkreg_t lb_debug_pins_regval; - struct { - bdrkreg_t dp_reserved : 32; - bdrkreg_t dp_debug_pins : 32; - } lb_debug_pins_fld_s; -} lb_debug_pins_u_t; - -#endif - - - - -/************************************************************************ - * * - * The LB unit provides the PI0 and PI1 units with a real-time clock * - * signal. The LB can generate this signal itself, based on the * - * Bedrock chip's system clock which the LB receives as an input. * - * Alternatively, the LB can filter a global clock signal which it * - * receives as an input and provide the filtered version to PI0 and * - * PI1. The user can program the LB_RT_LOCAL_CTRL register to choose * - * the source of the real-time clock. If the user chooses to generate * - * the real-time clock internally within the LB, then the user can * - * specify the period for the real-time clock signal. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_rt_local_ctrl_u { - bdrkreg_t lb_rt_local_ctrl_regval; - struct { - bdrkreg_t rlc_gclk_enable : 1; - bdrkreg_t rlc_reserved_4 : 3; - bdrkreg_t rlc_max_count : 10; - bdrkreg_t rlc_reserved_3 : 2; - bdrkreg_t rlc_gclk_counter : 10; - bdrkreg_t rlc_reserved_2 : 2; - bdrkreg_t rlc_gclk : 1; - bdrkreg_t rlc_reserved_1 : 3; - bdrkreg_t rlc_use_internal : 1; - bdrkreg_t rlc_reserved : 31; - } lb_rt_local_ctrl_fld_s; -} lb_rt_local_ctrl_u_t; - -#else - -typedef union lb_rt_local_ctrl_u { - bdrkreg_t lb_rt_local_ctrl_regval; - struct { - bdrkreg_t rlc_reserved : 31; - bdrkreg_t rlc_use_internal : 1; - bdrkreg_t rlc_reserved_1 : 3; - bdrkreg_t rlc_gclk : 1; - bdrkreg_t rlc_reserved_2 : 2; - bdrkreg_t rlc_gclk_counter : 10; - bdrkreg_t rlc_reserved_3 : 2; - bdrkreg_t rlc_max_count : 10; - bdrkreg_t rlc_reserved_4 : 3; - bdrkreg_t rlc_gclk_enable : 1; - } lb_rt_local_ctrl_fld_s; -} lb_rt_local_ctrl_u_t; - -#endif - - - - -/************************************************************************ - * * - * When the value of the USE_INTERNAL field in the LB_RT_LOCAL_CTRL * - * register is 0, the LB filters an incoming global clock signal and * - * provides the result to PI0 and PI1 for their real-time clock * - * inputs. The LB can perform either simple filtering or complex * - * filtering, depending on the value of the MASK_ENABLE bit. For the * - * simple filtering option, the LB merely removes glitches from the * - * incoming global clock; if the global clock goes high (or low) for * - * only a single cycle, the LB considers it to be a glitch and does * - * not pass it through to PI0 and PI1. For the complex filtering * - * option, the LB expects positive edges on the incoming global clock * - * to be spaced at fairly regular intervals and it looks for them at * - * these times; the LB keeps track of unexpected or missing positive * - * edges, and it generates an edge itself whenever the incoming * - * global clock apparently misses an edge. For each filtering option, * - * the real-time clock which the LB provides to PI0 and PI1 is not * - * necessarily a square wave; when a positive edge happens, the * - * real-time clock stays high for (2*MAX_COUNT+1-OFFSET)/2 cycles of * - * the LB's system clock, and then is low until the next positive * - * edge. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_rt_filter_ctrl_u { - bdrkreg_t lb_rt_filter_ctrl_regval; - struct { - bdrkreg_t rfc_offset : 5; - bdrkreg_t rfc_reserved_4 : 3; - bdrkreg_t rfc_mask_counter : 12; - bdrkreg_t rfc_mask_enable : 1; - bdrkreg_t rfc_reserved_3 : 3; - bdrkreg_t rfc_dropout_counter : 10; - bdrkreg_t rfc_reserved_2 : 2; - bdrkreg_t rfc_dropout_thresh : 10; - bdrkreg_t rfc_reserved_1 : 2; - bdrkreg_t rfc_error_counter : 10; - bdrkreg_t rfc_reserved : 6; - } lb_rt_filter_ctrl_fld_s; -} lb_rt_filter_ctrl_u_t; - -#else - -typedef union lb_rt_filter_ctrl_u { - bdrkreg_t lb_rt_filter_ctrl_regval; - struct { - bdrkreg_t rfc_reserved : 6; - bdrkreg_t rfc_error_counter : 10; - bdrkreg_t rfc_reserved_1 : 2; - bdrkreg_t rfc_dropout_thresh : 10; - bdrkreg_t rfc_reserved_2 : 2; - bdrkreg_t rfc_dropout_counter : 10; - bdrkreg_t rfc_reserved_3 : 3; - bdrkreg_t rfc_mask_enable : 1; - bdrkreg_t rfc_mask_counter : 12; - bdrkreg_t rfc_reserved_4 : 3; - bdrkreg_t rfc_offset : 5; - } lb_rt_filter_ctrl_fld_s; -} lb_rt_filter_ctrl_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is a scratch register that is reset to 0x0. At the * - * normal address, the register is a simple storage location. At the * - * Write-If-Zero address, the register accepts a new value from a * - * write operation only if the current value is zero. * - * * - ************************************************************************/ - - - - -typedef union lb_scratch_reg0_u { - bdrkreg_t lb_scratch_reg0_regval; - struct { - bdrkreg_t sr_scratch_bits : 64; - } lb_scratch_reg0_fld_s; -} lb_scratch_reg0_u_t; - - - - -/************************************************************************ - * * - * These registers are scratch registers that are not reset. At a * - * register's normal address, it is a simple storage location. At a * - * register's Write-If-Zero address, it accepts a new value from a * - * write operation only if the current value is zero. * - * * - ************************************************************************/ - - - - -typedef union lb_scratch_reg1_u { - bdrkreg_t lb_scratch_reg1_regval; - struct { - bdrkreg_t sr_scratch_bits : 64; - } lb_scratch_reg1_fld_s; -} lb_scratch_reg1_u_t; - - - - -/************************************************************************ - * * - * These registers are scratch registers that are not reset. At a * - * register's normal address, it is a simple storage location. At a * - * register's Write-If-Zero address, it accepts a new value from a * - * write operation only if the current value is zero. * - * * - ************************************************************************/ - - - - -typedef union lb_scratch_reg2_u { - bdrkreg_t lb_scratch_reg2_regval; - struct { - bdrkreg_t sr_scratch_bits : 64; - } lb_scratch_reg2_fld_s; -} lb_scratch_reg2_u_t; - - - - -/************************************************************************ - * * - * These one-bit registers are scratch registers. At a register's * - * normal address, it is a simple storage location. At a register's * - * Read-Set-If-Zero address, it returns the original contents and * - * sets the bit if the original value is zero. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_scratch_reg3_u { - bdrkreg_t lb_scratch_reg3_regval; - struct { - bdrkreg_t sr_scratch_bit : 1; - bdrkreg_t sr_reserved : 63; - } lb_scratch_reg3_fld_s; -} lb_scratch_reg3_u_t; - -#else - -typedef union lb_scratch_reg3_u { - bdrkreg_t lb_scratch_reg3_regval; - struct { - bdrkreg_t sr_reserved : 63; - bdrkreg_t sr_scratch_bit : 1; - } lb_scratch_reg3_fld_s; -} lb_scratch_reg3_u_t; - -#endif - - - - -/************************************************************************ - * * - * These one-bit registers are scratch registers. At a register's * - * normal address, it is a simple storage location. At a register's * - * Read-Set-If-Zero address, it returns the original contents and * - * sets the bit if the original value is zero. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_scratch_reg4_u { - bdrkreg_t lb_scratch_reg4_regval; - struct { - bdrkreg_t sr_scratch_bit : 1; - bdrkreg_t sr_reserved : 63; - } lb_scratch_reg4_fld_s; -} lb_scratch_reg4_u_t; - -#else - -typedef union lb_scratch_reg4_u { - bdrkreg_t lb_scratch_reg4_regval; - struct { - bdrkreg_t sr_reserved : 63; - bdrkreg_t sr_scratch_bit : 1; - } lb_scratch_reg4_fld_s; -} lb_scratch_reg4_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is a scratch register that is reset to 0x0. At the * - * normal address, the register is a simple storage location. At the * - * Write-If-Zero address, the register accepts a new value from a * - * write operation only if the current value is zero. * - * * - ************************************************************************/ - - - - -typedef union lb_scratch_reg0_wz_u { - bdrkreg_t lb_scratch_reg0_wz_regval; - struct { - bdrkreg_t srw_scratch_bits : 64; - } lb_scratch_reg0_wz_fld_s; -} lb_scratch_reg0_wz_u_t; - - - - -/************************************************************************ - * * - * These registers are scratch registers that are not reset. At a * - * register's normal address, it is a simple storage location. At a * - * register's Write-If-Zero address, it accepts a new value from a * - * write operation only if the current value is zero. * - * * - ************************************************************************/ - - - - -typedef union lb_scratch_reg1_wz_u { - bdrkreg_t lb_scratch_reg1_wz_regval; - struct { - bdrkreg_t srw_scratch_bits : 64; - } lb_scratch_reg1_wz_fld_s; -} lb_scratch_reg1_wz_u_t; - - - - -/************************************************************************ - * * - * These registers are scratch registers that are not reset. At a * - * register's normal address, it is a simple storage location. At a * - * register's Write-If-Zero address, it accepts a new value from a * - * write operation only if the current value is zero. * - * * - ************************************************************************/ - - - - -typedef union lb_scratch_reg2_wz_u { - bdrkreg_t lb_scratch_reg2_wz_regval; - struct { - bdrkreg_t srw_scratch_bits : 64; - } lb_scratch_reg2_wz_fld_s; -} lb_scratch_reg2_wz_u_t; - - - - -/************************************************************************ - * * - * These one-bit registers are scratch registers. At a register's * - * normal address, it is a simple storage location. At a register's * - * Read-Set-If-Zero address, it returns the original contents and * - * sets the bit if the original value is zero. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_scratch_reg3_rz_u { - bdrkreg_t lb_scratch_reg3_rz_regval; - struct { - bdrkreg_t srr_scratch_bit : 1; - bdrkreg_t srr_reserved : 63; - } lb_scratch_reg3_rz_fld_s; -} lb_scratch_reg3_rz_u_t; - -#else - -typedef union lb_scratch_reg3_rz_u { - bdrkreg_t lb_scratch_reg3_rz_regval; - struct { - bdrkreg_t srr_reserved : 63; - bdrkreg_t srr_scratch_bit : 1; - } lb_scratch_reg3_rz_fld_s; -} lb_scratch_reg3_rz_u_t; - -#endif - - - - -/************************************************************************ - * * - * These one-bit registers are scratch registers. At a register's * - * normal address, it is a simple storage location. At a register's * - * Read-Set-If-Zero address, it returns the original contents and * - * sets the bit if the original value is zero. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_scratch_reg4_rz_u { - bdrkreg_t lb_scratch_reg4_rz_regval; - struct { - bdrkreg_t srr_scratch_bit : 1; - bdrkreg_t srr_reserved : 63; - } lb_scratch_reg4_rz_fld_s; -} lb_scratch_reg4_rz_u_t; - -#else - -typedef union lb_scratch_reg4_rz_u { - bdrkreg_t lb_scratch_reg4_rz_regval; - struct { - bdrkreg_t srr_reserved : 63; - bdrkreg_t srr_scratch_bit : 1; - } lb_scratch_reg4_rz_fld_s; -} lb_scratch_reg4_rz_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This register contains vector PIO parameters. A * - * write to this register triggers the LB to send out a vector PIO * - * request packet. Immediately after servicing a write request to the * - * LB_VECTOR_PARMS register, the LB sends back a reply (i.e., the LB * - * doesn't wait for the vector PIO operation to finish first). Three * - * LB registers provide the contents for an outgoing vector PIO * - * request packet. Software should wait until the BUSY bit in * - * LB_VECTOR_PARMS is clear and then initialize all three of these * - * registers before initiating a vector PIO operation. The three * - * vector PIO registers are: * - * LB_VECTOR_ROUTE * - * LB_VECTOR_DATA * - * LB_VECTOR_PARMS (should be written last) * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_vector_parms_u { - bdrkreg_t lb_vector_parms_regval; - struct { - bdrkreg_t vp_type : 1; - bdrkreg_t vp_reserved_2 : 2; - bdrkreg_t vp_address : 21; - bdrkreg_t vp_reserved_1 : 8; - bdrkreg_t vp_write_id : 8; - bdrkreg_t vp_pio_id : 11; - bdrkreg_t vp_reserved : 12; - bdrkreg_t vp_busy : 1; - } lb_vector_parms_fld_s; -} lb_vector_parms_u_t; - -#else - -typedef union lb_vector_parms_u { - bdrkreg_t lb_vector_parms_regval; - struct { - bdrkreg_t vp_busy : 1; - bdrkreg_t vp_reserved : 12; - bdrkreg_t vp_pio_id : 11; - bdrkreg_t vp_write_id : 8; - bdrkreg_t vp_reserved_1 : 8; - bdrkreg_t vp_address : 21; - bdrkreg_t vp_reserved_2 : 2; - bdrkreg_t vp_type : 1; - } lb_vector_parms_fld_s; -} lb_vector_parms_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the vector PIO route. This is one of the 3 * - * vector PIO control registers. * - * * - ************************************************************************/ - - - - -typedef union lb_vector_route_u { - bdrkreg_t lb_vector_route_regval; - struct { - bdrkreg_t vr_vector : 64; - } lb_vector_route_fld_s; -} lb_vector_route_u_t; - - - - -/************************************************************************ - * * - * This register contains the vector PIO write data. This is one of * - * the 3 vector PIO control registers. The contents of this register * - * also provide the data value to be sent in outgoing vector PIO read * - * requests and vector PIO write replies. * - * * - ************************************************************************/ - - - - -typedef union lb_vector_data_u { - bdrkreg_t lb_vector_data_regval; - struct { - bdrkreg_t vd_write_data : 64; - } lb_vector_data_fld_s; -} lb_vector_data_u_t; - - - - -/************************************************************************ - * * - * Description: This register contains the vector PIO return status. * - * Software should clear this register before launching a vector PIO * - * request from the LB. The LB will not modify this register's value * - * if an incoming reply packet encounters any kind of error. If an * - * incoming reply packet does not encounter an error but the * - * STATUS_VALID bit is already set, then the LB sets the OVERRUN bit * - * and leaves the other fields unchanged. The LB updates the values * - * of the SOURCE, PIO_ID, WRITE_ID, ADDRESS and TYPE fields only if * - * an incoming vector PIO reply packet does not encounter an error * - * and the STATUS_VALID bit is clear; at the same time, the LB sets * - * the STATUS_VALID bit and will also update the LB_VECTOR_RETURN and * - * LB_VECTOR_READ_DATA registers. * - * * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_vector_status_u { - bdrkreg_t lb_vector_status_regval; - struct { - bdrkreg_t vs_type : 3; - bdrkreg_t vs_address : 21; - bdrkreg_t vs_reserved : 8; - bdrkreg_t vs_write_id : 8; - bdrkreg_t vs_pio_id : 11; - bdrkreg_t vs_source : 11; - bdrkreg_t vs_overrun : 1; - bdrkreg_t vs_status_valid : 1; - } lb_vector_status_fld_s; -} lb_vector_status_u_t; - -#else - -typedef union lb_vector_status_u { - bdrkreg_t lb_vector_status_regval; - struct { - bdrkreg_t vs_status_valid : 1; - bdrkreg_t vs_overrun : 1; - bdrkreg_t vs_source : 11; - bdrkreg_t vs_pio_id : 11; - bdrkreg_t vs_write_id : 8; - bdrkreg_t vs_reserved : 8; - bdrkreg_t vs_address : 21; - bdrkreg_t vs_type : 3; - } lb_vector_status_fld_s; -} lb_vector_status_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the return vector PIO route. The LB will * - * not modify this register's value if an incoming reply packet * - * encounters any kind of error. The LB also will not modify this * - * register's value if the STATUS_VALID bit in the LB_VECTOR_STATUS * - * register is set when it receives an incoming vector PIO reply. The * - * LB stores an incoming vector PIO reply packet's vector route flit * - * in this register only if the packet does not encounter an error * - * and the STATUS_VALID bit is clear. * - * * - ************************************************************************/ - - - - -typedef union lb_vector_return_u { - bdrkreg_t lb_vector_return_regval; - struct { - bdrkreg_t vr_return_vector : 64; - } lb_vector_return_fld_s; -} lb_vector_return_u_t; - - - - -/************************************************************************ - * * - * This register contains the vector PIO read data, if any. The LB * - * will not modify this register's value if an incoming reply packet * - * encounters any kind of error. The LB also will not modify this * - * register's value if the STATUS_VALID bit in the LB_VECTOR_STATUS * - * register is set when it receives an incoming vector PIO reply. The * - * LB stores an incoming vector PIO reply packet's data flit in this * - * register only if the packet does not encounter an error and the * - * STATUS_VALID bit is clear. * - * * - ************************************************************************/ - - - - -typedef union lb_vector_read_data_u { - bdrkreg_t lb_vector_read_data_regval; - struct { - bdrkreg_t vrd_read_data : 64; - } lb_vector_read_data_fld_s; -} lb_vector_read_data_u_t; - - - - -/************************************************************************ - * * - * Description: This register contains the vector PIO return status. * - * Software should clear this register before launching a vector PIO * - * request from the LB. The LB will not modify this register's value * - * if an incoming reply packet encounters any kind of error. If an * - * incoming reply packet does not encounter an error but the * - * STATUS_VALID bit is already set, then the LB sets the OVERRUN bit * - * and leaves the other fields unchanged. The LB updates the values * - * of the SOURCE, PIO_ID, WRITE_ID, ADDRESS and TYPE fields only if * - * an incoming vector PIO reply packet does not encounter an error * - * and the STATUS_VALID bit is clear; at the same time, the LB sets * - * the STATUS_VALID bit and will also update the LB_VECTOR_RETURN and * - * LB_VECTOR_READ_DATA registers. * - * * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union lb_vector_status_clear_u { - bdrkreg_t lb_vector_status_clear_regval; - struct { - bdrkreg_t vsc_type : 3; - bdrkreg_t vsc_address : 21; - bdrkreg_t vsc_reserved : 8; - bdrkreg_t vsc_write_id : 8; - bdrkreg_t vsc_pio_id : 11; - bdrkreg_t vsc_source : 11; - bdrkreg_t vsc_overrun : 1; - bdrkreg_t vsc_status_valid : 1; - } lb_vector_status_clear_fld_s; -} lb_vector_status_clear_u_t; - -#else - -typedef union lb_vector_status_clear_u { - bdrkreg_t lb_vector_status_clear_regval; - struct { - bdrkreg_t vsc_status_valid : 1; - bdrkreg_t vsc_overrun : 1; - bdrkreg_t vsc_source : 11; - bdrkreg_t vsc_pio_id : 11; - bdrkreg_t vsc_write_id : 8; - bdrkreg_t vsc_reserved : 8; - bdrkreg_t vsc_address : 21; - bdrkreg_t vsc_type : 3; - } lb_vector_status_clear_fld_s; -} lb_vector_status_clear_u_t; - -#endif - - - - - - -#endif /* __ASSEMBLY__ */ - -/************************************************************************ - * * - * MAKE ALL ADDITIONS AFTER THIS LINE * - * * - ************************************************************************/ - - - - - -#endif /* _ASM_IA64_SN_SN1_HUBLB_H */ diff --git a/include/asm-ia64/sn/sn1/hublb_next.h b/include/asm-ia64/sn/sn1/hublb_next.h deleted file mode 100644 index 5b14992fc6d21..0000000000000 --- a/include/asm-ia64/sn/sn1/hublb_next.h +++ /dev/null @@ -1,109 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_HUBLB_NEXT_H -#define _ASM_IA64_SN_SN1_HUBLB_NEXT_H - -/********************************************************************** - - This contains some mask and shift values for LB defined as required - for compatibility. - - **********************************************************************/ - -#define LRI_SYSTEM_SIZE_SHFT 46 -#define LRI_SYSTEM_SIZE_MASK (UINT64_CAST 0x3 << LRI_SYSTEM_SIZE_SHFT) -#define LRI_NODEID_SHFT 32 -#define LRI_NODEID_MASK (UINT64_CAST 0xff << LRI_NODEID_SHFT)/* Node ID */ -#define LRI_CHIPID_SHFT 12 -#define LRI_CHIPID_MASK (UINT64_CAST 0xffff << LRI_CHIPID_SHFT) /* should be 0x3012 */ -#define LRI_REV_SHFT 28 -#define LRI_REV_MASK (UINT64_CAST 0xf << LRI_REV_SHFT)/* Chip revision */ - -/* Values for LRI_SYSTEM_SIZE */ -#define SYSTEM_SIZE_INVALID 0x3 -#define SYSTEM_SIZE_NMODE 0x2 -#define SYSTEM_SIZE_COARSE 0x1 -#define SYSTEM_SIZE_SMALL 0x0 - -/* In fine mode, each node is a region. In coarse mode, there are - * 2 nodes per region. In N-mode, there are 4 nodes per region. */ -#define NASID_TO_FINEREG_SHFT 0 -#define NASID_TO_COARSEREG_SHFT 1 -#define NASID_TO_NMODEREG_SHFT 2 - -#define LR_LOCALRESET (UINT64_CAST 1) -/* - * LB_VECTOR_PARMS mask and shift definitions. - * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS. - */ - -#define LVP_BUSY (UINT64_CAST 1 << 63) -#define LVP_PIOID_SHFT 40 -#define LVP_PIOID_MASK (UINT64_CAST 0x7ff << 40) -#define LVP_WRITEID_SHFT 32 -#define LVP_WRITEID_MASK (UINT64_CAST 0xff << 32) -#define LVP_ADDRESS_MASK (UINT64_CAST 0xfffff8) /* Bits 23:3 */ -#define LVP_TYPE_SHFT 0 -#define LVP_TYPE_MASK (UINT64_CAST 0x3) - -/* LB_VECTOR_STATUS mask and shift definitions */ - -#define LVS_VALID (UINT64_CAST 1 << 63) -#define LVS_OVERRUN (UINT64_CAST 1 << 62) -#define LVS_TARGET_SHFT 51 -#define LVS_TARGET_MASK (UINT64_CAST 0x7ff << 51) -#define LVS_PIOID_SHFT 40 -#define LVS_PIOID_MASK (UINT64_CAST 0x7ff << 40) -#define LVS_WRITEID_SHFT 32 -#define LVS_WRITEID_MASK (UINT64_CAST 0xff << 32) -#define LVS_ADDRESS_MASK (UINT64_CAST 0xfffff8) /* Bits 23:3 */ -#define LVS_TYPE_SHFT 0 -#define LVS_TYPE_MASK (UINT64_CAST 0x7) -#define LVS_ERROR_MASK (UINT64_CAST 0x4) /* bit set means error */ - -/* LB_RT_LOCAL_CTRL mask and shift definitions */ - -#define LRLC_USE_INT_SHFT 32 -#define LRLC_USE_INT_MASK (UINT64_CAST 1 << 32) -#define LRLC_USE_INT (UINT64_CAST 1 << 32) -#define LRLC_GCLK_SHFT 28 -#define LRLC_GCLK_MASK (UINT64_CAST 1 << 28) -#define LRLC_GCLK (UINT64_CAST 1 << 28) -#define LRLC_GCLK_COUNT_SHFT 16 -#define LRLC_GCLK_COUNT_MASK (UINT64_CAST 0x3ff << 16) -#define LRLC_MAX_COUNT_SHFT 4 -#define LRLC_MAX_COUNT_MASK (UINT64_CAST 0x3ff << 4) -#define LRLC_GCLK_EN_SHFT 0 -#define LRLC_GCLK_EN_MASK (UINT64_CAST 1) -#define LRLC_GCLK_EN (UINT64_CAST 1) - -/* LB_NODES_ABSENT mask and shift definitions */ -#define LNA_VALID_SHFT 15 -#define LNA_VALID_MASK (UINT64_CAST 1 << LNA_VALID_SHFT) -#define LNA_VALID (UINT64_CAST 1 << LNA_VALID_SHFT) -#define LNA_NODE_SHFT 0 -#define LNA_NODE_MASK (UINT64_CAST 0xff << LNA_NODE_SHFT) - -/* LB_NODES_ABSENT has 4 identical sub-registers, on 16-bit boundaries */ -#define LNA_ENTRY_SHFT 16 -#define LNA_MAX_ENTRIES 4 -#define LNA_ADD(_reg, _n) ((_reg) = (_reg) << LNA_ENTRY_SHFT | \ - LNA_VALID | (_n) << LNA_NODE_SHFT) - -#define PIOTYPE_READ 0 /* VECTOR_PARMS and VECTOR_STATUS */ -#define PIOTYPE_WRITE 1 /* VECTOR_PARMS and VECTOR_STATUS */ -#define PIOTYPE_UNDEFINED 2 /* VECTOR_PARMS and VECTOR_STATUS */ -/* XXX IP35 doesn't support vector exchange: scr. regs. do locks directly */ -#define PIOTYPE_EXCHANGE 3 /* VECTOR_PARMS and VECTOR_STATUS */ -#define PIOTYPE_ADDR_ERR 4 /* VECTOR_STATUS only */ -#define PIOTYPE_CMD_ERR 5 /* VECTOR_STATUS only */ -#define PIOTYPE_PROT_ERR 6 /* VECTOR_STATUS only */ -#define PIOTYPE_UNKNOWN 7 /* VECTOR_STATUS only */ - -#endif /* _ASM_IA64_SN_SN1_HUBLB_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hubmd.h b/include/asm-ia64/sn/sn1/hubmd.h deleted file mode 100644 index 09001472d71d4..0000000000000 --- a/include/asm-ia64/sn/sn1/hubmd.h +++ /dev/null @@ -1,2476 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_HUBMD_H -#define _ASM_IA64_SN_SN1_HUBMD_H - - -/************************************************************************ - * * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * - * * - * This file is created by an automated script. Any (minimal) changes * - * made manually to this file should be made with care. * - * * - * MAKE ALL ADDITIONS TO THE END OF THIS FILE * - * * - ************************************************************************/ - - -#define MD_CURRENT_CELL 0x00780000 /* - * BDDIR, LREG, LBOOT, - * RREG, RBOOT - * protection and mask - * for using Local - * Access protection. - */ - - - -#define MD_MEMORY_CONFIG 0x00780008 /* - * Memory/Directory - * DIMM control - */ - - - -#define MD_ARBITRATION_CONTROL 0x00780010 /* - * Arbitration - * Parameters - */ - - - -#define MD_MIG_CONFIG 0x00780018 /* - * Page Migration - * control - */ - - - -#define MD_FANDOP_CAC_STAT0 0x00780020 /* - * Fetch-and-op cache - * 0 status - */ - - - -#define MD_FANDOP_CAC_STAT1 0x00780028 /* - * Fetch-and-op cache - * 1 status - */ - - - -#define MD_MISC0_ERROR 0x00780040 /* - * Miscellaneous MD - * error - */ - - - -#define MD_MISC1_ERROR 0x00780048 /* - * Miscellaneous MD - * error - */ - - - -#define MD_MISC1_ERROR_CLR 0x00780058 /* - * Miscellaneous MD - * error clear - */ - - - -#define MD_OUTGOING_RP_QUEUE_SIZE 0x00780060 /* - * MD outgoing reply - * queues sizing - */ - - - -#define MD_PERF_SEL0 0x00790000 /* - * Selects events - * monitored by - * MD_PERF_CNT0 - */ - - - -#define MD_PERF_SEL1 0x00790008 /* - * Selects events - * monitored by - * MD_PERF_CNT1 - */ - - - -#define MD_PERF_CNT0 0x00790010 /* - * Performance counter - * 0 - */ - - - -#define MD_PERF_CNT1 0x00790018 /* - * Performance counter - * 1 - */ - - - -#define MD_REFRESH_CONTROL 0x007A0000 /* - * Memory/Directory - * refresh control - */ - - - -#define MD_JUNK_BUS_TIMING 0x007A0008 /* Junk Bus Timing */ - - - -#define MD_LED0 0x007A0010 /* Reads of 8-bit LED0 */ - - - -#define MD_LED1 0x007A0018 /* Reads of 8-bit LED1 */ - - - -#define MD_LED2 0x007A0020 /* Reads of 8-bit LED2 */ - - - -#define MD_LED3 0x007A0028 /* Reads of 8-bit LED3 */ - - - -#define MD_BIST_CTL 0x007A0030 /* - * BIST general - * control - */ - - - -#define MD_BIST_DATA 0x007A0038 /* - * BIST initial data - * pattern and - * variation control - */ - - - -#define MD_BIST_AB_ERR_ADDR 0x007A0040 /* BIST error address */ - - - -#define MD_BIST_STATUS 0x007A0048 /* BIST status */ - - - -#define MD_IB_DEBUG 0x007A0060 /* IB debug select */ - - - -#define MD_DIR_CONFIG 0x007C0000 /* - * Directory mode - * control - */ - - - -#define MD_DIR_ERROR 0x007C0010 /* - * Directory DIMM - * error - */ - - - -#define MD_DIR_ERROR_CLR 0x007C0018 /* - * Directory DIMM - * error clear - */ - - - -#define MD_PROTOCOL_ERROR 0x007C0020 /* - * Directory protocol - * error - */ - - - -#define MD_PROTOCOL_ERR_CLR 0x007C0028 /* - * Directory protocol - * error clear - */ - - - -#define MD_MIG_CANDIDATE 0x007C0030 /* - * Page migration - * candidate - */ - - - -#define MD_MIG_CANDIDATE_CLR 0x007C0038 /* - * Page migration - * candidate clear - */ - - - -#define MD_MIG_DIFF_THRESH 0x007C0040 /* - * Page migration - * count difference - * threshold - */ - - - -#define MD_MIG_VALUE_THRESH 0x007C0048 /* - * Page migration - * count absolute - * threshold - */ - - - -#define MD_OUTGOING_RQ_QUEUE_SIZE 0x007C0050 /* - * MD outgoing request - * queues sizing - */ - - - -#define MD_BIST_DB_ERR_DATA 0x007C0058 /* - * BIST directory - * error data - */ - - - -#define MD_DB_DEBUG 0x007C0060 /* DB debug select */ - - - -#define MD_MB_ECC_CONFIG 0x007E0000 /* - * Data ECC - * Configuration - */ - - - -#define MD_MEM_ERROR 0x007E0010 /* Memory DIMM error */ - - - -#define MD_MEM_ERROR_CLR 0x007E0018 /* - * Memory DIMM error - * clear - */ - - - -#define MD_BIST_MB_ERR_DATA_0 0x007E0020 /* - * BIST memory error - * data - */ - - - -#define MD_BIST_MB_ERR_DATA_1 0x007E0028 /* - * BIST memory error - * data - */ - - - -#define MD_BIST_MB_ERR_DATA_2 0x007E0030 /* - * BIST memory error - * data - */ - - - -#define MD_BIST_MB_ERR_DATA_3 0x007E0038 /* - * BIST memory error - * data - */ - - - -#define MD_MB_DEBUG 0x007E0040 /* MB debug select */ - - - - - -#ifndef __ASSEMBLY__ - -/************************************************************************ - * * - * Description: This register shows which regions are in the current * - * cell. If a region has its bit set in this register, then it uses * - * the Local Access protection in the directory instead of the * - * separate per-region protection (which would cause a small * - * performance penalty). In addition, writeback and write reply * - * commands from outside the current cell will always check the * - * directory protection before writing data to memory. Writeback and * - * write reply commands from inside the current cell will write * - * memory regardless of the protection value. * - * This register is also used as the access-rights bit-vector for * - * most of the ASIC-special (HSpec) portion of the address space. It * - * covers the BDDIR, LREG, LBOOT, RREG, and RBOOT spaces. It does not * - * cover the UALIAS and BDECC spaces, as they are covered by the * - * protection in the directory. If a bit in the bit-vector is set, * - * the region corresponding to that bit has read/write permission on * - * these spaces. If the bit is clear, then that region has read-only * - * access to these spaces (except for LREG/RREG which have no access * - * when the bit is clear). * - * The granularity of a region is set by the REGION_SIZE register in * - * the NI local register space. * - * NOTE: This means that no processor outside the current cell can * - * write into the BDDIR, LREG, LBOOT, RREG, or RBOOT spaces. * - * * - ************************************************************************/ - - - - -typedef union md_current_cell_u { - bdrkreg_t md_current_cell_regval; - struct { - bdrkreg_t cc_hspec_prot : 64; - } md_current_cell_fld_s; -} md_current_cell_u_t; - - - - -/************************************************************************ - * * - * Description: This register contains three sets of information. * - * The first set describes the size and configuration of DIMMs that * - * are plugged into a system, the second set controls which set of * - * protection checks are performed on each access and the third set * - * controls various DDR SDRAM timing parameters. * - * In order to config a DIMM bank, three fields must be initialized: * - * BANK_SIZE, DRAM_WIDTH, and BANK_ENABLE. The BANK_SIZE field sets * - * the address range that the MD unit will accept for that DIMM bank. * - * All addresses larger than the specified size will return errors on * - * access. In order to read from a DIMM bank, Bedrock must know * - * whether or not the bank contains x4 or x8/x16 DRAM. The operating * - * system must query the System Controller for this information and * - * then set the DRAM_WIDTH field accordingly. The BANK_ENABLE field * - * can be used to individually enable the two physical banks located * - * on each DIMM bank. * - * The contents of this register are preserved through soft-resets. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_memory_config_u { - bdrkreg_t md_memory_config_regval; - struct { - bdrkreg_t mc_dimm0_bank_enable : 2; - bdrkreg_t mc_reserved_7 : 1; - bdrkreg_t mc_dimm0_dram_width : 1; - bdrkreg_t mc_dimm0_bank_size : 4; - bdrkreg_t mc_dimm1_bank_enable : 2; - bdrkreg_t mc_reserved_6 : 1; - bdrkreg_t mc_dimm1_dram_width : 1; - bdrkreg_t mc_dimm1_bank_size : 4; - bdrkreg_t mc_dimm2_bank_enable : 2; - bdrkreg_t mc_reserved_5 : 1; - bdrkreg_t mc_dimm2_dram_width : 1; - bdrkreg_t mc_dimm2_bank_size : 4; - bdrkreg_t mc_dimm3_bank_enable : 2; - bdrkreg_t mc_reserved_4 : 1; - bdrkreg_t mc_dimm3_dram_width : 1; - bdrkreg_t mc_dimm3_bank_size : 4; - bdrkreg_t mc_dimm0_sel : 2; - bdrkreg_t mc_reserved_3 : 10; - bdrkreg_t mc_cc_enable : 1; - bdrkreg_t mc_io_prot_en : 1; - bdrkreg_t mc_io_prot_ignore : 1; - bdrkreg_t mc_cpu_prot_ignore : 1; - bdrkreg_t mc_db_neg_edge : 1; - bdrkreg_t mc_phase_delay : 1; - bdrkreg_t mc_delay_mux_sel : 2; - bdrkreg_t mc_sample_time : 2; - bdrkreg_t mc_reserved_2 : 2; - bdrkreg_t mc_mb_neg_edge : 3; - bdrkreg_t mc_reserved_1 : 1; - bdrkreg_t mc_rcd_config : 1; - bdrkreg_t mc_rp_config : 1; - bdrkreg_t mc_reserved : 2; - } md_memory_config_fld_s; -} md_memory_config_u_t; - -#else - -typedef union md_memory_config_u { - bdrkreg_t md_memory_config_regval; - struct { - bdrkreg_t mc_reserved : 2; - bdrkreg_t mc_rp_config : 1; - bdrkreg_t mc_rcd_config : 1; - bdrkreg_t mc_reserved_1 : 1; - bdrkreg_t mc_mb_neg_edge : 3; - bdrkreg_t mc_reserved_2 : 2; - bdrkreg_t mc_sample_time : 2; - bdrkreg_t mc_delay_mux_sel : 2; - bdrkreg_t mc_phase_delay : 1; - bdrkreg_t mc_db_neg_edge : 1; - bdrkreg_t mc_cpu_prot_ignore : 1; - bdrkreg_t mc_io_prot_ignore : 1; - bdrkreg_t mc_io_prot_en : 1; - bdrkreg_t mc_cc_enable : 1; - bdrkreg_t mc_reserved_3 : 10; - bdrkreg_t mc_dimm0_sel : 2; - bdrkreg_t mc_dimm3_bank_size : 4; - bdrkreg_t mc_dimm3_dram_width : 1; - bdrkreg_t mc_reserved_4 : 1; - bdrkreg_t mc_dimm3_bank_enable : 2; - bdrkreg_t mc_dimm2_bank_size : 4; - bdrkreg_t mc_dimm2_dram_width : 1; - bdrkreg_t mc_reserved_5 : 1; - bdrkreg_t mc_dimm2_bank_enable : 2; - bdrkreg_t mc_dimm1_bank_size : 4; - bdrkreg_t mc_dimm1_dram_width : 1; - bdrkreg_t mc_reserved_6 : 1; - bdrkreg_t mc_dimm1_bank_enable : 2; - bdrkreg_t mc_dimm0_bank_size : 4; - bdrkreg_t mc_dimm0_dram_width : 1; - bdrkreg_t mc_reserved_7 : 1; - bdrkreg_t mc_dimm0_bank_enable : 2; - } md_memory_config_fld_s; -} md_memory_config_u_t; - -#endif - - - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_arbitration_control_u { - bdrkreg_t md_arbitration_control_regval; - struct { - bdrkreg_t ac_reply_guar : 4; - bdrkreg_t ac_write_guar : 4; - bdrkreg_t ac_reserved : 56; - } md_arbitration_control_fld_s; -} md_arbitration_control_u_t; - -#else - -typedef union md_arbitration_control_u { - bdrkreg_t md_arbitration_control_regval; - struct { - bdrkreg_t ac_reserved : 56; - bdrkreg_t ac_write_guar : 4; - bdrkreg_t ac_reply_guar : 4; - } md_arbitration_control_fld_s; -} md_arbitration_control_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains page migration control fields. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_mig_config_u { - bdrkreg_t md_mig_config_regval; - struct { - bdrkreg_t mc_mig_interval : 10; - bdrkreg_t mc_reserved_2 : 6; - bdrkreg_t mc_mig_node_mask : 8; - bdrkreg_t mc_reserved_1 : 8; - bdrkreg_t mc_mig_enable : 1; - bdrkreg_t mc_reserved : 31; - } md_mig_config_fld_s; -} md_mig_config_u_t; - -#else - -typedef union md_mig_config_u { - bdrkreg_t md_mig_config_regval; - struct { - bdrkreg_t mc_reserved : 31; - bdrkreg_t mc_mig_enable : 1; - bdrkreg_t mc_reserved_1 : 8; - bdrkreg_t mc_mig_node_mask : 8; - bdrkreg_t mc_reserved_2 : 6; - bdrkreg_t mc_mig_interval : 10; - } md_mig_config_fld_s; -} md_mig_config_u_t; - -#endif - - - - -/************************************************************************ - * * - * Each register contains the valid bit and address of the entry in * - * the fetch-and-op for cache 0 (or 1). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_fandop_cac_stat0_u { - bdrkreg_t md_fandop_cac_stat0_regval; - struct { - bdrkreg_t fcs_reserved_1 : 6; - bdrkreg_t fcs_addr : 27; - bdrkreg_t fcs_reserved : 30; - bdrkreg_t fcs_valid : 1; - } md_fandop_cac_stat0_fld_s; -} md_fandop_cac_stat0_u_t; - -#else - -typedef union md_fandop_cac_stat0_u { - bdrkreg_t md_fandop_cac_stat0_regval; - struct { - bdrkreg_t fcs_valid : 1; - bdrkreg_t fcs_reserved : 30; - bdrkreg_t fcs_addr : 27; - bdrkreg_t fcs_reserved_1 : 6; - } md_fandop_cac_stat0_fld_s; -} md_fandop_cac_stat0_u_t; - -#endif - - - - -/************************************************************************ - * * - * Each register contains the valid bit and address of the entry in * - * the fetch-and-op for cache 0 (or 1). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_fandop_cac_stat1_u { - bdrkreg_t md_fandop_cac_stat1_regval; - struct { - bdrkreg_t fcs_reserved_1 : 6; - bdrkreg_t fcs_addr : 27; - bdrkreg_t fcs_reserved : 30; - bdrkreg_t fcs_valid : 1; - } md_fandop_cac_stat1_fld_s; -} md_fandop_cac_stat1_u_t; - -#else - -typedef union md_fandop_cac_stat1_u { - bdrkreg_t md_fandop_cac_stat1_regval; - struct { - bdrkreg_t fcs_valid : 1; - bdrkreg_t fcs_reserved : 30; - bdrkreg_t fcs_addr : 27; - bdrkreg_t fcs_reserved_1 : 6; - } md_fandop_cac_stat1_fld_s; -} md_fandop_cac_stat1_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: Contains a number of fields to capture various * - * random memory/directory errors. For each 2-bit field, the LSB * - * indicates that additional information has been captured for the * - * error and the MSB indicates overrun, thus: * - * x1: bits 51...0 of this register contain additional information * - * for the message that caused this error * - * 1x: overrun occurred * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_misc0_error_u { - bdrkreg_t md_misc0_error_regval; - struct { - bdrkreg_t me_command : 7; - bdrkreg_t me_reserved_4 : 1; - bdrkreg_t me_source : 11; - bdrkreg_t me_reserved_3 : 1; - bdrkreg_t me_suppl : 11; - bdrkreg_t me_reserved_2 : 1; - bdrkreg_t me_virtual_channel : 2; - bdrkreg_t me_reserved_1 : 2; - bdrkreg_t me_tail : 1; - bdrkreg_t me_reserved : 11; - bdrkreg_t me_xb_error : 4; - bdrkreg_t me_bad_partial_data : 2; - bdrkreg_t me_missing_dv : 2; - bdrkreg_t me_short_pack : 2; - bdrkreg_t me_long_pack : 2; - bdrkreg_t me_ill_msg : 2; - bdrkreg_t me_ill_revision : 2; - } md_misc0_error_fld_s; -} md_misc0_error_u_t; - -#else - -typedef union md_misc0_error_u { - bdrkreg_t md_misc0_error_regval; - struct { - bdrkreg_t me_ill_revision : 2; - bdrkreg_t me_ill_msg : 2; - bdrkreg_t me_long_pack : 2; - bdrkreg_t me_short_pack : 2; - bdrkreg_t me_missing_dv : 2; - bdrkreg_t me_bad_partial_data : 2; - bdrkreg_t me_xb_error : 4; - bdrkreg_t me_reserved : 11; - bdrkreg_t me_tail : 1; - bdrkreg_t me_reserved_1 : 2; - bdrkreg_t me_virtual_channel : 2; - bdrkreg_t me_reserved_2 : 1; - bdrkreg_t me_suppl : 11; - bdrkreg_t me_reserved_3 : 1; - bdrkreg_t me_source : 11; - bdrkreg_t me_reserved_4 : 1; - bdrkreg_t me_command : 7; - } md_misc0_error_fld_s; -} md_misc0_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * Address for error captured in MISC0_ERROR. Error valid bits are * - * repeated in both MISC0_ERROR and MISC1_ERROR (allowing them to be * - * read sequentially without missing any errors). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_misc1_error_u { - bdrkreg_t md_misc1_error_regval; - struct { - bdrkreg_t me_reserved_1 : 3; - bdrkreg_t me_address : 38; - bdrkreg_t me_reserved : 7; - bdrkreg_t me_xb_error : 4; - bdrkreg_t me_bad_partial_data : 2; - bdrkreg_t me_missing_dv : 2; - bdrkreg_t me_short_pack : 2; - bdrkreg_t me_long_pack : 2; - bdrkreg_t me_ill_msg : 2; - bdrkreg_t me_ill_revision : 2; - } md_misc1_error_fld_s; -} md_misc1_error_u_t; - -#else - -typedef union md_misc1_error_u { - bdrkreg_t md_misc1_error_regval; - struct { - bdrkreg_t me_ill_revision : 2; - bdrkreg_t me_ill_msg : 2; - bdrkreg_t me_long_pack : 2; - bdrkreg_t me_short_pack : 2; - bdrkreg_t me_missing_dv : 2; - bdrkreg_t me_bad_partial_data : 2; - bdrkreg_t me_xb_error : 4; - bdrkreg_t me_reserved : 7; - bdrkreg_t me_address : 38; - bdrkreg_t me_reserved_1 : 3; - } md_misc1_error_fld_s; -} md_misc1_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * Address for error captured in MISC0_ERROR. Error valid bits are * - * repeated in both MISC0_ERROR and MISC1_ERROR (allowing them to be * - * read sequentially without missing any errors). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_misc1_error_clr_u { - bdrkreg_t md_misc1_error_clr_regval; - struct { - bdrkreg_t mec_reserved_1 : 3; - bdrkreg_t mec_address : 38; - bdrkreg_t mec_reserved : 7; - bdrkreg_t mec_xb_error : 4; - bdrkreg_t mec_bad_partial_data : 2; - bdrkreg_t mec_missing_dv : 2; - bdrkreg_t mec_short_pack : 2; - bdrkreg_t mec_long_pack : 2; - bdrkreg_t mec_ill_msg : 2; - bdrkreg_t mec_ill_revision : 2; - } md_misc1_error_clr_fld_s; -} md_misc1_error_clr_u_t; - -#else - -typedef union md_misc1_error_clr_u { - bdrkreg_t md_misc1_error_clr_regval; - struct { - bdrkreg_t mec_ill_revision : 2; - bdrkreg_t mec_ill_msg : 2; - bdrkreg_t mec_long_pack : 2; - bdrkreg_t mec_short_pack : 2; - bdrkreg_t mec_missing_dv : 2; - bdrkreg_t mec_bad_partial_data : 2; - bdrkreg_t mec_xb_error : 4; - bdrkreg_t mec_reserved : 7; - bdrkreg_t mec_address : 38; - bdrkreg_t mec_reserved_1 : 3; - } md_misc1_error_clr_fld_s; -} md_misc1_error_clr_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: The MD no longer allows for arbitrarily sizing the * - * reply queues, so all of the fields in this register are read-only * - * and contain the reset default value of 12 for the MOQHs (for * - * headers) and 24 for the MOQDs (for data). * - * Reading from this register returns the values currently held in * - * the MD's credit counters. Writing to the register resets the * - * counters to the default reset values specified in the table below. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_outgoing_rp_queue_size_u { - bdrkreg_t md_outgoing_rp_queue_size_regval; - struct { - bdrkreg_t orqs_reserved_6 : 8; - bdrkreg_t orqs_moqh_p0_rp_size : 4; - bdrkreg_t orqs_reserved_5 : 4; - bdrkreg_t orqs_moqh_p1_rp_size : 4; - bdrkreg_t orqs_reserved_4 : 4; - bdrkreg_t orqs_moqh_np_rp_size : 4; - bdrkreg_t orqs_reserved_3 : 4; - bdrkreg_t orqs_moqd_pi0_rp_size : 5; - bdrkreg_t orqs_reserved_2 : 3; - bdrkreg_t orqs_moqd_pi1_rp_size : 5; - bdrkreg_t orqs_reserved_1 : 3; - bdrkreg_t orqs_moqd_np_rp_size : 5; - bdrkreg_t orqs_reserved : 11; - } md_outgoing_rp_queue_size_fld_s; -} md_outgoing_rp_queue_size_u_t; - -#else - -typedef union md_outgoing_rp_queue_size_u { - bdrkreg_t md_outgoing_rp_queue_size_regval; - struct { - bdrkreg_t orqs_reserved : 11; - bdrkreg_t orqs_moqd_np_rp_size : 5; - bdrkreg_t orqs_reserved_1 : 3; - bdrkreg_t orqs_moqd_pi1_rp_size : 5; - bdrkreg_t orqs_reserved_2 : 3; - bdrkreg_t orqs_moqd_pi0_rp_size : 5; - bdrkreg_t orqs_reserved_3 : 4; - bdrkreg_t orqs_moqh_np_rp_size : 4; - bdrkreg_t orqs_reserved_4 : 4; - bdrkreg_t orqs_moqh_p1_rp_size : 4; - bdrkreg_t orqs_reserved_5 : 4; - bdrkreg_t orqs_moqh_p0_rp_size : 4; - bdrkreg_t orqs_reserved_6 : 8; - } md_outgoing_rp_queue_size_fld_s; -} md_outgoing_rp_queue_size_u_t; - -#endif - - - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_perf_sel0_u { - bdrkreg_t md_perf_sel0_regval; - struct { - bdrkreg_t ps_cnt_mode : 2; - bdrkreg_t ps_reserved_2 : 2; - bdrkreg_t ps_activity : 4; - bdrkreg_t ps_source : 7; - bdrkreg_t ps_reserved_1 : 1; - bdrkreg_t ps_channel : 4; - bdrkreg_t ps_command : 40; - bdrkreg_t ps_reserved : 3; - bdrkreg_t ps_interrupt : 1; - } md_perf_sel0_fld_s; -} md_perf_sel0_u_t; - -#else - -typedef union md_perf_sel0_u { - bdrkreg_t md_perf_sel0_regval; - struct { - bdrkreg_t ps_interrupt : 1; - bdrkreg_t ps_reserved : 3; - bdrkreg_t ps_command : 40; - bdrkreg_t ps_channel : 4; - bdrkreg_t ps_reserved_1 : 1; - bdrkreg_t ps_source : 7; - bdrkreg_t ps_activity : 4; - bdrkreg_t ps_reserved_2 : 2; - bdrkreg_t ps_cnt_mode : 2; - } md_perf_sel0_fld_s; -} md_perf_sel0_u_t; - -#endif - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_perf_sel1_u { - bdrkreg_t md_perf_sel1_regval; - struct { - bdrkreg_t ps_cnt_mode : 2; - bdrkreg_t ps_reserved_2 : 2; - bdrkreg_t ps_activity : 4; - bdrkreg_t ps_source : 7; - bdrkreg_t ps_reserved_1 : 1; - bdrkreg_t ps_channel : 4; - bdrkreg_t ps_command : 40; - bdrkreg_t ps_reserved : 3; - bdrkreg_t ps_interrupt : 1; - } md_perf_sel1_fld_s; -} md_perf_sel1_u_t; - -#else - -typedef union md_perf_sel1_u { - bdrkreg_t md_perf_sel1_regval; - struct { - bdrkreg_t ps_interrupt : 1; - bdrkreg_t ps_reserved : 3; - bdrkreg_t ps_command : 40; - bdrkreg_t ps_channel : 4; - bdrkreg_t ps_reserved_1 : 1; - bdrkreg_t ps_source : 7; - bdrkreg_t ps_activity : 4; - bdrkreg_t ps_reserved_2 : 2; - bdrkreg_t ps_cnt_mode : 2; - } md_perf_sel1_fld_s; -} md_perf_sel1_u_t; - -#endif - - - - -/************************************************************************ - * * - * Performance counter. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_perf_cnt0_u { - bdrkreg_t md_perf_cnt0_regval; - struct { - bdrkreg_t pc_perf_cnt : 41; - bdrkreg_t pc_reserved : 23; - } md_perf_cnt0_fld_s; -} md_perf_cnt0_u_t; - -#else - -typedef union md_perf_cnt0_u { - bdrkreg_t md_perf_cnt0_regval; - struct { - bdrkreg_t pc_reserved : 23; - bdrkreg_t pc_perf_cnt : 41; - } md_perf_cnt0_fld_s; -} md_perf_cnt0_u_t; - -#endif - - - - -/************************************************************************ - * * - * Performance counter. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_perf_cnt1_u { - bdrkreg_t md_perf_cnt1_regval; - struct { - bdrkreg_t pc_perf_cnt : 41; - bdrkreg_t pc_reserved : 23; - } md_perf_cnt1_fld_s; -} md_perf_cnt1_u_t; - -#else - -typedef union md_perf_cnt1_u { - bdrkreg_t md_perf_cnt1_regval; - struct { - bdrkreg_t pc_reserved : 23; - bdrkreg_t pc_perf_cnt : 41; - } md_perf_cnt1_fld_s; -} md_perf_cnt1_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This register contains the control for * - * memory/directory refresh. Once the MEMORY_CONFIG register contains * - * the correct DIMM information, the hardware takes care of * - * refreshing all the banks in the system. Therefore, the value in * - * the counter threshold is corresponds exactly to the refresh value * - * required by the SDRAM parts (expressed in Bedrock clock cycles). * - * The refresh will execute whenever there is a free cycle and there * - * are still banks that have not been refreshed in the current * - * window. If the window expires with banks still waiting to be * - * refreshed, all other transactions are halted until the banks are * - * refreshed. * - * The upper order bit contains an enable, which may be needed for * - * correct initialization of the DIMMs (according to the specs, the * - * first operation to the DIMMs should be a mode register write, not * - * a refresh, so this bit is cleared on reset) and is also useful for * - * diagnostic purposes. * - * For the SDRAM parts used by Bedrock, 4096 refreshes need to be * - * issued during every 64 ms window, resulting in a refresh threshold * - * of 3125 Bedrock cycles. * - * The ENABLE and CNT_THRESH fields of this register are preserved * - * through soft-resets. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_refresh_control_u { - bdrkreg_t md_refresh_control_regval; - struct { - bdrkreg_t rc_cnt_thresh : 12; - bdrkreg_t rc_counter : 12; - bdrkreg_t rc_reserved : 39; - bdrkreg_t rc_enable : 1; - } md_refresh_control_fld_s; -} md_refresh_control_u_t; - -#else - -typedef union md_refresh_control_u { - bdrkreg_t md_refresh_control_regval; - struct { - bdrkreg_t rc_enable : 1; - bdrkreg_t rc_reserved : 39; - bdrkreg_t rc_counter : 12; - bdrkreg_t rc_cnt_thresh : 12; - } md_refresh_control_fld_s; -} md_refresh_control_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register controls the read and write timing for Flash PROM, * - * UART and Synergy junk bus devices. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_junk_bus_timing_u { - bdrkreg_t md_junk_bus_timing_regval; - struct { - bdrkreg_t jbt_fprom_setup_hold : 8; - bdrkreg_t jbt_fprom_enable : 8; - bdrkreg_t jbt_uart_setup_hold : 8; - bdrkreg_t jbt_uart_enable : 8; - bdrkreg_t jbt_synergy_setup_hold : 8; - bdrkreg_t jbt_synergy_enable : 8; - bdrkreg_t jbt_reserved : 16; - } md_junk_bus_timing_fld_s; -} md_junk_bus_timing_u_t; - -#else - -typedef union md_junk_bus_timing_u { - bdrkreg_t md_junk_bus_timing_regval; - struct { - bdrkreg_t jbt_reserved : 16; - bdrkreg_t jbt_synergy_enable : 8; - bdrkreg_t jbt_synergy_setup_hold : 8; - bdrkreg_t jbt_uart_enable : 8; - bdrkreg_t jbt_uart_setup_hold : 8; - bdrkreg_t jbt_fprom_enable : 8; - bdrkreg_t jbt_fprom_setup_hold : 8; - } md_junk_bus_timing_fld_s; -} md_junk_bus_timing_u_t; - -#endif - - - - -/************************************************************************ - * * - * Each of these addresses allows the value on one 8-bit bank of * - * LEDs to be read. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_led0_u { - bdrkreg_t md_led0_regval; - struct { - bdrkreg_t l_data : 8; - bdrkreg_t l_reserved : 56; - } md_led0_fld_s; -} md_led0_u_t; - -#else - -typedef union md_led0_u { - bdrkreg_t md_led0_regval; - struct { - bdrkreg_t l_reserved : 56; - bdrkreg_t l_data : 8; - } md_led0_fld_s; -} md_led0_u_t; - -#endif - - - - -/************************************************************************ - * * - * Each of these addresses allows the value on one 8-bit bank of * - * LEDs to be read. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_led1_u { - bdrkreg_t md_led1_regval; - struct { - bdrkreg_t l_data : 8; - bdrkreg_t l_reserved : 56; - } md_led1_fld_s; -} md_led1_u_t; - -#else - -typedef union md_led1_u { - bdrkreg_t md_led1_regval; - struct { - bdrkreg_t l_reserved : 56; - bdrkreg_t l_data : 8; - } md_led1_fld_s; -} md_led1_u_t; - -#endif - - - - -/************************************************************************ - * * - * Each of these addresses allows the value on one 8-bit bank of * - * LEDs to be read. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_led2_u { - bdrkreg_t md_led2_regval; - struct { - bdrkreg_t l_data : 8; - bdrkreg_t l_reserved : 56; - } md_led2_fld_s; -} md_led2_u_t; - -#else - -typedef union md_led2_u { - bdrkreg_t md_led2_regval; - struct { - bdrkreg_t l_reserved : 56; - bdrkreg_t l_data : 8; - } md_led2_fld_s; -} md_led2_u_t; - -#endif - - - - -/************************************************************************ - * * - * Each of these addresses allows the value on one 8-bit bank of * - * LEDs to be read. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_led3_u { - bdrkreg_t md_led3_regval; - struct { - bdrkreg_t l_data : 8; - bdrkreg_t l_reserved : 56; - } md_led3_fld_s; -} md_led3_u_t; - -#else - -typedef union md_led3_u { - bdrkreg_t md_led3_regval; - struct { - bdrkreg_t l_reserved : 56; - bdrkreg_t l_data : 8; - } md_led3_fld_s; -} md_led3_u_t; - -#endif - - - - -/************************************************************************ - * * - * Core control for the BIST function. Start and stop BIST at any * - * time. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_bist_ctl_u { - bdrkreg_t md_bist_ctl_regval; - struct { - bdrkreg_t bc_bist_start : 1; - bdrkreg_t bc_bist_stop : 1; - bdrkreg_t bc_bist_reset : 1; - bdrkreg_t bc_reserved_1 : 1; - bdrkreg_t bc_bank_num : 1; - bdrkreg_t bc_dimm_num : 2; - bdrkreg_t bc_reserved : 57; - } md_bist_ctl_fld_s; -} md_bist_ctl_u_t; - -#else - -typedef union md_bist_ctl_u { - bdrkreg_t md_bist_ctl_regval; - struct { - bdrkreg_t bc_reserved : 57; - bdrkreg_t bc_dimm_num : 2; - bdrkreg_t bc_bank_num : 1; - bdrkreg_t bc_reserved_1 : 1; - bdrkreg_t bc_bist_reset : 1; - bdrkreg_t bc_bist_stop : 1; - bdrkreg_t bc_bist_start : 1; - } md_bist_ctl_fld_s; -} md_bist_ctl_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contain the initial BIST data nibble and the 4-bit data control * - * field.. * - * * - ************************************************************************/ - - - -#ifdef LITTLE_ENDIAN - -typedef union md_bist_data_u { - bdrkreg_t md_bist_data_regval; - struct { - bdrkreg_t bd_bist_data : 4; - bdrkreg_t bd_bist_nibble : 1; - bdrkreg_t bd_bist_byte : 1; - bdrkreg_t bd_bist_cycle : 1; - bdrkreg_t bd_bist_write : 1; - bdrkreg_t bd_reserved : 56; - } md_bist_data_fld_s; -} md_bist_data_u_t; - -#else - -typedef union md_bist_data_u { - bdrkreg_t md_bist_data_regval; - struct { - bdrkreg_t bd_reserved : 56; - bdrkreg_t bd_bist_write : 1; - bdrkreg_t bd_bist_cycle : 1; - bdrkreg_t bd_bist_byte : 1; - bdrkreg_t bd_bist_nibble : 1; - bdrkreg_t bd_bist_data : 4; - } md_bist_data_fld_s; -} md_bist_data_u_t; - -#endif - - - - -/************************************************************************ - * * - * Captures the BIST error address and indicates whether it is an MB * - * error or DB error. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_bist_ab_err_addr_u { - bdrkreg_t md_bist_ab_err_addr_regval; - struct { - bdrkreg_t baea_be_db_cas_addr : 15; - bdrkreg_t baea_reserved_3 : 1; - bdrkreg_t baea_be_mb_cas_addr : 15; - bdrkreg_t baea_reserved_2 : 1; - bdrkreg_t baea_be_ras_addr : 15; - bdrkreg_t baea_reserved_1 : 1; - bdrkreg_t baea_bist_mb_error : 1; - bdrkreg_t baea_bist_db_error : 1; - bdrkreg_t baea_reserved : 14; - } md_bist_ab_err_addr_fld_s; -} md_bist_ab_err_addr_u_t; - -#else - -typedef union md_bist_ab_err_addr_u { - bdrkreg_t md_bist_ab_err_addr_regval; - struct { - bdrkreg_t baea_reserved : 14; - bdrkreg_t baea_bist_db_error : 1; - bdrkreg_t baea_bist_mb_error : 1; - bdrkreg_t baea_reserved_1 : 1; - bdrkreg_t baea_be_ras_addr : 15; - bdrkreg_t baea_reserved_2 : 1; - bdrkreg_t baea_be_mb_cas_addr : 15; - bdrkreg_t baea_reserved_3 : 1; - bdrkreg_t baea_be_db_cas_addr : 15; - } md_bist_ab_err_addr_fld_s; -} md_bist_ab_err_addr_u_t; - -#endif - - - -/************************************************************************ - * * - * Contains information on BIST progress and memory bank currently * - * under BIST. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_bist_status_u { - bdrkreg_t md_bist_status_regval; - struct { - bdrkreg_t bs_bist_passed : 1; - bdrkreg_t bs_bist_done : 1; - bdrkreg_t bs_reserved : 62; - } md_bist_status_fld_s; -} md_bist_status_u_t; - -#else - -typedef union md_bist_status_u { - bdrkreg_t md_bist_status_regval; - struct { - bdrkreg_t bs_reserved : 62; - bdrkreg_t bs_bist_done : 1; - bdrkreg_t bs_bist_passed : 1; - } md_bist_status_fld_s; -} md_bist_status_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains 3 bits that allow the selection of IB debug information * - * at the debug port (see design specification for available debug * - * information). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_ib_debug_u { - bdrkreg_t md_ib_debug_regval; - struct { - bdrkreg_t id_ib_debug_sel : 2; - bdrkreg_t id_reserved : 62; - } md_ib_debug_fld_s; -} md_ib_debug_u_t; - -#else - -typedef union md_ib_debug_u { - bdrkreg_t md_ib_debug_regval; - struct { - bdrkreg_t id_reserved : 62; - bdrkreg_t id_ib_debug_sel : 2; - } md_ib_debug_fld_s; -} md_ib_debug_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains the directory specific mode bits. The contents of this * - * register are preserved through soft-resets. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_dir_config_u { - bdrkreg_t md_dir_config_regval; - struct { - bdrkreg_t dc_dir_flavor : 1; - bdrkreg_t dc_ignore_dir_ecc : 1; - bdrkreg_t dc_reserved : 62; - } md_dir_config_fld_s; -} md_dir_config_u_t; - -#else - -typedef union md_dir_config_u { - bdrkreg_t md_dir_config_regval; - struct { - bdrkreg_t dc_reserved : 62; - bdrkreg_t dc_ignore_dir_ecc : 1; - bdrkreg_t dc_dir_flavor : 1; - } md_dir_config_fld_s; -} md_dir_config_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: Contains information on uncorrectable and * - * correctable directory ECC errors, along with protection ECC * - * errors. The priority of ECC errors latched is: uncorrectable * - * directory, protection error, correctable directory. Thus the valid * - * bits signal: * - * 1xxx: uncorrectable directory ECC error (UCE) * - * 01xx: access protection double bit error (AE) * - * 001x: correctable directory ECC error (CE) * - * 0001: access protection correctable error (ACE) * - * If the UCE valid bit is set, the address field contains a pointer * - * to the Hspec address of the offending directory entry, the * - * syndrome field contains the bad syndrome, and the UCE overrun bit * - * indicates whether multiple double-bit errors were received. * - * If the UCE valid bit is clear but the AE valid bit is set, the * - * address field contains a pointer to the Hspec address of the * - * offending protection entry, the Bad Protection field contains the * - * 4-bit bad protection value, the PROT_INDEX field shows which of * - * the 8 protection values in the word was bad and the AE overrun bit * - * indicates whether multiple AE errors were received. * - * If the UCE and AE valid bits are clear, but the CE valid bit is * - * set, the address field contains a pointer to the Hspec address of * - * the offending directory entry, the syndrome field contains the bad * - * syndrome, and the CE overrun bit indicates whether multiple * - * single-bit errors were received. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_dir_error_u { - bdrkreg_t md_dir_error_regval; - struct { - bdrkreg_t de_reserved_3 : 3; - bdrkreg_t de_hspec_addr : 30; - bdrkreg_t de_reserved_2 : 7; - bdrkreg_t de_bad_syn : 7; - bdrkreg_t de_reserved_1 : 1; - bdrkreg_t de_bad_protect : 4; - bdrkreg_t de_prot_index : 3; - bdrkreg_t de_reserved : 1; - bdrkreg_t de_ace_overrun : 1; - bdrkreg_t de_ce_overrun : 1; - bdrkreg_t de_ae_overrun : 1; - bdrkreg_t de_uce_overrun : 1; - bdrkreg_t de_ace_valid : 1; - bdrkreg_t de_ce_valid : 1; - bdrkreg_t de_ae_valid : 1; - bdrkreg_t de_uce_valid : 1; - } md_dir_error_fld_s; -} md_dir_error_u_t; - -#else - -typedef union md_dir_error_u { - bdrkreg_t md_dir_error_regval; - struct { - bdrkreg_t de_uce_valid : 1; - bdrkreg_t de_ae_valid : 1; - bdrkreg_t de_ce_valid : 1; - bdrkreg_t de_ace_valid : 1; - bdrkreg_t de_uce_overrun : 1; - bdrkreg_t de_ae_overrun : 1; - bdrkreg_t de_ce_overrun : 1; - bdrkreg_t de_ace_overrun : 1; - bdrkreg_t de_reserved : 1; - bdrkreg_t de_prot_index : 3; - bdrkreg_t de_bad_protect : 4; - bdrkreg_t de_reserved_1 : 1; - bdrkreg_t de_bad_syn : 7; - bdrkreg_t de_reserved_2 : 7; - bdrkreg_t de_hspec_addr : 30; - bdrkreg_t de_reserved_3 : 3; - } md_dir_error_fld_s; -} md_dir_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: Contains information on uncorrectable and * - * correctable directory ECC errors, along with protection ECC * - * errors. The priority of ECC errors latched is: uncorrectable * - * directory, protection error, correctable directory. Thus the valid * - * bits signal: * - * 1xxx: uncorrectable directory ECC error (UCE) * - * 01xx: access protection double bit error (AE) * - * 001x: correctable directory ECC error (CE) * - * 0001: access protection correctable error (ACE) * - * If the UCE valid bit is set, the address field contains a pointer * - * to the Hspec address of the offending directory entry, the * - * syndrome field contains the bad syndrome, and the UCE overrun bit * - * indicates whether multiple double-bit errors were received. * - * If the UCE valid bit is clear but the AE valid bit is set, the * - * address field contains a pointer to the Hspec address of the * - * offending protection entry, the Bad Protection field contains the * - * 4-bit bad protection value, the PROT_INDEX field shows which of * - * the 8 protection values in the word was bad and the AE overrun bit * - * indicates whether multiple AE errors were received. * - * If the UCE and AE valid bits are clear, but the CE valid bit is * - * set, the address field contains a pointer to the Hspec address of * - * the offending directory entry, the syndrome field contains the bad * - * syndrome, and the CE overrun bit indicates whether multiple * - * single-bit errors were received. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_dir_error_clr_u { - bdrkreg_t md_dir_error_clr_regval; - struct { - bdrkreg_t dec_reserved_3 : 3; - bdrkreg_t dec_hspec_addr : 30; - bdrkreg_t dec_reserved_2 : 7; - bdrkreg_t dec_bad_syn : 7; - bdrkreg_t dec_reserved_1 : 1; - bdrkreg_t dec_bad_protect : 4; - bdrkreg_t dec_prot_index : 3; - bdrkreg_t dec_reserved : 1; - bdrkreg_t dec_ace_overrun : 1; - bdrkreg_t dec_ce_overrun : 1; - bdrkreg_t dec_ae_overrun : 1; - bdrkreg_t dec_uce_overrun : 1; - bdrkreg_t dec_ace_valid : 1; - bdrkreg_t dec_ce_valid : 1; - bdrkreg_t dec_ae_valid : 1; - bdrkreg_t dec_uce_valid : 1; - } md_dir_error_clr_fld_s; -} md_dir_error_clr_u_t; - -#else - -typedef union md_dir_error_clr_u { - bdrkreg_t md_dir_error_clr_regval; - struct { - bdrkreg_t dec_uce_valid : 1; - bdrkreg_t dec_ae_valid : 1; - bdrkreg_t dec_ce_valid : 1; - bdrkreg_t dec_ace_valid : 1; - bdrkreg_t dec_uce_overrun : 1; - bdrkreg_t dec_ae_overrun : 1; - bdrkreg_t dec_ce_overrun : 1; - bdrkreg_t dec_ace_overrun : 1; - bdrkreg_t dec_reserved : 1; - bdrkreg_t dec_prot_index : 3; - bdrkreg_t dec_bad_protect : 4; - bdrkreg_t dec_reserved_1 : 1; - bdrkreg_t dec_bad_syn : 7; - bdrkreg_t dec_reserved_2 : 7; - bdrkreg_t dec_hspec_addr : 30; - bdrkreg_t dec_reserved_3 : 3; - } md_dir_error_clr_fld_s; -} md_dir_error_clr_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains information on requests that encounter no valid protocol * - * table entry. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_protocol_error_u { - bdrkreg_t md_protocol_error_regval; - struct { - bdrkreg_t pe_overrun : 1; - bdrkreg_t pe_pointer_me : 1; - bdrkreg_t pe_reserved_1 : 1; - bdrkreg_t pe_address : 30; - bdrkreg_t pe_reserved : 1; - bdrkreg_t pe_ptr1_btmbits : 3; - bdrkreg_t pe_dir_format : 2; - bdrkreg_t pe_dir_state : 3; - bdrkreg_t pe_priority : 1; - bdrkreg_t pe_access : 1; - bdrkreg_t pe_msg_type : 8; - bdrkreg_t pe_initiator : 11; - bdrkreg_t pe_valid : 1; - } md_protocol_error_fld_s; -} md_protocol_error_u_t; - -#else - -typedef union md_protocol_error_u { - bdrkreg_t md_protocol_error_regval; - struct { - bdrkreg_t pe_valid : 1; - bdrkreg_t pe_initiator : 11; - bdrkreg_t pe_msg_type : 8; - bdrkreg_t pe_access : 1; - bdrkreg_t pe_priority : 1; - bdrkreg_t pe_dir_state : 3; - bdrkreg_t pe_dir_format : 2; - bdrkreg_t pe_ptr1_btmbits : 3; - bdrkreg_t pe_reserved : 1; - bdrkreg_t pe_address : 30; - bdrkreg_t pe_reserved_1 : 1; - bdrkreg_t pe_pointer_me : 1; - bdrkreg_t pe_overrun : 1; - } md_protocol_error_fld_s; -} md_protocol_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains information on requests that encounter no valid protocol * - * table entry. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_protocol_err_clr_u { - bdrkreg_t md_protocol_err_clr_regval; - struct { - bdrkreg_t pec_overrun : 1; - bdrkreg_t pec_pointer_me : 1; - bdrkreg_t pec_reserved_1 : 1; - bdrkreg_t pec_address : 30; - bdrkreg_t pec_reserved : 1; - bdrkreg_t pec_ptr1_btmbits : 3; - bdrkreg_t pec_dir_format : 2; - bdrkreg_t pec_dir_state : 3; - bdrkreg_t pec_priority : 1; - bdrkreg_t pec_access : 1; - bdrkreg_t pec_msg_type : 8; - bdrkreg_t pec_initiator : 11; - bdrkreg_t pec_valid : 1; - } md_protocol_err_clr_fld_s; -} md_protocol_err_clr_u_t; - -#else - -typedef union md_protocol_err_clr_u { - bdrkreg_t md_protocol_err_clr_regval; - struct { - bdrkreg_t pec_valid : 1; - bdrkreg_t pec_initiator : 11; - bdrkreg_t pec_msg_type : 8; - bdrkreg_t pec_access : 1; - bdrkreg_t pec_priority : 1; - bdrkreg_t pec_dir_state : 3; - bdrkreg_t pec_dir_format : 2; - bdrkreg_t pec_ptr1_btmbits : 3; - bdrkreg_t pec_reserved : 1; - bdrkreg_t pec_address : 30; - bdrkreg_t pec_reserved_1 : 1; - bdrkreg_t pec_pointer_me : 1; - bdrkreg_t pec_overrun : 1; - } md_protocol_err_clr_fld_s; -} md_protocol_err_clr_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains the address of the page and the requestor which caused a * - * migration threshold to be exceeded. Also contains the type of * - * threshold exceeded and an overrun bit. For Value mode type * - * interrupts, it indicates whether the local or the remote counter * - * triggered the interrupt. Unlike most registers, when the overrun * - * bit is set the register contains information on the most recent * - * (the last) migration candidate. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_mig_candidate_u { - bdrkreg_t md_mig_candidate_regval; - struct { - bdrkreg_t mc_address : 21; - bdrkreg_t mc_initiator : 11; - bdrkreg_t mc_overrun : 1; - bdrkreg_t mc_type : 1; - bdrkreg_t mc_local : 1; - bdrkreg_t mc_reserved : 28; - bdrkreg_t mc_valid : 1; - } md_mig_candidate_fld_s; -} md_mig_candidate_u_t; - -#else - -typedef union md_mig_candidate_u { - bdrkreg_t md_mig_candidate_regval; - struct { - bdrkreg_t mc_valid : 1; - bdrkreg_t mc_reserved : 28; - bdrkreg_t mc_local : 1; - bdrkreg_t mc_type : 1; - bdrkreg_t mc_overrun : 1; - bdrkreg_t mc_initiator : 11; - bdrkreg_t mc_address : 21; - } md_mig_candidate_fld_s; -} md_mig_candidate_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains the address of the page and the requestor which caused a * - * migration threshold to be exceeded. Also contains the type of * - * threshold exceeded and an overrun bit. For Value mode type * - * interrupts, it indicates whether the local or the remote counter * - * triggered the interrupt. Unlike most registers, when the overrun * - * bit is set the register contains information on the most recent * - * (the last) migration candidate. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_mig_candidate_clr_u { - bdrkreg_t md_mig_candidate_clr_regval; - struct { - bdrkreg_t mcc_address : 21; - bdrkreg_t mcc_initiator : 11; - bdrkreg_t mcc_overrun : 1; - bdrkreg_t mcc_type : 1; - bdrkreg_t mcc_local : 1; - bdrkreg_t mcc_reserved : 28; - bdrkreg_t mcc_valid : 1; - } md_mig_candidate_clr_fld_s; -} md_mig_candidate_clr_u_t; - -#else - -typedef union md_mig_candidate_clr_u { - bdrkreg_t md_mig_candidate_clr_regval; - struct { - bdrkreg_t mcc_valid : 1; - bdrkreg_t mcc_reserved : 28; - bdrkreg_t mcc_local : 1; - bdrkreg_t mcc_type : 1; - bdrkreg_t mcc_overrun : 1; - bdrkreg_t mcc_initiator : 11; - bdrkreg_t mcc_address : 21; - } md_mig_candidate_clr_fld_s; -} md_mig_candidate_clr_u_t; - -#endif - - - - -/************************************************************************ - * * - * Controls the generation of page-migration interrupts and loading * - * of the MIGRATION_CANDIDATE register for pages which are using the * - * difference between the requestor and home counts. If the * - * difference is greater-than or equal to than the threshold * - * contained in the register, and the valid bit is set, the migration * - * candidate is loaded (and an interrupt generated if enabled by the * - * page migration mode). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_mig_diff_thresh_u { - bdrkreg_t md_mig_diff_thresh_regval; - struct { - bdrkreg_t mdt_threshold : 15; - bdrkreg_t mdt_reserved_1 : 17; - bdrkreg_t mdt_th_action : 3; - bdrkreg_t mdt_sat_action : 3; - bdrkreg_t mdt_reserved : 25; - bdrkreg_t mdt_valid : 1; - } md_mig_diff_thresh_fld_s; -} md_mig_diff_thresh_u_t; - -#else - -typedef union md_mig_diff_thresh_u { - bdrkreg_t md_mig_diff_thresh_regval; - struct { - bdrkreg_t mdt_valid : 1; - bdrkreg_t mdt_reserved : 25; - bdrkreg_t mdt_sat_action : 3; - bdrkreg_t mdt_th_action : 3; - bdrkreg_t mdt_reserved_1 : 17; - bdrkreg_t mdt_threshold : 15; - } md_mig_diff_thresh_fld_s; -} md_mig_diff_thresh_u_t; - -#endif - - - - -/************************************************************************ - * * - * Controls the generation of page-migration interrupts and loading * - * of the MIGRATION_CANDIDATE register for pages that are using the * - * absolute value of the requestor count. If the value is * - * greater-than or equal to the threshold contained in the register, * - * and the register valid bit is set, the migration candidate is * - * loaded and an interrupt generated. For the value mode of page * - * migration, there are two variations. In the first variation, * - * interrupts are only generated when the remote counter reaches the * - * threshold, not when the local counter reaches the threshold. In * - * the second mode, both the local counter and the remote counter * - * generate interrupts if they reach the threshold. This second mode * - * is useful for performance monitoring, to track the number of local * - * and remote references to a page. LOCAL_INT determines whether we * - * will generate interrupts when the local counter reaches the * - * threshold. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_mig_value_thresh_u { - bdrkreg_t md_mig_value_thresh_regval; - struct { - bdrkreg_t mvt_threshold : 15; - bdrkreg_t mvt_reserved_1 : 17; - bdrkreg_t mvt_th_action : 3; - bdrkreg_t mvt_sat_action : 3; - bdrkreg_t mvt_reserved : 24; - bdrkreg_t mvt_local_int : 1; - bdrkreg_t mvt_valid : 1; - } md_mig_value_thresh_fld_s; -} md_mig_value_thresh_u_t; - -#else - -typedef union md_mig_value_thresh_u { - bdrkreg_t md_mig_value_thresh_regval; - struct { - bdrkreg_t mvt_valid : 1; - bdrkreg_t mvt_local_int : 1; - bdrkreg_t mvt_reserved : 24; - bdrkreg_t mvt_sat_action : 3; - bdrkreg_t mvt_th_action : 3; - bdrkreg_t mvt_reserved_1 : 17; - bdrkreg_t mvt_threshold : 15; - } md_mig_value_thresh_fld_s; -} md_mig_value_thresh_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains the controls for the sizing of the three MOQH request * - * queues. The maximum (and default) value is 4. Queue sizes are in * - * flits. One header equals one flit. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_outgoing_rq_queue_size_u { - bdrkreg_t md_outgoing_rq_queue_size_regval; - struct { - bdrkreg_t orqs_reserved_3 : 8; - bdrkreg_t orqs_moqh_p0_rq_size : 3; - bdrkreg_t orqs_reserved_2 : 5; - bdrkreg_t orqs_moqh_p1_rq_size : 3; - bdrkreg_t orqs_reserved_1 : 5; - bdrkreg_t orqs_moqh_np_rq_size : 3; - bdrkreg_t orqs_reserved : 37; - } md_outgoing_rq_queue_size_fld_s; -} md_outgoing_rq_queue_size_u_t; - -#else - -typedef union md_outgoing_rq_queue_size_u { - bdrkreg_t md_outgoing_rq_queue_size_regval; - struct { - bdrkreg_t orqs_reserved : 37; - bdrkreg_t orqs_moqh_np_rq_size : 3; - bdrkreg_t orqs_reserved_1 : 5; - bdrkreg_t orqs_moqh_p1_rq_size : 3; - bdrkreg_t orqs_reserved_2 : 5; - bdrkreg_t orqs_moqh_p0_rq_size : 3; - bdrkreg_t orqs_reserved_3 : 8; - } md_outgoing_rq_queue_size_fld_s; -} md_outgoing_rq_queue_size_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains the 32-bit directory word failing BIST. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_bist_db_err_data_u { - bdrkreg_t md_bist_db_err_data_regval; - struct { - bdrkreg_t bded_db_er_d : 32; - bdrkreg_t bded_reserved : 32; - } md_bist_db_err_data_fld_s; -} md_bist_db_err_data_u_t; - -#else - -typedef union md_bist_db_err_data_u { - bdrkreg_t md_bist_db_err_data_regval; - struct { - bdrkreg_t bded_reserved : 32; - bdrkreg_t bded_db_er_d : 32; - } md_bist_db_err_data_fld_s; -} md_bist_db_err_data_u_t; - -#endif - - - -/************************************************************************ - * * - * Contains 2 bits that allow the selection of DB debug information * - * at the debug port (see the design specification for descrition of * - * the available debug information). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_db_debug_u { - bdrkreg_t md_db_debug_regval; - struct { - bdrkreg_t dd_db_debug_sel : 2; - bdrkreg_t dd_reserved : 62; - } md_db_debug_fld_s; -} md_db_debug_u_t; - -#else - -typedef union md_db_debug_u { - bdrkreg_t md_db_debug_regval; - struct { - bdrkreg_t dd_reserved : 62; - bdrkreg_t dd_db_debug_sel : 2; - } md_db_debug_fld_s; -} md_db_debug_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains the IgnoreECC bit. When this bit is set, all ECC errors * - * are ignored. ECC bits will still be generated on writebacks. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_mb_ecc_config_u { - bdrkreg_t md_mb_ecc_config_regval; - struct { - bdrkreg_t mec_ignore_dataecc : 1; - bdrkreg_t mec_reserved : 63; - } md_mb_ecc_config_fld_s; -} md_mb_ecc_config_u_t; - -#else - -typedef union md_mb_ecc_config_u { - bdrkreg_t md_mb_ecc_config_regval; - struct { - bdrkreg_t mec_reserved : 63; - bdrkreg_t mec_ignore_dataecc : 1; - } md_mb_ecc_config_fld_s; -} md_mb_ecc_config_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: Contains information on read memory errors (both * - * correctable and uncorrectable) and write memory errors (always * - * uncorrectable). The errors are prioritized as follows: * - * highest: uncorrectable read error (READ_UCE) * - * middle: write error (WRITE_UCE) * - * lowest: correctable read error (READ_CE) * - * Each type of error maintains a two-bit valid/overrun field * - * (READ_UCE, WRITE_UCE, or READ_CE). Bit 0 of each two-bit field * - * corresponds to the valid bit, and bit 1 of each two-bit field * - * corresponds to the overrun bit. * - * The rule for the valid bit is that it gets set whenever that error * - * occurs, regardless of whether a higher priority error has occurred. * - * The rule for the overrun bit is that it gets set whenever we are * - * unable to record the address information for this particular * - * error, due to a previous error of the same or higher priority. * - * Note that the syndrome and address information always corresponds * - * to the earliest, highest priority error. * - * Finally, the UCE_DIFF_ADDR bit is set whenever there have been * - * several uncorrectable errors, to different cache line addresses. * - * If all the UCEs were to the same cache line address, then * - * UCE_DIFF_ADDR will be 0. This allows the operating system to * - * detect the case where a UCE error is read exclusively, and then * - * written back by the processor. If the bit is 0, it indicates that * - * no information has been lost about UCEs on other cache lines. In * - * particular, partial writes do a read modify write of the cache * - * line. A UCE read error will be set when the cache line is read, * - * and a UCE write error will occur when the cache line is written * - * back, but the UCE_DIFF_ADDR will not be set. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_mem_error_u { - bdrkreg_t md_mem_error_regval; - struct { - bdrkreg_t me_reserved_5 : 3; - bdrkreg_t me_address : 30; - bdrkreg_t me_reserved_4 : 7; - bdrkreg_t me_bad_syn : 8; - bdrkreg_t me_reserved_3 : 4; - bdrkreg_t me_read_ce : 2; - bdrkreg_t me_reserved_2 : 2; - bdrkreg_t me_write_uce : 2; - bdrkreg_t me_reserved_1 : 2; - bdrkreg_t me_read_uce : 2; - bdrkreg_t me_reserved : 1; - bdrkreg_t me_uce_diff_addr : 1; - } md_mem_error_fld_s; -} md_mem_error_u_t; - -#else - -typedef union md_mem_error_u { - bdrkreg_t md_mem_error_regval; - struct { - bdrkreg_t me_uce_diff_addr : 1; - bdrkreg_t me_reserved : 1; - bdrkreg_t me_read_uce : 2; - bdrkreg_t me_reserved_1 : 2; - bdrkreg_t me_write_uce : 2; - bdrkreg_t me_reserved_2 : 2; - bdrkreg_t me_read_ce : 2; - bdrkreg_t me_reserved_3 : 4; - bdrkreg_t me_bad_syn : 8; - bdrkreg_t me_reserved_4 : 7; - bdrkreg_t me_address : 30; - bdrkreg_t me_reserved_5 : 3; - } md_mem_error_fld_s; -} md_mem_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: Contains information on read memory errors (both * - * correctable and uncorrectable) and write memory errors (always * - * uncorrectable). The errors are prioritized as follows: * - * highest: uncorrectable read error (READ_UCE) * - * middle: write error (WRITE_UCE) * - * lowest: correctable read error (READ_CE) * - * Each type of error maintains a two-bit valid/overrun field * - * (READ_UCE, WRITE_UCE, or READ_CE). Bit 0 of each two-bit field * - * corresponds to the valid bit, and bit 1 of each two-bit field * - * corresponds to the overrun bit. * - * The rule for the valid bit is that it gets set whenever that error * - * occurs, regardless of whether a higher priority error has occurred. * - * The rule for the overrun bit is that it gets set whenever we are * - * unable to record the address information for this particular * - * error, due to a previous error of the same or higher priority. * - * Note that the syndrome and address information always corresponds * - * to the earliest, highest priority error. * - * Finally, the UCE_DIFF_ADDR bit is set whenever there have been * - * several uncorrectable errors, to different cache line addresses. * - * If all the UCEs were to the same cache line address, then * - * UCE_DIFF_ADDR will be 0. This allows the operating system to * - * detect the case where a UCE error is read exclusively, and then * - * written back by the processor. If the bit is 0, it indicates that * - * no information has been lost about UCEs on other cache lines. In * - * particular, partial writes do a read modify write of the cache * - * line. A UCE read error will be set when the cache line is read, * - * and a UCE write error will occur when the cache line is written * - * back, but the UCE_DIFF_ADDR will not be set. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_mem_error_clr_u { - bdrkreg_t md_mem_error_clr_regval; - struct { - bdrkreg_t mec_reserved_5 : 3; - bdrkreg_t mec_address : 30; - bdrkreg_t mec_reserved_4 : 7; - bdrkreg_t mec_bad_syn : 8; - bdrkreg_t mec_reserved_3 : 4; - bdrkreg_t mec_read_ce : 2; - bdrkreg_t mec_reserved_2 : 2; - bdrkreg_t mec_write_uce : 2; - bdrkreg_t mec_reserved_1 : 2; - bdrkreg_t mec_read_uce : 2; - bdrkreg_t mec_reserved : 1; - bdrkreg_t mec_uce_diff_addr : 1; - } md_mem_error_clr_fld_s; -} md_mem_error_clr_u_t; - -#else - -typedef union md_mem_error_clr_u { - bdrkreg_t md_mem_error_clr_regval; - struct { - bdrkreg_t mec_uce_diff_addr : 1; - bdrkreg_t mec_reserved : 1; - bdrkreg_t mec_read_uce : 2; - bdrkreg_t mec_reserved_1 : 2; - bdrkreg_t mec_write_uce : 2; - bdrkreg_t mec_reserved_2 : 2; - bdrkreg_t mec_read_ce : 2; - bdrkreg_t mec_reserved_3 : 4; - bdrkreg_t mec_bad_syn : 8; - bdrkreg_t mec_reserved_4 : 7; - bdrkreg_t mec_address : 30; - bdrkreg_t mec_reserved_5 : 3; - } md_mem_error_clr_fld_s; -} md_mem_error_clr_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains one-quarter of the error memory line failing BIST. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_bist_mb_err_data_0_u { - bdrkreg_t md_bist_mb_err_data_0_regval; - struct { - bdrkreg_t bmed0_mb_er_d : 36; - bdrkreg_t bmed0_reserved : 28; - } md_bist_mb_err_data_0_fld_s; -} md_bist_mb_err_data_0_u_t; - -#else - -typedef union md_bist_mb_err_data_0_u { - bdrkreg_t md_bist_mb_err_data_0_regval; - struct { - bdrkreg_t bmed0_reserved : 28; - bdrkreg_t bmed0_mb_er_d : 36; - } md_bist_mb_err_data_0_fld_s; -} md_bist_mb_err_data_0_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains one-quarter of the error memory line failing BIST. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_bist_mb_err_data_1_u { - bdrkreg_t md_bist_mb_err_data_1_regval; - struct { - bdrkreg_t bmed1_mb_er_d : 36; - bdrkreg_t bmed1_reserved : 28; - } md_bist_mb_err_data_1_fld_s; -} md_bist_mb_err_data_1_u_t; - -#else - -typedef union md_bist_mb_err_data_1_u { - bdrkreg_t md_bist_mb_err_data_1_regval; - struct { - bdrkreg_t bmed1_reserved : 28; - bdrkreg_t bmed1_mb_er_d : 36; - } md_bist_mb_err_data_1_fld_s; -} md_bist_mb_err_data_1_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains one-quarter of the error memory line failing BIST. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_bist_mb_err_data_2_u { - bdrkreg_t md_bist_mb_err_data_2_regval; - struct { - bdrkreg_t bmed2_mb_er_d : 36; - bdrkreg_t bmed2_reserved : 28; - } md_bist_mb_err_data_2_fld_s; -} md_bist_mb_err_data_2_u_t; - -#else - -typedef union md_bist_mb_err_data_2_u { - bdrkreg_t md_bist_mb_err_data_2_regval; - struct { - bdrkreg_t bmed2_reserved : 28; - bdrkreg_t bmed2_mb_er_d : 36; - } md_bist_mb_err_data_2_fld_s; -} md_bist_mb_err_data_2_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains one-quarter of the error memory line failing BIST. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_bist_mb_err_data_3_u { - bdrkreg_t md_bist_mb_err_data_3_regval; - struct { - bdrkreg_t bmed3_mb_er_d : 36; - bdrkreg_t bmed3_reserved : 28; - } md_bist_mb_err_data_3_fld_s; -} md_bist_mb_err_data_3_u_t; - -#else - -typedef union md_bist_mb_err_data_3_u { - bdrkreg_t md_bist_mb_err_data_3_regval; - struct { - bdrkreg_t bmed3_reserved : 28; - bdrkreg_t bmed3_mb_er_d : 36; - } md_bist_mb_err_data_3_fld_s; -} md_bist_mb_err_data_3_u_t; - -#endif - - - - -/************************************************************************ - * * - * Contains 1 bit that allow the selection of MB debug information * - * at the debug port (see the design specification for the available * - * debug information). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union md_mb_debug_u { - bdrkreg_t md_mb_debug_regval; - struct { - bdrkreg_t md_mb_debug_sel : 1; - bdrkreg_t md_reserved : 63; - } md_mb_debug_fld_s; -} md_mb_debug_u_t; - -#else - -typedef union md_mb_debug_u { - bdrkreg_t md_mb_debug_regval; - struct { - bdrkreg_t md_reserved : 63; - bdrkreg_t md_mb_debug_sel : 1; - } md_mb_debug_fld_s; -} md_mb_debug_u_t; - -#endif - - - - - - -#endif /* __ASSEMBLY__ */ - -/************************************************************************ - * * - * MAKE ALL ADDITIONS AFTER THIS LINE * - * * - ************************************************************************/ - - - - -#endif /* _ASM_IA64_SN_SN1_HUBMD_H */ diff --git a/include/asm-ia64/sn/sn1/hubmd_next.h b/include/asm-ia64/sn/sn1/hubmd_next.h deleted file mode 100644 index 263dc66e78f28..0000000000000 --- a/include/asm-ia64/sn/sn1/hubmd_next.h +++ /dev/null @@ -1,812 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_HUBMD_NEXT_H -#define _ASM_IA64_SN_SN1_HUBMD_NEXT_H - -/* XXX moved over from SN/SN0/hubmd.h -- each should be checked for SN1 */ -/* In fact, most of this stuff is wrong. Some is correct, such as - * MD_PAGE_SIZE and MD_PAGE_NUM_SHFT. - */ - -#define MD_PERF_COUNTERS 6 -#define MD_PERF_SETS 6 - -#define MD_SIZE_EMPTY 0 -#define MD_SIZE_64MB 1 -#define MD_SIZE_128MB 2 -#define MD_SIZE_256MB 3 -#define MD_SIZE_512MB 4 -#define MD_SIZE_1GB 5 - -#define MD_SIZE_BYTES(size) ((size) == 0 ? 0 : 0x2000000L << (size)) -#define MD_SIZE_MBYTES(size) ((size) == 0 ? 0 : 0x20 << (size)) -#define MD_NUM_ENABLED(_x) ((_x & 0x1) + ((_x >> 1) & 0x1) + \ - ((_x >> 2) & 0x1) + ((_x >> 3) & 0x1)) - - -/* Hardware page size and shift */ - -#define MD_PAGE_SIZE 16384 /* Page size in bytes */ -#define MD_PAGE_NUM_SHFT 14 /* Address to page number shift */ - -#define MMC_IO_PROT (UINT64_CAST 1 << 45) - -/* Register offsets from LOCAL_HUB or REMOTE_HUB */ -#define MD_PERF_SEL 0x210000 /* Select perf monitor events */ - -/* MD_MIG_VALUE_THRESH bit definitions */ - -#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63) -#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff) - -/* MD_MIG_CANDIDATE bit definitions */ - -#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63) -#define MD_MIG_CANDIDATE_VALID_SHFT 63 -#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30) -#define MD_MIG_CANDIDATE_TYPE_SHFT 30 -#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29) -#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29 -#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20) -#define MD_MIG_CANDIDATE_NODEID_SHFT 20 -#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff) - - -/* XXX protection and migration are completely revised on SN1. On - SN0, the reference count and protection fields were accessed in the - same word, but on SN1 they reside at different addresses. The - users of these macros will need to be rewritten. Also, the MD page - size is 16K on SN1 but 4K on SN0. */ - -/* Premium SIMM protection entry shifts and masks. */ - -#define MD_PPROT_SHFT 0 /* Prot. field */ -#define MD_PPROT_MASK 0xf -#define MD_PPROT_REFCNT_SHFT 5 /* Reference count */ -#define MD_PPROT_REFCNT_WIDTH 0x7ffff -#define MD_PPROT_REFCNT_MASK (MD_PPROT_REFCNT_WIDTH << 5) - -#define MD_PPROT_IO_SHFT 8 /* I/O Prot field */ - -/* Standard SIMM protection entry shifts and masks. */ - -#define MD_SPROT_SHFT 0 /* Prot. field */ -#define MD_SPROT_MASK 0xf -#define MD_SPROT_IO_SHFT 8 -#define MD_SPROT_REFCNT_SHFT 5 /* Reference count */ -#define MD_SPROT_REFCNT_WIDTH 0x7ff -#define MD_SPROT_REFCNT_MASK (MD_SPROT_REFCNT_WIDTH << 5) - -/* Migration modes used in protection entries */ - -#define MD_PROT_MIGMD_IREL (UINT64_CAST 0x3 << 3) -#define MD_PROT_MIGMD_IABS (UINT64_CAST 0x2 << 3) -#define MD_PROT_MIGMD_PREL (UINT64_CAST 0x1 << 3) -#define MD_PROT_MIGMD_OFF (UINT64_CAST 0x0 << 3) - -/* - * Operations on Memory/Directory DIMM control register - */ - -#define DIRTYPE_PREMIUM 1 -#define DIRTYPE_STANDARD 0 - -/* - * Operations on page migration count difference and absolute threshold - * registers - */ - -#define MD_MIG_VALUE_THRESH_GET(region) ( \ - REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \ - MD_MIG_VALUE_THRES_VALUE_MASK) - -#define MD_MIG_VALUE_THRESH_SET(region, value) ( \ - REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \ - MD_MIG_VALUE_THRES_VALID_MASK | (value))) - -#define MD_MIG_VALUE_THRESH_ENABLE(region) ( \ - REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \ - REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) \ - | MD_MIG_VALUE_THRES_VALID_MASK)) - -/* - * Operations on page migration candidate register - */ - -#define MD_MIG_CANDIDATE_GET(my_region_id) ( \ - REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR)) - -#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK) - -#define MD_MIG_CANDIDATE_NODEID(value) ( \ - ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT) - -#define MD_MIG_CANDIDATE_TYPE(value) ( \ - ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT) - -#define MD_MIG_CANDIDATE_VALID(value) ( \ - ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT) - -/* - * Macros to retrieve fields in the protection entry - */ - -/* for Premium SIMM */ -#define MD_PPROT_REFCNT_GET(value) ( \ - ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT) - -/* for Standard SIMM */ -#define MD_SPROT_REFCNT_GET(value) ( \ - ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT) - -#ifndef __ASSEMBLY__ -#ifdef LITTLE_ENDIAN - -typedef union md_perf_sel { - uint64_t perf_sel_reg; - struct { - uint64_t perf_sel : 3, - perf_en : 1, - perf_rsvd : 60; - } perf_sel_bits; -} md_perf_sel_t; - -#else - -typedef union md_perf_sel { - uint64_t perf_sel_reg; - struct { - uint64_t perf_rsvd : 60, - perf_en : 1, - perf_sel : 3; - } perf_sel_bits; -} md_perf_sel_t; - -#endif -#endif /* __ASSEMBLY__ */ - - -/* Like SN0, SN1 supports a mostly-flat address space with 8 - CPU-visible, evenly spaced, contiguous regions, or "software - banks". On SN1, software bank n begins at addresses n * 1GB, - 0 <= n < 8. - - Physically (and very unlike SN0), each SN1 node board contains 8 - dimm sockets, arranged as 4 "DIMM banks" of 2 dimms each. DIMM - size and width (x4/x8) is assigned per dimm bank. Each DIMM bank - consists of 2 "physical banks", one on the front sides of the 2 - DIMMs and the other on the back sides. Therefore a node has a - total of 8 ( = 4 * 2) physical banks. They are collectively - referred to as "locational banks", since the locational bank number - depends on the physical location of the DIMMs on the board. - - Dimm bank 0, Phys bank 0a (locational bank 0a) - Slot D0 ---------------------------------------------- - Dimm bank 0, Phys bank 1a (locational bank 1a) - - Dimm bank 1, Phys bank 0a (locational bank 2a) - Slot D1 ---------------------------------------------- - Dimm bank 1, Phys bank 1a (locational bank 3a) - - Dimm bank 2, Phys bank 0a (locational bank 4a) - Slot D2 ---------------------------------------------- - Dimm bank 2, Phys bank 1a (locational bank 5a) - - Dimm bank 3, Phys bank 0a (locational bank 6a) - Slot D3 ---------------------------------------------- - Dimm bank 3, Phys bank 1a (locational bank 7a) - - Dimm bank 0, Phys bank 0b (locational bank 0b) - Slot D4 ---------------------------------------------- - Dimm bank 0, Phys bank 1b (locational bank 1b) - - Dimm bank 1, Phys bank 0b (locational bank 2b) - Slot D5 ---------------------------------------------- - Dimm bank 1, Phys bank 1b (locational bank 3b) - - Dimm bank 2, Phys bank 0b (locational bank 4b) - Slot D6 ---------------------------------------------- - Dimm bank 2, Phys bank 1b (locational bank 5b) - - Dimm bank 3, Phys bank 0b (locational bank 6b) - Slot D7 ---------------------------------------------- - Dimm bank 3, Phys bank 1b (locational bank 7b) - - Since bank size is assigned per DIMM bank, each pair of locational - banks must have the same size. However, they may be - enabled/disabled individually. - - The locational banks map to the software banks via the dimm0_sel - field in MD_MEMORY_CONFIG. When the field is 0 (the usual case), - the mapping is direct: eg. locational bank 1 (dimm bank 0, - physical bank 1, which is the back side of the first DIMM pair) - corresponds to software bank 1, at node offset 1GB. More - generally, locational bank = software bank XOR dimm0_sel. - - All the PROM's data structures (promlog variables, klconfig, etc.) - track memory by the locational bank number. The kernel usually - tracks memory by the software bank number. - memsupport.c:slot_psize_compute() performs the mapping. - - (Note: the terms "locational bank" and "software bank" are not - offical in any way, but I've tried to make the PROM use them - consistently -- bjj.) - */ - -#define MD_MEM_BANKS 8 -#define MD_MEM_DIMM_BANKS 4 -#define MD_BANK_SHFT 30 /* log2(1 GB) */ -#define MD_BANK_MASK (UINT64_CAST 0x7 << 30) -#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT) /* 1 GB */ -#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT) -#define MD_BANK_GET(addr) (((addr) & MD_BANK_MASK) >> MD_BANK_SHFT) -#define MD_BANK_TO_DIMM_BANK(_b) (( (_b) >> 1) & 0x3) -#define MD_BANK_TO_PHYS_BANK(_b) (( (_b) >> 0) & 0x1) -#define MD_DIMM_BANK_GET(addr) MD_BANK_TO_DIMM_BANK(MD_BANK_GET(addr)) -#define MD_PHYS_BANK_GET(addr) MD_BANK_TO_PHYS_BANK(MD_BANK_GET(addr)) - - -/* Split an MD pointer (or message source & suppl. fields) into node, device */ - -#define MD_PTR_NODE_SHFT 3 -#define MD_PTR_DEVICE_MASK 0x7 -#define MD_PTR_SUBNODE0_MASK 0x1 -#define MD_PTR_SUBNODE1_MASK 0x4 - - -/********************************************************************** - - Backdoor protection and page counter structures - -**********************************************************************/ - -/* Protection entries and page counters are interleaved at 4 separate - addresses, 0x10 apart. Software must read/write all four. */ - -#define BD_ITLV_COUNT 4 -#define BD_ITLV_STRIDE 0x10 - -/* Protection entries */ - -/* (these macros work for standard (_rgn < 32) or premium DIMMs) */ -#define MD_PROT_SHFT(_rgn, _io) ((((_rgn) & 0x20) >> 2 | \ - ((_rgn) & 0x01) << 2 | \ - ((_io) & 0x1) << 1) * 8) -#define MD_PROT_MASK(_rgn, _io) (0xff << MD_PROT_SHFT(_rgn, _io)) -#define MD_PROT_GET(_val, _rgn, _io) \ - (((_val) & MD_PROT_MASK(_rgn, _io)) >> MD_PROT_SHFT(_rgn, _io)) - -/* Protection field values */ - -#define MD_PROT_RW (UINT64_CAST 0xff) -#define MD_PROT_RO (UINT64_CAST 0x0f) -#define MD_PROT_NO (UINT64_CAST 0x00) - - - - -/********************************************************************** - - Directory format structures - -***********************************************************************/ - -#ifndef __ASSEMBLY__ - -/* Standard Directory Entries */ - -#ifdef LITTLE_ENDIAN - -struct md_sdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */ - bdrkreg_t sdp_format : 2; - bdrkreg_t sdp_state : 3; - bdrkreg_t sdp_priority : 3; - bdrkreg_t sdp_pointer1 : 8; - bdrkreg_t sdp_ecc : 6; - bdrkreg_t sdp_locprot : 1; - bdrkreg_t sdp_reserved : 1; - bdrkreg_t sdp_crit_word_off : 3; - bdrkreg_t sdp_pointer2 : 5; - bdrkreg_t sdp_fill : 32; -}; - -#else - -struct md_sdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */ - bdrkreg_t sdp_fill : 32; - bdrkreg_t sdp_pointer2 : 5; - bdrkreg_t sdp_crit_word_off : 3; - bdrkreg_t sdp_reserved : 1; - bdrkreg_t sdp_locprot : 1; - bdrkreg_t sdp_ecc : 6; - bdrkreg_t sdp_pointer1 : 8; - bdrkreg_t sdp_priority : 3; - bdrkreg_t sdp_state : 3; - bdrkreg_t sdp_format : 2; -}; - -#endif - -#ifdef LITTLE_ENDIAN - -struct md_sdir_fine_fmt { /* shared (fine) */ - bdrkreg_t sdf_format : 2; - bdrkreg_t sdf_tag1 : 3; - bdrkreg_t sdf_tag2 : 3; - bdrkreg_t sdf_vector1 : 8; - bdrkreg_t sdf_ecc : 6; - bdrkreg_t sdf_locprot : 1; - bdrkreg_t sdf_tag2valid : 1; - bdrkreg_t sdf_vector2 : 8; - bdrkreg_t sdf_fill : 32; -}; - -#else - -struct md_sdir_fine_fmt { /* shared (fine) */ - bdrkreg_t sdf_fill : 32; - bdrkreg_t sdf_vector2 : 8; - bdrkreg_t sdf_tag2valid : 1; - bdrkreg_t sdf_locprot : 1; - bdrkreg_t sdf_ecc : 6; - bdrkreg_t sdf_vector1 : 8; - bdrkreg_t sdf_tag2 : 3; - bdrkreg_t sdf_tag1 : 3; - bdrkreg_t sdf_format : 2; -}; - -#endif - -#ifdef LITTLE_ENDIAN - -struct md_sdir_coarse_fmt { /* shared (coarse) */ - bdrkreg_t sdc_format : 2; - bdrkreg_t sdc_reserved_1 : 6; - bdrkreg_t sdc_vector_a : 8; - bdrkreg_t sdc_ecc : 6; - bdrkreg_t sdc_locprot : 1; - bdrkreg_t sdc_reserved : 1; - bdrkreg_t sdc_vector_b : 8; - bdrkreg_t sdc_fill : 32; -}; - -#else - -struct md_sdir_coarse_fmt { /* shared (coarse) */ - bdrkreg_t sdc_fill : 32; - bdrkreg_t sdc_vector_b : 8; - bdrkreg_t sdc_reserved : 1; - bdrkreg_t sdc_locprot : 1; - bdrkreg_t sdc_ecc : 6; - bdrkreg_t sdc_vector_a : 8; - bdrkreg_t sdc_reserved_1 : 6; - bdrkreg_t sdc_format : 2; -}; - -#endif - -typedef union md_sdir { - /* The 32 bits of standard directory, in bits 31:0 */ - uint64_t sd_val; - struct md_sdir_pointer_fmt sdp_fmt; - struct md_sdir_fine_fmt sdf_fmt; - struct md_sdir_coarse_fmt sdc_fmt; -} md_sdir_t; - - -/* Premium Directory Entries */ - -#ifdef LITTLE_ENDIAN - -struct md_pdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */ - bdrkreg_t pdp_format : 2; - bdrkreg_t pdp_state : 3; - bdrkreg_t pdp_priority : 3; - bdrkreg_t pdp_pointer1_a : 8; - bdrkreg_t pdp_reserved_4 : 6; - bdrkreg_t pdp_pointer1_b : 3; - bdrkreg_t pdp_reserved_3 : 7; - bdrkreg_t pdp_ecc_a : 6; - bdrkreg_t pdp_locprot : 1; - bdrkreg_t pdp_reserved_2 : 1; - bdrkreg_t pdp_crit_word_off : 3; - bdrkreg_t pdp_pointer2_a : 5; - bdrkreg_t pdp_ecc_b : 1; - bdrkreg_t pdp_reserved_1 : 5; - bdrkreg_t pdp_pointer2_b : 3; - bdrkreg_t pdp_reserved : 7; -}; - -#else - -struct md_pdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */ - bdrkreg_t pdp_reserved : 7; - bdrkreg_t pdp_pointer2_b : 3; - bdrkreg_t pdp_reserved_1 : 5; - bdrkreg_t pdp_ecc_b : 1; - bdrkreg_t pdp_pointer2_a : 5; - bdrkreg_t pdp_crit_word_off : 3; - bdrkreg_t pdp_reserved_2 : 1; - bdrkreg_t pdp_locprot : 1; - bdrkreg_t pdp_ecc_a : 6; - bdrkreg_t pdp_reserved_3 : 7; - bdrkreg_t pdp_pointer1_b : 3; - bdrkreg_t pdp_reserved_4 : 6; - bdrkreg_t pdp_pointer1_a : 8; - bdrkreg_t pdp_priority : 3; - bdrkreg_t pdp_state : 3; - bdrkreg_t pdp_format : 2; -}; - -#endif - -#ifdef LITTLE_ENDIAN - -struct md_pdir_fine_fmt { /* shared (fine) */ - bdrkreg_t pdf_format : 2; - bdrkreg_t pdf_tag1_a : 3; - bdrkreg_t pdf_tag2_a : 3; - bdrkreg_t pdf_vector1_a : 8; - bdrkreg_t pdf_reserved_1 : 6; - bdrkreg_t pdf_tag1_b : 2; - bdrkreg_t pdf_vector1_b : 8; - bdrkreg_t pdf_ecc_a : 6; - bdrkreg_t pdf_locprot : 1; - bdrkreg_t pdf_tag2valid : 1; - bdrkreg_t pdf_vector2_a : 8; - bdrkreg_t pdf_ecc_b : 1; - bdrkreg_t pdf_reserved : 5; - bdrkreg_t pdf_tag2_b : 2; - bdrkreg_t pdf_vector2_b : 8; -}; - -#else - -struct md_pdir_fine_fmt { /* shared (fine) */ - bdrkreg_t pdf_vector2_b : 8; - bdrkreg_t pdf_tag2_b : 2; - bdrkreg_t pdf_reserved : 5; - bdrkreg_t pdf_ecc_b : 1; - bdrkreg_t pdf_vector2_a : 8; - bdrkreg_t pdf_tag2valid : 1; - bdrkreg_t pdf_locprot : 1; - bdrkreg_t pdf_ecc_a : 6; - bdrkreg_t pdf_vector1_b : 8; - bdrkreg_t pdf_tag1_b : 2; - bdrkreg_t pdf_reserved_1 : 6; - bdrkreg_t pdf_vector1_a : 8; - bdrkreg_t pdf_tag2_a : 3; - bdrkreg_t pdf_tag1_a : 3; - bdrkreg_t pdf_format : 2; -}; - -#endif - -#ifdef LITTLE_ENDIAN - -struct md_pdir_sparse_fmt { /* shared (sparse) */ - bdrkreg_t pds_format : 2; - bdrkreg_t pds_column_a : 6; - bdrkreg_t pds_row_a : 8; - bdrkreg_t pds_column_b : 16; - bdrkreg_t pds_ecc_a : 6; - bdrkreg_t pds_locprot : 1; - bdrkreg_t pds_reserved_1 : 1; - bdrkreg_t pds_row_b : 8; - bdrkreg_t pds_ecc_b : 1; - bdrkreg_t pds_column_c : 10; - bdrkreg_t pds_reserved : 5; -}; - -#else - -struct md_pdir_sparse_fmt { /* shared (sparse) */ - bdrkreg_t pds_reserved : 5; - bdrkreg_t pds_column_c : 10; - bdrkreg_t pds_ecc_b : 1; - bdrkreg_t pds_row_b : 8; - bdrkreg_t pds_reserved_1 : 1; - bdrkreg_t pds_locprot : 1; - bdrkreg_t pds_ecc_a : 6; - bdrkreg_t pds_column_b : 16; - bdrkreg_t pds_row_a : 8; - bdrkreg_t pds_column_a : 6; - bdrkreg_t pds_format : 2; -}; - -#endif - -typedef union md_pdir { - /* The 64 bits of premium directory */ - uint64_t pd_val; - struct md_pdir_pointer_fmt pdp_fmt; - struct md_pdir_fine_fmt pdf_fmt; - struct md_pdir_sparse_fmt pds_fmt; -} md_pdir_t; - -#endif /* __ASSEMBLY__ */ - - -/********************************************************************** - - The defines for backdoor directory and backdoor ECC. - -***********************************************************************/ - -/* Directory formats, for each format's "format" field */ - -#define MD_FORMAT_UNOWNED (UINT64_CAST 0x0) /* 00 */ -#define MD_FORMAT_POINTER (UINT64_CAST 0x1) /* 01 */ -#define MD_FORMAT_SHFINE (UINT64_CAST 0x2) /* 10 */ -#define MD_FORMAT_SHCOARSE (UINT64_CAST 0x3) /* 11 */ - /* Shared coarse (standard) and shared sparse (premium) both use fmt 0x3 */ - - -/* - * Cacheline state values. - * - * These are really *software* notions of the "state" of a cacheline; but the - * actual values have been carefully chosen to align with some hardware values! - * The MD_FMT_ST_TO_STATE macro is used to convert from hardware format/state - * pairs in the directory entried into one of these cacheline state values. - */ - -#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x0) /* ptr format, hw-defined */ -#define MD_DIR_UNOWNED (UINT64_CAST 0x1) /* format=0 */ -#define MD_DIR_SHARED (UINT64_CAST 0x2) /* format=2,3 */ -#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x4) /* ptr format, hw-defined */ -#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x5) /* ptr format, hw-defined */ -#define MD_DIR_WAIT (UINT64_CAST 0x6) /* ptr format, hw-defined */ -#define MD_DIR_POISONED (UINT64_CAST 0x7) /* ptr format, hw-defined */ - -#ifndef __ASSEMBLY__ - -/* Convert format and state fields into a single "cacheline state" value, defined above */ - -#define MD_FMT_ST_TO_STATE(fmt, state) \ - ((fmt) == MD_FORMAT_POINTER ? (state) : \ - (fmt) == MD_FORMAT_UNOWNED ? MD_DIR_UNOWNED : \ - MD_DIR_SHARED) -#define MD_DIR_STATE(x) MD_FMT_ST_TO_STATE(MD_DIR_FORMAT(x), MD_DIR_STVAL(x)) - -#endif /* __ASSEMBLY__ */ - - - -/* Directory field shifts and masks */ - -/* Standard */ - -#define MD_SDIR_FORMAT_SHFT 0 /* All formats */ -#define MD_SDIR_FORMAT_MASK (0x3 << 0) -#define MD_SDIR_STATE_SHFT 2 /* Pointer fmt. only */ -#define MD_SDIR_STATE_MASK (0x7 << 2) - -/* Premium */ - -#define MD_PDIR_FORMAT_SHFT 0 /* All formats */ -#define MD_PDIR_FORMAT_MASK (0x3 << 0) -#define MD_PDIR_STATE_SHFT 2 /* Pointer fmt. only */ -#define MD_PDIR_STATE_MASK (0x7 << 2) - -/* Generic */ - -#define MD_FORMAT_SHFT 0 /* All formats */ -#define MD_FORMAT_MASK (0x3 << 0) -#define MD_STATE_SHFT 2 /* Pointer fmt. only */ -#define MD_STATE_MASK (0x7 << 2) - - -/* Special shifts to reconstruct fields from the _a and _b parts */ - -/* Standard: only shared coarse has split fields */ - -#define MD_SDC_VECTORB_SHFT 8 /* eg: sdc_vector_a is 8 bits */ - -/* Premium: pointer, shared fine, shared sparse */ - -#define MD_PDP_POINTER1A_MASK 0xFF -#define MD_PDP_POINTER1B_SHFT 8 -#define MD_PDP_POINTER2B_SHFT 5 -#define MD_PDP_ECCB_SHFT 6 - -#define MD_PDF_VECTOR1B_SHFT 8 -#define MD_PDF_VECTOR2B_SHFT 8 -#define MD_PDF_TAG1B_SHFT 3 -#define MD_PDF_TAG2B_SHFT 3 -#define MD_PDF_ECC_SHFT 6 - -#define MD_PDS_ROWB_SHFT 8 -#define MD_PDS_COLUMNB_SHFT 6 -#define MD_PDS_COLUMNC_SHFT (MD_PDS_COLUMNB_SHFT + 16) -#define MD_PDS_ECC_SHFT 6 - - - -/* - * Directory/protection/counter initialization values, premium and standard - */ - -#define MD_PDIR_INIT 0 -#define MD_PDIR_INIT_CNT 0 -#define MD_PDIR_INIT_PROT 0 - -#define MD_SDIR_INIT 0 -#define MD_SDIR_INIT_CNT 0 -#define MD_SDIR_INIT_PROT 0 - -#define MD_PDIR_MASK 0xffffffffffffffff -#define MD_SDIR_MASK 0xffffffff - -/* When premium mode is on for probing but standard directory memory - is installed, the valid directory bits depend on the phys. bank */ -#define MD_PDIR_PROBE_MASK(pb) 0xffffffffffffffff -#define MD_SDIR_PROBE_MASK(pb) (0xffff0000ffff << ((pb) ? 16 : 0)) - - -/* - * Misc. field extractions and conversions - */ - -/* Convert an MD pointer (or message source, supplemental fields) */ - -#define MD_PTR_NODE(x) ((x) >> MD_PTR_NODE_SHFT) -#define MD_PTR_DEVICE(x) ((x) & MD_PTR_DEVICE_MASK) -#define MD_PTR_SLICE(x) (((x) & MD_PTR_SUBNODE0_MASK) | \ - ((x) & MD_PTR_SUBNODE1_MASK) >> 1) -#define MD_PTR_OWNER_CPU(x) (! ((x) & 2)) -#define MD_PTR_OWNER_IO(x) ((x) & 2) - -/* Extract format and raw state from a directory entry */ - -#define MD_DIR_FORMAT(x) ((x) >> MD_SDIR_FORMAT_SHFT & \ - MD_SDIR_FORMAT_MASK >> MD_SDIR_FORMAT_SHFT) -#define MD_DIR_STVAL(x) ((x) >> MD_SDIR_STATE_SHFT & \ - MD_SDIR_STATE_MASK >> MD_SDIR_STATE_SHFT) - -/* Mask & Shift to get HSPEC_ADDR from MD DIR_ERROR register */ -#define ERROR_ADDR_SHFT 3 -#define ERROR_HSPEC_SHFT 3 -#define DIR_ERR_HSPEC_MASK 0x1fffffff8 - -/* - * DIR_ERR* and MEM_ERR* defines are used to avoid ugly - * #ifdefs for SN0 and SN1 in memerror.c code. See SN0/hubmd.h - * for corresponding SN0 definitions. - */ -#define md_dir_error_t md_dir_error_u_t -#define md_mem_error_t md_mem_error_u_t -#define derr_reg md_dir_error_regval -#define merr_reg md_mem_error_regval - -#define DIR_ERR_UCE_VALID dir_err.md_dir_error_fld_s.de_uce_valid -#define DIR_ERR_AE_VALID dir_err.md_dir_error_fld_s.de_ae_valid -#define DIR_ERR_BAD_SYN dir_err.md_dir_error_fld_s.de_bad_syn -#define DIR_ERR_CE_OVERRUN dir_err.md_dir_error_fld_s.de_ce_overrun -#define MEM_ERR_ADDRESS mem_err.md_mem_error_fld_s.me_address - /* BRINGUP Can the overrun bit be set without the valid bit? */ -#define MEM_ERR_CE_OVERRUN (mem_err.md_mem_error_fld_s.me_read_ce >> 1) -#define MEM_ERR_BAD_SYN mem_err.md_mem_error_fld_s.me_bad_syn -#define MEM_ERR_UCE_VALID (mem_err.md_mem_error_fld_s.me_read_uce & 1) - - - -/********************************************************************* - - We have the shift and masks of various fields defined below. - - *********************************************************************/ - -/* MD_REFRESH_CONTROL fields */ - -#define MRC_ENABLE_SHFT 63 -#define MRC_ENABLE_MASK (UINT64_CAST 1 << 63) -#define MRC_ENABLE (UINT64_CAST 1 << 63) -#define MRC_COUNTER_SHFT 12 -#define MRC_COUNTER_MASK (UINT64_CAST 0xfff << 12) -#define MRC_CNT_THRESH_MASK 0xfff -#define MRC_RESET_DEFAULTS (UINT64_CAST 0x800) - -/* MD_DIR_CONFIG fields */ - -#define MDC_DIR_PREMIUM (UINT64_CAST 1 << 0) -#define MDC_IGNORE_ECC_SHFT 1 -#define MDC_IGNORE_ECC_MASK (UINT64_CAST 1 << 1) - -/* MD_MEMORY_CONFIG fields */ - -#define MMC_RP_CONFIG_SHFT 61 -#define MMC_RP_CONFIG_MASK (UINT64_CAST 1 << 61) -#define MMC_RCD_CONFIG_SHFT 60 -#define MMC_RCD_CONFIG_MASK (UINT64_CAST 1 << 60) -#define MMC_MB_NEG_EDGE_SHFT 56 -#define MMC_MB_NEG_EDGE_MASK (UINT64_CAST 0x7 << 56) -#define MMC_SAMPLE_TIME_SHFT 52 -#define MMC_SAMPLE_TIME_MASK (UINT64_CAST 0x3 << 52) -#define MMC_DELAY_MUX_SEL_SHFT 50 -#define MMC_DELAY_MUX_SEL_MASK (UINT64_CAST 0x3 << 50) -#define MMC_PHASE_DELAY_SHFT 49 -#define MMC_PHASE_DELAY_MASK (UINT64_CAST 1 << 49) -#define MMC_DB_NEG_EDGE_SHFT 48 -#define MMC_DB_NEG_EDGE_MASK (UINT64_CAST 1 << 48) -#define MMC_CPU_PROT_IGNORE_SHFT 47 -#define MMC_CPU_PROT_IGNORE_MASK (UINT64_CAST 1 << 47) -#define MMC_IO_PROT_IGNORE_SHFT 46 -#define MMC_IO_PROT_IGNORE_MASK (UINT64_CAST 1 << 46) -#define MMC_IO_PROT_EN_SHFT 45 -#define MMC_IO_PROT_EN_MASK (UINT64_CAST 1 << 45) -#define MMC_CC_ENABLE_SHFT 44 -#define MMC_CC_ENABLE_MASK (UINT64_CAST 1 << 44) -#define MMC_DIMM0_SEL_SHFT 32 -#define MMC_DIMM0_SEL_MASK (UINT64_CAST 0x3 << 32) -#define MMC_DIMM_SIZE_SHFT(_dimm) ((_dimm << 3) + 4) -#define MMC_DIMM_SIZE_MASK(_dimm) (UINT64_CAST 0xf << MMC_DIMM_SIZE_SHFT(_dimm)) -#define MMC_DIMM_WIDTH_SHFT(_dimm) ((_dimm << 3) + 3) -#define MMC_DIMM_WIDTH_MASK(_dimm) (UINT64_CAST 0x1 << MMC_DIMM_WIDTH_SHFT(_dimm)) -#define MMC_DIMM_BANKS_SHFT(_dimm) (_dimm << 3) -#define MMC_DIMM_BANKS_MASK(_dimm) (UINT64_CAST 0x3 << MMC_DIMM_BANKS_SHFT(_dimm)) -#define MMC_BANK_ALL_MASK 0xffffffffLL -/* Default values for write-only bits in MD_MEMORY_CONFIG */ -#define MMC_DEFAULT_BITS (UINT64_CAST 0x7 << MMC_MB_NEG_EDGE_SHFT) - -/* MD_MB_ECC_CONFIG fields */ - -#define MEC_IGNORE_ECC (UINT64_CAST 0x1 << 0) - -/* MD_BIST_DATA fields */ - -#define MBD_BIST_WRITE (UINT64_CAST 1 << 7) -#define MBD_BIST_CYCLE (UINT64_CAST 1 << 6) -#define MBD_BIST_BYTE (UINT64_CAST 1 << 5) -#define MBD_BIST_NIBBLE (UINT64_CAST 1 << 4) -#define MBD_BIST_DATA_MASK 0xf - -/* MD_BIST_CTL fields */ - -#define MBC_DIMM_SHFT 5 -#define MBC_DIMM_MASK (UINT64_CAST 0x3 << 5) -#define MBC_BANK_SHFT 4 -#define MBC_BANK_MASK (UINT64_CAST 0x1 << 4) -#define MBC_BIST_RESET (UINT64_CAST 0x1 << 2) -#define MBC_BIST_STOP (UINT64_CAST 0x1 << 1) -#define MBC_BIST_START (UINT64_CAST 0x1 << 0) - -#define MBC_GO(dimm, bank) \ - (((dimm) << MBC_DIMM_SHFT) & MBC_DIMM_MASK | \ - ((bank) << MBC_BANK_SHFT) & MBC_BANK_MASK | \ - MBC_BIST_START) - -/* MD_BIST_STATUS fields */ - -#define MBS_BIST_DONE (UINT64_CAST 0X1 << 1) -#define MBS_BIST_PASSED (UINT64_CAST 0X1 << 0) - -/* MD_JUNK_BUS_TIMING fields */ - -#define MJT_SYNERGY_ENABLE_SHFT 40 -#define MJT_SYNERGY_ENABLE_MASK (UINT64_CAST 0Xff << MJT_SYNERGY_ENABLE_SHFT) -#define MJT_SYNERGY_SETUP_SHFT 32 -#define MJT_SYNERGY_SETUP_MASK (UINT64_CAST 0Xff << MJT_SYNERGY_SETUP_SHFT) -#define MJT_UART_ENABLE_SHFT 24 -#define MJT_UART_ENABLE_MASK (UINT64_CAST 0Xff << MJT_UART_ENABLE_SHFT) -#define MJT_UART_SETUP_SHFT 16 -#define MJT_UART_SETUP_MASK (UINT64_CAST 0Xff << MJT_UART_SETUP_SHFT) -#define MJT_FPROM_ENABLE_SHFT 8 -#define MJT_FPROM_ENABLE_MASK (UINT64_CAST 0Xff << MJT_FPROM_ENABLE_SHFT) -#define MJT_FPROM_SETUP_SHFT 0 -#define MJT_FPROM_SETUP_MASK (UINT64_CAST 0Xff << MJT_FPROM_SETUP_SHFT) - -#define MEM_ERROR_VALID_CE 1 - - -/* MD_FANDOP_CAC_STAT0, MD_FANDOP_CAC_STAT1 addr field shift */ - -#define MFC_ADDR_SHFT 6 - -#endif /* _ASM_IA64_SN_SN1_HUBMD_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hubni.h b/include/asm-ia64/sn/sn1/hubni.h deleted file mode 100644 index 6bfc241fac8ff..0000000000000 --- a/include/asm-ia64/sn/sn1/hubni.h +++ /dev/null @@ -1,1781 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_HUBNI_H -#define _ASM_IA64_SN_SN1_HUBNI_H - - -/************************************************************************ - * * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * - * * - * This file is created by an automated script. Any (minimal) changes * - * made manually to this file should be made with care. * - * * - * MAKE ALL ADDITIONS TO THE END OF THIS FILE * - * * - ************************************************************************/ - -#define NI_PORT_STATUS 0x00680000 /* LLP Status */ - - - -#define NI_PORT_RESET 0x00680008 /* - * Reset the Network - * Interface - */ - - - -#define NI_RESET_ENABLE 0x00680010 /* Warm Reset Enable */ - - - -#define NI_DIAG_PARMS 0x00680018 /* - * Diagnostic - * Parameters - */ - - - -#define NI_CHANNEL_CONTROL 0x00680020 /* - * Virtual channel - * control - */ - - - -#define NI_CHANNEL_TEST 0x00680028 /* LLP Test Control. */ - - - -#define NI_PORT_PARMS 0x00680030 /* LLP Parameters */ - - - -#define NI_CHANNEL_AGE 0x00680038 /* - * Network age - * injection control - */ - - - -#define NI_PORT_ERRORS 0x00680100 /* Errors */ - - - -#define NI_PORT_HEADER_A 0x00680108 /* - * Error Header first - * half - */ - - - -#define NI_PORT_HEADER_B 0x00680110 /* - * Error Header second - * half - */ - - - -#define NI_PORT_SIDEBAND 0x00680118 /* Error Sideband */ - - - -#define NI_PORT_ERROR_CLEAR 0x00680120 /* - * Clear the Error - * bits - */ - - - -#define NI_LOCAL_TABLE_0 0x00681000 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_1 0x00681008 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_2 0x00681010 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_3 0x00681018 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_4 0x00681020 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_5 0x00681028 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_6 0x00681030 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_7 0x00681038 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_8 0x00681040 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_9 0x00681048 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_10 0x00681050 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_11 0x00681058 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_12 0x00681060 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_13 0x00681068 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_14 0x00681070 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_15 0x00681078 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_16 0x00681080 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_17 0x00681088 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_18 0x00681090 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_19 0x00681098 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_20 0x006810A0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_21 0x006810A8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_22 0x006810B0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_23 0x006810B8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_24 0x006810C0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_25 0x006810C8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_26 0x006810D0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_27 0x006810D8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_28 0x006810E0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_29 0x006810E8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_30 0x006810F0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_31 0x006810F8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_32 0x00681100 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_33 0x00681108 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_34 0x00681110 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_35 0x00681118 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_36 0x00681120 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_37 0x00681128 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_38 0x00681130 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_39 0x00681138 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_40 0x00681140 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_41 0x00681148 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_42 0x00681150 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_43 0x00681158 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_44 0x00681160 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_45 0x00681168 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_46 0x00681170 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_47 0x00681178 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_48 0x00681180 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_49 0x00681188 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_50 0x00681190 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_51 0x00681198 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_52 0x006811A0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_53 0x006811A8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_54 0x006811B0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_55 0x006811B8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_56 0x006811C0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_57 0x006811C8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_58 0x006811D0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_59 0x006811D8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_60 0x006811E0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_61 0x006811E8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_62 0x006811F0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_63 0x006811F8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_64 0x00681200 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_65 0x00681208 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_66 0x00681210 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_67 0x00681218 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_68 0x00681220 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_69 0x00681228 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_70 0x00681230 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_71 0x00681238 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_72 0x00681240 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_73 0x00681248 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_74 0x00681250 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_75 0x00681258 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_76 0x00681260 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_77 0x00681268 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_78 0x00681270 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_79 0x00681278 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_80 0x00681280 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_81 0x00681288 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_82 0x00681290 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_83 0x00681298 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_84 0x006812A0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_85 0x006812A8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_86 0x006812B0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_87 0x006812B8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_88 0x006812C0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_89 0x006812C8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_90 0x006812D0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_91 0x006812D8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_92 0x006812E0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_93 0x006812E8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_94 0x006812F0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_95 0x006812F8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_96 0x00681300 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_97 0x00681308 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_98 0x00681310 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_99 0x00681318 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_100 0x00681320 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_101 0x00681328 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_102 0x00681330 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_103 0x00681338 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_104 0x00681340 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_105 0x00681348 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_106 0x00681350 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_107 0x00681358 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_108 0x00681360 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_109 0x00681368 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_110 0x00681370 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_111 0x00681378 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_112 0x00681380 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_113 0x00681388 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_114 0x00681390 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_115 0x00681398 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_116 0x006813A0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_117 0x006813A8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_118 0x006813B0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_119 0x006813B8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_120 0x006813C0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_121 0x006813C8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_122 0x006813D0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_123 0x006813D8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_124 0x006813E0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_125 0x006813E8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_126 0x006813F0 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_LOCAL_TABLE_127 0x006813F8 /* - * Base of Local - * Mapping Table 0-127 - */ - - - -#define NI_GLOBAL_TABLE 0x00682000 /* - * Base of Global - * Mapping Table - */ - - - - - -#ifndef __ASSEMBLY__ - -/************************************************************************ - * * - * This register describes the LLP status. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_port_status_u { - bdrkreg_t ni_port_status_regval; - struct { - bdrkreg_t ps_port_status : 2; - bdrkreg_t ps_remote_power : 1; - bdrkreg_t ps_rsvd : 61; - } ni_port_status_fld_s; -} ni_port_status_u_t; - -#else - -typedef union ni_port_status_u { - bdrkreg_t ni_port_status_regval; - struct { - bdrkreg_t ps_rsvd : 61; - bdrkreg_t ps_remote_power : 1; - bdrkreg_t ps_port_status : 2; - } ni_port_status_fld_s; -} ni_port_status_u_t; - -#endif - - - - -/************************************************************************ - * * - * Writing this register issues a reset to the network interface. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_port_reset_u { - bdrkreg_t ni_port_reset_regval; - struct { - bdrkreg_t pr_link_reset_out : 1; - bdrkreg_t pr_port_reset : 1; - bdrkreg_t pr_local_reset : 1; - bdrkreg_t pr_rsvd : 61; - } ni_port_reset_fld_s; -} ni_port_reset_u_t; - -#else - -typedef union ni_port_reset_u { - bdrkreg_t ni_port_reset_regval; - struct { - bdrkreg_t pr_rsvd : 61; - bdrkreg_t pr_local_reset : 1; - bdrkreg_t pr_port_reset : 1; - bdrkreg_t pr_link_reset_out : 1; - } ni_port_reset_fld_s; -} ni_port_reset_u_t; - -#endif - - - -/************************************************************************ - * * - * This register contains the warm reset enable bit. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_reset_enable_u { - bdrkreg_t ni_reset_enable_regval; - struct { - bdrkreg_t re_reset_ok : 1; - bdrkreg_t re_rsvd : 63; - } ni_reset_enable_fld_s; -} ni_reset_enable_u_t; - -#else - -typedef union ni_reset_enable_u { - bdrkreg_t ni_reset_enable_regval; - struct { - bdrkreg_t re_rsvd : 63; - bdrkreg_t re_reset_ok : 1; - } ni_reset_enable_fld_s; -} ni_reset_enable_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains parameters for diagnostics. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_diag_parms_u { - bdrkreg_t ni_diag_parms_regval; - struct { - bdrkreg_t dp_send_data_error : 1; - bdrkreg_t dp_port_disable : 1; - bdrkreg_t dp_send_err_off : 1; - bdrkreg_t dp_rsvd : 61; - } ni_diag_parms_fld_s; -} ni_diag_parms_u_t; - -#else - -typedef union ni_diag_parms_u { - bdrkreg_t ni_diag_parms_regval; - struct { - bdrkreg_t dp_rsvd : 61; - bdrkreg_t dp_send_err_off : 1; - bdrkreg_t dp_port_disable : 1; - bdrkreg_t dp_send_data_error : 1; - } ni_diag_parms_fld_s; -} ni_diag_parms_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the virtual channel selection control for * - * outgoing messages from the Bedrock. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_channel_control_u { - bdrkreg_t ni_channel_control_regval; - struct { - bdrkreg_t cc_vch_one_request : 1; - bdrkreg_t cc_vch_two_request : 1; - bdrkreg_t cc_vch_nine_request : 1; - bdrkreg_t cc_vch_vector_request : 1; - bdrkreg_t cc_vch_one_reply : 1; - bdrkreg_t cc_vch_two_reply : 1; - bdrkreg_t cc_vch_nine_reply : 1; - bdrkreg_t cc_vch_vector_reply : 1; - bdrkreg_t cc_send_vch_sel : 1; - bdrkreg_t cc_rsvd : 55; - } ni_channel_control_fld_s; -} ni_channel_control_u_t; - -#else - -typedef union ni_channel_control_u { - bdrkreg_t ni_channel_control_regval; - struct { - bdrkreg_t cc_rsvd : 55; - bdrkreg_t cc_send_vch_sel : 1; - bdrkreg_t cc_vch_vector_reply : 1; - bdrkreg_t cc_vch_nine_reply : 1; - bdrkreg_t cc_vch_two_reply : 1; - bdrkreg_t cc_vch_one_reply : 1; - bdrkreg_t cc_vch_vector_request : 1; - bdrkreg_t cc_vch_nine_request : 1; - bdrkreg_t cc_vch_two_request : 1; - bdrkreg_t cc_vch_one_request : 1; - } ni_channel_control_fld_s; -} ni_channel_control_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register allows access to the LLP test logic. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_channel_test_u { - bdrkreg_t ni_channel_test_regval; - struct { - bdrkreg_t ct_testseed : 20; - bdrkreg_t ct_testmask : 8; - bdrkreg_t ct_testdata : 20; - bdrkreg_t ct_testvalid : 1; - bdrkreg_t ct_testcberr : 1; - bdrkreg_t ct_testflit : 3; - bdrkreg_t ct_testclear : 1; - bdrkreg_t ct_testerrcapture : 1; - bdrkreg_t ct_rsvd : 9; - } ni_channel_test_fld_s; -} ni_channel_test_u_t; - -#else - -typedef union ni_channel_test_u { - bdrkreg_t ni_channel_test_regval; - struct { - bdrkreg_t ct_rsvd : 9; - bdrkreg_t ct_testerrcapture : 1; - bdrkreg_t ct_testclear : 1; - bdrkreg_t ct_testflit : 3; - bdrkreg_t ct_testcberr : 1; - bdrkreg_t ct_testvalid : 1; - bdrkreg_t ct_testdata : 20; - bdrkreg_t ct_testmask : 8; - bdrkreg_t ct_testseed : 20; - } ni_channel_test_fld_s; -} ni_channel_test_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains LLP port parameters and enables for the * - * capture of header data. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_port_parms_u { - bdrkreg_t ni_port_parms_regval; - struct { - bdrkreg_t pp_max_burst : 10; - bdrkreg_t pp_null_timeout : 6; - bdrkreg_t pp_max_retry : 10; - bdrkreg_t pp_d_avail_sel : 2; - bdrkreg_t pp_rsvd_1 : 1; - bdrkreg_t pp_first_err_enable : 1; - bdrkreg_t pp_squash_err_enable : 1; - bdrkreg_t pp_vch_err_enable : 4; - bdrkreg_t pp_rsvd : 29; - } ni_port_parms_fld_s; -} ni_port_parms_u_t; - -#else - -typedef union ni_port_parms_u { - bdrkreg_t ni_port_parms_regval; - struct { - bdrkreg_t pp_rsvd : 29; - bdrkreg_t pp_vch_err_enable : 4; - bdrkreg_t pp_squash_err_enable : 1; - bdrkreg_t pp_first_err_enable : 1; - bdrkreg_t pp_rsvd_1 : 1; - bdrkreg_t pp_d_avail_sel : 2; - bdrkreg_t pp_max_retry : 10; - bdrkreg_t pp_null_timeout : 6; - bdrkreg_t pp_max_burst : 10; - } ni_port_parms_fld_s; -} ni_port_parms_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains the age at which request and reply packets * - * are injected into the network. This feature allows replies to be * - * given a higher fixed priority than requests, which can be * - * important in some network saturation situations. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_channel_age_u { - bdrkreg_t ni_channel_age_regval; - struct { - bdrkreg_t ca_request_inject_age : 8; - bdrkreg_t ca_reply_inject_age : 8; - bdrkreg_t ca_rsvd : 48; - } ni_channel_age_fld_s; -} ni_channel_age_u_t; - -#else - -typedef union ni_channel_age_u { - bdrkreg_t ni_channel_age_regval; - struct { - bdrkreg_t ca_rsvd : 48; - bdrkreg_t ca_reply_inject_age : 8; - bdrkreg_t ca_request_inject_age : 8; - } ni_channel_age_fld_s; -} ni_channel_age_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains latched LLP port and problematic message * - * errors. The contents are the same information as the * - * NI_PORT_ERROR_CLEAR register, but, in this register read accesses * - * are non-destructive. Bits [52:24] assert the NI interrupt. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_port_errors_u { - bdrkreg_t ni_port_errors_regval; - struct { - bdrkreg_t pe_sn_error_count : 8; - bdrkreg_t pe_cb_error_count : 8; - bdrkreg_t pe_retry_count : 8; - bdrkreg_t pe_tail_timeout : 4; - bdrkreg_t pe_fifo_overflow : 4; - bdrkreg_t pe_external_short : 4; - bdrkreg_t pe_external_long : 4; - bdrkreg_t pe_external_bad_header : 4; - bdrkreg_t pe_internal_short : 4; - bdrkreg_t pe_internal_long : 4; - bdrkreg_t pe_link_reset_in : 1; - bdrkreg_t pe_rsvd : 11; - } ni_port_errors_fld_s; -} ni_port_errors_u_t; - -#else - -typedef union ni_port_errors_u { - bdrkreg_t ni_port_errors_regval; - struct { - bdrkreg_t pe_rsvd : 11; - bdrkreg_t pe_link_reset_in : 1; - bdrkreg_t pe_internal_long : 4; - bdrkreg_t pe_internal_short : 4; - bdrkreg_t pe_external_bad_header : 4; - bdrkreg_t pe_external_long : 4; - bdrkreg_t pe_external_short : 4; - bdrkreg_t pe_fifo_overflow : 4; - bdrkreg_t pe_tail_timeout : 4; - bdrkreg_t pe_retry_count : 8; - bdrkreg_t pe_cb_error_count : 8; - bdrkreg_t pe_sn_error_count : 8; - } ni_port_errors_fld_s; -} ni_port_errors_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register provides the sideband data associated with the * - * NI_PORT_HEADER registers and also additional data for error * - * processing. This register is not cleared on reset. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_port_sideband_u { - bdrkreg_t ni_port_sideband_regval; - struct { - bdrkreg_t ps_sideband : 8; - bdrkreg_t ps_bad_dest : 1; - bdrkreg_t ps_bad_prexsel : 1; - bdrkreg_t ps_rcv_error : 1; - bdrkreg_t ps_bad_message : 1; - bdrkreg_t ps_squash : 1; - bdrkreg_t ps_sn_status : 1; - bdrkreg_t ps_cb_status : 1; - bdrkreg_t ps_send_error : 1; - bdrkreg_t ps_vch_active : 4; - bdrkreg_t ps_rsvd : 44; - } ni_port_sideband_fld_s; -} ni_port_sideband_u_t; - -#else - -typedef union ni_port_sideband_u { - bdrkreg_t ni_port_sideband_regval; - struct { - bdrkreg_t ps_rsvd : 44; - bdrkreg_t ps_vch_active : 4; - bdrkreg_t ps_send_error : 1; - bdrkreg_t ps_cb_status : 1; - bdrkreg_t ps_sn_status : 1; - bdrkreg_t ps_squash : 1; - bdrkreg_t ps_bad_message : 1; - bdrkreg_t ps_rcv_error : 1; - bdrkreg_t ps_bad_prexsel : 1; - bdrkreg_t ps_bad_dest : 1; - bdrkreg_t ps_sideband : 8; - } ni_port_sideband_fld_s; -} ni_port_sideband_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register contains latched LLP port and problematic message * - * errors. The contents are the same information as the * - * NI_PORT_ERROR_CLEAR register, but, in this register read accesses * - * are non-destructive. Bits [52:24] assert the NI interrupt. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_port_error_clear_u { - bdrkreg_t ni_port_error_clear_regval; - struct { - bdrkreg_t pec_sn_error_count : 8; - bdrkreg_t pec_cb_error_count : 8; - bdrkreg_t pec_retry_count : 8; - bdrkreg_t pec_tail_timeout : 4; - bdrkreg_t pec_fifo_overflow : 4; - bdrkreg_t pec_external_short : 4; - bdrkreg_t pec_external_long : 4; - bdrkreg_t pec_external_bad_header : 4; - bdrkreg_t pec_internal_short : 4; - bdrkreg_t pec_internal_long : 4; - bdrkreg_t pec_link_reset_in : 1; - bdrkreg_t pec_rsvd : 11; - } ni_port_error_clear_fld_s; -} ni_port_error_clear_u_t; - -#else - -typedef union ni_port_error_clear_u { - bdrkreg_t ni_port_error_clear_regval; - struct { - bdrkreg_t pec_rsvd : 11; - bdrkreg_t pec_link_reset_in : 1; - bdrkreg_t pec_internal_long : 4; - bdrkreg_t pec_internal_short : 4; - bdrkreg_t pec_external_bad_header : 4; - bdrkreg_t pec_external_long : 4; - bdrkreg_t pec_external_short : 4; - bdrkreg_t pec_fifo_overflow : 4; - bdrkreg_t pec_tail_timeout : 4; - bdrkreg_t pec_retry_count : 8; - bdrkreg_t pec_cb_error_count : 8; - bdrkreg_t pec_sn_error_count : 8; - } ni_port_error_clear_fld_s; -} ni_port_error_clear_u_t; - -#endif - - - - -/************************************************************************ - * * - * Lookup table for the next hop's exit port. The table entry * - * selection is based on the 7-bit LocalCube routing destination. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_local_table_0_u { - bdrkreg_t ni_local_table_0_regval; - struct { - bdrkreg_t lt0_next_exit_port : 4; - bdrkreg_t lt0_next_vch_lsb : 1; - bdrkreg_t lt0_rsvd : 59; - } ni_local_table_0_fld_s; -} ni_local_table_0_u_t; - -#else - -typedef union ni_local_table_0_u { - bdrkreg_t ni_local_table_0_regval; - struct { - bdrkreg_t lt0_rsvd : 59; - bdrkreg_t lt0_next_vch_lsb : 1; - bdrkreg_t lt0_next_exit_port : 4; - } ni_local_table_0_fld_s; -} ni_local_table_0_u_t; - -#endif - - - - -/************************************************************************ - * * - * Lookup table for the next hop's exit port. The table entry * - * selection is based on the 7-bit LocalCube routing destination. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_local_table_127_u { - bdrkreg_t ni_local_table_127_regval; - struct { - bdrkreg_t lt1_next_exit_port : 4; - bdrkreg_t lt1_next_vch_lsb : 1; - bdrkreg_t lt1_rsvd : 59; - } ni_local_table_127_fld_s; -} ni_local_table_127_u_t; - -#else - -typedef union ni_local_table_127_u { - bdrkreg_t ni_local_table_127_regval; - struct { - bdrkreg_t lt1_rsvd : 59; - bdrkreg_t lt1_next_vch_lsb : 1; - bdrkreg_t lt1_next_exit_port : 4; - } ni_local_table_127_fld_s; -} ni_local_table_127_u_t; - -#endif - - - - -/************************************************************************ - * * - * Lookup table for the next hop's exit port. The table entry * - * selection is based on the 1-bit MetaCube routing destination. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union ni_global_table_u { - bdrkreg_t ni_global_table_regval; - struct { - bdrkreg_t gt_next_exit_port : 4; - bdrkreg_t gt_next_vch_lsb : 1; - bdrkreg_t gt_rsvd : 59; - } ni_global_table_fld_s; -} ni_global_table_u_t; - -#else - -typedef union ni_global_table_u { - bdrkreg_t ni_global_table_regval; - struct { - bdrkreg_t gt_rsvd : 59; - bdrkreg_t gt_next_vch_lsb : 1; - bdrkreg_t gt_next_exit_port : 4; - } ni_global_table_fld_s; -} ni_global_table_u_t; - -#endif - - - - - - -#endif /* __ASSEMBLY__ */ - -/************************************************************************ - * * - * The following defines which were not formed into structures are * - * probably indentical to another register, and the name of the * - * register is provided against each of these registers. This * - * information needs to be checked carefully * - * * - * NI_LOCAL_TABLE_1 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_2 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_3 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_4 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_5 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_6 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_7 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_8 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_9 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_10 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_11 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_12 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_13 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_14 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_15 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_16 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_17 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_18 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_19 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_20 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_21 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_22 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_23 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_24 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_25 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_26 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_27 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_28 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_29 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_30 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_31 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_32 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_33 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_34 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_35 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_36 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_37 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_38 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_39 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_40 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_41 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_42 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_43 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_44 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_45 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_46 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_47 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_48 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_49 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_50 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_51 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_52 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_53 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_54 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_55 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_56 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_57 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_58 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_59 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_60 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_61 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_62 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_63 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_64 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_65 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_66 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_67 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_68 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_69 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_70 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_71 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_72 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_73 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_74 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_75 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_76 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_77 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_78 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_79 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_80 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_81 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_82 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_83 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_84 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_85 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_86 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_87 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_88 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_89 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_90 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_91 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_92 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_93 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_94 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_95 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_96 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_97 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_98 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_99 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_100 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_101 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_102 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_103 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_104 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_105 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_106 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_107 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_108 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_109 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_110 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_111 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_112 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_113 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_114 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_115 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_116 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_117 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_118 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_119 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_120 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_121 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_122 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_123 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_124 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_125 NI_LOCAL_TABLE_0 * - * NI_LOCAL_TABLE_126 NI_LOCAL_TABLE_0 * - * * - ************************************************************************/ - - -/************************************************************************ - * * - * The following defines were not formed into structures * - * * - * This could be because the document did not contain details of the * - * register, or because the automated script did not recognize the * - * register details in the documentation. If these register need * - * structure definition, please create them manually * - * * - * NI_PORT_HEADER_A 0x680108 * - * NI_PORT_HEADER_B 0x680110 * - * * - ************************************************************************/ - - -/************************************************************************ - * * - * MAKE ALL ADDITIONS AFTER THIS LINE * - * * - ************************************************************************/ - - - - - -#endif /* _ASM_IA64_SN_SN1_HUBNI_H */ diff --git a/include/asm-ia64/sn/sn1/hubni_next.h b/include/asm-ia64/sn/sn1/hubni_next.h deleted file mode 100644 index ebee5b7ad9736..0000000000000 --- a/include/asm-ia64/sn/sn1/hubni_next.h +++ /dev/null @@ -1,174 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_HUBNI_NEXT_H -#define _ASM_IA64_SN_SN1_HUBNI_NEXT_H - -#define NI_LOCAL_ENTRIES 128 -#define NI_META_ENTRIES 1 - -#define NI_LOCAL_TABLE(_x) (NI_LOCAL_TABLE_0 + (8 * (_x))) -#define NI_META_TABLE(_x) (NI_GLOBAL_TABLE + (8 * (_x))) - -/************************************************************** - - Masks and shifts for NI registers are defined below. - -**************************************************************/ - -#define NPS_LINKUP_SHFT 1 -#define NPS_LINKUP_MASK (UINT64_CAST 0x1 << 1) - - -#define NPR_LOCALRESET (UINT64_CAST 1 << 2) /* Reset loc. bdrck */ -#define NPR_PORTRESET (UINT64_CAST 1 << 1) /* Send warm reset */ -#define NPR_LINKRESET (UINT64_CAST 1 << 0) /* Send link reset */ - -/* NI_DIAG_PARMS bit definitions */ -#define NDP_SENDERROR (UINT64_CAST 1 << 0) /* Send data error */ -#define NDP_PORTDISABLE (UINT64_CAST 1 << 1) /* Port disable */ -#define NDP_SENDERROFF (UINT64_CAST 1 << 2) /* Disable send error recovery */ - - -/* NI_PORT_ERROR mask and shift definitions (some are not present in SN0) */ - -#define NPE_LINKRESET (UINT64_CAST 1 << 52) -#define NPE_INTLONG_SHFT 48 -#define NPE_INTLONG_MASK (UINT64_CAST 0xf << NPE_INTLONG_SHFT) -#define NPE_INTSHORT_SHFT 44 -#define NPE_INTSHORT_MASK (UINT64_CAST 0xf << NPE_INTSHORT_SHFT) -#define NPE_EXTBADHEADER_SHFT 40 -#define NPE_EXTBADHEADER_MASK (UINT64_CAST 0xf << NPE_EXTBADHEADER_SHFT) -#define NPE_EXTLONG_SHFT 36 -#define NPE_EXTLONG_MASK (UINT64_CAST 0xf << NPE_EXTLONG_SHFT) -#define NPE_EXTSHORT_SHFT 32 -#define NPE_EXTSHORT_MASK (UINT64_CAST 0xf << NPE_EXTSHORT_SHFT) -#define NPE_FIFOOVFLOW_SHFT 28 -#define NPE_FIFOOVFLOW_MASK (UINT64_CAST 0xf << NPE_FIFOOVFLOW_SHFT) -#define NPE_TAILTO_SHFT 24 -#define NPE_TAILTO_MASK (UINT64_CAST 0xf << NPE_TAILTO_SHFT) -#define NPE_RETRYCOUNT_SHFT 16 -#define NPE_RETRYCOUNT_MASK (UINT64_CAST 0xff << NPE_RETRYCOUNT_SHFT) -#define NPE_CBERRCOUNT_SHFT 8 -#define NPE_CBERRCOUNT_MASK (UINT64_CAST 0xff << NPE_CBERRCOUNT_SHFT) -#define NPE_SNERRCOUNT_SHFT 0 -#define NPE_SNERRCOUNT_MASK (UINT64_CAST 0xff << NPE_SNERRCOUNT_SHFT) - -#define NPE_COUNT_MAX 0xff - -#define NPE_FATAL_ERRORS (NPE_LINKRESET | NPE_INTLONG_MASK |\ - NPE_INTSHORT_MASK | NPE_EXTBADHEADER_MASK |\ - NPE_EXTLONG_MASK | NPE_EXTSHORT_MASK |\ - NPE_FIFOOVFLOW_MASK | NPE_TAILTO_MASK) - -#ifndef __ASSEMBLY__ -/* NI_PORT_HEADER[AB] registers (not automatically generated) */ - -#ifdef LITTLE_ENDIAN - -typedef union ni_port_header_a_u { - bdrkreg_t ni_port_header_a_regval; - struct { - bdrkreg_t pha_v : 1; - bdrkreg_t pha_age : 8; - bdrkreg_t pha_direction : 4; - bdrkreg_t pha_destination : 8; - bdrkreg_t pha_reserved_1 : 3; - bdrkreg_t pha_command : 8; - bdrkreg_t pha_prexsel : 3; - bdrkreg_t pha_address_b : 27; - bdrkreg_t pha_reserved : 2; - } ni_port_header_a_fld_s; -} ni_port_header_a_u_t; - -#else - -typedef union ni_port_header_a_u { - bdrkreg_t ni_port_header_a_regval; - struct { - bdrkreg_t pha_reserved : 2; - bdrkreg_t pha_address_b : 27; - bdrkreg_t pha_prexsel : 3; - bdrkreg_t pha_command : 8; - bdrkreg_t pha_reserved_1 : 3; - bdrkreg_t pha_destination : 8; - bdrkreg_t pha_direction : 4; - bdrkreg_t pha_age : 8; - bdrkreg_t pha_v : 1; - } ni_port_header_a_fld_s; -} ni_port_header_a_u_t; - -#endif - -#ifdef LITTLE_ENDIAN - -typedef union ni_port_header_b_u { - bdrkreg_t ni_port_header_b_regval; - struct { - bdrkreg_t phb_supplemental : 11; - bdrkreg_t phb_reserved_2 : 5; - bdrkreg_t phb_source : 11; - bdrkreg_t phb_reserved_1 : 8; - bdrkreg_t phb_address_a : 3; - bdrkreg_t phb_address_c : 8; - bdrkreg_t phb_reserved : 18; - } ni_port_header_b_fld_s; -} ni_port_header_b_u_t; - -#else - -typedef union ni_port_header_b_u { - bdrkreg_t ni_port_header_b_regval; - struct { - bdrkreg_t phb_reserved : 18; - bdrkreg_t phb_address_c : 8; - bdrkreg_t phb_address_a : 3; - bdrkreg_t phb_reserved_1 : 8; - bdrkreg_t phb_source : 11; - bdrkreg_t phb_reserved_2 : 5; - bdrkreg_t phb_supplemental : 11; - } ni_port_header_b_fld_s; -} ni_port_header_b_u_t; - -#endif -#endif - -/* NI_RESET_ENABLE mask definitions */ - -#define NRE_RESETOK (UINT64_CAST 1) /* Let LLP reset bedrock */ - -/* NI PORT_ERRORS, Max number of RETRY_COUNT, Check Bit, and Sequence */ -/* Number errors (8 bit counters that do not wrap). */ -#define NI_LLP_RETRY_MAX 0xff -#define NI_LLP_CB_MAX 0xff -#define NI_LLP_SN_MAX 0xff - -/* NI_PORT_PARMS shift and mask definitions */ - -#define NPP_VCH_ERR_EN_SHFT 31 -#define NPP_VCH_ERR_EN_MASK (0xf << NPP_VCH_ERR_EN_SHFT) -#define NPP_SQUASH_ERR_EN_SHFT 30 -#define NPP_SQUASH_ERR_EN_MASK (0x1 << NPP_SQUASH_ERR_EN_SHFT) -#define NPP_FIRST_ERR_EN_SHFT 29 -#define NPP_FIRST_ERR_EN_MASK (0x1 << NPP_FIRST_ERR_EN_SHFT) -#define NPP_D_AVAIL_SEL_SHFT 26 -#define NPP_D_AVAIL_SEL_MASK (0x3 << NPP_D_AVAIL_SEL_SHFT) -#define NPP_MAX_RETRY_SHFT 16 -#define NPP_MAX_RETRY_MASK (0x3ff << NPP_MAX_RETRY_SHFT) -#define NPP_NULL_TIMEOUT_SHFT 10 -#define NPP_NULL_TIMEOUT_MASK (0x3f << NPP_NULL_TIMEOUT_SHFT) -#define NPP_MAX_BURST_SHFT 0 -#define NPP_MAX_BURST_MASK (0x3ff << NPP_MAX_BURST_SHFT) - -#define NPP_RESET_DEFAULTS (0xf << NPP_VCH_ERR_EN_SHFT | \ - 0x1 << NPP_FIRST_ERR_EN_SHFT | \ - 0x3ff << NPP_MAX_RETRY_SHFT | \ - 0x6 << NPP_NULL_TIMEOUT_SHFT | \ - 0x3f0 << NPP_MAX_BURST_SHFT) - -#endif /* _ASM_IA64_SN_SN1_HUBNI_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hubpi.h b/include/asm-ia64/sn/sn1/hubpi.h deleted file mode 100644 index 7c698412621ab..0000000000000 --- a/include/asm-ia64/sn/sn1/hubpi.h +++ /dev/null @@ -1,4263 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_HUBPI_H -#define _ASM_IA64_SN_SN1_HUBPI_H - -/************************************************************************ - * * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * - * * - * This file is created by an automated script. Any (minimal) changes * - * made manually to this file should be made with care. * - * * - * MAKE ALL ADDITIONS TO THE END OF THIS FILE * - * * - ************************************************************************/ - - -#define PI_CPU_PROTECT 0x00000000 /* CPU Protection */ - - - -#define PI_PROT_OVRRD 0x00000008 /* - * Clear CPU - * Protection bit in - * CPU_PROTECT - */ - - - -#define PI_IO_PROTECT 0x00000010 /* - * Interrupt Pending - * Protection for IO - * access - */ - - - -#define PI_REGION_PRESENT 0x00000018 /* Region present */ - - - -#define PI_CPU_NUM 0x00000020 /* CPU Number ID */ - - - -#define PI_CALIAS_SIZE 0x00000028 /* Cached Alias Size */ - - - -#define PI_MAX_CRB_TIMEOUT 0x00000030 /* - * Maximum Timeout for - * CRB - */ - - - -#define PI_CRB_SFACTOR 0x00000038 /* - * Scale Factor for - * CRB Timeout - */ - - - -#define PI_CPU_PRESENT_A 0x00000040 /* - * CPU Present for - * CPU_A - */ - - - -#define PI_CPU_PRESENT_B 0x00000048 /* - * CPU Present for - * CPU_B - */ - - - -#define PI_CPU_ENABLE_A 0x00000050 /* - * CPU Enable for - * CPU_A - */ - - - -#define PI_CPU_ENABLE_B 0x00000058 /* - * CPU Enable for - * CPU_B - */ - - - -#define PI_REPLY_LEVEL 0x00010060 /* - * Reply FIFO Priority - * Control - */ - - - -#define PI_GFX_CREDIT_MODE 0x00020068 /* - * Graphics Credit - * Mode - */ - - - -#define PI_NMI_A 0x00000070 /* - * Non-maskable - * Interrupt to CPU A - */ - - - -#define PI_NMI_B 0x00000078 /* - * Non-maskable - * Interrupt to CPU B - */ - - - -#define PI_INT_PEND_MOD 0x00000090 /* - * Interrupt Pending - * Modify - */ - - - -#define PI_INT_PEND0 0x00000098 /* Interrupt Pending 0 */ - - - -#define PI_INT_PEND1 0x000000A0 /* Interrupt Pending 1 */ - - - -#define PI_INT_MASK0_A 0x000000A8 /* - * Interrupt Mask 0 - * for CPU A - */ - - - -#define PI_INT_MASK1_A 0x000000B0 /* - * Interrupt Mask 1 - * for CPU A - */ - - - -#define PI_INT_MASK0_B 0x000000B8 /* - * Interrupt Mask 0 - * for CPU B - */ - - - -#define PI_INT_MASK1_B 0x000000C0 /* - * Interrupt Mask 1 - * for CPU B - */ - - - -#define PI_CC_PEND_SET_A 0x000000C8 /* - * CC Interrupt - * Pending for CPU A - */ - - - -#define PI_CC_PEND_SET_B 0x000000D0 /* - * CC Interrupt - * Pending for CPU B - */ - - - -#define PI_CC_PEND_CLR_A 0x000000D8 /* - * CPU to CPU - * Interrupt Pending - * Clear for CPU A - */ - - - -#define PI_CC_PEND_CLR_B 0x000000E0 /* - * CPU to CPU - * Interrupt Pending - * Clear for CPU B - */ - - - -#define PI_CC_MASK 0x000000E8 /* - * Mask of both - * CC_PENDs - */ - - - -#define PI_INT_PEND1_REMAP 0x000000F0 /* - * Remap Interrupt - * Pending - */ - - - -#define PI_RT_COUNTER 0x00030100 /* Real Time Counter */ - - - -#define PI_RT_COMPARE_A 0x00000108 /* Real Time Compare A */ - - - -#define PI_RT_COMPARE_B 0x00000110 /* Real Time Compare B */ - - - -#define PI_PROFILE_COMPARE 0x00000118 /* Profiling Compare */ - - - -#define PI_RT_INT_PEND_A 0x00000120 /* - * RT interrupt - * pending - */ - - - -#define PI_RT_INT_PEND_B 0x00000128 /* - * RT interrupt - * pending - */ - - - -#define PI_PROF_INT_PEND_A 0x00000130 /* - * Profiling interrupt - * pending - */ - - - -#define PI_PROF_INT_PEND_B 0x00000138 /* - * Profiling interrupt - * pending - */ - - - -#define PI_RT_INT_EN_A 0x00000140 /* RT Interrupt Enable */ - - - -#define PI_RT_INT_EN_B 0x00000148 /* RT Interrupt Enable */ - - - -#define PI_PROF_INT_EN_A 0x00000150 /* - * Profiling Interrupt - * Enable - */ - - - -#define PI_PROF_INT_EN_B 0x00000158 /* - * Profiling Interrupt - * Enable - */ - - - -#define PI_DEBUG_SEL 0x00000160 /* PI Debug Select */ - - - -#define PI_INT_PEND_MOD_ALIAS 0x00000180 /* - * Interrupt Pending - * Modify - */ - - - -#define PI_PERF_CNTL_A 0x00040200 /* - * Performance Counter - * Control A - */ - - - -#define PI_PERF_CNTR0_A 0x00040208 /* - * Performance Counter - * 0 A - */ - - - -#define PI_PERF_CNTR1_A 0x00040210 /* - * Performance Counter - * 1 A - */ - - - -#define PI_PERF_CNTL_B 0x00050200 /* - * Performance Counter - * Control B - */ - - - -#define PI_PERF_CNTR0_B 0x00050208 /* - * Performance Counter - * 0 B - */ - - - -#define PI_PERF_CNTR1_B 0x00050210 /* - * Performance Counter - * 1 B - */ - - - -#define PI_GFX_PAGE_A 0x00000300 /* Graphics Page */ - - - -#define PI_GFX_CREDIT_CNTR_A 0x00000308 /* - * Graphics Credit - * Counter - */ - - - -#define PI_GFX_BIAS_A 0x00000310 /* TRex+ BIAS */ - - - -#define PI_GFX_INT_CNTR_A 0x00000318 /* - * Graphics Interrupt - * Counter - */ - - - -#define PI_GFX_INT_CMP_A 0x00000320 /* - * Graphics Interrupt - * Compare - */ - - - -#define PI_GFX_PAGE_B 0x00000328 /* Graphics Page */ - - - -#define PI_GFX_CREDIT_CNTR_B 0x00000330 /* - * Graphics Credit - * Counter - */ - - - -#define PI_GFX_BIAS_B 0x00000338 /* TRex+ BIAS */ - - - -#define PI_GFX_INT_CNTR_B 0x00000340 /* - * Graphics Interrupt - * Counter - */ - - - -#define PI_GFX_INT_CMP_B 0x00000348 /* - * Graphics Interrupt - * Compare - */ - - - -#define PI_ERR_INT_PEND_WR 0x000003F8 /* - * Error Interrupt - * Pending (Writable) - */ - - - -#define PI_ERR_INT_PEND 0x00000400 /* - * Error Interrupt - * Pending - */ - - - -#define PI_ERR_INT_MASK_A 0x00000408 /* - * Error Interrupt - * Mask CPU_A - */ - - - -#define PI_ERR_INT_MASK_B 0x00000410 /* - * Error Interrupt - * Mask CPU_B - */ - - - -#define PI_ERR_STACK_ADDR_A 0x00000418 /* - * Error Stack Address - * Pointer - */ - - - -#define PI_ERR_STACK_ADDR_B 0x00000420 /* - * Error Stack Address - * Pointer - */ - - - -#define PI_ERR_STACK_SIZE 0x00000428 /* Error Stack Size */ - - - -#define PI_ERR_STATUS0_A 0x00000430 /* Error Status 0 */ - - - -#define PI_ERR_STATUS0_A_CLR 0x00000438 /* Error Status 0 */ - - - -#define PI_ERR_STATUS1_A 0x00000440 /* Error Status 1 */ - - - -#define PI_ERR_STATUS1_A_CLR 0x00000448 /* Error Status 1 */ - - - -#define PI_ERR_STATUS0_B 0x00000450 /* Error Status 0 */ - - - -#define PI_ERR_STATUS0_B_CLR 0x00000458 /* Error Status 0 */ - - - -#define PI_ERR_STATUS1_B 0x00000460 /* Error Status 1 */ - - - -#define PI_ERR_STATUS1_B_CLR 0x00000468 /* Error Status 1 */ - - - -#define PI_SPOOL_CMP_A 0x00000470 /* Spool Compare */ - - - -#define PI_SPOOL_CMP_B 0x00000478 /* Spool Compare */ - - - -#define PI_CRB_TIMEOUT_A 0x00000480 /* - * CRB entries which - * have timed out but - * are still valid - */ - - - -#define PI_CRB_TIMEOUT_B 0x00000488 /* - * CRB entries which - * have timed out but - * are still valid - */ - - - -#define PI_SYSAD_ERRCHK_EN 0x00000490 /* - * enables - * sysad/cmd/state - * error checking - */ - - - -#define PI_FORCE_BAD_CHECK_BIT_A 0x00000498 /* - * force SysAD Check - * Bit error - */ - - - -#define PI_FORCE_BAD_CHECK_BIT_B 0x000004A0 /* - * force SysAD Check - * Bit error - */ - - - -#define PI_NACK_CNT_A 0x000004A8 /* - * consecutive NACK - * counter - */ - - - -#define PI_NACK_CNT_B 0x000004B0 /* - * consecutive NACK - * counter - */ - - - -#define PI_NACK_CMP 0x000004B8 /* NACK count compare */ - - - -#define PI_SPOOL_MASK 0x000004C0 /* Spool error mask */ - - - -#define PI_SPURIOUS_HDR_0 0x000004C8 /* Spurious Error 0 */ - - - -#define PI_SPURIOUS_HDR_1 0x000004D0 /* Spurious Error 1 */ - - - -#define PI_ERR_INJECT 0x000004D8 /* - * SysAD bus error - * injection - */ - - - - - -#ifndef __ASSEMBLY__ - -/************************************************************************ - * * - * Description: This read/write register determines on a * - * bit-per-region basis whether incoming CPU-initiated PIO Read and * - * Write to local PI registers are allowed. If access is allowed, the * - * PI's response to a partial read is a PRPLY message, and the * - * response to a partial write is a PACK message. If access is not * - * allowed, the PI's response to a partial read is a PRERR message, * - * and the response to a partial write is a PWERR message. * - * This register is not reset by a soft reset. * - * * - ************************************************************************/ - - - - -typedef union pi_cpu_protect_u { - bdrkreg_t pi_cpu_protect_regval; - struct { - bdrkreg_t cp_cpu_protect : 64; - } pi_cpu_protect_fld_s; -} pi_cpu_protect_u_t; - - - - -/************************************************************************ - * * - * A write with a special data pattern allows any CPU to set its * - * region's bit in CPU_PROTECT. This register has data pattern * - * protection. * - * * - ************************************************************************/ - - - - -typedef union pi_prot_ovrrd_u { - bdrkreg_t pi_prot_ovrrd_regval; - struct { - bdrkreg_t po_prot_ovrrd : 64; - } pi_prot_ovrrd_fld_s; -} pi_prot_ovrrd_u_t; - - - - -/************************************************************************ - * * - * Description: This read/write register determines on a * - * bit-per-region basis whether incoming IO-initiated interrupts are * - * allowed to set bits in INT_PEND0 and INT_PEND1. If access is * - * allowed, the PI's response to a partial read is a PRPLY message, * - * and the response to a partial write is a PACK message. If access * - * is not allowed, the PI's response to a partial read is a PRERR * - * message, and the response to a partial write is a PWERR message. * - * This register is not reset by a soft reset. * - * * - ************************************************************************/ - - - - -typedef union pi_io_protect_u { - bdrkreg_t pi_io_protect_regval; - struct { - bdrkreg_t ip_io_protect : 64; - } pi_io_protect_fld_s; -} pi_io_protect_u_t; - - - - -/************************************************************************ - * * - * Description: This read/write register determines on a * - * bit-per-region basis whether read access from a local processor to * - * the region is permissible. For example, setting a bit to 0 * - * prevents speculative reads to that non-existent node. If a read * - * request to a non-present region occurs, an ERR response is issued * - * to the TRex+ (no PI error registers are modified). It is up to * - * software to load this register with the proper contents. * - * Region-present checking is only done for coherent read requests - * - * partial reads/writes will be issued to a non-present region. The * - * setting of these bits does not affect a node's access to its * - * CALIAS space. * - * This register is not reset by a soft reset. * - * * - ************************************************************************/ - - - - -typedef union pi_region_present_u { - bdrkreg_t pi_region_present_regval; - struct { - bdrkreg_t rp_region_present : 64; - } pi_region_present_fld_s; -} pi_region_present_u_t; - - - - -/************************************************************************ - * * - * A read to the location will allow a CPU to identify itself as * - * either CPU_A or CPU_B, and will indicate whether the CPU is * - * connected to PI 0 or PI 1. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_cpu_num_u { - bdrkreg_t pi_cpu_num_regval; - struct { - bdrkreg_t cn_cpu_num : 1; - bdrkreg_t cn_pi_id : 1; - bdrkreg_t cn_rsvd : 62; - } pi_cpu_num_fld_s; -} pi_cpu_num_u_t; - -#else - -typedef union pi_cpu_num_u { - bdrkreg_t pi_cpu_num_regval; - struct { - bdrkreg_t cn_rsvd : 62; - bdrkreg_t cn_pi_id : 1; - bdrkreg_t cn_cpu_num : 1; - } pi_cpu_num_fld_s; -} pi_cpu_num_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This read/write location determines the size of the * - * Calias Space. * - * This register is not reset by a soft reset. * - * NOTE: For predictable behavior, all Calias spaces in a system must * - * be set to the same size. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_calias_size_u { - bdrkreg_t pi_calias_size_regval; - struct { - bdrkreg_t cs_calias_size : 4; - bdrkreg_t cs_rsvd : 60; - } pi_calias_size_fld_s; -} pi_calias_size_u_t; - -#else - -typedef union pi_calias_size_u { - bdrkreg_t pi_calias_size_regval; - struct { - bdrkreg_t cs_rsvd : 60; - bdrkreg_t cs_calias_size : 4; - } pi_calias_size_fld_s; -} pi_calias_size_u_t; - -#endif - - - - -/************************************************************************ - * * - * This Read/Write location determines at which value (increment) * - * the CRB Timeout Counters cause a timeout error to occur. See * - * Section 3.4.2.2, "Time-outs in RRB and WRB" in the * - * Processor Interface chapter, volume 1 of this document for more * - * details. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_max_crb_timeout_u { - bdrkreg_t pi_max_crb_timeout_regval; - struct { - bdrkreg_t mct_max_timeout : 8; - bdrkreg_t mct_rsvd : 56; - } pi_max_crb_timeout_fld_s; -} pi_max_crb_timeout_u_t; - -#else - -typedef union pi_max_crb_timeout_u { - bdrkreg_t pi_max_crb_timeout_regval; - struct { - bdrkreg_t mct_rsvd : 56; - bdrkreg_t mct_max_timeout : 8; - } pi_max_crb_timeout_fld_s; -} pi_max_crb_timeout_u_t; - -#endif - - - - -/************************************************************************ - * * - * This Read/Write location determines how often a valid CRB's * - * Timeout Counter is incremented. See Section 3.4.2.2, * - * "Time-outs in RRB and WRB" in the Processor Interface * - * chapter, volume 1 of this document for more details. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_crb_sfactor_u { - bdrkreg_t pi_crb_sfactor_regval; - struct { - bdrkreg_t cs_sfactor : 24; - bdrkreg_t cs_rsvd : 40; - } pi_crb_sfactor_fld_s; -} pi_crb_sfactor_u_t; - -#else - -typedef union pi_crb_sfactor_u { - bdrkreg_t pi_crb_sfactor_regval; - struct { - bdrkreg_t cs_rsvd : 40; - bdrkreg_t cs_sfactor : 24; - } pi_crb_sfactor_fld_s; -} pi_crb_sfactor_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. The PI sets this * - * bit when it sees the first transaction initiated by the associated * - * CPU. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_cpu_present_a_u { - bdrkreg_t pi_cpu_present_a_regval; - struct { - bdrkreg_t cpa_cpu_present : 1; - bdrkreg_t cpa_rsvd : 63; - } pi_cpu_present_a_fld_s; -} pi_cpu_present_a_u_t; - -#else - -typedef union pi_cpu_present_a_u { - bdrkreg_t pi_cpu_present_a_regval; - struct { - bdrkreg_t cpa_rsvd : 63; - bdrkreg_t cpa_cpu_present : 1; - } pi_cpu_present_a_fld_s; -} pi_cpu_present_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. The PI sets this * - * bit when it sees the first transaction initiated by the associated * - * CPU. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_cpu_present_b_u { - bdrkreg_t pi_cpu_present_b_regval; - struct { - bdrkreg_t cpb_cpu_present : 1; - bdrkreg_t cpb_rsvd : 63; - } pi_cpu_present_b_fld_s; -} pi_cpu_present_b_u_t; - -#else - -typedef union pi_cpu_present_b_u { - bdrkreg_t pi_cpu_present_b_regval; - struct { - bdrkreg_t cpb_rsvd : 63; - bdrkreg_t cpb_cpu_present : 1; - } pi_cpu_present_b_fld_s; -} pi_cpu_present_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There is one of these registers for each CPU. This * - * Read/Write location determines whether the associated CPU is * - * enabled to issue external requests. When this bit is zero for a * - * processor, the PI ignores SysReq_L from that processor, and so * - * never grants it the bus. * - * This register is not reset by a soft reset. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_cpu_enable_a_u { - bdrkreg_t pi_cpu_enable_a_regval; - struct { - bdrkreg_t cea_cpu_enable : 1; - bdrkreg_t cea_rsvd : 63; - } pi_cpu_enable_a_fld_s; -} pi_cpu_enable_a_u_t; - -#else - -typedef union pi_cpu_enable_a_u { - bdrkreg_t pi_cpu_enable_a_regval; - struct { - bdrkreg_t cea_rsvd : 63; - bdrkreg_t cea_cpu_enable : 1; - } pi_cpu_enable_a_fld_s; -} pi_cpu_enable_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There is one of these registers for each CPU. This * - * Read/Write location determines whether the associated CPU is * - * enabled to issue external requests. When this bit is zero for a * - * processor, the PI ignores SysReq_L from that processor, and so * - * never grants it the bus. * - * This register is not reset by a soft reset. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_cpu_enable_b_u { - bdrkreg_t pi_cpu_enable_b_regval; - struct { - bdrkreg_t ceb_cpu_enable : 1; - bdrkreg_t ceb_rsvd : 63; - } pi_cpu_enable_b_fld_s; -} pi_cpu_enable_b_u_t; - -#else - -typedef union pi_cpu_enable_b_u { - bdrkreg_t pi_cpu_enable_b_regval; - struct { - bdrkreg_t ceb_rsvd : 63; - bdrkreg_t ceb_cpu_enable : 1; - } pi_cpu_enable_b_fld_s; -} pi_cpu_enable_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. A write to this * - * location will cause an NMI to be issued to the CPU. * - * * - ************************************************************************/ - - - - -typedef union pi_nmi_a_u { - bdrkreg_t pi_nmi_a_regval; - struct { - bdrkreg_t na_nmi_cpu : 64; - } pi_nmi_a_fld_s; -} pi_nmi_a_u_t; - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. A write to this * - * location will cause an NMI to be issued to the CPU. * - * * - ************************************************************************/ - - - - -typedef union pi_nmi_b_u { - bdrkreg_t pi_nmi_b_regval; - struct { - bdrkreg_t nb_nmi_cpu : 64; - } pi_nmi_b_fld_s; -} pi_nmi_b_u_t; - - - - -/************************************************************************ - * * - * A write to this register allows a single bit in the INT_PEND0 or * - * INT_PEND1 registers to be set or cleared. If 6 is clear, a bit is * - * modified in INT_PEND0, while if 6 is set, a bit is modified in * - * INT_PEND1. The value in 5:0 (ranging from 63 to 0) will determine * - * which bit in the register is effected. The value of 8 will * - * determine whether the desired bit is set (8=1) or cleared (8=0). * - * This is the only register which is accessible by IO issued PWRI * - * command and is protected through the IO_PROTECT register. If the * - * region bit in the IO_PROTECT is not set then a WERR reply is * - * issued. CPU access is controlled through CPU_PROTECT. The contents * - * of this register are masked with the contents of INT_MASK_A * - * (INT_MASK_B) to determine whether an L2 interrupt is issued to * - * CPU_A (CPU_B). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_int_pend_mod_u { - bdrkreg_t pi_int_pend_mod_regval; - struct { - bdrkreg_t ipm_bit_select : 6; - bdrkreg_t ipm_reg_select : 1; - bdrkreg_t ipm_rsvd_1 : 1; - bdrkreg_t ipm_value : 1; - bdrkreg_t ipm_rsvd : 55; - } pi_int_pend_mod_fld_s; -} pi_int_pend_mod_u_t; - -#else - -typedef union pi_int_pend_mod_u { - bdrkreg_t pi_int_pend_mod_regval; - struct { - bdrkreg_t ipm_rsvd : 55; - bdrkreg_t ipm_value : 1; - bdrkreg_t ipm_rsvd_1 : 1; - bdrkreg_t ipm_reg_select : 1; - bdrkreg_t ipm_bit_select : 6; - } pi_int_pend_mod_fld_s; -} pi_int_pend_mod_u_t; - -#endif - - - - -/************************************************************************ - * * - * This read-only register provides information about interrupts * - * that are currently pending. The interrupts in this register map to * - * interrupt level 2 (L2). The GFX_INT_A/B bits are set by hardware * - * but must be cleared by software. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_int_pend0_u { - bdrkreg_t pi_int_pend0_regval; - struct { - bdrkreg_t ip_int_pend0_lo : 1; - bdrkreg_t ip_gfx_int_a : 1; - bdrkreg_t ip_gfx_int_b : 1; - bdrkreg_t ip_page_migration : 1; - bdrkreg_t ip_uart_ucntrl : 1; - bdrkreg_t ip_or_cc_pend_a : 1; - bdrkreg_t ip_or_cc_pend_b : 1; - bdrkreg_t ip_int_pend0_hi : 57; - } pi_int_pend0_fld_s; -} pi_int_pend0_u_t; - -#else - -typedef union pi_int_pend0_u { - bdrkreg_t pi_int_pend0_regval; - struct { - bdrkreg_t ip_int_pend0_hi : 57; - bdrkreg_t ip_or_cc_pend_b : 1; - bdrkreg_t ip_or_cc_pend_a : 1; - bdrkreg_t ip_uart_ucntrl : 1; - bdrkreg_t ip_page_migration : 1; - bdrkreg_t ip_gfx_int_b : 1; - bdrkreg_t ip_gfx_int_a : 1; - bdrkreg_t ip_int_pend0_lo : 1; - } pi_int_pend0_fld_s; -} pi_int_pend0_u_t; - -#endif - - - - -/************************************************************************ - * * - * This read-only register provides information about interrupts * - * that are currently pending. The interrupts in this register map to * - * interrupt level 3 (L3), unless remapped by the INT_PEND1_REMAP * - * register. The SYS_COR_ERR_A/B, RTC_DROP_OUT, and NACK_INT_A/B bits * - * are set by hardware but must be cleared by software. The * - * SYSTEM_SHUTDOWN, NI_ERROR, LB_ERROR and XB_ERROR bits just reflect * - * the value of other logic, and cannot be changed by PI register * - * writes. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_int_pend1_u { - bdrkreg_t pi_int_pend1_regval; - struct { - bdrkreg_t ip_int_pend1 : 54; - bdrkreg_t ip_xb_error : 1; - bdrkreg_t ip_lb_error : 1; - bdrkreg_t ip_nack_int_a : 1; - bdrkreg_t ip_nack_int_b : 1; - bdrkreg_t ip_perf_cntr_oflow : 1; - bdrkreg_t ip_sys_cor_err_b : 1; - bdrkreg_t ip_sys_cor_err_a : 1; - bdrkreg_t ip_md_corr_error : 1; - bdrkreg_t ip_ni_error : 1; - bdrkreg_t ip_system_shutdown : 1; - } pi_int_pend1_fld_s; -} pi_int_pend1_u_t; - -#else - -typedef union pi_int_pend1_u { - bdrkreg_t pi_int_pend1_regval; - struct { - bdrkreg_t ip_system_shutdown : 1; - bdrkreg_t ip_ni_error : 1; - bdrkreg_t ip_md_corr_error : 1; - bdrkreg_t ip_sys_cor_err_a : 1; - bdrkreg_t ip_sys_cor_err_b : 1; - bdrkreg_t ip_perf_cntr_oflow : 1; - bdrkreg_t ip_nack_int_b : 1; - bdrkreg_t ip_nack_int_a : 1; - bdrkreg_t ip_lb_error : 1; - bdrkreg_t ip_xb_error : 1; - bdrkreg_t ip_int_pend1 : 54; - } pi_int_pend1_fld_s; -} pi_int_pend1_u_t; - -#endif - - - - -/************************************************************************ - * * - * This read/write register masks the contents of INT_PEND0 to * - * determine whether an L2 interrupt (bit 10 of the processor's Cause * - * register) is sent to CPU_A if the same bit in the INT_PEND0 * - * register is also set. Only one processor in a Bedrock should * - * enable the PAGE_MIGRATION bit/interrupt. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_int_mask0_a_u { - bdrkreg_t pi_int_mask0_a_regval; - struct { - bdrkreg_t ima_int_mask0_lo : 1; - bdrkreg_t ima_gfx_int_a : 1; - bdrkreg_t ima_gfx_int_b : 1; - bdrkreg_t ima_page_migration : 1; - bdrkreg_t ima_uart_ucntrl : 1; - bdrkreg_t ima_or_ccp_mask_a : 1; - bdrkreg_t ima_or_ccp_mask_b : 1; - bdrkreg_t ima_int_mask0_hi : 57; - } pi_int_mask0_a_fld_s; -} pi_int_mask0_a_u_t; - -#else - -typedef union pi_int_mask0_a_u { - bdrkreg_t pi_int_mask0_a_regval; - struct { - bdrkreg_t ima_int_mask0_hi : 57; - bdrkreg_t ima_or_ccp_mask_b : 1; - bdrkreg_t ima_or_ccp_mask_a : 1; - bdrkreg_t ima_uart_ucntrl : 1; - bdrkreg_t ima_page_migration : 1; - bdrkreg_t ima_gfx_int_b : 1; - bdrkreg_t ima_gfx_int_a : 1; - bdrkreg_t ima_int_mask0_lo : 1; - } pi_int_mask0_a_fld_s; -} pi_int_mask0_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * This read/write register masks the contents of INT_PEND1 to * - * determine whether an interrupt should be sent. Bits 63:32 always * - * generate an L3 interrupt (bit 11 of the processor's Cause * - * register) is sent to CPU_A if the same bit in the INT_PEND1 * - * register is set. Bits 31:0 can generate either an L3 or L2 * - * interrupt, depending on the value of INT_PEND1_REMAP[3:0]. Only * - * one processor in a Bedrock should enable the NI_ERROR, LB_ERROR, * - * XB_ERROR and MD_CORR_ERROR bits. * - * * - ************************************************************************/ - - - - -typedef union pi_int_mask1_a_u { - bdrkreg_t pi_int_mask1_a_regval; - struct { - bdrkreg_t ima_int_mask1 : 64; - } pi_int_mask1_a_fld_s; -} pi_int_mask1_a_u_t; - - - - -/************************************************************************ - * * - * This read/write register masks the contents of INT_PEND0 to * - * determine whether an L2 interrupt (bit 10 of the processor's Cause * - * register) is sent to CPU_B if the same bit in the INT_PEND0 * - * register is also set. Only one processor in a Bedrock should * - * enable the PAGE_MIGRATION bit/interrupt. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_int_mask0_b_u { - bdrkreg_t pi_int_mask0_b_regval; - struct { - bdrkreg_t imb_int_mask0_lo : 1; - bdrkreg_t imb_gfx_int_a : 1; - bdrkreg_t imb_gfx_int_b : 1; - bdrkreg_t imb_page_migration : 1; - bdrkreg_t imb_uart_ucntrl : 1; - bdrkreg_t imb_or_ccp_mask_a : 1; - bdrkreg_t imb_or_ccp_mask_b : 1; - bdrkreg_t imb_int_mask0_hi : 57; - } pi_int_mask0_b_fld_s; -} pi_int_mask0_b_u_t; - -#else - -typedef union pi_int_mask0_b_u { - bdrkreg_t pi_int_mask0_b_regval; - struct { - bdrkreg_t imb_int_mask0_hi : 57; - bdrkreg_t imb_or_ccp_mask_b : 1; - bdrkreg_t imb_or_ccp_mask_a : 1; - bdrkreg_t imb_uart_ucntrl : 1; - bdrkreg_t imb_page_migration : 1; - bdrkreg_t imb_gfx_int_b : 1; - bdrkreg_t imb_gfx_int_a : 1; - bdrkreg_t imb_int_mask0_lo : 1; - } pi_int_mask0_b_fld_s; -} pi_int_mask0_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * This read/write register masks the contents of INT_PEND1 to * - * determine whether an interrupt should be sent. Bits 63:32 always * - * generate an L3 interrupt (bit 11 of the processor's Cause * - * register) is sent to CPU_B if the same bit in the INT_PEND1 * - * register is set. Bits 31:0 can generate either an L3 or L2 * - * interrupt, depending on the value of INT_PEND1_REMAP[3:0]. Only * - * one processor in a Bedrock should enable the NI_ERROR, LB_ERROR, * - * XB_ERROR and MD_CORR_ERROR bits. * - * * - ************************************************************************/ - - - - -typedef union pi_int_mask1_b_u { - bdrkreg_t pi_int_mask1_b_regval; - struct { - bdrkreg_t imb_int_mask1 : 64; - } pi_int_mask1_b_fld_s; -} pi_int_mask1_b_u_t; - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. These registers do * - * not have access protection. A store to this location by a CPU will * - * cause the bit corresponding to the source's region to be set in * - * CC_PEND_A (or CC_PEND_B). The contents of CC_PEND_A (or CC_PEND_B) * - * determines on a bit-per-region basis whether a CPU-to-CPU * - * interrupt is pending CPU_A (or CPU_B). * - * * - ************************************************************************/ - - - - -typedef union pi_cc_pend_set_a_u { - bdrkreg_t pi_cc_pend_set_a_regval; - struct { - bdrkreg_t cpsa_cc_pend : 64; - } pi_cc_pend_set_a_fld_s; -} pi_cc_pend_set_a_u_t; - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. These registers do * - * not have access protection. A store to this location by a CPU will * - * cause the bit corresponding to the source's region to be set in * - * CC_PEND_A (or CC_PEND_B). The contents of CC_PEND_A (or CC_PEND_B) * - * determines on a bit-per-region basis whether a CPU-to-CPU * - * interrupt is pending CPU_A (or CPU_B). * - * * - ************************************************************************/ - - - - -typedef union pi_cc_pend_set_b_u { - bdrkreg_t pi_cc_pend_set_b_regval; - struct { - bdrkreg_t cpsb_cc_pend : 64; - } pi_cc_pend_set_b_fld_s; -} pi_cc_pend_set_b_u_t; - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. Reading this * - * location will return the contents of CC_PEND_A (or CC_PEND_B). * - * Writing this location will clear the bits corresponding to which * - * data bits are driven high during the store; therefore, storing all * - * ones would clear all bits. * - * * - ************************************************************************/ - - - - -typedef union pi_cc_pend_clr_a_u { - bdrkreg_t pi_cc_pend_clr_a_regval; - struct { - bdrkreg_t cpca_cc_pend : 64; - } pi_cc_pend_clr_a_fld_s; -} pi_cc_pend_clr_a_u_t; - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. Reading this * - * location will return the contents of CC_PEND_A (or CC_PEND_B). * - * Writing this location will clear the bits corresponding to which * - * data bits are driven high during the store; therefore, storing all * - * ones would clear all bits. * - * * - ************************************************************************/ - - - - -typedef union pi_cc_pend_clr_b_u { - bdrkreg_t pi_cc_pend_clr_b_regval; - struct { - bdrkreg_t cpcb_cc_pend : 64; - } pi_cc_pend_clr_b_fld_s; -} pi_cc_pend_clr_b_u_t; - - - - -/************************************************************************ - * * - * This read/write register masks the contents of both CC_PEND_A and * - * CC_PEND_B. * - * * - ************************************************************************/ - - - - -typedef union pi_cc_mask_u { - bdrkreg_t pi_cc_mask_regval; - struct { - bdrkreg_t cm_cc_mask : 64; - } pi_cc_mask_fld_s; -} pi_cc_mask_u_t; - - - - -/************************************************************************ - * * - * This read/write register redirects INT_PEND1[31:0] from L3 to L2 * - * interrupt level.Bit 4 in this register is used to enable error * - * interrupt forwarding to the II. When this bit is set, if any of * - * the three memory interrupts (correctable error, uncorrectable * - * error, or page migration), or the NI, LB or XB error interrupts * - * are set, the PI_II_ERROR_INT wire will be asserted. When this wire * - * is asserted, the II will send an interrupt to the node specified * - * in its IIDSR (Interrupt Destination Register). This allows these * - * interrupts to be forwarded to another node. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_int_pend1_remap_u { - bdrkreg_t pi_int_pend1_remap_regval; - struct { - bdrkreg_t ipr_remap_0 : 1; - bdrkreg_t ipr_remap_1 : 1; - bdrkreg_t ipr_remap_2 : 1; - bdrkreg_t ipr_remap_3 : 1; - bdrkreg_t ipr_error_forward : 1; - bdrkreg_t ipr_reserved : 59; - } pi_int_pend1_remap_fld_s; -} pi_int_pend1_remap_u_t; - -#else - -typedef union pi_int_pend1_remap_u { - bdrkreg_t pi_int_pend1_remap_regval; - struct { - bdrkreg_t ipr_reserved : 59; - bdrkreg_t ipr_error_forward : 1; - bdrkreg_t ipr_remap_3 : 1; - bdrkreg_t ipr_remap_2 : 1; - bdrkreg_t ipr_remap_1 : 1; - bdrkreg_t ipr_remap_0 : 1; - } pi_int_pend1_remap_fld_s; -} pi_int_pend1_remap_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. When the real time * - * counter (RT_Counter) is equal to the value in this register, the * - * RT_INT_PEND register is set, which causes a Level-4 interrupt to * - * be sent to the processor. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_rt_compare_a_u { - bdrkreg_t pi_rt_compare_a_regval; - struct { - bdrkreg_t rca_rt_compare : 55; - bdrkreg_t rca_rsvd : 9; - } pi_rt_compare_a_fld_s; -} pi_rt_compare_a_u_t; - -#else - -typedef union pi_rt_compare_a_u { - bdrkreg_t pi_rt_compare_a_regval; - struct { - bdrkreg_t rca_rsvd : 9; - bdrkreg_t rca_rt_compare : 55; - } pi_rt_compare_a_fld_s; -} pi_rt_compare_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. When the real time * - * counter (RT_Counter) is equal to the value in this register, the * - * RT_INT_PEND register is set, which causes a Level-4 interrupt to * - * be sent to the processor. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_rt_compare_b_u { - bdrkreg_t pi_rt_compare_b_regval; - struct { - bdrkreg_t rcb_rt_compare : 55; - bdrkreg_t rcb_rsvd : 9; - } pi_rt_compare_b_fld_s; -} pi_rt_compare_b_u_t; - -#else - -typedef union pi_rt_compare_b_u { - bdrkreg_t pi_rt_compare_b_regval; - struct { - bdrkreg_t rcb_rsvd : 9; - bdrkreg_t rcb_rt_compare : 55; - } pi_rt_compare_b_fld_s; -} pi_rt_compare_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * When the least significant 32 bits of the real time counter * - * (RT_Counter) are equal to the value in this register, the * - * PROF_INT_PEND_A and PROF_INT_PEND_B registers are set to 0x1. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_profile_compare_u { - bdrkreg_t pi_profile_compare_regval; - struct { - bdrkreg_t pc_profile_compare : 32; - bdrkreg_t pc_rsvd : 32; - } pi_profile_compare_fld_s; -} pi_profile_compare_u_t; - -#else - -typedef union pi_profile_compare_u { - bdrkreg_t pi_profile_compare_regval; - struct { - bdrkreg_t pc_rsvd : 32; - bdrkreg_t pc_profile_compare : 32; - } pi_profile_compare_fld_s; -} pi_profile_compare_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. If the bit in the * - * corresponding RT_INT_EN_A/B register is set, the processor's level * - * 5 interrupt is set to the value of the RTC_INT_PEND bit in this * - * register. Storing any value to this location will clear the * - * RTC_INT_PEND bit in the register. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_rt_int_pend_a_u { - bdrkreg_t pi_rt_int_pend_a_regval; - struct { - bdrkreg_t ripa_rtc_int_pend : 1; - bdrkreg_t ripa_rsvd : 63; - } pi_rt_int_pend_a_fld_s; -} pi_rt_int_pend_a_u_t; - -#else - -typedef union pi_rt_int_pend_a_u { - bdrkreg_t pi_rt_int_pend_a_regval; - struct { - bdrkreg_t ripa_rsvd : 63; - bdrkreg_t ripa_rtc_int_pend : 1; - } pi_rt_int_pend_a_fld_s; -} pi_rt_int_pend_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. If the bit in the * - * corresponding RT_INT_EN_A/B register is set, the processor's level * - * 5 interrupt is set to the value of the RTC_INT_PEND bit in this * - * register. Storing any value to this location will clear the * - * RTC_INT_PEND bit in the register. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_rt_int_pend_b_u { - bdrkreg_t pi_rt_int_pend_b_regval; - struct { - bdrkreg_t ripb_rtc_int_pend : 1; - bdrkreg_t ripb_rsvd : 63; - } pi_rt_int_pend_b_fld_s; -} pi_rt_int_pend_b_u_t; - -#else - -typedef union pi_rt_int_pend_b_u { - bdrkreg_t pi_rt_int_pend_b_regval; - struct { - bdrkreg_t ripb_rsvd : 63; - bdrkreg_t ripb_rtc_int_pend : 1; - } pi_rt_int_pend_b_fld_s; -} pi_rt_int_pend_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. Both registers are * - * set when the PROFILE_COMPARE register is equal to bits [31:0] of * - * the RT_Counter. If the bit in the corresponding PROF_INT_EN_A/B * - * register is set, the processor's level 5 interrupt is set to the * - * value of the PROF_INT_PEND bit in this register. Storing any value * - * to this location will clear the PROF_INT_PEND bit in the register. * - * The reason for having A and B versions of this register is that * - * they need to be cleared independently. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_prof_int_pend_a_u { - bdrkreg_t pi_prof_int_pend_a_regval; - struct { - bdrkreg_t pipa_prof_int_pend : 1; - bdrkreg_t pipa_rsvd : 63; - } pi_prof_int_pend_a_fld_s; -} pi_prof_int_pend_a_u_t; - -#else - -typedef union pi_prof_int_pend_a_u { - bdrkreg_t pi_prof_int_pend_a_regval; - struct { - bdrkreg_t pipa_rsvd : 63; - bdrkreg_t pipa_prof_int_pend : 1; - } pi_prof_int_pend_a_fld_s; -} pi_prof_int_pend_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. Both registers are * - * set when the PROFILE_COMPARE register is equal to bits [31:0] of * - * the RT_Counter. If the bit in the corresponding PROF_INT_EN_A/B * - * register is set, the processor's level 5 interrupt is set to the * - * value of the PROF_INT_PEND bit in this register. Storing any value * - * to this location will clear the PROF_INT_PEND bit in the register. * - * The reason for having A and B versions of this register is that * - * they need to be cleared independently. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_prof_int_pend_b_u { - bdrkreg_t pi_prof_int_pend_b_regval; - struct { - bdrkreg_t pipb_prof_int_pend : 1; - bdrkreg_t pipb_rsvd : 63; - } pi_prof_int_pend_b_fld_s; -} pi_prof_int_pend_b_u_t; - -#else - -typedef union pi_prof_int_pend_b_u { - bdrkreg_t pi_prof_int_pend_b_regval; - struct { - bdrkreg_t pipb_rsvd : 63; - bdrkreg_t pipb_prof_int_pend : 1; - } pi_prof_int_pend_b_fld_s; -} pi_prof_int_pend_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. Enables RTC * - * interrupt to the associated CPU. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_rt_int_en_a_u { - bdrkreg_t pi_rt_int_en_a_regval; - struct { - bdrkreg_t riea_rtc_int_en : 1; - bdrkreg_t riea_rsvd : 63; - } pi_rt_int_en_a_fld_s; -} pi_rt_int_en_a_u_t; - -#else - -typedef union pi_rt_int_en_a_u { - bdrkreg_t pi_rt_int_en_a_regval; - struct { - bdrkreg_t riea_rsvd : 63; - bdrkreg_t riea_rtc_int_en : 1; - } pi_rt_int_en_a_fld_s; -} pi_rt_int_en_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. Enables RTC * - * interrupt to the associated CPU. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_rt_int_en_b_u { - bdrkreg_t pi_rt_int_en_b_regval; - struct { - bdrkreg_t rieb_rtc_int_en : 1; - bdrkreg_t rieb_rsvd : 63; - } pi_rt_int_en_b_fld_s; -} pi_rt_int_en_b_u_t; - -#else - -typedef union pi_rt_int_en_b_u { - bdrkreg_t pi_rt_int_en_b_regval; - struct { - bdrkreg_t rieb_rsvd : 63; - bdrkreg_t rieb_rtc_int_en : 1; - } pi_rt_int_en_b_fld_s; -} pi_rt_int_en_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. Enables profiling * - * interrupt to the associated CPU. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_prof_int_en_a_u { - bdrkreg_t pi_prof_int_en_a_regval; - struct { - bdrkreg_t piea_prof_int_en : 1; - bdrkreg_t piea_rsvd : 63; - } pi_prof_int_en_a_fld_s; -} pi_prof_int_en_a_u_t; - -#else - -typedef union pi_prof_int_en_a_u { - bdrkreg_t pi_prof_int_en_a_regval; - struct { - bdrkreg_t piea_rsvd : 63; - bdrkreg_t piea_prof_int_en : 1; - } pi_prof_int_en_a_fld_s; -} pi_prof_int_en_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. Enables profiling * - * interrupt to the associated CPU. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_prof_int_en_b_u { - bdrkreg_t pi_prof_int_en_b_regval; - struct { - bdrkreg_t pieb_prof_int_en : 1; - bdrkreg_t pieb_rsvd : 63; - } pi_prof_int_en_b_fld_s; -} pi_prof_int_en_b_u_t; - -#else - -typedef union pi_prof_int_en_b_u { - bdrkreg_t pi_prof_int_en_b_regval; - struct { - bdrkreg_t pieb_rsvd : 63; - bdrkreg_t pieb_prof_int_en : 1; - } pi_prof_int_en_b_fld_s; -} pi_prof_int_en_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register controls operation of the debug data from the PI, * - * along with Debug_Sel[2:0] from the Debug module. For some values * - * of Debug_Sel[2:0], the B_SEL bit selects whether the debug bits * - * are looking at the processor A or processor B logic. The remaining * - * bits select which signal(s) are ORed to create DebugData bits 31 * - * and 30 for all of the PI debug selections. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_debug_sel_u { - bdrkreg_t pi_debug_sel_regval; - struct { - bdrkreg_t ds_low_t5cc_a : 1; - bdrkreg_t ds_low_t5cc_b : 1; - bdrkreg_t ds_low_totcc_a : 1; - bdrkreg_t ds_low_totcc_b : 1; - bdrkreg_t ds_low_reqcc_a : 1; - bdrkreg_t ds_low_reqcc_b : 1; - bdrkreg_t ds_low_rplcc_a : 1; - bdrkreg_t ds_low_rplcc_b : 1; - bdrkreg_t ds_low_intcc : 1; - bdrkreg_t ds_low_perf_inc_a_0 : 1; - bdrkreg_t ds_low_perf_inc_a_1 : 1; - bdrkreg_t ds_low_perf_inc_b_0 : 1; - bdrkreg_t ds_low_perf_inc_b_1 : 1; - bdrkreg_t ds_high_t5cc_a : 1; - bdrkreg_t ds_high_t5cc_b : 1; - bdrkreg_t ds_high_totcc_a : 1; - bdrkreg_t ds_high_totcc_b : 1; - bdrkreg_t ds_high_reqcc_a : 1; - bdrkreg_t ds_high_reqcc_b : 1; - bdrkreg_t ds_high_rplcc_a : 1; - bdrkreg_t ds_high_rplcc_b : 1; - bdrkreg_t ds_high_intcc : 1; - bdrkreg_t ds_high_perf_inc_a_0 : 1; - bdrkreg_t ds_high_perf_inc_a_1 : 1; - bdrkreg_t ds_high_perf_inc_b_0 : 1; - bdrkreg_t ds_high_perf_inc_b_1 : 1; - bdrkreg_t ds_b_sel : 1; - bdrkreg_t ds_rsvd : 37; - } pi_debug_sel_fld_s; -} pi_debug_sel_u_t; - -#else - -typedef union pi_debug_sel_u { - bdrkreg_t pi_debug_sel_regval; - struct { - bdrkreg_t ds_rsvd : 37; - bdrkreg_t ds_b_sel : 1; - bdrkreg_t ds_high_perf_inc_b_1 : 1; - bdrkreg_t ds_high_perf_inc_b_0 : 1; - bdrkreg_t ds_high_perf_inc_a_1 : 1; - bdrkreg_t ds_high_perf_inc_a_0 : 1; - bdrkreg_t ds_high_intcc : 1; - bdrkreg_t ds_high_rplcc_b : 1; - bdrkreg_t ds_high_rplcc_a : 1; - bdrkreg_t ds_high_reqcc_b : 1; - bdrkreg_t ds_high_reqcc_a : 1; - bdrkreg_t ds_high_totcc_b : 1; - bdrkreg_t ds_high_totcc_a : 1; - bdrkreg_t ds_high_t5cc_b : 1; - bdrkreg_t ds_high_t5cc_a : 1; - bdrkreg_t ds_low_perf_inc_b_1 : 1; - bdrkreg_t ds_low_perf_inc_b_0 : 1; - bdrkreg_t ds_low_perf_inc_a_1 : 1; - bdrkreg_t ds_low_perf_inc_a_0 : 1; - bdrkreg_t ds_low_intcc : 1; - bdrkreg_t ds_low_rplcc_b : 1; - bdrkreg_t ds_low_rplcc_a : 1; - bdrkreg_t ds_low_reqcc_b : 1; - bdrkreg_t ds_low_reqcc_a : 1; - bdrkreg_t ds_low_totcc_b : 1; - bdrkreg_t ds_low_totcc_a : 1; - bdrkreg_t ds_low_t5cc_b : 1; - bdrkreg_t ds_low_t5cc_a : 1; - } pi_debug_sel_fld_s; -} pi_debug_sel_u_t; - -#endif - - -/************************************************************************ - * * - * A write to this register allows a single bit in the INT_PEND0 or * - * INT_PEND1 registers to be set or cleared. If 6 is clear, a bit is * - * modified in INT_PEND0, while if 6 is set, a bit is modified in * - * INT_PEND1. The value in 5:0 (ranging from 63 to 0) will determine * - * which bit in the register is effected. The value of 8 will * - * determine whether the desired bit is set (8=1) or cleared (8=0). * - * This is the only register which is accessible by IO issued PWRI * - * command and is protected through the IO_PROTECT register. If the * - * region bit in the IO_PROTECT is not set then a WERR reply is * - * issued. CPU access is controlled through CPU_PROTECT. The contents * - * of this register are masked with the contents of INT_MASK_A * - * (INT_MASK_B) to determine whether an L2 interrupt is issued to * - * CPU_A (CPU_B). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_int_pend_mod_alias_u { - bdrkreg_t pi_int_pend_mod_alias_regval; - struct { - bdrkreg_t ipma_bit_select : 6; - bdrkreg_t ipma_reg_select : 1; - bdrkreg_t ipma_rsvd_1 : 1; - bdrkreg_t ipma_value : 1; - bdrkreg_t ipma_rsvd : 55; - } pi_int_pend_mod_alias_fld_s; -} pi_int_pend_mod_alias_u_t; - -#else - -typedef union pi_int_pend_mod_alias_u { - bdrkreg_t pi_int_pend_mod_alias_regval; - struct { - bdrkreg_t ipma_rsvd : 55; - bdrkreg_t ipma_value : 1; - bdrkreg_t ipma_rsvd_1 : 1; - bdrkreg_t ipma_reg_select : 1; - bdrkreg_t ipma_bit_select : 6; - } pi_int_pend_mod_alias_fld_s; -} pi_int_pend_mod_alias_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. This register * - * specifies the value of the Graphics Page. Uncached writes into the * - * Graphics Page (with uncached attribute of IO) are done with GFXWS * - * commands rather than the normal PWRI commands. GFXWS commands are * - * tracked with the graphics credit counters. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_gfx_page_a_u { - bdrkreg_t pi_gfx_page_a_regval; - struct { - bdrkreg_t gpa_rsvd_1 : 17; - bdrkreg_t gpa_gfx_page_addr : 23; - bdrkreg_t gpa_en_gfx_page : 1; - bdrkreg_t gpa_rsvd : 23; - } pi_gfx_page_a_fld_s; -} pi_gfx_page_a_u_t; - -#else - -typedef union pi_gfx_page_a_u { - bdrkreg_t pi_gfx_page_a_regval; - struct { - bdrkreg_t gpa_rsvd : 23; - bdrkreg_t gpa_en_gfx_page : 1; - bdrkreg_t gpa_gfx_page_addr : 23; - bdrkreg_t gpa_rsvd_1 : 17; - } pi_gfx_page_a_fld_s; -} pi_gfx_page_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. This register * - * counts graphics credits. This counter is decremented for each * - * doubleword sent to graphics with GFXWS or GFXWL commands. It is * - * incremented for each doubleword acknowledge from graphics. When * - * this counter has a smaller value than the GFX_BIAS register, * - * SysWrRdy_L is deasserted, an interrupt is sent to the processor, * - * and SysWrRdy_L is allowed to be asserted again. This is the basic * - * mechanism for flow-controlling graphics writes. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_gfx_credit_cntr_a_u { - bdrkreg_t pi_gfx_credit_cntr_a_regval; - struct { - bdrkreg_t gcca_gfx_credit_cntr : 12; - bdrkreg_t gcca_rsvd : 52; - } pi_gfx_credit_cntr_a_fld_s; -} pi_gfx_credit_cntr_a_u_t; - -#else - -typedef union pi_gfx_credit_cntr_a_u { - bdrkreg_t pi_gfx_credit_cntr_a_regval; - struct { - bdrkreg_t gcca_rsvd : 52; - bdrkreg_t gcca_gfx_credit_cntr : 12; - } pi_gfx_credit_cntr_a_fld_s; -} pi_gfx_credit_cntr_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. When the graphics * - * credit counter is less than or equal to this value, a flow control * - * interrupt is sent. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_gfx_bias_a_u { - bdrkreg_t pi_gfx_bias_a_regval; - struct { - bdrkreg_t gba_gfx_bias : 12; - bdrkreg_t gba_rsvd : 52; - } pi_gfx_bias_a_fld_s; -} pi_gfx_bias_a_u_t; - -#else - -typedef union pi_gfx_bias_a_u { - bdrkreg_t pi_gfx_bias_a_regval; - struct { - bdrkreg_t gba_rsvd : 52; - bdrkreg_t gba_gfx_bias : 12; - } pi_gfx_bias_a_fld_s; -} pi_gfx_bias_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There is one of these registers for each CPU. When * - * this counter reaches the value of the GFX_INT_CMP register, an * - * interrupt is sent to the associated processor. At each clock * - * cycle, the value in this register can be changed by any one of the * - * following actions: * - * - Written by software. * - * - Loaded with the value of GFX_INT_CMP, when an interrupt, NMI, or * - * soft reset occurs, thus preventing an additional interrupt. * - * - Zeroed, when the GFX_CREDIT_CNTR rises above the bias value. * - * - Incremented (by one at each clock) for each clock that the * - * GFX_CREDIT_CNTR is less than or equal to zero. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_gfx_int_cntr_a_u { - bdrkreg_t pi_gfx_int_cntr_a_regval; - struct { - bdrkreg_t gica_gfx_int_cntr : 26; - bdrkreg_t gica_rsvd : 38; - } pi_gfx_int_cntr_a_fld_s; -} pi_gfx_int_cntr_a_u_t; - -#else - -typedef union pi_gfx_int_cntr_a_u { - bdrkreg_t pi_gfx_int_cntr_a_regval; - struct { - bdrkreg_t gica_rsvd : 38; - bdrkreg_t gica_gfx_int_cntr : 26; - } pi_gfx_int_cntr_a_fld_s; -} pi_gfx_int_cntr_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. The value in this * - * register is loaded into the GFX_INT_CNTR register when an * - * interrupt, NMI, or soft reset is sent to the processor. The value * - * in this register is compared to the value of GFX_INT_CNTR and an * - * interrupt is sent when they become equal. * - * * - ************************************************************************/ - - - - -#ifdef LINUX - -typedef union pi_gfx_int_cmp_a_u { - bdrkreg_t pi_gfx_int_cmp_a_regval; - struct { - bdrkreg_t gica_gfx_int_cmp : 26; - bdrkreg_t gica_rsvd : 38; - } pi_gfx_int_cmp_a_fld_s; -} pi_gfx_int_cmp_a_u_t; - -#else - -typedef union pi_gfx_int_cmp_a_u { - bdrkreg_t pi_gfx_int_cmp_a_regval; - struct { - bdrkreg_t gica_rsvd : 38; - bdrkreg_t gica_gfx_int_cmp : 26; - } pi_gfx_int_cmp_a_fld_s; -} pi_gfx_int_cmp_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. This register * - * specifies the value of the Graphics Page. Uncached writes into the * - * Graphics Page (with uncached attribute of IO) are done with GFXWS * - * commands rather than the normal PWRI commands. GFXWS commands are * - * tracked with the graphics credit counters. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_gfx_page_b_u { - bdrkreg_t pi_gfx_page_b_regval; - struct { - bdrkreg_t gpb_rsvd_1 : 17; - bdrkreg_t gpb_gfx_page_addr : 23; - bdrkreg_t gpb_en_gfx_page : 1; - bdrkreg_t gpb_rsvd : 23; - } pi_gfx_page_b_fld_s; -} pi_gfx_page_b_u_t; - -#else - -typedef union pi_gfx_page_b_u { - bdrkreg_t pi_gfx_page_b_regval; - struct { - bdrkreg_t gpb_rsvd : 23; - bdrkreg_t gpb_en_gfx_page : 1; - bdrkreg_t gpb_gfx_page_addr : 23; - bdrkreg_t gpb_rsvd_1 : 17; - } pi_gfx_page_b_fld_s; -} pi_gfx_page_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. This register * - * counts graphics credits. This counter is decremented for each * - * doubleword sent to graphics with GFXWS or GFXWL commands. It is * - * incremented for each doubleword acknowledge from graphics. When * - * this counter has a smaller value than the GFX_BIAS register, * - * SysWrRdy_L is deasserted, an interrupt is sent to the processor, * - * and SysWrRdy_L is allowed to be asserted again. This is the basic * - * mechanism for flow-controlling graphics writes. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_gfx_credit_cntr_b_u { - bdrkreg_t pi_gfx_credit_cntr_b_regval; - struct { - bdrkreg_t gccb_gfx_credit_cntr : 12; - bdrkreg_t gccb_rsvd : 52; - } pi_gfx_credit_cntr_b_fld_s; -} pi_gfx_credit_cntr_b_u_t; - -#else - -typedef union pi_gfx_credit_cntr_b_u { - bdrkreg_t pi_gfx_credit_cntr_b_regval; - struct { - bdrkreg_t gccb_rsvd : 52; - bdrkreg_t gccb_gfx_credit_cntr : 12; - } pi_gfx_credit_cntr_b_fld_s; -} pi_gfx_credit_cntr_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. When the graphics * - * credit counter is less than or equal to this value, a flow control * - * interrupt is sent. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_gfx_bias_b_u { - bdrkreg_t pi_gfx_bias_b_regval; - struct { - bdrkreg_t gbb_gfx_bias : 12; - bdrkreg_t gbb_rsvd : 52; - } pi_gfx_bias_b_fld_s; -} pi_gfx_bias_b_u_t; - -#else - -typedef union pi_gfx_bias_b_u { - bdrkreg_t pi_gfx_bias_b_regval; - struct { - bdrkreg_t gbb_rsvd : 52; - bdrkreg_t gbb_gfx_bias : 12; - } pi_gfx_bias_b_fld_s; -} pi_gfx_bias_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There is one of these registers for each CPU. When * - * this counter reaches the value of the GFX_INT_CMP register, an * - * interrupt is sent to the associated processor. At each clock * - * cycle, the value in this register can be changed by any one of the * - * following actions: * - * - Written by software. * - * - Loaded with the value of GFX_INT_CMP, when an interrupt, NMI, or * - * soft reset occurs, thus preventing an additional interrupt. * - * - Zeroed, when the GFX_CREDIT_CNTR rises above the bias value. * - * - Incremented (by one at each clock) for each clock that the * - * GFX_CREDIT_CNTR is less than or equal to zero. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_gfx_int_cntr_b_u { - bdrkreg_t pi_gfx_int_cntr_b_regval; - struct { - bdrkreg_t gicb_gfx_int_cntr : 26; - bdrkreg_t gicb_rsvd : 38; - } pi_gfx_int_cntr_b_fld_s; -} pi_gfx_int_cntr_b_u_t; - -#else - -typedef union pi_gfx_int_cntr_b_u { - bdrkreg_t pi_gfx_int_cntr_b_regval; - struct { - bdrkreg_t gicb_rsvd : 38; - bdrkreg_t gicb_gfx_int_cntr : 26; - } pi_gfx_int_cntr_b_fld_s; -} pi_gfx_int_cntr_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. The value in this * - * register is loaded into the GFX_INT_CNTR register when an * - * interrupt, NMI, or soft reset is sent to the processor. The value * - * in this register is compared to the value of GFX_INT_CNTR and an * - * interrupt is sent when they become equal. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_gfx_int_cmp_b_u { - bdrkreg_t pi_gfx_int_cmp_b_regval; - struct { - bdrkreg_t gicb_gfx_int_cmp : 26; - bdrkreg_t gicb_rsvd : 38; - } pi_gfx_int_cmp_b_fld_s; -} pi_gfx_int_cmp_b_u_t; - -#else - -typedef union pi_gfx_int_cmp_b_u { - bdrkreg_t pi_gfx_int_cmp_b_regval; - struct { - bdrkreg_t gicb_rsvd : 38; - bdrkreg_t gicb_gfx_int_cmp : 26; - } pi_gfx_int_cmp_b_fld_s; -} pi_gfx_int_cmp_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: A read of this register returns all sources of * - * Bedrock Error Interrupts. Storing to the write-with-clear location * - * clears any bit for which a one appears on the data bus. Storing to * - * the writable location does a direct write to all unreserved bits * - * (except for MEM_UNC). * - * In Synergy mode, the processor that is the source of the command * - * that got an error is independent of the A or B SysAD bus. So in * - * Synergy mode, Synergy provides the source processor number in bit * - * 52 of the SysAD bus in all commands. The PI saves this in the RRB * - * or WRB entry, and uses that value to determine which error bit (A * - * or B) to set, as well as which ERR_STATUS and spool registers to * - * use, for all error types in this register that are specified as an * - * error to CPU_A or CPU_B. * - * This register is not cleared at reset. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_int_pend_wr_u { - bdrkreg_t pi_err_int_pend_wr_regval; - struct { - bdrkreg_t eipw_spool_comp_b : 1; - bdrkreg_t eipw_spool_comp_a : 1; - bdrkreg_t eipw_spurious_b : 1; - bdrkreg_t eipw_spurious_a : 1; - bdrkreg_t eipw_wrb_terr_b : 1; - bdrkreg_t eipw_wrb_terr_a : 1; - bdrkreg_t eipw_wrb_werr_b : 1; - bdrkreg_t eipw_wrb_werr_a : 1; - bdrkreg_t eipw_sysstate_par_b : 1; - bdrkreg_t eipw_sysstate_par_a : 1; - bdrkreg_t eipw_sysad_data_ecc_b : 1; - bdrkreg_t eipw_sysad_data_ecc_a : 1; - bdrkreg_t eipw_sysad_addr_ecc_b : 1; - bdrkreg_t eipw_sysad_addr_ecc_a : 1; - bdrkreg_t eipw_syscmd_data_par_b : 1; - bdrkreg_t eipw_syscmd_data_par_a : 1; - bdrkreg_t eipw_syscmd_addr_par_b : 1; - bdrkreg_t eipw_syscmd_addr_par_a : 1; - bdrkreg_t eipw_spool_err_b : 1; - bdrkreg_t eipw_spool_err_a : 1; - bdrkreg_t eipw_ue_uncached_b : 1; - bdrkreg_t eipw_ue_uncached_a : 1; - bdrkreg_t eipw_sysstate_tag_b : 1; - bdrkreg_t eipw_sysstate_tag_a : 1; - bdrkreg_t eipw_mem_unc : 1; - bdrkreg_t eipw_sysad_bad_data_b : 1; - bdrkreg_t eipw_sysad_bad_data_a : 1; - bdrkreg_t eipw_ue_cached_b : 1; - bdrkreg_t eipw_ue_cached_a : 1; - bdrkreg_t eipw_pkt_len_err_b : 1; - bdrkreg_t eipw_pkt_len_err_a : 1; - bdrkreg_t eipw_irb_err_b : 1; - bdrkreg_t eipw_irb_err_a : 1; - bdrkreg_t eipw_irb_timeout_b : 1; - bdrkreg_t eipw_irb_timeout_a : 1; - bdrkreg_t eipw_rsvd : 29; - } pi_err_int_pend_wr_fld_s; -} pi_err_int_pend_wr_u_t; - -#else - -typedef union pi_err_int_pend_wr_u { - bdrkreg_t pi_err_int_pend_wr_regval; - struct { - bdrkreg_t eipw_rsvd : 29; - bdrkreg_t eipw_irb_timeout_a : 1; - bdrkreg_t eipw_irb_timeout_b : 1; - bdrkreg_t eipw_irb_err_a : 1; - bdrkreg_t eipw_irb_err_b : 1; - bdrkreg_t eipw_pkt_len_err_a : 1; - bdrkreg_t eipw_pkt_len_err_b : 1; - bdrkreg_t eipw_ue_cached_a : 1; - bdrkreg_t eipw_ue_cached_b : 1; - bdrkreg_t eipw_sysad_bad_data_a : 1; - bdrkreg_t eipw_sysad_bad_data_b : 1; - bdrkreg_t eipw_mem_unc : 1; - bdrkreg_t eipw_sysstate_tag_a : 1; - bdrkreg_t eipw_sysstate_tag_b : 1; - bdrkreg_t eipw_ue_uncached_a : 1; - bdrkreg_t eipw_ue_uncached_b : 1; - bdrkreg_t eipw_spool_err_a : 1; - bdrkreg_t eipw_spool_err_b : 1; - bdrkreg_t eipw_syscmd_addr_par_a : 1; - bdrkreg_t eipw_syscmd_addr_par_b : 1; - bdrkreg_t eipw_syscmd_data_par_a : 1; - bdrkreg_t eipw_syscmd_data_par_b : 1; - bdrkreg_t eipw_sysad_addr_ecc_a : 1; - bdrkreg_t eipw_sysad_addr_ecc_b : 1; - bdrkreg_t eipw_sysad_data_ecc_a : 1; - bdrkreg_t eipw_sysad_data_ecc_b : 1; - bdrkreg_t eipw_sysstate_par_a : 1; - bdrkreg_t eipw_sysstate_par_b : 1; - bdrkreg_t eipw_wrb_werr_a : 1; - bdrkreg_t eipw_wrb_werr_b : 1; - bdrkreg_t eipw_wrb_terr_a : 1; - bdrkreg_t eipw_wrb_terr_b : 1; - bdrkreg_t eipw_spurious_a : 1; - bdrkreg_t eipw_spurious_b : 1; - bdrkreg_t eipw_spool_comp_a : 1; - bdrkreg_t eipw_spool_comp_b : 1; - } pi_err_int_pend_wr_fld_s; -} pi_err_int_pend_wr_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: A read of this register returns all sources of * - * Bedrock Error Interrupts. Storing to the write-with-clear location * - * clears any bit for which a one appears on the data bus. Storing to * - * the writable location does a direct write to all unreserved bits * - * (except for MEM_UNC). * - * In Synergy mode, the processor that is the source of the command * - * that got an error is independent of the A or B SysAD bus. So in * - * Synergy mode, Synergy provides the source processor number in bit * - * 52 of the SysAD bus in all commands. The PI saves this in the RRB * - * or WRB entry, and uses that value to determine which error bit (A * - * or B) to set, as well as which ERR_STATUS and spool registers to * - * use, for all error types in this register that are specified as an * - * error to CPU_A or CPU_B. * - * This register is not cleared at reset. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_int_pend_u { - bdrkreg_t pi_err_int_pend_regval; - struct { - bdrkreg_t eip_spool_comp_b : 1; - bdrkreg_t eip_spool_comp_a : 1; - bdrkreg_t eip_spurious_b : 1; - bdrkreg_t eip_spurious_a : 1; - bdrkreg_t eip_wrb_terr_b : 1; - bdrkreg_t eip_wrb_terr_a : 1; - bdrkreg_t eip_wrb_werr_b : 1; - bdrkreg_t eip_wrb_werr_a : 1; - bdrkreg_t eip_sysstate_par_b : 1; - bdrkreg_t eip_sysstate_par_a : 1; - bdrkreg_t eip_sysad_data_ecc_b : 1; - bdrkreg_t eip_sysad_data_ecc_a : 1; - bdrkreg_t eip_sysad_addr_ecc_b : 1; - bdrkreg_t eip_sysad_addr_ecc_a : 1; - bdrkreg_t eip_syscmd_data_par_b : 1; - bdrkreg_t eip_syscmd_data_par_a : 1; - bdrkreg_t eip_syscmd_addr_par_b : 1; - bdrkreg_t eip_syscmd_addr_par_a : 1; - bdrkreg_t eip_spool_err_b : 1; - bdrkreg_t eip_spool_err_a : 1; - bdrkreg_t eip_ue_uncached_b : 1; - bdrkreg_t eip_ue_uncached_a : 1; - bdrkreg_t eip_sysstate_tag_b : 1; - bdrkreg_t eip_sysstate_tag_a : 1; - bdrkreg_t eip_mem_unc : 1; - bdrkreg_t eip_sysad_bad_data_b : 1; - bdrkreg_t eip_sysad_bad_data_a : 1; - bdrkreg_t eip_ue_cached_b : 1; - bdrkreg_t eip_ue_cached_a : 1; - bdrkreg_t eip_pkt_len_err_b : 1; - bdrkreg_t eip_pkt_len_err_a : 1; - bdrkreg_t eip_irb_err_b : 1; - bdrkreg_t eip_irb_err_a : 1; - bdrkreg_t eip_irb_timeout_b : 1; - bdrkreg_t eip_irb_timeout_a : 1; - bdrkreg_t eip_rsvd : 29; - } pi_err_int_pend_fld_s; -} pi_err_int_pend_u_t; - -#else - -typedef union pi_err_int_pend_u { - bdrkreg_t pi_err_int_pend_regval; - struct { - bdrkreg_t eip_rsvd : 29; - bdrkreg_t eip_irb_timeout_a : 1; - bdrkreg_t eip_irb_timeout_b : 1; - bdrkreg_t eip_irb_err_a : 1; - bdrkreg_t eip_irb_err_b : 1; - bdrkreg_t eip_pkt_len_err_a : 1; - bdrkreg_t eip_pkt_len_err_b : 1; - bdrkreg_t eip_ue_cached_a : 1; - bdrkreg_t eip_ue_cached_b : 1; - bdrkreg_t eip_sysad_bad_data_a : 1; - bdrkreg_t eip_sysad_bad_data_b : 1; - bdrkreg_t eip_mem_unc : 1; - bdrkreg_t eip_sysstate_tag_a : 1; - bdrkreg_t eip_sysstate_tag_b : 1; - bdrkreg_t eip_ue_uncached_a : 1; - bdrkreg_t eip_ue_uncached_b : 1; - bdrkreg_t eip_spool_err_a : 1; - bdrkreg_t eip_spool_err_b : 1; - bdrkreg_t eip_syscmd_addr_par_a : 1; - bdrkreg_t eip_syscmd_addr_par_b : 1; - bdrkreg_t eip_syscmd_data_par_a : 1; - bdrkreg_t eip_syscmd_data_par_b : 1; - bdrkreg_t eip_sysad_addr_ecc_a : 1; - bdrkreg_t eip_sysad_addr_ecc_b : 1; - bdrkreg_t eip_sysad_data_ecc_a : 1; - bdrkreg_t eip_sysad_data_ecc_b : 1; - bdrkreg_t eip_sysstate_par_a : 1; - bdrkreg_t eip_sysstate_par_b : 1; - bdrkreg_t eip_wrb_werr_a : 1; - bdrkreg_t eip_wrb_werr_b : 1; - bdrkreg_t eip_wrb_terr_a : 1; - bdrkreg_t eip_wrb_terr_b : 1; - bdrkreg_t eip_spurious_a : 1; - bdrkreg_t eip_spurious_b : 1; - bdrkreg_t eip_spool_comp_a : 1; - bdrkreg_t eip_spool_comp_b : 1; - } pi_err_int_pend_fld_s; -} pi_err_int_pend_u_t; - -#endif - - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. This read/write * - * register masks the contents of ERR_INT_PEND to determine which * - * conditions cause a Level-6 interrupt to CPU_A or CPU_B. A bit set * - * allows the interrupt. Only one processor in a Bedrock should * - * enable the Memory/Directory Uncorrectable Error bit. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_int_mask_a_u { - bdrkreg_t pi_err_int_mask_a_regval; - struct { - bdrkreg_t eima_mask : 35; - bdrkreg_t eima_rsvd : 29; - } pi_err_int_mask_a_fld_s; -} pi_err_int_mask_a_u_t; - -#else - -typedef union pi_err_int_mask_a_u { - bdrkreg_t pi_err_int_mask_a_regval; - struct { - bdrkreg_t eima_rsvd : 29; - bdrkreg_t eima_mask : 35; - } pi_err_int_mask_a_fld_s; -} pi_err_int_mask_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. This read/write * - * register masks the contents of ERR_INT_PEND to determine which * - * conditions cause a Level-6 interrupt to CPU_A or CPU_B. A bit set * - * allows the interrupt. Only one processor in a Bedrock should * - * enable the Memory/Directory Uncorrectable Error bit. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_int_mask_b_u { - bdrkreg_t pi_err_int_mask_b_regval; - struct { - bdrkreg_t eimb_mask : 35; - bdrkreg_t eimb_rsvd : 29; - } pi_err_int_mask_b_fld_s; -} pi_err_int_mask_b_u_t; - -#else - -typedef union pi_err_int_mask_b_u { - bdrkreg_t pi_err_int_mask_b_regval; - struct { - bdrkreg_t eimb_rsvd : 29; - bdrkreg_t eimb_mask : 35; - } pi_err_int_mask_b_fld_s; -} pi_err_int_mask_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There is one of these registers for each CPU. This * - * register is the address of the next write to the error stack. This * - * register is incremented after each such write. Only the low N bits * - * are incremented, where N is defined by the size of the error stack * - * specified in the ERR_STACK_SIZE register. * - * This register is not reset by a soft reset. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_stack_addr_a_u { - bdrkreg_t pi_err_stack_addr_a_regval; - struct { - bdrkreg_t esaa_rsvd_1 : 3; - bdrkreg_t esaa_addr : 30; - bdrkreg_t esaa_rsvd : 31; - } pi_err_stack_addr_a_fld_s; -} pi_err_stack_addr_a_u_t; - -#else - -typedef union pi_err_stack_addr_a_u { - bdrkreg_t pi_err_stack_addr_a_regval; - struct { - bdrkreg_t esaa_rsvd : 31; - bdrkreg_t esaa_addr : 30; - bdrkreg_t esaa_rsvd_1 : 3; - } pi_err_stack_addr_a_fld_s; -} pi_err_stack_addr_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: There is one of these registers for each CPU. This * - * register is the address of the next write to the error stack. This * - * register is incremented after each such write. Only the low N bits * - * are incremented, where N is defined by the size of the error stack * - * specified in the ERR_STACK_SIZE register. * - * This register is not reset by a soft reset. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_stack_addr_b_u { - bdrkreg_t pi_err_stack_addr_b_regval; - struct { - bdrkreg_t esab_rsvd_1 : 3; - bdrkreg_t esab_addr : 30; - bdrkreg_t esab_rsvd : 31; - } pi_err_stack_addr_b_fld_s; -} pi_err_stack_addr_b_u_t; - -#else - -typedef union pi_err_stack_addr_b_u { - bdrkreg_t pi_err_stack_addr_b_regval; - struct { - bdrkreg_t esab_rsvd : 31; - bdrkreg_t esab_addr : 30; - bdrkreg_t esab_rsvd_1 : 3; - } pi_err_stack_addr_b_fld_s; -} pi_err_stack_addr_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: Sets the size (number of 64-bit entries) in the * - * error stack that is spooled to local memory when an error occurs. * - * Table16 defines the format of each entry in the spooled error * - * stack. * - * This register is not reset by a soft reset. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_stack_size_u { - bdrkreg_t pi_err_stack_size_regval; - struct { - bdrkreg_t ess_size : 4; - bdrkreg_t ess_rsvd : 60; - } pi_err_stack_size_fld_s; -} pi_err_stack_size_u_t; - -#else - -typedef union pi_err_stack_size_u { - bdrkreg_t pi_err_stack_size_regval; - struct { - bdrkreg_t ess_rsvd : 60; - bdrkreg_t ess_size : 4; - } pi_err_stack_size_fld_s; -} pi_err_stack_size_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is not cleared at reset. Writing this register with * - * the Write-clear address (with any data) clears both the * - * ERR_STATUS0_A and ERR_STATUS1_A registers. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_status0_a_u { - bdrkreg_t pi_err_status0_a_regval; - struct { - bdrkreg_t esa_error_type : 3; - bdrkreg_t esa_proc_req_num : 3; - bdrkreg_t esa_supplemental : 11; - bdrkreg_t esa_cmd : 8; - bdrkreg_t esa_addr : 37; - bdrkreg_t esa_over_run : 1; - bdrkreg_t esa_valid : 1; - } pi_err_status0_a_fld_s; -} pi_err_status0_a_u_t; - -#else - -typedef union pi_err_status0_a_u { - bdrkreg_t pi_err_status0_a_regval; - struct { - bdrkreg_t esa_valid : 1; - bdrkreg_t esa_over_run : 1; - bdrkreg_t esa_addr : 37; - bdrkreg_t esa_cmd : 8; - bdrkreg_t esa_supplemental : 11; - bdrkreg_t esa_proc_req_num : 3; - bdrkreg_t esa_error_type : 3; - } pi_err_status0_a_fld_s; -} pi_err_status0_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is not cleared at reset. Writing this register with * - * the Write-clear address (with any data) clears both the * - * ERR_STATUS0_A and ERR_STATUS1_A registers. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_status0_a_clr_u { - bdrkreg_t pi_err_status0_a_clr_regval; - struct { - bdrkreg_t esac_error_type : 3; - bdrkreg_t esac_proc_req_num : 3; - bdrkreg_t esac_supplemental : 11; - bdrkreg_t esac_cmd : 8; - bdrkreg_t esac_addr : 37; - bdrkreg_t esac_over_run : 1; - bdrkreg_t esac_valid : 1; - } pi_err_status0_a_clr_fld_s; -} pi_err_status0_a_clr_u_t; - -#else - -typedef union pi_err_status0_a_clr_u { - bdrkreg_t pi_err_status0_a_clr_regval; - struct { - bdrkreg_t esac_valid : 1; - bdrkreg_t esac_over_run : 1; - bdrkreg_t esac_addr : 37; - bdrkreg_t esac_cmd : 8; - bdrkreg_t esac_supplemental : 11; - bdrkreg_t esac_proc_req_num : 3; - bdrkreg_t esac_error_type : 3; - } pi_err_status0_a_clr_fld_s; -} pi_err_status0_a_clr_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is not cleared at reset. Writing this register with * - * the Write-clear address (with any data) clears both the * - * ERR_STATUS0_A and ERR_STATUS1_A registers. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_status1_a_u { - bdrkreg_t pi_err_status1_a_regval; - struct { - bdrkreg_t esa_spool_count : 21; - bdrkreg_t esa_time_out_count : 8; - bdrkreg_t esa_inval_count : 10; - bdrkreg_t esa_crb_num : 3; - bdrkreg_t esa_wrb : 1; - bdrkreg_t esa_e_bits : 2; - bdrkreg_t esa_t_bit : 1; - bdrkreg_t esa_i_bit : 1; - bdrkreg_t esa_h_bit : 1; - bdrkreg_t esa_w_bit : 1; - bdrkreg_t esa_a_bit : 1; - bdrkreg_t esa_r_bit : 1; - bdrkreg_t esa_v_bit : 1; - bdrkreg_t esa_p_bit : 1; - bdrkreg_t esa_source : 11; - } pi_err_status1_a_fld_s; -} pi_err_status1_a_u_t; - -#else - -typedef union pi_err_status1_a_u { - bdrkreg_t pi_err_status1_a_regval; - struct { - bdrkreg_t esa_source : 11; - bdrkreg_t esa_p_bit : 1; - bdrkreg_t esa_v_bit : 1; - bdrkreg_t esa_r_bit : 1; - bdrkreg_t esa_a_bit : 1; - bdrkreg_t esa_w_bit : 1; - bdrkreg_t esa_h_bit : 1; - bdrkreg_t esa_i_bit : 1; - bdrkreg_t esa_t_bit : 1; - bdrkreg_t esa_e_bits : 2; - bdrkreg_t esa_wrb : 1; - bdrkreg_t esa_crb_num : 3; - bdrkreg_t esa_inval_count : 10; - bdrkreg_t esa_time_out_count : 8; - bdrkreg_t esa_spool_count : 21; - } pi_err_status1_a_fld_s; -} pi_err_status1_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is not cleared at reset. Writing this register with * - * the Write-clear address (with any data) clears both the * - * ERR_STATUS0_A and ERR_STATUS1_A registers. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_status1_a_clr_u { - bdrkreg_t pi_err_status1_a_clr_regval; - struct { - bdrkreg_t esac_spool_count : 21; - bdrkreg_t esac_time_out_count : 8; - bdrkreg_t esac_inval_count : 10; - bdrkreg_t esac_crb_num : 3; - bdrkreg_t esac_wrb : 1; - bdrkreg_t esac_e_bits : 2; - bdrkreg_t esac_t_bit : 1; - bdrkreg_t esac_i_bit : 1; - bdrkreg_t esac_h_bit : 1; - bdrkreg_t esac_w_bit : 1; - bdrkreg_t esac_a_bit : 1; - bdrkreg_t esac_r_bit : 1; - bdrkreg_t esac_v_bit : 1; - bdrkreg_t esac_p_bit : 1; - bdrkreg_t esac_source : 11; - } pi_err_status1_a_clr_fld_s; -} pi_err_status1_a_clr_u_t; - -#else - -typedef union pi_err_status1_a_clr_u { - bdrkreg_t pi_err_status1_a_clr_regval; - struct { - bdrkreg_t esac_source : 11; - bdrkreg_t esac_p_bit : 1; - bdrkreg_t esac_v_bit : 1; - bdrkreg_t esac_r_bit : 1; - bdrkreg_t esac_a_bit : 1; - bdrkreg_t esac_w_bit : 1; - bdrkreg_t esac_h_bit : 1; - bdrkreg_t esac_i_bit : 1; - bdrkreg_t esac_t_bit : 1; - bdrkreg_t esac_e_bits : 2; - bdrkreg_t esac_wrb : 1; - bdrkreg_t esac_crb_num : 3; - bdrkreg_t esac_inval_count : 10; - bdrkreg_t esac_time_out_count : 8; - bdrkreg_t esac_spool_count : 21; - } pi_err_status1_a_clr_fld_s; -} pi_err_status1_a_clr_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is not cleared at reset. Writing this register with * - * the Write-clear address (with any data) clears both the * - * ERR_STATUS0_B and ERR_STATUS1_B registers. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_status0_b_u { - bdrkreg_t pi_err_status0_b_regval; - struct { - bdrkreg_t esb_error_type : 3; - bdrkreg_t esb_proc_request_number : 3; - bdrkreg_t esb_supplemental : 11; - bdrkreg_t esb_cmd : 8; - bdrkreg_t esb_addr : 37; - bdrkreg_t esb_over_run : 1; - bdrkreg_t esb_valid : 1; - } pi_err_status0_b_fld_s; -} pi_err_status0_b_u_t; - -#else - -typedef union pi_err_status0_b_u { - bdrkreg_t pi_err_status0_b_regval; - struct { - bdrkreg_t esb_valid : 1; - bdrkreg_t esb_over_run : 1; - bdrkreg_t esb_addr : 37; - bdrkreg_t esb_cmd : 8; - bdrkreg_t esb_supplemental : 11; - bdrkreg_t esb_proc_request_number : 3; - bdrkreg_t esb_error_type : 3; - } pi_err_status0_b_fld_s; -} pi_err_status0_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is not cleared at reset. Writing this register with * - * the Write-clear address (with any data) clears both the * - * ERR_STATUS0_B and ERR_STATUS1_B registers. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_status0_b_clr_u { - bdrkreg_t pi_err_status0_b_clr_regval; - struct { - bdrkreg_t esbc_error_type : 3; - bdrkreg_t esbc_proc_request_number : 3; - bdrkreg_t esbc_supplemental : 11; - bdrkreg_t esbc_cmd : 8; - bdrkreg_t esbc_addr : 37; - bdrkreg_t esbc_over_run : 1; - bdrkreg_t esbc_valid : 1; - } pi_err_status0_b_clr_fld_s; -} pi_err_status0_b_clr_u_t; - -#else - -typedef union pi_err_status0_b_clr_u { - bdrkreg_t pi_err_status0_b_clr_regval; - struct { - bdrkreg_t esbc_valid : 1; - bdrkreg_t esbc_over_run : 1; - bdrkreg_t esbc_addr : 37; - bdrkreg_t esbc_cmd : 8; - bdrkreg_t esbc_supplemental : 11; - bdrkreg_t esbc_proc_request_number : 3; - bdrkreg_t esbc_error_type : 3; - } pi_err_status0_b_clr_fld_s; -} pi_err_status0_b_clr_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is not cleared at reset. Writing this register with * - * the Write-clear address (with any data) clears both the * - * ERR_STATUS0_B and ERR_STATUS1_B registers. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_status1_b_u { - bdrkreg_t pi_err_status1_b_regval; - struct { - bdrkreg_t esb_spool_count : 21; - bdrkreg_t esb_time_out_count : 8; - bdrkreg_t esb_inval_count : 10; - bdrkreg_t esb_crb_num : 3; - bdrkreg_t esb_wrb : 1; - bdrkreg_t esb_e_bits : 2; - bdrkreg_t esb_t_bit : 1; - bdrkreg_t esb_i_bit : 1; - bdrkreg_t esb_h_bit : 1; - bdrkreg_t esb_w_bit : 1; - bdrkreg_t esb_a_bit : 1; - bdrkreg_t esb_r_bit : 1; - bdrkreg_t esb_v_bit : 1; - bdrkreg_t esb_p_bit : 1; - bdrkreg_t esb_source : 11; - } pi_err_status1_b_fld_s; -} pi_err_status1_b_u_t; - -#else - -typedef union pi_err_status1_b_u { - bdrkreg_t pi_err_status1_b_regval; - struct { - bdrkreg_t esb_source : 11; - bdrkreg_t esb_p_bit : 1; - bdrkreg_t esb_v_bit : 1; - bdrkreg_t esb_r_bit : 1; - bdrkreg_t esb_a_bit : 1; - bdrkreg_t esb_w_bit : 1; - bdrkreg_t esb_h_bit : 1; - bdrkreg_t esb_i_bit : 1; - bdrkreg_t esb_t_bit : 1; - bdrkreg_t esb_e_bits : 2; - bdrkreg_t esb_wrb : 1; - bdrkreg_t esb_crb_num : 3; - bdrkreg_t esb_inval_count : 10; - bdrkreg_t esb_time_out_count : 8; - bdrkreg_t esb_spool_count : 21; - } pi_err_status1_b_fld_s; -} pi_err_status1_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is not cleared at reset. Writing this register with * - * the Write-clear address (with any data) clears both the * - * ERR_STATUS0_B and ERR_STATUS1_B registers. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_status1_b_clr_u { - bdrkreg_t pi_err_status1_b_clr_regval; - struct { - bdrkreg_t esbc_spool_count : 21; - bdrkreg_t esbc_time_out_count : 8; - bdrkreg_t esbc_inval_count : 10; - bdrkreg_t esbc_crb_num : 3; - bdrkreg_t esbc_wrb : 1; - bdrkreg_t esbc_e_bits : 2; - bdrkreg_t esbc_t_bit : 1; - bdrkreg_t esbc_i_bit : 1; - bdrkreg_t esbc_h_bit : 1; - bdrkreg_t esbc_w_bit : 1; - bdrkreg_t esbc_a_bit : 1; - bdrkreg_t esbc_r_bit : 1; - bdrkreg_t esbc_v_bit : 1; - bdrkreg_t esbc_p_bit : 1; - bdrkreg_t esbc_source : 11; - } pi_err_status1_b_clr_fld_s; -} pi_err_status1_b_clr_u_t; - -#else - -typedef union pi_err_status1_b_clr_u { - bdrkreg_t pi_err_status1_b_clr_regval; - struct { - bdrkreg_t esbc_source : 11; - bdrkreg_t esbc_p_bit : 1; - bdrkreg_t esbc_v_bit : 1; - bdrkreg_t esbc_r_bit : 1; - bdrkreg_t esbc_a_bit : 1; - bdrkreg_t esbc_w_bit : 1; - bdrkreg_t esbc_h_bit : 1; - bdrkreg_t esbc_i_bit : 1; - bdrkreg_t esbc_t_bit : 1; - bdrkreg_t esbc_e_bits : 2; - bdrkreg_t esbc_wrb : 1; - bdrkreg_t esbc_crb_num : 3; - bdrkreg_t esbc_inval_count : 10; - bdrkreg_t esbc_time_out_count : 8; - bdrkreg_t esbc_spool_count : 21; - } pi_err_status1_b_clr_fld_s; -} pi_err_status1_b_clr_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_spool_cmp_a_u { - bdrkreg_t pi_spool_cmp_a_regval; - struct { - bdrkreg_t sca_compare : 20; - bdrkreg_t sca_rsvd : 44; - } pi_spool_cmp_a_fld_s; -} pi_spool_cmp_a_u_t; - -#else - -typedef union pi_spool_cmp_a_u { - bdrkreg_t pi_spool_cmp_a_regval; - struct { - bdrkreg_t sca_rsvd : 44; - bdrkreg_t sca_compare : 20; - } pi_spool_cmp_a_fld_s; -} pi_spool_cmp_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_spool_cmp_b_u { - bdrkreg_t pi_spool_cmp_b_regval; - struct { - bdrkreg_t scb_compare : 20; - bdrkreg_t scb_rsvd : 44; - } pi_spool_cmp_b_fld_s; -} pi_spool_cmp_b_u_t; - -#else - -typedef union pi_spool_cmp_b_u { - bdrkreg_t pi_spool_cmp_b_regval; - struct { - bdrkreg_t scb_rsvd : 44; - bdrkreg_t scb_compare : 20; - } pi_spool_cmp_b_fld_s; -} pi_spool_cmp_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. A timeout can be * - * forced by writing one(s). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_crb_timeout_a_u { - bdrkreg_t pi_crb_timeout_a_regval; - struct { - bdrkreg_t cta_rrb : 4; - bdrkreg_t cta_wrb : 8; - bdrkreg_t cta_rsvd : 52; - } pi_crb_timeout_a_fld_s; -} pi_crb_timeout_a_u_t; - -#else - -typedef union pi_crb_timeout_a_u { - bdrkreg_t pi_crb_timeout_a_regval; - struct { - bdrkreg_t cta_rsvd : 52; - bdrkreg_t cta_wrb : 8; - bdrkreg_t cta_rrb : 4; - } pi_crb_timeout_a_fld_s; -} pi_crb_timeout_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. A timeout can be * - * forced by writing one(s). * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_crb_timeout_b_u { - bdrkreg_t pi_crb_timeout_b_regval; - struct { - bdrkreg_t ctb_rrb : 4; - bdrkreg_t ctb_wrb : 8; - bdrkreg_t ctb_rsvd : 52; - } pi_crb_timeout_b_fld_s; -} pi_crb_timeout_b_u_t; - -#else - -typedef union pi_crb_timeout_b_u { - bdrkreg_t pi_crb_timeout_b_regval; - struct { - bdrkreg_t ctb_rsvd : 52; - bdrkreg_t ctb_wrb : 8; - bdrkreg_t ctb_rrb : 4; - } pi_crb_timeout_b_fld_s; -} pi_crb_timeout_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register controls error checking and forwarding of SysAD * - * errors. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_sysad_errchk_en_u { - bdrkreg_t pi_sysad_errchk_en_regval; - struct { - bdrkreg_t see_ecc_gen_en : 1; - bdrkreg_t see_qual_gen_en : 1; - bdrkreg_t see_sadp_chk_en : 1; - bdrkreg_t see_cmdp_chk_en : 1; - bdrkreg_t see_state_chk_en : 1; - bdrkreg_t see_qual_chk_en : 1; - bdrkreg_t see_rsvd : 58; - } pi_sysad_errchk_en_fld_s; -} pi_sysad_errchk_en_u_t; - -#else - -typedef union pi_sysad_errchk_en_u { - bdrkreg_t pi_sysad_errchk_en_regval; - struct { - bdrkreg_t see_rsvd : 58; - bdrkreg_t see_qual_chk_en : 1; - bdrkreg_t see_state_chk_en : 1; - bdrkreg_t see_cmdp_chk_en : 1; - bdrkreg_t see_sadp_chk_en : 1; - bdrkreg_t see_qual_gen_en : 1; - bdrkreg_t see_ecc_gen_en : 1; - } pi_sysad_errchk_en_fld_s; -} pi_sysad_errchk_en_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. If any bit in this * - * register is set, then whenever reply data arrives with the UE * - * (uncorrectable error) indication set, the check-bits that are * - * generated and sent to the SysAD will be inverted corresponding to * - * the bits set in the register. This will also prevent the assertion * - * of the data quality indicator. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_force_bad_check_bit_a_u { - bdrkreg_t pi_force_bad_check_bit_a_regval; - struct { - bdrkreg_t fbcba_bad_check_bit : 8; - bdrkreg_t fbcba_rsvd : 56; - } pi_force_bad_check_bit_a_fld_s; -} pi_force_bad_check_bit_a_u_t; - -#else - -typedef union pi_force_bad_check_bit_a_u { - bdrkreg_t pi_force_bad_check_bit_a_regval; - struct { - bdrkreg_t fbcba_rsvd : 56; - bdrkreg_t fbcba_bad_check_bit : 8; - } pi_force_bad_check_bit_a_fld_s; -} pi_force_bad_check_bit_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. If any bit in this * - * register is set, then whenever reply data arrives with the UE * - * (uncorrectable error) indication set, the check-bits that are * - * generated and sent to the SysAD will be inverted corresponding to * - * the bits set in the register. This will also prevent the assertion * - * of the data quality indicator. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_force_bad_check_bit_b_u { - bdrkreg_t pi_force_bad_check_bit_b_regval; - struct { - bdrkreg_t fbcbb_bad_check_bit : 8; - bdrkreg_t fbcbb_rsvd : 56; - } pi_force_bad_check_bit_b_fld_s; -} pi_force_bad_check_bit_b_u_t; - -#else - -typedef union pi_force_bad_check_bit_b_u { - bdrkreg_t pi_force_bad_check_bit_b_regval; - struct { - bdrkreg_t fbcbb_rsvd : 56; - bdrkreg_t fbcbb_bad_check_bit : 8; - } pi_force_bad_check_bit_b_fld_s; -} pi_force_bad_check_bit_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. When a counter is * - * enabled, it increments each time a DNACK reply is received. The * - * counter is cleared when any other reply is received. The register * - * is cleared when the CNT_EN bit is zero. If a DNACK reply is * - * received when the counter equals the value in the NACK_CMP * - * register, the counter is cleared, an error response is sent to the * - * CPU instead of a nack response, and the NACK_INT_A/B bit is set in * - * INT_PEND1. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_nack_cnt_a_u { - bdrkreg_t pi_nack_cnt_a_regval; - struct { - bdrkreg_t nca_nack_cnt : 20; - bdrkreg_t nca_cnt_en : 1; - bdrkreg_t nca_rsvd : 43; - } pi_nack_cnt_a_fld_s; -} pi_nack_cnt_a_u_t; - -#else - -typedef union pi_nack_cnt_a_u { - bdrkreg_t pi_nack_cnt_a_regval; - struct { - bdrkreg_t nca_rsvd : 43; - bdrkreg_t nca_cnt_en : 1; - bdrkreg_t nca_nack_cnt : 20; - } pi_nack_cnt_a_fld_s; -} pi_nack_cnt_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * There is one of these registers for each CPU. When a counter is * - * enabled, it increments each time a DNACK reply is received. The * - * counter is cleared when any other reply is received. The register * - * is cleared when the CNT_EN bit is zero. If a DNACK reply is * - * received when the counter equals the value in the NACK_CMP * - * register, the counter is cleared, an error response is sent to the * - * CPU instead of a nack response, and the NACK_INT_A/B bit is set in * - * INT_PEND1. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_nack_cnt_b_u { - bdrkreg_t pi_nack_cnt_b_regval; - struct { - bdrkreg_t ncb_nack_cnt : 20; - bdrkreg_t ncb_cnt_en : 1; - bdrkreg_t ncb_rsvd : 43; - } pi_nack_cnt_b_fld_s; -} pi_nack_cnt_b_u_t; - -#else - -typedef union pi_nack_cnt_b_u { - bdrkreg_t pi_nack_cnt_b_regval; - struct { - bdrkreg_t ncb_rsvd : 43; - bdrkreg_t ncb_cnt_en : 1; - bdrkreg_t ncb_nack_cnt : 20; - } pi_nack_cnt_b_fld_s; -} pi_nack_cnt_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * The setting of this register affects both CPUs on this PI. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_nack_cmp_u { - bdrkreg_t pi_nack_cmp_regval; - struct { - bdrkreg_t nc_nack_cmp : 20; - bdrkreg_t nc_rsvd : 44; - } pi_nack_cmp_fld_s; -} pi_nack_cmp_u_t; - -#else - -typedef union pi_nack_cmp_u { - bdrkreg_t pi_nack_cmp_regval; - struct { - bdrkreg_t nc_rsvd : 44; - bdrkreg_t nc_nack_cmp : 20; - } pi_nack_cmp_fld_s; -} pi_nack_cmp_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register controls which errors are spooled. When a bit in * - * this register is set, the corresponding error is spooled. The * - * setting of this register affects both CPUs on this PI. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_spool_mask_u { - bdrkreg_t pi_spool_mask_regval; - struct { - bdrkreg_t sm_access_err : 1; - bdrkreg_t sm_uncached_err : 1; - bdrkreg_t sm_dir_err : 1; - bdrkreg_t sm_timeout_err : 1; - bdrkreg_t sm_poison_err : 1; - bdrkreg_t sm_nack_oflow_err : 1; - bdrkreg_t sm_rsvd : 58; - } pi_spool_mask_fld_s; -} pi_spool_mask_u_t; - -#else - -typedef union pi_spool_mask_u { - bdrkreg_t pi_spool_mask_regval; - struct { - bdrkreg_t sm_rsvd : 58; - bdrkreg_t sm_nack_oflow_err : 1; - bdrkreg_t sm_poison_err : 1; - bdrkreg_t sm_timeout_err : 1; - bdrkreg_t sm_dir_err : 1; - bdrkreg_t sm_uncached_err : 1; - bdrkreg_t sm_access_err : 1; - } pi_spool_mask_fld_s; -} pi_spool_mask_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is not cleared at reset. When the VALID bit is * - * zero, this register (along with SPURIOUS_HDR_1) will capture the * - * header of an incoming spurious message received from the XBar. A * - * spurious message is a message that does not match up with any of * - * the CRB entries. This is a read/write register, so it is cleared * - * by writing of all zeros. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_spurious_hdr_0_u { - bdrkreg_t pi_spurious_hdr_0_regval; - struct { - bdrkreg_t sh0_prev_valid_b : 1; - bdrkreg_t sh0_prev_valid_a : 1; - bdrkreg_t sh0_rsvd : 4; - bdrkreg_t sh0_supplemental : 11; - bdrkreg_t sh0_cmd : 8; - bdrkreg_t sh0_addr : 37; - bdrkreg_t sh0_tail : 1; - bdrkreg_t sh0_valid : 1; - } pi_spurious_hdr_0_fld_s; -} pi_spurious_hdr_0_u_t; - -#else - -typedef union pi_spurious_hdr_0_u { - bdrkreg_t pi_spurious_hdr_0_regval; - struct { - bdrkreg_t sh0_valid : 1; - bdrkreg_t sh0_tail : 1; - bdrkreg_t sh0_addr : 37; - bdrkreg_t sh0_cmd : 8; - bdrkreg_t sh0_supplemental : 11; - bdrkreg_t sh0_rsvd : 4; - bdrkreg_t sh0_prev_valid_a : 1; - bdrkreg_t sh0_prev_valid_b : 1; - } pi_spurious_hdr_0_fld_s; -} pi_spurious_hdr_0_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is not cleared at reset. When the VALID bit in * - * SPURIOUS_HDR_0 is zero, this register (along with SPURIOUS_HDR_0) * - * will capture the header of an incoming spurious message received * - * from the XBar. A spurious message is a message that does not match * - * up with any of the CRB entries. This is a read/write register, so * - * it is cleared by writing of all zeros. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_spurious_hdr_1_u { - bdrkreg_t pi_spurious_hdr_1_regval; - struct { - bdrkreg_t sh1_rsvd : 53; - bdrkreg_t sh1_source : 11; - } pi_spurious_hdr_1_fld_s; -} pi_spurious_hdr_1_u_t; - -#else - -typedef union pi_spurious_hdr_1_u { - bdrkreg_t pi_spurious_hdr_1_regval; - struct { - bdrkreg_t sh1_source : 11; - bdrkreg_t sh1_rsvd : 53; - } pi_spurious_hdr_1_fld_s; -} pi_spurious_hdr_1_u_t; - -#endif - - - - -/************************************************************************ - * * - * Description: This register controls the injection of errors in * - * outbound SysAD transfers. When a write sets a bit in this * - * register, the PI logic is "armed" to inject that error. At the * - * first transfer of the specified type, the error is injected and * - * the bit in this register is cleared. Writing to this register does * - * not cause a transaction to occur. A bit in this register will * - * remain set until a transaction of the specified type occurs as a * - * result of normal system activity. This register can be polled to * - * determine if an error has been injected or is still "armed". * - * This register does not control injection of data quality bad * - * indicator on a data cycle. This type of error can be created by * - * reading from a memory location that has an uncorrectable ECC * - * error. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_err_inject_u { - bdrkreg_t pi_err_inject_regval; - struct { - bdrkreg_t ei_cmd_syscmd_par_a : 1; - bdrkreg_t ei_data_syscmd_par_a : 1; - bdrkreg_t ei_cmd_sysad_corecc_a : 1; - bdrkreg_t ei_data_sysad_corecc_a : 1; - bdrkreg_t ei_cmd_sysad_uncecc_a : 1; - bdrkreg_t ei_data_sysad_uncecc_a : 1; - bdrkreg_t ei_sysresp_par_a : 1; - bdrkreg_t ei_reserved_1 : 25; - bdrkreg_t ei_cmd_syscmd_par_b : 1; - bdrkreg_t ei_data_syscmd_par_b : 1; - bdrkreg_t ei_cmd_sysad_corecc_b : 1; - bdrkreg_t ei_data_sysad_corecc_b : 1; - bdrkreg_t ei_cmd_sysad_uncecc_b : 1; - bdrkreg_t ei_data_sysad_uncecc_b : 1; - bdrkreg_t ei_sysresp_par_b : 1; - bdrkreg_t ei_reserved : 25; - } pi_err_inject_fld_s; -} pi_err_inject_u_t; - -#else - -typedef union pi_err_inject_u { - bdrkreg_t pi_err_inject_regval; - struct { - bdrkreg_t ei_reserved : 25; - bdrkreg_t ei_sysresp_par_b : 1; - bdrkreg_t ei_data_sysad_uncecc_b : 1; - bdrkreg_t ei_cmd_sysad_uncecc_b : 1; - bdrkreg_t ei_data_sysad_corecc_b : 1; - bdrkreg_t ei_cmd_sysad_corecc_b : 1; - bdrkreg_t ei_data_syscmd_par_b : 1; - bdrkreg_t ei_cmd_syscmd_par_b : 1; - bdrkreg_t ei_reserved_1 : 25; - bdrkreg_t ei_sysresp_par_a : 1; - bdrkreg_t ei_data_sysad_uncecc_a : 1; - bdrkreg_t ei_cmd_sysad_uncecc_a : 1; - bdrkreg_t ei_data_sysad_corecc_a : 1; - bdrkreg_t ei_cmd_sysad_corecc_a : 1; - bdrkreg_t ei_data_syscmd_par_a : 1; - bdrkreg_t ei_cmd_syscmd_par_a : 1; - } pi_err_inject_fld_s; -} pi_err_inject_u_t; - -#endif - - - - -/************************************************************************ - * * - * This Read/Write location determines at what point the TRex+ is * - * stopped from issuing requests, based on the number of entries in * - * the incoming reply FIFO. When the number of entries in the Reply * - * FIFO is greater than the value of this register, the PI will * - * deassert both SysWrRdy and SysRdRdy to both processors. The Reply * - * FIFO has a depth of 0x3F entries, so setting this register to 0x3F * - * effectively disables this feature, allowing requests to be issued * - * always. Setting this register to 0x00 effectively lowers the * - * TRex+'s priority below the reply FIFO, disabling TRex+ requests * - * any time there is an entry waiting in the incoming FIFO.This * - * register is in its own 64KB page so that it can be mapped to user * - * space. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_reply_level_u { - bdrkreg_t pi_reply_level_regval; - struct { - bdrkreg_t rl_reply_level : 6; - bdrkreg_t rl_rsvd : 58; - } pi_reply_level_fld_s; -} pi_reply_level_u_t; - -#else - -typedef union pi_reply_level_u { - bdrkreg_t pi_reply_level_regval; - struct { - bdrkreg_t rl_rsvd : 58; - bdrkreg_t rl_reply_level : 6; - } pi_reply_level_fld_s; -} pi_reply_level_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register is used to change the graphics credit counter * - * operation from "Doubleword" mode to "Transaction" mode. This * - * register is in its own 64KB page so that it can be mapped to user * - * space. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_gfx_credit_mode_u { - bdrkreg_t pi_gfx_credit_mode_regval; - struct { - bdrkreg_t gcm_trans_mode : 1; - bdrkreg_t gcm_rsvd : 63; - } pi_gfx_credit_mode_fld_s; -} pi_gfx_credit_mode_u_t; - -#else - -typedef union pi_gfx_credit_mode_u { - bdrkreg_t pi_gfx_credit_mode_regval; - struct { - bdrkreg_t gcm_rsvd : 63; - bdrkreg_t gcm_trans_mode : 1; - } pi_gfx_credit_mode_fld_s; -} pi_gfx_credit_mode_u_t; - -#endif - - - -/************************************************************************ - * * - * This location contains a 55-bit read/write counter that wraps to * - * zero when the maximum value is reached. This counter is * - * incremented at each rising edge of the global clock (GCLK). This * - * register is in its own 64KB page so that it can be mapped to user * - * space. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_rt_counter_u { - bdrkreg_t pi_rt_counter_regval; - struct { - bdrkreg_t rc_count : 55; - bdrkreg_t rc_rsvd : 9; - } pi_rt_counter_fld_s; -} pi_rt_counter_u_t; - -#else - -typedef union pi_rt_counter_u { - bdrkreg_t pi_rt_counter_regval; - struct { - bdrkreg_t rc_rsvd : 9; - bdrkreg_t rc_count : 55; - } pi_rt_counter_fld_s; -} pi_rt_counter_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register controls the performance counters for one CPU. * - * There are two counters for each CPU. Each counter can be * - * configured to count a variety of events. The performance counter * - * registers for each processor are in their own 64KB page so that * - * they can be mapped to user space. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_perf_cntl_a_u { - bdrkreg_t pi_perf_cntl_a_regval; - struct { - bdrkreg_t pca_cntr_0_select : 28; - bdrkreg_t pca_cntr_0_mode : 3; - bdrkreg_t pca_cntr_0_enable : 1; - bdrkreg_t pca_cntr_1_select : 28; - bdrkreg_t pca_cntr_1_mode : 3; - bdrkreg_t pca_cntr_1_enable : 1; - } pi_perf_cntl_a_fld_s; -} pi_perf_cntl_a_u_t; - -#else - -typedef union pi_perf_cntl_a_u { - bdrkreg_t pi_perf_cntl_a_regval; - struct { - bdrkreg_t pca_cntr_1_enable : 1; - bdrkreg_t pca_cntr_1_mode : 3; - bdrkreg_t pca_cntr_1_select : 28; - bdrkreg_t pca_cntr_0_enable : 1; - bdrkreg_t pca_cntr_0_mode : 3; - bdrkreg_t pca_cntr_0_select : 28; - } pi_perf_cntl_a_fld_s; -} pi_perf_cntl_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register accesses the performance counter 0 for each CPU. * - * Each performance counter is 40-bits wide. On overflow, It wraps to * - * zero, sets the overflow bit in this register, and sets the * - * PERF_CNTR_OFLOW bit in the INT_PEND1 register. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_perf_cntr0_a_u { - bdrkreg_t pi_perf_cntr0_a_regval; - struct { - bdrkreg_t pca_count_value : 40; - bdrkreg_t pca_overflow : 1; - bdrkreg_t pca_rsvd : 23; - } pi_perf_cntr0_a_fld_s; -} pi_perf_cntr0_a_u_t; - -#else - -typedef union pi_perf_cntr0_a_u { - bdrkreg_t pi_perf_cntr0_a_regval; - struct { - bdrkreg_t pca_rsvd : 23; - bdrkreg_t pca_overflow : 1; - bdrkreg_t pca_count_value : 40; - } pi_perf_cntr0_a_fld_s; -} pi_perf_cntr0_a_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register accesses the performance counter 1for each CPU. * - * Each performance counter is 40-bits wide. On overflow, It wraps to * - * zero, sets the overflow bit in this register, and sets the * - * PERF_CNTR_OFLOW bit in the INT_PEND1 register. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_perf_cntr1_a_u { - bdrkreg_t pi_perf_cntr1_a_regval; - struct { - bdrkreg_t pca_count_value : 40; - bdrkreg_t pca_overflow : 1; - bdrkreg_t pca_rsvd : 23; - } pi_perf_cntr1_a_fld_s; -} pi_perf_cntr1_a_u_t; - -#else - -typedef union pi_perf_cntr1_a_u { - bdrkreg_t pi_perf_cntr1_a_regval; - struct { - bdrkreg_t pca_rsvd : 23; - bdrkreg_t pca_overflow : 1; - bdrkreg_t pca_count_value : 40; - } pi_perf_cntr1_a_fld_s; -} pi_perf_cntr1_a_u_t; - -#endif - - - - - -/************************************************************************ - * * - * This register controls the performance counters for one CPU. * - * There are two counters for each CPU. Each counter can be * - * configured to count a variety of events. The performance counter * - * registers for each processor are in their own 64KB page so that * - * they can be mapped to user space. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_perf_cntl_b_u { - bdrkreg_t pi_perf_cntl_b_regval; - struct { - bdrkreg_t pcb_cntr_0_select : 28; - bdrkreg_t pcb_cntr_0_mode : 3; - bdrkreg_t pcb_cntr_0_enable : 1; - bdrkreg_t pcb_cntr_1_select : 28; - bdrkreg_t pcb_cntr_1_mode : 3; - bdrkreg_t pcb_cntr_1_enable : 1; - } pi_perf_cntl_b_fld_s; -} pi_perf_cntl_b_u_t; - -#else - -typedef union pi_perf_cntl_b_u { - bdrkreg_t pi_perf_cntl_b_regval; - struct { - bdrkreg_t pcb_cntr_1_enable : 1; - bdrkreg_t pcb_cntr_1_mode : 3; - bdrkreg_t pcb_cntr_1_select : 28; - bdrkreg_t pcb_cntr_0_enable : 1; - bdrkreg_t pcb_cntr_0_mode : 3; - bdrkreg_t pcb_cntr_0_select : 28; - } pi_perf_cntl_b_fld_s; -} pi_perf_cntl_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register accesses the performance counter 0 for each CPU. * - * Each performance counter is 40-bits wide. On overflow, It wraps to * - * zero, sets the overflow bit in this register, and sets the * - * PERF_CNTR_OFLOW bit in the INT_PEND1 register. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_perf_cntr0_b_u { - bdrkreg_t pi_perf_cntr0_b_regval; - struct { - bdrkreg_t pcb_count_value : 40; - bdrkreg_t pcb_overflow : 1; - bdrkreg_t pcb_rsvd : 23; - } pi_perf_cntr0_b_fld_s; -} pi_perf_cntr0_b_u_t; - -#else - -typedef union pi_perf_cntr0_b_u { - bdrkreg_t pi_perf_cntr0_b_regval; - struct { - bdrkreg_t pcb_rsvd : 23; - bdrkreg_t pcb_overflow : 1; - bdrkreg_t pcb_count_value : 40; - } pi_perf_cntr0_b_fld_s; -} pi_perf_cntr0_b_u_t; - -#endif - - - - -/************************************************************************ - * * - * This register accesses the performance counter 1for each CPU. * - * Each performance counter is 40-bits wide. On overflow, It wraps to * - * zero, sets the overflow bit in this register, and sets the * - * PERF_CNTR_OFLOW bit in the INT_PEND1 register. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union pi_perf_cntr1_b_u { - bdrkreg_t pi_perf_cntr1_b_regval; - struct { - bdrkreg_t pcb_count_value : 40; - bdrkreg_t pcb_overflow : 1; - bdrkreg_t pcb_rsvd : 23; - } pi_perf_cntr1_b_fld_s; -} pi_perf_cntr1_b_u_t; - -#else - -typedef union pi_perf_cntr1_b_u { - bdrkreg_t pi_perf_cntr1_b_regval; - struct { - bdrkreg_t pcb_rsvd : 23; - bdrkreg_t pcb_overflow : 1; - bdrkreg_t pcb_count_value : 40; - } pi_perf_cntr1_b_fld_s; -} pi_perf_cntr1_b_u_t; - -#endif - - - - - - -#endif /* __ASSEMBLY__ */ - -/************************************************************************ - * * - * MAKE ALL ADDITIONS AFTER THIS LINE * - * * - ************************************************************************/ - - -#define PI_GFX_OFFSET (PI_GFX_PAGE_B - PI_GFX_PAGE_A) -#define PI_GFX_PAGE_ENABLE 0x0000010000000000LL - - -#endif /* _ASM_IA64_SN_SN1_HUBPI_H */ diff --git a/include/asm-ia64/sn/sn1/hubpi_next.h b/include/asm-ia64/sn/sn1/hubpi_next.h deleted file mode 100644 index a4ea9f3277ba3..0000000000000 --- a/include/asm-ia64/sn/sn1/hubpi_next.h +++ /dev/null @@ -1,331 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_HUBPI_NEXT_H -#define _ASM_IA64_SN_SN1_HUBPI_NEXT_H - - -/* define for remote PI_1 space. It is always half of a node_addressspace - * from PI_0. The normal REMOTE_HUB space for PI registers access - * the PI_0 space, unless they are qualified by PI_1. - */ -#define PI_0(x) (x) -#define PI_1(x) ((x) + 0x200000) -#define PIREG(x,sn) ((sn) ? PI_1(x) : PI_0(x)) - -#define PI_MIN_STACK_SIZE 4096 /* For figuring out the size to set */ -#define PI_STACK_SIZE_SHFT 12 /* 4k */ - -#define PI_STACKADDR_OFFSET (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A) -#define PI_ERRSTAT_OFFSET (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A) -#define PI_RDCLR_OFFSET (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A) -/* these macros are correct, but fix their users to understand two PIs - and 4 CPUs (slices) per bedrock */ -#define PI_INT_MASK_OFFSET (PI_INT_MASK0_B - PI_INT_MASK0_A) -#define PI_INT_SET_OFFSET (PI_CC_PEND_CLR_B - PI_CC_PEND_CLR_A) -#define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A) - -#define ERR_STACK_SIZE_BYTES(_sz) \ - ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0) - -#define PI_CRB_STS_P (1 << 9) /* "P" (partial word read/write) bit */ -#define PI_CRB_STS_V (1 << 8) /* "V" (valid) bit */ -#define PI_CRB_STS_R (1 << 7) /* "R" (response data sent to CPU) */ -#define PI_CRB_STS_A (1 << 6) /* "A" (data ack. received) bit */ -#define PI_CRB_STS_W (1 << 5) /* "W" (waiting for write compl.) */ -#define PI_CRB_STS_H (1 << 4) /* "H" (gathering invalidates) bit */ -#define PI_CRB_STS_I (1 << 3) /* "I" (targ. inbound invalidate) */ -#define PI_CRB_STS_T (1 << 2) /* "T" (targ. inbound intervention) */ -#define PI_CRB_STS_E (0x3) /* "E" (coherent read type) */ - -/* When the "P" bit is set in the sk_crb_sts field of an error stack - * entry, the "R," "A," "H," and "I" bits are actually bits 6..3 of - * the address. This macro extracts those address bits and shifts - * them to their proper positions, ready to be ORed in to the rest of - * the address (which is calculated as sk_addr << 7). - */ -#define PI_CRB_STS_ADDR_BITS(sts) \ - ((sts) & (PI_CRB_STS_I | PI_CRB_STS_H) | \ - ((sts) & (PI_CRB_STS_A | PI_CRB_STS_R)) >> 1) - -#ifndef __ASSEMBLY__ -/* - * format of error stack and error status registers. - */ - -#ifdef LITTLE_ENDIAN - -struct err_stack_format { - uint64_t sk_err_type: 3, /* error type */ - sk_suppl : 3, /* lowest 3 bit of supplemental */ - sk_t5_req : 3, /* RRB T5 request number */ - sk_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ - sk_rw_rb : 1, /* RRB == 0, WRB == 1 */ - sk_crb_sts : 10, /* status from RRB or WRB */ - sk_cmd : 8, /* message command */ - sk_addr : 33; /* address */ -}; - -#else - -struct err_stack_format { - uint64_t sk_addr : 33, /* address */ - sk_cmd : 8, /* message command */ - sk_crb_sts : 10, /* status from RRB or WRB */ - sk_rw_rb : 1, /* RRB == 0, WRB == 1 */ - sk_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ - sk_t5_req : 3, /* RRB T5 request number */ - sk_suppl : 3, /* lowest 3 bit of supplemental */ - sk_err_type: 3; /* error type */ -}; - -#endif - -typedef union pi_err_stack { - uint64_t pi_stk_word; - struct err_stack_format pi_stk_fmt; -} pi_err_stack_t; - -/* Simplified version of pi_err_status0_a_u_t (PI_ERR_STATUS0_A) */ -#ifdef LITTLE_ENDIAN - -struct err_status0_format { - uint64_t s0_err_type : 3, /* Encoded error cause */ - s0_proc_req_num : 3, /* Request number for RRB only */ - s0_supplemental : 11, /* ncoming message sup field */ - s0_cmd : 8, /* Incoming message command */ - s0_addr : 37, /* Address */ - s0_over_run : 1, /* Subsequent errors spooled */ - s0_valid : 1; /* error is valid */ -}; - -#else - -struct err_status0_format { - uint64_t s0_valid : 1, /* error is valid */ - s0_over_run : 1, /* Subsequent errors spooled */ - s0_addr : 37, /* Address */ - s0_cmd : 8, /* Incoming message command */ - s0_supplemental : 11, /* ncoming message sup field */ - s0_proc_req_num : 3, /* Request number for RRB only */ - s0_err_type : 3; /* Encoded error cause */ -}; - -#endif - - -typedef union pi_err_stat0 { - uint64_t pi_stat0_word; - struct err_status0_format pi_stat0_fmt; -} pi_err_stat0_t; - -/* Simplified version of pi_err_status1_a_u_t (PI_ERR_STATUS1_A) */ - -#ifdef LITTLE_ENDIAN - -struct err_status1_format { - uint64_t s1_spl_cnt : 21, /* number spooled to memory */ - s1_to_cnt : 8, /* crb timeout counter */ - s1_inval_cnt:10, /* signed invalidate counter RRB */ - s1_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ - s1_rw_rb : 1, /* RRB == 0, WRB == 1 */ - s1_crb_sts : 10, /* status from RRB or WRB */ - s1_src : 11; /* message source */ -}; - -#else - -struct err_status1_format { - uint64_t s1_src : 11, /* message source */ - s1_crb_sts : 10, /* status from RRB or WRB */ - s1_rw_rb : 1, /* RRB == 0, WRB == 1 */ - s1_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ - s1_inval_cnt:10, /* signed invalidate counter RRB */ - s1_to_cnt : 8, /* crb timeout counter */ - s1_spl_cnt : 21; /* number spooled to memory */ -}; - -#endif - -typedef union pi_err_stat1 { - uint64_t pi_stat1_word; - struct err_status1_format pi_stat1_fmt; -} pi_err_stat1_t; -#endif - -/* Error stack types (sk_err_type) for reads: */ -#define PI_ERR_RD_AERR 0 /* Read Access Error */ -#define PI_ERR_RD_PRERR 1 /* Uncached Partitial Read */ -#define PI_ERR_RD_DERR 2 /* Directory Error */ -#define PI_ERR_RD_TERR 3 /* read timeout */ -#define PI_ERR_RD_PERR 4 /* Poison Access Violation */ -#define PI_ERR_RD_NACK 5 /* Excessive NACKs */ -#define PI_ERR_RD_RDE 6 /* Response Data Error */ -#define PI_ERR_RD_PLERR 7 /* Packet Length Error */ -/* Error stack types (sk_err_type) for writes: */ -#define PI_ERR_WR_WERR 0 /* Write Access Error */ -#define PI_ERR_WR_PWERR 1 /* Uncached Write Error */ -#define PI_ERR_WR_TERR 3 /* write timeout */ -#define PI_ERR_WR_RDE 6 /* Response Data Error */ -#define PI_ERR_WR_PLERR 7 /* Packet Length Error */ - - -/* For backwards compatibility */ -#define PI_RT_COUNT PI_RT_COUNTER /* Real Time Counter */ -#define PI_RT_EN_A PI_RT_INT_EN_A /* RT int for CPU A enable */ -#define PI_RT_EN_B PI_RT_INT_EN_B /* RT int for CPU B enable */ -#define PI_PROF_EN_A PI_PROF_INT_EN_A /* PROF int for CPU A enable */ -#define PI_PROF_EN_B PI_PROF_INT_EN_B /* PROF int for CPU B enable */ -#define PI_RT_PEND_A PI_RT_INT_PEND_A /* RT interrupt pending */ -#define PI_RT_PEND_B PI_RT_INT_PEND_B /* RT interrupt pending */ -#define PI_PROF_PEND_A PI_PROF_INT_PEND_A /* Profiling interrupt pending */ -#define PI_PROF_PEND_B PI_PROF_INT_PEND_B /* Profiling interrupt pending */ - - -/* Bits in PI_SYSAD_ERRCHK_EN */ -#define PI_SYSAD_ERRCHK_ECCGEN 0x01 /* Enable ECC generation */ -#define PI_SYSAD_ERRCHK_QUALGEN 0x02 /* Enable data quality signal gen. */ -#define PI_SYSAD_ERRCHK_SADP 0x04 /* Enable SysAD parity checking */ -#define PI_SYSAD_ERRCHK_CMDP 0x08 /* Enable SysCmd parity checking */ -#define PI_SYSAD_ERRCHK_STATE 0x10 /* Enable SysState parity checking */ -#define PI_SYSAD_ERRCHK_QUAL 0x20 /* Enable data quality checking */ -#define PI_SYSAD_CHECK_ALL 0x3f /* Generate and check all signals. */ - -/* CALIAS values */ -#define PI_CALIAS_SIZE_0 0 -#define PI_CALIAS_SIZE_4K 1 -#define PI_CALIAS_SIZE_8K 2 -#define PI_CALIAS_SIZE_16K 3 -#define PI_CALIAS_SIZE_32K 4 -#define PI_CALIAS_SIZE_64K 5 -#define PI_CALIAS_SIZE_128K 6 -#define PI_CALIAS_SIZE_256K 7 -#define PI_CALIAS_SIZE_512K 8 -#define PI_CALIAS_SIZE_1M 9 -#define PI_CALIAS_SIZE_2M 10 -#define PI_CALIAS_SIZE_4M 11 -#define PI_CALIAS_SIZE_8M 12 -#define PI_CALIAS_SIZE_16M 13 -#define PI_CALIAS_SIZE_32M 14 -#define PI_CALIAS_SIZE_64M 15 - -/* Fields in PI_ERR_STATUS0_[AB] */ -#define PI_ERR_ST0_VALID_MASK 0x8000000000000000 -#define PI_ERR_ST0_VALID_SHFT 63 - -/* Fields in PI_SPURIOUS_HDR_0 */ -#define PI_SPURIOUS_HDR_VALID_MASK 0x8000000000000000 -#define PI_SPURIOUS_HDR_VALID_SHFT 63 - -/* Fields in PI_NACK_CNT_A/B */ -#define PI_NACK_CNT_EN_SHFT 20 -#define PI_NACK_CNT_EN_MASK 0x100000 -#define PI_NACK_CNT_MASK 0x0fffff -#define PI_NACK_CNT_MAX 0x0fffff - -/* Bits in PI_ERR_INT_PEND */ -#define PI_ERR_SPOOL_CMP_B 0x000000001 /* Spool end hit high water */ -#define PI_ERR_SPOOL_CMP_A 0x000000002 -#define PI_ERR_SPUR_MSG_B 0x000000004 /* Spurious message intr. */ -#define PI_ERR_SPUR_MSG_A 0x000000008 -#define PI_ERR_WRB_TERR_B 0x000000010 /* WRB TERR */ -#define PI_ERR_WRB_TERR_A 0x000000020 -#define PI_ERR_WRB_WERR_B 0x000000040 /* WRB WERR */ -#define PI_ERR_WRB_WERR_A 0x000000080 -#define PI_ERR_SYSSTATE_B 0x000000100 /* SysState parity error */ -#define PI_ERR_SYSSTATE_A 0x000000200 -#define PI_ERR_SYSAD_DATA_B 0x000000400 /* SysAD data parity error */ -#define PI_ERR_SYSAD_DATA_A 0x000000800 -#define PI_ERR_SYSAD_ADDR_B 0x000001000 /* SysAD addr parity error */ -#define PI_ERR_SYSAD_ADDR_A 0x000002000 -#define PI_ERR_SYSCMD_DATA_B 0x000004000 /* SysCmd data parity error */ -#define PI_ERR_SYSCMD_DATA_A 0x000008000 -#define PI_ERR_SYSCMD_ADDR_B 0x000010000 /* SysCmd addr parity error */ -#define PI_ERR_SYSCMD_ADDR_A 0x000020000 -#define PI_ERR_BAD_SPOOL_B 0x000040000 /* Error spooling to memory */ -#define PI_ERR_BAD_SPOOL_A 0x000080000 -#define PI_ERR_UNCAC_UNCORR_B 0x000100000 /* Uncached uncorrectable */ -#define PI_ERR_UNCAC_UNCORR_A 0x000200000 -#define PI_ERR_SYSSTATE_TAG_B 0x000400000 /* SysState tag parity error */ -#define PI_ERR_SYSSTATE_TAG_A 0x000800000 -#define PI_ERR_MD_UNCORR 0x001000000 /* Must be cleared in MD */ -#define PI_ERR_SYSAD_BAD_DATA_B 0x002000000 /* SysAD Data quality bad */ -#define PI_ERR_SYSAD_BAD_DATA_A 0x004000000 -#define PI_ERR_UE_CACHED_B 0x008000000 /* UE during cached load */ -#define PI_ERR_UE_CACHED_A 0x010000000 -#define PI_ERR_PKT_LEN_ERR_B 0x020000000 /* Xbar data too long/short */ -#define PI_ERR_PKT_LEN_ERR_A 0x040000000 -#define PI_ERR_IRB_ERR_B 0x080000000 /* Protocol error */ -#define PI_ERR_IRB_ERR_A 0x100000000 -#define PI_ERR_IRB_TIMEOUT_B 0x200000000 /* IRB_B got a timeout */ -#define PI_ERR_IRB_TIMEOUT_A 0x400000000 - -#define PI_ERR_CLEAR_ALL_A 0x554aaaaaa -#define PI_ERR_CLEAR_ALL_B 0x2aa555555 - - -/* - * The following three macros define all possible error int pends. - */ - -#define PI_FATAL_ERR_CPU_A (PI_ERR_IRB_TIMEOUT_A | \ - PI_ERR_IRB_ERR_A | \ - PI_ERR_PKT_LEN_ERR_A | \ - PI_ERR_SYSSTATE_TAG_A | \ - PI_ERR_BAD_SPOOL_A | \ - PI_ERR_SYSCMD_ADDR_A | \ - PI_ERR_SYSCMD_DATA_A | \ - PI_ERR_SYSAD_ADDR_A | \ - PI_ERR_SYSAD_DATA_A | \ - PI_ERR_SYSSTATE_A) - -#define PI_MISC_ERR_CPU_A (PI_ERR_UE_CACHED_A | \ - PI_ERR_SYSAD_BAD_DATA_A| \ - PI_ERR_UNCAC_UNCORR_A | \ - PI_ERR_WRB_WERR_A | \ - PI_ERR_WRB_TERR_A | \ - PI_ERR_SPUR_MSG_A | \ - PI_ERR_SPOOL_CMP_A) - -#define PI_FATAL_ERR_CPU_B (PI_ERR_IRB_TIMEOUT_B | \ - PI_ERR_IRB_ERR_B | \ - PI_ERR_PKT_LEN_ERR_B | \ - PI_ERR_SYSSTATE_TAG_B | \ - PI_ERR_BAD_SPOOL_B | \ - PI_ERR_SYSCMD_ADDR_B | \ - PI_ERR_SYSCMD_DATA_B | \ - PI_ERR_SYSAD_ADDR_B | \ - PI_ERR_SYSAD_DATA_B | \ - PI_ERR_SYSSTATE_B) - -#define PI_MISC_ERR_CPU_B (PI_ERR_UE_CACHED_B | \ - PI_ERR_SYSAD_BAD_DATA_B| \ - PI_ERR_UNCAC_UNCORR_B | \ - PI_ERR_WRB_WERR_B | \ - PI_ERR_WRB_TERR_B | \ - PI_ERR_SPUR_MSG_B | \ - PI_ERR_SPOOL_CMP_B) - -#define PI_ERR_GENERIC (PI_ERR_MD_UNCORR) - -/* Values for PI_MAX_CRB_TIMEOUT and PI_CRB_SFACTOR */ -#define PMCT_MAX 0xff -#define PCS_MAX 0xffffff - -/* pi_err_status0_a_u_t address shift */ -#define ERR_STAT0_ADDR_SHFT 3 - -/* PI error read/write bit (RRB == 0, WRB == 1) */ -/* pi_err_status1_a_u_t.pi_err_status1_a_fld_s.esa_wrb */ -#define PI_ERR_RRB 0 -#define PI_ERR_WRB 1 - -/* Error stack address shift, for use with pi_stk_fmt.sk_addr */ -#define ERR_STK_ADDR_SHFT 3 - -#endif /* _ASM_IA64_SN_SN1_HUBPI_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hubspc.h b/include/asm-ia64/sn/sn1/hubspc.h deleted file mode 100644 index c0af0b6de5516..0000000000000 --- a/include/asm-ia64/sn/sn1/hubspc.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_HUBSPC_H -#define _ASM_IA64_SN_SN1_HUBSPC_H - -typedef enum { - HUBSPC_REFCOUNTERS, - HUBSPC_PROM -} hubspc_subdevice_t; - - -/* - * Reference Counters - */ - -extern int refcounters_attach(devfs_handle_t hub); - -#endif /* _ASM_IA64_SN_SN1_HUBSPC_H */ diff --git a/include/asm-ia64/sn/sn1/hubstat.h b/include/asm-ia64/sn/sn1/hubstat.h deleted file mode 100644 index ddf3626243d01..0000000000000 --- a/include/asm-ia64/sn/sn1/hubstat.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 - 2001 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_SN1_HUBSTAT_H -#define _ASM_IA64_SN_SN1_HUBSTAT_H - -typedef int64_t hub_count_t; - -#define HUBSTAT_VERSION 1 - -typedef struct hubstat_s { - char hs_version; /* structure version */ - cnodeid_t hs_cnode; /* cnode of this hub */ - nasid_t hs_nasid; /* Nasid of same */ - int64_t hs_timebase; /* Time of first sample */ - int64_t hs_timestamp; /* Time of last sample */ - int64_t hs_per_minute; /* Ticks per minute */ - - union { - hubreg_t hs_niu_stat_rev_id; /* SN0: Status rev ID */ - hubreg_t hs_niu_port_status; /* SN1: Port status */ - } hs_niu; - - hub_count_t hs_ni_retry_errors; /* Total retry errors */ - hub_count_t hs_ni_sn_errors; /* Total sn errors */ - hub_count_t hs_ni_cb_errors; /* Total cb errors */ - int hs_ni_overflows; /* NI count overflows */ - hub_count_t hs_ii_sn_errors; /* Total sn errors */ - hub_count_t hs_ii_cb_errors; /* Total cb errors */ - int hs_ii_overflows; /* II count overflows */ - - /* - * Anything below this comment is intended for kernel internal-use - * only and may be changed at any time. - * - * Any members that contain pointers or are conditionally compiled - * need to be below here also. - */ - int64_t hs_last_print; /* When we last printed */ - char hs_print; /* Should we print */ - - char *hs_name; /* This hub's name */ - unsigned char hs_maint; /* Should we print to availmon */ -} hubstat_t; - -#define hs_ni_stat_rev_id hs_niu.hs_niu_stat_rev_id -#define hs_ni_port_status hs_niu.hs_niu_port_status - -extern struct file_operations hub_mon_fops; - -#endif /* _ASM_IA64_SN_SN1_HUBSTAT_H */ diff --git a/include/asm-ia64/sn/sn1/hubxb.h b/include/asm-ia64/sn/sn1/hubxb.h deleted file mode 100644 index 8a9ee36ae3127..0000000000000 --- a/include/asm-ia64/sn/sn1/hubxb.h +++ /dev/null @@ -1,1288 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_HUBXB_H -#define _ASM_IA64_SN_SN1_HUBXB_H - -/************************************************************************ - * * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * - * * - * This file is created by an automated script. Any (minimal) changes * - * made manually to this file should be made with care. * - * * - * MAKE ALL ADDITIONS TO THE END OF THIS FILE * - * * - ************************************************************************/ - - -#define XB_PARMS 0x00700000 /* - * Controls - * crossbar-wide - * parameters. - */ - - - -#define XB_SLOW_GNT 0x00700008 /* - * Controls wavefront - * arbiter grant - * frequency, used to - * slow XB grants - */ - - - -#define XB_SPEW_CONTROL 0x00700010 /* - * Controls spew - * settings (debug - * only). - */ - - - -#define XB_IOQ_ARB_TRIGGER 0x00700018 /* - * Controls IOQ - * trigger level - */ - - - -#define XB_FIRST_ERROR 0x00700090 /* - * Records the first - * crossbar error - * seen. - */ - - - -#define XB_POQ0_ERROR 0x00700020 /* - * POQ0 error - * register. - */ - - - -#define XB_PIQ0_ERROR 0x00700028 /* - * PIQ0 error - * register. - */ - - - -#define XB_POQ1_ERROR 0x00700030 /* - * POQ1 error - * register. - */ - - - -#define XB_PIQ1_ERROR 0x00700038 /* - * PIQ1 error - * register. - */ - - - -#define XB_MP0_ERROR 0x00700040 /* - * MOQ for PI0 error - * register. - */ - - - -#define XB_MP1_ERROR 0x00700048 /* - * MOQ for PI1 error - * register. - */ - - - -#define XB_MMQ_ERROR 0x00700050 /* - * MOQ for misc. (LB, - * NI, II) error - * register. - */ - - - -#define XB_MIQ_ERROR 0x00700058 /* - * MIQ error register, - * addtional MIQ - * errors are logged - * in MD "Input - * Error - * Registers". - */ - - - -#define XB_NOQ_ERROR 0x00700060 /* NOQ error register. */ - - - -#define XB_NIQ_ERROR 0x00700068 /* NIQ error register. */ - - - -#define XB_IOQ_ERROR 0x00700070 /* IOQ error register. */ - - - -#define XB_IIQ_ERROR 0x00700078 /* IIQ error register. */ - - - -#define XB_LOQ_ERROR 0x00700080 /* LOQ error register. */ - - - -#define XB_LIQ_ERROR 0x00700088 /* LIQ error register. */ - - - -#define XB_DEBUG_DATA_CTL 0x00700098 /* - * Debug Datapath - * Select - */ - - - -#define XB_DEBUG_ARB_CTL 0x007000A0 /* - * XB master debug - * control - */ - - - -#define XB_POQ0_ERROR_CLEAR 0x00700120 /* - * Clears - * XB_POQ0_ERROR - * register. - */ - - - -#define XB_PIQ0_ERROR_CLEAR 0x00700128 /* - * Clears - * XB_PIQ0_ERROR - * register. - */ - - - -#define XB_POQ1_ERROR_CLEAR 0x00700130 /* - * Clears - * XB_POQ1_ERROR - * register. - */ - - - -#define XB_PIQ1_ERROR_CLEAR 0x00700138 /* - * Clears - * XB_PIQ1_ERROR - * register. - */ - - - -#define XB_MP0_ERROR_CLEAR 0x00700140 /* - * Clears XB_MP0_ERROR - * register. - */ - - - -#define XB_MP1_ERROR_CLEAR 0x00700148 /* - * Clears XB_MP1_ERROR - * register. - */ - - - -#define XB_MMQ_ERROR_CLEAR 0x00700150 /* - * Clears XB_MMQ_ERROR - * register. - */ - - - -#define XB_XM_MIQ_ERROR_CLEAR 0x00700158 /* - * Clears XB_MIQ_ERROR - * register - */ - - - -#define XB_NOQ_ERROR_CLEAR 0x00700160 /* - * Clears XB_NOQ_ERROR - * register. - */ - - - -#define XB_NIQ_ERROR_CLEAR 0x00700168 /* - * Clears XB_NIQ_ERROR - * register. - */ - - - -#define XB_IOQ_ERROR_CLEAR 0x00700170 /* - * Clears XB_IOQ - * _ERROR register. - */ - - - -#define XB_IIQ_ERROR_CLEAR 0x00700178 /* - * Clears XB_IIQ - * _ERROR register. - */ - - - -#define XB_LOQ_ERROR_CLEAR 0x00700180 /* - * Clears XB_LOQ_ERROR - * register. - */ - - - -#define XB_LIQ_ERROR_CLEAR 0x00700188 /* - * Clears XB_LIQ_ERROR - * register. - */ - - - -#define XB_FIRST_ERROR_CLEAR 0x00700190 /* - * Clears - * XB_FIRST_ERROR - * register - */ - - - - - -#ifndef __ASSEMBLY__ - -/************************************************************************ - * * - * Access to parameters which control various aspects of the * - * crossbar's operation. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_parms_u { - bdrkreg_t xb_parms_regval; - struct { - bdrkreg_t p_byp_en : 1; - bdrkreg_t p_rsrvd_1 : 3; - bdrkreg_t p_age_wrap : 8; - bdrkreg_t p_deadlock_to_wrap : 20; - bdrkreg_t p_tail_to_wrap : 20; - bdrkreg_t p_rsrvd : 12; - } xb_parms_fld_s; -} xb_parms_u_t; - -#else - -typedef union xb_parms_u { - bdrkreg_t xb_parms_regval; - struct { - bdrkreg_t p_rsrvd : 12; - bdrkreg_t p_tail_to_wrap : 20; - bdrkreg_t p_deadlock_to_wrap : 20; - bdrkreg_t p_age_wrap : 8; - bdrkreg_t p_rsrvd_1 : 3; - bdrkreg_t p_byp_en : 1; - } xb_parms_fld_s; -} xb_parms_u_t; - -#endif - - - - -/************************************************************************ - * * - * Sets the period of wavefront grants given to each unit. The * - * register's value corresponds to the number of cycles between each * - * wavefront grant opportunity given to the requesting unit. If set * - * to 0xF, no grants are given to this unit. If set to 0xE, the unit * - * is granted at the slowest rate (sometimes called "molasses mode"). * - * This feature can be used to apply backpressure to a unit's output * - * queue(s). The setting does not affect bypass grants. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_slow_gnt_u { - bdrkreg_t xb_slow_gnt_regval; - struct { - bdrkreg_t sg_lb_slow_gnt : 4; - bdrkreg_t sg_ii_slow_gnt : 4; - bdrkreg_t sg_ni_slow_gnt : 4; - bdrkreg_t sg_mmq_slow_gnt : 4; - bdrkreg_t sg_mp1_slow_gnt : 4; - bdrkreg_t sg_mp0_slow_gnt : 4; - bdrkreg_t sg_pi1_slow_gnt : 4; - bdrkreg_t sg_pi0_slow_gnt : 4; - bdrkreg_t sg_rsrvd : 32; - } xb_slow_gnt_fld_s; -} xb_slow_gnt_u_t; - -#else - -typedef union xb_slow_gnt_u { - bdrkreg_t xb_slow_gnt_regval; - struct { - bdrkreg_t sg_rsrvd : 32; - bdrkreg_t sg_pi0_slow_gnt : 4; - bdrkreg_t sg_pi1_slow_gnt : 4; - bdrkreg_t sg_mp0_slow_gnt : 4; - bdrkreg_t sg_mp1_slow_gnt : 4; - bdrkreg_t sg_mmq_slow_gnt : 4; - bdrkreg_t sg_ni_slow_gnt : 4; - bdrkreg_t sg_ii_slow_gnt : 4; - bdrkreg_t sg_lb_slow_gnt : 4; - } xb_slow_gnt_fld_s; -} xb_slow_gnt_u_t; - -#endif - - - - -/************************************************************************ - * * - * Enables snooping of internal crossbar traffic by spewing all * - * traffic across a selected crossbar point to the PI1 port. Only one * - * bit should be set at any one time, and any bit set will preclude * - * using the P1 for anything but a debug connection. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_spew_control_u { - bdrkreg_t xb_spew_control_regval; - struct { - bdrkreg_t sc_snoop_liq : 1; - bdrkreg_t sc_snoop_iiq : 1; - bdrkreg_t sc_snoop_niq : 1; - bdrkreg_t sc_snoop_miq : 1; - bdrkreg_t sc_snoop_piq0 : 1; - bdrkreg_t sc_snoop_loq : 1; - bdrkreg_t sc_snoop_ioq : 1; - bdrkreg_t sc_snoop_noq : 1; - bdrkreg_t sc_snoop_mmq : 1; - bdrkreg_t sc_snoop_mp0 : 1; - bdrkreg_t sc_snoop_poq0 : 1; - bdrkreg_t sc_rsrvd : 53; - } xb_spew_control_fld_s; -} xb_spew_control_u_t; - -#else - -typedef union xb_spew_control_u { - bdrkreg_t xb_spew_control_regval; - struct { - bdrkreg_t sc_rsrvd : 53; - bdrkreg_t sc_snoop_poq0 : 1; - bdrkreg_t sc_snoop_mp0 : 1; - bdrkreg_t sc_snoop_mmq : 1; - bdrkreg_t sc_snoop_noq : 1; - bdrkreg_t sc_snoop_ioq : 1; - bdrkreg_t sc_snoop_loq : 1; - bdrkreg_t sc_snoop_piq0 : 1; - bdrkreg_t sc_snoop_miq : 1; - bdrkreg_t sc_snoop_niq : 1; - bdrkreg_t sc_snoop_iiq : 1; - bdrkreg_t sc_snoop_liq : 1; - } xb_spew_control_fld_s; -} xb_spew_control_u_t; - -#endif - - - - -/************************************************************************ - * * - * Number of clocks the IOQ will wait before beginning XB * - * arbitration. This is set so that the slower IOQ data rate can * - * catch up up with the XB data rate in the IOQ buffer. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_ioq_arb_trigger_u { - bdrkreg_t xb_ioq_arb_trigger_regval; - struct { - bdrkreg_t iat_ioq_arb_trigger : 4; - bdrkreg_t iat_rsrvd : 60; - } xb_ioq_arb_trigger_fld_s; -} xb_ioq_arb_trigger_u_t; - -#else - -typedef union xb_ioq_arb_trigger_u { - bdrkreg_t xb_ioq_arb_trigger_regval; - struct { - bdrkreg_t iat_rsrvd : 60; - bdrkreg_t iat_ioq_arb_trigger : 4; - } xb_ioq_arb_trigger_fld_s; -} xb_ioq_arb_trigger_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by POQ0.Can be written to test software, will * - * cause an interrupt. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_poq0_error_u { - bdrkreg_t xb_poq0_error_regval; - struct { - bdrkreg_t pe_invalid_xsel : 2; - bdrkreg_t pe_rsrvd_3 : 2; - bdrkreg_t pe_overflow : 2; - bdrkreg_t pe_rsrvd_2 : 2; - bdrkreg_t pe_underflow : 2; - bdrkreg_t pe_rsrvd_1 : 2; - bdrkreg_t pe_tail_timeout : 2; - bdrkreg_t pe_unused : 6; - bdrkreg_t pe_rsrvd : 44; - } xb_poq0_error_fld_s; -} xb_poq0_error_u_t; - -#else - -typedef union xb_poq0_error_u { - bdrkreg_t xb_poq0_error_regval; - struct { - bdrkreg_t pe_rsrvd : 44; - bdrkreg_t pe_unused : 6; - bdrkreg_t pe_tail_timeout : 2; - bdrkreg_t pe_rsrvd_1 : 2; - bdrkreg_t pe_underflow : 2; - bdrkreg_t pe_rsrvd_2 : 2; - bdrkreg_t pe_overflow : 2; - bdrkreg_t pe_rsrvd_3 : 2; - bdrkreg_t pe_invalid_xsel : 2; - } xb_poq0_error_fld_s; -} xb_poq0_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by PIQ0. Note that the PIQ/PI interface * - * precludes PIQ underflow. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_piq0_error_u { - bdrkreg_t xb_piq0_error_regval; - struct { - bdrkreg_t pe_overflow : 2; - bdrkreg_t pe_rsrvd_1 : 2; - bdrkreg_t pe_deadlock_timeout : 2; - bdrkreg_t pe_rsrvd : 58; - } xb_piq0_error_fld_s; -} xb_piq0_error_u_t; - -#else - -typedef union xb_piq0_error_u { - bdrkreg_t xb_piq0_error_regval; - struct { - bdrkreg_t pe_rsrvd : 58; - bdrkreg_t pe_deadlock_timeout : 2; - bdrkreg_t pe_rsrvd_1 : 2; - bdrkreg_t pe_overflow : 2; - } xb_piq0_error_fld_s; -} xb_piq0_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by MP0 queue (the MOQ for processor 0). Since * - * the xselect is decoded on the MD/MOQ interface, no invalid xselect * - * errors are possible. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_mp0_error_u { - bdrkreg_t xb_mp0_error_regval; - struct { - bdrkreg_t me_rsrvd_3 : 4; - bdrkreg_t me_overflow : 2; - bdrkreg_t me_rsrvd_2 : 2; - bdrkreg_t me_underflow : 2; - bdrkreg_t me_rsrvd_1 : 2; - bdrkreg_t me_tail_timeout : 2; - bdrkreg_t me_rsrvd : 50; - } xb_mp0_error_fld_s; -} xb_mp0_error_u_t; - -#else - -typedef union xb_mp0_error_u { - bdrkreg_t xb_mp0_error_regval; - struct { - bdrkreg_t me_rsrvd : 50; - bdrkreg_t me_tail_timeout : 2; - bdrkreg_t me_rsrvd_1 : 2; - bdrkreg_t me_underflow : 2; - bdrkreg_t me_rsrvd_2 : 2; - bdrkreg_t me_overflow : 2; - bdrkreg_t me_rsrvd_3 : 4; - } xb_mp0_error_fld_s; -} xb_mp0_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by MIQ. * - * * - ************************************************************************/ - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_miq_error_u { - bdrkreg_t xb_miq_error_regval; - struct { - bdrkreg_t me_rsrvd_1 : 4; - bdrkreg_t me_deadlock_timeout : 4; - bdrkreg_t me_rsrvd : 56; - } xb_miq_error_fld_s; -} xb_miq_error_u_t; - -#else - -typedef union xb_miq_error_u { - bdrkreg_t xb_miq_error_regval; - struct { - bdrkreg_t me_rsrvd : 56; - bdrkreg_t me_deadlock_timeout : 4; - bdrkreg_t me_rsrvd_1 : 4; - } xb_miq_error_fld_s; -} xb_miq_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by NOQ. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_noq_error_u { - bdrkreg_t xb_noq_error_regval; - struct { - bdrkreg_t ne_rsvd : 4; - bdrkreg_t ne_overflow : 4; - bdrkreg_t ne_underflow : 4; - bdrkreg_t ne_tail_timeout : 4; - bdrkreg_t ne_rsrvd : 48; - } xb_noq_error_fld_s; -} xb_noq_error_u_t; - -#else - -typedef union xb_noq_error_u { - bdrkreg_t xb_noq_error_regval; - struct { - bdrkreg_t ne_rsrvd : 48; - bdrkreg_t ne_tail_timeout : 4; - bdrkreg_t ne_underflow : 4; - bdrkreg_t ne_overflow : 4; - bdrkreg_t ne_rsvd : 4; - } xb_noq_error_fld_s; -} xb_noq_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by LOQ. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_loq_error_u { - bdrkreg_t xb_loq_error_regval; - struct { - bdrkreg_t le_invalid_xsel : 2; - bdrkreg_t le_rsrvd_1 : 6; - bdrkreg_t le_underflow : 2; - bdrkreg_t le_rsvd : 2; - bdrkreg_t le_tail_timeout : 2; - bdrkreg_t le_rsrvd : 50; - } xb_loq_error_fld_s; -} xb_loq_error_u_t; - -#else - -typedef union xb_loq_error_u { - bdrkreg_t xb_loq_error_regval; - struct { - bdrkreg_t le_rsrvd : 50; - bdrkreg_t le_tail_timeout : 2; - bdrkreg_t le_rsvd : 2; - bdrkreg_t le_underflow : 2; - bdrkreg_t le_rsrvd_1 : 6; - bdrkreg_t le_invalid_xsel : 2; - } xb_loq_error_fld_s; -} xb_loq_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by LIQ. Note that the LIQ only records errors * - * for the request channel. The reply channel can never deadlock or * - * overflow because it does not have hardware flow control. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_liq_error_u { - bdrkreg_t xb_liq_error_regval; - struct { - bdrkreg_t le_overflow : 1; - bdrkreg_t le_rsrvd_1 : 3; - bdrkreg_t le_deadlock_timeout : 1; - bdrkreg_t le_rsrvd : 59; - } xb_liq_error_fld_s; -} xb_liq_error_u_t; - -#else - -typedef union xb_liq_error_u { - bdrkreg_t xb_liq_error_regval; - struct { - bdrkreg_t le_rsrvd : 59; - bdrkreg_t le_deadlock_timeout : 1; - bdrkreg_t le_rsrvd_1 : 3; - bdrkreg_t le_overflow : 1; - } xb_liq_error_fld_s; -} xb_liq_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * First error is latched whenever the Valid bit is clear and an * - * error occurs. Any valid bit on in this register causes an * - * interrupt to PI0 and PI1. This interrupt bit will persist until * - * the specific error register to capture the error is cleared, then * - * the FIRST_ERROR register is cleared (in that oder.) The * - * FIRST_ERROR register is not writable, but will be set when any of * - * the corresponding error registers are written by software. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_first_error_u { - bdrkreg_t xb_first_error_regval; - struct { - bdrkreg_t fe_type : 4; - bdrkreg_t fe_channel : 4; - bdrkreg_t fe_source : 4; - bdrkreg_t fe_valid : 1; - bdrkreg_t fe_rsrvd : 51; - } xb_first_error_fld_s; -} xb_first_error_u_t; - -#else - -typedef union xb_first_error_u { - bdrkreg_t xb_first_error_regval; - struct { - bdrkreg_t fe_rsrvd : 51; - bdrkreg_t fe_valid : 1; - bdrkreg_t fe_source : 4; - bdrkreg_t fe_channel : 4; - bdrkreg_t fe_type : 4; - } xb_first_error_fld_s; -} xb_first_error_u_t; - -#endif - - - - -/************************************************************************ - * * - * Controls DEBUG_DATA mux setting. Allows user to watch the output * - * of any OQ or input of any IQ on the DEBUG port. Note that bits * - * 13:0 are one-hot. If more than one bit is set in [13:0], the debug * - * output is undefined. Details on the debug output lines can be * - * found in the XB chapter of the Bedrock Interface Specification. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_debug_data_ctl_u { - bdrkreg_t xb_debug_data_ctl_regval; - struct { - bdrkreg_t ddc_observe_liq_traffic : 1; - bdrkreg_t ddc_observe_iiq_traffic : 1; - bdrkreg_t ddc_observe_niq_traffic : 1; - bdrkreg_t ddc_observe_miq_traffic : 1; - bdrkreg_t ddc_observe_piq1_traffic : 1; - bdrkreg_t ddc_observe_piq0_traffic : 1; - bdrkreg_t ddc_observe_loq_traffic : 1; - bdrkreg_t ddc_observe_ioq_traffic : 1; - bdrkreg_t ddc_observe_noq_traffic : 1; - bdrkreg_t ddc_observe_mp1_traffic : 1; - bdrkreg_t ddc_observe_mp0_traffic : 1; - bdrkreg_t ddc_observe_mmq_traffic : 1; - bdrkreg_t ddc_observe_poq1_traffic : 1; - bdrkreg_t ddc_observe_poq0_traffic : 1; - bdrkreg_t ddc_observe_source_field : 1; - bdrkreg_t ddc_observe_lodata : 1; - bdrkreg_t ddc_rsrvd : 48; - } xb_debug_data_ctl_fld_s; -} xb_debug_data_ctl_u_t; - -#else - -typedef union xb_debug_data_ctl_u { - bdrkreg_t xb_debug_data_ctl_regval; - struct { - bdrkreg_t ddc_rsrvd : 48; - bdrkreg_t ddc_observe_lodata : 1; - bdrkreg_t ddc_observe_source_field : 1; - bdrkreg_t ddc_observe_poq0_traffic : 1; - bdrkreg_t ddc_observe_poq1_traffic : 1; - bdrkreg_t ddc_observe_mmq_traffic : 1; - bdrkreg_t ddc_observe_mp0_traffic : 1; - bdrkreg_t ddc_observe_mp1_traffic : 1; - bdrkreg_t ddc_observe_noq_traffic : 1; - bdrkreg_t ddc_observe_ioq_traffic : 1; - bdrkreg_t ddc_observe_loq_traffic : 1; - bdrkreg_t ddc_observe_piq0_traffic : 1; - bdrkreg_t ddc_observe_piq1_traffic : 1; - bdrkreg_t ddc_observe_miq_traffic : 1; - bdrkreg_t ddc_observe_niq_traffic : 1; - bdrkreg_t ddc_observe_iiq_traffic : 1; - bdrkreg_t ddc_observe_liq_traffic : 1; - } xb_debug_data_ctl_fld_s; -} xb_debug_data_ctl_u_t; - -#endif - - - - -/************************************************************************ - * * - * Controls debug mux setting for XB Input/Output Queues and * - * Arbiter. Can select one of the following values. Details on the * - * debug output lines can be found in the XB chapter of the Bedrock * - * Interface Specification. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_debug_arb_ctl_u { - bdrkreg_t xb_debug_arb_ctl_regval; - struct { - bdrkreg_t dac_xb_debug_select : 3; - bdrkreg_t dac_rsrvd : 61; - } xb_debug_arb_ctl_fld_s; -} xb_debug_arb_ctl_u_t; - -#else - -typedef union xb_debug_arb_ctl_u { - bdrkreg_t xb_debug_arb_ctl_regval; - struct { - bdrkreg_t dac_rsrvd : 61; - bdrkreg_t dac_xb_debug_select : 3; - } xb_debug_arb_ctl_fld_s; -} xb_debug_arb_ctl_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by POQ0.Can be written to test software, will * - * cause an interrupt. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_poq0_error_clear_u { - bdrkreg_t xb_poq0_error_clear_regval; - struct { - bdrkreg_t pec_invalid_xsel : 2; - bdrkreg_t pec_rsrvd_3 : 2; - bdrkreg_t pec_overflow : 2; - bdrkreg_t pec_rsrvd_2 : 2; - bdrkreg_t pec_underflow : 2; - bdrkreg_t pec_rsrvd_1 : 2; - bdrkreg_t pec_tail_timeout : 2; - bdrkreg_t pec_unused : 6; - bdrkreg_t pec_rsrvd : 44; - } xb_poq0_error_clear_fld_s; -} xb_poq0_error_clear_u_t; - -#else - -typedef union xb_poq0_error_clear_u { - bdrkreg_t xb_poq0_error_clear_regval; - struct { - bdrkreg_t pec_rsrvd : 44; - bdrkreg_t pec_unused : 6; - bdrkreg_t pec_tail_timeout : 2; - bdrkreg_t pec_rsrvd_1 : 2; - bdrkreg_t pec_underflow : 2; - bdrkreg_t pec_rsrvd_2 : 2; - bdrkreg_t pec_overflow : 2; - bdrkreg_t pec_rsrvd_3 : 2; - bdrkreg_t pec_invalid_xsel : 2; - } xb_poq0_error_clear_fld_s; -} xb_poq0_error_clear_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by PIQ0. Note that the PIQ/PI interface * - * precludes PIQ underflow. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_piq0_error_clear_u { - bdrkreg_t xb_piq0_error_clear_regval; - struct { - bdrkreg_t pec_overflow : 2; - bdrkreg_t pec_rsrvd_1 : 2; - bdrkreg_t pec_deadlock_timeout : 2; - bdrkreg_t pec_rsrvd : 58; - } xb_piq0_error_clear_fld_s; -} xb_piq0_error_clear_u_t; - -#else - -typedef union xb_piq0_error_clear_u { - bdrkreg_t xb_piq0_error_clear_regval; - struct { - bdrkreg_t pec_rsrvd : 58; - bdrkreg_t pec_deadlock_timeout : 2; - bdrkreg_t pec_rsrvd_1 : 2; - bdrkreg_t pec_overflow : 2; - } xb_piq0_error_clear_fld_s; -} xb_piq0_error_clear_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by MP0 queue (the MOQ for processor 0). Since * - * the xselect is decoded on the MD/MOQ interface, no invalid xselect * - * errors are possible. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_mp0_error_clear_u { - bdrkreg_t xb_mp0_error_clear_regval; - struct { - bdrkreg_t mec_rsrvd_3 : 4; - bdrkreg_t mec_overflow : 2; - bdrkreg_t mec_rsrvd_2 : 2; - bdrkreg_t mec_underflow : 2; - bdrkreg_t mec_rsrvd_1 : 2; - bdrkreg_t mec_tail_timeout : 2; - bdrkreg_t mec_rsrvd : 50; - } xb_mp0_error_clear_fld_s; -} xb_mp0_error_clear_u_t; - -#else - -typedef union xb_mp0_error_clear_u { - bdrkreg_t xb_mp0_error_clear_regval; - struct { - bdrkreg_t mec_rsrvd : 50; - bdrkreg_t mec_tail_timeout : 2; - bdrkreg_t mec_rsrvd_1 : 2; - bdrkreg_t mec_underflow : 2; - bdrkreg_t mec_rsrvd_2 : 2; - bdrkreg_t mec_overflow : 2; - bdrkreg_t mec_rsrvd_3 : 4; - } xb_mp0_error_clear_fld_s; -} xb_mp0_error_clear_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by MIQ. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_xm_miq_error_clear_u { - bdrkreg_t xb_xm_miq_error_clear_regval; - struct { - bdrkreg_t xmec_rsrvd_1 : 4; - bdrkreg_t xmec_deadlock_timeout : 4; - bdrkreg_t xmec_rsrvd : 56; - } xb_xm_miq_error_clear_fld_s; -} xb_xm_miq_error_clear_u_t; - -#else - -typedef union xb_xm_miq_error_clear_u { - bdrkreg_t xb_xm_miq_error_clear_regval; - struct { - bdrkreg_t xmec_rsrvd : 56; - bdrkreg_t xmec_deadlock_timeout : 4; - bdrkreg_t xmec_rsrvd_1 : 4; - } xb_xm_miq_error_clear_fld_s; -} xb_xm_miq_error_clear_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by NOQ. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_noq_error_clear_u { - bdrkreg_t xb_noq_error_clear_regval; - struct { - bdrkreg_t nec_rsvd : 4; - bdrkreg_t nec_overflow : 4; - bdrkreg_t nec_underflow : 4; - bdrkreg_t nec_tail_timeout : 4; - bdrkreg_t nec_rsrvd : 48; - } xb_noq_error_clear_fld_s; -} xb_noq_error_clear_u_t; - -#else - -typedef union xb_noq_error_clear_u { - bdrkreg_t xb_noq_error_clear_regval; - struct { - bdrkreg_t nec_rsrvd : 48; - bdrkreg_t nec_tail_timeout : 4; - bdrkreg_t nec_underflow : 4; - bdrkreg_t nec_overflow : 4; - bdrkreg_t nec_rsvd : 4; - } xb_noq_error_clear_fld_s; -} xb_noq_error_clear_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by LOQ. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_loq_error_clear_u { - bdrkreg_t xb_loq_error_clear_regval; - struct { - bdrkreg_t lec_invalid_xsel : 2; - bdrkreg_t lec_rsrvd_1 : 6; - bdrkreg_t lec_underflow : 2; - bdrkreg_t lec_rsvd : 2; - bdrkreg_t lec_tail_timeout : 2; - bdrkreg_t lec_rsrvd : 50; - } xb_loq_error_clear_fld_s; -} xb_loq_error_clear_u_t; - -#else - -typedef union xb_loq_error_clear_u { - bdrkreg_t xb_loq_error_clear_regval; - struct { - bdrkreg_t lec_rsrvd : 50; - bdrkreg_t lec_tail_timeout : 2; - bdrkreg_t lec_rsvd : 2; - bdrkreg_t lec_underflow : 2; - bdrkreg_t lec_rsrvd_1 : 6; - bdrkreg_t lec_invalid_xsel : 2; - } xb_loq_error_clear_fld_s; -} xb_loq_error_clear_u_t; - -#endif - - - - -/************************************************************************ - * * - * Records errors seen by LIQ. Note that the LIQ only records errors * - * for the request channel. The reply channel can never deadlock or * - * overflow because it does not have hardware flow control. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_liq_error_clear_u { - bdrkreg_t xb_liq_error_clear_regval; - struct { - bdrkreg_t lec_overflow : 1; - bdrkreg_t lec_rsrvd_1 : 3; - bdrkreg_t lec_deadlock_timeout : 1; - bdrkreg_t lec_rsrvd : 59; - } xb_liq_error_clear_fld_s; -} xb_liq_error_clear_u_t; - -#else - -typedef union xb_liq_error_clear_u { - bdrkreg_t xb_liq_error_clear_regval; - struct { - bdrkreg_t lec_rsrvd : 59; - bdrkreg_t lec_deadlock_timeout : 1; - bdrkreg_t lec_rsrvd_1 : 3; - bdrkreg_t lec_overflow : 1; - } xb_liq_error_clear_fld_s; -} xb_liq_error_clear_u_t; - -#endif - - - - -/************************************************************************ - * * - * First error is latched whenever the Valid bit is clear and an * - * error occurs. Any valid bit on in this register causes an * - * interrupt to PI0 and PI1. This interrupt bit will persist until * - * the specific error register to capture the error is cleared, then * - * the FIRST_ERROR register is cleared (in that oder.) The * - * FIRST_ERROR register is not writable, but will be set when any of * - * the corresponding error registers are written by software. * - * * - ************************************************************************/ - - - - -#ifdef LITTLE_ENDIAN - -typedef union xb_first_error_clear_u { - bdrkreg_t xb_first_error_clear_regval; - struct { - bdrkreg_t fec_type : 4; - bdrkreg_t fec_channel : 4; - bdrkreg_t fec_source : 4; - bdrkreg_t fec_valid : 1; - bdrkreg_t fec_rsrvd : 51; - } xb_first_error_clear_fld_s; -} xb_first_error_clear_u_t; - -#else - -typedef union xb_first_error_clear_u { - bdrkreg_t xb_first_error_clear_regval; - struct { - bdrkreg_t fec_rsrvd : 51; - bdrkreg_t fec_valid : 1; - bdrkreg_t fec_source : 4; - bdrkreg_t fec_channel : 4; - bdrkreg_t fec_type : 4; - } xb_first_error_clear_fld_s; -} xb_first_error_clear_u_t; - -#endif - - - - - - -#endif /* __ASSEMBLY__ */ - -/************************************************************************ - * * - * The following defines were not formed into structures * - * * - * This could be because the document did not contain details of the * - * register, or because the automated script did not recognize the * - * register details in the documentation. If these register need * - * structure definition, please create them manually * - * * - * XB_POQ1_ERROR 0x700030 * - * XB_PIQ1_ERROR 0x700038 * - * XB_MP1_ERROR 0x700048 * - * XB_MMQ_ERROR 0x700050 * - * XB_NIQ_ERROR 0x700068 * - * XB_IOQ_ERROR 0x700070 * - * XB_IIQ_ERROR 0x700078 * - * XB_POQ1_ERROR_CLEAR 0x700130 * - * XB_PIQ1_ERROR_CLEAR 0x700138 * - * XB_MP1_ERROR_CLEAR 0x700148 * - * XB_MMQ_ERROR_CLEAR 0x700150 * - * XB_NIQ_ERROR_CLEAR 0x700168 * - * XB_IOQ_ERROR_CLEAR 0x700170 * - * XB_IIQ_ERROR_CLEAR 0x700178 * - * * - ************************************************************************/ - - -/************************************************************************ - * * - * MAKE ALL ADDITIONS AFTER THIS LINE * - * * - ************************************************************************/ - - - - - -#endif /* _ASM_IA64_SN_SN1_HUBXB_H */ diff --git a/include/asm-ia64/sn/sn1/hubxb_next.h b/include/asm-ia64/sn/sn1/hubxb_next.h deleted file mode 100644 index b9df887b9373f..0000000000000 --- a/include/asm-ia64/sn/sn1/hubxb_next.h +++ /dev/null @@ -1,32 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_HUBXB_NEXT_H -#define _ASM_IA64_SN_SN1_HUBXB_NEXT_H - -/* XB_FIRST_ERROR fe_source field encoding */ -#define XVE_SOURCE_POQ0 0xf /* 1111 */ -#define XVE_SOURCE_PIQ0 0xe /* 1110 */ -#define XVE_SOURCE_POQ1 0xd /* 1101 */ -#define XVE_SOURCE_PIQ1 0xc /* 1100 */ -#define XVE_SOURCE_MP0 0xb /* 1011 */ -#define XVE_SOURCE_MP1 0xa /* 1010 */ -#define XVE_SOURCE_MMQ 0x9 /* 1001 */ -#define XVE_SOURCE_MIQ 0x8 /* 1000 */ -#define XVE_SOURCE_NOQ 0x7 /* 0111 */ -#define XVE_SOURCE_NIQ 0x6 /* 0110 */ -#define XVE_SOURCE_IOQ 0x5 /* 0101 */ -#define XVE_SOURCE_IIQ 0x4 /* 0100 */ -#define XVE_SOURCE_LOQ 0x3 /* 0011 */ -#define XVE_SOURCE_LIQ 0x2 /* 0010 */ - -/* XB_PARMS fields */ -#define XBP_RESET_DEFAULTS 0x0008000080000021LL -#define XBP_ACTIVE_DEFAULTS 0x00080000fffff021LL - -#endif /* _ASM_IA64_SN_SN1_HUBXB_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hwcntrs.h b/include/asm-ia64/sn/sn1/hwcntrs.h deleted file mode 100644 index 0ec78e887ab5b..0000000000000 --- a/include/asm-ia64/sn/sn1/hwcntrs.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_HWCNTRS_H -#define _ASM_IA64_SN_SN1_HWCNTRS_H - - -typedef uint64_t refcnt_t; - -#define SN0_REFCNT_MAX_COUNTERS 64 - -typedef struct sn0_refcnt_set { - refcnt_t refcnt[SN0_REFCNT_MAX_COUNTERS]; - uint64_t flags; - uint64_t reserved[4]; -} sn0_refcnt_set_t; - -typedef struct sn0_refcnt_buf { - sn0_refcnt_set_t refcnt_set; - uint64_t paddr; - uint64_t page_size; - cnodeid_t cnodeid; /* cnodeid + pad[3] use 64 bits */ - uint16_t pad[3]; - uint64_t reserved[4]; -} sn0_refcnt_buf_t; - -typedef struct sn0_refcnt_args { - uint64_t vaddr; - uint64_t len; - sn0_refcnt_buf_t* buf; - uint64_t reserved[4]; -} sn0_refcnt_args_t; - -/* - * Info needed by the user level program - * to mmap the refcnt buffer - */ - -#define RCB_INFO_GET 1 -#define RCB_SLOT_GET 2 - -typedef struct rcb_info { - uint64_t rcb_len; /* total refcnt buffer len in bytes */ - - int rcb_sw_sets; /* number of sw counter sets in buffer */ - int rcb_sw_counters_per_set; /* sw counters per set -- num_compact_nodes */ - int rcb_sw_counter_size; /* sizeof(refcnt_t) -- size of sw cntr */ - - int rcb_base_pages; /* number of base pages in node */ - int rcb_base_page_size; /* sw base page size */ - uint64_t rcb_base_paddr; /* base physical address for this node */ - - int rcb_cnodeid; /* cnodeid for this node */ - int rcb_granularity; /* hw page size used for counter sets */ - uint rcb_hw_counter_max; /* max hwcounter count (width mask) */ - int rcb_diff_threshold; /* current node differential threshold */ - int rcb_abs_threshold; /* current node absolute threshold */ - int rcb_num_slots; /* physmem slots */ - - int rcb_reserved[512]; - -} rcb_info_t; - -typedef struct rcb_slot { - uint64_t base; - uint64_t size; -} rcb_slot_t; - -#if defined(__KERNEL__) -typedef struct sn0_refcnt_args_32 { - uint64_t vaddr; - uint64_t len; - app32_ptr_t buf; - uint64_t reserved[4]; -} sn0_refcnt_args_32_t; - -/* Defines and Macros */ -/* A set of reference counts are for 4k bytes of physical memory */ -#define NBPREFCNTP 0x1000 -#define BPREFCNTPSHIFT 12 -#define bytes_to_refcntpages(x) (((__psunsigned_t)(x)+(NBPREFCNTP-1))>>BPREFCNTPSHIFT) -#define refcntpage_offset(x) ((__psunsigned_t)(x)&((NBPP-1)&~(NBPREFCNTP-1))) -#define align_to_refcntpage(x) ((__psunsigned_t)(x)&(~(NBPREFCNTP-1))) - -extern void migr_refcnt_read(sn0_refcnt_buf_t*); -extern void migr_refcnt_read_extended(sn0_refcnt_buf_t*); -extern int migr_refcnt_enabled(void); - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IA64_SN_SN1_HWCNTRS_H */ diff --git a/include/asm-ia64/sn/sn1/intr.h b/include/asm-ia64/sn/sn1/intr.h deleted file mode 100644 index a05b7898c0a69..0000000000000 --- a/include/asm-ia64/sn/sn1/intr.h +++ /dev/null @@ -1,237 +0,0 @@ -/* $Id: intr.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_INTR_H -#define _ASM_IA64_SN_SN1_INTR_H - -/* Subnode wildcard */ -#define SUBNODE_ANY (-1) - -/* Number of interrupt levels associated with each interrupt register. */ -#define N_INTPEND_BITS 64 - -#define INT_PEND0_BASELVL 0 -#define INT_PEND1_BASELVL 64 - -#define N_INTPENDJUNK_BITS 8 -#define INTPENDJUNK_CLRBIT 0x80 - -#include <asm/sn/intr_public.h> -#include <asm/sn/driver.h> -#include <asm/sn/xtalk/xtalk.h> -#include <asm/sn/hack.h> - -#ifndef __ASSEMBLY__ -#define II_NAMELEN 24 - -/* - * Dispatch table entry - contains information needed to call an interrupt - * routine. - */ -typedef struct intr_vector_s { - intr_func_t iv_func; /* Interrupt handler function */ - intr_func_t iv_prefunc; /* Interrupt handler prologue func */ - void *iv_arg; /* Argument to pass to handler */ - cpuid_t iv_mustruncpu; /* Where we must run. */ -} intr_vector_t; - -/* Interrupt information table. */ -typedef struct intr_info_s { - xtalk_intr_setfunc_t ii_setfunc; /* Function to set the interrupt - * destination and level register. - * It returns 0 (success) or an - * error code. - */ - void *ii_cookie; /* arg passed to setfunc */ - devfs_handle_t ii_owner_dev; /* device that owns this intr */ - char ii_name[II_NAMELEN]; /* Name of this intr. */ - int ii_flags; /* informational flags */ -} intr_info_t; - - -#define THD_CREATED 0x00000001 /* - * We've created a thread for this - * interrupt. - */ - -/* - * Bits for ii_flags: - */ -#define II_UNRESERVE 0 -#define II_RESERVE 1 /* Interrupt reserved. */ -#define II_INUSE 2 /* Interrupt connected */ -#define II_ERRORINT 4 /* INterrupt is an error condition */ -#define II_THREADED 8 /* Interrupt handler is threaded. */ - -/* - * Interrupt level wildcard - */ -#define INTRCONNECT_ANYBIT (-1) - -/* - * This structure holds information needed both to call and to maintain - * interrupts. The two are in separate arrays for the locality benefits. - * Since there's only one set of vectors per hub chip (but more than one - * CPU, the lock to change the vector tables must be here rather than in - * the PDA. - */ - -typedef struct intr_vecblk_s { - intr_vector_t vectors[N_INTPEND_BITS]; /* information needed to - call an intr routine. */ - intr_info_t info[N_INTPEND_BITS]; /* information needed only - to maintain interrupts. */ - spinlock_t vector_lock; /* Lock for this and the - masks in the PDA. */ - splfunc_t vector_spl; /* vector_lock req'd spl */ - int vector_state; /* Initialized to zero. - Set to INTR_INITED - by hubintr_init. - */ - int vector_count; /* Number of vectors - * reserved. - */ - int cpu_count[CPUS_PER_SUBNODE]; /* How many interrupts are - * connected to each CPU - */ - int ithreads_enabled; /* Are interrupt threads - * initialized on this node. - * and block? - */ -} intr_vecblk_t; - -/* Possible values for vector_state: */ -#define VECTOR_UNINITED 0 -#define VECTOR_INITED 1 -#define VECTOR_SET 2 - -#define hub_intrvect0 private.p_intmasks.dispatch0->vectors -#define hub_intrvect1 private.p_intmasks.dispatch1->vectors -#define hub_intrinfo0 private.p_intmasks.dispatch0->info -#define hub_intrinfo1 private.p_intmasks.dispatch1->info - -/* - * Macros to manipulate the interrupt register on the calling hub chip. - */ - -#define LOCAL_HUB_SEND_INTR(_level) LOCAL_HUB_S(PI_INT_PEND_MOD, \ - (0x100|(_level))) -#define REMOTE_HUB_PI_SEND_INTR(_hub, _sn, _level) \ - REMOTE_HUB_PI_S((_hub), _sn, PI_INT_PEND_MOD, (0x100|(_level))) - -#define REMOTE_CPU_SEND_INTR(_cpuid, _level) \ - REMOTE_HUB_PI_S(cpuid_to_nasid(_cpuid), \ - SUBNODE(cpuid_to_slice(_cpuid)), \ - PI_INT_PEND_MOD, (0x100|(_level))) - -/* - * When clearing the interrupt, make sure this clear does make it - * to the hub. Otherwise we could end up losing interrupts. - * We do an uncached load of the int_pend0 register to ensure this. - */ - -#define LOCAL_HUB_CLR_INTR(_level) \ - LOCAL_HUB_S(PI_INT_PEND_MOD, (_level)), \ - LOCAL_HUB_L(PI_INT_PEND0) -#define REMOTE_HUB_PI_CLR_INTR(_hub, _sn, _level) \ - REMOTE_HUB_PI_S((_hub), (_sn), PI_INT_PEND_MOD, (_level)), \ - REMOTE_HUB_PI_L((_hub), (_sn), PI_INT_PEND0) - -/* Special support for use by gfx driver only. Supports special gfx hub interrupt. */ -extern void install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg); - -void setrtvector(intr_func_t func); - -/* - * Interrupt blocking - */ -extern void intr_block_bit(cpuid_t cpu, int bit); -extern void intr_unblock_bit(cpuid_t cpu, int bit); - -#endif /* __ASSEMBLY__ */ - -/* - * Hard-coded interrupt levels: - */ - -/* - * L0 = SW1 - * L1 = SW2 - * L2 = INT_PEND0 - * L3 = INT_PEND1 - * L4 = RTC - * L5 = Profiling Timer - * L6 = Hub Errors - * L7 = Count/Compare (T5 counters) - */ - - -/* INT_PEND0 hard-coded bits. */ -#ifdef DEBUG_INTR_TSTAMP -/* hard coded interrupt level for interrupt latency test interrupt */ -#define CPU_INTRLAT_B 62 -#define CPU_INTRLAT_A 61 -#endif - -/* Hardcoded bits required by software. */ -#define MSC_MESG_INTR 9 -#define CPU_ACTION_B 8 -#define CPU_ACTION_A 7 - -/* These are determined by hardware: */ -#define CC_PEND_B 6 -#define CC_PEND_A 5 -#define UART_INTR 4 -#define PG_MIG_INTR 3 -#define GFX_INTR_B 2 -#define GFX_INTR_A 1 -#define RESERVED_INTR 0 - -/* INT_PEND1 hard-coded bits: */ -#define MSC_PANIC_INTR 63 -#define NI_ERROR_INTR 62 -#define MD_COR_ERR_INTR 61 -#define COR_ERR_INTR_B 60 -#define COR_ERR_INTR_A 59 -#define CLK_ERR_INTR 58 - -# define NACK_INT_B 57 -# define NACK_INT_A 56 -# define LB_ERROR 55 -# define XB_ERROR 54 - -#define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch Bridge Errors */ - -#define IP27_INTR_0 52 /* Reserved for PROM use */ -#define IP27_INTR_1 51 /* (do not use in Kernel) */ -#define IP27_INTR_2 50 -#define IP27_INTR_3 49 -#define IP27_INTR_4 48 -#define IP27_INTR_5 47 -#define IP27_INTR_6 46 -#define IP27_INTR_7 45 - -#define TLB_INTR_B 44 /* used for tlb flush random */ -#define TLB_INTR_A 43 - -#define LLP_PFAIL_INTR_B 42 /* see ml/SN/SN0/sysctlr.c */ -#define LLP_PFAIL_INTR_A 41 - -#define NI_BRDCAST_ERR_B 40 -#define NI_BRDCAST_ERR_A 39 - -# define IO_ERROR_INTR 38 /* set up by prom */ -# define DEBUG_INTR_B 37 /* used by symmon to stop all cpus */ -# define DEBUG_INTR_A 36 - -// These aren't strictly accurate or complete. See the -// Synergy Spec. for details. -#define SGI_UART_IRQ (65) -#define SGI_HUB_ERROR_IRQ (182) - -#endif /* _ASM_IA64_SN_SN1_INTR_H */ diff --git a/include/asm-ia64/sn/sn1/intr_public.h b/include/asm-ia64/sn/sn1/intr_public.h deleted file mode 100644 index 3d2d1e2d9d4d6..0000000000000 --- a/include/asm-ia64/sn/sn1/intr_public.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $Id: intr_public.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_INTR_PUBLIC_H -#define _ASM_IA64_SN_SN1_INTR_PUBLIC_H - -/* REMEMBER: If you change these, the whole world needs to be recompiled. - * It would also require changing the hubspl.s code and SN0/intr.c - * Currently, the spl code has no support for multiple INTPEND1 masks. - */ - -#define N_INTPEND0_MASKS 1 -#define N_INTPEND1_MASKS 1 - -#define INTPEND0_MAXMASK (N_INTPEND0_MASKS - 1) -#define INTPEND1_MAXMASK (N_INTPEND1_MASKS - 1) - -#ifndef __ASSEMBLY__ -#include <asm/sn/arch.h> - -struct intr_vecblk_s; /* defined in asm/sn/intr.h */ - -/* - * The following are necessary to create the illusion of a CEL - * on the IP27 hub. We'll add more priority levels soon, but for - * now, any interrupt in a particular band effectively does an spl. - * These must be in the PDA since they're different for each processor. - * Users of this structure must hold the vector_lock in the appropriate vector - * block before modifying the mask arrays. There's only one vector block - * for each Hub so a lock in the PDA wouldn't be adequate. - */ -typedef struct hub_intmasks_s { - /* - * The masks are stored with the lowest-priority (most inclusive) - * in the lowest-numbered masks (i.e., 0, 1, 2...). - */ - /* INT_PEND0: */ - hubreg_t intpend0_masks[N_INTPEND0_MASKS]; - /* INT_PEND1: */ - hubreg_t intpend1_masks[N_INTPEND1_MASKS]; - /* INT_PEND0: */ - struct intr_vecblk_s *dispatch0; - /* INT_PEND1: */ - struct intr_vecblk_s *dispatch1; -} hub_intmasks_t; - -#endif /* __ASSEMBLY__ */ -#endif /* _ASM_IA64_SN_SN1_INTR_PUBLIC_H */ diff --git a/include/asm-ia64/sn/sn1/ip27config.h b/include/asm-ia64/sn/sn1/ip27config.h deleted file mode 100644 index 71b92c46697a3..0000000000000 --- a/include/asm-ia64/sn/sn1/ip27config.h +++ /dev/null @@ -1,657 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_SN1_IP27CONFIG_H -#define _ASM_IA64_SN_SN1_IP27CONFIG_H - - -/* - * Structure: ip27config_s - * Typedef: ip27config_t - * Purpose: Maps out the region of the boot prom used to define - * configuration information. - * Notes: Corresponds to ip27config structure found in start.s. - * Fields are ulong where possible to facilitate IP27 PROM fetches. - */ - -#define CONFIG_INFO_OFFSET 0x60 - -#define IP27CONFIG_ADDR (LBOOT_BASE + \ - CONFIG_INFO_OFFSET) -#define IP27CONFIG_ADDR_NODE(n) (NODE_RBOOT_BASE(n) + \ - CONFIG_INFO_OFFSET) - -/* Offset to the config_type field within local ip27config structure */ -#define CONFIG_FLAGS_ADDR (IP27CONFIG_ADDR + 72) -/* Offset to the config_type field in the ip27config structure on - * node with nasid n - */ -#define CONFIG_FLAGS_ADDR_NODE(n) (IP27CONFIG_ADDR_NODE(n) + 72) - -/* Meaning of each valid bit in the config flags - * None are currently defined - */ - -/* Meaning of each mach_type value - */ -#define SN1_MACH_TYPE 0 - -/* - * Since 800 ns works well with various HUB frequencies, (such as 360, - * 380, 390, and 400 MHZ), we now use 800ns rtc cycle time instead of - * 1 microsec. - */ -#define IP27_RTC_FREQ 1250 /* 800ns cycle time */ - -#ifndef __ASSEMBLY__ - -typedef struct ip27config_s { /* KEEP IN SYNC w/ start.s & below */ - uint time_const; /* Time constant */ - uint r10k_mode; /* R10k boot mode bits */ - - uint64_t magic; /* CONFIG_MAGIC */ - - uint64_t freq_cpu; /* Hz */ - uint64_t freq_hub; /* Hz */ - uint64_t freq_rtc; /* Hz */ - - uint ecc_enable; /* ECC enable flag */ - uint fprom_cyc; /* FPROM_CYC speed control */ - - uint mach_type; /* Inidicate IP27 (0) or Sn00 (1) */ - - uint check_sum_adj; /* Used after config hdr overlay */ - /* to make the checksum 0 again */ - uint flash_count; /* Value incr'd on each PROM flash */ - uint fprom_wr; /* FPROM_WR speed control */ - - uint pvers_vers; /* Prom version number */ - uint pvers_rev; /* Prom revision number */ - uint config_type; /* To support special configurations - * (none currently defined) - */ -} ip27config_t; - -typedef struct { - uint r10k_mode; /* R10k boot mode bits */ - uint freq_cpu; /* Hz */ - uint freq_hub; /* Hz */ - char fprom_cyc; /* FPROM_CYC speed control */ - char mach_type; /* IP35(0) is only type defined */ - char fprom_wr; /* FPROM_WR speed control */ -} config_modifiable_t; - -#define IP27CONFIG (*(ip27config_t *) IP27CONFIG_ADDR) -#define IP27CONFIG_NODE(n) (*(ip27config_t *) IP27CONFIG_ADDR_NODE(n)) -#define SN00 0 /* IP35 has no Speedo equivalent */ - -/* Get the config flags from local ip27config */ -#define CONFIG_FLAGS (*(uint *) (CONFIG_FLAGS_ADDR)) - -/* Get the config flags from ip27config on the node - * with nasid n - */ -#define CONFIG_FLAGS_NODE(n) (*(uint *) (CONFIG_FLAGS_ADDR_NODE(n))) - -/* Macro to check if the local ip27config indicates a config - * of 12 p 4io - */ -#define CONFIG_12P4I (0) /* IP35 has no 12p4i equivalent */ - -/* Macro to check if the ip27config on node with nasid n - * indicates a config of 12 p 4io - */ -#define CONFIG_12P4I_NODE(n) (0) - -#endif /* __ASSEMBLY__ */ - -#if __ASSEMBLY__ - .struct 0 /* KEEP IN SYNC WITH C structure */ - -ip27c_time_const: .word 0 -ip27c_r10k_mode: .word 0 - -ip27c_magic: .dword 0 - -ip27c_freq_cpu: .dword 0 -ip27c_freq_hub: .dword 0 -ip27c_freq_rtc: .dword 0 - -ip27c_ecc_enable: .word 1 -ip27c_fprom_cyc: .word 0 - -ip27c_mach_type: .word 0 -ip27c_check_sum_adj: .word 0 - -ip27c_flash_count: .word 0 -ip27c_fprom_wr: .word 0 - -ip27c_pvers_vers: .word 0 -ip27c_pvers_rev: .word 0 - -ip27c_config_type: .word 0 /* To recognize special configs */ -#endif /* __ASSEMBLY__ */ - -/* - * R10000 Configuration Cycle - These define the SYSAD values used - * during the reset cycle. - */ - -#define IP27C_R10000_KSEG0CA_SHFT 0 -#define IP27C_R10000_KSEG0CA_MASK (7 << IP27C_R10000_KSEG0CA_SHFT) -#define IP27C_R10000_KSEG0CA(_B) ((_B) << IP27C_R10000_KSEG0CA_SHFT) - -#define IP27C_R10000_DEVNUM_SHFT 3 -#define IP27C_R10000_DEVNUM_MASK (3 << IP27C_R10000_DEVNUM_SHFT) -#define IP27C_R10000_DEVNUM(_B) ((_B) << IP27C_R10000_DEVNUM_SHFT) - -#define IP27C_R10000_CRPT_SHFT 5 -#define IP27C_R10000_CRPT_MASK (1 << IP27C_R10000_CRPT_SHFT) -#define IP27C_R10000_CPRT(_B) ((_B)<<IP27C_R10000_CRPT_SHFT) - -#define IP27C_R10000_PER_SHFT 6 -#define IP27C_R10000_PER_MASK (1 << IP27C_R10000_PER_SHFT) -#define IP27C_R10000_PER(_B) ((_B) << IP27C_R10000_PER_SHFT) - -#define IP27C_R10000_PRM_SHFT 7 -#define IP27C_R10000_PRM_MASK (3 << IP27C_R10000_PRM_SHFT) -#define IP27C_R10000_PRM(_B) ((_B) << IP27C_R10000_PRM_SHFT) - -#define IP27C_R10000_SCD_SHFT 9 -#define IP27C_R10000_SCD_MASK (0xf << IP27C_R10000_SCD_MASK) -#define IP27C_R10000_SCD(_B) ((_B) << IP27C_R10000_SCD_SHFT) - -#define IP27C_R10000_SCBS_SHFT 13 -#define IP27C_R10000_SCBS_MASK (1 << IP27C_R10000_SCBS_SHFT) -#define IP27C_R10000_SCBS(_B) (((_B)) << IP27C_R10000_SCBS_SHFT) - -#define IP27C_R10000_SCCE_SHFT 14 -#define IP27C_R10000_SCCE_MASK (1 << IP27C_R10000_SCCE_SHFT) -#define IP27C_R10000_SCCE(_B) ((_B) << IP27C_R10000_SCCE_SHFT) - -#define IP27C_R10000_ME_SHFT 15 -#define IP27C_R10000_ME_MASK (1 << IP27C_R10000_ME_SHFT) -#define IP27C_R10000_ME(_B) ((_B) << IP27C_R10000_ME_SHFT) - -#define IP27C_R10000_SCS_SHFT 16 -#define IP27C_R10000_SCS_MASK (7 << IP27C_R10000_SCS_SHFT) -#define IP27C_R10000_SCS(_B) ((_B) << IP27C_R10000_SCS_SHFT) - -#define IP27C_R10000_SCCD_SHFT 19 -#define IP27C_R10000_SCCD_MASK (7 << IP27C_R10000_SCCD_SHFT) -#define IP27C_R10000_SCCD(_B) ((_B) << IP27C_R10000_SCCD_SHFT) - -#define IP27C_R10000_DDR_SHFT 23 -#define IP27C_R10000_DDR_MASK (1 << IP27C_R10000_DDR_SHFT) -#define IP27C_R10000_DDR(_B) ((_B) << IP27C_R10000_DDR_SHFT) - -#define IP27C_R10000_SCCT_SHFT 25 -#define IP27C_R10000_SCCT_MASK (0xf << IP27C_R10000_SCCT_SHFT) -#define IP27C_R10000_SCCT(_B) ((_B) << IP27C_R10000_SCCT_SHFT) - -#define IP27C_R10000_ODSC_SHFT 29 -#define IP27C_R10000_ODSC_MASK (1 << IP27C_R10000_ODSC_SHFT) -#define IP27C_R10000_ODSC(_B) ((_B) << IP27C_R10000_ODSC_SHFT) - -#define IP27C_R10000_ODSYS_SHFT 30 -#define IP27C_R10000_ODSYS_MASK (1 << IP27C_R10000_ODSYS_SHFT) -#define IP27C_R10000_ODSYS(_B) ((_B) << IP27C_R10000_ODSYS_SHFT) - -#define IP27C_R10000_CTM_SHFT 31 -#define IP27C_R10000_CTM_MASK (1 << IP27C_R10000_CTM_SHFT) -#define IP27C_R10000_CTM(_B) ((_B) << IP27C_R10000_CTM_SHFT) - -#define IP27C_MHZ(x) (1000000 * (x)) -#define IP27C_KHZ(x) (1000 * (x)) -#define IP27C_MB(x) ((x) << 20) - -/* - * PROM Configurations - */ - -#define CONFIG_MAGIC 0x69703237636f6e66 - -/* The high 32 bits of the "mode bits". Bits 7..0 contain one more - * than the number of 5ms clocks in the 100ms "long delay" intervals - * of the TRex reset sequence. Bit 8 is the "synergy mode" bit. - */ -#define CONFIG_TIME_CONST 0x15 - -#define CONFIG_ECC_ENABLE 1 -#define CONFIG_CHECK_SUM_ADJ 0 -#define CONFIG_DEFAULT_FLASH_COUNT 0 - -/* - * Some promICEs have trouble if CONFIG_FPROM_SETUP is too low. - * The nominal value for 100 MHz hub is 5, for 200MHz bedrock is 16. - * any update to the below should also reflected in the logic in - * IO7prom/flashprom.c function _verify_config_info and _fill_in_config_info - */ - -/* default junk bus timing values to use */ -#define CONFIG_SYNERGY_ENABLE 0xff -#define CONFIG_SYNERGY_SETUP 0xff -#define CONFIG_UART_ENABLE 0x0c -#define CONFIG_UART_SETUP 0x02 -#define CONFIG_FPROM_ENABLE 0x10 -#define CONFIG_FPROM_SETUP 0x10 - -#define CONFIG_FREQ_RTC IP27C_KHZ(IP27_RTC_FREQ) - -#ifndef __ASSEMBLY__ - -/* we are going to define all the known configs is a table - * for building hex images we will pull out the particular - * slice we care about by using the IP27_CONFIG_XX_XX as - * entries into the table - * to keep the table of reasonable size we only include the - * values that differ across configurations - * please note then that this makes assumptions about what - * will and will not change across configurations - */ - -/* these numbers are as the are ordered in the table below */ -#define IP27_CONFIG_UNKNOWN (-1) -#define IP27_CONFIG_SN1_1MB_200_400_200_TABLE 0 -#define IP27_CONFIG_SN00_4MB_100_200_133_TABLE 1 -#define IP27_CONFIG_SN1_4MB_200_400_267_TABLE 2 -#define IP27_CONFIG_SN1_8MB_200_500_250_TABLE 3 -#define IP27_CONFIG_SN1_8MB_200_400_267_TABLE 4 -#define IP27_CONFIG_SN1_4MB_180_360_240_TABLE 5 -#define NUMB_IP_CONFIGS 6 - -#ifdef DEF_IP_CONFIG_TABLE -/* - * N.B.: A new entry needs to be added here everytime a new config is added - * The table is indexed by the PIMM PSC value - */ - -static int psc_to_flash_config[] = { - IP27_CONFIG_SN1_4MB_200_400_267_TABLE, /* 0x0 */ - IP27_CONFIG_SN1_8MB_200_500_250_TABLE, /* 0x1 */ - IP27_CONFIG_SN1_8MB_200_400_267_TABLE, /* 0x2 */ - IP27_CONFIG_UNKNOWN, /* 0x3 */ - IP27_CONFIG_UNKNOWN, /* 0x4 */ - IP27_CONFIG_UNKNOWN, /* 0x5 */ - IP27_CONFIG_UNKNOWN, /* 0x6 */ - IP27_CONFIG_UNKNOWN, /* 0x7 */ - IP27_CONFIG_SN1_4MB_180_360_240_TABLE, /* 0x8 */ - IP27_CONFIG_UNKNOWN, /* 0x9 */ - IP27_CONFIG_UNKNOWN, /* 0xa */ - IP27_CONFIG_UNKNOWN, /* 0xb */ - IP27_CONFIG_UNKNOWN, /* 0xc */ - IP27_CONFIG_UNKNOWN, /* 0xd */ - IP27_CONFIG_SN00_4MB_100_200_133_TABLE, /* 0xe O200 PIMM for bringup */ - IP27_CONFIG_UNKNOWN /* 0xf == PIMM not installed */ -}; - -static config_modifiable_t ip_config_table[NUMB_IP_CONFIGS] = { -/* the 1MB_200_400_200 values (Generic settings, will work for any config.) */ -{ - (IP27C_R10000_KSEG0CA(5) + \ - IP27C_R10000_DEVNUM(0) + \ - IP27C_R10000_CPRT(0) + \ - IP27C_R10000_PER(0) + \ - IP27C_R10000_PRM(3) + \ - IP27C_R10000_SCD(3) + \ - IP27C_R10000_SCBS(1) + \ - IP27C_R10000_SCCE(0) + \ - IP27C_R10000_ME(1) + \ - IP27C_R10000_SCS(1) + \ - IP27C_R10000_SCCD(3) + \ - IP27C_R10000_SCCT(9) + \ - IP27C_R10000_ODSC(0) + \ - IP27C_R10000_ODSYS(1) + \ - IP27C_R10000_CTM(0)), - IP27C_MHZ(400), - IP27C_MHZ(200), - CONFIG_FPROM_SETUP, - SN1_MACH_TYPE, - CONFIG_FPROM_ENABLE -}, - -/* the 4MB_100_200_133 values (O200 PIMM w/translation board, PSC 0xe) - * (SysAD at 100MHz (SCD=3), and bedrock core at 200 MHz) */ -{ - /* ODSYS == 0 means HSTL1 on SysAD bus; other PIMMs use HSTL2 */ - (IP27C_R10000_KSEG0CA(5) + \ - IP27C_R10000_DEVNUM(0) + \ - IP27C_R10000_CPRT(0) + \ - IP27C_R10000_PER(0) + \ - IP27C_R10000_PRM(3) + \ - IP27C_R10000_SCD(3) + \ - IP27C_R10000_SCBS(1) + \ - IP27C_R10000_SCCE(0) + \ - IP27C_R10000_ME(1) + \ - IP27C_R10000_SCS(3) + \ - IP27C_R10000_SCCD(2) + \ - IP27C_R10000_SCCT(9) + \ - IP27C_R10000_ODSC(0) + \ - IP27C_R10000_ODSYS(0) + \ - IP27C_R10000_CTM(0)), - IP27C_MHZ(200), - IP27C_MHZ(200), - CONFIG_FPROM_SETUP, - SN1_MACH_TYPE, - CONFIG_FPROM_ENABLE -}, - -/* 4MB_200_400_267 values (R12KS, 3.7ns, LWR, 030-1602-001, PSC 0x0) */ -{ - (IP27C_R10000_KSEG0CA(5) + \ - IP27C_R10000_DEVNUM(0) + \ - IP27C_R10000_CPRT(0) + \ - IP27C_R10000_PER(0) + \ - IP27C_R10000_PRM(3) + \ - IP27C_R10000_SCD(3) + \ - IP27C_R10000_SCBS(1) + \ - IP27C_R10000_SCCE(0) + \ - IP27C_R10000_ME(1) + \ - IP27C_R10000_SCS(3) + \ - IP27C_R10000_SCCD(2) + \ - IP27C_R10000_SCCT(0xa) + \ - IP27C_R10000_ODSC(0) + \ - IP27C_R10000_ODSYS(1) + \ - IP27C_R10000_CTM(0)), - IP27C_MHZ(400), - IP27C_MHZ(200), - CONFIG_FPROM_SETUP, - SN1_MACH_TYPE, - CONFIG_FPROM_ENABLE -}, - -/* 8MB_200_500_250 values (R14K, 4.0ns, DDR1, 030-1520-001, PSC 0x1) */ -{ - (IP27C_R10000_KSEG0CA(5) + \ - IP27C_R10000_DEVNUM(0) + \ - IP27C_R10000_CPRT(0) + \ - IP27C_R10000_PER(0) + \ - IP27C_R10000_PRM(3) + \ - IP27C_R10000_SCD(4) + \ - IP27C_R10000_SCBS(1) + \ - IP27C_R10000_SCCE(0) + \ - IP27C_R10000_ME(1) + \ - IP27C_R10000_SCS(4) + \ - IP27C_R10000_DDR(1) + \ - IP27C_R10000_SCCD(3) + \ - IP27C_R10000_SCCT(0xa) + \ - IP27C_R10000_ODSC(0) + \ - IP27C_R10000_ODSYS(1) + \ - IP27C_R10000_CTM(0)), - IP27C_MHZ(500), - IP27C_MHZ(200), - CONFIG_FPROM_SETUP, - SN1_MACH_TYPE, - CONFIG_FPROM_ENABLE -}, - -/* 8MB_200_400_267 values (R12KS, 3.7ns, LWR, 030-1616-001, PSC 0x2) */ -{ - (IP27C_R10000_KSEG0CA(5) + \ - IP27C_R10000_DEVNUM(0) + \ - IP27C_R10000_CPRT(0) + \ - IP27C_R10000_PER(0) + \ - IP27C_R10000_PRM(3) + \ - IP27C_R10000_SCD(3) + \ - IP27C_R10000_SCBS(1) + \ - IP27C_R10000_SCCE(0) + \ - IP27C_R10000_ME(1) + \ - IP27C_R10000_SCS(4) + \ - IP27C_R10000_SCCD(2) + \ - IP27C_R10000_SCCT(0xa) + \ - IP27C_R10000_ODSC(0) + \ - IP27C_R10000_ODSYS(1) + \ - IP27C_R10000_CTM(0)), - IP27C_MHZ(400), - IP27C_MHZ(200), - CONFIG_FPROM_SETUP, - SN1_MACH_TYPE, - CONFIG_FPROM_ENABLE -}, - -/* 4MB_180_360_240 values (R12KS, 3.7ns, LWR, 030-1627-001, PSC 0x8) - * (SysAD at 180 MHz (SCD=3, the fastest possible), bedrock core at 200MHz) */ -{ - (IP27C_R10000_KSEG0CA(5) + \ - IP27C_R10000_DEVNUM(0) + \ - IP27C_R10000_CPRT(0) + \ - IP27C_R10000_PER(0) + \ - IP27C_R10000_PRM(3) + \ - IP27C_R10000_SCD(3) + \ - IP27C_R10000_SCBS(1) + \ - IP27C_R10000_SCCE(0) + \ - IP27C_R10000_ME(1) + \ - IP27C_R10000_SCS(3) + \ - IP27C_R10000_SCCD(2) + \ - IP27C_R10000_SCCT(9) + \ - IP27C_R10000_ODSC(0) + \ - IP27C_R10000_ODSYS(1) + \ - IP27C_R10000_CTM(0)), - IP27C_MHZ(360), - IP27C_MHZ(200), - CONFIG_FPROM_SETUP, - SN1_MACH_TYPE, - CONFIG_FPROM_ENABLE -}, - -}; -#else -extern config_modifiable_t ip_config_table[]; -#endif /* DEF_IP27_CONFIG_TABLE */ - -#ifdef IP27_CONFIG_SN00_4MB_100_200_133 -#define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].r10k_mode -#define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].freq_cpu -#define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].freq_hub -#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].fprom_cyc -#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].mach_type -#define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].fprom_wr -#endif /* IP27_CONFIG_SN00_4MB_100_200_133 */ - -#ifdef IP27_CONFIG_SN1_1MB_200_400_200 -#define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].r10k_mode -#define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].freq_cpu -#define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].freq_hub -#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].fprom_cyc -#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].mach_type -#define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].fprom_wr -#endif /* IP27_CONFIG_SN1_1MB_200_400_200 */ - -#ifdef IP27_CONFIG_SN1_4MB_200_400_267 -#define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].r10k_mode -#define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].freq_cpu -#define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].freq_hub -#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].fprom_cyc -#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].mach_type -#define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].fprom_wr -#endif /* IP27_CONFIG_SN1_4MB_200_400_267 */ - -#ifdef IP27_CONFIG_SN1_8MB_200_500_250 -#define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].r10k_mode -#define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].freq_cpu -#define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].freq_hub -#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].fprom_cyc -#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].mach_type -#define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].fprom_wr -#endif /* IP27_CONFIG_SN1_8MB_200_500_250 */ - -#ifdef IP27_CONFIG_SN1_8MB_200_400_267 -#define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].r10k_mode -#define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].freq_cpu -#define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].freq_hub -#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].fprom_cyc -#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].mach_type -#define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].fprom_wr -#endif /* IP27_CONFIG_SN1_8MB_200_400_267 */ - -#ifdef IP27_CONFIG_SN1_4MB_180_360_240 -#define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].r10k_mode -#define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].freq_cpu -#define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].freq_hub -#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_cyc -#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].mach_type -#define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_wr -#endif /* IP27_CONFIG_SN1_4MB_180_360_240 */ - -#endif /* __ASSEMBLY__ */ - -#if __ASSEMBLY__ - -/* these need to be in here since we need assembly definitions - * for building hex images (as required by start.s) - */ -#ifdef IP27_CONFIG_SN00_4MB_100_200_133 -#define BRINGUP_PRM_VAL 3 -#define CONFIG_CPU_MODE \ - (IP27C_R10000_KSEG0CA(5) + \ - IP27C_R10000_DEVNUM(0) + \ - IP27C_R10000_CPRT(0) + \ - IP27C_R10000_PER(0) + \ - IP27C_R10000_PRM(BRINGUP_PRM_VAL) + \ - IP27C_R10000_SCD(3) + \ - IP27C_R10000_SCBS(1) + \ - IP27C_R10000_SCCE(0) + \ - IP27C_R10000_ME(1) + \ - IP27C_R10000_SCS(3) + \ - IP27C_R10000_SCCD(2) + \ - IP27C_R10000_SCCT(9) + \ - IP27C_R10000_ODSC(0) + \ - IP27C_R10000_ODSYS(0) + \ - IP27C_R10000_CTM(0)) -#define CONFIG_FREQ_CPU IP27C_MHZ(200) -#define CONFIG_FREQ_HUB IP27C_MHZ(200) -#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP -#define CONFIG_MACH_TYPE SN1_MACH_TYPE -#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE -#endif /* IP27_CONFIG_SN00_4MB_100_200_133 */ - -#ifdef IP27_CONFIG_SN1_1MB_200_400_200 -#define CONFIG_CPU_MODE \ - (IP27C_R10000_KSEG0CA(5) + \ - IP27C_R10000_DEVNUM(0) + \ - IP27C_R10000_CPRT(0) + \ - IP27C_R10000_PER(0) + \ - IP27C_R10000_PRM(3) + \ - IP27C_R10000_SCD(3) + \ - IP27C_R10000_SCBS(1) + \ - IP27C_R10000_SCCE(0) + \ - IP27C_R10000_ME(1) + \ - IP27C_R10000_SCS(1) + \ - IP27C_R10000_SCCD(3) + \ - IP27C_R10000_SCCT(9) + \ - IP27C_R10000_ODSC(0) + \ - IP27C_R10000_ODSYS(1) + \ - IP27C_R10000_CTM(0)) -#define CONFIG_FREQ_CPU IP27C_MHZ(400) -#define CONFIG_FREQ_HUB IP27C_MHZ(200) -#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP -#define CONFIG_MACH_TYPE SN1_MACH_TYPE -#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE -#endif /* IP27_CONFIG_SN1_1MB_200_400_200 */ - -#ifdef IP27_CONFIG_SN1_4MB_200_400_267 -#define CONFIG_CPU_MODE \ - (IP27C_R10000_KSEG0CA(5) + \ - IP27C_R10000_DEVNUM(0) + \ - IP27C_R10000_CPRT(0) + \ - IP27C_R10000_PER(0) + \ - IP27C_R10000_PRM(3) + \ - IP27C_R10000_SCD(3) + \ - IP27C_R10000_SCBS(1) + \ - IP27C_R10000_SCCE(0) + \ - IP27C_R10000_ME(1) + \ - IP27C_R10000_SCS(3) + \ - IP27C_R10000_SCCD(2) + \ - IP27C_R10000_SCCT(0xa) + \ - IP27C_R10000_ODSC(0) + \ - IP27C_R10000_ODSYS(1) + \ - IP27C_R10000_CTM(0)) -#define CONFIG_FREQ_CPU IP27C_MHZ(400) -#define CONFIG_FREQ_HUB IP27C_MHZ(200) -#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP -#define CONFIG_MACH_TYPE SN1_MACH_TYPE -#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE -#endif /* IP27_CONFIG_SN1_4MB_200_400_267 */ - -#ifdef IP27_CONFIG_SN1_8MB_200_500_250 -#define CONFIG_CPU_MODE \ - (IP27C_R10000_KSEG0CA(5) + \ - IP27C_R10000_DEVNUM(0) + \ - IP27C_R10000_CPRT(0) + \ - IP27C_R10000_PER(0) + \ - IP27C_R10000_PRM(3) + \ - IP27C_R10000_SCD(4) + \ - IP27C_R10000_SCBS(1) + \ - IP27C_R10000_SCCE(0) + \ - IP27C_R10000_ME(1) + \ - IP27C_R10000_SCS(4) + \ - IP27C_R10000_SCCD(3) + \ - IP27C_R10000_DDR(1) + \ - IP27C_R10000_SCCT(0xa) + \ - IP27C_R10000_ODSC(0) + \ - IP27C_R10000_ODSYS(1) + \ - IP27C_R10000_CTM(0)) -#define CONFIG_FREQ_CPU IP27C_MHZ(500) -#define CONFIG_FREQ_HUB IP27C_MHZ(200) -#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP -#define CONFIG_MACH_TYPE SN1_MACH_TYPE -#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE -#endif /* IP27_CONFIG_SN1_8MB_200_500_250 */ - -#ifdef IP27_CONFIG_SN1_8MB_200_400_267 -#define CONFIG_CPU_MODE \ - (IP27C_R10000_KSEG0CA(5) + \ - IP27C_R10000_DEVNUM(0) + \ - IP27C_R10000_CPRT(0) + \ - IP27C_R10000_PER(0) + \ - IP27C_R10000_PRM(3) + \ - IP27C_R10000_SCD(3) + \ - IP27C_R10000_SCBS(1) + \ - IP27C_R10000_SCCE(0) + \ - IP27C_R10000_ME(1) + \ - IP27C_R10000_SCS(4) + \ - IP27C_R10000_SCCD(2) + \ - IP27C_R10000_SCCT(0xa) + \ - IP27C_R10000_ODSC(0) + \ - IP27C_R10000_ODSYS(1) + \ - IP27C_R10000_CTM(0)) -#define CONFIG_FREQ_CPU IP27C_MHZ(400) -#define CONFIG_FREQ_HUB IP27C_MHZ(200) -#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP -#define CONFIG_MACH_TYPE SN1_MACH_TYPE -#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE -#endif /* IP27_CONFIG_SN1_8MB_200_400_267 */ - -#ifdef IP27_CONFIG_SN1_4MB_180_360_240 -#define CONFIG_CPU_MODE \ - (IP27C_R10000_KSEG0CA(5) + \ - IP27C_R10000_DEVNUM(0) + \ - IP27C_R10000_CPRT(0) + \ - IP27C_R10000_PER(0) + \ - IP27C_R10000_PRM(3) + \ - IP27C_R10000_SCD(3) + \ - IP27C_R10000_SCBS(1) + \ - IP27C_R10000_SCCE(0) + \ - IP27C_R10000_ME(1) + \ - IP27C_R10000_SCS(3) + \ - IP27C_R10000_SCCD(2) + \ - IP27C_R10000_SCCT(9) + \ - IP27C_R10000_ODSC(0) + \ - IP27C_R10000_ODSYS(1) + \ - IP27C_R10000_CTM(0)) -#define CONFIG_FREQ_CPU IP27C_MHZ(360) -#define CONFIG_FREQ_HUB IP27C_MHZ(200) -#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP -#define CONFIG_MACH_TYPE SN1_MACH_TYPE -#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE -#endif /* IP27_CONFIG_SN1_4MB_180_360_240 */ - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_IA64_SN_SN1_IP27CONFIG_H */ diff --git a/include/asm-ia64/sn/sn1/mem_refcnt.h b/include/asm-ia64/sn/sn1/mem_refcnt.h deleted file mode 100644 index 80acfffd4999d..0000000000000 --- a/include/asm-ia64/sn/sn1/mem_refcnt.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_MEM_REFCNT_H -#define _ASM_IA64_SN_SN1_MEM_REFCNT_H - -extern int mem_refcnt_attach(devfs_handle_t hub); -extern int mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp); -extern int mem_refcnt_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp); -extern int mem_refcnt_mmap(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot); -extern int mem_refcnt_unmap(devfs_handle_t dev, vhandl_t *vt); -extern int mem_refcnt_ioctl(devfs_handle_t dev, - int cmd, - void *arg, - int mode, - cred_t *cred_p, - int *rvalp); - - -#endif /* _ASM_IA64_SN_SN1_MEM_REFCNT_H */ diff --git a/include/asm-ia64/sn/sn1/mmzone_sn1.h b/include/asm-ia64/sn/sn1/mmzone_sn1.h deleted file mode 100644 index a9e1f9cdd1b90..0000000000000 --- a/include/asm-ia64/sn/sn1/mmzone_sn1.h +++ /dev/null @@ -1,149 +0,0 @@ -#ifndef _ASM_IA64_SN_MMZONE_SN1_H -#define _ASM_IA64_SN_MMZONE_SN1_H - -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 2000-2002 Silicon Graphics, Inc. All rights reserved. - */ - -#include <linux/config.h> - - -/* - * SGI SN1 Arch defined values - * - * An SN1 physical address is broken down as follows: - * - * +-----------------------------------------+ - * | | | | node offset | - * | unused | AS | node |-------------------| - * | | | | cn | clump offset | - * +-----------------------------------------+ - * 6 4 4 4 3 3 3 3 2 0 - * 3 4 3 0 9 3 2 0 9 0 - * - * bits 63-44 Unused - must be zero - * bits 43-40 Address space ID. Cached memory has a value of 0. - * Chipset & IO addresses have non-zero values. - * bits 39-33 Node number. Note that some configurations do NOT - * have a node zero. - * bits 32-0 Node offset. - * - * The node offset can be further broken down as: - * bits 32-30 Clump (bank) number. - * bits 29-0 Clump (bank) offset. - * - * A node consists of up to 8 clumps (banks) of memory. A clump may be empty, or may be - * populated with a single contiguous block of memory starting at clump - * offset 0. The size of the block is (2**n) * 64MB, where 0<n<5. - * - * - * NOTE: This file exports symbols prefixed with "PLAT_". Symbols prefixed with - * "SN_" are intended for internal use only and should not be used in - * any platform independent code. - * - * This file is also responsible for exporting the following definitions: - * cnodeid_t Define a compact node id. - */ - -typedef signed short cnodeid_t; - -#define SN1_BANKS_PER_NODE 8 -#define SN1_NODE_SIZE (8UL*1024*1024*1024) /* 8 GB per node */ -#define SN1_BANK_SIZE (SN1_NODE_SIZE/SN1_BANKS_PER_NODE) -#define SN1_NODE_SHIFT 33 -#define SN1_NODE_MASK 0x7fUL -#define SN1_NODE_OFFSET_MASK (SN1_NODE_SIZE-1) -#define SN1_NODE_NUMBER(addr) (((unsigned long)(addr) >> SN1_NODE_SHIFT) & SN1_NODE_MASK) -#define SN1_NODE_CLUMP_NUMBER(addr) (((unsigned long)(addr) >>30) & 7) -#define SN1_NODE_OFFSET(addr) (((unsigned long)(addr)) & SN1_NODE_OFFSET_MASK) -#define SN1_KADDR(nasid, offset) (((unsigned long)(nasid)<<SN1_NODE_SHIFT) | (offset) | PAGE_OFFSET) - - -#define PLAT_MAX_NODE_NUMBER 128 /* Maximum node number +1 */ -#define PLAT_MAX_COMPACT_NODES 128 /* Maximum number of nodes in SSI */ - -#define PLAT_MAX_PHYS_MEMORY (1UL << 40) - - - -/* - * On the SN platforms, a clump is the same as a memory bank. - */ -#define PLAT_CLUMPS_PER_NODE SN1_BANKS_PER_NODE -#define PLAT_CLUMP_OFFSET(addr) ((unsigned long)(addr) & 0x3fffffffUL) -#define PLAT_CLUMPSIZE (SN1_NODE_SIZE/PLAT_CLUMPS_PER_NODE) -#define PLAT_MAXCLUMPS (PLAT_CLUMPS_PER_NODE*PLAT_MAX_COMPACT_NODES) - - - - -/* - * PLAT_VALID_MEM_KADDR returns a boolean to indicate if a kaddr is potentially a - * valid cacheable identity mapped RAM memory address. - * Note that the RAM may or may not actually be present!! - */ -#define SN1_VALID_KERN_ADDR_MASK 0xffffff0000000000UL -#define SN1_VALID_KERN_ADDR_VALUE 0xe000000000000000UL -#define PLAT_VALID_MEM_KADDR(kaddr) (((unsigned long)(kaddr) & SN1_VALID_KERN_ADDR_MASK) == SN1_VALID_KERN_ADDR_VALUE) - - - -/* - * Memory is conceptually divided into chunks. A chunk is either - * completely present, or else the kernel assumes it is completely - * absent. Each node consists of a number of possibly discontiguous chunks. - */ -#define SN1_CHUNKSHIFT 26 /* 64 MB */ -#define PLAT_CHUNKSIZE (1UL << SN1_CHUNKSHIFT) -#define PLAT_CHUNKNUM(addr) (((addr) & (PLAT_MAX_PHYS_MEMORY-1)) >> SN1_CHUNKSHIFT) - - -/* - * Given a kaddr, find the nid (compact nodeid) - */ -#ifdef CONFIG_IA64_SGI_SN_DEBUG -#define DISCONBUG(kaddr) panic("DISCONTIG BUG: line %d, %s. kaddr 0x%lx", \ - __LINE__, __FILE__, (long)(kaddr)) - -#define KVADDR_TO_NID(kaddr) ({long _ktn=(long)(kaddr); \ - kern_addr_valid(_ktn) ? \ - local_node_data->physical_node_map[SN1_NODE_NUMBER(_ktn)] :\ - (DISCONBUG(_ktn), 0UL);}) -#else -#define KVADDR_TO_NID(kaddr) (local_node_data->physical_node_map[SN1_NODE_NUMBER(kaddr)]) -#endif - - - -/* - * Given a kaddr, find the index into the clump_mem_map_base array of the page struct entry - * for the first page of the clump. - */ -#define PLAT_CLUMP_MEM_MAP_INDEX(kaddr) ({long _kmmi=(long)(kaddr); \ - KVADDR_TO_NID(_kmmi) * PLAT_CLUMPS_PER_NODE + \ - SN1_NODE_CLUMP_NUMBER(_kmmi);}) - - -/* - * Calculate a "goal" value to be passed to __alloc_bootmem_node for allocating structures on - * nodes so that they don't alias to the same line in the cache as the previous allocated structure. - * This macro takes an address of the end of previous allocation, rounds it to a page boundary & - * changes the node number. - */ -#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) __pa(SN1_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnode]), \ - (SN1_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT)) - - - - -/* - * Convert a proximity domain number (from the ACPI tables) into a physical node number. - */ - -#define PLAT_PXM_TO_PHYS_NODE_NUMBER(pxm) (pxm) - -#endif /* _ASM_IA64_SN_MMZONE_SN1_H */ diff --git a/include/asm-ia64/sn/sn1/slotnum.h b/include/asm-ia64/sn/sn1/slotnum.h deleted file mode 100644 index 1d5f05a70e539..0000000000000 --- a/include/asm-ia64/sn/sn1/slotnum.h +++ /dev/null @@ -1,87 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_SN1_SLOTNUM_H -#define _ASM_IA64_SN_SN1_SLOTNUM_H - -#define SLOTNUM_MAXLENGTH 16 - -/* - * This file attempts to define a slot number space across all slots. - * - * Node slots - * Router slots - * Crosstalk slots - * - * Other slots are children of their parent crosstalk slot: - * PCI slots - * VME slots - * - * The PCI class has been added since the XBridge ASIC on SN-MIPS - * has built-in PCI bridges (2). On IBricks, widget E & F serve - * PCI busses, and on PBricks all widgets serve as PCI busses - * with the use of the super-bridge mode of the XBridge ASIC. - */ - -#define SLOTNUM_NODE_CLASS 0x00 /* Node */ -#define SLOTNUM_ROUTER_CLASS 0x10 /* Router */ -#define SLOTNUM_XTALK_CLASS 0x20 /* Xtalk */ -#define SLOTNUM_MIDPLANE_CLASS 0x30 /* Midplane */ -#define SLOTNUM_XBOW_CLASS 0x40 /* Xbow */ -#define SLOTNUM_KNODE_CLASS 0x50 /* Kego node */ -#define SLOTNUM_PCI_CLASS 0x60 /* PCI widgets on XBridge */ -#define SLOTNUM_INVALID_CLASS 0xf0 /* Invalid */ - -#define SLOTNUM_CLASS_MASK 0xf0 -#define SLOTNUM_SLOT_MASK 0x0f - -#define SLOTNUM_GETCLASS(_sn) ((_sn) & SLOTNUM_CLASS_MASK) -#define SLOTNUM_GETSLOT(_sn) ((_sn) & SLOTNUM_SLOT_MASK) - -/* This determines module to pnode mapping. */ -/* NODESLOTS_PER_MODULE has changed from 4 to 6 - * to support the 12P 4IO configuration. This change - * helps in minimum number of changes to code which - * depend on the number of node boards within a module. - */ -#define NODESLOTS_PER_MODULE 6 -#define NODESLOTS_PER_MODULE_SHFT 2 - -#define HIGHEST_I2C_VISIBLE_NODESLOT 4 -#define RTRSLOTS_PER_MODULE 2 - -#if __KERNEL__ -#include <asm/sn/xtalk/xtalk.h> - -extern slotid_t xbwidget_to_xtslot(int crossbow, int widget); -extern slotid_t hub_slotbits_to_slot(slotid_t slotbits); -extern slotid_t hub_slot_to_crossbow(slotid_t hub_slot); -extern slotid_t router_slotbits_to_slot(slotid_t slotbits); -extern slotid_t get_node_slotid(nasid_t nasid); -extern slotid_t get_my_slotid(void); -extern slotid_t get_node_crossbow(nasid_t); -extern xwidgetnum_t hub_slot_to_widget(slotid_t); -extern void get_slotname(slotid_t, char *); -extern void get_my_slotname(char *); -extern slotid_t get_widget_slotnum(int xbow, int widget); -extern void get_widget_slotname(int, int, char *); -extern void router_slotbits_to_slotname(int, char *); -extern slotid_t meta_router_slotbits_to_slot(slotid_t) ; -extern slotid_t hub_slot_get(void); - -extern int node_can_talk_to_elsc(void); - -extern int slot_to_widget(int) ; -#define MAX_IO_SLOT_NUM 12 -#define MAX_NODE_SLOT_NUM 4 -#define MAX_ROUTER_SLOTNUM 2 - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IA64_SN_SN1_SLOTNUM_H */ diff --git a/include/asm-ia64/sn/sn1/sn_private.h b/include/asm-ia64/sn/sn1/sn_private.h deleted file mode 100644 index 27ebfe4c8157f..0000000000000 --- a/include/asm-ia64/sn/sn1/sn_private.h +++ /dev/null @@ -1,292 +0,0 @@ -/* $Id: sn_private.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN1_SN_PRIVATE_H -#define _ASM_IA64_SN_SN1_SN_PRIVATE_H - -#include <asm/sn/nodepda.h> -#include <asm/sn/xtalk/xwidget.h> -#include <asm/sn/xtalk/xtalk_private.h> - -extern nasid_t master_nasid; - -/* promif.c */ -#ifdef LATER -extern cpuid_t cpu_node_probe(cpumask_t *cpumask, int *numnodes); -#endif -extern void he_arcs_set_vectors(void); -extern void mem_init(void); -#ifdef LATER -extern int cpu_enabled(cpuid_t); -#endif -extern void cpu_unenable(cpuid_t); -extern nasid_t get_lowest_nasid(void); -extern __psunsigned_t get_master_bridge_base(void); -extern void set_master_bridge_base(void); -extern int check_nasid_equiv(nasid_t, nasid_t); -extern nasid_t get_console_nasid(void); -extern char get_console_pcislot(void); -#ifdef LATER -extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int); -#endif - -extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid); - -/* memsupport.c */ -extern void poison_state_alter_range(__psunsigned_t start, int len, int poison); -extern int memory_present(paddr_t); -extern int memory_read_accessible(paddr_t); -extern int memory_write_accessible(paddr_t); -extern void memory_set_access(paddr_t, int, int); -extern void show_dir_state(paddr_t, void (*)(char *, ...)); -extern void check_dir_state(nasid_t, int, void (*)(char *, ...)); -extern void set_dir_owner(paddr_t, int); -extern void set_dir_state(paddr_t, int); -extern void set_dir_state_POISONED(paddr_t); -extern void set_dir_state_UNOWNED(paddr_t); -extern int is_POISONED_dir_state(paddr_t); -extern int is_UNOWNED_dir_state(paddr_t); -extern void get_dir_ent(paddr_t paddr, int *state, - uint64_t *vec_ptr, hubreg_t *elo); - -/* intr.c */ -extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name); -extern void intr_unreserve_level(cpuid_t cpu, int level); -extern int intr_connect_level(cpuid_t cpu, int bit, ilvl_t mask_no, - intr_func_t intr_prefunc); -extern int intr_disconnect_level(cpuid_t cpu, int bit); -extern cpuid_t intr_heuristic(devfs_handle_t dev, device_desc_t dev_desc, - int req_bit,int intr_resflags,devfs_handle_t owner_dev, - char *intr_name,int *resp_bit); -extern void intr_block_bit(cpuid_t cpu, int bit); -extern void intr_unblock_bit(cpuid_t cpu, int bit); -extern void setrtvector(intr_func_t); -extern void install_cpuintr(cpuid_t cpu); -extern void install_dbgintr(cpuid_t cpu); -extern void install_tlbintr(cpuid_t cpu); -extern void hub_migrintr_init(cnodeid_t /*cnode*/); -extern int cause_intr_connect(int level, intr_func_t handler, uint intr_spl_mask); -extern int cause_intr_disconnect(int level); -extern void intr_reserve_hardwired(cnodeid_t); -extern void intr_clear_all(nasid_t); -extern void intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...)); - -/* error_dump.c */ -extern char *hub_rrb_err_type[]; -extern char *hub_wrb_err_type[]; - -void nmi_dump(void); -void install_cpu_nmi_handler(int slice); - -/* klclock.c */ -extern void hub_rtc_init(cnodeid_t); - -/* bte.c */ -void bte_lateinit(void); -void bte_wait_for_xfer_completion(void *); - -/* klgraph.c */ -void klhwg_add_all_nodes(devfs_handle_t); -void klhwg_add_all_modules(devfs_handle_t); - -/* klidbg.c */ -void install_klidbg_functions(void); - -/* klnuma.c */ -extern void replicate_kernel_text(int numnodes); -extern __psunsigned_t get_freemem_start(cnodeid_t cnode); -extern void setup_replication_mask(int maxnodes); - -/* init.c */ -extern cnodeid_t get_compact_nodeid(void); /* get compact node id */ -extern void init_platform_nodepda(nodepda_t *npda, cnodeid_t node); -extern void init_platform_pda(cpuid_t cpu); -extern void per_cpu_init(void); -#ifdef LATER -extern cpumask_t boot_cpumask; -#endif -extern int is_fine_dirmode(void); -extern void update_node_information(cnodeid_t); - -#ifdef LATER -/* clksupport.c */ -extern void early_counter_intr(eframe_t *); -#endif - -/* hubio.c */ -extern void hubio_init(void); -extern void hub_merge_clean(nasid_t nasid); -extern void hub_set_piomode(nasid_t nasid, int conveyor); - -/* huberror.c */ -extern void hub_error_init(cnodeid_t); -extern void dump_error_spool(cpuid_t cpu, void (*pf)(char *, ...)); -extern void hubni_error_handler(char *, int); -extern int check_ni_errors(void); - -/* Used for debugger to signal upper software a breakpoint has taken place */ - -extern void *debugger_update; -extern __psunsigned_t debugger_stopped; - -/* - * IP27 piomap, created by hub_pio_alloc. - * xtalk_info MUST BE FIRST, since this structure is cast to a - * xtalk_piomap_s by generic xtalk routines. - */ -struct hub_piomap_s { - struct xtalk_piomap_s hpio_xtalk_info;/* standard crosstalk pio info */ - devfs_handle_t hpio_hub; /* which hub's mapping registers are set up */ - short hpio_holdcnt; /* count of current users of bigwin mapping */ - char hpio_bigwin_num;/* if big window map, which one */ - int hpio_flags; /* defined below */ -}; -/* hub_piomap flags */ -#define HUB_PIOMAP_IS_VALID 0x1 -#define HUB_PIOMAP_IS_BIGWINDOW 0x2 -#define HUB_PIOMAP_IS_FIXED 0x4 - -#define hub_piomap_xt_piomap(hp) (&hp->hpio_xtalk_info) -#define hub_piomap_hub_v(hp) (hp->hpio_hub) -#define hub_piomap_winnum(hp) (hp->hpio_bigwin_num) - -#if TBD - /* Ensure that hpio_xtalk_info is first */ - #assert (&(((struct hub_piomap_s *)0)->hpio_xtalk_info) == 0) -#endif - - -/* - * IP27 dmamap, created by hub_pio_alloc. - * xtalk_info MUST BE FIRST, since this structure is cast to a - * xtalk_dmamap_s by generic xtalk routines. - */ -struct hub_dmamap_s { - struct xtalk_dmamap_s hdma_xtalk_info;/* standard crosstalk dma info */ - devfs_handle_t hdma_hub; /* which hub we go through */ - int hdma_flags; /* defined below */ -}; -/* hub_dmamap flags */ -#define HUB_DMAMAP_IS_VALID 0x1 -#define HUB_DMAMAP_USED 0x2 -#define HUB_DMAMAP_IS_FIXED 0x4 - -#if TBD - /* Ensure that hdma_xtalk_info is first */ - #assert (&(((struct hub_dmamap_s *)0)->hdma_xtalk_info) == 0) -#endif - -/* - * IP27 interrupt handle, created by hub_intr_alloc. - * xtalk_info MUST BE FIRST, since this structure is cast to a - * xtalk_intr_s by generic xtalk routines. - */ -struct hub_intr_s { - struct xtalk_intr_s i_xtalk_info; /* standard crosstalk intr info */ - ilvl_t i_swlevel; /* software level for blocking intr */ - cpuid_t i_cpuid; /* which cpu */ - int i_bit; /* which bit */ - int i_flags; -}; -/* flag values */ -#define HUB_INTR_IS_ALLOCED 0x1 /* for debug: allocated */ -#define HUB_INTR_IS_CONNECTED 0x4 /* for debug: connected to a software driver */ - -#if TBD - /* Ensure that i_xtalk_info is first */ - #assert (&(((struct hub_intr_s *)0)->i_xtalk_info) == 0) -#endif - - -/* IP27 hub-specific information stored under INFO_LBL_HUB_INFO */ -/* TBD: IP27-dependent stuff currently in nodepda.h should be here */ -typedef struct hubinfo_s { - nodepda_t *h_nodepda; /* pointer to node's private data area */ - cnodeid_t h_cnodeid; /* compact nodeid */ - nasid_t h_nasid; /* nasid */ - - /* structures for PIO management */ - xwidgetnum_t h_widgetid; /* my widget # (as viewed from xbow) */ - struct hub_piomap_s h_small_window_piomap[HUB_WIDGET_ID_MAX+1]; - sv_t h_bwwait; /* wait for big window to free */ - spinlock_t h_bwlock; /* guard big window piomap's */ - spinlock_t h_crblock; /* gaurd CRB error handling */ - int h_num_big_window_fixed; /* count number of FIXED maps */ - struct hub_piomap_s h_big_window_piomap[HUB_NUM_BIG_WINDOW]; - hub_intr_t hub_ii_errintr; -} *hubinfo_t; - -#define hubinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \ - (vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t *)infoptr)) - -#define hubinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \ - (vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t)infoptr) - -#define hubinfo_to_hubv(hinfo, hub_v) (hinfo->h_nodepda->node_vertex) - -/* - * Hub info PIO map access functions. - */ -#define hubinfo_bwin_piomap_get(hinfo, win) \ - (&hinfo->h_big_window_piomap[win]) -#define hubinfo_swin_piomap_get(hinfo, win) \ - (&hinfo->h_small_window_piomap[win]) - -/* IP27 cpu-specific information stored under INFO_LBL_CPU_INFO */ -/* TBD: IP27-dependent stuff currently in pda.h should be here */ -typedef struct cpuinfo_s { -#ifdef LATER - pda_t *ci_cpupda; /* pointer to CPU's private data area */ -#endif - cpuid_t ci_cpuid; /* CPU ID */ -} *cpuinfo_t; - -#define cpuinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \ - (vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t *)infoptr)) - -#define cpuinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \ - (vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr) - -/* Special initialization function for xswitch vertices created during startup. */ -extern void xswitch_vertex_init(devfs_handle_t xswitch); - -extern xtalk_provider_t hub_provider; - -/* du.c */ -int ducons_write(char *buf, int len); - -/* memerror.c */ - -extern void install_eccintr(cpuid_t cpu); -extern void memerror_get_stats(cnodeid_t cnode, - int *bank_stats, int *bank_stats_max); -extern void probe_md_errors(nasid_t); -/* sysctlr.c */ -extern void sysctlr_init(void); -extern void sysctlr_power_off(int sdonly); -extern void sysctlr_keepalive(void); - -#define valid_cpuid(_x) (((_x) >= 0) && ((_x) < maxcpus)) - -/* Useful definitions to get the memory dimm given a physical - * address. - */ -#define paddr_dimm(_pa) ((_pa & MD_BANK_MASK) >> MD_BANK_SHFT) -#define paddr_cnode(_pa) (NASID_TO_COMPACT_NODEID(NASID_GET(_pa))) -extern void membank_pathname_get(paddr_t,char *); - -/* To redirect the output into the error buffer */ -#define errbuf_print(_s) printf("#%s",_s) - -extern void crbx(nasid_t nasid, void (*pf)(char *, ...)); -void bootstrap(void); - -/* sndrv.c */ -extern int sndrv_attach(devfs_handle_t vertex); - -#endif /* _ASM_IA64_SN_SN1_SN_PRIVATE_H */ diff --git a/include/asm-ia64/sn/sn1/synergy.h b/include/asm-ia64/sn/sn1/synergy.h deleted file mode 100644 index f99dee05192ab..0000000000000 --- a/include/asm-ia64/sn/sn1/synergy.h +++ /dev/null @@ -1,184 +0,0 @@ -#ifndef _ASM_IA64_SN_SN1_SYNERGY_H -#define _ASM_IA64_SN_SN1_SYNERGY_H - -#include <asm/io.h> -#include <asm/sn/hcl.h> -#include <asm/sn/addrs.h> -#include <asm/sn/intr_public.h> - - -/* - * Definitions for the synergy asic driver - * - * These are for SGI platforms only. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 2000-2002 Silicon Graphics, Inc. All rights reserved. - */ - - -#define SYNERGY_L4_BYTES (64UL*1024*1024) -#define SYNERGY_L4_WAYS 8 -#define SYNERGY_L4_BYTES_PER_WAY (SYNERGY_L4_BYTES/SYNERGY_L4_WAYS) -#define SYNERGY_BLOCK_SIZE 512UL - - -#define SSPEC_BASE (0xe0000000000UL) -#define LB_REG_BASE (SSPEC_BASE + 0x0) - -#define VEC_MASK3A_ADDR (0x2a0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) -#define VEC_MASK3B_ADDR (0x2a8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) -#define VEC_MASK3A (0x2a0) -#define VEC_MASK3B (0x2a8) - -#define VEC_MASK2A_ADDR (0x2b0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) -#define VEC_MASK2B_ADDR (0x2b8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) -#define VEC_MASK2A (0x2b0) -#define VEC_MASK2B (0x2b8) - -#define VEC_MASK1A_ADDR (0x2c0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) -#define VEC_MASK1B_ADDR (0x2c8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) -#define VEC_MASK1A (0x2c0) -#define VEC_MASK1B (0x2c8) - -#define VEC_MASK0A_ADDR (0x2d0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) -#define VEC_MASK0B_ADDR (0x2d8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) -#define VEC_MASK0A (0x2d0) -#define VEC_MASK0B (0x2d8) - -#define GBL_PERF_A_ADDR (0x330 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) -#define GBL_PERF_B_ADDR (0x338 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) - -#define WRITE_LOCAL_SYNERGY_REG(addr, value) __synergy_out(addr, value) - -#define HSPEC_SYNERGY0_0 0x04000000 /* Synergy0 Registers */ -#define HSPEC_SYNERGY1_0 0x05000000 /* Synergy1 Registers */ -#define HS_SYNERGY_STRIDE (HSPEC_SYNERGY1_0 - HSPEC_SYNERGY0_0) -#define REMOTE_HSPEC(_n, _x) (HUBREG_CAST (RREG_BASE(_n) + (_x))) - -#define RREG_BASE(_n) (NODE_LREG_BASE(_n)) -#define NODE_LREG_BASE(_n) (NODE_HSPEC_BASE(_n) + 0x30000000) -#define NODE_HSPEC_BASE(_n) (HSPEC_BASE + NODE_OFFSET(_n)) -#ifndef HSPEC_BASE -#define HSPEC_BASE (SYN_UNCACHED_SPACE | HSPEC_BASE_SYN) -#endif -#define SYN_UNCACHED_SPACE 0xc000000000000000 -#define HSPEC_BASE_SYN 0x00000b0000000000 -#define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS) -#define NODE_SIZE_BITS 33 - -#define SYN_TAG_DISABLE_WAY (SSPEC_BASE+0xae0) - - -#define RSYN_REG_OFFSET(fsb, reg) (((fsb) ? HSPEC_SYNERGY1_0 : HSPEC_SYNERGY0_0) | (reg)) - -#define REMOTE_SYNERGY_LOAD(nasid, fsb, reg) __remote_synergy_in(nasid, fsb, reg) -#define REMOTE_SYNERGY_STORE(nasid, fsb, reg, val) __remote_synergy_out(nasid, fsb, reg, val) - -static inline uint64_t -__remote_synergy_in(int nasid, int fsb, uint64_t reg) { - volatile uint64_t *addr; - - addr = (uint64_t *)(RREG_BASE(nasid) + RSYN_REG_OFFSET(fsb, reg)); - return (*addr); -} - -static inline void -__remote_synergy_out(int nasid, int fsb, uint64_t reg, uint64_t value) { - volatile uint64_t *addr; - - addr = (uint64_t *)(RREG_BASE(nasid) + RSYN_REG_OFFSET(fsb, (reg<<2))); - *(addr+0) = value >> 48; - *(addr+1) = value >> 32; - *(addr+2) = value >> 16; - *(addr+3) = value; - __ia64_mf_a(); -} - -/* XX this doesn't make a lot of sense. Which fsb? */ -static inline void -__synergy_out(unsigned long addr, unsigned long value) -{ - volatile unsigned long *adr = (unsigned long *) - (addr | __IA64_UNCACHED_OFFSET); - - *adr = value; - __ia64_mf_a(); -} - -#define READ_LOCAL_SYNERGY_REG(addr) __synergy_in(addr) - -/* XX this doesn't make a lot of sense. Which fsb? */ -static inline unsigned long -__synergy_in(unsigned long addr) -{ - unsigned long ret, *adr = (unsigned long *) - (addr | __IA64_UNCACHED_OFFSET); - - ret = *adr; - __ia64_mf_a(); - return ret; -} - -struct sn1_intr_action { - void (*handler)(int, void *, struct pt_regs *); - void *intr_arg; - unsigned long flags; - struct sn1_intr_action * next; -}; - -typedef struct synergy_da_s { - hub_intmasks_t s_intmasks; -}synergy_da_t; - -struct sn1_cnode_action_list { - spinlock_t action_list_lock; - struct sn1_intr_action *action_list; -}; - -/* - * ioctl cmds for node/hub/synergy/[01]/mon for synergy - * perf monitoring are defined in sndrv.h - */ - -/* multiplex the counters every 10 timer interrupts */ -#define SYNERGY_PERF_FREQ_DEFAULT 10 - -/* macros for synergy "mon" device ioctl handler */ -#define SYNERGY_PERF_INFO(_s, _f) (arbitrary_info_t)(((_s) << 16)|(_f)) -#define SYNERGY_PERF_INFO_CNODE(_x) (cnodeid_t)(((uint64_t)_x) >> 16) -#define SYNERGY_PERF_INFO_FSB(_x) (((uint64_t)_x) & 1) - -/* synergy perf control registers */ -#define PERF_CNTL0_A 0xab0UL /* control A on FSB0 */ -#define PERF_CNTL0_B 0xab8UL /* control B on FSB0 */ -#define PERF_CNTL1_A 0xac0UL /* control A on FSB1 */ -#define PERF_CNTL1_B 0xac8UL /* control B on FSB1 */ - -/* synergy perf counters */ -#define PERF_CNTR0_A 0xad0UL /* counter A on FSB0 */ -#define PERF_CNTR0_B 0xad8UL /* counter B on FSB0 */ -#define PERF_CNTR1_A 0xaf0UL /* counter A on FSB1 */ -#define PERF_CNTR1_B 0xaf8UL /* counter B on FSB1 */ - -/* Synergy perf data. Each nodepda keeps a list of these */ -struct synergy_perf_s { - uint64_t intervals; /* count of active intervals for this event */ - uint64_t total_intervals;/* snapshot of total intervals */ - uint64_t modesel; /* mode and sel bits, both A and B registers */ - struct synergy_perf_s *next; /* next in circular linked list */ - uint64_t counts[2]; /* [0] is synergy-A counter, [1] synergy-B counter */ -}; - -typedef struct synergy_perf_s synergy_perf_t; - -typedef struct synergy_info_s synergy_info_t; - -extern void synergy_perf_init(void); -extern void synergy_perf_update(int); -extern struct file_operations synergy_mon_fops; - -#endif /* _ASM_IA64_SN_SN1_SYNERGY_H */ diff --git a/include/asm-ia64/sn/sn2/addrs.h b/include/asm-ia64/sn/sn2/addrs.h index ba12fbd2eed95..c415366196bff 100644 --- a/include/asm-ia64/sn/sn2/addrs.h +++ b/include/asm-ia64/sn/sn2/addrs.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SN2_ADDRS_H @@ -57,7 +57,7 @@ typedef union ia64_sn2_pa { #define LOCAL_MEM_SPACE 0xc000010000000000 /* Local Memory space */ #define GLOBAL_MMR_SPACE 0xc000000800000000 /* Global MMR space */ #define GLOBAL_PHYS_MMR_SPACE 0x0000000800000000 /* Global Physical MMR space */ -#define GET_SPACE 0xc000001000000000 /* GET space */ +#define GET_SPACE 0xe000001000000000 /* GET space */ #define AMO_SPACE 0xc000002000000000 /* AMO space */ #define CACHEABLE_MEM_SPACE 0xe000003000000000 /* Cacheable memory space */ #define UNCACHED 0xc000000000000000 /* UnCacheable memory space */ diff --git a/include/asm-ia64/sn/sn2/arch.h b/include/asm-ia64/sn/sn2/arch.h index d630ed226f11e..f31578259dd6a 100644 --- a/include/asm-ia64/sn/sn2/arch.h +++ b/include/asm-ia64/sn/sn2/arch.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SN2_ARCH_H #define _ASM_IA64_SN_SN2_ARCH_H @@ -46,6 +46,7 @@ #define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8) +#define CNASID_MASK_BYTES (NASID_MASK_BYTES / 2) /* diff --git a/include/asm-ia64/sn/sn2/intr.h b/include/asm-ia64/sn/sn2/intr.h index 09cb8319474c6..d021292d9bf15 100644 --- a/include/asm-ia64/sn/sn2/intr.h +++ b/include/asm-ia64/sn/sn2/intr.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SN2_INTR_H #define _ASM_IA64_SN_SN2_INTR_H @@ -14,13 +14,17 @@ // These two IRQ's are used by partitioning. #define SGI_XPC_ACTIVATE (0x30) +#define SGI_II_ERROR (0x31) +#define SGI_XBOW_ERROR (0x32) +#define SGI_PCIBR_ERROR (0x33) #define SGI_XPC_NOTIFY (0xe7) -#define IA64_SN2_FIRST_DEVICE_VECTOR (0x31) +#define IA64_SN2_FIRST_DEVICE_VECTOR (0x34) #define IA64_SN2_LAST_DEVICE_VECTOR (0xe6) #define SN2_IRQ_RESERVED (0x1) #define SN2_IRQ_CONNECTED (0x2) +#define SN2_IRQ_SHARED (0x4) #define SN2_IRQ_PER_HUB (2048) diff --git a/include/asm-ia64/sn/sn2/io.h b/include/asm-ia64/sn/sn2/io.h index b0c928f019173..eff4f8641b150 100644 --- a/include/asm-ia64/sn/sn2/io.h +++ b/include/asm-ia64/sn/sn2/io.h @@ -32,8 +32,8 @@ __sn_inb (unsigned long port) unsigned char ret; ret = *addr; - sn_dma_flush((unsigned long)addr); __sn_mf_a(); + sn_dma_flush((unsigned long)addr); return ret; } @@ -44,8 +44,8 @@ __sn_inw (unsigned long port) unsigned short ret; ret = *addr; - sn_dma_flush((unsigned long)addr); __sn_mf_a(); + sn_dma_flush((unsigned long)addr); return ret; } @@ -56,8 +56,8 @@ __sn_inl (unsigned long port) unsigned int ret; ret = *addr; - sn_dma_flush((unsigned long)addr); __sn_mf_a(); + sn_dma_flush((unsigned long)addr); return ret; } @@ -103,6 +103,7 @@ __sn_readb (void *addr) unsigned char val; val = *(volatile unsigned char *)addr; + __sn_mf_a(); sn_dma_flush((unsigned long)addr); return val; } @@ -113,6 +114,7 @@ __sn_readw (void *addr) unsigned short val; val = *(volatile unsigned short *)addr; + __sn_mf_a(); sn_dma_flush((unsigned long)addr); return val; } @@ -123,6 +125,7 @@ __sn_readl (void *addr) unsigned int val; val = *(volatile unsigned int *) addr; + __sn_mf_a(); sn_dma_flush((unsigned long)addr); return val; } @@ -133,6 +136,7 @@ __sn_readq (void *addr) unsigned long val; val = *(volatile unsigned long *) addr; + __sn_mf_a(); sn_dma_flush((unsigned long)addr); return val; } diff --git a/include/asm-ia64/sn/sn2/mmzone_sn2.h b/include/asm-ia64/sn/sn2/mmzone_sn2.h deleted file mode 100644 index e495529d78737..0000000000000 --- a/include/asm-ia64/sn/sn2/mmzone_sn2.h +++ /dev/null @@ -1,165 +0,0 @@ -#ifndef _ASM_IA64_SN_MMZONE_SN2_H -#define _ASM_IA64_SN_MMZONE_SN2_H - -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 2000-2002 Silicon Graphics, Inc. All rights reserved. - */ - -#include <linux/config.h> - - -/* - * SGI SN2 Arch defined values - * - * An SN2 physical address is broken down as follows: - * - * +-----------------------------------------+ - * | | | | node offset | - * | unused | node | AS |-------------------| - * | | | | cn | clump offset | - * +-----------------------------------------+ - * 6 4 4 3 3 3 3 3 3 0 - * 3 9 8 8 7 6 5 4 3 0 - * - * bits 63-49 Unused - must be zero - * bits 48-38 Node number. Note that some configurations do NOT - * have a node zero. - * bits 37-36 Address space ID. Cached memory has a value of 3 (!!!). - * Chipset & IO addresses have other values. - * (Yikes!! The hardware folks hate us...) - * bits 35-0 Node offset. - * - * The node offset can be further broken down as: - * bits 35-34 Clump (bank) number. - * bits 33-0 Clump (bank) offset. - * - * A node consists of up to 4 clumps (banks) of memory. A clump may be empty, or may be - * populated with a single contiguous block of memory starting at clump - * offset 0. The size of the block is (2**n) * 64MB, where 0<n<9. - * - * Important notes: - * - IO space addresses are embedded with the range of valid memory addresses. - * - All cached memory addresses have bits 36 & 37 set to 1's. - * - There is no physical address 0. - * - * NOTE: This file exports symbols prefixed with "PLAT_". Symbols prefixed with - * "SN_" are intended for internal use only and should not be used in - * any platform independent code. - * - * This file is also responsible for exporting the following definitions: - * cnodeid_t Define a compact node id. - */ - -typedef signed short cnodeid_t; - -#define SN2_BANKS_PER_NODE 4 -#define SN2_NODE_SIZE (64UL*1024*1024*1024) /* 64GB per node */ -#define SN2_BANK_SIZE (SN2_NODE_SIZE/SN2_BANKS_PER_NODE) -#define SN2_NODE_SHIFT 38 -#define SN2_NODE_MASK 0x7ffUL -#define SN2_NODE_OFFSET_MASK (SN2_NODE_SIZE-1) -#define SN2_NODE_NUMBER(addr) (((unsigned long)(addr) >> SN2_NODE_SHIFT) & SN2_NODE_MASK) -#define SN2_NODE_CLUMP_NUMBER(kaddr) (((unsigned long)(kaddr) >>34) & 3) -#define SN2_NODE_OFFSET(addr) (((unsigned long)(addr)) & SN2_NODE_OFFSET_MASK) -#define SN2_KADDR(nasid, offset) (((unsigned long)(nasid)<<SN2_NODE_SHIFT) | (offset) | SN2_PAGE_OFFSET) -#define SN2_PAGE_OFFSET 0xe000003000000000UL /* Cacheable memory space */ - - -#define PLAT_MAX_NODE_NUMBER 2048 /* Maximum node number + 1 */ -#define PLAT_MAX_COMPACT_NODES 128 /* Maximum number of nodes in SSI system */ - -#define PLAT_MAX_PHYS_MEMORY (1UL << 49) - - - -/* - * On the SN platforms, a clump is the same as a memory bank. - */ -#define PLAT_CLUMPS_PER_NODE SN2_BANKS_PER_NODE -#define PLAT_CLUMP_OFFSET(addr) ((unsigned long)(addr) & 0x3ffffffffUL) -#define PLAT_CLUMPSIZE (SN2_NODE_SIZE/PLAT_CLUMPS_PER_NODE) -#define PLAT_MAXCLUMPS (PLAT_CLUMPS_PER_NODE * PLAT_MAX_COMPACT_NODES) - - - -/* - * PLAT_VALID_MEM_KADDR returns a boolean to indicate if a kaddr is potentially a - * valid cacheable identity mapped RAM memory address. - * Note that the RAM may or may not actually be present!! - */ -#define SN2_VALID_KERN_ADDR_MASK 0xffff003000000000UL -#define SN2_VALID_KERN_ADDR_VALUE 0xe000003000000000UL -#define PLAT_VALID_MEM_KADDR(kaddr) (((unsigned long)(kaddr) & SN2_VALID_KERN_ADDR_MASK) == SN2_VALID_KERN_ADDR_VALUE) - - - -/* - * Memory is conceptually divided into chunks. A chunk is either - * completely present, or else the kernel assumes it is completely - * absent. Each node consists of a number of possibly contiguous chunks. - */ -#define SN2_CHUNKSHIFT 25 /* 32 MB */ -#define PLAT_CHUNKSIZE (1UL << SN2_CHUNKSHIFT) -#define PLAT_CHUNKNUM(addr) ({unsigned long _p=(unsigned long)(addr); \ - (((_p&SN2_NODE_MASK)>>2) | \ - (_p&SN2_NODE_OFFSET_MASK)) >>SN2_CHUNKSHIFT;}) - -/* - * Given a kaddr, find the nid (compact nodeid) - */ -#ifdef CONFIG_IA64_SGI_SN_DEBUG -#define DISCONBUG(kaddr) panic("DISCONTIG BUG: line %d, %s. kaddr 0x%lx", \ - __LINE__, __FILE__, (long)(kaddr)) - -#define KVADDR_TO_NID(kaddr) ({long _ktn=(long)(kaddr); \ - kern_addr_valid(_ktn) ? \ - local_node_data->physical_node_map[SN2_NODE_NUMBER(_ktn)] : \ - (DISCONBUG(_ktn), 0UL);}) -#else -#define KVADDR_TO_NID(kaddr) (local_node_data->physical_node_map[SN2_NODE_NUMBER(kaddr)]) -#endif - - - -/* - * Given a kaddr, find the index into the clump_mem_map_base array of the page struct entry - * for the first page of the clump. - */ -#define PLAT_CLUMP_MEM_MAP_INDEX(kaddr) ({long _kmmi=(long)(kaddr); \ - KVADDR_TO_NID(_kmmi) * PLAT_CLUMPS_PER_NODE + \ - SN2_NODE_CLUMP_NUMBER(_kmmi);}) - - - -/* - * Calculate a "goal" value to be passed to __alloc_bootmem_node for allocating structures on - * nodes so that they don't alias to the same line in the cache as the previous allocated structure. - * This macro takes an address of the end of previous allocation, rounds it to a page boundary & - * changes the node number. - */ -#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) __pa(SN2_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnode]), \ - (SN2_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT)) - - - - -/* - * Convert a proximity domain number (from the ACPI tables) into a physical node number. - * Note: on SN2, the promity domain number is the same as bits [8:1] of the NASID. The following - * algorithm relies on: - * - bit 0 of the NASID for cpu nodes is always 0 - * - bits [10:9] of all NASIDs in a partition are always the same - * - hard_smp_processor_id return the SAPIC of the current cpu & - * bits 0..11 contain the NASID. - * - * All of this complexity is because MS architectually limited proximity domain numbers to - * 8 bits. - */ - -#define PLAT_PXM_TO_PHYS_NODE_NUMBER(pxm) (((pxm)<<1) | (hard_smp_processor_id() & 0x300)) - -#endif /* _ASM_IA64_SN_MMZONE_SN2_H */ diff --git a/include/asm-ia64/sn/sn2/shub.h b/include/asm-ia64/sn/sn2/shub.h index 2c6719107c839..4547ff440550f 100644 --- a/include/asm-ia64/sn/sn2/shub.h +++ b/include/asm-ia64/sn/sn2/shub.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. */ diff --git a/include/asm-ia64/sn/sn2/shub_md.h b/include/asm-ia64/sn/sn2/shub_md.h index 874b1c30a9608..2c4a7dc3b4f2b 100644 --- a/include/asm-ia64/sn/sn2/shub_md.h +++ b/include/asm-ia64/sn/sn2/shub_md.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001, 2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001, 2002-2003 Silicon Graphics, Inc. All rights reserved. */ diff --git a/include/asm-ia64/sn/sn2/shub_mmr.h b/include/asm-ia64/sn/sn2/shub_mmr.h index 61aa480414d80..05ea7efaf453e 100644 --- a/include/asm-ia64/sn/sn2/shub_mmr.h +++ b/include/asm-ia64/sn/sn2/shub_mmr.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. */ @@ -25746,14 +25746,14 @@ /* Real-time Clock */ /* ==================================================================== */ -#define SH_RTC 0x00000001101c0000 -#define SH_RTC_MASK 0x007fffffffffffff +#define SH_RTC 0x00000001101c0000UL +#define SH_RTC_MASK 0x007fffffffffffffUL #define SH_RTC_INIT 0x0000000000000000 /* SH_RTC_REAL_TIME_CLOCK */ /* Description: Real-time Clock */ #define SH_RTC_REAL_TIME_CLOCK_SHFT 0 -#define SH_RTC_REAL_TIME_CLOCK_MASK 0x007fffffffffffff +#define SH_RTC_REAL_TIME_CLOCK_MASK 0x007fffffffffffffUL /* ==================================================================== */ /* Register "SH_SCRATCH0" */ diff --git a/include/asm-ia64/sn/sn2/shub_mmr_t.h b/include/asm-ia64/sn/sn2/shub_mmr_t.h index d2cef5e24a81a..f0397c4007502 100644 --- a/include/asm-ia64/sn/sn2/shub_mmr_t.h +++ b/include/asm-ia64/sn/sn2/shub_mmr_t.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. */ diff --git a/include/asm-ia64/sn/sn2/shubio.h b/include/asm-ia64/sn/sn2/shubio.h index 51c33b67c9c7f..19e7cfdb44b3c 100644 --- a/include/asm-ia64/sn/sn2/shubio.h +++ b/include/asm-ia64/sn/sn2/shubio.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SN2_SHUBIO_H @@ -3035,31 +3035,31 @@ typedef union ii_ippr_u { /* Scratch registers (all bits available) */ #define IIO_SCRATCH_REG0 IIO_ISCR0 #define IIO_SCRATCH_REG1 IIO_ISCR1 -#define IIO_SCRATCH_MASK 0xffffffffffffffff - -#define IIO_SCRATCH_BIT0_0 0x0000000000000001 -#define IIO_SCRATCH_BIT0_1 0x0000000000000002 -#define IIO_SCRATCH_BIT0_2 0x0000000000000004 -#define IIO_SCRATCH_BIT0_3 0x0000000000000008 -#define IIO_SCRATCH_BIT0_4 0x0000000000000010 -#define IIO_SCRATCH_BIT0_5 0x0000000000000020 -#define IIO_SCRATCH_BIT0_6 0x0000000000000040 -#define IIO_SCRATCH_BIT0_7 0x0000000000000080 -#define IIO_SCRATCH_BIT0_8 0x0000000000000100 -#define IIO_SCRATCH_BIT0_9 0x0000000000000200 -#define IIO_SCRATCH_BIT0_A 0x0000000000000400 - -#define IIO_SCRATCH_BIT1_0 0x0000000000000001 -#define IIO_SCRATCH_BIT1_1 0x0000000000000002 +#define IIO_SCRATCH_MASK 0xffffffffffffffffUL + +#define IIO_SCRATCH_BIT0_0 0x0000000000000001UL +#define IIO_SCRATCH_BIT0_1 0x0000000000000002UL +#define IIO_SCRATCH_BIT0_2 0x0000000000000004UL +#define IIO_SCRATCH_BIT0_3 0x0000000000000008UL +#define IIO_SCRATCH_BIT0_4 0x0000000000000010UL +#define IIO_SCRATCH_BIT0_5 0x0000000000000020UL +#define IIO_SCRATCH_BIT0_6 0x0000000000000040UL +#define IIO_SCRATCH_BIT0_7 0x0000000000000080UL +#define IIO_SCRATCH_BIT0_8 0x0000000000000100UL +#define IIO_SCRATCH_BIT0_9 0x0000000000000200UL +#define IIO_SCRATCH_BIT0_A 0x0000000000000400UL + +#define IIO_SCRATCH_BIT1_0 0x0000000000000001UL +#define IIO_SCRATCH_BIT1_1 0x0000000000000002UL /* IO Translation Table Entries */ #define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */ /* Hw manuals number them 1..7! */ /* * IIO_IMEM Register fields. */ -#define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */ -#define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */ -#define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */ +#define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */ +#define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */ +#define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */ /* * As a permanent workaround for a bug in the PI side of the shub, we've @@ -3191,23 +3191,23 @@ typedef union ii_ippr_u { /* * IO BTE Length/Status (IIO_IBLS) register bit field definitions */ -#define IBLS_BUSY (0x1 << 20) +#define IBLS_BUSY (0x1UL << 20) #define IBLS_ERROR_SHFT 16 -#define IBLS_ERROR (0x1 << IBLS_ERROR_SHFT) +#define IBLS_ERROR (0x1UL << IBLS_ERROR_SHFT) #define IBLS_LENGTH_MASK 0xffff /* * IO BTE Control/Terminate register (IBCT) register bit field definitions */ -#define IBCT_POISON (0x1 << 8) -#define IBCT_NOTIFY (0x1 << 4) -#define IBCT_ZFIL_MODE (0x1 << 0) +#define IBCT_POISON (0x1UL << 8) +#define IBCT_NOTIFY (0x1UL << 4) +#define IBCT_ZFIL_MODE (0x1UL << 0) /* * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2) */ -#define IIEPH1_VALID (1 << 44) -#define IIEPH1_OVERRUN (1 << 40) +#define IIEPH1_VALID (1UL << 44) +#define IIEPH1_OVERRUN (1UL << 40) #define IIEPH1_ERR_TYPE_SHFT 32 #define IIEPH1_ERR_TYPE_MASK 0xf #define IIEPH1_SOURCE_SHFT 20 @@ -3217,7 +3217,7 @@ typedef union ii_ippr_u { #define IIEPH1_CMD_SHFT 0 #define IIEPH1_CMD_MASK 7 -#define IIEPH2_TAIL (1 << 40) +#define IIEPH2_TAIL (1UL << 40) #define IIEPH2_ADDRESS_SHFT 0 #define IIEPH2_ADDRESS_MASK 38 @@ -3229,21 +3229,21 @@ typedef union ii_ippr_u { /* * IO Error Clear register bit field definitions */ -#define IECLR_PI1_FWD_INT (1 << 31) /* clear PI1_FORWARD_INT in iidsr */ -#define IECLR_PI0_FWD_INT (1 << 30) /* clear PI0_FORWARD_INT in iidsr */ -#define IECLR_SPUR_RD_HDR (1 << 29) /* clear valid bit in ixss reg */ -#define IECLR_BTE1 (1 << 18) /* clear bte error 1 */ -#define IECLR_BTE0 (1 << 17) /* clear bte error 0 */ -#define IECLR_CRAZY (1 << 16) /* clear crazy bit in wstat reg */ -#define IECLR_PRB_F (1 << 15) /* clear err bit in PRB_F reg */ -#define IECLR_PRB_E (1 << 14) /* clear err bit in PRB_E reg */ -#define IECLR_PRB_D (1 << 13) /* clear err bit in PRB_D reg */ -#define IECLR_PRB_C (1 << 12) /* clear err bit in PRB_C reg */ -#define IECLR_PRB_B (1 << 11) /* clear err bit in PRB_B reg */ -#define IECLR_PRB_A (1 << 10) /* clear err bit in PRB_A reg */ -#define IECLR_PRB_9 (1 << 9) /* clear err bit in PRB_9 reg */ -#define IECLR_PRB_8 (1 << 8) /* clear err bit in PRB_8 reg */ -#define IECLR_PRB_0 (1 << 0) /* clear err bit in PRB_0 reg */ +#define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */ +#define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */ +#define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */ +#define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */ +#define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */ +#define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */ +#define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */ +#define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */ +#define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */ +#define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */ +#define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */ +#define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */ +#define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */ +#define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */ +#define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */ /* * IIO CRB control register Fields: IIO_ICCR @@ -3495,7 +3495,7 @@ typedef union iprte_a { typedef struct hub_piomap_s *hub_piomap_t; extern hub_piomap_t -hub_piomap_alloc(devfs_handle_t dev, /* set up mapping for this device */ +hub_piomap_alloc(vertex_hdl_t dev, /* set up mapping for this device */ device_desc_t dev_desc, /* device descriptor */ iopaddr_t xtalk_addr, /* map for this xtalk_addr range */ size_t byte_count, @@ -3513,7 +3513,7 @@ extern void hub_piomap_done(hub_piomap_t hub_piomap); extern caddr_t -hub_piotrans_addr( devfs_handle_t dev, /* translate to this device */ +hub_piotrans_addr( vertex_hdl_t dev, /* translate to this device */ device_desc_t dev_desc, /* device descriptor */ iopaddr_t xtalk_addr, /* Crosstalk address */ size_t byte_count, /* map this many bytes */ @@ -3523,7 +3523,7 @@ hub_piotrans_addr( devfs_handle_t dev, /* translate to this device */ typedef struct hub_dmamap_s *hub_dmamap_t; extern hub_dmamap_t -hub_dmamap_alloc( devfs_handle_t dev, /* set up mappings for dev */ +hub_dmamap_alloc( vertex_hdl_t dev, /* set up mappings for dev */ device_desc_t dev_desc, /* device descriptor */ size_t byte_count_max, /* max size of a mapping */ unsigned flags); /* defined in dma.h */ @@ -3545,14 +3545,14 @@ extern void hub_dmamap_done( hub_dmamap_t dmamap); /* done w/ mapping resources */ extern iopaddr_t -hub_dmatrans_addr( devfs_handle_t dev, /* translate for this device */ +hub_dmatrans_addr( vertex_hdl_t dev, /* translate for this device */ device_desc_t dev_desc, /* device descriptor */ paddr_t paddr, /* system physical address */ size_t byte_count, /* length */ unsigned flags); /* defined in dma.h */ extern alenlist_t -hub_dmatrans_list( devfs_handle_t dev, /* translate for this device */ +hub_dmatrans_list( vertex_hdl_t dev, /* translate for this device */ device_desc_t dev_desc, /* device descriptor */ alenlist_t palenlist, /* system addr/length list */ unsigned flags); /* defined in dma.h */ @@ -3561,12 +3561,12 @@ extern void hub_dmamap_drain( hub_dmamap_t map); extern void -hub_dmaaddr_drain( devfs_handle_t vhdl, +hub_dmaaddr_drain( vertex_hdl_t vhdl, paddr_t addr, size_t bytes); extern void -hub_dmalist_drain( devfs_handle_t vhdl, +hub_dmalist_drain( vertex_hdl_t vhdl, alenlist_t list); @@ -3574,14 +3574,14 @@ hub_dmalist_drain( devfs_handle_t vhdl, typedef struct hub_intr_s *hub_intr_t; extern hub_intr_t -hub_intr_alloc( devfs_handle_t dev, /* which device */ +hub_intr_alloc( vertex_hdl_t dev, /* which device */ device_desc_t dev_desc, /* device descriptor */ - devfs_handle_t owner_dev); /* owner of this interrupt */ + vertex_hdl_t owner_dev); /* owner of this interrupt */ extern hub_intr_t -hub_intr_alloc_nothd(devfs_handle_t dev, /* which device */ +hub_intr_alloc_nothd(vertex_hdl_t dev, /* which device */ device_desc_t dev_desc, /* device descriptor */ - devfs_handle_t owner_dev); /* owner of this interrupt */ + vertex_hdl_t owner_dev); /* owner of this interrupt */ extern void hub_intr_free(hub_intr_t intr_hdl); @@ -3596,16 +3596,14 @@ hub_intr_connect( hub_intr_t intr_hdl, /* xtalk intr resource hndl */ extern void hub_intr_disconnect(hub_intr_t intr_hdl); -extern devfs_handle_t -hub_intr_cpu_get(hub_intr_t intr_hdl); /* CONFIGURATION MANAGEMENT */ extern void -hub_provider_startup(devfs_handle_t hub); +hub_provider_startup(vertex_hdl_t hub); extern void -hub_provider_shutdown(devfs_handle_t hub); +hub_provider_shutdown(vertex_hdl_t hub); #define HUB_PIO_CONVEYOR 0x1 /* PIO in conveyor belt mode */ #define HUB_PIO_FIRE_N_FORGET 0x2 /* PIO in fire-and-forget mode */ @@ -3619,38 +3617,26 @@ hub_provider_shutdown(devfs_handle_t hub); typedef int hub_widget_flags_t; -/* Set the PIO mode for a widget. These two functions perform the - * same operation, but hub_device_flags_set() takes a hardware graph - * vertex while hub_widget_flags_set() takes a nasid and widget - * number. In most cases, hub_device_flags_set() should be used. - */ +/* Set the PIO mode for a widget. */ extern int hub_widget_flags_set(nasid_t nasid, xwidgetnum_t widget_num, hub_widget_flags_t flags); -/* Depending on the flags set take the appropriate actions */ -extern int hub_device_flags_set(devfs_handle_t widget_dev, - hub_widget_flags_t flags); - - /* Error Handling. */ -extern int hub_ioerror_handler(devfs_handle_t, int, int, struct io_error_s *); +extern int hub_ioerror_handler(vertex_hdl_t, int, int, struct io_error_s *); extern int kl_ioerror_handler(cnodeid_t, cnodeid_t, cpuid_t, int, paddr_t, caddr_t, ioerror_mode_t); -extern void hub_widget_reset(devfs_handle_t, xwidgetnum_t); -extern int hub_error_devenable(devfs_handle_t, int, int); -extern void hub_widgetdev_enable(devfs_handle_t, int); -extern void hub_widgetdev_shutdown(devfs_handle_t, int); -extern int hub_dma_enabled(devfs_handle_t); +extern int hub_error_devenable(vertex_hdl_t, int, int); +extern int hub_dma_enabled(vertex_hdl_t); /* hubdev */ extern void hubdev_init(void); -extern void hubdev_register(int (*attach_method)(devfs_handle_t)); -extern int hubdev_unregister(int (*attach_method)(devfs_handle_t)); -extern int hubdev_docallouts(devfs_handle_t hub); +extern void hubdev_register(int (*attach_method)(vertex_hdl_t)); +extern int hubdev_unregister(int (*attach_method)(vertex_hdl_t)); +extern int hubdev_docallouts(vertex_hdl_t hub); -extern caddr_t hubdev_prombase_get(devfs_handle_t hub); -extern cnodeid_t hubdev_cnodeid_get(devfs_handle_t hub); +extern caddr_t hubdev_prombase_get(vertex_hdl_t hub); +extern cnodeid_t hubdev_cnodeid_get(vertex_hdl_t hub); #endif /* __ASSEMBLY__ */ #endif /* _KERNEL */ diff --git a/include/asm-ia64/sn/sn2/slotnum.h b/include/asm-ia64/sn/sn2/slotnum.h index 3ebb4ba93a440..03146d5e6cbd5 100644 --- a/include/asm-ia64/sn/sn2/slotnum.h +++ b/include/asm-ia64/sn/sn2/slotnum.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1992 - 1997,2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 1992-1997,2001-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SN2_SLOTNUM_H diff --git a/include/asm-ia64/sn/sn2/sn_private.h b/include/asm-ia64/sn/sn2/sn_private.h index 51baf4015dc86..5b553d81c79b8 100644 --- a/include/asm-ia64/sn/sn2/sn_private.h +++ b/include/asm-ia64/sn/sn2/sn_private.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SN2_SN_PRIVATE_H #define _ASM_IA64_SN_SN2_SN_PRIVATE_H @@ -49,13 +49,13 @@ extern void get_dir_ent(paddr_t paddr, int *state, #endif /* intr.c */ -extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name); +extern int intr_reserve_level(cpuid_t cpu, int level, int err, vertex_hdl_t owner_dev, char *name); extern void intr_unreserve_level(cpuid_t cpu, int level); extern int intr_connect_level(cpuid_t cpu, int bit, ilvl_t mask_no, intr_func_t intr_prefunc); extern int intr_disconnect_level(cpuid_t cpu, int bit); -extern cpuid_t intr_heuristic(devfs_handle_t dev, device_desc_t dev_desc, - int req_bit,int intr_resflags,devfs_handle_t owner_dev, +extern cpuid_t intr_heuristic(vertex_hdl_t dev, device_desc_t dev_desc, + int req_bit,int intr_resflags,vertex_hdl_t owner_dev, char *intr_name,int *resp_bit); extern void intr_block_bit(cpuid_t cpu, int bit); extern void intr_unblock_bit(cpuid_t cpu, int bit); @@ -83,8 +83,8 @@ void bte_lateinit(void); void bte_wait_for_xfer_completion(void *); /* klgraph.c */ -void klhwg_add_all_nodes(devfs_handle_t); -void klhwg_add_all_modules(devfs_handle_t); +void klhwg_add_all_nodes(vertex_hdl_t); +void klhwg_add_all_modules(vertex_hdl_t); /* klidbg.c */ void install_klidbg_functions(void); @@ -97,7 +97,6 @@ extern void setup_replication_mask(int maxnodes); /* init.c */ extern cnodeid_t get_compact_nodeid(void); /* get compact node id */ extern void init_platform_nodepda(nodepda_t *npda, cnodeid_t node); -extern void init_platform_pda(cpuid_t cpu); extern void per_cpu_init(void); extern int is_fine_dirmode(void); extern void update_node_information(cnodeid_t); @@ -125,7 +124,7 @@ extern __psunsigned_t debugger_stopped; */ struct hub_piomap_s { struct xtalk_piomap_s hpio_xtalk_info;/* standard crosstalk pio info */ - devfs_handle_t hpio_hub; /* which shub's mapping registers are set up */ + vertex_hdl_t hpio_hub; /* which shub's mapping registers are set up */ short hpio_holdcnt; /* count of current users of bigwin mapping */ char hpio_bigwin_num;/* if big window map, which one */ int hpio_flags; /* defined below */ @@ -146,7 +145,7 @@ struct hub_piomap_s { */ struct hub_dmamap_s { struct xtalk_dmamap_s hdma_xtalk_info;/* standard crosstalk dma info */ - devfs_handle_t hdma_hub; /* which shub we go through */ + vertex_hdl_t hdma_hub; /* which shub we go through */ int hdma_flags; /* defined below */ }; /* shub_dmamap flags */ @@ -214,7 +213,7 @@ typedef struct cpuinfo_s { (vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr) /* Special initialization function for xswitch vertices created during startup. */ -extern void xswitch_vertex_init(devfs_handle_t xswitch); +extern void xswitch_vertex_init(vertex_hdl_t xswitch); extern xtalk_provider_t hub_provider; @@ -248,6 +247,6 @@ extern void crbx(nasid_t nasid, void (*pf)(char *, ...)); void bootstrap(void); /* sndrv.c */ -extern int sndrv_attach(devfs_handle_t vertex); +extern int sndrv_attach(vertex_hdl_t vertex); #endif /* _ASM_IA64_SN_SN2_SN_PRIVATE_H */ diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h index 3a56e4aeff326..74dd5a6d24606 100644 --- a/include/asm-ia64/sn/sn_cpuid.h +++ b/include/asm-ia64/sn/sn_cpuid.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. */ @@ -18,6 +18,7 @@ #include <asm/sn/types.h> #include <asm/current.h> #include <asm/nodedata.h> +#include <asm/sn/pda.h> /* @@ -51,11 +52,6 @@ * * LID - processor defined register (see PRM V2). * - * On SN1 - * 31:24 - id Contains the NASID - * 23:16 - eid Contains 0-3 to identify the cpu on the node - * bit 17 - synergy number - * bit 16 - FSB slot number * On SN2 * 31:28 - id Contains 0-3 to identify the cpu on the node * 27:16 - eid Contains the NASID @@ -64,34 +60,30 @@ * * The following assumes the following mappings for LID register values: * - * The macros convert between cpu physical ids & slice/fsb/synergy/nasid/cnodeid. + * The macros convert between cpu physical ids & slice/nasid/cnodeid. * These terms are described below: * * + * Brick * ----- ----- ----- ----- CPU - * | 0 | | 1 | | 2 | | 3 | SLICE + * | 0 | | 1 | | 0 | | 1 | SLICE * ----- ----- ----- ----- * | | | | * | | | | - * 0 | | 1 0 | | 1 FSB SLOT + * 0 | | 2 0 | | 2 FSB SLOT * ------- ------- * | | * | | - * ------- ------- - * | | | | - * | 0 | | 1 | SYNERGY (SN1 only) - * | | | | - * ------- ------- * | | - * | | - * ------------------------------- - * | | - * | BEDROCK / SHUB | NASID (0..MAX_NASIDS) - * | | CNODEID (0..num_compact_nodes-1) - * | | - * | | - * ------------------------------- - * | + * ------------ ------------- + * | | | | + * | SHUB | | SHUB | NASID (0..MAX_NASIDS) + * | |----- | | CNODEID (0..num_compact_nodes-1) + * | | | | + * | | | | + * ------------ ------------- + * | | + * * */ @@ -100,25 +92,15 @@ #define cpu_physical_id(cpuid) ((ia64_get_lid() >> 16) & 0xffff) #endif -#ifdef CONFIG_IA64_SGI_SN1 /* * macros for some of these exist in sn/addrs.h & sn/arch.h, etc. However, * trying #include these files here causes circular dependencies. */ -#define cpu_physical_id_to_nasid(cpi) ((cpi) >> 8) -#define cpu_physical_id_to_synergy(cpi) (((cpi) >> 1) & 1) -#define cpu_physical_id_to_fsb_slot(cpi) ((cpi) & 1) -#define cpu_physical_id_to_slice(cpi) ((cpi) & 3) -#define get_nasid() ((ia64_get_lid() >> 24)) -#define get_slice() ((ia64_get_lid() >> 16) & 3) -#define get_node_number(addr) (((unsigned long)(addr)>>33) & 0x7f) -#else #define cpu_physical_id_to_nasid(cpi) ((cpi) &0xfff) #define cpu_physical_id_to_slice(cpi) ((cpi>>12) & 3) #define get_nasid() ((ia64_get_lid() >> 16) & 0xfff) #define get_slice() ((ia64_get_lid() >> 28) & 0xf) #define get_node_number(addr) (((unsigned long)(addr)>>38) & 0x7ff) -#endif /* * NOTE: id & eid refer to Intel's definitions of the LID register @@ -129,11 +111,7 @@ #define nasid_slice_to_cpuid(nasid,slice) (cpu_logical_id(nasid_slice_to_cpu_physical_id((nasid),(slice)))) -#ifdef CONFIG_IA64_SGI_SN1 -#define nasid_slice_to_cpu_physical_id(nasid, slice) (((nasid)<<8) | (slice)) -#else #define nasid_slice_to_cpu_physical_id(nasid, slice) (((slice)<<12) | (nasid)) -#endif /* * The following table/struct is used for managing PTC coherency domains. @@ -145,26 +123,9 @@ typedef struct { } sn_sapicid_info_t; extern sn_sapicid_info_t sn_sapicid_info[]; /* indexed by cpuid */ +extern short physical_node_map[]; /* indexed by nasid to get cnode */ - -#ifdef CONFIG_IA64_SGI_SN1 -/* - * cpuid_to_fsb_slot - convert a cpuid to the fsb slot number that it is in. - * (there are 2 cpus per FSB. This function returns 0 or 1) - */ -#define cpuid_to_fsb_slot(cpuid) (cpu_physical_id_to_fsb_slot(cpu_physical_id(cpuid))) - - -/* - * cpuid_to_synergy - convert a cpuid to the synergy that it resides on - * (there are 2 synergies per node. Function returns 0 or 1 to - * specify which synergy the cpu is on) - */ -#define cpuid_to_synergy(cpuid) (cpu_physical_id_to_synergy(cpu_physical_id(cpuid))) - -#endif - /* * cpuid_to_slice - convert a cpuid to the slice that it resides on * There are 4 cpus per node. This function returns 0 .. 3) @@ -181,7 +142,7 @@ extern sn_sapicid_info_t sn_sapicid_info[]; /* indexed by cpuid */ /* * cpuid_to_cnodeid - convert a cpuid to the cnode that it resides on */ -#define cpuid_to_cnodeid(cpuid) (local_node_data->physical_node_map[cpuid_to_nasid(cpuid)]) +#define cpuid_to_cnodeid(cpuid) (physical_node_map[cpuid_to_nasid(cpuid)]) /* @@ -190,13 +151,13 @@ extern sn_sapicid_info_t sn_sapicid_info[]; /* indexed by cpuid */ * Just extract the NASID from the pointer. * */ -#define cnodeid_to_nasid(cnodeid) (get_node_number(local_node_data->pg_data_ptrs[cnodeid])) +#define cnodeid_to_nasid(cnodeid) pda->cnodeid_to_nasid_table[cnodeid] /* * nasid_to_cnodeid - convert a NASID to a cnodeid */ -#define nasid_to_cnodeid(nasid) (nasid) /* (local_node_data->physical_node_map[nasid]) */ +#define nasid_to_cnodeid(nasid) (physical_node_map[nasid]) /* @@ -214,23 +175,8 @@ extern sn_sapicid_info_t sn_sapicid_info[]; /* indexed by cpuid */ #define cpuid_to_subnode(cpuid) ((cpuid_to_slice(cpuid)<2) ? 0 : 1) -/* - * cpuid_to_localslice - convert a cpuid to a local slice - * slice 0 & 2 are local slice 0 - * slice 1 & 3 are local slice 1 - */ -#define cpuid_to_localslice(cpuid) (cpuid_to_slice(cpuid) & 1) - - #define smp_physical_node_id() (cpuid_to_nasid(smp_processor_id())) -/* - * cnodeid_to_cpuid - convert a cnode to a cpuid of a cpu on the node. - * returns -1 if no cpus exist on the node - */ -extern int cnodeid_to_cpuid(int cnode); - - #endif /* _ASM_IA64_SN_SN_CPUID_H */ diff --git a/include/asm-ia64/sn/sn_fru.h b/include/asm-ia64/sn/sn_fru.h index f2800c1780543..c70bb7ea1fc2c 100644 --- a/include/asm-ia64/sn/sn_fru.h +++ b/include/asm-ia64/sn/sn_fru.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 1999-2001 Silicon Graphics, Inc. - * All rights reserved. + * Copyright (C) 1992-1997,1999-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SN_FRU_H #define _ASM_IA64_SN_SN_FRU_H diff --git a/include/asm-ia64/sn/sn_pio_sync.h b/include/asm-ia64/sn/sn_pio_sync.h deleted file mode 100644 index 1fc590447eef5..0000000000000 --- a/include/asm-ia64/sn/sn_pio_sync.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved. - */ - - -#ifndef _ASM_IA64_SN_SN_PIO_WRITE_SYNC_H -#define _ASM_IA64_SN_SN_PIO_WRITE_SYNC_H - -#include <linux/config.h> -#ifdef CONFIG_IA64_SGI_SN2 -#include <asm/sn/sn_cpuid.h> -#include <asm/sn/sn2/addrs.h> -#include <asm/sn/sn2/shub_mmr.h> -#include <asm/sn/sn2/shub_mmr_t.h> - -/* - * This macro flushes all outstanding PIOs performed by this cpu to the - * intended destination SHUB. This in essence ensures that all PIO's - * issues by this cpu has landed at it's destination. - * - * This macro expects the caller: - * 1. The thread is locked. - * 2. All prior PIO operations has been fenced with __ia64_mf_a(). - * - * The expectation is that get_slice() will return either 0 or 2. - * When we have multi-core cpu's, the expectation is get_slice() will - * return either 0,1 or 2,3. - */ - -#define SN_PIO_WRITE_SYNC \ - { \ - volatile unsigned long sn_pio_writes_done; \ - do { \ - sn_pio_writes_done = (volatile unsigned long) (SH_PIO_WRITE_STATUS_0_WRITES_OK_MASK & HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(get_nasid(), (get_slice() < 2) ? SH_PIO_WRITE_STATUS_0 : SH_PIO_WRITE_STATUS_1 ))); \ - } while (!sn_pio_writes_done); \ - __ia64_mf_a(); \ - } -#else - -/* - * For all ARCHITECTURE type, this is a NOOP. - */ - -#define SN_PIO_WRITE_SYNC - -#endif - -#endif /* _ASM_IA64_SN_SN_PIO_WRITE_SYNC_H */ diff --git a/include/asm-ia64/sn/sn_private.h b/include/asm-ia64/sn/sn_private.h index e382cb5d80e25..4fd2074bd54c0 100644 --- a/include/asm-ia64/sn/sn_private.h +++ b/include/asm-ia64/sn/sn_private.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SN_PRIVATE_H #define _ASM_IA64_SN_SN_PRIVATE_H @@ -14,10 +14,6 @@ #include <asm/sn/xtalk/xwidget.h> #include <asm/sn/xtalk/xtalk_private.h> -#if defined(CONFIG_IA64_SGI_SN1) -#include <asm/sn/sn1/sn_private.h> -#elif defined(CONFIG_IA64_SGI_SN2) #include <asm/sn/sn2/sn_private.h> -#endif #endif /* _ASM_IA64_SN_SN_PRIVATE_H */ diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h index e1f1b3e4d0a31..66fd8ef46c75c 100644 --- a/include/asm-ia64/sn/sn_sal.h +++ b/include/asm-ia64/sn/sn_sal.h @@ -8,7 +8,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2000-2003 Silicon Graphics, Inc. All rights reserved. */ @@ -36,6 +36,8 @@ #define SN_SAL_CONSOLE_POLL 0x02000026 #define SN_SAL_CONSOLE_INTR 0x02000027 #define SN_SAL_CONSOLE_PUTB 0x02000028 +#define SN_SAL_CONSOLE_XMIT_CHARS 0x0200002a +#define SN_SAL_CONSOLE_READC 0x0200002b #define SN_SAL_SYSCTL_MODID_GET 0x02000031 #define SN_SAL_SYSCTL_GET 0x02000032 #define SN_SAL_SYSCTL_IOBRICK_MODULE_GET 0x02000033 @@ -47,17 +49,22 @@ #define SN_SAL_SYSCTL_PARTITION_GET 0x0200003a #define SN_SAL_SYSTEM_POWER_DOWN 0x0200003b #define SN_SAL_GET_MASTER_BASEIO_NASID 0x0200003c +#define SN_SAL_COHERENCE 0x0200003d +#define SN_SAL_SYSCTL_FRU_CAPTURE 0x0200003f /* * Service-specific constants */ -#define SAL_CONSOLE_INTR_IN 0 /* manipulate input interrupts */ -#define SAL_CONSOLE_INTR_OUT 1 /* manipulate output low-water - * interrupts - */ + +/* Console interrupt manipulation */ + /* action codes */ #define SAL_CONSOLE_INTR_OFF 0 /* turn the interrupt off */ #define SAL_CONSOLE_INTR_ON 1 /* turn the interrupt on */ +#define SAL_CONSOLE_INTR_STATUS 2 /* retrieve the interrupt status */ + /* interrupt specification & status return codes */ +#define SAL_CONSOLE_INTR_XMIT 1 /* output interrupt */ +#define SAL_CONSOLE_INTR_RECV 2 /* input interrupt */ /* @@ -103,15 +110,8 @@ sn_sal_rev_minor(void) * Specify the minimum PROM revsion required for this kernel. * Note that they're stored in hex format... */ -#ifdef CONFIG_IA64_SGI_SN1 -#define SN_SAL_MIN_MAJOR 0x0 -#define SN_SAL_MIN_MINOR 0x03 /* SN1 PROMs are stuck at rev 0.03 */ -#elif defined(CONFIG_IA64_SGI_SN2) -#define SN_SAL_MIN_MAJOR 0x0 -#define SN_SAL_MIN_MINOR 0x11 -#else -#error "must specify which PROM revisions this kernel needs" -#endif /* CONFIG_IA64_SGI_SN1 */ +#define SN_SAL_MIN_MAJOR 0x1 /* SN2 kernels need at least PROM 1.0 */ +#define SN_SAL_MIN_MINOR 0x0 u64 ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr); @@ -124,10 +124,10 @@ ia64_sn_get_console_nasid(void) { struct ia64_sal_retval ret_stuff; - ret_stuff.status = (uint64_t)0; - ret_stuff.v0 = (uint64_t)0; - ret_stuff.v1 = (uint64_t)0; - ret_stuff.v2 = (uint64_t)0; + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_NASID, 0, 0, 0, 0, 0, 0, 0); if (ret_stuff.status < 0) @@ -146,10 +146,10 @@ ia64_sn_get_master_baseio_nasid(void) { struct ia64_sal_retval ret_stuff; - ret_stuff.status = (uint64_t)0; - ret_stuff.v0 = (uint64_t)0; - ret_stuff.v1 = (uint64_t)0; - ret_stuff.v2 = (uint64_t)0; + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_BASEIO_NASID, 0, 0, 0, 0, 0, 0, 0); if (ret_stuff.status < 0) @@ -166,12 +166,12 @@ ia64_sn_get_klconfig_addr(nasid_t nasid) extern u64 klgraph_addr[]; int cnodeid; - cnodeid = 0 /* nasid_to_cnodeid(nasid) */; + cnodeid = nasid_to_cnodeid(nasid); if (klgraph_addr[cnodeid] == 0) { - ret_stuff.status = (uint64_t)0; - ret_stuff.v0 = (uint64_t)0; - ret_stuff.v1 = (uint64_t)0; - ret_stuff.v2 = (uint64_t)0; + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0); /* @@ -195,11 +195,11 @@ ia64_sn_console_getc(int *ch) { struct ia64_sal_retval ret_stuff; - ret_stuff.status = (uint64_t)0; - ret_stuff.v0 = (uint64_t)0; - ret_stuff.v1 = (uint64_t)0; - ret_stuff.v2 = (uint64_t)0; - __SAL_CALL(ret_stuff, SN_SAL_CONSOLE_GETC, 0, 0, 0, 0, 0, 0, 0); + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_GETC, 0, 0, 0, 0, 0, 0, 0); /* character is in 'v0' */ *ch = (int)ret_stuff.v0; @@ -208,6 +208,26 @@ ia64_sn_console_getc(int *ch) } /* + * Read a character from the SAL console device, after a previous interrupt + * or poll operation has given us to know that a character is available + * to be read. + */ +static inline u64 +ia64_sn_console_readc(void) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_READC, 0, 0, 0, 0, 0, 0, 0); + + /* character is in 'v0' */ + return ret_stuff.v0; +} + +/* * Sends the given character to the console. */ static inline u64 @@ -215,11 +235,11 @@ ia64_sn_console_putc(char ch) { struct ia64_sal_retval ret_stuff; - ret_stuff.status = (uint64_t)0; - ret_stuff.v0 = (uint64_t)0; - ret_stuff.v1 = (uint64_t)0; - ret_stuff.v2 = (uint64_t)0; - __SAL_CALL(ret_stuff, SN_SAL_CONSOLE_PUTC, (uint64_t)ch, 0, 0, 0, 0, 0, 0); + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (uint64_t)ch, 0, 0, 0, 0, 0, 0); return ret_stuff.status; } @@ -228,17 +248,20 @@ ia64_sn_console_putc(char ch) * Sends the given buffer to the console. */ static inline u64 -ia64_sn_console_putb(char *buf, int len) +ia64_sn_console_putb(const char *buf, int len) { struct ia64_sal_retval ret_stuff; - ret_stuff.status = (uint64_t)0; - ret_stuff.v0 = (uint64_t)0; - ret_stuff.v1 = (uint64_t)0; - ret_stuff.v2 = (uint64_t)0; - __SAL_CALL(ret_stuff, SN_SAL_CONSOLE_PUTB, (uint64_t)buf, (uint64_t)len, 0, 0, 0, 0, 0); + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (uint64_t)buf, (uint64_t)len, 0, 0, 0, 0, 0); - return ret_stuff.status; + if ( ret_stuff.status == 0 ) { + return ret_stuff.v0; + } + return (u64)0; } /* @@ -249,11 +272,11 @@ ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec) { struct ia64_sal_retval ret_stuff; - ret_stuff.status = (uint64_t)0; - ret_stuff.v0 = (uint64_t)0; - ret_stuff.v1 = (uint64_t)0; - ret_stuff.v2 = (uint64_t)0; - __SAL_CALL(ret_stuff, SN_SAL_PRINT_ERROR, (uint64_t)hook, (uint64_t)rec, 0, 0, 0, 0, 0); + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_PRINT_ERROR, (uint64_t)hook, (uint64_t)rec, 0, 0, 0, 0, 0); return ret_stuff.status; } @@ -266,11 +289,11 @@ ia64_sn_plat_cpei_handler(void) { struct ia64_sal_retval ret_stuff; - ret_stuff.status = (uint64_t)0; - ret_stuff.v0 = (uint64_t)0; - ret_stuff.v1 = (uint64_t)0; - ret_stuff.v2 = (uint64_t)0; - __SAL_CALL(ret_stuff, SN_SAL_LOG_CE, 0, 0, 0, 0, 0, 0, 0); + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_LOG_CE, 0, 0, 0, 0, 0, 0, 0); return ret_stuff.status; } @@ -283,11 +306,11 @@ ia64_sn_console_check(int *result) { struct ia64_sal_retval ret_stuff; - ret_stuff.status = (uint64_t)0; - ret_stuff.v0 = (uint64_t)0; - ret_stuff.v1 = (uint64_t)0; - ret_stuff.v2 = (uint64_t)0; - __SAL_CALL(ret_stuff, SN_SAL_CONSOLE_POLL, 0, 0, 0, 0, 0, 0, 0); + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_POLL, 0, 0, 0, 0, 0, 0, 0); /* result is in 'v0' */ *result = (int)ret_stuff.v0; @@ -296,6 +319,86 @@ ia64_sn_console_check(int *result) } /* + * Checks console interrupt status + */ +static inline u64 +ia64_sn_console_intr_status(void) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR, + 0, SAL_CONSOLE_INTR_STATUS, + 0, 0, 0, 0, 0); + + if (ret_stuff.status == 0) { + return ret_stuff.v0; + } + + return 0; +} + +/* + * Enable an interrupt on the SAL console device. + */ +static inline void +ia64_sn_console_intr_enable(uint64_t intr) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR, + intr, SAL_CONSOLE_INTR_ON, + 0, 0, 0, 0, 0); +} + +/* + * Disable an interrupt on the SAL console device. + */ +static inline void +ia64_sn_console_intr_disable(uint64_t intr) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR, + intr, SAL_CONSOLE_INTR_OFF, + 0, 0, 0, 0, 0); +} + +/* + * Sends a character buffer to the console asynchronously. + */ +static inline u64 +ia64_sn_console_xmit_chars(char *buf, int len) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS, + (uint64_t)buf, (uint64_t)len, + 0, 0, 0, 0, 0); + + if (ret_stuff.status == 0) { + return ret_stuff.v0; + } + + return 0; +} + +/* * Returns the iobrick module Id */ static inline u64 @@ -303,11 +406,11 @@ ia64_sn_sysctl_iobrick_module_get(nasid_t nasid, int *result) { struct ia64_sal_retval ret_stuff; - ret_stuff.status = (uint64_t)0; - ret_stuff.v0 = (uint64_t)0; - ret_stuff.v1 = (uint64_t)0; - ret_stuff.v2 = (uint64_t)0; - SAL_CALL(ret_stuff, SN_SAL_SYSCTL_IOBRICK_MODULE_GET, nasid, 0, 0, 0, 0, 0, 0); + ret_stuff.status = 0; + ret_stuff.v0 = 0; + ret_stuff.v1 = 0; + ret_stuff.v2 = 0; + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYSCTL_IOBRICK_MODULE_GET, nasid, 0, 0, 0, 0, 0, 0); /* result is in 'v0' */ *result = (int)ret_stuff.v0; @@ -339,7 +442,7 @@ static inline u64 ia64_sn_sys_serial_get(char *buf) { struct ia64_sal_retval ret_stuff; - SAL_CALL(ret_stuff, SN_SAL_SYS_SERIAL_GET, buf, 0, 0, 0, 0, 0, 0); + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYS_SERIAL_GET, buf, 0, 0, 0, 0, 0, 0); return ret_stuff.status; } @@ -395,7 +498,6 @@ ia64_sn_sysctl_partition_get(nasid_t nasid) return ((partid_t)ret_stuff.v0); } -#ifdef CONFIG_IA64_SGI_SN2 /* * Returns the partition id of the current processor. */ @@ -411,7 +513,25 @@ sn_local_partid(void) { } } -#endif /* CONFIG_IA64_SGI_SN2 */ +/* + * Change or query the coherence domain for this partition. Each cpu-based + * nasid is represented by a bit in an array of 64-bit words: + * 0 = not in this partition's coherency domain + * 1 = in this partition's coherency domain + * It is not possible for the local system's nasids to be removed from + * the coherency domain. + * + * new_domain = set the coherence domain to the given nasids + * old_domain = return the current coherence domain + */ +static inline int +sn_change_coherence(u64 *new_domain, u64 *old_domain) +{ + struct ia64_sal_retval ret_stuff; + SAL_CALL(ret_stuff, SN_SAL_COHERENCE, new_domain, old_domain, 0, 0, + 0, 0, 0); + return ret_stuff.status; +} /* * Turns off system power. @@ -425,5 +545,20 @@ ia64_sn_power_down(void) /* never returns */ } +/** + * ia64_sn_fru_capture - tell the system controller to capture hw state + * + * This routine will call the SAL which will tell the system controller(s) + * to capture hw mmr information from each SHub in the system. + */ +static inline u64 +ia64_sn_fru_capture(void) +{ + struct ia64_sal_retval isrv; + SAL_CALL(isrv, SN_SAL_SYSCTL_FRU_CAPTURE, 0, 0, 0, 0, 0, 0, 0); + if (isrv.status) + return 0; + return isrv.v0; +} #endif /* _ASM_IA64_SN_SN_SAL_H */ diff --git a/include/asm-ia64/sn/snconfig.h b/include/asm-ia64/sn/snconfig.h deleted file mode 100644 index 0ea7f49d1ccb6..0000000000000 --- a/include/asm-ia64/sn/snconfig.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_IA64_SN_SNCONFIG_H -#define _ASM_IA64_SN_SNCONFIG_H - -#include <linux/config.h> - -#if defined(CONFIG_IA64_SGI_SN1) -#include <asm/sn/sn1/ip27config.h> -#elif defined(CONFIG_IA64_SGI_SN2) -#endif - -#endif /* _ASM_IA64_SN_SNCONFIG_H */ diff --git a/include/asm-ia64/sn/sndrv.h b/include/asm-ia64/sn/sndrv.h index ea5f4c5abfbdc..b657c16c86953 100644 --- a/include/asm-ia64/sn/sndrv.h +++ b/include/asm-ia64/sn/sndrv.h @@ -1,3 +1,35 @@ +/* + * Copyright (c) 2002-2003 Silicon Graphics, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: + * + * http://www.sgi.com + * + * For further information regarding this notice, see: + * + * http://oss.sgi.com/projects/GenInfo/NoticeExplan + */ + #ifndef _ASM_IA64_SN_SNDRV_H #define _ASM_IA64_SN_SNDRV_H diff --git a/include/asm-ia64/sn/sv.h b/include/asm-ia64/sn/sv.h index 8e93fb91e0eb6..69ae9762f20c1 100644 --- a/include/asm-ia64/sn/sv.h +++ b/include/asm-ia64/sn/sv.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved + * Copyright (C) 2000-2003 Silicon Graphics, Inc. All Rights Reserved. * * This implemenation of synchronization variables is heavily based on * one done by Steve Lord <lord@sgi.com> diff --git a/include/asm-ia64/sn/systeminfo.h b/include/asm-ia64/sn/systeminfo.h index 819e2a043f385..b8d85db1c544a 100644 --- a/include/asm-ia64/sn/systeminfo.h +++ b/include/asm-ia64/sn/systeminfo.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SYSTEMINFO_H #define _ASM_IA64_SN_SYSTEMINFO_H diff --git a/include/asm-ia64/sn/types.h b/include/asm-ia64/sn/types.h index acc56951766c2..0275ce759abfc 100644 --- a/include/asm-ia64/sn/types.h +++ b/include/asm-ia64/sn/types.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1999,2001-2002 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (C) 1999,2001-2003 Silicon Graphics, Inc. All Rights Reserved. * Copyright (C) 1999 by Ralf Baechle */ #ifndef _ASM_IA64_SN_TYPES_H @@ -13,16 +13,10 @@ #include <linux/types.h> typedef unsigned long cpuid_t; -typedef unsigned long cpumask_t; typedef signed short nasid_t; /* node id in numa-as-id space */ typedef signed char partid_t; /* partition ID type */ -#ifdef CONFIG_IA64_SGI_SN2 typedef unsigned int moduleid_t; /* user-visible module number type */ typedef unsigned int cmoduleid_t; /* kernel compact module id type */ -#else -typedef signed short moduleid_t; /* user-visible module number type */ -typedef signed short cmoduleid_t; /* kernel compact module id type */ -#endif typedef signed char slabid_t; typedef unsigned char clusterid_t; /* Clusterid of the cell */ @@ -32,5 +26,6 @@ typedef unsigned long iopaddr_t; typedef unsigned char uchar_t; typedef unsigned long paddr_t; typedef unsigned long pfn_t; +typedef short cnodeid_t; #endif /* _ASM_IA64_SN_TYPES_H */ diff --git a/include/asm-ia64/sn/uart16550.h b/include/asm-ia64/sn/uart16550.h index e7f9251a5ce6b..96f39fd43d44a 100644 --- a/include/asm-ia64/sn/uart16550.h +++ b/include/asm-ia64/sn/uart16550.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_UART16550_H diff --git a/include/asm-ia64/sn/vector.h b/include/asm-ia64/sn/vector.h index f6db63e3dad0a..a01d7b9aea69f 100644 --- a/include/asm-ia64/sn/vector.h +++ b/include/asm-ia64/sn/vector.h @@ -4,29 +4,16 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_VECTOR_H #define _ASM_IA64_SN_VECTOR_H #include <linux/config.h> -#include <asm/sn/arch.h> #define NET_VEC_NULL ((net_vec_t) 0) #define NET_VEC_BAD ((net_vec_t) -1) -#ifdef RTL - -#define VEC_POLLS_W 16 /* Polls before write times out */ -#define VEC_POLLS_R 16 /* Polls before read times out */ -#define VEC_POLLS_X 16 /* Polls before exch times out */ - -#define VEC_RETRIES_W 1 /* Retries before write fails */ -#define VEC_RETRIES_R 1 /* Retries before read fails */ -#define VEC_RETRIES_X 1 /* Retries before exch fails */ - -#else /* RTL */ - #define VEC_POLLS_W 128 /* Polls before write times out */ #define VEC_POLLS_R 128 /* Polls before read times out */ #define VEC_POLLS_X 128 /* Polls before exch times out */ @@ -35,37 +22,6 @@ #define VEC_RETRIES_R 8 /* Retries before read fails */ #define VEC_RETRIES_X 4 /* Retries before exch fails */ -#endif /* RTL */ - -#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -#define VECTOR_PARMS LB_VECTOR_PARMS -#define VECTOR_ROUTE LB_VECTOR_ROUTE -#define VECTOR_DATA LB_VECTOR_DATA -#define VECTOR_STATUS LB_VECTOR_STATUS -#define VECTOR_RETURN LB_VECTOR_RETURN -#define VECTOR_READ_DATA LB_VECTOR_READ_DATA -#define VECTOR_STATUS_CLEAR LB_VECTOR_STATUS_CLEAR -#define VP_PIOID_SHFT LVP_PIOID_SHFT -#define VP_PIOID_MASK LVP_PIOID_MASK -#define VP_WRITEID_SHFT LVP_WRITEID_SHFT -#define VP_WRITEID_MASK LVP_WRITEID_MASK -#define VP_ADDRESS_MASK LVP_ADDRESS_MASK -#define VP_TYPE_SHFT LVP_TYPE_SHFT -#define VP_TYPE_MASK LVP_TYPE_MASK -#define VS_VALID LVS_VALID -#define VS_OVERRUN LVS_OVERRUN -#define VS_TARGET_SHFT LVS_TARGET_SHFT -#define VS_TARGET_MASK LVS_TARGET_MASK -#define VS_PIOID_SHFT LVS_PIOID_SHFT -#define VS_PIOID_MASK LVS_PIOID_MASK -#define VS_WRITEID_SHFT LVS_WRITEID_SHFT -#define VS_WRITEID_MASK LVS_WRITEID_MASK -#define VS_ADDRESS_MASK LVS_ADDRESS_MASK -#define VS_TYPE_SHFT LVS_TYPE_SHFT -#define VS_TYPE_MASK LVS_TYPE_MASK -#define VS_ERROR_MASK LVS_ERROR_MASK -#endif - #define NET_ERROR_NONE 0 /* No error */ #define NET_ERROR_HARDWARE (-1) /* Hardware error */ #define NET_ERROR_OVERRUN (-2) /* Extra response(s) */ diff --git a/include/asm-ia64/sn/xtalk/xbow.h b/include/asm-ia64/sn/xtalk/xbow.h index a23ba30c2ca35..702d10be57fdc 100644 --- a/include/asm-ia64/sn/xtalk/xbow.h +++ b/include/asm-ia64/sn/xtalk/xbow.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_SN_XTALK_XBOW_H #define _ASM_SN_SN_XTALK_XBOW_H @@ -406,12 +405,6 @@ typedef struct xbow_cfg_s { /* XBOW_WID_ARB_RELOAD */ #define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */ - -#ifdef CONFIG_IA64_SGI_SN1 -#define nasid_has_xbridge(nasid) \ - (XWIDGET_PART_NUM(XWIDGET_ID_READ(nasid, 0)) == XXBOW_WIDGET_PART_NUM) -#endif - #define IS_XBRIDGE_XBOW(wid) \ (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \ XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) diff --git a/include/asm-ia64/sn/xtalk/xbow_info.h b/include/asm-ia64/sn/xtalk/xbow_info.h index c4b32bb98a268..ccfc3348652b1 100644 --- a/include/asm-ia64/sn/xtalk/xbow_info.h +++ b/include/asm-ia64/sn/xtalk/xbow_info.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992-1997,2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_XTALK_XBOW_INFO_H #define _ASM_SN_XTALK_XBOW_INFO_H @@ -48,9 +48,9 @@ typedef struct xbow_perf { volatile uint32_t *xp_perf_reg; } xbow_perf_t; -extern void xbow_update_perf_counters(devfs_handle_t); -extern xbow_perf_link_t *xbow_get_perf_counters(devfs_handle_t); -extern int xbow_enable_perf_counter(devfs_handle_t, int, int, int); +extern void xbow_update_perf_counters(vertex_hdl_t); +extern xbow_perf_link_t *xbow_get_perf_counters(vertex_hdl_t); +extern int xbow_enable_perf_counter(vertex_hdl_t, int, int, int); #define XBOWIOC_PERF_ENABLE 1 #define XBOWIOC_PERF_DISABLE 2 diff --git a/include/asm-ia64/sn/xtalk/xswitch.h b/include/asm-ia64/sn/xtalk/xswitch.h index beb44a0271ec4..a406bea97d598 100644 --- a/include/asm-ia64/sn/xtalk/xswitch.h +++ b/include/asm-ia64/sn/xtalk/xswitch.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992-1997,2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_XTALK_XSWITCH_H #define _ASM_SN_XTALK_XSWITCH_H @@ -23,39 +23,36 @@ typedef struct xswitch_info_s *xswitch_info_t; typedef int - xswitch_reset_link_f(devfs_handle_t xconn); + xswitch_reset_link_f(vertex_hdl_t xconn); typedef struct xswitch_provider_s { xswitch_reset_link_f *reset_link; } xswitch_provider_t; -extern void xswitch_provider_register(devfs_handle_t sw_vhdl, xswitch_provider_t * xsw_fns); +extern void xswitch_provider_register(vertex_hdl_t sw_vhdl, xswitch_provider_t * xsw_fns); xswitch_reset_link_f xswitch_reset_link; -extern xswitch_info_t xswitch_info_new(devfs_handle_t vhdl); +extern xswitch_info_t xswitch_info_new(vertex_hdl_t vhdl); extern void xswitch_info_link_is_ok(xswitch_info_t xswitch_info, xwidgetnum_t port); extern void xswitch_info_vhdl_set(xswitch_info_t xswitch_info, xwidgetnum_t port, - devfs_handle_t xwidget); + vertex_hdl_t xwidget); extern void xswitch_info_master_assignment_set(xswitch_info_t xswitch_info, xwidgetnum_t port, - devfs_handle_t master_vhdl); + vertex_hdl_t master_vhdl); -extern xswitch_info_t xswitch_info_get(devfs_handle_t vhdl); +extern xswitch_info_t xswitch_info_get(vertex_hdl_t vhdl); extern int xswitch_info_link_ok(xswitch_info_t xswitch_info, xwidgetnum_t port); -extern devfs_handle_t xswitch_info_vhdl_get(xswitch_info_t xswitch_info, +extern vertex_hdl_t xswitch_info_vhdl_get(xswitch_info_t xswitch_info, xwidgetnum_t port); -extern devfs_handle_t xswitch_info_master_assignment_get(xswitch_info_t xswitch_info, +extern vertex_hdl_t xswitch_info_master_assignment_get(xswitch_info_t xswitch_info, xwidgetnum_t port); -extern int xswitch_id_get(devfs_handle_t vhdl); -extern void xswitch_id_set(devfs_handle_t vhdl,int xbow_num); - #endif /* __ASSEMBLY__ */ #endif /* _ASM_SN_XTALK_XSWITCH_H */ diff --git a/include/asm-ia64/sn/xtalk/xtalk.h b/include/asm-ia64/sn/xtalk/xtalk.h index 14b1680f13d07..0a55893fb95d6 100644 --- a/include/asm-ia64/sn/xtalk/xtalk.h +++ b/include/asm-ia64/sn/xtalk/xtalk.h @@ -4,12 +4,15 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_XTALK_XTALK_H #define _ASM_SN_XTALK_XTALK_H #include <linux/config.h> +#include "asm/sn/sgi.h" + + /* * xtalk.h -- platform-independent crosstalk interface */ @@ -85,7 +88,7 @@ struct xwidget_hwid_s; /* PIO MANAGEMENT */ typedef xtalk_piomap_t -xtalk_piomap_alloc_f (devfs_handle_t dev, /* set up mapping for this device */ +xtalk_piomap_alloc_f (vertex_hdl_t dev, /* set up mapping for this device */ device_desc_t dev_desc, /* device descriptor */ iopaddr_t xtalk_addr, /* map for this xtalk_addr range */ size_t byte_count, @@ -103,14 +106,14 @@ typedef void xtalk_piomap_done_f (xtalk_piomap_t xtalk_piomap); typedef caddr_t -xtalk_piotrans_addr_f (devfs_handle_t dev, /* translate for this device */ +xtalk_piotrans_addr_f (vertex_hdl_t dev, /* translate for this device */ device_desc_t dev_desc, /* device descriptor */ iopaddr_t xtalk_addr, /* Crosstalk address */ size_t byte_count, /* map this many bytes */ unsigned flags); /* (currently unused) */ extern caddr_t -xtalk_pio_addr (devfs_handle_t dev, /* translate for this device */ +xtalk_pio_addr (vertex_hdl_t dev, /* translate for this device */ device_desc_t dev_desc, /* device descriptor */ iopaddr_t xtalk_addr, /* Crosstalk address */ size_t byte_count, /* map this many bytes */ @@ -122,7 +125,7 @@ xtalk_pio_addr (devfs_handle_t dev, /* translate for this device */ typedef struct xtalk_dmamap_s *xtalk_dmamap_t; typedef xtalk_dmamap_t -xtalk_dmamap_alloc_f (devfs_handle_t dev, /* set up mappings for this device */ +xtalk_dmamap_alloc_f (vertex_hdl_t dev, /* set up mappings for this device */ device_desc_t dev_desc, /* device descriptor */ size_t byte_count_max, /* max size of a mapping */ unsigned flags); /* defined in dma.h */ @@ -144,14 +147,14 @@ typedef void xtalk_dmamap_done_f (xtalk_dmamap_t dmamap); typedef iopaddr_t -xtalk_dmatrans_addr_f (devfs_handle_t dev, /* translate for this device */ +xtalk_dmatrans_addr_f (vertex_hdl_t dev, /* translate for this device */ device_desc_t dev_desc, /* device descriptor */ paddr_t paddr, /* system physical address */ size_t byte_count, /* length */ unsigned flags); typedef alenlist_t -xtalk_dmatrans_list_f (devfs_handle_t dev, /* translate for this device */ +xtalk_dmatrans_list_f (vertex_hdl_t dev, /* translate for this device */ device_desc_t dev_desc, /* device descriptor */ alenlist_t palenlist, /* system address/length list */ unsigned flags); @@ -160,12 +163,12 @@ typedef void xtalk_dmamap_drain_f (xtalk_dmamap_t map); /* drain this map's channel */ typedef void -xtalk_dmaaddr_drain_f (devfs_handle_t vhdl, /* drain channel from this device */ +xtalk_dmaaddr_drain_f (vertex_hdl_t vhdl, /* drain channel from this device */ paddr_t addr, /* to this physical address */ size_t bytes); /* for this many bytes */ typedef void -xtalk_dmalist_drain_f (devfs_handle_t vhdl, /* drain channel from this device */ +xtalk_dmalist_drain_f (vertex_hdl_t vhdl, /* drain channel from this device */ alenlist_t list); /* for this set of physical blocks */ @@ -196,54 +199,47 @@ typedef int xtalk_intr_setfunc_f (xtalk_intr_t intr_hdl); /* interrupt handle */ typedef xtalk_intr_t -xtalk_intr_alloc_f (devfs_handle_t dev, /* which crosstalk device */ +xtalk_intr_alloc_f (vertex_hdl_t dev, /* which crosstalk device */ device_desc_t dev_desc, /* device descriptor */ - devfs_handle_t owner_dev); /* owner of this intr */ + vertex_hdl_t owner_dev); /* owner of this intr */ typedef void xtalk_intr_free_f (xtalk_intr_t intr_hdl); -#ifdef CONFIG_IA64_SGI_SN1 -typedef int -xtalk_intr_connect_f (xtalk_intr_t intr_hdl, /* xtalk intr resource handle */ - xtalk_intr_setfunc_f *setfunc, /* func to set intr hw */ - void *setfunc_arg); /* arg to setfunc */ -#else typedef int xtalk_intr_connect_f (xtalk_intr_t intr_hdl, /* xtalk intr resource handle */ intr_func_t intr_func, /* xtalk intr handler */ void *intr_arg, /* arg to intr handler */ xtalk_intr_setfunc_f *setfunc, /* func to set intr hw */ void *setfunc_arg); /* arg to setfunc */ -#endif typedef void xtalk_intr_disconnect_f (xtalk_intr_t intr_hdl); -typedef devfs_handle_t +typedef vertex_hdl_t xtalk_intr_cpu_get_f (xtalk_intr_t intr_hdl); /* xtalk intr resource handle */ /* CONFIGURATION MANAGEMENT */ typedef void -xtalk_provider_startup_f (devfs_handle_t xtalk_provider); +xtalk_provider_startup_f (vertex_hdl_t xtalk_provider); typedef void -xtalk_provider_shutdown_f (devfs_handle_t xtalk_provider); +xtalk_provider_shutdown_f (vertex_hdl_t xtalk_provider); typedef void -xtalk_widgetdev_enable_f (devfs_handle_t, int); +xtalk_widgetdev_enable_f (vertex_hdl_t, int); typedef void -xtalk_widgetdev_shutdown_f (devfs_handle_t, int); +xtalk_widgetdev_shutdown_f (vertex_hdl_t, int); typedef int -xtalk_dma_enabled_f (devfs_handle_t); +xtalk_dma_enabled_f (vertex_hdl_t); /* Error Management */ typedef int -xtalk_error_devenable_f (devfs_handle_t xconn_vhdl, +xtalk_error_devenable_f (vertex_hdl_t xconn_vhdl, int devnum, int error_code); @@ -285,7 +281,6 @@ typedef struct xtalk_provider_s { xtalk_intr_free_f *intr_free; xtalk_intr_connect_f *intr_connect; xtalk_intr_disconnect_f *intr_disconnect; - xtalk_intr_cpu_get_f *intr_cpu_get; /* CONFIGURATION MANAGEMENT */ xtalk_provider_startup_f *provider_startup; @@ -327,7 +322,7 @@ extern xtalk_early_piotrans_addr_f xtalk_early_piotrans_addr; /* error management */ -extern int xtalk_error_handler(devfs_handle_t, +extern int xtalk_error_handler(vertex_hdl_t, int, ioerror_mode_t, ioerror_t *); @@ -341,33 +336,33 @@ typedef unchar xtalk_intr_vector_t; /* crosstalk interrupt vector (0..255) */ #define XTALK_INTR_VECTOR_NONE (xtalk_intr_vector_t)0 /* Generic crosstalk interrupt interfaces */ -extern devfs_handle_t xtalk_intr_dev_get(xtalk_intr_t xtalk_intr); +extern vertex_hdl_t xtalk_intr_dev_get(xtalk_intr_t xtalk_intr); extern xwidgetnum_t xtalk_intr_target_get(xtalk_intr_t xtalk_intr); extern xtalk_intr_vector_t xtalk_intr_vector_get(xtalk_intr_t xtalk_intr); extern iopaddr_t xtalk_intr_addr_get(xtalk_intr_t xtalk_intr); -extern devfs_handle_t xtalk_intr_cpu_get(xtalk_intr_t xtalk_intr); +extern vertex_hdl_t xtalk_intr_cpu_get(xtalk_intr_t xtalk_intr); extern void *xtalk_intr_sfarg_get(xtalk_intr_t xtalk_intr); /* Generic crosstalk pio interfaces */ -extern devfs_handle_t xtalk_pio_dev_get(xtalk_piomap_t xtalk_piomap); +extern vertex_hdl_t xtalk_pio_dev_get(xtalk_piomap_t xtalk_piomap); extern xwidgetnum_t xtalk_pio_target_get(xtalk_piomap_t xtalk_piomap); extern iopaddr_t xtalk_pio_xtalk_addr_get(xtalk_piomap_t xtalk_piomap); extern size_t xtalk_pio_mapsz_get(xtalk_piomap_t xtalk_piomap); extern caddr_t xtalk_pio_kvaddr_get(xtalk_piomap_t xtalk_piomap); /* Generic crosstalk dma interfaces */ -extern devfs_handle_t xtalk_dma_dev_get(xtalk_dmamap_t xtalk_dmamap); +extern vertex_hdl_t xtalk_dma_dev_get(xtalk_dmamap_t xtalk_dmamap); extern xwidgetnum_t xtalk_dma_target_get(xtalk_dmamap_t xtalk_dmamap); /* Register/unregister Crosstalk providers and get implementation handle */ extern void xtalk_set_early_piotrans_addr(xtalk_early_piotrans_addr_f *); -extern void xtalk_provider_register(devfs_handle_t provider, xtalk_provider_t *xtalk_fns); -extern void xtalk_provider_unregister(devfs_handle_t provider); -extern xtalk_provider_t *xtalk_provider_fns_get(devfs_handle_t provider); +extern void xtalk_provider_register(vertex_hdl_t provider, xtalk_provider_t *xtalk_fns); +extern void xtalk_provider_unregister(vertex_hdl_t provider); +extern xtalk_provider_t *xtalk_provider_fns_get(vertex_hdl_t provider); /* Crosstalk Switch generic layer, for use by initialization code */ -extern void xswitch_census(devfs_handle_t xswitchv); -extern void xswitch_init_widgets(devfs_handle_t xswitchv); +extern void xswitch_census(vertex_hdl_t xswitchv); +extern void xswitch_init_widgets(vertex_hdl_t xswitchv); /* early init interrupt management */ @@ -397,7 +392,7 @@ xtalk_intr_preconn_f (void *which_xtalk, typedef xtalk_intr_setfunc_f *xtalk_intr_setfunc_t; -typedef void xtalk_iter_f(devfs_handle_t vhdl); +typedef void xtalk_iter_f(vertex_hdl_t vhdl); extern void xtalk_iterate(char *prefix, xtalk_iter_f *func); diff --git a/include/asm-ia64/sn/xtalk/xtalk_private.h b/include/asm-ia64/sn/xtalk/xtalk_private.h index 4f5fcd4301191..cfa029d0fe4c3 100644 --- a/include/asm-ia64/sn/xtalk/xtalk_private.h +++ b/include/asm-ia64/sn/xtalk/xtalk_private.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_XTALK_XTALK_PRIVATE_H #define _ASM_SN_XTALK_XTALK_PRIVATE_H @@ -23,7 +23,7 @@ * All Crosstalk providers set up PIO using this information. */ struct xtalk_piomap_s { - devfs_handle_t xp_dev; /* a requestor of this mapping */ + vertex_hdl_t xp_dev; /* a requestor of this mapping */ xwidgetnum_t xp_target; /* target (node's widget number) */ iopaddr_t xp_xtalk_addr; /* which crosstalk addr is mapped */ size_t xp_mapsz; /* size of this mapping */ @@ -34,7 +34,7 @@ struct xtalk_piomap_s { * All Crosstalk providers set up DMA using this information. */ struct xtalk_dmamap_s { - devfs_handle_t xd_dev; /* a requestor of this mapping */ + vertex_hdl_t xd_dev; /* a requestor of this mapping */ xwidgetnum_t xd_target; /* target (node's widget number) */ }; @@ -42,7 +42,7 @@ struct xtalk_dmamap_s { * All Crosstalk providers set up interrupts using this information. */ struct xtalk_intr_s { - devfs_handle_t xi_dev; /* requestor of this intr */ + vertex_hdl_t xi_dev; /* requestor of this intr */ xwidgetnum_t xi_target; /* master's widget number */ xtalk_intr_vector_t xi_vector; /* 8-bit interrupt vector */ iopaddr_t xi_addr; /* xtalk address to generate intr */ @@ -72,10 +72,10 @@ struct xtalk_intr_s { */ struct xwidget_info_s { char *w_fingerprint; - devfs_handle_t w_vertex; /* back pointer to vertex */ + vertex_hdl_t w_vertex; /* back pointer to vertex */ xwidgetnum_t w_id; /* widget id */ struct xwidget_hwid_s w_hwid; /* hardware identification (part/rev/mfg) */ - devfs_handle_t w_master; /* CACHED widget's master */ + vertex_hdl_t w_master; /* CACHED widget's master */ xwidgetnum_t w_masterid; /* CACHED widget's master's widgetnum */ error_handler_f *w_efunc; /* error handling function */ error_handler_arg_t w_einfo; /* first parameter for efunc */ diff --git a/include/asm-ia64/sn/xtalk/xtalkaddrs.h b/include/asm-ia64/sn/xtalk/xtalkaddrs.h index 0f2069c900076..2528b00a4ea37 100644 --- a/include/asm-ia64/sn/xtalk/xtalkaddrs.h +++ b/include/asm-ia64/sn/xtalk/xtalkaddrs.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_XTALK_XTALKADDRS_H #define _ASM_SN_XTALK_XTALKADDRS_H diff --git a/include/asm-ia64/sn/xtalk/xwidget.h b/include/asm-ia64/sn/xtalk/xwidget.h index bea83bb83ba01..a49b9425a3d86 100644 --- a/include/asm-ia64/sn/xtalk/xwidget.h +++ b/include/asm-ia64/sn/xtalk/xwidget.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef __ASM_SN_XTALK_XWIDGET_H__ #define __ASM_SN_XTALK_XWIDGET_H__ @@ -261,27 +260,26 @@ extern int xwidget_driver_register(xwidget_part_num_t part_num, extern void xwidget_driver_unregister(char *driver_prefix); extern int xwidget_register(struct xwidget_hwid_s *hwid, - devfs_handle_t dev, + vertex_hdl_t dev, xwidgetnum_t id, - devfs_handle_t master, - xwidgetnum_t targetid, - async_attach_t aa); + vertex_hdl_t master, + xwidgetnum_t targetid); -extern int xwidget_unregister(devfs_handle_t); +extern int xwidget_unregister(vertex_hdl_t); -extern void xwidget_reset(devfs_handle_t xwidget); -extern void xwidget_gfx_reset(devfs_handle_t xwidget); -extern char *xwidget_name_get(devfs_handle_t xwidget); +extern void xwidget_reset(vertex_hdl_t xwidget); +extern void xwidget_gfx_reset(vertex_hdl_t xwidget); +extern char *xwidget_name_get(vertex_hdl_t xwidget); /* Generic crosstalk widget information access interface */ -extern xwidget_info_t xwidget_info_chk(devfs_handle_t widget); -extern xwidget_info_t xwidget_info_get(devfs_handle_t widget); -extern void xwidget_info_set(devfs_handle_t widget, xwidget_info_t widget_info); -extern devfs_handle_t xwidget_info_dev_get(xwidget_info_t xwidget_info); +extern xwidget_info_t xwidget_info_chk(vertex_hdl_t widget); +extern xwidget_info_t xwidget_info_get(vertex_hdl_t widget); +extern void xwidget_info_set(vertex_hdl_t widget, xwidget_info_t widget_info); +extern vertex_hdl_t xwidget_info_dev_get(xwidget_info_t xwidget_info); extern xwidgetnum_t xwidget_info_id_get(xwidget_info_t xwidget_info); extern int xwidget_info_type_get(xwidget_info_t xwidget_info); extern int xwidget_info_state_get(xwidget_info_t xwidget_info); -extern devfs_handle_t xwidget_info_master_get(xwidget_info_t xwidget_info); +extern vertex_hdl_t xwidget_info_master_get(xwidget_info_t xwidget_info); extern xwidgetnum_t xwidget_info_masterid_get(xwidget_info_t xwidget_info); extern xwidget_part_num_t xwidget_info_part_num_get(xwidget_info_t xwidget_info); extern xwidget_rev_num_t xwidget_info_rev_num_get(xwidget_info_t xwidget_info); |