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authorHai Nguyen Pham <hai.pham.ud@renesas.com>2019-03-08 16:12:53 +0700
committerRyo Kataoka <ryo.kataoka.wt@renesas.com>2019-03-22 20:50:41 +0900
commit32a18bd7115e72735d7db0ff1e33a0042d586765 (patch)
treeeda96f381c576159b4c0b72e3829546062100c77
parent0e9229ea60ac32cbed06910e8677b66c0e6553a3 (diff)
downloadrenesas-bsp-32a18bd7115e72735d7db0ff1e33a0042d586765.tar.gz
Revert "arm64: dts: renesas: r8a77965: Attach the SYS-DMAC to the IPMMU"
This reverts commit fee499aca1b44e5a2f7d6937ab0f42afdee5a8dc to keep IPMMU address translation for SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 is disabled by default. Signed-off-by: Hai Nguyen Pham <hai.pham.ud@renesas.com>
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77965.dtsi24
1 files changed, 0 insertions, 24 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index b10de67b01757..11c89fe3e6865 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -750,14 +750,6 @@
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <16>;
- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
};
dmac1: dma-controller@e7300000 {
@@ -792,14 +784,6 @@
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <16>;
- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
};
dmac2: dma-controller@e7310000 {
@@ -834,14 +818,6 @@
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <16>;
- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
};
ipmmu_mm: mmu@e67b0000 {