3.0 patches

4 files changed, 126 insertions, 0 deletions

diff --git a/queue-3.0/arm-7014-1-cache-l2x0-fix-l2-cache-size-calculation.patch b/queue-3.0/arm-7014-1-cache-l2x0-fix-l2-cache-size-calculation.patch
new file mode 100644
index 0000000000..f7b3cb0956
--- /dev/null
+++ b/queue-3.0/arm-7014-1-cache-l2x0-fix-l2-cache-size-calculation.patch
@@ -0,0 +1,41 @@
+From 43c734be5571a4daad9f0a3e0b3229a1c0049917 Mon Sep 17 00:00:00 2001
+From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+Date: Mon, 15 Aug 2011 10:43:44 +0100
+Subject: ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.
+
+From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+
+commit 43c734be5571a4daad9f0a3e0b3229a1c0049917 upstream.
+
+This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and
+PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3
+bits.
+
+The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits
+[19:17] for Way size, however the existing code only uses 2 bits to
+get this value. This results in incorrect cachesize calculations.
+
+It also results in performing operations on the whole cache when we
+erroneously decide that the range is big enough (due to l2x0_size being
+too small) and also prints incorrect cachesize.
+
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+Acked-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ arch/arm/include/asm/hardware/cache-l2x0.h |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/include/asm/hardware/cache-l2x0.h
++++ b/arch/arm/include/asm/hardware/cache-l2x0.h
+@@ -64,7 +64,7 @@
+ #define L2X0_AUX_CTRL_MASK			0xc0000fff
+ #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT	16
+ #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT		17
+-#define L2X0_AUX_CTRL_WAY_SIZE_MASK		(0x3 << 17)
++#define L2X0_AUX_CTRL_WAY_SIZE_MASK		(0x7 << 17)
+ #define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT	22
+ #define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT		26
+ #define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT		27
diff --git a/queue-3.0/drm-radeon-kms-add-s-r-quirk-for-compaq-presario-v5245eu.patch b/queue-3.0/drm-radeon-kms-add-s-r-quirk-for-compaq-presario-v5245eu.patch
new file mode 100644
index 0000000000..966cf2da4c
--- /dev/null
+++ b/queue-3.0/drm-radeon-kms-add-s-r-quirk-for-compaq-presario-v5245eu.patch
@@ -0,0 +1,39 @@
+From 302a8e8b06d312dcb3b718dfeb42aa912b5f426b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 29 Aug 2011 14:55:25 +0000
+Subject: drm/radeon/kms: add s/r quirk for Compaq Presario V5245EU
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 302a8e8b06d312dcb3b718dfeb42aa912b5f426b upstream.
+
+Fixes resume on Compaq Presario V5245EU.
+
+Fixes:
+https://bugzilla.kernel.org/show_bug.cgi?id=41642
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/radeon_combios.c |    8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/radeon_combios.c
++++ b/drivers/gpu/drm/radeon/radeon_combios.c
+@@ -3279,6 +3279,14 @@ void radeon_combios_asic_init(struct drm
+ 	    rdev->pdev->subsystem_device == 0x30a4)
+ 		return;
+ 
++	/* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
++	 * - it hangs on resume inside the dynclk 1 table.
++	 */
++	if (rdev->family == CHIP_RS480 &&
++	    rdev->pdev->subsystem_vendor == 0x103c &&
++	    rdev->pdev->subsystem_device == 0x30ae)
++		return;
++
+ 	/* DYN CLK 1 */
+ 	table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
+ 	if (table)
diff --git a/queue-3.0/drm-radeon-kms-evergreen-ni-reset-spi-block-on-cp-resume.patch b/queue-3.0/drm-radeon-kms-evergreen-ni-reset-spi-block-on-cp-resume.patch
new file mode 100644
index 0000000000..72d2019e0b
--- /dev/null
+++ b/queue-3.0/drm-radeon-kms-evergreen-ni-reset-spi-block-on-cp-resume.patch
@@ -0,0 +1,43 @@
+From a49a50dad48586d42ebac1a6730c3a3cd5603421 Mon Sep 17 00:00:00 2001
+From: Jerome Glisse <jglisse@redhat.com>
+Date: Wed, 24 Aug 2011 20:00:17 +0000
+Subject: drm/radeon/kms: evergreen & ni reset SPI block on CP resume
+
+From: Jerome Glisse <jglisse@redhat.com>
+
+commit a49a50dad48586d42ebac1a6730c3a3cd5603421 upstream.
+
+For some reason SPI block is in broken state after module
+unloading. This lead to broken rendering after reloading
+module. Fix this by reseting SPI block in CP resume function
+
+Signed-off-by: Jerome Glisse <jglisse@redhat.com
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/evergreen.c |    1 +
+ drivers/gpu/drm/radeon/ni.c        |    1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -1357,6 +1357,7 @@ int evergreen_cp_resume(struct radeon_de
+ 				 SOFT_RESET_PA |
+ 				 SOFT_RESET_SH |
+ 				 SOFT_RESET_VGT |
++				 SOFT_RESET_SPI |
+ 				 SOFT_RESET_SX));
+ 	RREG32(GRBM_SOFT_RESET);
+ 	mdelay(15);
+--- a/drivers/gpu/drm/radeon/ni.c
++++ b/drivers/gpu/drm/radeon/ni.c
+@@ -1158,6 +1158,7 @@ int cayman_cp_resume(struct radeon_devic
+ 				 SOFT_RESET_PA |
+ 				 SOFT_RESET_SH |
+ 				 SOFT_RESET_VGT |
++				 SOFT_RESET_SPI |
+ 				 SOFT_RESET_SX));
+ 	RREG32(GRBM_SOFT_RESET);
+ 	mdelay(15);
diff --git a/queue-3.0/series b/queue-3.0/series
index 0021890e36..14bccb2ad0 100644
--- a/queue-3.0/series
+++ b/queue-3.0/series
@@ -45,3 +45,6 @@ sparc-fix-array-bounds-error-setting-up-pcic-nmi-trap.patch
 sparc32-sun4d-change-ipi-irq-level-to-prevent-collision.patch
 regulator-tps65910-add-missing-breaks-in-switch-case.patch
 sparc64-only-panther-cheetah-chips-have-popc.patch
+drm-radeon-kms-add-s-r-quirk-for-compaq-presario-v5245eu.patch
+drm-radeon-kms-evergreen-ni-reset-spi-block-on-cp-resume.patch
+arm-7014-1-cache-l2x0-fix-l2-cache-size-calculation.patch