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path: root/drivers/cxl/cxl.h
AgeCommit message (Expand)AuthorFilesLines
2024-05-01cxl/acpi: Cleanup __cxl_parse_cfmws()Dan Williams1-0/+5
2024-04-30cxl: Fix compile warning for cxl_security_ops externDave Jiang1-0/+2
2024-04-08cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coordDave Jiang1-4/+2
2024-04-08cxl: Fix incorrect region perf data calculationDave Jiang1-2/+0
2024-03-12cxl/region: Add memory hotplug notifier for cxl regionDave Jiang1-0/+3
2024-03-12cxl/region: Calculate performance data for a regionDave Jiang1-0/+4
2024-03-12cxl: Split out host bridge access coordinatesDave Jiang1-0/+2
2024-03-12cxl: Split out combine_coordinates() for common shared usageDave Jiang1-0/+4
2024-03-12ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access c...Dave Jiang1-1/+1
2024-02-16cxl: Fix sysfs export of qos_class for memdevDave Jiang1-0/+2
2024-01-05Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams1-2/+0
2024-01-05cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang1-7/+7
2024-01-05cxl: Introduce put_cxl_root() helperDave Jiang1-0/+3
2024-01-04cxl/port: Fix missing target list lockDan Williams1-2/+0
2023-12-22cxl: Add helper function that calculate performance data for downstream portsDave Jiang1-0/+3
2023-12-22cxl: Store the access coordinates for the generic portsDave Jiang1-0/+2
2023-12-22cxl: Calculate and store PCI link latency for the downstream portsDave Jiang1-0/+4
2023-12-22cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang1-0/+25
2023-12-22cxl: Add callback to parse the SSLBIS subtable from CDATDave Jiang1-0/+4
2023-12-22cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang1-0/+2
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams1-0/+1
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams1-0/+3
2023-10-27cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang1-0/+3
2023-10-27cxl: Add cxl_decoders_committed() helperDave Jiang1-0/+1
2023-10-27cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmRobert Richter1-2/+1
2023-10-27cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman1-0/+10
2023-10-27cxl/pci: Add RCH downstream port AER register discoveryRobert Richter1-0/+7
2023-10-27cxl/port: Remove Component Register base address from struct cxl_portRobert Richter1-2/+0
2023-10-27cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter1-4/+4
2023-10-27cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter1-2/+2
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-25/+32
2023-06-25Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams1-0/+16
2023-06-25Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxlDan Williams1-7/+9
2023-06-25Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams1-6/+5
2023-06-25Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams1-1/+0
2023-06-25cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEMDan Williams1-1/+1
2023-06-25cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams1-2/+2
2023-06-25cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams1-2/+2
2023-06-25cxl/region: Flag partially torn down regions as unusableDan Williams1-0/+8
2023-06-25cxl/region: Move cache invalidation before region teardown, and before setupDan Williams1-7/+1
2023-06-25cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter1-0/+2
2023-06-25cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter1-0/+2
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter1-0/+2
2023-06-25cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter1-2/+0
2023-06-25cxl/pci: Refactor component register discovery for reuseTerry Bowman1-0/+1
2023-06-25cxl/core/regs: Add @dev to cxl_register_mapRobert Richter1-4/+6
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams1-6/+7
2023-06-25cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter1-2/+2
2023-06-25cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams1-2/+7
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter1-9/+3
2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron1-0/+13
2023-05-30cxl: Add functions to get an instance of / count regblocks of a given typeJonathan Cameron1-0/+3
2023-05-23cxl/mbox: Add background cmd handling machineryDavidlohr Bueso1-0/+8
2023-05-18cxl/port: Enable the HDM decoder capability for switch portsDan Williams1-0/+1
2023-04-04cxl/port: Fix find_cxl_root() for RCDs and simplify itDan Williams1-2/+2
2023-04-04cxl/hdm: Skip emulation when driver manages mem_enableDan Williams1-1/+3
2023-02-25Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds1-2/+94
2023-02-14Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams1-2/+18
2023-02-14cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang1-1/+2
2023-02-14cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang1-1/+2
2023-02-14cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang1-0/+14
2023-02-14Merge branch 'for-6.3/cxl' into cxl/nextDan Williams1-0/+1
2023-02-14cxl: add RAS status unmasking for CXLDave Jiang1-0/+1
2023-02-10Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams1-0/+57
2023-02-10cxl/dax: Create dax devices for CXL RAM regionsDan Williams1-0/+12
2023-02-10tools/testing/cxl: Define a fixed volatile configuration to parseDan Williams1-0/+2
2023-02-10cxl/region: Add region autodiscoveryDan Williams1-0/+29
2023-02-10cxl/region: Add a mode attribute for regionsDan Williams1-0/+14
2023-01-27driver core: make struct bus_type.uevent() take a const *Greg Kroah-Hartman1-2/+2
2023-01-26cxl/mem: Wire up event interruptsDavidlohr Bueso1-0/+4
2023-01-26cxl/mem: Read, trace, and clear events on driver loadIra Weiny1-0/+12
2023-01-04cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams1-0/+2
2022-12-05cxl: update names for interleave ways conversion macrosDave Jiang1-7/+7
2022-12-05cxl: update names for interleave granularity conversion macrosDave Jiang1-6/+7
2022-12-05Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams1-2/+9
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams1-9/+29
2022-12-05Merge branch 'for-6.2/cxl-security' into for-6.2/cxlDan Williams1-0/+11
2022-12-05cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_memDan Williams1-2/+0
2022-12-03cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield1-2/+9
2022-12-03cxl/pci: Add (hopeful) error handling supportDan Williams1-0/+1
2022-12-03cxl/pci: Find and map the RAS Capability StructureDan Williams1-0/+19
2022-12-03cxl/pci: Prepare for mapping RAS Capability StructureDan Williams1-1/+3
2022-12-03cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams1-8/+6
2022-12-03cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter1-0/+16
2022-12-03cxl/region: Manage CPU caches relative to DPA invalidation eventsDan Williams1-0/+8
2022-12-02cxl: add dimm_id support for __nvdimm_create()Dave Jiang1-0/+3
2022-12-02cxl/acpi: Move rescan to the workqueueDan Williams1-1/+2
2022-12-02cxl/pmem: Remove the cxl_pmem_wq and related infrastructureDan Williams1-17/+0
2022-12-02cxl/pmem: Refactor nvdimm device registration, delete the workqueueDan Williams1-2/+5
2022-12-02cxl/region: Drop redundant pmem region release handlingDan Williams1-1/+0
2022-11-14cxl: Replace HDM decoder granularity magic numbersAdam Manzanares1-4/+7
2022-11-14cxl/core: Remove duplicate declaration of devm_cxl_iomap_block()Robert Richter1-2/+0
2022-11-04cxl/region: Fix 'distance' calculation with passthrough portsDan Williams1-0/+2
2022-11-04cxl/pmem: Fix cxl_pmem_region and cxl_memdev leakDan Williams1-1/+1
2022-08-05cxl/region: describe targets and nr_targets members of cxl_region_paramsBagas Sanjaya1-0/+2
2022-08-01cxl/acpi: Minimize granularity for x1 interleavesDan Williams1-0/+2
2022-08-01cxl/region: prevent underflow in ways_to_cxl()Dan Carpenter1-1/+1
2022-07-26cxl/region: Introduce cxl_pmem_region objectsDan Williams1-1/+35
2022-07-26cxl/pmem: Fix offline_nvdimm_bus() to offline by bridgeDan Williams1-0/+1
2022-07-26cxl/region: Add region driver boiler plateDan Williams1-0/+1
2022-07-25cxl/hdm: Commit decoder state to hardwareDan Williams1-1/+12
2022-07-25cxl/region: Program target listsDan Williams1-0/+2
2022-07-25cxl/region: Attach endpoint decodersDan Williams1-0/+20
2022-07-25cxl/acpi: Add a host-bridge index lookup mechanismDan Williams1-0/+2
2022-07-25cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams1-0/+11
2022-07-25cxl/region: Allocate HPA capacity to regionsDan Williams1-0/+2
2022-07-25cxl/region: Add interleave geometry attributesBen Widawsky1-0/+33
2022-07-25cxl/region: Add a 'uuid' attributeBen Widawsky1-0/+25
2022-07-21cxl/region: Add region creation supportBen Widawsky1-0/+18
2022-07-21cxl/mem: Enumerate port targets before adding endpointsDan Williams1-0/+5
2022-07-21cxl/port: Move dport tracking to an xarrayDan Williams1-5/+7
2022-07-21cxl/port: Move 'cxl_ep' references to an xarray per portDan Williams1-3/+1
2022-07-21cxl/port: Record parent dport when adding portsDan Williams1-2/+5
2022-07-21cxl/port: Record dport in endpoint referencesDan Williams1-0/+2
2022-07-21cxl/hdm: Track next decoder to allocateDan Williams1-0/+2
2022-07-21cxl/hdm: Add 'mode' attribute to decoder objectsDan Williams1-0/+9
2022-07-21cxl/hdm: Enumerate allocated DPADan Williams1-0/+2
2022-07-21cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams1-1/+14
2022-07-21cxl/core: Define a 'struct cxl_root_decoder'Dan Williams1-2/+13
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams1-8/+22
2022-07-19cxl/port: Read CDAT tableIra Weiny1-0/+7
2022-07-11cxl/pmem: Delete unused nvdimm attributeDan Williams1-1/+0
2022-07-10cxl/port: Cache CXL host bridge dataDan Williams1-0/+2
2022-07-09cxl: Introduce cxl_to_{ways,granularity}Dan Williams1-0/+26
2022-07-09cxl/core: Drop is_cxl_decoder()Dan Williams1-1/+0
2022-07-09cxl/core: Drop ->platform_res attribute for root decodersDan Williams1-5/+1
2022-07-09cxl/core: Rename ->decoder_range ->hpa_rangeDan Williams1-2/+2
2022-06-21cxl/core: Use is_endpoint_decoderBen Widawsky1-0/+1
2022-04-28cxl: Drop cxl_device_lock()Dan Williams1-78/+0
2022-02-08cxl/core/port: Add endpoint decodersBen Widawsky1-0/+1
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky1-0/+6
2022-02-08cxl/core/port: Add switch port enumerationDan Williams1-0/+19
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams1-4/+4
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky1-0/+4
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams1-6/+27
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams1-12/+4
2022-02-08cxl/pmem: Introduce a find_cxl_root() helperDan Williams1-0/+1
2022-02-08cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams1-0/+3
2022-02-08cxl/core/port: Use dedicated lock for decoder target listDan Williams1-0/+2
2022-02-08cxl: Prove CXL lockingDan Williams1-0/+81
2022-02-08cxl/core: Track port depthBen Widawsky1-0/+2
2022-02-08cxl/core/port: Clarify decoder creationBen Widawsky1-1/+15
2022-02-08cxl/core: Convert decoder range to resourceBen Widawsky1-2/+6
2022-02-08cxl: Introduce module_cxl_driverBen Widawsky1-0/+3
2022-02-08cxl/acpi: Map component registers for Root PortsBen Widawsky1-0/+4
2022-01-04cxl/core: Remove cxld_const_init in cxl_decoder_alloc()Nathan Chancellor1-1/+1
2021-11-15cxl/pmem: Fix module reload vs workqueue stateDan Williams1-0/+8
2021-11-08Merge tag 'cxl-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds1-19/+39
2021-10-29cxl/pci: Add @base to cxl_register_mapDan Williams1-0/+10
2021-09-25cxl/core: Replace unions with struct_group()Kees Cook1-43/+18
2021-09-21cxl/core: Split decoder setup into alloc + addDan Williams1-9/+6
2021-09-21tools/testing/cxl: Introduce a mock memory device + driverDan Williams1-1/+1
2021-09-21cxl/bus: Populate the target list at decoder createDan Williams1-15/+10
2021-09-21tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams1-0/+16
2021-09-21cxl/pmem: Add support for multiple nvdimm-bridge objectsDan Williams1-0/+2
2021-08-06cxl/pci: Simplify register setupBen Widawsky1-1/+0
2021-06-15cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams1-1/+11
2021-06-15cxl/pmem: Add initial infrastructure for pmem supportDan Williams1-0/+24
2021-06-15cxl/core: Add cxl-bus driver infrastructureDan Williams1-0/+22
2021-06-12cxl/hdm: Fix decoder count calculationBen Widawsky1-0/+7
2021-06-09cxl/acpi: Introduce cxl_decoder objectsDan Williams1-0/+63
2021-06-09cxl/acpi: Add downstream port data to cxl_port instancesDan Williams1-0/+21
2021-06-09cxl/acpi: Introduce the root of a cxl_port topologyDan Williams1-0/+31
2021-06-05cxl/pci: Add HDM decoder capabilitiesBen Widawsky1-6/+59
2021-06-05cxl/pci: Map registers based on capabilitiesIra Weiny1-5/+28
2021-05-14cxl/core: Refactor CXL register lookup for bridge reuseDan Williams1-0/+3
2021-05-14cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devicesDan Williams1-0/+32
2021-05-14cxl/mem: Move some definitions to mem.hDan Williams1-57/+0
2021-02-16cxl/mem: Enable commands via CELBen Widawsky1-0/+2
2021-02-16cxl/mem: Register CXL memX devicesDan Williams1-0/+3
2021-02-16cxl/mem: Find device capabilitiesBen Widawsky1-0/+90
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-20 01:55:58 +0000