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9 dayscxl: Fix cxl_endpoint_get_perf_coordinate() support for RCHDave Jiang1-1/+14
2024-04-22cxl/core: Fix potential payload size confusion in cxl_mem_get_poison()Dan Williams1-21/+17
2024-04-11Merge tag 'cxl-fixes-6.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds7-141/+158
2024-04-08cxl: Add checks to access_coordinate calculation to fail missing dataDave Jiang1-1/+18
2024-04-08cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coordDave Jiang5-44/+88
2024-04-08cxl: Fix incorrect region perf data calculationDave Jiang4-100/+45
2024-04-08cxl: Fix retrieving of access_coordinates in PCIe pathDave Jiang1-13/+22
2024-04-05cxl: Remove checking of iter in cxl_endpoint_get_perf_coordinates()Dave Jiang1-1/+1
2024-04-03cxl/core: Fix initialization of mbox_cmd.size_out in get eventKwangjin Ko1-1/+2
2024-03-26cxl/core/regs: Fix usage of map->reg_type in cxl_decode_regblock() before ass...Dave Jiang1-2/+3
2024-03-26cxl/mem: Fix for the index of Clear Event Record HandleYuquan Wang1-1/+1
2024-03-27cxl: remove CONFIG_CXL_PMU entry in drivers/cxl/KconfigMasahiro Yamada1-13/+0
2024-03-18Merge tag 'trace-v6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tra...Linus Torvalds1-7/+7
2024-03-18cxl/trace: Properly initialize cxl_poison region nameAlison Schofield1-7/+7
2024-03-13Merge branch 'for-6.9/cxl-fixes' into for-6.9/cxlDan Williams1-15/+15
2024-03-13Merge branch 'for-6.9/cxl-einj' into for-6.9/cxlDan Williams1-0/+41
2024-03-13Merge branch 'for-6.9/cxl-qos' into for-6.9/cxlDan Williams6-33/+342
2024-03-13lib/firmware_table: Provide buffer length argument to cdat_table_parse()Robert Richter2-4/+10
2024-03-12cxl/pci: Get rid of pointer arithmetic reading CDAT tableRobert Richter2-36/+65
2024-03-12cxl/pci: Rename DOE mailbox handle to doe_mbRobert Richter1-10/+10
2024-03-12cxl: Fix the incorrect assignment of SSLBIS entry pointer initial locationDave Jiang1-15/+15
2024-03-12cxl/core: Add CXL EINJ debugfs filesBen Cheatham1-0/+41
2024-03-12cxl/region: Deal with numa nodes not enumerated by SRATDave Jiang3-1/+12
2024-03-12cxl/region: Add memory hotplug notifier for cxl regionDave Jiang4-0/+80
2024-03-12cxl/region: Add sysfs attribute for locality attributes of CXL regionsDave Jiang1-0/+94
2024-03-12cxl/region: Calculate performance data for a regionDave Jiang3-0/+71
2024-03-12cxl: Set cxlmd->endpoint before adding port deviceDave Jiang1-1/+1
2024-03-12cxl: Move QoS class to be calculated from the nearest CPUDave Jiang1-3/+3
2024-03-12cxl: Split out host bridge access coordinatesDave Jiang3-9/+56
2024-03-12cxl: Split out combine_coordinates() for common shared usageDave Jiang3-25/+29
2024-03-12ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access c...Dave Jiang3-5/+7
2024-02-20cxl/acpi: Fix load failures due to single window creation failureDan Williams1-18/+28
2024-02-20Merge branch 'for-6.8/cxl-cper' into for-6.8/cxlDan Williams2-59/+4
2024-02-20acpi/ghes: Remove CXL CPER notificationsDan Williams1-56/+1
2024-02-16cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS windowRobert Richter1-3/+3
2024-02-16cxl: Fix sysfs export of qos_class for memdevDave Jiang4-36/+66
2024-02-16cxl: Remove unnecessary type cast in cxl_qos_class_verify()Dave Jiang1-2/+1
2024-02-16cxl: Change 'struct cxl_memdev_state' *_perf_list to single 'struct cxl_dpa_p...Dave Jiang4-90/+34
2024-02-16cxl/region: Allow out of order assembly of autodiscovered regionsAlison Schofield1-10/+38
2024-02-16cxl/region: Handle endpoint decoders in cxl_region_find_decoder()Alison Schofield1-6/+8
2024-02-09Merge tag 'efi-fixes-for-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds1-3/+3
2024-02-03cxl/trace: Remove unnecessary memcpy'sIra Weiny1-3/+3
2024-01-29cxl/pci: Skip to handle RAS errors if CXL.mem device is detachedLi Ming1-12/+31
2024-01-24cxl/region：Fix overflow issue in alloc_hpa()Quanquan Cao1-2/+2
2024-01-22cxl/pci: Skip irq features if MSI/MSI-X are not supportedIra Weiny1-11/+15
2024-01-12cxl/core: use sysfs_emit() for attr's _show()Shiyang Ruan1-1/+1
2024-01-09Merge branch 'for-6.8/cxl-cper' into for-6.8/cxlDan Williams4-138/+124
2024-01-09cxl/pci: Register for and process CPER eventsIra Weiny3-13/+89
2024-01-09cxl/events: Create a CXL event unionIra Weiny2-23/+17
2024-01-09cxl/events: Separate UUID from event structuresIra Weiny1-1/+1
2024-01-09cxl/events: Remove passing a UUID to known event tracesIra Weiny2-15/+19
2024-01-09cxl/events: Create common event UUID definesIra Weiny2-27/+27
2024-01-05Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams3-26/+14
2024-01-05Merge branch 'for-6.8/cxl-misc' into for-6.8/cxlDan Williams1-1/+1
2024-01-05Merge branch 'for-6.8/cxl-cdat' into for-6.8/cxlDan Williams6-27/+44
2024-01-05cxl/events: Promote CXL event structures to a core headerIra Weiny1-89/+1
2024-01-05cxl: Refactor to use __free() for cxl_root allocation in cxl_endpoint_port_pr...Dave Jiang1-3/+2
2024-01-05cxl: Refactor to use __free() for cxl_root allocation in cxl_find_nvdimm_brid...Dave Jiang1-5/+3
2024-01-05cxl: Fix device reference leak in cxl_port_perf_data_calculate()Dave Jiang1-2/+5
2024-01-05cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang6-23/+28
2024-01-05cxl: Introduce put_cxl_root() helperDave Jiang2-0/+12
2024-01-04cxl/port: Fix missing target list lockDan Williams2-17/+7
2024-01-04cxl/port: Fix decoder initialization when nr_targets > interleave_waysHuang Ying1-1/+1
2024-01-03cxl/region: fix x9 interleave typoJim Harris1-1/+1
2024-01-03cxl/trace: Pass UUID explicitly to event tracesIra Weiny2-18/+18
2024-01-02Merge branch 'for-6.8/cxl-cdat' into for-6.8/cxlDan Williams17-39/+1009
2024-01-02cxl/region: use %pap format to print resource_size_tRandy Dunlap1-2/+2
2023-12-24cxl/region: Add dev_dbg() detail on failure to allocate HPA spaceAlison Schofield1-2/+3
2023-12-22cxl: Check qos_class validity on memdev probeDave Jiang1-0/+103
2023-12-22cxl: Export sysfs attributes for memory device QoS classDave Jiang1-6/+61
2023-12-22cxl: Store QTG IDs and related info to the CXL memory device contextDave Jiang3-0/+92
2023-12-22cxl: Compute the entire CXL path latency and bandwidth dataDave Jiang1-1/+58
2023-12-22cxl: Add helper function that calculate performance data for downstream portsDave Jiang2-0/+78
2023-12-22cxl: Store the access coordinates for the generic portsDave Jiang2-0/+27
2023-12-22cxl: Calculate and store PCI link latency for the downstream portsDave Jiang5-0/+61
2023-12-22cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang3-13/+193
2023-12-22cxl: Add callback to parse the SSLBIS subtable from CDATDave Jiang3-0/+104
2023-12-22cxl: Add callback to parse the DSLBIS subtable from CDATDave Jiang1-2/+100
2023-12-22cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang5-0/+99
2023-12-18cxl: Fix unregister_region() callback parameter assignmentDave Jiang1-4/+4
2023-12-14cxl/pmu: Ensure put_device on pmu devicesIra Weiny1-1/+1
2023-12-08cxl/cdat: Free correct buffer on checksum errorIra Weiny1-7/+6
2023-12-07cxl/hdm: Fix dpa translation lockingDan Williams2-4/+3
2023-12-07cxl: Add Support for Get TimestampDavidlohr Bueso2-0/+2
2023-11-29cxl/memdev: Hold region_rwsem during inject and clear poison opsAlison Schofield1-2/+16
2023-11-29cxl/core: Always hold region_rwsem while reading poison listsAlison Schofield2-6/+8
2023-11-22cxl/hdm: Fix a benign lockdep splatDave Jiang1-0/+2
2023-11-02cxl/pci: Change CXL AER support check to use native AERTerry Bowman1-2/+2
2023-10-31cxl/hdm: Remove broken error pathDan Williams2-17/+10
2023-10-31cxl/hdm: Fix && vs || bugDan Carpenter1-1/+1
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams5-6/+40
2023-10-31Merge branch 'for-6.7/cxl' into cxl/nextDan Williams4-5/+11
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams5-12/+60
2023-10-31Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextDan Williams10-129/+406
2023-10-27cxl: Add support for reading CXL switch CDAT tableDave Jiang2-5/+20
2023-10-27cxl: Add checksum verification to CDAT from CXLDave Jiang1-7/+23
2023-10-27cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang3-0/+17
2023-10-27cxl: Add decoders_committed sysfs attribute to cxl_portDave Jiang1-0/+25
2023-10-27cxl: Add cxl_decoders_committed() helperDave Jiang5-6/+15
2023-10-27cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmRobert Richter3-6/+4
2023-10-27cxl/core/regs: Rename phys_addr in cxl_map_component_regs()Robert Richter1-3/+3
2023-10-27cxl/pci: Disable root port interrupts in RCH modeTerry Bowman1-0/+32
2023-10-27cxl/pci: Add RCH downstream port error loggingTerry Bowman1-0/+96
2023-10-27cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman2-0/+46
2023-10-27cxl/pci: Update CXL error logging to use RAS register addressTerry Bowman1-13/+31
2023-10-27PCI/AER: Refactor cper_print_aer() for use by CXL driver moduleTerry Bowman1-0/+1
2023-10-27cxl/pci: Add RCH downstream port AER register discoveryRobert Richter5-0/+61
2023-10-27cxl/port: Remove Component Register base address from struct cxl_portRobert Richter2-5/+1
2023-10-27cxl/pci: Remove Component Register base address from struct cxl_dev_stateRobert Richter2-5/+0
2023-10-27cxl/hdm: Use stored Component Register mappings to map HDM decoder capabilityRobert Richter3-39/+43
2023-10-27cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_s...Robert Richter3-4/+9
2023-10-27cxl/port: Pre-initialize component register mappingsRobert Richter1-5/+7
2023-10-27cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter2-7/+7
2023-10-27cxl/port: Fix @host confusion in cxl_dport_setup_regs()Dan Williams1-12/+31
2023-10-27cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter5-20/+20
2023-10-27cxl/port: Fix delete_endpoint() vs parent unregistration raceDan Williams1-15/+19
2023-10-27cxl/region: Fix x1 root-decoder granularity calculationsJim Harris1-1/+8
2023-10-27cxl/region: Fix cxl_region_rwsem lock held when returning to user spaceLi Zhijian1-1/+1
2023-10-27cxl/region: Use cxl_calc_interleave_pos() for auto-discoveryAlison Schofield1-112/+15
2023-10-27cxl/region: Calculate a target position in a region interleaveAlison Schofield1-0/+127
2023-10-26cxl/region: Prepare the decoder match range helper for reuseAlison Schofield1-6/+11
2023-10-24cxl/mbox: Remove useless cast in cxl_mem_create_range_info()Alison Schofield1-2/+1
2023-10-24cxl/region: Do not try to cleanup after cxl_region_setup_targets() failsJim Harris1-7/+7
2023-10-09cxl/mem: Fix shutdown orderDan Williams1-1/+1
2023-10-06cxl/memdev: Fix sanitize vs decoder setup lockingDan Williams8-49/+90
2023-10-06cxl/pci: Fix sanitize notifier setupDan Williams3-42/+50
2023-10-06cxl/pci: Clarify devm host for memdev relative setupDan Williams3-12/+13
2023-10-06cxl/pci: Remove inconsistent usage of dev_err_probe()Dan Williams1-11/+2
2023-10-06cxl/pci: Remove hardirq handler for cxl_request_irq()Dan Williams1-6/+6
2023-09-29cxl/pci: Cleanup 'sanitize' to always pollDan Williams3-39/+26
2023-09-29cxl/pci: Remove unnecessary device reference management in sanitize workDan Williams1-5/+0
2023-09-22cxl/acpi: Annotate struct cxl_cxims_data with __counted_byKees Cook1-2/+2
2023-09-22cxl/port: Fix cxl_test register enumeration regressionDan Williams1-4/+9
2023-09-15cxl/pci: Update commentIra Weiny1-1/+4
2023-09-15cxl/port: Quiet warning messages from the cxl_test environmentDan Williams2-2/+7
2023-09-14cxl/region: Refactor granularity select in cxl_port_setup_targets()Alison Schofield1-9/+8
2023-09-14cxl/region: Match auto-discovered region decoders by HPA rangeAlison Schofield1-1/+23
2023-09-14cxl/mbox: Fix CEL logic for poison and security commandsIra Weiny1-11/+12
2023-09-11cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()Smita Koralahalli1-2/+1
2023-09-11cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registersSmita Koralahalli1-3/+3
2023-07-28cxl/memdev: Only show sanitize sysfs files when supportedDavidlohr Bueso3-1/+78
2023-07-28cxl/memdev: Document security state in kern-docDavidlohr Bueso1-0/+1
2023-07-18cxl/acpi: Return 'rc' instead of '0' in cxl_parse_cfmws()Breno Leitao1-1/+1
2023-07-18cxl/acpi: Fix a use-after-free in cxl_parse_cfmws()Breno Leitao1-2/+1
2023-07-14cxl/mem: Fix a double shift bugDan Carpenter1-1/+1
2023-07-14cxl: fix CONFIG_FW_LOADER dependencyArnd Bergmann1-1/+2
2023-06-29cxl: Fix one kernel-doc commentYang Li1-1/+1
2023-06-27cxl/pci: Use correct flag for sanitize pollingDavidlohr Bueso1-1/+1
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams12-291/+443
2023-06-25Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams10-7/+224
2023-06-25perf: CXL Performance Monitoring Unit driverJonathan Cameron1-0/+13
2023-06-25Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxlDan Williams2-46/+72
2023-06-25Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams16-445/+515
2023-06-25Merge branch 'for-6.5/cxl-fwupd' into for-6.5/cxlDan Williams4-0/+395
2023-06-25Merge branch 'for-6.5/cxl-background' into for-6.5/cxlDan Williams6-21/+434
2023-06-25cxl: add a firmware update mechanism using the sysfs firmware loaderVishal Verma4-0/+395
2023-06-25cxl/mem: Support Secure EraseDavidlohr Bueso3-1/+34
2023-06-25cxl/mem: Wire up Sanitization supportDavidlohr Bueso4-0/+132
2023-06-25cxl/mbox: Add sanitization handling machineryDavidlohr Bueso3-3/+91
2023-06-25cxl/mem: Introduce security state sysfs fileDavidlohr Bueso3-0/+46
2023-06-25cxl/mbox: Allow for IRQ_NONE case in the isrDavidlohr Bueso1-2/+4
2023-06-25Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams3-33/+9
2023-06-25cxl/memdev: Formalize endpoint port linkageDan Williams4-5/+8
2023-06-25cxl/pci: Unconditionally unmask 256B Flit errorsDan Williams1-16/+2
2023-06-25cxl/region: Manage decoder target_type at decoder-attach timeDan Williams1-0/+12
2023-06-25cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEMDan Williams2-10/+27
2023-06-25cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams5-12/+13
2023-06-25cxl/memdev: Make mailbox functionality optionalDan Williams3-1/+28
2023-06-25cxl/mbox: Move mailbox related driver state to its own data structureDan Williams7-271/+312
2023-06-25cxl: Remove leftover attribute documentation in 'struct cxl_dev_state'Dan Williams1-1/+0
2023-06-25cxl: Fix kernel-doc warningsDan Williams1-3/+3
2023-06-25cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams2-6/+6
2023-06-25cxl/region: Fix state transitions after reset failureDan Williams1-11/+15
2023-06-25cxl/region: Flag partially torn down regions as unusableDan Williams2-0/+20
2023-06-25cxl/region: Move cache invalidation before region teardown, and before setupDan Williams2-36/+38
2023-06-25cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter2-0/+13
2023-06-25cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter2-0/+29
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter4-18/+57
2023-06-25cxl/mem: Prepare for early RCH dport component register setupRobert Richter1-5/+4
2023-06-25cxl/regs: Remove early capability checks in Component Register setupRobert Richter3-9/+6
2023-06-25cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter2-3/+0
2023-06-25cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's portRobert Richter1-28/+63
2023-06-25cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()Robert Richter1-45/+45
2023-06-25cxl/pci: Refactor component register discovery for reuseTerry Bowman3-74/+83
2023-06-25cxl/core/regs: Add @dev to cxl_register_mapRobert Richter4-24/+31
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams7-63/+71
2023-06-25cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter3-14/+14
2023-06-25cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams4-7/+15
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter6-50/+61
2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron9-1/+155
2023-05-30cxl: Add functions to get an instance of / count regblocks of a given typeJonathan Cameron2-6/+56
2023-05-26cxl: Explicitly initialize resources when media is not readyDave Jiang1-6/+11
2023-05-23cxl/mbox: Add background cmd handling machineryDavidlohr Bueso4-1/+106
2023-05-23cxl/pci: Introduce cxl_request_irq()Davidlohr Bueso1-16/+23
2023-05-23cxl/pci: Allocate irq vectors earlier during probeDavidlohr Bueso1-4/+4
2023-05-19cxl/port: Fix NULL pointer access in devm_cxl_add_port()Robert Richter1-4/+3
2023-05-18cxl: Move cxl_await_media_ready() to before capacity info retrievalDave Jiang5-11/+21
2023-05-18cxl: Wait Memory_Info_Valid before access memory related infoDave Jiang2-9/+78
2023-05-18cxl/port: Enable the HDM decoder capability for switch portsDan Williams3-9/+33
2023-05-13cxl: Add missing return to cdat read error pathDave Jiang1-0/+1
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-09 02:10:51 +0000