diff options
| author | Robert Richter <rrichter@amd.com> | 2023-06-22 15:55:06 -0500 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-06-25 11:51:17 -0700 |
| commit | d8bffff2016f7aef1c1dbe01125720475507b6f2 (patch) | |
| tree | 99ad0c127a83637e1a3fac1dd151fbcb3be231e9 /drivers/cxl | |
| parent | d02034b4025a086b1294bfd4a2e77525e816cea4 (diff) | |
| download | linux-d8bffff2016f7aef1c1dbe01125720475507b6f2.tar.gz | |
cxl/port: Remove Component Register base address from struct cxl_dport
The Component Register base address @component_reg_phys is no longer
used after the rework of the Component Register setup which now uses
struct member @comp_map instead. Remove the base address.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230622205523.85375-11-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl')
| -rw-r--r-- | drivers/cxl/core/port.c | 1 | ||||
| -rw-r--r-- | drivers/cxl/cxl.h | 2 |
2 files changed, 0 insertions, 3 deletions
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index cdfe0ea7a2e9ed..e0d2e75964402a 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -960,7 +960,6 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, dport->dport_dev = dport_dev; dport->port_id = port_id; - dport->component_reg_phys = component_reg_phys; dport->port = port; cond_cxl_root_lock(port); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index ae265357170e88..7fbc52b81554ad 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -594,7 +594,6 @@ struct cxl_rcrb_info { * struct cxl_dport - CXL downstream port * @dport_dev: PCI bridge or firmware device representing the downstream link * @port_id: unique hardware identifier for dport in decoder target list - * @component_reg_phys: downstream port component registers * @rcrb: Data about the Root Complex Register Block layout * @rch: Indicate whether this dport was enumerated in RCH or VH mode * @port: reference to cxl_port that contains this downstream port @@ -602,7 +601,6 @@ struct cxl_rcrb_info { struct cxl_dport { struct device *dport_dev; int port_id; - resource_size_t component_reg_phys; struct cxl_rcrb_info rcrb; bool rch; struct cxl_port *port; |