diff options
Diffstat (limited to 'include/asm-ia64/sn/pci')
| -rw-r--r-- | include/asm-ia64/sn/pci/bridge.h | 345 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pci_bus_cvlink.h | 7 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pci_defs.h | 111 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pciba.h | 2 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pcibr.h | 102 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pcibr_private.h | 80 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pciio.h | 141 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pciio_private.h | 12 |
8 files changed, 290 insertions, 510 deletions
diff --git a/include/asm-ia64/sn/pci/bridge.h b/include/asm-ia64/sn/pci/bridge.h index ebbc59ad0d1b0..bc021e657f72d 100644 --- a/include/asm-ia64/sn/pci/bridge.h +++ b/include/asm-ia64/sn/pci/bridge.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_BRIDGE_H #define _ASM_SN_PCI_BRIDGE_H @@ -36,7 +36,6 @@ #include <linux/config.h> #include <asm/sn/xtalk/xwidget.h> -#ifndef CONFIG_IA64_SGI_SN1 #include <asm/sn/pci/pic.h> extern int io_get_sh_swapper(nasid_t); @@ -45,7 +44,6 @@ extern int io_get_sh_swapper(nasid_t); #define BRIDGE_REG_SET32(reg) \ *(volatile uint32_t *) (((uint64_t)reg)^4) -#endif /* CONFIG_IA64_SGI_SN1 */ /* I/O page size */ @@ -111,7 +109,6 @@ typedef volatile bridge_ate_t *bridge_ate_p; * Generated from Bridge spec dated 04oct95 */ -#ifndef CONFIG_IA64_SGI_SN1 /* * pic_widget_cfg_s is a local definition of widget_cfg_t but with @@ -605,292 +602,6 @@ typedef volatile struct bridge_s { } b_external_flash; } bridge_t; -#else /* CONFIG_IA64_SGI_SN1 */ - - -typedef volatile struct bridge_s { - - /* Local Registers 0x000000-0x00FFFF */ - - /* standard widget configuration 0x000000-0x000057 */ - widget_cfg_t b_widget; /* 0x000000 */ - - /* helper fieldnames for accessing bridge widget */ - -#define b_wid_id b_widget.w_id -#define b_wid_stat b_widget.w_status -#define b_wid_err_upper b_widget.w_err_upper_addr -#define b_wid_err_lower b_widget.w_err_lower_addr -#define b_wid_control b_widget.w_control -#define b_wid_req_timeout b_widget.w_req_timeout -#define b_wid_int_upper b_widget.w_intdest_upper_addr -#define b_wid_int_lower b_widget.w_intdest_lower_addr -#define b_wid_err_cmdword b_widget.w_err_cmd_word -#define b_wid_llp b_widget.w_llp_cfg -#define b_wid_tflush b_widget.w_tflush - - /* - * we access these through synergy unswizzled space, so the address - * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) - * That's why we put the register first and filler second. - */ - /* bridge-specific widget configuration 0x000058-0x00007F */ - bridgereg_t b_wid_aux_err; /* 0x00005C */ - bridgereg_t _pad_000058; - - bridgereg_t b_wid_resp_upper; /* 0x000064 */ - bridgereg_t _pad_000060; - - bridgereg_t b_wid_resp_lower; /* 0x00006C */ - bridgereg_t _pad_000068; - - bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ - bridgereg_t _pad_000070; - - bridgereg_t _pad_000078[2]; - - /* PMU & Map 0x000080-0x00008F */ - bridgereg_t b_dir_map; /* 0x000084 */ - bridgereg_t _pad_000080; - bridgereg_t _pad_000088[2]; - - /* SSRAM 0x000090-0x00009F */ - bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */ - bridgereg_t _pad_000090; -#define b_ram_perr b_ram_perr_or_map_fault /* Bridge */ -#define b_map_fault b_ram_perr_or_map_fault /* Xbridge */ - bridgereg_t _pad_000098[2]; - - /* Arbitration 0x0000A0-0x0000AF */ - bridgereg_t b_arb; /* 0x0000A4 */ - bridgereg_t _pad_0000A0; - bridgereg_t _pad_0000A8[2]; - - /* Number In A Can 0x0000B0-0x0000BF */ - bridgereg_t b_nic; /* 0x0000B4 */ - bridgereg_t _pad_0000B0; - bridgereg_t _pad_0000B8[2]; - - /* PCI/GIO 0x0000C0-0x0000FF */ - bridgereg_t b_bus_timeout; /* 0x0000C4 */ - bridgereg_t _pad_0000C0; -#define b_pci_bus_timeout b_bus_timeout - - bridgereg_t b_pci_cfg; /* 0x0000CC */ - bridgereg_t _pad_0000C8; - - bridgereg_t b_pci_err_upper; /* 0x0000D4 */ - bridgereg_t _pad_0000D0; - - bridgereg_t b_pci_err_lower; /* 0x0000DC */ - bridgereg_t _pad_0000D8; - bridgereg_t _pad_0000E0[8]; -#define b_gio_err_lower b_pci_err_lower -#define b_gio_err_upper b_pci_err_upper - - /* Interrupt 0x000100-0x0001FF */ - bridgereg_t b_int_status; /* 0x000104 */ - bridgereg_t _pad_000100; - - bridgereg_t b_int_enable; /* 0x00010C */ - bridgereg_t _pad_000108; - - bridgereg_t b_int_rst_stat; /* 0x000114 */ - bridgereg_t _pad_000110; - - bridgereg_t b_int_mode; /* 0x00011C */ - bridgereg_t _pad_000118; - - bridgereg_t b_int_device; /* 0x000124 */ - bridgereg_t _pad_000120; - - bridgereg_t b_int_host_err; /* 0x00012C */ - bridgereg_t _pad_000128; - - struct { - bridgereg_t addr; /* 0x0001{34,,,6C} */ - bridgereg_t __pad; /* 0x0001{30,,,68} */ - } b_int_addr[8]; /* 0x000130 */ - - bridgereg_t b_err_int_view; /* 0x000174 */ - bridgereg_t _pad_000170; - - bridgereg_t b_mult_int; /* 0x00017c */ - bridgereg_t _pad_000178; - - struct { - bridgereg_t intr; /* 0x0001{84,,,BC} */ - bridgereg_t __pad; /* 0x0001{80,,,B8} */ - } b_force_always[8]; /* 0x000180 */ - - struct { - bridgereg_t intr; /* 0x0001{C4,,,FC} */ - bridgereg_t __pad; /* 0x0001{C0,,,F8} */ - } b_force_pin[8]; /* 0x0001C0 */ - - /* Device 0x000200-0x0003FF */ - struct { - bridgereg_t reg; /* 0x0002{04,,,3C} */ - bridgereg_t __pad; /* 0x0002{00,,,38} */ - } b_device[8]; /* 0x000200 */ - - struct { - bridgereg_t reg; /* 0x0002{44,,,7C} */ - bridgereg_t __pad; /* 0x0002{40,,,78} */ - } b_wr_req_buf[8]; /* 0x000240 */ - - struct { - bridgereg_t reg; /* 0x0002{84,,,8C} */ - bridgereg_t __pad; /* 0x0002{80,,,88} */ - } b_rrb_map[2]; /* 0x000280 */ -#define b_even_resp b_rrb_map[0].reg /* 0x000284 */ -#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ - - bridgereg_t b_resp_status; /* 0x000294 */ - bridgereg_t _pad_000290; - - bridgereg_t b_resp_clear; /* 0x00029C */ - bridgereg_t _pad_000298; - - bridgereg_t _pad_0002A0[24]; - - /* Xbridge only */ - struct { - bridgereg_t upper; /* 0x0003{04,,,F4} */ - bridgereg_t __pad1; /* 0x0003{00,,,F0} */ - bridgereg_t lower; /* 0x0003{0C,,,FC} */ - bridgereg_t __pad2; /* 0x0003{08,,,F8} */ - } b_buf_addr_match[16]; - - /* Performance Monitor Registers (even only) */ - struct { - bridgereg_t flush_w_touch; /* 0x000404,,,5C4 */ - bridgereg_t __pad1; /* 0x000400,,,5C0 */ - - bridgereg_t flush_wo_touch; /* 0x00040C,,,5CC */ - bridgereg_t __pad2; /* 0x000408,,,5C8 */ - - bridgereg_t inflight; /* 0x000414,,,5D4 */ - bridgereg_t __pad3; /* 0x000410,,,5D0 */ - - bridgereg_t prefetch; /* 0x00041C,,,5DC */ - bridgereg_t __pad4; /* 0x000418,,,5D8 */ - - bridgereg_t total_pci_retry; /* 0x000424,,,5E4 */ - bridgereg_t __pad5; /* 0x000420,,,5E0 */ - - bridgereg_t max_pci_retry; /* 0x00042C,,,5EC */ - bridgereg_t __pad6; /* 0x000428,,,5E8 */ - - bridgereg_t max_latency; /* 0x000434,,,5F4 */ - bridgereg_t __pad7; /* 0x000430,,,5F0 */ - - bridgereg_t clear_all; /* 0x00043C,,,5FC */ - bridgereg_t __pad8; /* 0x000438,,,5F8 */ - } b_buf_count[8]; - - char _pad_000600[0x010000 - 0x000600]; - - /* - * The Xbridge has 1024 internal ATE's and the Bridge has 128. - * Make enough room for the Xbridge ATE's and depend on runtime - * checks to limit access to bridge ATE's. - */ - - /* Internal Address Translation Entry RAM 0x010000-0x011fff */ - union { - bridge_ate_t wr; /* write-only */ - struct { - bridgereg_t rd; /* read-only */ - bridgereg_t _p_pad; - } hi; - } b_int_ate_ram[XBRIDGE_INTERNAL_ATES]; - -#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd - - /* the xbridge read path for internal ates starts at 0x12000. - * I don't believe we ever try to read the ates. - */ - /* Internal Address Translation Entry RAM LOW 0x012000-0x013fff */ - struct { - bridgereg_t rd; - bridgereg_t _p_pad; - } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES]; - - char _pad_014000[0x20000 - 0x014000]; - - /* PCI Device Configuration Spaces 0x020000-0x027FFF */ - union { /* make all access sizes available. */ - uchar_t c[0x1000 / 1]; - uint16_t s[0x1000 / 2]; - uint32_t l[0x1000 / 4]; - uint64_t d[0x1000 / 8]; - union { - uchar_t c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; - } f[8]; - } b_type0_cfg_dev[8]; /* 0x020000 */ - - /* PCI Type 1 Configuration Space 0x028000-0x028FFF */ - union { /* make all access sizes available. */ - uchar_t c[0x1000 / 1]; - uint16_t s[0x1000 / 2]; - uint32_t l[0x1000 / 4]; - uint64_t d[0x1000 / 8]; - union { - uchar_t c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; - } f[8]; - } b_type1_cfg; /* 0x028000-0x029000 */ - - char _pad_029000[0x007000]; /* 0x029000-0x030000 */ - - /* PCI Interrupt Acknowledge Cycle 0x030000 */ - union { - uchar_t c[8 / 1]; - uint16_t s[8 / 2]; - uint32_t l[8 / 4]; - uint64_t d[8 / 8]; - } b_pci_iack; /* 0x030000 */ - - uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ - - /* External Address Translation Entry RAM 0x080000-0x0FFFFF */ - bridge_ate_t b_ext_ate_ram[0x10000]; - - /* Reserved 0x100000-0x1FFFFF */ - char _pad_100000[0x200000-0x100000]; - - /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */ - union { /* make all access sizes available. */ - uchar_t c[0x100000 / 1]; - uint16_t s[0x100000 / 2]; - uint32_t l[0x100000 / 4]; - uint64_t d[0x100000 / 8]; - } b_devio_raw[10]; /* 0x200000 */ - - /* b_devio macro is a bit strange; it reflects the - * fact that the Bridge ASIC provides 2M for the - * first two DevIO windows and 1M for the other six. - */ -#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] - - /* External Flash Proms 1,0 0xC00000-0xFFFFFF */ - union { /* make all access sizes available. */ - uchar_t c[0x400000 / 1]; /* read-only */ - uint16_t s[0x400000 / 2]; /* read-write */ - uint32_t l[0x400000 / 4]; /* read-only */ - uint64_t d[0x400000 / 8]; /* read-only */ - } b_external_flash; /* 0xC00000 */ -} bridge_t; - -#endif /* CONFIG_IA64_SGI_SN1 */ - - #define berr_field berr_un.berr_st #endif /* __ASSEMBLY__ */ @@ -1428,8 +1139,7 @@ typedef volatile struct bridge_s { #define BRIDGE_ISR_ERRORS \ (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \ BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ - BRIDGE_ISR_PMU_ESIZE_FAULT|PIC_ISR_PCIX_ARB_ERR| \ - PIC_ISR_INT_RAM_PERR) + BRIDGE_ISR_PMU_ESIZE_FAULT|PIC_ISR_INT_RAM_PERR) /* * List of Errors which are fatal and kill the sytem @@ -1598,22 +1308,6 @@ typedef volatile struct bridge_s { #define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff -#ifdef SN0 -/* - * The NASID should be shifted by this amount and stored into the - * interrupt(x) register. - */ -#define BRIDGE_INT_ADDR_NASID_SHFT 8 - -/* - * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to - * memory. - */ -#define BRIDGE_INT_ADDR_DEST_IO (1 << 17) -#define BRIDGE_INT_ADDR_DEST_MEM 0 -#define BRIDGE_INT_ADDR_MASK (1 << 17) -#endif - /* Bridge device(x) register bits definition */ #define BRIDGE_DEV_ERR_LOCK_EN (1ull << 28) #define BRIDGE_DEV_PAGE_CHK_DIS (1ull << 27) @@ -1728,6 +1422,38 @@ typedef volatile struct bridge_s { #define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT /* + * Macros for Xtalk to Bridge bus (PCI) PIO + * refer to section 5.2.1 Figure 4 of the "PCI Interface Chip (PIC) Volume II + * Programmer's Reference" (Revision 0.8 as of this writing). + * + * These are PIC bridge specific. A separate set of macros was defined + * because PIC deviates from Bridge/Xbridge by not supporting a big-window + * alias for PCI I/O space, and also redefines XTALK addresses + * 0x0000C0000000L and 0x000100000000L to be PCI MEM aliases for the second + * bus. + */ + +/* XTALK addresses that map into PIC Bridge Bus addr space */ +#define PICBRIDGE0_PIO32_XTALK_ALIAS_BASE 0x000040000000L +#define PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL +#define PICBRIDGE0_PIO64_XTALK_ALIAS_BASE 0x000080000000L +#define PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL +#define PICBRIDGE1_PIO32_XTALK_ALIAS_BASE 0x0000C0000000L +#define PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT 0x0000FFFFFFFFL +#define PICBRIDGE1_PIO64_XTALK_ALIAS_BASE 0x000100000000L +#define PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT 0x00013FFFFFFFL + +/* XTALK addresses that map into PCI addresses */ +#define PICBRIDGE0_PCI_MEM32_BASE PICBRIDGE0_PIO32_XTALK_ALIAS_BASE +#define PICBRIDGE0_PCI_MEM32_LIMIT PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT +#define PICBRIDGE0_PCI_MEM64_BASE PICBRIDGE0_PIO64_XTALK_ALIAS_BASE +#define PICBRIDGE0_PCI_MEM64_LIMIT PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT +#define PICBRIDGE1_PCI_MEM32_BASE PICBRIDGE1_PIO32_XTALK_ALIAS_BASE +#define PICBRIDGE1_PCI_MEM32_LIMIT PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT +#define PICBRIDGE1_PCI_MEM64_BASE PICBRIDGE1_PIO64_XTALK_ALIAS_BASE +#define PICBRIDGE1_PCI_MEM64_LIMIT PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT + +/* * Macros for Bridge bus (PCI/GIO) to Xtalk DMA */ /* Bridge Bus DMA addresses */ @@ -1845,9 +1571,6 @@ typedef union ate_u { #define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT)) #define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT)) -#define is_xbridge(bridge) IS_XBRIDGE(bridge->b_wid_id) -#define is_pic(bridge) IS_PIC_BRIDGE(bridge->b_wid_id) - /* extern declarations */ #ifndef __ASSEMBLY__ diff --git a/include/asm-ia64/sn/pci/pci_bus_cvlink.h b/include/asm-ia64/sn/pci/pci_bus_cvlink.h index 6c4e2dfc21563..517acefde8b2f 100644 --- a/include/asm-ia64/sn/pci/pci_bus_cvlink.h +++ b/include/asm-ia64/sn/pci/pci_bus_cvlink.h @@ -4,13 +4,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_CVLINK_H #define _ASM_SN_PCI_CVLINK_H #include <asm/sn/types.h> -#include <asm/sn/hack.h> #include <asm/sn/sgi.h> #include <asm/sn/driver.h> #include <asm/sn/iograph.h> @@ -50,11 +49,11 @@ (((struct sn_widget_sysdata *)((pci_bus)->sysdata))->vhdl) struct sn_widget_sysdata { - devfs_handle_t vhdl; + vertex_hdl_t vhdl; }; struct sn_device_sysdata { - devfs_handle_t vhdl; + vertex_hdl_t vhdl; int isa64; int isPIC; volatile unsigned int *dma_buf_sync; diff --git a/include/asm-ia64/sn/pci/pci_defs.h b/include/asm-ia64/sn/pci/pci_defs.h index 2df7888e56169..73dbb4b81a0d3 100644 --- a/include/asm-ia64/sn/pci/pci_defs.h +++ b/include/asm-ia64/sn/pci/pci_defs.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCI_DEFS_H #define _ASM_SN_PCI_PCI_DEFS_H @@ -321,6 +321,112 @@ extern void pci_write(void * address, int data, int type); #ifndef __ASSEMBLY__ +#ifdef LITTLE_ENDIAN + +/* + * PCI config space definition + */ +typedef volatile struct pci_cfg_s { + uint16_t vendor_id; + uint16_t dev_id; + uint16_t cmd; + uint16_t status; + uchar_t rev; + uchar_t prog_if; + uchar_t sub_class; + uchar_t class; + uchar_t line_size; + uchar_t lt; + uchar_t hdr_type; + uchar_t bist; + uint32_t bar[6]; + uint32_t cardbus; + uint16_t subsys_vendor_id; + uint16_t subsys_dev_id; + uint32_t exp_rom; + uint32_t res[2]; + uchar_t int_line; + uchar_t int_pin; + uchar_t min_gnt; + uchar_t max_lat; +} pci_cfg_t; + +/* + * PCI Type 1 config space definition for PCI to PCI Bridges (PPBs) + */ +typedef volatile struct pci_cfg1_s { + uint16_t vendor_id; + uint16_t dev_id; + uint16_t cmd; + uint16_t status; + uchar_t rev; + uchar_t prog_if; + uchar_t sub_class; + uchar_t class; + uchar_t line_size; + uchar_t lt; + uchar_t hdr_type; + uchar_t bist; + uint32_t bar[2]; + uchar_t pri_bus_num; + uchar_t snd_bus_num; + uchar_t sub_bus_num; + uchar_t slt; + uchar_t io_base; + uchar_t io_limit; + uint16_t snd_status; + uint16_t mem_base; + uint16_t mem_limit; + uint16_t pmem_base; + uint16_t pmem_limit; + uint32_t pmem_base_upper; + uint32_t pmem_limit_upper; + uint16_t io_base_upper; + uint16_t io_limit_upper; + uint32_t res; + uint32_t exp_rom; + uchar_t int_line; + uchar_t int_pin; + uint16_t ppb_control; + +} pci_cfg1_t; + +/* + * PCI-X Capability + */ +typedef volatile struct cap_pcix_cmd_reg_s { + uint16_t data_parity_enable: 1, + enable_relaxed_order: 1, + max_mem_read_cnt: 2, + max_split: 3, + reserved1: 9; +} cap_pcix_cmd_reg_t; + +typedef volatile struct cap_pcix_stat_reg_s { + uint32_t func_num: 3, + dev_num: 5, + bus_num: 8, + bit64_device: 1, + mhz133_capable: 1, + split_complt_discard: 1, + unexpect_split_complt: 1, + device_complex: 1, + max_mem_read_cnt: 2, + max_out_split: 3, + max_cum_read: 3, + split_complt_err: 1, + reserved1: 2; +} cap_pcix_stat_reg_t; + +typedef volatile struct cap_pcix_type0_s { + uchar_t pcix_cap_id; + uchar_t pcix_cap_nxt; + cap_pcix_cmd_reg_t pcix_type0_command; + cap_pcix_stat_reg_t pcix_type0_status; +} cap_pcix_type0_t; + +#else + /* * PCI config space definition */ @@ -388,6 +494,8 @@ typedef volatile struct pci_cfg1_s { uchar_t int_line; } pci_cfg1_t; + + /* * PCI-X Capability */ @@ -422,5 +530,6 @@ typedef volatile struct cap_pcix_type0_s { cap_pcix_stat_reg_t pcix_type0_status; } cap_pcix_type0_t; +#endif #endif /* __ASSEMBLY__ */ #endif /* _ASM_SN_PCI_PCI_DEFS_H */ diff --git a/include/asm-ia64/sn/pci/pciba.h b/include/asm-ia64/sn/pci/pciba.h index f8b16a2033e99..fd62d78c57a32 100644 --- a/include/asm-ia64/sn/pci/pciba.h +++ b/include/asm-ia64/sn/pci/pciba.h @@ -3,7 +3,7 @@ * Public License. See the file "COPYING" in the main directory of * this archive for more details. * - * Copyright (C) 1997, 2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1997, 2001-2003 Silicon Graphics, Inc. All rights reserved. * */ diff --git a/include/asm-ia64/sn/pci/pcibr.h b/include/asm-ia64/sn/pci/pcibr.h index c29d13c49fb73..c9153ea71e9e4 100644 --- a/include/asm-ia64/sn/pci/pcibr.h +++ b/include/asm-ia64/sn/pci/pcibr.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCIBR_H #define _ASM_SN_PCI_PCIBR_H @@ -59,9 +59,7 @@ typedef struct pcibr_intr_s *pcibr_intr_t; * code and part number registered by pcibr_init(). */ -extern void pcibr_init(void); - -extern int pcibr_attach(devfs_handle_t); +extern int pcibr_attach(vertex_hdl_t); /* ===================================================================== * bus provider function table @@ -94,7 +92,7 @@ extern pciio_provider_t pci_pic_provider; * smarts on the part of the compilation system). */ -extern pcibr_piomap_t pcibr_piomap_alloc(devfs_handle_t dev, +extern pcibr_piomap_t pcibr_piomap_alloc(vertex_hdl_t dev, device_desc_t dev_desc, pciio_space_t space, iopaddr_t pci_addr, @@ -110,24 +108,24 @@ extern caddr_t pcibr_piomap_addr(pcibr_piomap_t piomap, extern void pcibr_piomap_done(pcibr_piomap_t piomap); -extern caddr_t pcibr_piotrans_addr(devfs_handle_t dev, +extern caddr_t pcibr_piotrans_addr(vertex_hdl_t dev, device_desc_t dev_desc, pciio_space_t space, iopaddr_t pci_addr, size_t byte_count, unsigned flags); -extern iopaddr_t pcibr_piospace_alloc(devfs_handle_t dev, +extern iopaddr_t pcibr_piospace_alloc(vertex_hdl_t dev, device_desc_t dev_desc, pciio_space_t space, size_t byte_count, size_t alignment); -extern void pcibr_piospace_free(devfs_handle_t dev, +extern void pcibr_piospace_free(vertex_hdl_t dev, pciio_space_t space, iopaddr_t pciaddr, size_t byte_count); -extern pcibr_dmamap_t pcibr_dmamap_alloc(devfs_handle_t dev, +extern pcibr_dmamap_t pcibr_dmamap_alloc(vertex_hdl_t dev, device_desc_t dev_desc, size_t byte_count_max, unsigned flags); @@ -150,109 +148,97 @@ extern void pcibr_dmamap_done(pcibr_dmamap_t dmamap); * (This node id can be different for each PCI bus.) */ -extern cnodeid_t pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl); +extern cnodeid_t pcibr_get_dmatrans_node(vertex_hdl_t pconn_vhdl); -extern iopaddr_t pcibr_dmatrans_addr(devfs_handle_t dev, +extern iopaddr_t pcibr_dmatrans_addr(vertex_hdl_t dev, device_desc_t dev_desc, paddr_t paddr, size_t byte_count, unsigned flags); -extern alenlist_t pcibr_dmatrans_list(devfs_handle_t dev, +extern alenlist_t pcibr_dmatrans_list(vertex_hdl_t dev, device_desc_t dev_desc, alenlist_t palenlist, unsigned flags); extern void pcibr_dmamap_drain(pcibr_dmamap_t map); -extern void pcibr_dmaaddr_drain(devfs_handle_t vhdl, +extern void pcibr_dmaaddr_drain(vertex_hdl_t vhdl, paddr_t addr, size_t bytes); -extern void pcibr_dmalist_drain(devfs_handle_t vhdl, +extern void pcibr_dmalist_drain(vertex_hdl_t vhdl, alenlist_t list); typedef unsigned pcibr_intr_ibit_f(pciio_info_t info, pciio_intr_line_t lines); -extern void pcibr_intr_ibit_set(devfs_handle_t, pcibr_intr_ibit_f *); +extern void pcibr_intr_ibit_set(vertex_hdl_t, pcibr_intr_ibit_f *); -extern pcibr_intr_t pcibr_intr_alloc(devfs_handle_t dev, +extern pcibr_intr_t pcibr_intr_alloc(vertex_hdl_t dev, device_desc_t dev_desc, pciio_intr_line_t lines, - devfs_handle_t owner_dev); + vertex_hdl_t owner_dev); extern void pcibr_intr_free(pcibr_intr_t intr); -#ifdef CONFIG_IA64_SGI_SN1 -extern int pcibr_intr_connect(pcibr_intr_t intr); -#else extern int pcibr_intr_connect(pcibr_intr_t intr, intr_func_t, intr_arg_t); -#endif extern void pcibr_intr_disconnect(pcibr_intr_t intr); -extern devfs_handle_t pcibr_intr_cpu_get(pcibr_intr_t intr); +extern vertex_hdl_t pcibr_intr_cpu_get(pcibr_intr_t intr); -extern void pcibr_provider_startup(devfs_handle_t pcibr); +extern void pcibr_provider_startup(vertex_hdl_t pcibr); -extern void pcibr_provider_shutdown(devfs_handle_t pcibr); +extern void pcibr_provider_shutdown(vertex_hdl_t pcibr); -extern int pcibr_reset(devfs_handle_t dev); +extern int pcibr_reset(vertex_hdl_t dev); -extern int pcibr_write_gather_flush(devfs_handle_t dev); +extern int pcibr_write_gather_flush(vertex_hdl_t dev); -extern pciio_endian_t pcibr_endian_set(devfs_handle_t dev, +extern pciio_endian_t pcibr_endian_set(vertex_hdl_t dev, pciio_endian_t device_end, pciio_endian_t desired_end); -extern pciio_priority_t pcibr_priority_set(devfs_handle_t dev, +extern pciio_priority_t pcibr_priority_set(vertex_hdl_t dev, pciio_priority_t device_prio); -extern uint64_t pcibr_config_get(devfs_handle_t conn, +extern uint64_t pcibr_config_get(vertex_hdl_t conn, unsigned reg, unsigned size); -extern void pcibr_config_set(devfs_handle_t conn, +extern void pcibr_config_set(vertex_hdl_t conn, unsigned reg, unsigned size, uint64_t value); -extern int pcibr_error_devenable(devfs_handle_t pconn_vhdl, +extern int pcibr_error_devenable(vertex_hdl_t pconn_vhdl, int error_code); -#ifdef PIC_LATER -extern pciio_slot_t pcibr_error_extract(devfs_handle_t pcibr_vhdl, - pciio_space_t *spacep, - iopaddr_t *addrp); -#endif - -extern int pcibr_wrb_flush(devfs_handle_t pconn_vhdl); -extern int pcibr_rrb_check(devfs_handle_t pconn_vhdl, +extern int pcibr_wrb_flush(vertex_hdl_t pconn_vhdl); +extern int pcibr_rrb_check(vertex_hdl_t pconn_vhdl, int *count_vchan0, int *count_vchan1, int *count_reserved, int *count_pool); -#ifndef CONFIG_IA64_SGI_SN1 -extern int pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd, +extern int pcibr_alloc_all_rrbs(vertex_hdl_t vhdl, int even_odd, int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2, int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4); -#endif typedef void -rrb_alloc_funct_f (devfs_handle_t xconn_vhdl, +rrb_alloc_funct_f (vertex_hdl_t xconn_vhdl, int *vendor_list); typedef rrb_alloc_funct_f *rrb_alloc_funct_t; -void pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, +void pcibr_set_rrb_callback(vertex_hdl_t xconn_vhdl, rrb_alloc_funct_f *func); -extern int pcibr_device_unregister(devfs_handle_t); -extern int pcibr_dma_enabled(devfs_handle_t); +extern int pcibr_device_unregister(vertex_hdl_t); +extern int pcibr_dma_enabled(vertex_hdl_t); /* * Bridge-specific flags that can be set via pcibr_device_flags_set * and cleared via pcibr_device_flags_clear. Other flags are @@ -320,7 +306,7 @@ typedef int pcibr_device_flags_t; * "flags" are defined above. NOTE: this includes turning * things *OFF* as well as turning them *ON* ... */ -extern int pcibr_device_flags_set(devfs_handle_t dev, +extern int pcibr_device_flags_set(vertex_hdl_t dev, pcibr_device_flags_t flags); /* @@ -331,7 +317,7 @@ extern int pcibr_device_flags_set(devfs_handle_t dev, * <0 on failure, which occurs when we're unable to allocate any * buffers to a channel that desires at least one buffer. */ -extern int pcibr_rrb_alloc(devfs_handle_t pconn_vhdl, +extern int pcibr_rrb_alloc(vertex_hdl_t pconn_vhdl, int *count_vchan0, int *count_vchan1); @@ -345,19 +331,15 @@ extern iopaddr_t pcibr_dmamap_pciaddr_get(pcibr_dmamap_t); extern xwidget_intr_preset_f pcibr_xintr_preset; -extern void pcibr_hints_fix_rrbs(devfs_handle_t); -extern void pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t); -extern void pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong); -extern void pcibr_hints_handsoff(devfs_handle_t); +extern void pcibr_hints_fix_rrbs(vertex_hdl_t); +extern void pcibr_hints_dualslot(vertex_hdl_t, pciio_slot_t, pciio_slot_t); +extern void pcibr_hints_subdevs(vertex_hdl_t, pciio_slot_t, ulong); +extern void pcibr_hints_handsoff(vertex_hdl_t); -#ifdef CONFIG_IA64_SGI_SN1 -typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t); -#else typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t, int); -#endif -extern void pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *); +extern void pcibr_hints_intr_bits(vertex_hdl_t, pcibr_intr_bits_f *); -extern int pcibr_asic_rev(devfs_handle_t); +extern int pcibr_asic_rev(vertex_hdl_t); #endif /* __ASSEMBLY__ */ #endif /* #if defined(__KERNEL__) */ @@ -433,7 +415,7 @@ struct pcibr_slot_info_resp_s { short resp_bs_bridge_mode; int resp_has_host; char resp_host_slot; - devfs_handle_t resp_slot_conn; + vertex_hdl_t resp_slot_conn; char resp_slot_conn_name[MAXDEVNAME]; int resp_slot_status; int resp_l1_bus_num; @@ -460,10 +442,8 @@ struct pcibr_slot_info_resp_s { bridgereg_t resp_b_int_device; bridgereg_t resp_b_int_enable; bridgereg_t resp_b_int_host; -#ifndef CONFIG_IA64_SGI_SN1 picreg_t resp_p_int_enable; picreg_t resp_p_int_host; -#endif struct pcibr_slot_func_info_resp_s { int resp_f_status; char resp_f_slot_name[MAXDEVNAME]; diff --git a/include/asm-ia64/sn/pci/pcibr_private.h b/include/asm-ia64/sn/pci/pcibr_private.h index 569aba5e2b35d..86c7ba6918423 100644 --- a/include/asm-ia64/sn/pci/pcibr_private.h +++ b/include/asm-ia64/sn/pci/pcibr_private.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCIBR_PRIVATE_H #define _ASM_SN_PCI_PCIBR_PRIVATE_H @@ -16,6 +16,7 @@ */ #include <linux/config.h> +#include <linux/pci.h> #include <asm/sn/pci/pcibr.h> #include <asm/sn/pci/pciio_private.h> #include <asm/sn/ksys/l1.h> @@ -45,7 +46,7 @@ cfg_p pcibr_slot_config_addr(bridge_t *, pciio_slot_t, int); cfg_p pcibr_func_config_addr(bridge_t *, pciio_bus_t bus, pciio_slot_t, pciio_function_t, int); unsigned pcibr_slot_config_get(bridge_t *, pciio_slot_t, int); unsigned pcibr_func_config_get(bridge_t *, pciio_slot_t, pciio_function_t, int); -void pcibr_debug(uint32_t, devfs_handle_t, char *, ...); +void pcibr_debug(uint32_t, vertex_hdl_t, char *, ...); void pcibr_slot_config_set(bridge_t *, pciio_slot_t, int, unsigned); void pcibr_func_config_set(bridge_t *, pciio_slot_t, pciio_function_t, int, unsigned); @@ -171,6 +172,7 @@ struct pcibr_intr_s { unsigned bi_ibits; /* which Bridge interrupt bit(s) */ pcibr_soft_t bi_soft; /* shortcut to soft info */ struct pcibr_intr_cbuf_s bi_ibuf; /* circular buffer of wrap ptrs */ + unsigned bi_last_intr; /* For Shub lb lost intr. bug */ }; @@ -254,11 +256,7 @@ struct pcibr_intr_list_s { struct pcibr_intr_wrap_s { pcibr_soft_t iw_soft; /* which bridge */ volatile bridgereg_t *iw_stat; /* ptr to b_int_status */ -#ifdef CONFIG_IA64_SGI_SN1 - bridgereg_t iw_intr; /* bit in b_int_status */ -#else bridgereg_t iw_ibit; /* bit in b_int_status */ -#endif pcibr_intr_list_t iw_list; /* ghostbusters! */ int iw_hdlrcnt; /* running handler count */ int iw_shared; /* if Bridge bit is shared */ @@ -293,6 +291,8 @@ struct pcibr_intr_wrap_s { #define PCIBR_BRIDGETYPE_PIC 2 #define IS_XBRIDGE_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_XBRIDGE) #define IS_PIC_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_PIC) +#define IS_PIC_BUSNUM_SOFT(ps, bus) \ + (IS_PIC_SOFT(ps) && ((ps)->bs_busnum == (bus))) #define IS_BRIDGE_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_BRIDGE) #define IS_XBRIDGE_OR_PIC_SOFT(ps) (IS_XBRIDGE_SOFT(ps) || IS_PIC_SOFT(ps)) @@ -348,13 +348,13 @@ struct pcibr_intr_wrap_s { */ struct pcibr_soft_s { - devfs_handle_t bs_conn; /* xtalk connection point */ - devfs_handle_t bs_vhdl; /* vertex owned by pcibr */ + vertex_hdl_t bs_conn; /* xtalk connection point */ + vertex_hdl_t bs_vhdl; /* vertex owned by pcibr */ uint64_t bs_int_enable; /* Mask of enabled intrs */ bridge_t *bs_base; /* PIO pointer to Bridge chip */ char *bs_name; /* hw graph name */ xwidgetnum_t bs_xid; /* Bridge's xtalk ID number */ - devfs_handle_t bs_master; /* xtalk master vertex */ + vertex_hdl_t bs_master; /* xtalk master vertex */ xwidgetnum_t bs_mxid; /* master's xtalk ID number */ pciio_slot_t bs_first_slot; /* first existing slot */ pciio_slot_t bs_last_slot; /* last existing slot */ @@ -372,9 +372,6 @@ struct pcibr_soft_s { short bs_int_ate_size; /* number of internal ates */ short bs_bridge_type; /* see defines above */ short bs_bridge_mode; /* see defines above */ -#ifdef CONFIG_IA64_SGI_SN1 -#define bs_xbridge bs_bridge_type -#endif int bs_rev_num; /* revision number of Bridge */ /* bs_dma_flags are the forced dma flags used on all DMAs. Used for @@ -382,9 +379,6 @@ struct pcibr_soft_s { */ unsigned bs_dma_flags; /* forced DMA flags */ -#ifdef CONFIG_IA64_SGI_SN1 - l1sc_t *bs_l1sc; /* io brick l1 system cntr */ -#endif moduleid_t bs_moduleid; /* io brick moduleid */ short bs_bricktype; /* io brick type */ @@ -394,7 +388,7 @@ struct pcibr_soft_s { */ spinlock_t bs_lock; - devfs_handle_t bs_noslot_conn; /* NO-SLOT connection point */ + vertex_hdl_t bs_noslot_conn; /* NO-SLOT connection point */ pcibr_info_t bs_noslot_info; struct pcibr_soft_slot_s { /* information we keep about each CFG slot */ @@ -411,7 +405,7 @@ struct pcibr_soft_s { */ int has_host; pciio_slot_t host_slot; - devfs_handle_t slot_conn; + vertex_hdl_t slot_conn; /* PCI Hot-Plug status word */ int slot_status; @@ -531,13 +525,8 @@ struct pcibr_soft_s { int bs_rrb_avail[2]; int bs_rrb_res[8]; int bs_rrb_res_dflt[8]; -#ifdef CONFIG_IA64_SGI_SN1 - int bs_rrb_valid[16]; - int bs_rrb_valid_dflt[16]; -#else int bs_rrb_valid[8][4]; int bs_rrb_valid_dflt[8][4]; -#endif struct { /* Each Bridge interrupt bit has a single XIO * interrupt channel allocated. @@ -578,7 +567,7 @@ struct pcibr_soft_s { #ifdef LATER toid_t bserr_toutid; /* Timeout started by errintr */ #endif /* LATER */ - iopaddr_t bserr_addr; /* Address where error occurred */ + iopaddr_t bserr_addr; /* Address where error occured */ uint64_t bserr_intstat; /* interrupts active at error dump */ } bs_errinfo; @@ -599,16 +588,6 @@ struct pcibr_soft_s { * in Megabytes), and they generally tend to take once and never * release. */ -#ifdef CONFIG_IA64_SGI_SN1 - struct br_pcisp_info { - iopaddr_t pci_io_base; - iopaddr_t pci_io_last; - iopaddr_t pci_swin_base; - iopaddr_t pci_swin_last; - iopaddr_t pci_mem_base; - iopaddr_t pci_mem_last; - } bs_spinfo; -#endif /* CONFIG_IA64_SGI_SN1 */ struct pciio_win_map_s bs_io_win_map; /* I/O addr space */ struct pciio_win_map_s bs_swin_map; /* Small window addr space */ struct pciio_win_map_s bs_mem_win_map; /* Memory addr space */ @@ -655,8 +634,6 @@ struct pcibr_hints_s { pcibr_intr_bits_f *ph_intr_bits; /* map PCI INT[ABCD] to Bridge Int(n) */ }; -extern int pcibr_prefetch_enable_rev, pcibr_wg_enable_rev; - /* * Number of bridge non-fatal error interrupts we can see before * we decide to disable that interrupt. @@ -689,7 +666,6 @@ extern int pcibr_prefetch_enable_rev, pcibr_wg_enable_rev; #define NEW(ptr) NEWA(ptr,1) #define DEL(ptr) DELA(ptr,1) -#ifndef CONFIG_IA64_SGI_SN1 /* * Additional PIO spaces per slot are * recorded in this structure. @@ -701,7 +677,6 @@ struct pciio_piospace_s { iopaddr_t start; /* Starting address of the PIO space */ size_t count; /* size of PIO space */ }; -#endif /* CONFIG_IA64_SGI_SN1 */ /* Use io spin locks. This ensures that all the PIO writes from a particular * CPU to a particular IO device are synched before the start of the next @@ -715,11 +690,9 @@ struct pciio_piospace_s { #define pcibr_unlock(pcibr_soft, s) #endif /* PCI_LATER */ -#ifndef CONFIG_IA64_SGI_SN1 #define PCIBR_VALID_SLOT(ps, s) (s < PCIBR_NUM_SLOTS(ps)) #define PCIBR_D64_BASE_UNSET (0xFFFFFFFFFFFFFFFF) #define PCIBR_D32_BASE_UNSET (0xFFFFFFFF) -#endif #define INFO_LBL_PCIBR_ASIC_REV "_pcibr_asic_rev" #define PCIBR_SOFT_LIST 1 @@ -728,8 +701,35 @@ typedef struct pcibr_list_s *pcibr_list_p; struct pcibr_list_s { pcibr_list_p bl_next; pcibr_soft_t bl_soft; - devfs_handle_t bl_vhdl; + vertex_hdl_t bl_vhdl; }; #endif /* PCIBR_SOFT_LIST */ + +// Devices per widget: 2 buses, 2 slots per bus, 8 functions per slot. +#define DEV_PER_WIDGET (2*2*8) + +struct sn_flush_device_list { + int bus; + int pin; + struct bar_list { + unsigned long start; + unsigned long end; + } bar_list[PCI_ROM_RESOURCE]; + unsigned long force_int_addr; + volatile unsigned long flush_addr; + spinlock_t flush_lock; +}; + +struct sn_flush_nasid_entry { + struct sn_flush_device_list **widget_p; + unsigned long iio_itte1; + unsigned long iio_itte2; + unsigned long iio_itte3; + unsigned long iio_itte4; + unsigned long iio_itte5; + unsigned long iio_itte6; + unsigned long iio_itte7; +}; + #endif /* _ASM_SN_PCI_PCIBR_PRIVATE_H */ diff --git a/include/asm-ia64/sn/pci/pciio.h b/include/asm-ia64/sn/pci/pciio.h index b48737b2800b8..e7f47d3240bc5 100644 --- a/include/asm-ia64/sn/pci/pciio.h +++ b/include/asm-ia64/sn/pci/pciio.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCIIO_H #define _ASM_SN_PCI_PCIIO_H @@ -277,7 +277,7 @@ typedef struct pciio_win_alloc_s *pciio_win_alloc_t; #define PCIIO_PIOMAP_WIN(n) (0x8+(n)) typedef pciio_piomap_t -pciio_piomap_alloc_f (devfs_handle_t dev, /* set up mapping for this device */ +pciio_piomap_alloc_f (vertex_hdl_t dev, /* set up mapping for this device */ device_desc_t dev_desc, /* device descriptor */ pciio_space_t space, /* which address space */ iopaddr_t pcipio_addr, /* starting address */ @@ -297,7 +297,7 @@ typedef void pciio_piomap_done_f (pciio_piomap_t pciio_piomap); typedef caddr_t -pciio_piotrans_addr_f (devfs_handle_t dev, /* translate for this device */ +pciio_piotrans_addr_f (vertex_hdl_t dev, /* translate for this device */ device_desc_t dev_desc, /* device descriptor */ pciio_space_t space, /* which address space */ iopaddr_t pciio_addr, /* starting address */ @@ -305,7 +305,7 @@ pciio_piotrans_addr_f (devfs_handle_t dev, /* translate for this device */ unsigned flags); typedef caddr_t -pciio_pio_addr_f (devfs_handle_t dev, /* translate for this device */ +pciio_pio_addr_f (vertex_hdl_t dev, /* translate for this device */ device_desc_t dev_desc, /* device descriptor */ pciio_space_t space, /* which address space */ iopaddr_t pciio_addr, /* starting address */ @@ -314,14 +314,14 @@ pciio_pio_addr_f (devfs_handle_t dev, /* translate for this device */ unsigned flags); typedef iopaddr_t -pciio_piospace_alloc_f (devfs_handle_t dev, /* PIO space for this device */ +pciio_piospace_alloc_f (vertex_hdl_t dev, /* PIO space for this device */ device_desc_t dev_desc, /* Device descriptor */ pciio_space_t space, /* which address space */ size_t byte_count, /* Number of bytes of space */ size_t alignment); /* Alignment of allocation */ typedef void -pciio_piospace_free_f (devfs_handle_t dev, /* Device freeing space */ +pciio_piospace_free_f (vertex_hdl_t dev, /* Device freeing space */ pciio_space_t space, /* Which space is freed */ iopaddr_t pci_addr, /* Address being freed */ size_t size); /* Size freed */ @@ -329,7 +329,7 @@ pciio_piospace_free_f (devfs_handle_t dev, /* Device freeing space */ /* DMA MANAGEMENT */ typedef pciio_dmamap_t -pciio_dmamap_alloc_f (devfs_handle_t dev, /* set up mappings for this device */ +pciio_dmamap_alloc_f (vertex_hdl_t dev, /* set up mappings for this device */ device_desc_t dev_desc, /* device descriptor */ size_t byte_count_max, /* max size of a mapping */ unsigned flags); /* defined in dma.h */ @@ -342,123 +342,107 @@ pciio_dmamap_addr_f (pciio_dmamap_t dmamap, /* use these mapping resources paddr_t paddr, /* map for this address */ size_t byte_count); /* map this many bytes */ -typedef alenlist_t -pciio_dmamap_list_f (pciio_dmamap_t dmamap, /* use these mapping resources */ - alenlist_t alenlist, /* map this address/length list */ - unsigned flags); - typedef void pciio_dmamap_done_f (pciio_dmamap_t dmamap); typedef iopaddr_t -pciio_dmatrans_addr_f (devfs_handle_t dev, /* translate for this device */ +pciio_dmatrans_addr_f (vertex_hdl_t dev, /* translate for this device */ device_desc_t dev_desc, /* device descriptor */ paddr_t paddr, /* system physical address */ size_t byte_count, /* length */ unsigned flags); /* defined in dma.h */ -typedef alenlist_t -pciio_dmatrans_list_f (devfs_handle_t dev, /* translate for this device */ - device_desc_t dev_desc, /* device descriptor */ - alenlist_t palenlist, /* system address/length list */ - unsigned flags); /* defined in dma.h */ - typedef void pciio_dmamap_drain_f (pciio_dmamap_t map); typedef void -pciio_dmaaddr_drain_f (devfs_handle_t vhdl, +pciio_dmaaddr_drain_f (vertex_hdl_t vhdl, paddr_t addr, size_t bytes); typedef void -pciio_dmalist_drain_f (devfs_handle_t vhdl, +pciio_dmalist_drain_f (vertex_hdl_t vhdl, alenlist_t list); /* INTERRUPT MANAGEMENT */ typedef pciio_intr_t -pciio_intr_alloc_f (devfs_handle_t dev, /* which PCI device */ +pciio_intr_alloc_f (vertex_hdl_t dev, /* which PCI device */ device_desc_t dev_desc, /* device descriptor */ pciio_intr_line_t lines, /* which line(s) will be used */ - devfs_handle_t owner_dev); /* owner of this intr */ + vertex_hdl_t owner_dev); /* owner of this intr */ typedef void pciio_intr_free_f (pciio_intr_t intr_hdl); -#ifdef CONFIG_IA64_SGI_SN1 -typedef int -pciio_intr_connect_f (pciio_intr_t intr_hdl); /* pciio intr resource handle */ -#else typedef int pciio_intr_connect_f (pciio_intr_t intr_hdl, intr_func_t intr_func, intr_arg_t intr_arg); /* pciio intr resource handle */ -#endif typedef void pciio_intr_disconnect_f (pciio_intr_t intr_hdl); -typedef devfs_handle_t +typedef vertex_hdl_t pciio_intr_cpu_get_f (pciio_intr_t intr_hdl); /* pciio intr resource handle */ /* CONFIGURATION MANAGEMENT */ typedef void -pciio_provider_startup_f (devfs_handle_t pciio_provider); +pciio_provider_startup_f (vertex_hdl_t pciio_provider); typedef void -pciio_provider_shutdown_f (devfs_handle_t pciio_provider); +pciio_provider_shutdown_f (vertex_hdl_t pciio_provider); typedef int -pciio_reset_f (devfs_handle_t conn); /* pci connection point */ +pciio_reset_f (vertex_hdl_t conn); /* pci connection point */ typedef int -pciio_write_gather_flush_f (devfs_handle_t dev); /* Device flushing buffers */ +pciio_write_gather_flush_f (vertex_hdl_t dev); /* Device flushing buffers */ typedef pciio_endian_t /* actual endianness */ -pciio_endian_set_f (devfs_handle_t dev, /* specify endianness for this device */ +pciio_endian_set_f (vertex_hdl_t dev, /* specify endianness for this device */ pciio_endian_t device_end, /* endianness of device */ pciio_endian_t desired_end); /* desired endianness */ typedef pciio_priority_t -pciio_priority_set_f (devfs_handle_t pcicard, +pciio_priority_set_f (vertex_hdl_t pcicard, pciio_priority_t device_prio); typedef uint64_t -pciio_config_get_f (devfs_handle_t conn, /* pci connection point */ +pciio_config_get_f (vertex_hdl_t conn, /* pci connection point */ unsigned reg, /* register byte offset */ unsigned size); /* width in bytes (1..4) */ typedef void -pciio_config_set_f (devfs_handle_t conn, /* pci connection point */ +pciio_config_set_f (vertex_hdl_t conn, /* pci connection point */ unsigned reg, /* register byte offset */ unsigned size, /* width in bytes (1..4) */ uint64_t value); /* value to store */ typedef int -pciio_error_devenable_f (devfs_handle_t pconn_vhdl, int error_code); +pciio_error_devenable_f (vertex_hdl_t pconn_vhdl, int error_code); typedef pciio_slot_t -pciio_error_extract_f (devfs_handle_t vhdl, +pciio_error_extract_f (vertex_hdl_t vhdl, pciio_space_t *spacep, iopaddr_t *addrp); typedef void -pciio_driver_reg_callback_f (devfs_handle_t conn, +pciio_driver_reg_callback_f (vertex_hdl_t conn, int key1, int key2, int error); typedef void -pciio_driver_unreg_callback_f (devfs_handle_t conn, /* pci connection point */ +pciio_driver_unreg_callback_f (vertex_hdl_t conn, /* pci connection point */ int key1, int key2, int error); typedef int -pciio_device_unregister_f (devfs_handle_t conn); +pciio_device_unregister_f (vertex_hdl_t conn); typedef int -pciio_dma_enabled_f (devfs_handle_t conn); +pciio_dma_enabled_f (vertex_hdl_t conn); /* * Adapters that provide a PCI interface adhere to this software interface. @@ -477,10 +461,8 @@ typedef struct pciio_provider_s { pciio_dmamap_alloc_f *dmamap_alloc; pciio_dmamap_free_f *dmamap_free; pciio_dmamap_addr_f *dmamap_addr; - pciio_dmamap_list_f *dmamap_list; pciio_dmamap_done_f *dmamap_done; pciio_dmatrans_addr_f *dmatrans_addr; - pciio_dmatrans_list_f *dmatrans_list; pciio_dmamap_drain_f *dmamap_drain; pciio_dmaaddr_drain_f *dmaaddr_drain; pciio_dmalist_drain_f *dmalist_drain; @@ -525,10 +507,8 @@ extern pciio_piospace_free_f pciio_piospace_free; extern pciio_dmamap_alloc_f pciio_dmamap_alloc; extern pciio_dmamap_free_f pciio_dmamap_free; extern pciio_dmamap_addr_f pciio_dmamap_addr; -extern pciio_dmamap_list_f pciio_dmamap_list; extern pciio_dmamap_done_f pciio_dmamap_done; extern pciio_dmatrans_addr_f pciio_dmatrans_addr; -extern pciio_dmatrans_list_f pciio_dmatrans_list; extern pciio_dmamap_drain_f pciio_dmamap_drain; extern pciio_dmaaddr_drain_f pciio_dmaaddr_drain; extern pciio_dmalist_drain_f pciio_dmalist_drain; @@ -580,34 +560,31 @@ pciio_driver_register (pciio_vendor_id_t vendor_id, /* card's vendor number */ unsigned flags); extern void -pciio_error_register (devfs_handle_t pconn, /* which slot */ +pciio_error_register (vertex_hdl_t pconn, /* which slot */ error_handler_f *efunc, /* function to call */ error_handler_arg_t einfo); /* first parameter */ extern void pciio_driver_unregister(char *driver_prefix); -typedef void pciio_iter_f(devfs_handle_t pconn); /* a connect point */ - -extern void pciio_iterate(char *driver_prefix, - pciio_iter_f *func); +typedef void pciio_iter_f(vertex_hdl_t pconn); /* a connect point */ /* Interfaces used by PCI Bus Providers to talk to * the Generic PCI layer. */ -extern devfs_handle_t -pciio_device_register (devfs_handle_t connectpt, /* vertex at center of bus */ - devfs_handle_t master, /* card's master ASIC (pci provider) */ +extern vertex_hdl_t +pciio_device_register (vertex_hdl_t connectpt, /* vertex at center of bus */ + vertex_hdl_t master, /* card's master ASIC (pci provider) */ pciio_slot_t slot, /* card's slot (0..?) */ pciio_function_t func, /* card's func (0..?) */ pciio_vendor_id_t vendor, /* card's vendor number */ pciio_device_id_t device); /* card's device number */ extern void -pciio_device_unregister(devfs_handle_t connectpt); +pciio_device_unregister(vertex_hdl_t connectpt); extern pciio_info_t pciio_device_info_new (pciio_info_t pciio_info, /* preallocated info struct */ - devfs_handle_t master, /* card's master ASIC (pci provider) */ + vertex_hdl_t master, /* card's master ASIC (pci provider) */ pciio_slot_t slot, /* card's slot (0..?) */ pciio_function_t func, /* card's func (0..?) */ pciio_vendor_id_t vendor, /* card's vendor number */ @@ -616,24 +593,24 @@ pciio_device_info_new (pciio_info_t pciio_info, /* preallocated info struct */ extern void pciio_device_info_free(pciio_info_t pciio_info); -extern devfs_handle_t +extern vertex_hdl_t pciio_device_info_register( - devfs_handle_t connectpt, /* vertex at center of bus */ + vertex_hdl_t connectpt, /* vertex at center of bus */ pciio_info_t pciio_info); /* details about conn point */ extern void pciio_device_info_unregister( - devfs_handle_t connectpt, /* vertex at center of bus */ + vertex_hdl_t connectpt, /* vertex at center of bus */ pciio_info_t pciio_info); /* details about conn point */ extern int pciio_device_attach( - devfs_handle_t pcicard, /* vertex created by pciio_device_register */ + vertex_hdl_t pcicard, /* vertex created by pciio_device_register */ int drv_flags); extern int pciio_device_detach( - devfs_handle_t pcicard, /* vertex created by pciio_device_register */ + vertex_hdl_t pcicard, /* vertex created by pciio_device_register */ int drv_flags); @@ -654,20 +631,12 @@ pciio_device_win_populate(pciio_win_map_t win_map, /* win map */ size_t size); /* size of free range */ /* allocate window from mapping resource */ -#ifdef CONFIG_IA64_SGI_SN1 -extern iopaddr_t -pciio_device_win_alloc(pciio_win_map_t win_map, /* win map */ - pciio_win_alloc_t win_alloc, /* opaque allocation cookie */ - size_t size, /* size of allocation */ - size_t align); /* alignment of allocation */ -#else extern iopaddr_t pciio_device_win_alloc(pciio_win_map_t win_map, /* win map */ pciio_win_alloc_t win_alloc, /* opaque allocation cookie */ size_t start, /* start unit, or 0 */ size_t size, /* size of allocation */ size_t align); /* alignment of allocation */ -#endif /* free previously allocated window */ extern void @@ -680,11 +649,11 @@ pciio_device_win_free(pciio_win_alloc_t win_alloc); /* opaque allocation cookie */ /* Generic PCI interrupt interfaces */ -extern devfs_handle_t pciio_intr_dev_get(pciio_intr_t pciio_intr); -extern devfs_handle_t pciio_intr_cpu_get(pciio_intr_t pciio_intr); +extern vertex_hdl_t pciio_intr_dev_get(pciio_intr_t pciio_intr); +extern vertex_hdl_t pciio_intr_cpu_get(pciio_intr_t pciio_intr); /* Generic PCI pio interfaces */ -extern devfs_handle_t pciio_pio_dev_get(pciio_piomap_t pciio_piomap); +extern vertex_hdl_t pciio_pio_dev_get(pciio_piomap_t pciio_piomap); extern pciio_slot_t pciio_pio_slot_get(pciio_piomap_t pciio_piomap); extern pciio_space_t pciio_pio_space_get(pciio_piomap_t pciio_piomap); extern iopaddr_t pciio_pio_pciaddr_get(pciio_piomap_t pciio_piomap); @@ -692,26 +661,26 @@ extern ulong pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap); extern caddr_t pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap); /* Generic PCI dma interfaces */ -extern devfs_handle_t pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap); +extern vertex_hdl_t pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap); /* Register/unregister PCI providers and get implementation handle */ -extern void pciio_provider_register(devfs_handle_t provider, pciio_provider_t *pciio_fns); -extern void pciio_provider_unregister(devfs_handle_t provider); -extern pciio_provider_t *pciio_provider_fns_get(devfs_handle_t provider); +extern void pciio_provider_register(vertex_hdl_t provider, pciio_provider_t *pciio_fns); +extern void pciio_provider_unregister(vertex_hdl_t provider); +extern pciio_provider_t *pciio_provider_fns_get(vertex_hdl_t provider); /* Generic pci slot information access interface */ -extern pciio_info_t pciio_info_chk(devfs_handle_t vhdl); -extern pciio_info_t pciio_info_get(devfs_handle_t vhdl); -extern pciio_info_t pciio_hostinfo_get(devfs_handle_t vhdl); -extern void pciio_info_set(devfs_handle_t vhdl, pciio_info_t widget_info); -extern devfs_handle_t pciio_info_dev_get(pciio_info_t pciio_info); -extern devfs_handle_t pciio_info_hostdev_get(pciio_info_t pciio_info); +extern pciio_info_t pciio_info_chk(vertex_hdl_t vhdl); +extern pciio_info_t pciio_info_get(vertex_hdl_t vhdl); +extern pciio_info_t pciio_hostinfo_get(vertex_hdl_t vhdl); +extern void pciio_info_set(vertex_hdl_t vhdl, pciio_info_t widget_info); +extern vertex_hdl_t pciio_info_dev_get(pciio_info_t pciio_info); +extern vertex_hdl_t pciio_info_hostdev_get(pciio_info_t pciio_info); extern pciio_bus_t pciio_info_bus_get(pciio_info_t pciio_info); extern pciio_slot_t pciio_info_slot_get(pciio_info_t pciio_info); extern pciio_function_t pciio_info_function_get(pciio_info_t pciio_info); extern pciio_vendor_id_t pciio_info_vendor_id_get(pciio_info_t pciio_info); extern pciio_device_id_t pciio_info_device_id_get(pciio_info_t pciio_info); -extern devfs_handle_t pciio_info_master_get(pciio_info_t pciio_info); +extern vertex_hdl_t pciio_info_master_get(pciio_info_t pciio_info); extern arbitrary_info_t pciio_info_mfast_get(pciio_info_t pciio_info); extern pciio_provider_t *pciio_info_pops_get(pciio_info_t pciio_info); extern error_handler_f *pciio_info_efunc_get(pciio_info_t); @@ -722,8 +691,8 @@ extern size_t pciio_info_bar_size_get(pciio_info_t, int); extern iopaddr_t pciio_info_rom_base_get(pciio_info_t); extern size_t pciio_info_rom_size_get(pciio_info_t); extern int pciio_info_type1_get(pciio_info_t); -extern int pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *); -extern int pciio_dma_enabled(devfs_handle_t); +extern int pciio_error_handler(vertex_hdl_t, int, ioerror_mode_t, ioerror_t *); +extern int pciio_dma_enabled(vertex_hdl_t); #endif /* C or C++ */ #endif /* _ASM_SN_PCI_PCIIO_H */ diff --git a/include/asm-ia64/sn/pci/pciio_private.h b/include/asm-ia64/sn/pci/pciio_private.h index 57fbd9787152d..4ae63322d60c8 100644 --- a/include/asm-ia64/sn/pci/pciio_private.h +++ b/include/asm-ia64/sn/pci/pciio_private.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCIIO_PRIVATE_H #define _ASM_SN_PCI_PCIIO_PRIVATE_H @@ -24,7 +24,7 @@ */ struct pciio_piomap_s { unsigned pp_flags; /* PCIIO_PIOMAP flags */ - devfs_handle_t pp_dev; /* associated pci card */ + vertex_hdl_t pp_dev; /* associated pci card */ pciio_slot_t pp_slot; /* which slot the card is in */ pciio_space_t pp_space; /* which address space */ iopaddr_t pp_pciaddr; /* starting offset of mapping */ @@ -37,7 +37,7 @@ struct pciio_piomap_s { */ struct pciio_dmamap_s { unsigned pd_flags; /* PCIIO_DMAMAP flags */ - devfs_handle_t pd_dev; /* associated pci card */ + vertex_hdl_t pd_dev; /* associated pci card */ pciio_slot_t pd_slot; /* which slot the card is in */ }; @@ -47,7 +47,7 @@ struct pciio_dmamap_s { struct pciio_intr_s { unsigned pi_flags; /* PCIIO_INTR flags */ - devfs_handle_t pi_dev; /* associated pci card */ + vertex_hdl_t pi_dev; /* associated pci card */ device_desc_t pi_dev_desc; /* override device descriptor */ pciio_intr_line_t pi_lines; /* which interrupt line(s) */ intr_func_t pi_func; /* handler function (when connected) */ @@ -100,13 +100,13 @@ struct pciio_win_alloc_s { struct pciio_info_s { char *c_fingerprint; - devfs_handle_t c_vertex; /* back pointer to vertex */ + vertex_hdl_t c_vertex; /* back pointer to vertex */ pciio_bus_t c_bus; /* which bus the card is in */ pciio_slot_t c_slot; /* which slot the card is in */ pciio_function_t c_func; /* which func (on multi-func cards) */ pciio_vendor_id_t c_vendor; /* PCI card "vendor" code */ pciio_device_id_t c_device; /* PCI card "device" code */ - devfs_handle_t c_master; /* PCI bus provider */ + vertex_hdl_t c_master; /* PCI bus provider */ arbitrary_info_t c_mfast; /* cached fastinfo from c_master */ pciio_provider_t *c_pops; /* cached provider from c_master */ error_handler_f *c_efunc; /* error handling function */ |