6.1-stable patches

added patches:
	drm-amd-display-fix-disable-otg-wa-logic-in-dcn316.patch
	drm-amdgpu-always-force-full-reset-for-soc21.patch
	drm-amdgpu-reset-dgpu-if-suspend-got-aborted.patch
	drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch
	drm-i915-disable-port-sync-when-bigjoiner-is-used.patch

6 files changed, 323 insertions, 0 deletions

diff --git a/queue-6.1/drm-amd-display-fix-disable-otg-wa-logic-in-dcn316.patch b/queue-6.1/drm-amd-display-fix-disable-otg-wa-logic-in-dcn316.patch
new file mode 100644
index 0000000000..e286a2e6ab
--- /dev/null
+++ b/queue-6.1/drm-amd-display-fix-disable-otg-wa-logic-in-dcn316.patch
@@ -0,0 +1,72 @@
+From cf79814cb0bf5749b9f0db53ca231aa540c02768 Mon Sep 17 00:00:00 2001
+From: Fudongwang <fudong.wang@amd.com>
+Date: Tue, 26 Mar 2024 16:03:16 +0800
+Subject: drm/amd/display: fix disable otg wa logic in DCN316
+
+From: Fudongwang <fudong.wang@amd.com>
+
+commit cf79814cb0bf5749b9f0db53ca231aa540c02768 upstream.
+
+[Why]
+Wrong logic cause screen corruption.
+
+[How]
+Port logic from DCN35/314.
+
+Cc: stable@vger.kernel.org
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
+Signed-off-by: Fudongwang <fudong.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c |   19 ++++++----
+ 1 file changed, 12 insertions(+), 7 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+@@ -112,20 +112,25 @@ static int dcn316_get_active_display_cnt
+ 	return display_count;
+ }
+ 
+-static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
++static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
++		bool safe_to_lower, bool disable)
+ {
+ 	struct dc *dc = clk_mgr_base->ctx->dc;
+ 	int i;
+ 
+ 	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
+-		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
++		struct pipe_ctx *pipe = safe_to_lower
++			? &context->res_ctx.pipe_ctx[i]
++			: &dc->current_state->res_ctx.pipe_ctx[i];
+ 
+ 		if (pipe->top_pipe || pipe->prev_odm_pipe)
+ 			continue;
+-		if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
+-				     dc_is_virtual_signal(pipe->stream->signal))) {
++		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||
++				     !pipe->stream->link_enc)) {
+ 			if (disable) {
+-				pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
++				if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
++					pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
++
+ 				reset_sync_context_for_pipe(dc, context, i);
+ 			} else
+ 				pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
+@@ -222,11 +227,11 @@ static void dcn316_update_clocks(struct
+ 	}
+ 
+ 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
+-		dcn316_disable_otg_wa(clk_mgr_base, context, true);
++		dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
+ 
+ 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
+ 		dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
+-		dcn316_disable_otg_wa(clk_mgr_base, context, false);
++		dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
+ 
+ 		update_dispclk = true;
+ 	}
diff --git a/queue-6.1/drm-amdgpu-always-force-full-reset-for-soc21.patch b/queue-6.1/drm-amdgpu-always-force-full-reset-for-soc21.patch
new file mode 100644
index 0000000000..a938324622
--- /dev/null
+++ b/queue-6.1/drm-amdgpu-always-force-full-reset-for-soc21.patch
@@ -0,0 +1,33 @@
+From 65ff8092e4802f96d87d3d7cde146961f5228265 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Sat, 23 Mar 2024 20:46:53 -0400
+Subject: drm/amdgpu: always force full reset for SOC21
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 65ff8092e4802f96d87d3d7cde146961f5228265 upstream.
+
+There are cases where soft reset seems to succeed, but
+does not, so always use mode1/2 for now.
+
+Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/soc21.c |    2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
+@@ -460,10 +460,8 @@ static bool soc21_need_full_reset(struct
+ {
+ 	switch (adev->ip_versions[GC_HWIP][0]) {
+ 	case IP_VERSION(11, 0, 0):
+-		return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC);
+ 	case IP_VERSION(11, 0, 2):
+ 	case IP_VERSION(11, 0, 3):
+-		return false;
+ 	default:
+ 		return true;
+ 	}
diff --git a/queue-6.1/drm-amdgpu-reset-dgpu-if-suspend-got-aborted.patch b/queue-6.1/drm-amdgpu-reset-dgpu-if-suspend-got-aborted.patch
new file mode 100644
index 0000000000..0322fb0235
--- /dev/null
+++ b/queue-6.1/drm-amdgpu-reset-dgpu-if-suspend-got-aborted.patch
@@ -0,0 +1,62 @@
+From 8b2be55f4d6c1099d7f629b0ed7535a5be788c83 Mon Sep 17 00:00:00 2001
+From: Lijo Lazar <lijo.lazar@amd.com>
+Date: Wed, 14 Feb 2024 17:55:54 +0530
+Subject: drm/amdgpu: Reset dGPU if suspend got aborted
+
+From: Lijo Lazar <lijo.lazar@amd.com>
+
+commit 8b2be55f4d6c1099d7f629b0ed7535a5be788c83 upstream.
+
+For SOC21 ASICs, there is an issue in re-enabling PM features if a
+suspend got aborted. In such cases, reset the device during resume
+phase. This is a workaround till a proper solution is finalized.
+
+Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/soc21.c |   25 +++++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
+@@ -780,10 +780,35 @@ static int soc21_common_suspend(void *ha
+ 	return soc21_common_hw_fini(adev);
+ }
+ 
++static bool soc21_need_reset_on_resume(struct amdgpu_device *adev)
++{
++	u32 sol_reg1, sol_reg2;
++
++	/* Will reset for the following suspend abort cases.
++	 * 1) Only reset dGPU side.
++	 * 2) S3 suspend got aborted and TOS is active.
++	 */
++	if (!(adev->flags & AMD_IS_APU) && adev->in_s3 &&
++	    !adev->suspend_complete) {
++		sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
++		msleep(100);
++		sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
++
++		return (sol_reg1 != sol_reg2);
++	}
++
++	return false;
++}
++
+ static int soc21_common_resume(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
++	if (soc21_need_reset_on_resume(adev)) {
++		dev_info(adev->dev, "S3 suspend aborted, resetting...");
++		soc21_asic_reset(adev);
++	}
++
+ 	return soc21_common_hw_init(adev);
+ }
+ 
diff --git a/queue-6.1/drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch b/queue-6.1/drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch
new file mode 100644
index 0000000000..b96d266cbe
--- /dev/null
+++ b/queue-6.1/drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch
@@ -0,0 +1,106 @@
+From 7b1f6b5aaec0f849e19c3e99d4eea75876853cdd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Tue, 2 Apr 2024 18:50:03 +0300
+Subject: drm/i915/cdclk: Fix CDCLK programming order when pipes are active
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 7b1f6b5aaec0f849e19c3e99d4eea75876853cdd upstream.
+
+Currently we always reprogram CDCLK from the
+intel_set_cdclk_pre_plane_update() when using squash/crawl.
+The code only works correctly for the cd2x update or full
+modeset cases, and it was simply never updated to deal with
+squash/crawl.
+
+If the CDCLK frequency is increasing we must reprogram it
+before we do anything else that might depend on the new
+higher frequency, and conversely we must not decrease
+the frequency until everything that might still depend
+on the old higher frequency has been dealt with.
+
+Since cdclk_state->pipe is only relevant when doing a cd2x
+update we can't use it to determine the correct sequence
+during squash/crawl. To that end introduce cdclk_state->disable_pipes
+which simply indicates that we must perform the update
+while the pipes are disable (ie. during
+intel_set_cdclk_pre_plane_update()). Otherwise we use the
+same old vs. new CDCLK frequency comparsiong as for cd2x
+updates.
+
+The only remaining problem case is when the voltage_level
+needs to increase due to a DDI port, but the CDCLK frequency
+is decreasing (and not all pipes are being disabled). The
+current approach will not bump the voltage level up until
+after the port has already been enabled, which is too late.
+But we'll take care of that case separately.
+
+v2: Don't break the "must disable pipes case"
+v3: Keep the on stack 'pipe' for future use
+
+Cc: stable@vger.kernel.org
+Fixes: d62686ba3b54 ("drm/i915/adl_p: CDCLK crawl support for ADL")
+Reviewed-by: Uma Shankar <uma.shankar@intel.com>
+Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240402155016.13733-2-ville.syrjala@linux.intel.com
+(cherry picked from commit 3aecee90ac12a351905f12dda7643d5b0676d6ca)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_cdclk.c |    7 +++++--
+ drivers/gpu/drm/i915/display/intel_cdclk.h |    3 +++
+ 2 files changed, 8 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
++++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
+@@ -2152,7 +2152,7 @@ intel_set_cdclk_pre_plane_update(struct
+ 				 &new_cdclk_state->actual))
+ 		return;
+ 
+-	if (pipe == INVALID_PIPE ||
++	if (new_cdclk_state->disable_pipes ||
+ 	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
+ 		drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
+ 
+@@ -2181,7 +2181,7 @@ intel_set_cdclk_post_plane_update(struct
+ 				 &new_cdclk_state->actual))
+ 		return;
+ 
+-	if (pipe != INVALID_PIPE &&
++	if (!new_cdclk_state->disable_pipes &&
+ 	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
+ 		drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
+ 
+@@ -2634,6 +2634,7 @@ static struct intel_global_state *intel_
+ 		return NULL;
+ 
+ 	cdclk_state->pipe = INVALID_PIPE;
++	cdclk_state->disable_pipes = false;
+ 
+ 	return &cdclk_state->base;
+ }
+@@ -2793,6 +2794,8 @@ int intel_modeset_calc_cdclk(struct inte
+ 		if (ret)
+ 			return ret;
+ 
++		new_cdclk_state->disable_pipes = true;
++
+ 		drm_dbg_kms(&dev_priv->drm,
+ 			    "Modeset required for cdclk change\n");
+ 	}
+--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
++++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
+@@ -51,6 +51,9 @@ struct intel_cdclk_state {
+ 
+ 	/* bitmask of active pipes */
+ 	u8 active_pipes;
++
++	/* update cdclk with pipes disabled */
++	bool disable_pipes;
+ };
+ 
+ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
diff --git a/queue-6.1/drm-i915-disable-port-sync-when-bigjoiner-is-used.patch b/queue-6.1/drm-i915-disable-port-sync-when-bigjoiner-is-used.patch
new file mode 100644
index 0000000000..724f809280
--- /dev/null
+++ b/queue-6.1/drm-i915-disable-port-sync-when-bigjoiner-is-used.patch
@@ -0,0 +1,45 @@
+From 0653d501409eeb9f1deb7e4c12e4d0d2c9f1cba1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Fri, 5 Apr 2024 00:34:27 +0300
+Subject: drm/i915: Disable port sync when bigjoiner is used
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 0653d501409eeb9f1deb7e4c12e4d0d2c9f1cba1 upstream.
+
+The current modeset sequence can't handle port sync and bigjoiner
+at the same time. Refuse port sync when bigjoiner is needed,
+at least until we fix the modeset sequence.
+
+v2: Add a FIXME (Vandite)
+
+Cc: stable@vger.kernel.org
+Tested-by: Vidya Srinivas <vidya.srinivas@intel.com>
+Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240404213441.17637-4-ville.syrjala@linux.intel.com
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+(cherry picked from commit b37e1347b991459c38c56ec2476087854a4f720b)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_ddi.c |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/gpu/drm/i915/display/intel_ddi.c
++++ b/drivers/gpu/drm/i915/display/intel_ddi.c
+@@ -3683,7 +3683,12 @@ static bool m_n_equal(const struct intel
+ static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
+ 				       const struct intel_crtc_state *crtc_state2)
+ {
++	/*
++	 * FIXME the modeset sequence is currently wrong and
++	 * can't deal with bigjoiner + port sync at the same time.
++	 */
+ 	return crtc_state1->hw.active && crtc_state2->hw.active &&
++		!crtc_state1->bigjoiner_pipes && !crtc_state2->bigjoiner_pipes &&
+ 		crtc_state1->output_types == crtc_state2->output_types &&
+ 		crtc_state1->output_format == crtc_state2->output_format &&
+ 		crtc_state1->lane_count == crtc_state2->lane_count &&
diff --git a/queue-6.1/series b/queue-6.1/series
index 51e8ee5357..e6b0936b2a 100644
--- a/queue-6.1/series
+++ b/queue-6.1/series
@@ -62,3 +62,8 @@ x86-bugs-fix-bhi-handling-of-rrsba.patch
 x86-bugs-clarify-that-syscall-hardening-isn-t-a-bhi-mitigation.patch
 x86-bugs-remove-config_bhi_mitigation_auto-and-spectre_bhi-auto.patch
 x86-bugs-replace-config_spectre_bhi_-on-off-with-config_mitigation_spectre_bhi.patch
+drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch
+drm-i915-disable-port-sync-when-bigjoiner-is-used.patch
+drm-amdgpu-reset-dgpu-if-suspend-got-aborted.patch
+drm-amdgpu-always-force-full-reset-for-soc21.patch
+drm-amd-display-fix-disable-otg-wa-logic-in-dcn316.patch