5.15-stable patches

added patches:
	drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch
	drm-i915-disable-port-sync-when-bigjoiner-is-used.patch

3 files changed, 153 insertions, 0 deletions

diff --git a/queue-5.15/drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch b/queue-5.15/drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch
new file mode 100644
index 0000000000..55225f0505
--- /dev/null
+++ b/queue-5.15/drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch
@@ -0,0 +1,106 @@
+From 7b1f6b5aaec0f849e19c3e99d4eea75876853cdd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Tue, 2 Apr 2024 18:50:03 +0300
+Subject: drm/i915/cdclk: Fix CDCLK programming order when pipes are active
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 7b1f6b5aaec0f849e19c3e99d4eea75876853cdd upstream.
+
+Currently we always reprogram CDCLK from the
+intel_set_cdclk_pre_plane_update() when using squash/crawl.
+The code only works correctly for the cd2x update or full
+modeset cases, and it was simply never updated to deal with
+squash/crawl.
+
+If the CDCLK frequency is increasing we must reprogram it
+before we do anything else that might depend on the new
+higher frequency, and conversely we must not decrease
+the frequency until everything that might still depend
+on the old higher frequency has been dealt with.
+
+Since cdclk_state->pipe is only relevant when doing a cd2x
+update we can't use it to determine the correct sequence
+during squash/crawl. To that end introduce cdclk_state->disable_pipes
+which simply indicates that we must perform the update
+while the pipes are disable (ie. during
+intel_set_cdclk_pre_plane_update()). Otherwise we use the
+same old vs. new CDCLK frequency comparsiong as for cd2x
+updates.
+
+The only remaining problem case is when the voltage_level
+needs to increase due to a DDI port, but the CDCLK frequency
+is decreasing (and not all pipes are being disabled). The
+current approach will not bump the voltage level up until
+after the port has already been enabled, which is too late.
+But we'll take care of that case separately.
+
+v2: Don't break the "must disable pipes case"
+v3: Keep the on stack 'pipe' for future use
+
+Cc: stable@vger.kernel.org
+Fixes: d62686ba3b54 ("drm/i915/adl_p: CDCLK crawl support for ADL")
+Reviewed-by: Uma Shankar <uma.shankar@intel.com>
+Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240402155016.13733-2-ville.syrjala@linux.intel.com
+(cherry picked from commit 3aecee90ac12a351905f12dda7643d5b0676d6ca)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_cdclk.c |    7 +++++--
+ drivers/gpu/drm/i915/display/intel_cdclk.h |    3 +++
+ 2 files changed, 8 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
++++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
+@@ -2000,7 +2000,7 @@ intel_set_cdclk_pre_plane_update(struct
+ 				 &new_cdclk_state->actual))
+ 		return;
+ 
+-	if (pipe == INVALID_PIPE ||
++	if (new_cdclk_state->disable_pipes ||
+ 	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
+ 		drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
+ 
+@@ -2029,7 +2029,7 @@ intel_set_cdclk_post_plane_update(struct
+ 				 &new_cdclk_state->actual))
+ 		return;
+ 
+-	if (pipe != INVALID_PIPE &&
++	if (!new_cdclk_state->disable_pipes &&
+ 	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
+ 		drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
+ 
+@@ -2456,6 +2456,7 @@ static struct intel_global_state *intel_
+ 		return NULL;
+ 
+ 	cdclk_state->pipe = INVALID_PIPE;
++	cdclk_state->disable_pipes = false;
+ 
+ 	return &cdclk_state->base;
+ }
+@@ -2575,6 +2576,8 @@ int intel_modeset_calc_cdclk(struct inte
+ 		if (ret)
+ 			return ret;
+ 
++		new_cdclk_state->disable_pipes = true;
++
+ 		drm_dbg_kms(&dev_priv->drm,
+ 			    "Modeset required for cdclk change\n");
+ 	}
+--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
++++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
+@@ -52,6 +52,9 @@ struct intel_cdclk_state {
+ 
+ 	/* bitmask of active pipes */
+ 	u8 active_pipes;
++
++	/* update cdclk with pipes disabled */
++	bool disable_pipes;
+ };
+ 
+ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
diff --git a/queue-5.15/drm-i915-disable-port-sync-when-bigjoiner-is-used.patch b/queue-5.15/drm-i915-disable-port-sync-when-bigjoiner-is-used.patch
new file mode 100644
index 0000000000..a6067e784d
--- /dev/null
+++ b/queue-5.15/drm-i915-disable-port-sync-when-bigjoiner-is-used.patch
@@ -0,0 +1,45 @@
+From 0653d501409eeb9f1deb7e4c12e4d0d2c9f1cba1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Fri, 5 Apr 2024 00:34:27 +0300
+Subject: drm/i915: Disable port sync when bigjoiner is used
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 0653d501409eeb9f1deb7e4c12e4d0d2c9f1cba1 upstream.
+
+The current modeset sequence can't handle port sync and bigjoiner
+at the same time. Refuse port sync when bigjoiner is needed,
+at least until we fix the modeset sequence.
+
+v2: Add a FIXME (Vandite)
+
+Cc: stable@vger.kernel.org
+Tested-by: Vidya Srinivas <vidya.srinivas@intel.com>
+Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240404213441.17637-4-ville.syrjala@linux.intel.com
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+(cherry picked from commit b37e1347b991459c38c56ec2476087854a4f720b)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_ddi.c |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/gpu/drm/i915/display/intel_ddi.c
++++ b/drivers/gpu/drm/i915/display/intel_ddi.c
+@@ -3904,7 +3904,12 @@ static bool m_n_equal(const struct intel
+ static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
+ 				       const struct intel_crtc_state *crtc_state2)
+ {
++	/*
++	 * FIXME the modeset sequence is currently wrong and
++	 * can't deal with bigjoiner + port sync at the same time.
++	 */
+ 	return crtc_state1->hw.active && crtc_state2->hw.active &&
++		!crtc_state1->bigjoiner_pipes && !crtc_state2->bigjoiner_pipes &&
+ 		crtc_state1->output_types == crtc_state2->output_types &&
+ 		crtc_state1->output_format == crtc_state2->output_format &&
+ 		crtc_state1->lane_count == crtc_state2->lane_count &&
diff --git a/queue-5.15/series b/queue-5.15/series
index 95ade4d313..29fd4f4ff9 100644
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -42,3 +42,5 @@ x86-bugs-fix-bhi-handling-of-rrsba.patch
 x86-bugs-clarify-that-syscall-hardening-isn-t-a-bhi-mitigation.patch
 x86-bugs-remove-config_bhi_mitigation_auto-and-spectre_bhi-auto.patch
 x86-bugs-replace-config_spectre_bhi_-on-off-with-config_mitigation_spectre_bhi.patch
+drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch
+drm-i915-disable-port-sync-when-bigjoiner-is-used.patch