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| author | Akira Yokosawa <akiyks@gmail.com> | 2023-10-14 17:43:33 +0900 |
|---|---|---|
| committer | Paul E. McKenney <paulmck@kernel.org> | 2023-10-15 20:54:19 -0700 |
| commit | a20ad1bc751f812f7ded5b77ef44166f47077e27 (patch) | |
| tree | 33b42273522de9968e17513358f55ab9d9f3d98a | |
| parent | bf9d25963684d3d720a8f6dbd8fe590864deae50 (diff) | |
| download | perfbook-a20ad1bc751f812f7ded5b77ef44166f47077e27.tar.gz | |
memorder: Update of ordering SSE non-temporal memory move instructions
Since Linux v4.15, smp_mb(), smp_wmb(), and smp_rmb() don't suffice
for ordering them.
Update the text accordingly and add a footnote.
Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
Signed-off-by: Paul E. McKenney <paulmck@kernel.org>
| -rw-r--r-- | memorder/memorder.tex | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/memorder/memorder.tex b/memorder/memorder.tex index 6b9c3268..da56a699 100644 --- a/memorder/memorder.tex +++ b/memorder/memorder.tex @@ -6075,8 +6075,10 @@ that same location, you are on your own. Some SSE instructions are weakly ordered (\co{clflush} and non-temporal move instructions~\cite{IntelXeonV2b-96a}). Code that uses these non-temporal move instructions -can also use \co{mfence} for \co{smp_mb()}, -\co{lfence} for \co{smp_rmb()}, and \co{sfence} for \co{smp_wmb()}. +can use \co{mfence} for \co{mb()}, +\co{lfence} for \co{rmb()}, and \co{sfence} for \co{wmb()}.\footnote{ + \co{smp_mb()}, \co{smp_rmb()}, and \co{smp_wmb()} don't suffice + for ordering non-temporal move instructions since Linux v4.15.} A few older variants of the x86 CPU have a mode bit that enables out-of-order stores, and for these CPUs, \co{smp_wmb()} must also be defined to be \co{lock;addl}. |