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| author | Luc Van Oostenryck <lucvoo@kernel.org> | 2024-01-21 00:29:17 +0100 |
|---|---|---|
| committer | Luc Van Oostenryck <lucvoo@kernel.org> | 2024-01-23 21:51:07 +0100 |
| commit | 77b30af89aa02b98420b9cff6bdc6892647e00f1 (patch) | |
| tree | 46974fcc9038399c27d037eff243ca0c647a0839 | |
| parent | 3500cba405b71492fee7a07ac4fed21046311928 (diff) | |
| download | sparse-77b30af89aa02b98420b9cff6bdc6892647e00f1.tar.gz | |
riscv: G extension implies Zicsr & Zifencei
So, add the corresponding flags.
Signed-off-by: Luc Van Oostenryck <lucvoo@kernel.org>
| -rw-r--r-- | target-riscv.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-riscv.c b/target-riscv.c index d90f45a5..d30be04b 100644 --- a/target-riscv.c +++ b/target-riscv.c @@ -16,7 +16,7 @@ #define RISCV_COMP (1 << 8) #define RISCV_EMBD (1 << 9) #define RISCV_FPU (RISCV_FLOAT|RISCV_DOUBLE|RISCV_FDIV) -#define RISCV_GENERIC (RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU) +#define RISCV_GENERIC (RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU|RISCV_ZICSR|RISCV_ZIFENCEI) #define RISCV_ZICSR (1 << 10) #define RISCV_ZIFENCEI (1 << 11) #define RISCV_ZICBOM (1 << 12) |