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| author | Luc Van Oostenryck <lucvoo@kernel.org> | 2024-01-21 00:29:10 +0100 |
|---|---|---|
| committer | Luc Van Oostenryck <lucvoo@kernel.org> | 2024-01-23 21:49:25 +0100 |
| commit | 3500cba405b71492fee7a07ac4fed21046311928 (patch) | |
| tree | dc7053ac5add213dbe4dc3598b6c2230666f468d | |
| parent | 8264c2019f75563cf8704e4385f90b3020a468a7 (diff) | |
| download | sparse-3500cba405b71492fee7a07ac4fed21046311928.tar.gz | |
riscv: V extension implies F & D
So, add the corresponding flags.
Signed-off-by: Luc Van Oostenryck <lucvoo@kernel.org>
| -rw-r--r-- | target-riscv.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-riscv.c b/target-riscv.c index 910aa0ad..d90f45a5 100644 --- a/target-riscv.c +++ b/target-riscv.c @@ -42,7 +42,7 @@ static void parse_march_riscv(const char *arg) { "f", RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR }, { "d", RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR }, { "c", RISCV_COMP }, - { "v", RISCV_VECTOR }, + { "v", RISCV_VECTOR|RISCV_FPU|RISCV_ZICSR }, { "_zicsr", RISCV_ZICSR }, { "_zifencei", RISCV_ZIFENCEI }, { "_zicbom", RISCV_ZICBOM }, |