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| author | Conor Dooley <conor.dooley@microchip.com> | 2023-03-06 22:23:22 +0000 |
|---|---|---|
| committer | Luc Van Oostenryck <lucvoo@kernel.org> | 2024-01-21 14:43:56 +0100 |
| commit | 3a41dd055be9184e1d65ea7f3434f487847eb1dd (patch) | |
| tree | cdbfe59bab132ba358ea1f7aabb50afc9e22f536 | |
| parent | 40c42530d7d37217a98bf9bcd28e3ad2ba4fe678 (diff) | |
| download | sparse-3a41dd055be9184e1d65ea7f3434f487847eb1dd.tar.gz | |
RISC-V: Add basic support for the vector extension
I've started hitting this in CI while testing Andy's vector enablement
series. I'm not entirely sure if there is more to do here, other than
squeezing in the duplicate of what has been done for other extensions.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Luc Van Oostenryck <lucvoo@kernel.org>
| -rw-r--r-- | target-riscv.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-riscv.c b/target-riscv.c index 7a184973..b495386c 100644 --- a/target-riscv.c +++ b/target-riscv.c @@ -21,6 +21,7 @@ #define RISCV_ZIFENCEI (1 << 11) #define RISCV_ZICBOM (1 << 12) #define RISCV_ZIHINTPAUSE (1 << 13) +#define RISCV_VECTOR (1 << 14) static unsigned int riscv_flags; @@ -41,6 +42,7 @@ static void parse_march_riscv(const char *arg) { "f", RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR }, { "d", RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR }, { "c", RISCV_COMP }, + { "v", RISCV_VECTOR }, { "_zicsr", RISCV_ZICSR }, { "_zifencei", RISCV_ZIFENCEI }, { "_zicbom", RISCV_ZICBOM }, @@ -139,6 +141,8 @@ static void predefine_riscv(const struct target *self) predefine("__riscv_zicbom", 1, "1"); if (riscv_flags & RISCV_ZIHINTPAUSE) predefine("__riscv_zihintpause", 1, "1"); + if (riscv_flags & RISCV_VECTOR) + predefine("__riscv_vector", 1, "1"); if (cmodel) predefine_strong("__riscv_cmodel_%s", cmodel); |