From 3a41dd055be9184e1d65ea7f3434f487847eb1dd Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Mon, 6 Mar 2023 22:23:22 +0000 Subject: RISC-V: Add basic support for the vector extension I've started hitting this in CI while testing Andy's vector enablement series. I'm not entirely sure if there is more to do here, other than squeezing in the duplicate of what has been done for other extensions. Signed-off-by: Conor Dooley Signed-off-by: Luc Van Oostenryck --- target-riscv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-riscv.c b/target-riscv.c index 7a184973..b495386c 100644 --- a/target-riscv.c +++ b/target-riscv.c @@ -21,6 +21,7 @@ #define RISCV_ZIFENCEI (1 << 11) #define RISCV_ZICBOM (1 << 12) #define RISCV_ZIHINTPAUSE (1 << 13) +#define RISCV_VECTOR (1 << 14) static unsigned int riscv_flags; @@ -41,6 +42,7 @@ static void parse_march_riscv(const char *arg) { "f", RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR }, { "d", RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR }, { "c", RISCV_COMP }, + { "v", RISCV_VECTOR }, { "_zicsr", RISCV_ZICSR }, { "_zifencei", RISCV_ZIFENCEI }, { "_zicbom", RISCV_ZICBOM }, @@ -139,6 +141,8 @@ static void predefine_riscv(const struct target *self) predefine("__riscv_zicbom", 1, "1"); if (riscv_flags & RISCV_ZIHINTPAUSE) predefine("__riscv_zihintpause", 1, "1"); + if (riscv_flags & RISCV_VECTOR) + predefine("__riscv_vector", 1, "1"); if (cmodel) predefine_strong("__riscv_cmodel_%s", cmodel); -- cgit 1.2.3-korg