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| author | Luc Van Oostenryck <lucvoo@kernel.org> | 2024-02-03 17:12:35 +0100 |
|---|---|---|
| committer | Luc Van Oostenryck <lucvoo@kernel.org> | 2024-02-03 17:12:35 +0100 |
| commit | 0196afe16a50c76302921b139d412e82e5be2349 (patch) | |
| tree | 3eaeea56f33f93dda57250f5957648d5efd1fe6e | |
| parent | 09411a7a5127516a0741eb1bd8762642fa9197ce (diff) | |
| parent | 77b30af89aa02b98420b9cff6bdc6892647e00f1 (diff) | |
| download | sparse-0196afe16a50c76302921b139d412e82e5be2349.tar.gz | |
| -rw-r--r-- | target-riscv.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/target-riscv.c b/target-riscv.c index 7a184973..d30be04b 100644 --- a/target-riscv.c +++ b/target-riscv.c @@ -16,11 +16,12 @@ #define RISCV_COMP (1 << 8) #define RISCV_EMBD (1 << 9) #define RISCV_FPU (RISCV_FLOAT|RISCV_DOUBLE|RISCV_FDIV) -#define RISCV_GENERIC (RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU) +#define RISCV_GENERIC (RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU|RISCV_ZICSR|RISCV_ZIFENCEI) #define RISCV_ZICSR (1 << 10) #define RISCV_ZIFENCEI (1 << 11) #define RISCV_ZICBOM (1 << 12) #define RISCV_ZIHINTPAUSE (1 << 13) +#define RISCV_VECTOR (1 << 14) static unsigned int riscv_flags; @@ -41,6 +42,7 @@ static void parse_march_riscv(const char *arg) { "f", RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR }, { "d", RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR }, { "c", RISCV_COMP }, + { "v", RISCV_VECTOR|RISCV_FPU|RISCV_ZICSR }, { "_zicsr", RISCV_ZICSR }, { "_zifencei", RISCV_ZIFENCEI }, { "_zicbom", RISCV_ZICBOM }, @@ -139,6 +141,12 @@ static void predefine_riscv(const struct target *self) predefine("__riscv_zicbom", 1, "1"); if (riscv_flags & RISCV_ZIHINTPAUSE) predefine("__riscv_zihintpause", 1, "1"); + if (riscv_flags & RISCV_VECTOR) { + predefine("__riscv_vector", 1, "1"); + predefine("__riscv_v_min_vlen", 1, "128"); + predefine("__riscv_v_elen", 1, "64"); + predefine("__riscv_v_elen_fp", 1, "64"); + } if (cmodel) predefine_strong("__riscv_cmodel_%s", cmodel); |