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authorRoman Bolshakov <r.bolshakov@yadro.com>2020-03-29 10:11:25 +0300
committerPaolo Bonzini <pbonzini@redhat.com>2020-05-18 06:45:15 -0400
commit8202cf8424d2f1da6f67f6e825431e8159303ccc (patch)
treee0312854d7abc791de5fa48f69946a1dd6391154
parent401299a581d7b255a615de482c3a9e97e090fd8a (diff)
downloadkvm-unit-tests-8202cf8424d2f1da6f67f6e825431e8159303ccc.tar.gz
x86: realmode: Test interrupt delivery after STI
If interrupts are disabled, STI is inhibiting interrupts for the instruction following it. If STI is followed by HLT, the CPU is going to handle all pending or new interrupts as soon as HLT is executed. Test if emulator properly clears inhibition state and allows the scenario outlined above. Cc: Cameron Esfahani <dirty@apple.com> Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200329071125.79253-1-r.bolshakov@yadro.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
-rw-r--r--x86/realmode.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/x86/realmode.c b/x86/realmode.c
index 31f84d0..3518224 100644
--- a/x86/realmode.c
+++ b/x86/realmode.c
@@ -814,6 +814,26 @@ static void test_int(void)
report("int 1", 0, 1);
}
+static void test_sti_inhibit(void)
+{
+ init_inregs(NULL);
+
+ *(u32 *)(0x73 * 4) = 0x1000; /* Store IRQ 11 handler in the IDT */
+ *(u8 *)(0x1000) = 0xcf; /* 0x1000 contains an IRET instruction */
+
+ MK_INSN(sti_inhibit, "cli\n\t"
+ "movw $0x200b, %dx\n\t"
+ "movl $1, %eax\n\t"
+ "outl %eax, %dx\n\t" /* Set IRQ11 */
+ "movl $0, %eax\n\t"
+ "outl %eax, %dx\n\t" /* Clear IRQ11 */
+ "sti\n\t"
+ "hlt\n\t");
+ exec_in_big_real_mode(&insn_sti_inhibit);
+
+ report("sti inhibit", ~0, 1);
+}
+
static void test_imul(void)
{
MK_INSN(imul8_1, "mov $2, %al\n\t"
@@ -1739,6 +1759,7 @@ void realmode_start(void)
test_xchg();
test_iret();
test_int();
+ test_sti_inhibit();
test_imul();
test_mul();
test_div();