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| author | Zenghui Yu <yuzenghui@huawei.com> | 2020-02-11 16:39:00 +0800 |
|---|---|---|
| committer | Andrew Jones <drjones@redhat.com> | 2020-04-03 09:40:34 +0200 |
| commit | 401c09ea953372584c593fc76eaa39c6b06c0f4a (patch) | |
| tree | be5ab8f22e2dd9325ef339411680be164e96d429 | |
| parent | e44a257a89ef821802b21cf4fd0ee6f124278e15 (diff) | |
| download | kvm-unit-tests-401c09ea953372584c593fc76eaa39c6b06c0f4a.tar.gz | |
arm64: timer: Use the proper RDist register name in GICv3
We're actually going to read GICR_ISACTIVER0 and GICR_ISPENDR0 (in
SGI_base frame of the redistribitor) to get the active/pending state
of the timer interrupt. Fix this typo.
And since they have the same value, there's no functional change.
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
| -rw-r--r-- | arm/timer.c | 4 | ||||
| -rw-r--r-- | lib/arm/asm/gic-v3.h | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/arm/timer.c b/arm/timer.c index 94543f2..10a88f3 100644 --- a/arm/timer.c +++ b/arm/timer.c @@ -351,8 +351,8 @@ static void test_init(void) gic_icenabler = gicv2_dist_base() + GICD_ICENABLER; break; case 3: - gic_isactiver = gicv3_sgi_base() + GICD_ISACTIVER; - gic_ispendr = gicv3_sgi_base() + GICD_ISPENDR; + gic_isactiver = gicv3_sgi_base() + GICR_ISACTIVER0; + gic_ispendr = gicv3_sgi_base() + GICR_ISPENDR0; gic_isenabler = gicv3_sgi_base() + GICR_ISENABLER0; gic_icenabler = gicv3_sgi_base() + GICR_ICENABLER0; break; diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 0dc838b..e2736a1 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -32,6 +32,10 @@ #define GICR_IGROUPR0 GICD_IGROUPR #define GICR_ISENABLER0 GICD_ISENABLER #define GICR_ICENABLER0 GICD_ICENABLER +#define GICR_ISPENDR0 GICD_ISPENDR +#define GICR_ICPENDR0 GICD_ICPENDR +#define GICR_ISACTIVER0 GICD_ISACTIVER +#define GICR_ICACTIVER0 GICD_ICACTIVER #define GICR_IPRIORITYR0 GICD_IPRIORITYR #define ICC_SGI1R_AFFINITY_1_SHIFT 16 |