DDR3: Fix speed and PC3 number of high-speed modules.

git-svn-id: http://lm-sensors.org/svn/i2c-tools/trunk@6134 7894878c-1315-0410-8ee3-d5d059ff63e0

2 files changed, 12 insertions, 1 deletions

diff --git a/CHANGES b/CHANGES
index a9a0d16..4017d20 100644
--- a/CHANGES
+++ b/CHANGES
@@ -29,6 +29,7 @@ SVN HEAD
                 Round down PC3 numbers to comply with Jedec
                 Don't print the DDR3 time bases
                 Decode the FTB fields of DDR3 tCk, tAA, tRCD, tRP and tRC
+                Fix speed and PC3 number of high-speed DDR3 modules
   i2cdetect: Do a best effort detection if functionality is missing
              Clarify the SMBus commands used for probing by default
   i2c-dev.h: Minimize differences with kernel flavor
diff --git a/eeprom/decode-dimms b/eeprom/decode-dimms
index 2b51bf9..7fa6e58 100755
--- a/eeprom/decode-dimms
+++ b/eeprom/decode-dimms
@@ -1347,6 +1347,7 @@ sub decode_ddr3_sdram($)
 	my $temp;
 	my $ctime;
 	my ($ftb, $mtb);
+	my $ii;
 
 	my @module_types = ("Undefined", "RDIMM", "UDIMM", "SO-DIMM",
 			    "Micro-DIMM", "Mini-RDIMM", "Mini-UDIMM",
@@ -1370,6 +1371,16 @@ sub decode_ddr3_sdram($)
 	prints("Memory Characteristics");
 
 	$ctime = ddr3_mtb_ftb($bytes->[12], $bytes->[34], $mtb, $ftb);
+	# Starting with DDR3-1866, vendors may start approximating the
+	# minimum cycle time. Try to guess what they really meant so
+	# that the reported speed matches the standard.
+	for ($ii = 7; $ii < 15; $ii++) {
+		if ($ctime > 7.5/$ii - $ftb/1000 && $ctime < 7.5/$ii + $ftb/1000) {
+			$ctime = 7.5/$ii;
+			last;
+		}
+	}
+
 	my $ddrclk = 2 * (1000 / $ctime);
 	my $tbits = 1 << (($bytes->[8] & 7) + 3);
 	my $pcclk = int ($ddrclk * $tbits / 8);
@@ -1413,7 +1424,6 @@ sub decode_ddr3_sdram($)
 # latencies
 	my $highestCAS = 0;
 	my %cas;
-	my $ii;
 	my $cas_sup = ($bytes->[15] << 8) + $bytes->[14];
 	for ($ii = 0; $ii < 15; $ii++) {
 		if ($cas_sup & (1 << $ii)) {