Fix spelling errors.v135

Found by Debian Lintian

Signed-off-by: Andi Kleen <ak@linux.intel.com>

6 files changed, 12 insertions, 12 deletions

diff --git a/broadwell_epex.c b/broadwell_epex.c
index 576be1c..35d132f 100644
--- a/broadwell_epex.c
+++ b/broadwell_epex.c
@@ -91,7 +91,7 @@ static char *qpi[] = {
 	[0x22] = "Phy detected in-band reset (no width change)",
 	[0x23] = "Link failover clock failover",
 	[0x30] = "Rx detected CRC error - successful LLR after Phy re-init",
-	[0x31] = "Rx detected CRC error - successful LLR wihout Phy re-init",
+	[0x31] = "Rx detected CRC error - successful LLR without Phy re-init",
 };
 
 static struct field qpi_mc[] = {
diff --git a/core2.c b/core2.c
index c2824dc..0671bb2 100644
--- a/core2.c
+++ b/core2.c
@@ -69,7 +69,7 @@ static struct field p6old_status[] = {
 	FIELD(31, reserved_1bit),
 	FIELD(32, reserved_3bits),
 	SBITFIELD(35, "BINIT received from external bus"),
-	SBITFIELD(37, "Received hard error reponse on split transaction (Bus BINIT)"),
+	SBITFIELD(37, "Received hard error response on split transaction (Bus BINIT)"),
 	{}
 };
 
diff --git a/haswell.c b/haswell.c
index b309ae5..892ebc7 100644
--- a/haswell.c
+++ b/haswell.c
@@ -91,7 +91,7 @@ static char *qpi[] = {
 	[0x22] = "Phy detected in-band reset (no width change)",
 	[0x23] = "Link failover clock failover",
 	[0x30] = "Rx detected CRC error - successful LLR after Phy re-init",
-	[0x31] = "Rx detected CRC error - successful LLR wihout Phy re-init",
+	[0x31] = "Rx detected CRC error - successful LLR without Phy re-init",
 };
 
 static struct field qpi_mc[] = {
diff --git a/k8.c b/k8.c
index c99cf7f..16d44c5 100644
--- a/k8.c
+++ b/k8.c
@@ -89,7 +89,7 @@ static char *highbits[32] = {
 	[0] = "err cpu0",
 };
 static char *k8threshold[] = {
-	[0 ... K8_MCELOG_THRESHOLD_DRAM_ECC - 1] = "Unknow threshold counter",
+	[0 ... K8_MCELOG_THRESHOLD_DRAM_ECC - 1] = "Unknown threshold counter",
 	[K8_MCELOG_THRESHOLD_DRAM_ECC] = "MC4_MISC0 DRAM threshold",
 	[K8_MCELOG_THRESHOLD_LINK] = "MC4_MISC1 Link threshold",
 	[K8_MCELOG_THRESHOLD_L3_CACHE] = "MC4_MISC2 L3 Cache threshold",
diff --git a/mcelog.conf b/mcelog.conf
index f8abb99..54e2b91 100644
--- a/mcelog.conf
+++ b/mcelog.conf
@@ -23,7 +23,7 @@
 # If this value is set incorrectly the decoded output will be likely incorrect.
 # By default when this parameter is not set mcelog uses the CPU it is running on
 # on very new kernels the mcelog events reported by the kernel also carry
-# the CPU type which is used too when available and not overriden.
+# the CPU type which is used too when available and not overridden.
 
 # Enable daemon mode:
 #daemon = yes
@@ -132,7 +132,7 @@ mem-ce-error-trigger = socket-memory-error-trigger
 
 mem-ce-error-threshold = 100 / 24h
 
-#  Log socket error threshold explicitely?
+#  Log socket error threshold explicitly?
 mem-ce-error-log = yes
 
 # Trigger script for uncorrected bus error events
@@ -148,7 +148,7 @@ unknown-threshold-trigger = unknown-error-trigger
 # Processing of cache error thresholds reported by Intel CPUs.
 cache-threshold-trigger = cache-error-trigger
 
-# Should cache threshold events be logged explicitely?
+# Should cache threshold events be logged explicitly?
 cache-threshold-log = yes
 
 [page]
@@ -159,7 +159,7 @@ memory-ce-threshold = 10 / 24h
 # Trigger script for corrected errors.
 # memory-ce-trigger = page-error-trigger
 
-# Should page threshold events be logged explicitely?
+# Should page threshold events be logged explicitly?
 memory-ce-log = yes
 
 # specify the internal action in mcelog to exceeding a page error threshold
diff --git a/mcelog.conf.5 b/mcelog.conf.5
index 5a9afda..c87f23e 100644
--- a/mcelog.conf.5
+++ b/mcelog.conf.5
@@ -43,7 +43,7 @@ For valid values for type please see mcelog --help.
 If this value is set incorrectly the decoded output will be likely incorrect.
 By default when this parameter is not set mcelog uses the CPU it is running on
 on very new kernels the mcelog events reported by the kernel also carry
-the CPU type which is used too when available and not overriden.
+the CPU type which is used too when available and not overridden.
 .PP
 .PP
 Enable daemon mode:
@@ -204,7 +204,7 @@ Threshold on when to trigger a correct error for the socket.
 .B mem-ce-error-threshold = 100 / 24h
 .PP
 .PP
- log socket error threshold explicitely?
+ log socket error threshold explicitly?
 .PP
 .B mem-ce-error-log = yes
 .PP
@@ -230,7 +230,7 @@ Processing of cache error thresholds reported by intel cpus.
 .B cache-threshold-trigger = cache-error-trigger
 .PP
 .PP
-Should cache threshold events be logged explicitely?
+Should cache threshold events be logged explicitly?
 .PP
 .B cache-threshold-log = yes
 .PP
@@ -246,7 +246,7 @@ Trigger script for corrected errors.
 memory-ce-trigger = page-error-trigger
 .PP
 .PP
-Should page threshold events be logged explicitely?
+Should page threshold events be logged explicitly?
 .PP
 .B memory-ce-log = yes
 .PP