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authorAndi Kleen <ak@linux.intel.com>2008-12-05 18:43:03 +0100
committerAndi Kleen <ak@linux.intel.com>2008-12-05 18:43:03 +0100
commitf211ca5ab71ff3abfcb2af09dca31c77cdd49638 (patch)
treee4522fdbb3aa135e57f25fc1da96861beb38d278
parenta61b0bb9fcb3343ec3cafa7c774dbf51c9b7ade2 (diff)
downloadmce-inject-f211ca5ab71ff3abfcb2af09dca31c77cdd49638.tar.gz
Update struct mce with latest mce branch version
Signed-off-by: Andi Kleen <ak@linux.intel.com>
-rw-r--r--mce.h18
-rw-r--r--mce.y2
2 files changed, 15 insertions, 5 deletions
diff --git a/mce.h b/mce.h
index 7e8e9af..12628b2 100644
--- a/mce.h
+++ b/mce.h
@@ -23,6 +23,13 @@
#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
+#define MCJ_CTX_MASK 3
+#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
+#define MCJ_CTX_RANDOM 0 /* inject context: random */
+#define MCJ_CTX_PROCESS 1 /* inject context: process */
+#define MCJ_CTX_IRQ 2 /* inject context: IRQ */
+#define MCJ_NMI_BROADCAST 4 /* do NMI broadcasting */
+
/* Fields are zero when not available */
struct mce {
__u64 status;
@@ -31,13 +38,16 @@ struct mce {
__u64 mcgstatus;
__u64 ip;
__u64 tsc; /* cpu time stamp counter */
- __u64 res1; /* for future extension */
- __u64 res2; /* dito. */
- __u8 cs; /* code segment */
+ __u64 time; /* wall time_t when error was detected */
+ __u8 cpuvendor; /* cpu vendor as encoded in system.h */
+ __u8 inject_flags;
+ __u16 pad2;
+ __u32 cpuid; /* CPUID 1 EAX */
+ __u8 cs; /* code segment */
__u8 bank; /* machine check bank */
__u8 cpu; /* cpu that raised the error */
__u8 finished; /* entry is valid */
- __u32 pad;
+ __u32 extcpu; /* extended CPU number */
};
/*
diff --git a/mce.y b/mce.y
index 30b5eca..4a1db6e 100644
--- a/mce.y
+++ b/mce.y
@@ -82,7 +82,7 @@ mce_term: STATUS status_list { m.status = $2; }
| MISC NUMBER { m.misc = $2; m.status |= MCI_STATUS_MISCV; }
| NOBROADCAST { mce_flags |= MCE_NOBROADCAST; }
| HOLD { mce_flags |= MCE_HOLD; }
- | IN_IRQ { m.pad = MCEC_IRQ; }
+ | IN_IRQ { m.inject_flags |= MCEC_IRQ; }
;
mcgstatus_list: /* empty */