diff options
| author | Joakim Tjernlund <Joakim.Tjernlund@transmode.se> | 2011-10-10 13:30:08 +0200 |
|---|---|---|
| committer | Willy Tarreau <w@1wt.eu> | 2012-04-09 15:02:39 +0200 |
| commit | 3030b4837f6d4da3ce04eb5d3c3be4550bf82e8f (patch) | |
| tree | 8deaa903513c6f13e0c1353c09b93c558a5079d9 | |
| parent | 05ba176ac731ab7d89afbd7d9660d824264aeb20 (diff) | |
| download | linux-2.4-3030b4837f6d4da3ce04eb5d3c3be4550bf82e8f.tar.gz | |
8xx: Tag DAR with 0x00f0 to catch buggy instructions.
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
This also fixes MachineCheck to pass DAR and DSISR as well.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Willy Tarreau <w@1wt.eu>
| -rw-r--r-- | arch/ppc/kernel/head_8xx.S | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index ba05a57fa4673d..57858cef2ba0e8 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -197,7 +197,17 @@ label: \ STD_EXCEPTION(0x100, Reset, UnknownException) /* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + . = 0x200 +MachineCheck: + EXCEPTION_PROLOG + mfspr r20,DSISR + stw r20,_DSISR(r21) + mfspr r20,DAR + stw r20,_DAR(r21) + li r20,0x00f0 + mtspr DAR,r20 /* Tag DAR */ + addi r3,r1,STACK_FRAME_OVERHEAD + FINISH_EXCEPTION(MachineCheckException) /* Data access exception. * This is "never generated" by the MPC8xx. We jump to it for other @@ -211,6 +221,8 @@ DataAccess: mr r5,r20 mfspr r4,DAR stw r4,_DAR(r21) + li r20,0x00f0 + mtspr DAR,r20 /* Tag DAR */ addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ @@ -249,6 +261,8 @@ Alignment: EXCEPTION_PROLOG mfspr r4,DAR stw r4,_DAR(r21) + li r20,0x00f0 + mtspr DAR,r20 /* Tag DAR */ mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD @@ -433,6 +447,7 @@ DataStoreTLBMiss: * of the MMU. */ 2: li r21, 0x00f0 + mtspr DAR, r21 /* Tag DAR */ rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x3d80, r3) mtspr MD_RPN, r20 /* Update TLB entry */ @@ -543,6 +558,7 @@ DataTLBError: * of the MMU. */ li r21, 0x00f0 + mtspr DAR, r21 /* Tag DAR */ rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x3d80, r3) mtspr MD_RPN, r20 /* Update TLB entry */ |