aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_offset.h
blob: 5efcf9b27869c94053cb223c10a0eb0638b354d3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725
5726
5727
5728
5729
5730
5731
5732
5733
5734
5735
5736
5737
5738
5739
5740
5741
5742
5743
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787
5788
5789
5790
5791
5792
5793
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869
5870
5871
5872
5873
5874
5875
5876
5877
5878
5879
5880
5881
5882
5883
5884
5885
5886
5887
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084
6085
6086
6087
6088
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174
6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
6234
6235
6236
6237
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267
6268
6269
6270
6271
6272
6273
6274
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409
6410
6411
6412
6413
6414
6415
6416
6417
6418
6419
6420
6421
6422
6423
6424
6425
6426
6427
6428
6429
6430
6431
6432
6433
6434
6435
6436
6437
6438
6439
6440
6441
6442
6443
6444
6445
6446
6447
6448
6449
6450
6451
6452
6453
6454
6455
6456
6457
6458
6459
6460
6461
6462
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476
6477
6478
6479
6480
6481
6482
6483
6484
6485
6486
6487
6488
6489
6490
6491
6492
6493
6494
6495
6496
6497
6498
6499
6500
6501
6502
6503
6504
6505
6506
6507
6508
6509
6510
6511
6512
6513
6514
6515
6516
6517
6518
6519
6520
6521
6522
6523
6524
6525
6526
6527
6528
6529
6530
6531
6532
6533
6534
6535
6536
6537
6538
6539
6540
6541
6542
6543
6544
6545
6546
6547
6548
6549
6550
6551
6552
6553
6554
6555
6556
6557
6558
6559
6560
6561
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572
6573
6574
6575
6576
6577
6578
6579
6580
6581
6582
6583
6584
6585
6586
6587
6588
6589
6590
6591
6592
6593
6594
6595
6596
6597
6598
6599
6600
6601
6602
6603
6604
6605
6606
6607
6608
6609
6610
6611
6612
6613
6614
6615
6616
6617
6618
6619
6620
6621
6622
6623
6624
6625
6626
6627
6628
6629
6630
6631
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641
6642
6643
6644
6645
6646
6647
6648
6649
6650
6651
6652
6653
6654
6655
6656
6657
6658
6659
6660
6661
6662
6663
6664
6665
6666
6667
6668
6669
6670
6671
6672
6673
6674
6675
6676
6677
6678
6679
6680
6681
6682
6683
6684
6685
6686
6687
6688
6689
6690
6691
6692
6693
6694
6695
6696
6697
6698
6699
6700
6701
6702
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712
6713
6714
6715
6716
6717
6718
6719
6720
6721
6722
6723
6724
6725
6726
6727
6728
6729
6730
6731
6732
6733
6734
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748
6749
6750
6751
6752
6753
6754
6755
6756
6757
6758
6759
6760
6761
6762
6763
6764
6765
6766
6767
6768
6769
6770
6771
6772
6773
6774
6775
6776
6777
6778
6779
6780
6781
6782
6783
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793
6794
6795
6796
6797
6798
6799
6800
6801
6802
6803
6804
6805
6806
6807
6808
6809
6810
6811
6812
6813
6814
6815
6816
6817
6818
6819
6820
6821
6822
6823
6824
6825
6826
6827
6828
6829
6830
6831
6832
6833
6834
6835
6836
6837
6838
6839
6840
6841
6842
6843
6844
6845
6846
6847
6848
6849
6850
6851
6852
6853
6854
6855
6856
6857
6858
6859
6860
6861
6862
6863
6864
6865
6866
6867
6868
6869
6870
6871
6872
6873
6874
6875
6876
6877
6878
6879
6880
6881
6882
6883
6884
6885
6886
6887
6888
6889
6890
6891
6892
6893
6894
6895
6896
6897
6898
6899
6900
6901
6902
6903
6904
6905
6906
6907
6908
6909
6910
6911
6912
6913
6914
6915
6916
6917
6918
6919
6920
6921
6922
6923
6924
6925
6926
6927
6928
6929
6930
6931
6932
6933
6934
6935
6936
6937
6938
6939
6940
6941
6942
6943
6944
6945
6946
6947
6948
6949
6950
6951
6952
6953
6954
6955
6956
6957
6958
6959
6960
6961
6962
6963
6964
6965
6966
6967
6968
6969
6970
6971
6972
6973
6974
6975
6976
6977
6978
6979
6980
6981
6982
6983
6984
6985
6986
6987
6988
6989
6990
6991
6992
6993
6994
6995
6996
6997
6998
6999
7000
7001
7002
7003
7004
7005
7006
7007
7008
7009
7010
7011
7012
7013
7014
7015
7016
7017
7018
7019
7020
7021
7022
7023
7024
7025
7026
7027
7028
7029
7030
7031
7032
7033
7034
7035
7036
7037
7038
7039
7040
7041
7042
7043
7044
7045
7046
7047
7048
7049
7050
7051
7052
7053
7054
7055
7056
7057
7058
7059
7060
7061
7062
7063
7064
7065
7066
7067
7068
7069
7070
7071
7072
7073
7074
7075
7076
7077
7078
7079
7080
7081
7082
7083
7084
7085
7086
7087
7088
7089
7090
7091
7092
7093
7094
7095
7096
7097
7098
7099
7100
7101
7102
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115
7116
7117
7118
7119
7120
7121
7122
7123
7124
7125
7126
7127
7128
7129
7130
7131
7132
7133
7134
7135
7136
7137
7138
7139
7140
7141
7142
7143
7144
7145
7146
7147
7148
7149
7150
7151
7152
7153
7154
7155
7156
7157
7158
7159
7160
7161
7162
7163
7164
7165
7166
7167
7168
7169
7170
7171
7172
7173
7174
7175
7176
7177
7178
7179
7180
7181
7182
7183
7184
7185
7186
7187
7188
7189
7190
7191
7192
7193
7194
7195
7196
7197
7198
7199
7200
7201
7202
7203
7204
7205
7206
7207
7208
7209
7210
7211
7212
7213
7214
7215
7216
7217
7218
7219
7220
7221
7222
7223
7224
7225
7226
7227
7228
7229
7230
7231
7232
7233
7234
7235
7236
7237
7238
7239
7240
7241
7242
7243
7244
7245
7246
7247
7248
7249
7250
7251
7252
7253
7254
7255
7256
7257
7258
7259
7260
7261
7262
7263
7264
7265
7266
7267
7268
7269
7270
7271
7272
7273
7274
7275
7276
7277
7278
7279
7280
7281
7282
7283
7284
7285
7286
7287
7288
7289
7290
7291
7292
7293
7294
7295
7296
7297
7298
7299
7300
7301
7302
7303
7304
7305
7306
7307
7308
7309
7310
7311
7312
7313
7314
7315
7316
7317
7318
7319
7320
7321
7322
7323
7324
7325
7326
7327
7328
7329
7330
7331
7332
7333
7334
7335
7336
7337
7338
7339
7340
7341
7342
7343
7344
7345
7346
7347
7348
7349
7350
7351
7352
7353
7354
7355
7356
7357
7358
7359
7360
7361
7362
7363
7364
7365
7366
7367
7368
7369
7370
7371
7372
7373
7374
7375
7376
7377
7378
7379
7380
7381
7382
7383
7384
7385
7386
7387
7388
7389
7390
7391
7392
7393
7394
7395
7396
7397
7398
7399
7400
7401
7402
7403
7404
7405
7406
7407
7408
7409
7410
7411
7412
7413
7414
7415
7416
7417
7418
7419
7420
7421
7422
7423
7424
7425
7426
7427
7428
7429
7430
7431
7432
7433
7434
7435
7436
7437
7438
7439
7440
7441
7442
7443
7444
7445
7446
7447
7448
7449
7450
7451
7452
7453
7454
7455
7456
7457
7458
7459
7460
7461
7462
7463
7464
7465
7466
7467
7468
7469
7470
7471
7472
7473
7474
7475
7476
7477
7478
7479
7480
7481
7482
7483
7484
7485
7486
7487
7488
7489
7490
7491
7492
7493
7494
7495
7496
7497
7498
7499
7500
7501
7502
7503
7504
7505
7506
7507
7508
7509
7510
7511
7512
7513
7514
7515
7516
7517
7518
7519
7520
7521
7522
7523
7524
7525
7526
7527
7528
7529
7530
7531
7532
7533
7534
7535
7536
7537
7538
7539
7540
7541
7542
7543
7544
7545
7546
7547
7548
7549
7550
7551
7552
7553
7554
7555
7556
7557
7558
7559
7560
7561
7562
7563
7564
7565
7566
7567
7568
7569
7570
7571
7572
7573
7574
7575
7576
7577
7578
7579
7580
7581
7582
7583
7584
7585
7586
7587
7588
7589
7590
7591
7592
7593
7594
7595
7596
7597
7598
7599
7600
7601
7602
7603
7604
7605
7606
7607
7608
7609
7610
7611
7612
7613
7614
7615
7616
7617
7618
7619
7620
7621
7622
7623
7624
7625
7626
7627
7628
7629
7630
7631
7632
7633
7634
7635
7636
7637
7638
7639
7640
7641
7642
7643
7644
7645
7646
7647
7648
7649
7650
7651
7652
7653
7654
7655
7656
7657
7658
7659
7660
7661
7662
7663
7664
7665
7666
7667
7668
7669
7670
7671
7672
7673
7674
7675
7676
7677
7678
7679
7680
7681
7682
7683
7684
7685
7686
7687
7688
7689
7690
7691
7692
7693
7694
7695
7696
7697
7698
7699
7700
7701
7702
7703
7704
7705
7706
7707
7708
7709
7710
7711
7712
7713
7714
7715
7716
7717
7718
7719
7720
7721
7722
7723
7724
7725
7726
7727
7728
7729
7730
7731
7732
7733
7734
7735
7736
7737
7738
7739
7740
7741
7742
7743
7744
7745
7746
7747
7748
7749
7750
7751
7752
7753
7754
7755
7756
7757
7758
7759
7760
7761
7762
7763
7764
7765
7766
7767
7768
7769
7770
7771
7772
7773
7774
7775
7776
7777
7778
7779
7780
7781
7782
7783
7784
7785
7786
7787
7788
7789
7790
7791
7792
7793
7794
7795
7796
7797
7798
7799
7800
7801
7802
7803
7804
7805
7806
7807
7808
7809
7810
7811
7812
7813
7814
7815
7816
7817
7818
7819
7820
7821
7822
7823
7824
7825
7826
7827
7828
7829
7830
7831
7832
7833
7834
7835
7836
7837
7838
7839
7840
7841
7842
7843
7844
7845
7846
7847
7848
7849
7850
7851
7852
7853
7854
7855
7856
7857
7858
7859
7860
7861
7862
7863
7864
7865
7866
7867
7868
7869
7870
7871
7872
7873
7874
7875
7876
7877
7878
7879
7880
7881
7882
7883
7884
7885
7886
7887
7888
7889
7890
7891
7892
7893
7894
7895
7896
7897
7898
7899
7900
7901
7902
7903
7904
7905
7906
7907
7908
7909
7910
7911
7912
7913
7914
7915
7916
7917
7918
7919
7920
7921
7922
7923
7924
7925
7926
7927
7928
7929
7930
7931
7932
7933
7934
7935
7936
7937
7938
7939
7940
7941
7942
7943
7944
7945
7946
7947
7948
7949
7950
7951
7952
7953
7954
7955
7956
7957
7958
7959
7960
7961
7962
7963
7964
7965
7966
7967
7968
7969
7970
7971
7972
7973
7974
7975
7976
7977
7978
7979
7980
7981
7982
7983
7984
7985
7986
7987
7988
7989
7990
7991
7992
7993
7994
7995
7996
7997
7998
7999
8000
8001
8002
8003
8004
8005
8006
8007
8008
8009
8010
8011
8012
8013
8014
8015
8016
8017
8018
8019
8020
8021
8022
8023
8024
8025
8026
8027
8028
8029
8030
8031
8032
8033
8034
8035
8036
8037
8038
8039
8040
8041
8042
8043
8044
8045
8046
8047
8048
8049
8050
8051
8052
8053
8054
8055
8056
8057
8058
8059
8060
8061
8062
8063
8064
8065
8066
8067
8068
8069
8070
8071
8072
8073
8074
8075
8076
8077
8078
8079
8080
8081
8082
8083
8084
8085
8086
8087
8088
8089
8090
8091
8092
8093
8094
8095
8096
8097
8098
8099
8100
8101
8102
8103
8104
8105
8106
8107
8108
8109
8110
8111
8112
8113
8114
8115
8116
8117
8118
8119
8120
8121
8122
8123
8124
8125
8126
8127
8128
8129
8130
8131
8132
8133
8134
8135
8136
8137
8138
8139
8140
8141
8142
8143
8144
8145
8146
8147
8148
8149
8150
8151
8152
8153
8154
8155
8156
8157
8158
8159
8160
8161
8162
8163
8164
8165
8166
8167
8168
8169
8170
8171
8172
8173
8174
8175
8176
8177
8178
8179
8180
8181
8182
8183
8184
8185
8186
8187
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
8200
8201
8202
8203
8204
8205
8206
8207
8208
8209
8210
8211
8212
8213
8214
8215
8216
8217
8218
8219
8220
8221
8222
8223
8224
8225
8226
8227
8228
8229
8230
8231
8232
8233
8234
8235
8236
8237
8238
8239
8240
8241
8242
8243
8244
8245
8246
8247
8248
8249
8250
8251
8252
8253
8254
8255
8256
8257
8258
8259
8260
8261
8262
8263
8264
8265
8266
8267
8268
8269
8270
8271
8272
8273
8274
8275
8276
8277
8278
8279
8280
8281
8282
8283
8284
8285
8286
8287
8288
8289
8290
8291
8292
8293
8294
8295
8296
8297
8298
8299
8300
8301
8302
8303
8304
8305
8306
8307
8308
8309
8310
8311
8312
8313
8314
8315
8316
8317
8318
8319
8320
8321
8322
8323
8324
8325
8326
8327
8328
8329
8330
8331
8332
8333
8334
8335
8336
8337
8338
8339
8340
8341
8342
8343
8344
8345
8346
8347
8348
8349
8350
8351
8352
8353
8354
8355
8356
8357
8358
8359
8360
8361
8362
8363
8364
8365
8366
8367
8368
8369
8370
8371
8372
8373
8374
8375
8376
8377
8378
8379
8380
8381
8382
8383
8384
8385
8386
8387
8388
8389
8390
8391
8392
8393
8394
8395
8396
8397
8398
8399
8400
8401
8402
8403
8404
8405
8406
8407
8408
8409
8410
8411
8412
8413
8414
8415
8416
8417
8418
8419
8420
8421
8422
8423
8424
8425
8426
8427
8428
8429
8430
8431
8432
8433
8434
8435
8436
8437
8438
8439
8440
8441
8442
8443
8444
8445
8446
8447
8448
8449
8450
8451
8452
8453
8454
8455
8456
8457
8458
8459
8460
8461
8462
8463
8464
8465
8466
8467
8468
8469
8470
8471
8472
8473
8474
8475
8476
8477
8478
8479
8480
8481
8482
8483
8484
8485
8486
8487
8488
8489
8490
8491
8492
8493
8494
8495
8496
8497
8498
8499
8500
8501
8502
8503
8504
8505
8506
8507
8508
8509
8510
8511
8512
8513
8514
8515
8516
8517
8518
8519
8520
8521
8522
8523
8524
8525
8526
8527
8528
8529
8530
8531
8532
8533
8534
8535
8536
8537
8538
8539
8540
8541
8542
8543
8544
8545
8546
8547
8548
8549
8550
8551
8552
8553
8554
8555
8556
8557
8558
8559
8560
8561
8562
8563
8564
8565
8566
8567
8568
8569
8570
8571
8572
8573
8574
8575
8576
8577
8578
8579
8580
8581
8582
8583
8584
8585
8586
8587
8588
8589
8590
8591
8592
8593
8594
8595
8596
8597
8598
8599
8600
8601
8602
8603
8604
8605
8606
8607
8608
8609
8610
8611
8612
8613
8614
8615
8616
8617
8618
8619
8620
8621
8622
8623
8624
8625
8626
8627
8628
8629
8630
8631
8632
8633
8634
8635
8636
8637
8638
8639
8640
8641
8642
8643
8644
8645
8646
8647
8648
8649
8650
8651
8652
8653
8654
8655
8656
8657
8658
8659
8660
8661
8662
8663
8664
8665
8666
8667
8668
8669
8670
8671
8672
8673
8674
8675
8676
8677
8678
8679
8680
8681
8682
8683
8684
8685
8686
8687
8688
8689
8690
8691
8692
8693
8694
8695
8696
8697
8698
8699
8700
8701
8702
8703
8704
8705
8706
8707
8708
8709
8710
8711
8712
8713
8714
8715
8716
8717
8718
8719
8720
8721
8722
8723
8724
8725
8726
8727
8728
8729
8730
8731
8732
8733
8734
8735
8736
8737
8738
8739
8740
8741
8742
8743
8744
8745
8746
8747
8748
8749
8750
8751
8752
8753
8754
8755
8756
8757
8758
8759
8760
8761
8762
8763
8764
8765
8766
8767
8768
8769
8770
8771
8772
8773
8774
8775
8776
8777
8778
8779
8780
8781
8782
8783
8784
8785
8786
8787
8788
8789
8790
8791
8792
8793
8794
8795
8796
8797
8798
8799
8800
8801
8802
8803
8804
8805
8806
8807
8808
8809
8810
8811
8812
8813
8814
8815
8816
8817
8818
8819
8820
8821
8822
8823
8824
8825
8826
8827
8828
8829
8830
8831
8832
8833
8834
8835
8836
8837
8838
8839
8840
8841
8842
8843
8844
8845
8846
8847
8848
8849
8850
8851
8852
8853
8854
8855
8856
8857
8858
8859
8860
8861
8862
8863
8864
8865
8866
8867
8868
8869
8870
8871
8872
8873
8874
8875
8876
8877
8878
8879
8880
8881
8882
8883
8884
8885
8886
8887
8888
8889
8890
8891
8892
8893
8894
8895
8896
8897
8898
8899
8900
8901
8902
8903
8904
8905
8906
8907
8908
8909
8910
8911
8912
8913
8914
8915
8916
8917
8918
8919
8920
8921
8922
8923
8924
8925
8926
8927
8928
8929
8930
8931
8932
8933
8934
8935
8936
8937
8938
8939
8940
8941
8942
8943
8944
8945
8946
8947
8948
8949
8950
8951
8952
8953
8954
8955
8956
8957
8958
8959
8960
8961
8962
8963
8964
8965
8966
8967
8968
8969
8970
8971
8972
8973
8974
8975
8976
8977
8978
8979
8980
8981
8982
8983
8984
8985
8986
8987
8988
8989
8990
8991
8992
8993
8994
8995
8996
8997
8998
8999
9000
9001
9002
9003
9004
9005
9006
9007
9008
9009
9010
9011
9012
9013
9014
9015
9016
9017
9018
9019
9020
9021
9022
9023
9024
9025
9026
9027
9028
9029
9030
9031
9032
9033
9034
9035
9036
9037
9038
9039
9040
9041
9042
9043
9044
9045
9046
9047
9048
9049
9050
9051
9052
9053
9054
9055
9056
9057
9058
9059
9060
9061
9062
9063
9064
9065
9066
9067
9068
9069
9070
9071
9072
9073
9074
9075
9076
9077
9078
9079
9080
9081
9082
9083
9084
9085
9086
9087
9088
9089
9090
9091
9092
9093
9094
9095
9096
9097
9098
9099
9100
9101
9102
9103
9104
9105
9106
9107
9108
9109
9110
9111
9112
9113
9114
9115
9116
9117
9118
9119
9120
9121
9122
9123
9124
9125
9126
9127
9128
9129
9130
9131
9132
9133
9134
9135
9136
9137
9138
9139
9140
9141
9142
9143
9144
9145
9146
9147
9148
9149
9150
9151
9152
9153
9154
9155
9156
9157
9158
9159
9160
9161
9162
9163
9164
9165
9166
9167
9168
9169
9170
9171
9172
9173
9174
9175
9176
9177
9178
9179
9180
9181
9182
9183
9184
9185
9186
9187
9188
9189
9190
9191
9192
9193
9194
9195
9196
9197
9198
9199
9200
9201
9202
9203
9204
9205
9206
9207
9208
9209
9210
9211
9212
9213
9214
9215
9216
9217
9218
9219
9220
9221
9222
9223
9224
9225
9226
9227
9228
9229
9230
9231
9232
9233
9234
9235
9236
9237
9238
9239
9240
9241
9242
9243
9244
9245
9246
9247
9248
9249
9250
9251
9252
9253
9254
9255
9256
9257
9258
9259
9260
9261
9262
9263
9264
9265
9266
9267
9268
9269
9270
9271
9272
9273
9274
9275
9276
9277
9278
9279
9280
9281
9282
9283
9284
9285
9286
9287
9288
9289
9290
9291
9292
9293
9294
9295
9296
9297
9298
9299
9300
9301
9302
9303
9304
9305
9306
9307
9308
9309
9310
9311
9312
9313
9314
9315
9316
9317
9318
9319
9320
9321
9322
9323
9324
9325
9326
9327
9328
9329
9330
9331
9332
9333
9334
9335
9336
9337
9338
9339
9340
9341
9342
9343
9344
9345
9346
9347
9348
9349
9350
9351
9352
9353
9354
9355
9356
9357
9358
9359
9360
9361
9362
9363
9364
9365
9366
9367
9368
9369
9370
9371
9372
9373
9374
9375
9376
9377
9378
9379
9380
9381
9382
9383
9384
9385
9386
9387
9388
9389
9390
9391
9392
9393
9394
9395
9396
9397
9398
9399
9400
9401
9402
9403
9404
9405
9406
9407
9408
9409
9410
9411
9412
9413
9414
9415
9416
9417
9418
9419
9420
9421
9422
9423
9424
9425
9426
9427
9428
9429
9430
9431
9432
9433
9434
9435
9436
9437
9438
9439
9440
9441
9442
9443
9444
9445
9446
9447
9448
9449
9450
9451
9452
9453
9454
9455
9456
9457
9458
9459
9460
9461
9462
9463
9464
9465
9466
9467
9468
9469
9470
9471
9472
9473
9474
9475
9476
9477
9478
9479
9480
9481
9482
9483
9484
9485
9486
9487
9488
9489
9490
9491
9492
9493
9494
9495
9496
9497
9498
9499
9500
9501
9502
9503
9504
9505
9506
9507
9508
9509
9510
9511
9512
9513
9514
9515
9516
9517
9518
9519
9520
9521
9522
9523
9524
9525
9526
9527
9528
9529
9530
9531
9532
9533
9534
9535
9536
9537
9538
9539
9540
9541
9542
9543
9544
9545
9546
9547
9548
9549
9550
9551
9552
9553
9554
9555
9556
9557
9558
9559
9560
9561
9562
9563
9564
9565
9566
9567
9568
9569
9570
9571
9572
9573
9574
9575
9576
9577
9578
9579
9580
9581
9582
9583
9584
9585
9586
9587
9588
9589
9590
9591
9592
9593
9594
9595
9596
9597
9598
9599
9600
9601
9602
9603
9604
9605
9606
9607
9608
9609
9610
9611
9612
9613
9614
9615
9616
9617
9618
9619
9620
9621
9622
9623
9624
9625
9626
9627
9628
9629
9630
9631
9632
9633
9634
9635
9636
9637
9638
9639
9640
9641
9642
9643
9644
9645
9646
9647
9648
9649
9650
9651
9652
9653
9654
9655
9656
9657
9658
9659
9660
9661
9662
9663
9664
9665
9666
9667
9668
9669
9670
9671
9672
9673
9674
9675
9676
9677
9678
9679
9680
9681
9682
9683
9684
9685
9686
9687
9688
9689
9690
9691
9692
9693
9694
9695
9696
9697
9698
9699
9700
9701
9702
9703
9704
9705
9706
9707
9708
9709
9710
9711
9712
9713
9714
9715
9716
9717
9718
9719
9720
9721
9722
9723
9724
9725
9726
9727
9728
9729
9730
9731
9732
9733
9734
9735
9736
9737
9738
9739
9740
9741
9742
9743
9744
9745
9746
9747
9748
9749
9750
9751
9752
9753
9754
9755
9756
9757
9758
9759
9760
9761
9762
9763
9764
9765
9766
9767
9768
9769
9770
9771
9772
9773
9774
9775
9776
9777
9778
9779
9780
9781
9782
9783
9784
9785
9786
9787
9788
9789
9790
9791
9792
9793
9794
9795
9796
9797
9798
9799
9800
9801
9802
9803
9804
9805
9806
9807
9808
9809
9810
9811
9812
9813
9814
9815
9816
9817
9818
9819
9820
9821
9822
9823
9824
9825
9826
9827
9828
9829
9830
9831
9832
9833
9834
9835
9836
9837
9838
9839
9840
9841
9842
9843
9844
9845
9846
9847
9848
9849
9850
9851
9852
9853
9854
9855
9856
9857
9858
9859
9860
9861
9862
9863
9864
9865
9866
9867
9868
9869
9870
9871
9872
9873
9874
9875
9876
9877
9878
9879
9880
9881
9882
9883
9884
9885
9886
9887
9888
9889
9890
9891
9892
9893
9894
9895
9896
9897
9898
9899
9900
9901
9902
9903
9904
9905
9906
9907
9908
9909
9910
9911
9912
9913
9914
9915
9916
9917
9918
9919
9920
9921
9922
9923
9924
9925
9926
9927
9928
9929
9930
9931
9932
9933
9934
9935
9936
9937
9938
9939
9940
9941
9942
9943
9944
9945
9946
9947
9948
9949
9950
9951
9952
9953
9954
9955
9956
9957
9958
9959
9960
9961
9962
9963
9964
9965
9966
9967
9968
9969
9970
9971
9972
9973
9974
9975
9976
9977
9978
9979
9980
9981
9982
9983
9984
9985
9986
9987
9988
9989
9990
9991
9992
9993
9994
9995
9996
9997
9998
9999
10000
10001
10002
10003
10004
10005
10006
10007
10008
10009
10010
10011
10012
10013
10014
10015
10016
10017
10018
10019
10020
10021
10022
10023
10024
10025
10026
10027
10028
10029
10030
10031
10032
10033
10034
10035
10036
10037
10038
10039
10040
10041
10042
10043
10044
10045
10046
10047
10048
10049
10050
10051
10052
10053
10054
10055
10056
10057
10058
10059
10060
10061
10062
10063
10064
10065
10066
10067
10068
10069
10070
10071
10072
10073
10074
10075
10076
10077
10078
10079
10080
10081
10082
10083
10084
10085
10086
10087
10088
10089
10090
10091
10092
10093
10094
10095
10096
10097
10098
10099
10100
10101
10102
10103
10104
10105
10106
10107
10108
10109
10110
10111
10112
10113
10114
10115
10116
10117
10118
10119
10120
10121
10122
10123
10124
10125
10126
10127
10128
10129
10130
10131
10132
10133
10134
10135
10136
10137
10138
10139
10140
10141
10142
10143
10144
10145
10146
10147
10148
10149
10150
10151
10152
10153
10154
10155
10156
10157
10158
10159
10160
10161
10162
10163
10164
10165
10166
10167
10168
10169
10170
10171
10172
10173
10174
10175
10176
10177
10178
10179
10180
10181
10182
10183
10184
10185
10186
10187
10188
10189
10190
10191
10192
10193
10194
10195
10196
10197
10198
10199
10200
10201
10202
10203
10204
10205
10206
10207
10208
10209
10210
10211
10212
10213
10214
10215
10216
10217
10218
10219
10220
10221
10222
10223
10224
10225
10226
10227
10228
10229
10230
10231
10232
10233
10234
10235
10236
10237
10238
10239
10240
10241
10242
10243
10244
10245
10246
10247
10248
10249
10250
10251
10252
10253
10254
10255
10256
10257
10258
10259
10260
10261
10262
10263
10264
10265
10266
10267
10268
10269
10270
10271
10272
10273
10274
10275
10276
10277
10278
10279
10280
10281
10282
10283
10284
10285
10286
10287
10288
10289
10290
10291
10292
10293
10294
10295
10296
10297
10298
10299
10300
10301
10302
10303
10304
10305
10306
10307
10308
10309
10310
10311
10312
10313
10314
10315
10316
10317
10318
10319
10320
10321
10322
10323
10324
10325
10326
10327
10328
10329
10330
10331
10332
10333
10334
10335
10336
10337
10338
10339
10340
10341
10342
10343
10344
10345
10346
10347
10348
10349
10350
10351
10352
10353
10354
10355
10356
10357
10358
10359
10360
10361
10362
10363
10364
10365
10366
10367
10368
10369
10370
10371
10372
10373
10374
10375
10376
10377
10378
10379
10380
10381
10382
10383
10384
10385
10386
10387
10388
10389
10390
10391
10392
10393
10394
10395
10396
10397
10398
10399
10400
10401
10402
10403
10404
10405
10406
10407
10408
10409
10410
10411
10412
10413
10414
10415
10416
10417
10418
10419
10420
10421
10422
10423
10424
10425
10426
10427
10428
10429
10430
10431
10432
10433
10434
10435
10436
10437
10438
10439
10440
10441
10442
10443
10444
10445
10446
10447
10448
10449
10450
10451
10452
10453
10454
10455
10456
10457
10458
10459
10460
10461
10462
10463
10464
10465
10466
10467
10468
10469
10470
10471
10472
10473
10474
10475
10476
10477
10478
10479
10480
10481
10482
10483
10484
10485
10486
10487
10488
10489
10490
10491
10492
10493
10494
10495
10496
10497
10498
10499
10500
10501
10502
10503
10504
10505
10506
10507
10508
10509
10510
10511
10512
10513
10514
10515
10516
10517
10518
10519
10520
10521
10522
10523
10524
10525
10526
10527
10528
10529
10530
10531
10532
10533
10534
10535
10536
10537
10538
10539
10540
10541
10542
10543
10544
10545
10546
10547
10548
10549
10550
10551
10552
10553
10554
10555
10556
10557
10558
10559
10560
10561
10562
10563
10564
10565
10566
10567
10568
10569
10570
10571
10572
10573
10574
10575
10576
10577
10578
10579
10580
10581
10582
10583
10584
10585
10586
10587
10588
10589
10590
10591
10592
10593
10594
10595
10596
10597
10598
10599
10600
10601
10602
10603
10604
10605
10606
10607
10608
10609
10610
10611
10612
10613
10614
10615
10616
10617
10618
10619
10620
10621
10622
10623
10624
10625
10626
10627
10628
10629
10630
10631
10632
10633
10634
10635
10636
10637
10638
10639
10640
10641
10642
10643
10644
10645
10646
10647
10648
10649
10650
10651
10652
10653
10654
10655
10656
10657
10658
10659
10660
10661
10662
10663
10664
10665
10666
10667
10668
10669
10670
10671
10672
10673
10674
10675
10676
10677
10678
10679
10680
10681
10682
10683
10684
10685
10686
10687
10688
10689
10690
10691
10692
10693
10694
10695
10696
10697
10698
10699
10700
10701
10702
10703
10704
10705
10706
10707
10708
10709
10710
10711
10712
10713
10714
10715
10716
10717
10718
10719
10720
10721
10722
10723
10724
10725
10726
10727
10728
10729
10730
10731
10732
10733
10734
10735
10736
10737
10738
10739
10740
10741
10742
10743
10744
10745
10746
10747
10748
10749
10750
10751
10752
10753
10754
10755
10756
10757
10758
10759
10760
10761
10762
10763
10764
10765
10766
10767
10768
10769
10770
10771
10772
10773
10774
10775
10776
10777
10778
10779
10780
10781
10782
10783
10784
10785
10786
10787
10788
10789
10790
10791
10792
10793
10794
10795
10796
10797
10798
10799
10800
10801
10802
10803
10804
10805
10806
10807
10808
10809
10810
10811
10812
10813
10814
10815
10816
10817
10818
10819
10820
10821
10822
10823
10824
10825
10826
10827
10828
10829
10830
10831
10832
10833
10834
10835
10836
10837
10838
10839
10840
10841
10842
10843
10844
10845
10846
10847
10848
10849
10850
10851
10852
10853
10854
10855
10856
10857
10858
10859
10860
10861
10862
10863
10864
10865
10866
10867
10868
10869
10870
10871
10872
10873
10874
10875
10876
10877
10878
10879
10880
10881
10882
10883
10884
10885
10886
10887
10888
10889
10890
10891
10892
10893
10894
10895
10896
10897
10898
10899
10900
10901
10902
10903
10904
10905
10906
10907
10908
10909
10910
10911
10912
10913
10914
10915
10916
10917
10918
10919
10920
10921
10922
10923
10924
10925
10926
10927
10928
10929
10930
10931
10932
10933
10934
10935
10936
10937
10938
10939
10940
10941
10942
10943
10944
10945
10946
10947
10948
10949
10950
10951
10952
10953
10954
10955
10956
10957
10958
10959
10960
10961
10962
10963
10964
10965
10966
10967
10968
10969
10970
10971
10972
10973
10974
10975
10976
10977
10978
10979
10980
10981
10982
10983
10984
10985
10986
10987
10988
10989
10990
10991
10992
10993
10994
10995
10996
10997
10998
10999
11000
11001
11002
11003
11004
11005
11006
11007
11008
11009
11010
11011
11012
11013
11014
11015
11016
11017
11018
11019
11020
11021
11022
11023
11024
11025
11026
11027
11028
11029
11030
11031
11032
11033
11034
11035
11036
11037
11038
11039
11040
11041
11042
11043
11044
11045
11046
11047
11048
11049
11050
11051
11052
11053
11054
11055
11056
11057
11058
11059
11060
11061
11062
11063
11064
11065
11066
11067
11068
11069
11070
11071
11072
11073
11074
11075
11076
11077
11078
11079
11080
11081
11082
11083
11084
11085
11086
11087
11088
11089
11090
11091
11092
11093
11094
11095
11096
11097
11098
11099
11100
11101
11102
11103
11104
11105
11106
11107
11108
11109
11110
11111
11112
11113
11114
11115
11116
11117
11118
11119
11120
11121
11122
11123
11124
11125
11126
11127
11128
11129
11130
11131
11132
11133
11134
11135
11136
11137
11138
11139
11140
11141
11142
11143
11144
11145
11146
11147
11148
11149
11150
11151
11152
11153
11154
11155
11156
11157
11158
11159
11160
11161
11162
11163
11164
11165
11166
11167
11168
11169
11170
11171
11172
11173
11174
11175
11176
11177
11178
11179
11180
11181
11182
11183
11184
11185
11186
11187
11188
11189
11190
11191
11192
11193
11194
11195
11196
11197
11198
11199
11200
11201
11202
11203
11204
11205
11206
11207
11208
11209
11210
11211
11212
11213
11214
11215
11216
11217
11218
11219
11220
11221
11222
11223
11224
11225
11226
11227
11228
11229
11230
11231
11232
11233
11234
11235
11236
11237
11238
11239
11240
11241
11242
11243
11244
11245
11246
11247
11248
11249
11250
11251
11252
11253
11254
11255
11256
11257
11258
11259
11260
11261
11262
11263
11264
11265
11266
11267
11268
11269
11270
11271
11272
11273
11274
11275
11276
11277
11278
11279
11280
11281
11282
11283
11284
11285
11286
11287
11288
11289
11290
11291
11292
11293
11294
11295
11296
11297
11298
11299
11300
11301
11302
11303
11304
11305
11306
11307
11308
11309
11310
11311
11312
11313
11314
11315
11316
11317
11318
11319
11320
11321
11322
11323
11324
11325
11326
11327
11328
11329
11330
11331
11332
11333
11334
11335
11336
11337
11338
11339
11340
11341
11342
11343
11344
11345
11346
11347
11348
11349
11350
11351
11352
11353
11354
11355
11356
11357
11358
11359
11360
11361
11362
11363
11364
11365
11366
11367
11368
11369
11370
11371
11372
11373
11374
11375
11376
11377
11378
11379
11380
11381
11382
11383
11384
11385
11386
11387
11388
11389
11390
11391
11392
11393
11394
11395
11396
11397
11398
11399
11400
11401
11402
11403
11404
11405
11406
11407
11408
11409
11410
11411
11412
11413
11414
11415
11416
11417
11418
11419
11420
11421
11422
11423
11424
11425
11426
11427
11428
11429
11430
11431
11432
11433
11434
11435
11436
11437
11438
11439
11440
11441
11442
11443
11444
11445
11446
11447
11448
11449
11450
11451
11452
11453
11454
11455
11456
11457
11458
11459
11460
11461
11462
11463
11464
11465
11466
11467
11468
11469
11470
11471
11472
11473
11474
11475
11476
11477
11478
11479
11480
11481
11482
11483
11484
11485
11486
11487
11488
11489
11490
11491
11492
11493
11494
11495
11496
11497
11498
11499
11500
11501
11502
11503
11504
11505
11506
11507
11508
11509
11510
11511
11512
11513
11514
11515
11516
11517
11518
11519
11520
11521
11522
11523
11524
11525
11526
11527
11528
11529
11530
11531
11532
11533
11534
11535
11536
11537
11538
11539
11540
11541
11542
11543
11544
11545
11546
11547
11548
11549
11550
11551
11552
11553
11554
11555
11556
11557
11558
11559
11560
11561
11562
11563
11564
11565
11566
11567
11568
11569
11570
11571
11572
11573
11574
11575
11576
11577
11578
11579
11580
11581
11582
11583
11584
11585
11586
11587
11588
11589
11590
11591
11592
11593
11594
11595
11596
11597
11598
11599
11600
11601
11602
11603
11604
11605
11606
11607
11608
11609
11610
11611
11612
11613
11614
11615
11616
11617
11618
11619
11620
11621
11622
11623
11624
11625
11626
11627
11628
11629
11630
11631
11632
11633
11634
11635
11636
11637
11638
11639
11640
11641
11642
11643
11644
11645
11646
11647
11648
11649
11650
11651
11652
11653
11654
11655
11656
11657
11658
11659
11660
11661
11662
11663
11664
11665
11666
11667
11668
11669
11670
11671
11672
11673
11674
11675
11676
11677
11678
11679
11680
11681
11682
11683
11684
11685
11686
11687
11688
11689
11690
11691
11692
11693
11694
11695
11696
11697
11698
11699
11700
11701
11702
11703
11704
11705
11706
11707
11708
11709
11710
11711
11712
11713
11714
11715
11716
11717
11718
11719
11720
11721
11722
11723
11724
11725
11726
11727
11728
11729
11730
11731
11732
11733
11734
11735
11736
11737
11738
11739
11740
11741
11742
11743
11744
11745
11746
11747
11748
11749
11750
11751
11752
11753
11754
11755
11756
11757
11758
11759
11760
11761
11762
11763
11764
11765
11766
11767
11768
11769
11770
11771
11772
11773
11774
11775
11776
11777
11778
11779
11780
11781
11782
11783
11784
11785
11786
11787
11788
11789
11790
11791
11792
11793
11794
11795
11796
11797
11798
11799
11800
11801
11802
11803
11804
11805
11806
11807
11808
11809
11810
11811
11812
11813
11814
11815
11816
11817
11818
11819
11820
11821
11822
11823
11824
11825
11826
11827
11828
11829
11830
11831
11832
11833
11834
11835
11836
11837
11838
11839
11840
11841
11842
11843
11844
11845
11846
11847
11848
11849
11850
11851
11852
11853
11854
11855
11856
11857
11858
11859
11860
11861
11862
11863
11864
11865
11866
11867
11868
11869
11870
11871
11872
11873
11874
11875
11876
11877
11878
11879
11880
11881
11882
11883
11884
11885
11886
11887
11888
11889
11890
11891
11892
11893
11894
11895
11896
11897
11898
11899
11900
11901
11902
11903
11904
11905
11906
11907
11908
11909
11910
11911
11912
11913
11914
11915
11916
11917
11918
11919
11920
11921
11922
11923
11924
11925
11926
11927
11928
11929
11930
11931
11932
11933
11934
11935
11936
11937
11938
11939
11940
11941
11942
11943
11944
11945
11946
11947
11948
11949
11950
11951
11952
11953
11954
11955
11956
11957
11958
11959
11960
11961
11962
11963
11964
11965
11966
11967
11968
11969
11970
11971
11972
11973
11974
11975
11976
11977
11978
11979
11980
11981
11982
11983
11984
11985
11986
11987
11988
11989
11990
11991
11992
11993
11994
11995
11996
11997
11998
11999
12000
12001
12002
12003
12004
12005
12006
12007
12008
12009
12010
12011
12012
12013
12014
12015
12016
12017
12018
12019
12020
12021
12022
12023
12024
12025
12026
12027
12028
12029
12030
12031
12032
12033
12034
12035
12036
12037
12038
12039
12040
12041
12042
12043
12044
12045
12046
12047
12048
12049
12050
12051
12052
12053
12054
12055
12056
12057
12058
12059
12060
12061
12062
12063
12064
12065
12066
12067
12068
12069
12070
12071
12072
12073
12074
12075
12076
12077
12078
12079
12080
12081
12082
12083
12084
12085
12086
12087
12088
12089
12090
12091
12092
12093
12094
12095
12096
12097
12098
12099
12100
12101
12102
12103
12104
12105
12106
12107
12108
12109
12110
12111
12112
12113
12114
12115
12116
12117
12118
12119
12120
12121
12122
12123
12124
12125
12126
12127
12128
12129
12130
12131
12132
12133
12134
12135
12136
12137
12138
12139
12140
12141
12142
12143
12144
12145
12146
12147
12148
12149
12150
12151
12152
12153
12154
12155
12156
12157
12158
12159
12160
12161
12162
12163
12164
12165
12166
12167
12168
12169
12170
12171
12172
12173
12174
12175
12176
12177
12178
12179
12180
12181
12182
12183
12184
12185
12186
12187
12188
12189
12190
12191
12192
12193
12194
12195
12196
12197
12198
12199
12200
12201
12202
12203
12204
12205
12206
12207
12208
12209
12210
12211
12212
12213
12214
12215
12216
12217
12218
12219
12220
12221
12222
12223
12224
12225
12226
12227
12228
12229
12230
12231
12232
12233
12234
12235
12236
12237
12238
12239
12240
12241
12242
12243
12244
12245
12246
12247
12248
12249
12250
12251
12252
12253
12254
12255
12256
12257
12258
12259
12260
12261
12262
12263
12264
12265
12266
12267
12268
12269
12270
12271
12272
12273
12274
12275
12276
12277
12278
12279
12280
12281
12282
12283
12284
12285
12286
12287
12288
12289
12290
12291
12292
12293
12294
12295
12296
12297
12298
12299
12300
12301
12302
12303
12304
12305
12306
12307
12308
12309
12310
12311
12312
12313
12314
12315
12316
12317
12318
12319
12320
12321
12322
12323
12324
12325
12326
12327
12328
12329
12330
12331
12332
12333
12334
12335
12336
12337
12338
12339
12340
12341
12342
12343
12344
12345
12346
12347
12348
12349
12350
12351
12352
12353
12354
12355
12356
12357
12358
12359
12360
12361
12362
12363
12364
12365
12366
12367
12368
12369
12370
12371
12372
12373
12374
12375
12376
12377
12378
12379
12380
12381
12382
12383
12384
12385
12386
12387
12388
12389
12390
12391
12392
12393
12394
12395
12396
12397
12398
12399
12400
12401
12402
12403
12404
12405
12406
12407
12408
12409
12410
12411
12412
12413
12414
12415
12416
12417
12418
12419
12420
12421
12422
12423
12424
12425
12426
12427
12428
12429
12430
12431
12432
12433
12434
12435
12436
12437
12438
12439
12440
12441
12442
12443
12444
12445
12446
12447
12448
12449
12450
12451
12452
12453
12454
12455
12456
12457
12458
12459
12460
12461
12462
12463
12464
12465
12466
12467
12468
12469
12470
12471
12472
12473
12474
12475
12476
12477
12478
12479
12480
12481
12482
12483
12484
12485
12486
12487
12488
12489
12490
12491
12492
12493
12494
12495
12496
12497
12498
12499
12500
12501
12502
12503
12504
12505
12506
12507
12508
12509
12510
12511
12512
12513
12514
12515
12516
12517
12518
12519
12520
12521
12522
12523
12524
12525
12526
12527
12528
12529
12530
12531
12532
12533
12534
12535
12536
12537
12538
12539
12540
12541
12542
12543
12544
12545
12546
12547
12548
12549
12550
12551
12552
12553
12554
12555
12556
12557
12558
12559
12560
12561
12562
12563
12564
12565
12566
12567
12568
12569
12570
12571
12572
12573
12574
12575
12576
12577
12578
12579
12580
12581
12582
12583
12584
12585
12586
12587
12588
12589
12590
12591
12592
12593
12594
12595
12596
12597
12598
12599
12600
12601
12602
12603
12604
12605
12606
12607
12608
12609
12610
12611
12612
12613
12614
12615
12616
12617
12618
12619
12620
12621
12622
12623
12624
12625
12626
12627
12628
12629
12630
12631
12632
12633
12634
12635
12636
12637
12638
12639
12640
12641
12642
12643
12644
12645
12646
12647
12648
12649
12650
12651
12652
12653
12654
12655
12656
12657
12658
12659
12660
12661
12662
12663
12664
12665
12666
12667
12668
12669
12670
12671
12672
12673
12674
12675
12676
12677
12678
12679
12680
12681
12682
12683
12684
12685
12686
12687
12688
12689
12690
12691
12692
12693
12694
12695
12696
12697
12698
12699
12700
12701
12702
12703
12704
12705
12706
12707
12708
12709
12710
12711
12712
12713
12714
12715
12716
12717
12718
12719
12720
12721
12722
12723
12724
12725
12726
12727
12728
12729
12730
12731
12732
12733
12734
12735
12736
12737
12738
12739
12740
12741
12742
12743
12744
12745
12746
12747
12748
12749
12750
12751
12752
12753
12754
12755
12756
12757
12758
12759
12760
12761
12762
12763
12764
12765
12766
12767
12768
12769
12770
12771
12772
12773
12774
12775
12776
12777
12778
12779
12780
12781
12782
12783
12784
12785
12786
12787
12788
12789
12790
12791
12792
12793
12794
12795
12796
12797
12798
12799
12800
12801
12802
12803
12804
12805
12806
12807
12808
12809
12810
12811
12812
12813
12814
12815
12816
12817
12818
12819
12820
12821
12822
12823
12824
12825
12826
12827
12828
12829
12830
12831
12832
12833
12834
12835
12836
12837
12838
12839
12840
12841
12842
12843
12844
12845
12846
12847
12848
12849
12850
12851
12852
12853
12854
12855
12856
12857
12858
12859
12860
12861
12862
12863
12864
12865
12866
12867
12868
12869
12870
12871
12872
12873
12874
12875
12876
12877
12878
12879
12880
12881
12882
12883
12884
12885
12886
12887
12888
12889
12890
12891
12892
12893
12894
12895
12896
12897
12898
12899
12900
12901
12902
12903
12904
12905
12906
12907
12908
12909
12910
12911
12912
12913
12914
12915
12916
12917
12918
12919
12920
12921
12922
12923
12924
12925
12926
12927
12928
12929
12930
12931
12932
12933
12934
12935
12936
12937
12938
12939
12940
12941
12942
12943
12944
12945
12946
12947
12948
12949
12950
12951
12952
12953
12954
12955
12956
12957
12958
12959
12960
12961
12962
12963
12964
12965
12966
12967
12968
12969
12970
12971
12972
12973
12974
12975
12976
12977
12978
12979
12980
12981
12982
12983
12984
12985
12986
12987
12988
12989
12990
12991
12992
12993
12994
12995
12996
12997
12998
12999
13000
13001
13002
13003
13004
13005
13006
13007
13008
13009
13010
13011
13012
13013
13014
13015
13016
13017
13018
13019
13020
13021
13022
13023
13024
13025
13026
13027
13028
13029
13030
13031
13032
13033
13034
13035
13036
13037
13038
13039
13040
13041
13042
13043
13044
13045
13046
13047
13048
13049
13050
13051
13052
13053
13054
13055
13056
13057
13058
13059
13060
13061
13062
13063
13064
13065
13066
13067
13068
13069
13070
13071
13072
13073
13074
13075
13076
13077
13078
13079
13080
13081
13082
13083
13084
13085
13086
13087
13088
13089
13090
13091
13092
13093
13094
13095
13096
13097
13098
13099
13100
13101
13102
13103
13104
13105
13106
13107
13108
13109
13110
13111
13112
13113
13114
13115
13116
13117
13118
13119
13120
13121
13122
13123
13124
13125
13126
13127
13128
13129
13130
13131
13132
13133
13134
13135
13136
13137
13138
13139
13140
13141
13142
13143
13144
13145
13146
13147
13148
13149
13150
13151
13152
13153
13154
13155
13156
13157
13158
13159
13160
13161
13162
13163
13164
13165
13166
13167
13168
13169
13170
13171
13172
13173
13174
13175
13176
13177
13178
13179
13180
13181
13182
13183
13184
13185
13186
13187
13188
13189
13190
13191
13192
13193
13194
13195
13196
13197
13198
13199
13200
13201
13202
13203
13204
13205
13206
13207
13208
13209
13210
13211
13212
13213
13214
13215
13216
13217
13218
13219
13220
13221
13222
13223
13224
13225
13226
13227
13228
13229
13230
13231
13232
13233
13234
13235
13236
13237
13238
13239
13240
13241
13242
13243
13244
13245
13246
13247
13248
13249
13250
13251
13252
13253
13254
13255
13256
13257
13258
13259
13260
13261
13262
13263
13264
13265
13266
13267
13268
13269
13270
13271
13272
13273
13274
13275
13276
13277
13278
13279
13280
13281
13282
13283
13284
13285
13286
13287
13288
13289
13290
13291
13292
13293
13294
13295
13296
13297
13298
13299
13300
13301
13302
13303
13304
13305
13306
13307
13308
13309
13310
13311
13312
13313
13314
13315
13316
13317
13318
13319
13320
13321
13322
13323
13324
13325
13326
13327
13328
13329
13330
13331
13332
13333
13334
13335
13336
13337
13338
13339
13340
13341
13342
13343
13344
13345
13346
13347
13348
13349
13350
13351
13352
13353
13354
13355
13356
13357
13358
13359
13360
13361
13362
13363
13364
13365
13366
13367
13368
13369
13370
13371
13372
13373
13374
13375
13376
13377
13378
13379
13380
13381
13382
13383
13384
13385
13386
13387
13388
13389
13390
13391
13392
13393
13394
13395
13396
13397
13398
13399
13400
13401
13402
13403
13404
13405
13406
13407
13408
13409
13410
13411
13412
13413
13414
13415
13416
13417
13418
13419
13420
13421
13422
13423
13424
13425
13426
13427
13428
13429
13430
13431
13432
13433
13434
13435
13436
13437
13438
13439
13440
13441
13442
13443
13444
13445
13446
13447
13448
13449
13450
13451
13452
13453
13454
13455
13456
13457
13458
13459
13460
13461
13462
13463
13464
13465
13466
13467
13468
13469
13470
13471
13472
13473
13474
13475
13476
13477
13478
13479
13480
13481
13482
13483
13484
13485
13486
13487
13488
13489
13490
13491
13492
13493
13494
13495
13496
13497
13498
13499
13500
13501
13502
13503
13504
13505
13506
13507
13508
13509
13510
13511
13512
13513
13514
13515
13516
13517
13518
13519
13520
13521
13522
13523
13524
13525
13526
13527
13528
13529
13530
13531
13532
13533
13534
13535
13536
13537
13538
13539
13540
13541
13542
13543
13544
13545
13546
13547
13548
13549
13550
13551
13552
13553
13554
13555
13556
13557
13558
13559
13560
13561
13562
13563
13564
13565
13566
13567
13568
13569
13570
13571
13572
13573
13574
13575
13576
13577
13578
13579
13580
13581
13582
13583
13584
13585
13586
13587
13588
13589
13590
13591
13592
13593
13594
13595
13596
13597
13598
13599
13600
13601
13602
13603
13604
13605
13606
13607
13608
13609
13610
13611
13612
13613
13614
13615
13616
13617
13618
13619
13620
13621
13622
13623
13624
13625
13626
13627
13628
13629
13630
13631
13632
13633
13634
13635
13636
13637
13638
13639
13640
13641
13642
13643
13644
13645
13646
13647
13648
13649
13650
13651
13652
13653
13654
13655
13656
13657
13658
13659
13660
13661
13662
13663
13664
13665
13666
13667
13668
13669
13670
13671
13672
13673
13674
13675
13676
13677
13678
13679
13680
13681
13682
13683
13684
13685
13686
13687
13688
13689
13690
13691
13692
13693
13694
13695
13696
13697
13698
13699
13700
13701
13702
13703
13704
13705
13706
13707
13708
13709
13710
13711
13712
13713
13714
13715
13716
13717
13718
13719
13720
13721
13722
13723
13724
13725
13726
13727
13728
13729
13730
13731
13732
13733
13734
13735
13736
13737
13738
13739
13740
13741
13742
13743
13744
13745
13746
13747
13748
13749
13750
13751
13752
13753
13754
13755
13756
13757
13758
13759
13760
13761
13762
13763
13764
13765
13766
13767
13768
13769
13770
13771
13772
13773
13774
13775
13776
13777
13778
13779
13780
13781
13782
13783
13784
13785
13786
13787
13788
13789
13790
13791
13792
13793
13794
13795
13796
13797
13798
13799
13800
13801
13802
13803
13804
13805
13806
13807
13808
13809
13810
13811
13812
13813
13814
13815
13816
13817
13818
13819
13820
13821
13822
13823
13824
13825
13826
13827
13828
13829
13830
13831
13832
13833
13834
13835
13836
13837
13838
13839
13840
13841
13842
13843
13844
13845
13846
13847
13848
13849
13850
13851
13852
13853
13854
13855
13856
13857
13858
13859
13860
13861
13862
13863
13864
13865
13866
13867
13868
13869
13870
13871
13872
13873
13874
13875
13876
13877
13878
13879
13880
13881
13882
13883
13884
13885
13886
13887
13888
13889
13890
13891
13892
13893
13894
13895
13896
13897
13898
13899
13900
13901
13902
13903
13904
13905
13906
13907
13908
13909
13910
13911
13912
13913
13914
13915
13916
13917
13918
13919
13920
13921
13922
13923
13924
13925
13926
13927
13928
13929
13930
13931
13932
13933
13934
13935
13936
13937
13938
13939
13940
13941
13942
13943
13944
13945
13946
13947
13948
13949
13950
13951
13952
13953
13954
13955
13956
13957
13958
13959
13960
13961
13962
13963
13964
13965
13966
13967
13968
13969
13970
13971
13972
13973
13974
13975
13976
13977
13978
13979
13980
13981
13982
13983
13984
13985
13986
13987
13988
13989
13990
13991
13992
13993
13994
13995
13996
13997
13998
13999
14000
14001
14002
14003
14004
14005
14006
14007
14008
14009
14010
14011
14012
14013
14014
14015
14016
14017
14018
14019
14020
14021
14022
14023
14024
14025
14026
14027
14028
14029
14030
14031
14032
14033
14034
14035
14036
14037
14038
14039
14040
14041
14042
14043
14044
14045
14046
14047
14048
14049
14050
14051
14052
14053
14054
14055
14056
14057
14058
14059
14060
14061
14062
14063
14064
14065
14066
14067
14068
14069
14070
14071
14072
14073
14074
14075
14076
14077
14078
14079
14080
14081
14082
14083
14084
14085
14086
14087
14088
14089
14090
14091
14092
14093
14094
14095
14096
14097
14098
14099
14100
14101
14102
14103
14104
14105
14106
14107
14108
14109
14110
14111
14112
14113
14114
14115
14116
14117
14118
14119
14120
14121
14122
14123
14124
14125
14126
14127
14128
14129
14130
14131
14132
14133
14134
14135
14136
14137
14138
14139
14140
14141
14142
14143
14144
14145
14146
14147
14148
14149
14150
14151
14152
14153
14154
14155
14156
14157
14158
14159
14160
14161
14162
14163
14164
14165
14166
14167
14168
14169
14170
14171
14172
14173
14174
14175
14176
14177
14178
14179
14180
14181
14182
14183
14184
14185
14186
14187
14188
14189
14190
14191
14192
14193
14194
14195
14196
14197
14198
14199
14200
14201
14202
14203
14204
14205
14206
14207
14208
14209
14210
14211
14212
14213
14214
14215
14216
14217
14218
14219
14220
14221
14222
14223
14224
14225
14226
14227
14228
14229
14230
14231
14232
14233
14234
14235
14236
14237
14238
14239
14240
14241
14242
14243
14244
14245
14246
14247
14248
14249
14250
14251
14252
14253
14254
14255
14256
14257
14258
14259
14260
14261
14262
14263
14264
14265
14266
14267
14268
14269
14270
14271
14272
14273
14274
14275
14276
14277
14278
14279
14280
14281
14282
14283
14284
14285
14286
14287
14288
14289
14290
14291
14292
14293
14294
14295
14296
14297
14298
14299
14300
14301
14302
14303
14304
14305
14306
14307
14308
14309
14310
14311
14312
14313
14314
14315
14316
14317
14318
14319
14320
14321
14322
14323
14324
14325
14326
14327
14328
14329
14330
14331
14332
14333
14334
14335
14336
14337
14338
14339
14340
14341
14342
14343
14344
14345
14346
14347
14348
14349
14350
14351
14352
14353
14354
14355
14356
14357
14358
14359
14360
14361
14362
14363
14364
14365
14366
14367
14368
14369
14370
14371
14372
14373
14374
14375
14376
14377
14378
14379
14380
14381
14382
14383
14384
14385
14386
14387
14388
14389
14390
14391
14392
14393
14394
14395
14396
14397
14398
14399
14400
14401
14402
14403
14404
14405
14406
14407
14408
14409
14410
14411
14412
14413
14414
14415
14416
14417
14418
14419
14420
14421
14422
14423
14424
14425
14426
14427
14428
14429
14430
14431
14432
14433
14434
14435
14436
14437
14438
14439
14440
14441
14442
14443
14444
14445
14446
14447
14448
14449
14450
14451
14452
14453
14454
14455
14456
14457
14458
14459
14460
14461
14462
14463
14464
14465
14466
14467
14468
14469
14470
14471
14472
14473
14474
14475
14476
14477
14478
14479
14480
14481
14482
14483
14484
14485
14486
14487
14488
14489
14490
14491
14492
14493
14494
14495
14496
14497
14498
14499
14500
14501
14502
14503
14504
14505
14506
14507
14508
14509
14510
14511
14512
14513
14514
14515
14516
14517
14518
14519
14520
14521
14522
14523
14524
14525
14526
14527
14528
14529
14530
14531
14532
14533
14534
14535
14536
14537
14538
14539
14540
14541
14542
14543
14544
14545
14546
14547
14548
14549
14550
14551
14552
14553
14554
14555
14556
14557
14558
14559
14560
14561
14562
14563
14564
14565
14566
14567
14568
14569
14570
14571
14572
14573
14574
14575
14576
14577
14578
14579
14580
14581
14582
14583
14584
14585
14586
14587
14588
14589
14590
14591
14592
14593
14594
14595
14596
14597
14598
14599
14600
14601
14602
14603
14604
14605
14606
14607
14608
14609
14610
14611
14612
14613
14614
14615
14616
14617
14618
14619
14620
14621
14622
14623
14624
14625
14626
14627
14628
14629
14630
14631
14632
14633
14634
14635
14636
14637
14638
14639
14640
14641
14642
14643
14644
14645
14646
14647
14648
14649
14650
14651
14652
14653
14654
14655
14656
14657
14658
14659
14660
14661
14662
14663
14664
14665
14666
14667
14668
14669
14670
14671
14672
14673
14674
14675
14676
14677
14678
14679
14680
14681
14682
14683
14684
14685
14686
14687
14688
14689
14690
14691
14692
14693
14694
14695
14696
14697
14698
14699
14700
14701
14702
14703
14704
14705
14706
14707
14708
14709
14710
14711
14712
14713
14714
14715
14716
14717
14718
14719
14720
14721
14722
14723
14724
14725
14726
14727
14728
14729
14730
14731
14732
14733
14734
14735
14736
14737
14738
14739
14740
14741
14742
14743
14744
14745
14746
14747
14748
14749
14750
14751
14752
14753
14754
14755
14756
14757
14758
14759
14760
14761
14762
14763
14764
14765
14766
14767
14768
14769
14770
14771
14772
14773
14774
14775
14776
14777
14778
14779
14780
14781
14782
14783
14784
14785
14786
14787
14788
14789
14790
14791
14792
14793
14794
14795
14796
14797
14798
14799
14800
14801
14802
14803
14804
14805
14806
14807
14808
14809
14810
14811
14812
14813
14814
14815
14816
14817
14818
14819
14820
14821
14822
14823
14824
14825
14826
14827
14828
14829
14830
14831
14832
14833
14834
14835
14836
14837
14838
14839
14840
14841
14842
14843
14844
14845
14846
14847
14848
14849
14850
14851
14852
14853
14854
14855
14856
14857
14858
14859
14860
14861
14862
14863
14864
14865
14866
14867
14868
14869
14870
14871
14872
14873
14874
14875
14876
14877
14878
14879
14880
14881
14882
14883
14884
14885
14886
14887
14888
14889
14890
14891
14892
14893
14894
14895
14896
14897
14898
14899
14900
14901
14902
14903
14904
14905
14906
14907
14908
14909
14910
14911
14912
14913
14914
14915
14916
14917
14918
14919
14920
14921
14922
14923
14924
14925
14926
14927
14928
14929
14930
14931
14932
14933
14934
14935
14936
14937
14938
14939
14940
14941
14942
14943
14944
14945
14946
14947
14948
14949
14950
14951
14952
14953
14954
14955
14956
14957
14958
14959
14960
14961
14962
14963
14964
14965
14966
14967
14968
14969
14970
14971
14972
14973
14974
14975
14976
14977
14978
14979
14980
14981
14982
14983
14984
14985
14986
14987
14988
14989
14990
14991
14992
14993
14994
14995
14996
14997
14998
14999
15000
15001
15002
15003
15004
15005
15006
15007
15008
15009
15010
15011
15012
15013
15014
15015
15016
15017
15018
15019
15020
15021
15022
15023
15024
15025
15026
15027
15028
15029
15030
15031
15032
15033
15034
15035
15036
15037
15038
15039
15040
15041
15042
15043
15044
15045
15046
15047
15048
15049
15050
15051
15052
15053
15054
15055
15056
15057
15058
15059
15060
15061
15062
15063
15064
15065
15066
15067
15068
15069
15070
15071
15072
15073
15074
15075
15076
15077
15078
15079
15080
15081
15082
15083
15084
15085
15086
15087
15088
15089
15090
15091
15092
15093
15094
15095
15096
15097
15098
15099
15100
15101
15102
15103
15104
15105
15106
15107
15108
15109
15110
15111
15112
15113
15114
15115
15116
15117
15118
15119
15120
15121
15122
15123
15124
15125
15126
15127
15128
15129
15130
15131
15132
15133
15134
15135
15136
15137
15138
15139
15140
15141
15142
15143
15144
15145
15146
15147
15148
15149
15150
15151
15152
15153
15154
15155
15156
15157
15158
15159
15160
15161
15162
15163
15164
15165
15166
15167
15168
15169
15170
15171
15172
15173
15174
15175
15176
15177
15178
15179
15180
15181
15182
15183
15184
15185
15186
15187
15188
15189
15190
15191
15192
15193
15194
15195
15196
15197
15198
15199
15200
15201
15202
15203
15204
15205
15206
15207
15208
15209
15210
15211
15212
15213
15214
15215
15216
15217
15218
15219
15220
15221
15222
15223
15224
15225
15226
15227
15228
15229
15230
15231
15232
15233
15234
15235
15236
15237
15238
15239
15240
15241
15242
15243
15244
15245
15246
15247
15248
15249
15250
15251
15252
15253
15254
15255
15256
15257
15258
15259
/* SPDX-License-Identifier: MIT */
/* Copyright 2024 Advanced Micro Devices, Inc. */
#ifndef _dcn_3_5_1_OFFSET_HEADER
#define _dcn_3_5_1_OFFSET_HEADER

// addressBlock: dce_dc_hda_azcontroller_azdec
// base address: 0x1300000
#define regGLOBAL_CAPABILITIES                                                                          0x4b7000
#define regGLOBAL_CAPABILITIES_BASE_IDX                                                                 3
#define regMINOR_VERSION                                                                                0x4b7000
#define regMINOR_VERSION_BASE_IDX                                                                       3
#define regMAJOR_VERSION                                                                                0x4b7000
#define regMAJOR_VERSION_BASE_IDX                                                                       3
#define regOUTPUT_PAYLOAD_CAPABILITY                                                                    0x4b7001
#define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                           3
#define regINPUT_PAYLOAD_CAPABILITY                                                                     0x4b7001
#define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                            3
#define regGLOBAL_CONTROL                                                                               0x4b7002
#define regGLOBAL_CONTROL_BASE_IDX                                                                      3
#define regWAKE_ENABLE                                                                                  0x4b7003
#define regWAKE_ENABLE_BASE_IDX                                                                         3
#define regSTATE_CHANGE_STATUS                                                                          0x4b7003
#define regSTATE_CHANGE_STATUS_BASE_IDX                                                                 3
#define regGLOBAL_STATUS                                                                                0x4b7004
#define regGLOBAL_STATUS_BASE_IDX                                                                       3
#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY                                                             0x4b7006
#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX                                                    3
#define regINPUT_STREAM_PAYLOAD_CAPABILITY                                                              0x4b7006
#define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX                                                     3
#define regINTERRUPT_CONTROL                                                                            0x4b7008
#define regINTERRUPT_CONTROL_BASE_IDX                                                                   3
#define regINTERRUPT_STATUS                                                                             0x4b7009
#define regINTERRUPT_STATUS_BASE_IDX                                                                    3
#define regWALL_CLOCK_COUNTER                                                                           0x4b700c
#define regWALL_CLOCK_COUNTER_BASE_IDX                                                                  3
#define regSTREAM_SYNCHRONIZATION                                                                       0x4b700e
#define regSTREAM_SYNCHRONIZATION_BASE_IDX                                                              3
#define regCORB_LOWER_BASE_ADDRESS                                                                      0x4b7010
#define regCORB_LOWER_BASE_ADDRESS_BASE_IDX                                                             3
#define regCORB_UPPER_BASE_ADDRESS                                                                      0x4b7011
#define regCORB_UPPER_BASE_ADDRESS_BASE_IDX                                                             3
#define regAZCONTROLLER0_CORB_WRITE_POINTER                                                             0x4b7012
#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX                                                    3
#define regAZCONTROLLER0_CORB_READ_POINTER                                                              0x4b7012
#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX                                                     3
#define regAZCONTROLLER0_CORB_CONTROL                                                                   0x4b7013
#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX                                                          3
#define regAZCONTROLLER0_CORB_STATUS                                                                    0x4b7013
#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX                                                           3
#define regAZCONTROLLER0_CORB_SIZE                                                                      0x4b7013
#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX                                                             3
#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS                                                        0x4b7014
#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX                                               3
#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS                                                        0x4b7015
#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX                                               3
#define regAZCONTROLLER0_RIRB_WRITE_POINTER                                                             0x4b7016
#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX                                                    3
#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT                                                       0x4b7016
#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX                                              3
#define regAZCONTROLLER0_RIRB_CONTROL                                                                   0x4b7017
#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX                                                          3
#define regAZCONTROLLER0_RIRB_STATUS                                                                    0x4b7017
#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX                                                           3
#define regAZCONTROLLER0_RIRB_SIZE                                                                      0x4b7017
#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX                                                             3
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE                                             0x4b7018
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                    3
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                        0x4b7018
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                               3
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                       0x4b7018
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                              3
#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE                                             0x4b7019
#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                    3
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS                                                       0x4b701a
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX                                              3
#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS                                                0x4b701c
#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                       3
#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS                                                0x4b701d
#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                       3
#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS                                                       0x4b780c
#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                              3

// addressBlock: azendpoint_sinkinfoind
// base address: 0x0
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
#define ixSINK_DESCRIPTION0                                                                            0x0005
#define ixSINK_DESCRIPTION1                                                                            0x0006
#define ixSINK_DESCRIPTION2                                                                            0x0007
#define ixSINK_DESCRIPTION3                                                                            0x0008
#define ixSINK_DESCRIPTION4                                                                            0x0009
#define ixSINK_DESCRIPTION5                                                                            0x000a
#define ixSINK_DESCRIPTION6                                                                            0x000b
#define ixSINK_DESCRIPTION7                                                                            0x000c
#define ixSINK_DESCRIPTION8                                                                            0x000d
#define ixSINK_DESCRIPTION9                                                                            0x000e
#define ixSINK_DESCRIPTION10                                                                           0x000f
#define ixSINK_DESCRIPTION11                                                                           0x0010
#define ixSINK_DESCRIPTION12                                                                           0x0011
#define ixSINK_DESCRIPTION13                                                                           0x0012
#define ixSINK_DESCRIPTION14                                                                           0x0013
#define ixSINK_DESCRIPTION15                                                                           0x0014
#define ixSINK_DESCRIPTION16                                                                           0x0015
#define ixSINK_DESCRIPTION17                                                                           0x0016


// addressBlock: azf0controller_azinputcrc0resultind
// base address: 0x0
#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007


// addressBlock: azf0controller_azinputcrc1resultind
// base address: 0x0
#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007


// addressBlock: azf0controller_azcrc0resultind
// base address: 0x0
#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007


// addressBlock: azf0controller_azcrc1resultind
// base address: 0x0
#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007


// addressBlock: azf0stream0_streamind
// base address: 0x0
#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004


// addressBlock: azf0stream1_streamind
// base address: 0x0
#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004


// addressBlock: azf0stream2_streamind
// base address: 0x0
#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004


// addressBlock: azf0stream3_streamind
// base address: 0x0
#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004


// addressBlock: azf0stream4_streamind
// base address: 0x0
#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004


// addressBlock: azf0stream5_streamind
// base address: 0x0
#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004


// addressBlock: azf0stream6_streamind
// base address: 0x0
#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004


// addressBlock: azf0stream7_streamind
// base address: 0x0
#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004


// addressBlock: azf0stream8_streamind
// base address: 0x0
#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004


// addressBlock: azf0stream9_streamind
// base address: 0x0
#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004


// addressBlock: azf0stream10_streamind
// base address: 0x0
#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004


// addressBlock: azf0stream11_streamind
// base address: 0x0
#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004


// addressBlock: azf0stream12_streamind
// base address: 0x0
#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004


// addressBlock: azf0stream13_streamind
// base address: 0x0
#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004


// addressBlock: azf0stream14_streamind
// base address: 0x0
#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004


// addressBlock: azf0stream15_streamind
// base address: 0x0
#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004


// addressBlock: azf0endpoint0_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
#define ixAZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070


// addressBlock: azf0endpoint1_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
#define ixAZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070


// addressBlock: azf0endpoint2_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
#define ixAZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070


// addressBlock: azf0endpoint3_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
#define ixAZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070


// addressBlock: azf0endpoint4_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
#define ixAZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070


// addressBlock: azf0endpoint5_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
#define ixAZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070


// addressBlock: azf0endpoint6_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
#define ixAZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070


// addressBlock: azf0endpoint7_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
#define ixAZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070


// addressBlock: azf0inputendpoint0_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068


// addressBlock: azf0inputendpoint1_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068


// addressBlock: azf0inputendpoint2_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068


// addressBlock: azf0inputendpoint3_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068


// addressBlock: azf0inputendpoint4_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068


// addressBlock: azf0inputendpoint5_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068


// addressBlock: azf0inputendpoint6_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068


// addressBlock: azf0inputendpoint7_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068


// addressBlock: azendpoint_descriptorind
// base address: 0x0
#define ixAUDIO_DESCRIPTOR0                                                                            0x0001
#define ixAUDIO_DESCRIPTOR1                                                                            0x0002
#define ixAUDIO_DESCRIPTOR2                                                                            0x0003
#define ixAUDIO_DESCRIPTOR3                                                                            0x0004
#define ixAUDIO_DESCRIPTOR4                                                                            0x0005
#define ixAUDIO_DESCRIPTOR5                                                                            0x0006
#define ixAUDIO_DESCRIPTOR6                                                                            0x0007
#define ixAUDIO_DESCRIPTOR7                                                                            0x0008
#define ixAUDIO_DESCRIPTOR8                                                                            0x0009
#define ixAUDIO_DESCRIPTOR9                                                                            0x000a
#define ixAUDIO_DESCRIPTOR10                                                                           0x000b
#define ixAUDIO_DESCRIPTOR11                                                                           0x000c
#define ixAUDIO_DESCRIPTOR12                                                                           0x000d
#define ixAUDIO_DESCRIPTOR13                                                                           0x000e

// addressBlock: dce_dc_hda_azendpoint_azdec
// base address: 0x1300000
#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x4b7018
#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                      3
#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x4b7018
#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                     3


// addressBlock: dce_dc_hda_azinputendpoint_azdec
// base address: 0x1300000
#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                           0x4b7018
#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                  3
#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                          0x4b7018
#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                 3


// addressBlock: dce_dc_dccg_dccg_dispdec
// base address: 0x0
#define regPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
#define regPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
#define regPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
#define regPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
#define regDP_DTO_DBUF_EN                                                                               0x0044
#define regDP_DTO_DBUF_EN_BASE_IDX                                                                      1
#define regDSCCLK3_DTO_PARAM                                                                            0x0045
#define regDSCCLK3_DTO_PARAM_BASE_IDX                                                                   1
#define regDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
#define regDCCG_GATE_DISABLE_CNTL4                                                                      0x0049
#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX                                                             1
#define regDPSTREAMCLK_CNTL                                                                             0x004a
#define regDPSTREAMCLK_CNTL_BASE_IDX                                                                    1
#define regREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
#define regPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
#define regDCCG_PERFMON_CNTL2                                                                           0x004e
#define regDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1
#define regDCCG_GLOBAL_FGCG_REP_CNTL                                                                    0x0050
#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX                                                           1
#define regDCCG_DS_DTO_INCR                                                                             0x0053
#define regDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
#define regDCCG_DS_DTO_MODULO                                                                           0x0054
#define regDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
#define regDCCG_DS_CNTL                                                                                 0x0055
#define regDCCG_DS_CNTL_BASE_IDX                                                                        1
#define regDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
#define regDPREFCLK_CNTL                                                                                0x0058
#define regDPREFCLK_CNTL_BASE_IDX                                                                       1
#define regDCE_VERSION                                                                                  0x005e
#define regDCE_VERSION_BASE_IDX                                                                         1
#define regDCCG_GTC_CNTL                                                                                0x0060
#define regDCCG_GTC_CNTL_BASE_IDX                                                                       1
#define regDCCG_GTC_DTO_INCR                                                                            0x0061
#define regDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
#define regDCCG_GTC_DTO_MODULO                                                                          0x0062
#define regDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
#define regDCCG_GTC_CURRENT                                                                             0x0063
#define regDCCG_GTC_CURRENT_BASE_IDX                                                                    1
#define regSYMCLK32_SE_CNTL                                                                             0x0065
#define regSYMCLK32_SE_CNTL_BASE_IDX                                                                    1
#define regSYMCLK32_LE_CNTL                                                                             0x0066
#define regSYMCLK32_LE_CNTL_BASE_IDX                                                                    1
#define regDTBCLK_P_CNTL                                                                                0x0068
#define regDTBCLK_P_CNTL_BASE_IDX                                                                       1
#define regDCCG_GATE_DISABLE_CNTL5                                                                      0x0069
#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX                                                             1
#define regDSCCLK0_DTO_PARAM                                                                            0x006c
#define regDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
#define regDSCCLK1_DTO_PARAM                                                                            0x006d
#define regDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
#define regDSCCLK2_DTO_PARAM                                                                            0x006e
#define regDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
#define regOTG_PIXEL_RATE_DIV                                                                           0x006f
#define regOTG_PIXEL_RATE_DIV_BASE_IDX                                                                  1
#define regMILLISECOND_TIME_BASE_DIV                                                                    0x0070
#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
#define regDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
#define regDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
#define regDCCG_PERFMON_CNTL                                                                            0x0073
#define regDCCG_PERFMON_CNTL_BASE_IDX                                                                   1
#define regDCCG_GATE_DISABLE_CNTL                                                                       0x0074
#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
#define regDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
#define regSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
#define regDCCG_CAC_STATUS                                                                              0x0077
#define regDCCG_CAC_STATUS_BASE_IDX                                                                     1
#define regMICROSECOND_TIME_BASE_DIV                                                                    0x007b
#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
#define regDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
#define regSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
#define regDCCG_DISP_CNTL_REG                                                                           0x007f
#define regDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
#define regOTG0_PIXEL_RATE_CNTL                                                                         0x0080
#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
#define regDP_DTO0_PHASE                                                                                0x0081
#define regDP_DTO0_PHASE_BASE_IDX                                                                       1
#define regDP_DTO0_MODULO                                                                               0x0082
#define regDP_DTO0_MODULO_BASE_IDX                                                                      1
#define regOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
#define regOTG1_PIXEL_RATE_CNTL                                                                         0x0084
#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
#define regDP_DTO1_PHASE                                                                                0x0085
#define regDP_DTO1_PHASE_BASE_IDX                                                                       1
#define regDP_DTO1_MODULO                                                                               0x0086
#define regDP_DTO1_MODULO_BASE_IDX                                                                      1
#define regOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
#define regOTG2_PIXEL_RATE_CNTL                                                                         0x0088
#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
#define regDP_DTO2_PHASE                                                                                0x0089
#define regDP_DTO2_PHASE_BASE_IDX                                                                       1
#define regDP_DTO2_MODULO                                                                               0x008a
#define regDP_DTO2_MODULO_BASE_IDX                                                                      1
#define regOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
#define regOTG3_PIXEL_RATE_CNTL                                                                         0x008c
#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
#define regDP_DTO3_PHASE                                                                                0x008d
#define regDP_DTO3_PHASE_BASE_IDX                                                                       1
#define regDP_DTO3_MODULO                                                                               0x008e
#define regDP_DTO3_MODULO_BASE_IDX                                                                      1
#define regOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
#define regDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
#define regDPPCLK0_DTO_PARAM                                                                            0x0099
#define regDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
#define regDPPCLK1_DTO_PARAM                                                                            0x009a
#define regDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
#define regDPPCLK2_DTO_PARAM                                                                            0x009b
#define regDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
#define regDPPCLK3_DTO_PARAM                                                                            0x009c
#define regDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
#define regDCCG_CAC_STATUS2                                                                             0x009f
#define regDCCG_CAC_STATUS2_BASE_IDX                                                                    1
#define regSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
#define regSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
#define regSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
#define regSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
#define regSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
#define regDCCG_SOFT_RESET                                                                              0x00a6
#define regDCCG_SOFT_RESET_BASE_IDX                                                                     1
#define regDSCCLK_DTO_CTRL                                                                              0x00a7
#define regDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
#define regDPPCLK_CTRL                                                                                  0x00a8
#define regDPPCLK_CTRL_BASE_IDX                                                                         1
#define regDCCG_GATE_DISABLE_CNTL6                                                                      0x00a9
#define regDCCG_GATE_DISABLE_CNTL6_BASE_IDX                                                             1
#define regSYMCLK_PSP_CNTL                                                                              0x00aa
#define regSYMCLK_PSP_CNTL_BASE_IDX                                                                     1
#define regDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
#define regDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
#define regDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
#define regDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
#define regDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
#define regDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
#define regDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
#define regDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
#define regDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
#define regDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
#define regDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
#define regDPPCLK_DTO_CTRL                                                                              0x00b6
#define regDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
#define regDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
#define regDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
#define regFORCE_SYMCLK_DISABLE                                                                         0x00ba
#define regFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
#define regDTBCLK_DTO0_PHASE                                                                            0x0018
#define regDTBCLK_DTO0_PHASE_BASE_IDX                                                                   2
#define regDTBCLK_DTO1_PHASE                                                                            0x0019
#define regDTBCLK_DTO1_PHASE_BASE_IDX                                                                   2
#define regDTBCLK_DTO2_PHASE                                                                            0x001a
#define regDTBCLK_DTO2_PHASE_BASE_IDX                                                                   2
#define regDTBCLK_DTO3_PHASE                                                                            0x001b
#define regDTBCLK_DTO3_PHASE_BASE_IDX                                                                   2
#define regDTBCLK_DTO0_MODULO                                                                           0x001f
#define regDTBCLK_DTO0_MODULO_BASE_IDX                                                                  2
#define regDTBCLK_DTO1_MODULO                                                                           0x0020
#define regDTBCLK_DTO1_MODULO_BASE_IDX                                                                  2
#define regDTBCLK_DTO2_MODULO                                                                           0x0021
#define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2
#define regDTBCLK_DTO3_MODULO                                                                           0x0022
#define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2
#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a
#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2
#define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052
#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
#define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053
#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
#define regPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054
#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
#define regPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055
#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
#define regPHYESYMCLK_CLOCK_CNTL                                                                        0x0056
#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
#define regHDMISTREAMCLK_CNTL                                                                           0x0059
#define regHDMISTREAMCLK_CNTL_BASE_IDX                                                                  2
#define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a
#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2
#define regHDMISTREAMCLK0_DTO_PARAM                                                                     0x005b
#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX                                                            2
#define regDCCG_AUDIO_DTBCLK_DTO_PHASE                                                                  0x0061
#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX                                                         2
#define regDCCG_AUDIO_DTBCLK_DTO_MODULO                                                                 0x0062
#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX                                                        2
#define regDTBCLK_DTO_DBUF_EN                                                                           0x0063
#define regDTBCLK_DTO_DBUF_EN_BASE_IDX                                                                  2

// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
// base address: 0x0
#define regDENTIST_DISPCLK_CNTL                                                                         0x0064
#define regDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1


// addressBlock: azroot_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f


// addressBlock: azendpoint_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e


// addressBlock: azinputendpoint_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c


// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
// base address: 0x0
#define regDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0000
#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2
#define regDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0001
#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
#define regDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0002
#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2
#define regDC_PERFMON0_PERFMON_CNTL                                                                     0x0003
#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2
#define regDC_PERFMON0_PERFMON_CNTL2                                                                    0x0004
#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2
#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0005
#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
#define regDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0006
#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
#define regDC_PERFMON0_PERFMON_HI                                                                       0x0007
#define regDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2
#define regDC_PERFMON0_PERFMON_LOW                                                                      0x0008
#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2


// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
// base address: 0x30
#define regDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x000c
#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2
#define regDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x000d
#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
#define regDC_PERFMON1_PERFCOUNTER_STATE                                                                0x000e
#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2
#define regDC_PERFMON1_PERFMON_CNTL                                                                     0x000f
#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2
#define regDC_PERFMON1_PERFMON_CNTL2                                                                    0x0010
#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2
#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x0011
#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
#define regDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x0012
#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
#define regDC_PERFMON1_PERFMON_HI                                                                       0x0013
#define regDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2
#define regDC_PERFMON1_PERFMON_LOW                                                                      0x0014
#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2


// addressBlock: dce_dc_dmu_dc_pg_dispdec
// base address: 0x0
#define regDOMAIN0_PG_CONFIG                                                                            0x0080
#define regDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
#define regDOMAIN0_PG_STATUS                                                                            0x0081
#define regDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
#define regDOMAIN1_PG_CONFIG                                                                            0x0082
#define regDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
#define regDOMAIN1_PG_STATUS                                                                            0x0083
#define regDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
#define regDOMAIN2_PG_CONFIG                                                                            0x0084
#define regDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
#define regDOMAIN2_PG_STATUS                                                                            0x0085
#define regDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
#define regDOMAIN3_PG_CONFIG                                                                            0x0086
#define regDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
#define regDOMAIN3_PG_STATUS                                                                            0x0087
#define regDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
#define regDOMAIN16_PG_CONFIG                                                                           0x0089
#define regDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
#define regDOMAIN16_PG_STATUS                                                                           0x008a
#define regDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
#define regDOMAIN17_PG_CONFIG                                                                           0x008b
#define regDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
#define regDOMAIN17_PG_STATUS                                                                           0x008c
#define regDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
#define regDOMAIN18_PG_CONFIG                                                                           0x008d
#define regDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
#define regDOMAIN18_PG_STATUS                                                                           0x008e
#define regDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
#define regDOMAIN19_PG_CONFIG                                                                           0x008f
#define regDOMAIN19_PG_CONFIG_BASE_IDX                                                                  2
#define regDOMAIN19_PG_STATUS                                                                           0x0090
#define regDOMAIN19_PG_STATUS_BASE_IDX                                                                  2
#define regDOMAIN22_PG_CONFIG                                                                           0x0092
#define regDOMAIN22_PG_CONFIG_BASE_IDX                                                                  2
#define regDOMAIN22_PG_STATUS                                                                           0x0093
#define regDOMAIN22_PG_STATUS_BASE_IDX                                                                  2
#define regDOMAIN23_PG_CONFIG                                                                           0x0094
#define regDOMAIN23_PG_CONFIG_BASE_IDX                                                                  2
#define regDOMAIN23_PG_STATUS                                                                           0x0095
#define regDOMAIN23_PG_STATUS_BASE_IDX                                                                  2
#define regDOMAIN24_PG_CONFIG                                                                           0x0096
#define regDOMAIN24_PG_CONFIG_BASE_IDX                                                                  2
#define regDOMAIN24_PG_STATUS                                                                           0x0097
#define regDOMAIN24_PG_STATUS_BASE_IDX                                                                  2
#define regDOMAIN25_PG_CONFIG                                                                           0x0098
#define regDOMAIN25_PG_CONFIG_BASE_IDX                                                                  2
#define regDOMAIN25_PG_STATUS                                                                           0x0099
#define regDOMAIN25_PG_STATUS_BASE_IDX                                                                  2
#define regDCPG_INTERRUPT_STATUS                                                                        0x009a
#define regDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
#define regDCPG_INTERRUPT_STATUS_2                                                                      0x009b
#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
#define regDCPG_INTERRUPT_STATUS_3                                                                      0x009c
#define regDCPG_INTERRUPT_STATUS_3_BASE_IDX                                                             2
#define regDCPG_INTERRUPT_CONTROL_1                                                                     0x009d
#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
#define regDCPG_INTERRUPT_CONTROL_2                                                                     0x009e
#define regDCPG_INTERRUPT_CONTROL_2_BASE_IDX                                                            2
#define regDCPG_INTERRUPT_CONTROL_3                                                                     0x009f
#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
#define regDC_IP_REQUEST_CNTL                                                                           0x00a0
#define regDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
#define regLONO_MEM_PWR_REQ_CNTL                                                                        0x00a4
#define regLONO_MEM_PWR_REQ_CNTL_BASE_IDX                                                               2


// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
// base address: 0x2f8
#define regDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x00be
#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2
#define regDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x00bf
#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
#define regDC_PERFMON2_PERFCOUNTER_STATE                                                                0x00c0
#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2
#define regDC_PERFMON2_PERFMON_CNTL                                                                     0x00c1
#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2
#define regDC_PERFMON2_PERFMON_CNTL2                                                                    0x00c2
#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2
#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x00c3
#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
#define regDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x00c4
#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
#define regDC_PERFMON2_PERFMON_HI                                                                       0x00c5
#define regDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2
#define regDC_PERFMON2_PERFMON_LOW                                                                      0x00c6
#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2


// addressBlock: dce_dc_dmu_dmu_misc_dispdec
// base address: 0x0
#define regCC_DC_PIPE_DIS                                                                               0x00ca
#define regCC_DC_PIPE_DIS_BASE_IDX                                                                      2
#define regDMU_CLK_CNTL                                                                                 0x00cb
#define regDMU_CLK_CNTL_BASE_IDX                                                                        2
#define regDMCUB_SMU_INTERRUPT_CNTL                                                                     0x00cd
#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX                                                            2
#define regSMU_INTERRUPT_CONTROL                                                                        0x00ce
#define regSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
#define regZSC_CNTL                                                                                     0x00cf
#define regZSC_CNTL_BASE_IDX                                                                            2
#define regZSC_CNTL2                                                                                    0x00d0
#define regZSC_CNTL2_BASE_IDX                                                                           2
#define regDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
#define regZSC_STATUS                                                                                   0x00d7
#define regZSC_STATUS_BASE_IDX                                                                          2
#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG                                                                0x00d8
#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                       2
#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG                                                                 0x00d9
#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                        2
#define regZPR_CLK_UNGATE_DELAY                                                                         0x00da
#define regZPR_CLK_UNGATE_DELAY_BASE_IDX                                                                2



// addressBlock: dce_dc_dmu_ihc_dispdec
// base address: 0x0
#define regDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
#define regDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
#define regDC_GPU_TIMER_READ                                                                            0x0128
#define regDC_GPU_TIMER_READ_BASE_IDX                                                                   2
#define regDC_GPU_TIMER_READ_CNTL                                                                       0x0129
#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
#define regDISP_INTERRUPT_STATUS                                                                        0x012a
#define regDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
#define regDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
#define regDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
#define regDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
#define regDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
#define regDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147
#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2
#define regDCCG_INTERRUPT_DEST                                                                          0x0148
#define regDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regDMU_INTERRUPT_DEST                                                                           0x0149
#define regDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regDMU_INTERRUPT_DEST2                                                                          0x014a
#define regDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2
#define regDCPG_INTERRUPT_DEST                                                                          0x014b
#define regDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regDCPG_INTERRUPT_DEST2                                                                         0x014c
#define regDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
#define regMMHUBBUB_INTERRUPT_DEST                                                                      0x014d
#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
#define regWB_INTERRUPT_DEST                                                                            0x014e
#define regWB_INTERRUPT_DEST_BASE_IDX                                                                   2
#define regDCHUB_INTERRUPT_DEST                                                                         0x014f
#define regDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150
#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
#define regDCHUB_INTERRUPT_DEST2                                                                        0x0151
#define regDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
#define regDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152
#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
#define regMPC_INTERRUPT_DEST                                                                           0x0153
#define regMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regOPP_INTERRUPT_DEST                                                                           0x0154
#define regOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regOPTC_INTERRUPT_DEST                                                                          0x0155
#define regOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regOTG0_INTERRUPT_DEST                                                                          0x0156
#define regOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regOTG1_INTERRUPT_DEST                                                                          0x0157
#define regOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regOTG2_INTERRUPT_DEST                                                                          0x0158
#define regOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regOTG3_INTERRUPT_DEST                                                                          0x0159
#define regOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regOTG4_INTERRUPT_DEST                                                                          0x015a
#define regOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regOTG5_INTERRUPT_DEST                                                                          0x015b
#define regOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regDIG_INTERRUPT_DEST                                                                           0x015c
#define regDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d
#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
#define regDIO_INTERRUPT_DEST                                                                           0x015f
#define regDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regDCIO_INTERRUPT_DEST                                                                          0x0160
#define regDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regHPD_INTERRUPT_DEST                                                                           0x0161
#define regHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regAZ_INTERRUPT_DEST                                                                            0x0162
#define regAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
#define regAUX_INTERRUPT_DEST                                                                           0x0163
#define regAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regDSC_INTERRUPT_DEST                                                                           0x0164
#define regDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regHPO_INTERRUPT_DEST                                                                           0x0165
#define regHPO_INTERRUPT_DEST_BASE_IDX                                                                  2


// addressBlock: dce_dc_dmu_fgsec_dispdec
// base address: 0x0
#define regDMCUB_RBBMIF_SEC_CNTL                                                                        0x017a
#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX                                                               2


// addressBlock: dce_dc_dmu_rbbmif_dispdec
// base address: 0x0
#define regRBBMIF_TIMEOUT                                                                               0x017f
#define regRBBMIF_TIMEOUT_BASE_IDX                                                                      2
#define regRBBMIF_STATUS                                                                                0x0180
#define regRBBMIF_STATUS_BASE_IDX                                                                       2
#define regRBBMIF_STATUS_2                                                                              0x0181
#define regRBBMIF_STATUS_2_BASE_IDX                                                                     2
#define regRBBMIF_INT_STATUS                                                                            0x0182
#define regRBBMIF_INT_STATUS_BASE_IDX                                                                   2
#define regRBBMIF_TIMEOUT_DIS                                                                           0x0183
#define regRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
#define regRBBMIF_TIMEOUT_DIS_2                                                                         0x0184
#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
#define regRBBMIF_STATUS_FLAG                                                                           0x0185
#define regRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2


// addressBlock: dce_dc_dmu_dmcub_dispdec
// base address: 0x0
#define regDMCUB_REGION0_OFFSET                                                                         0x018e
#define regDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f
#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION1_OFFSET                                                                         0x0190
#define regDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191
#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION2_OFFSET                                                                         0x0192
#define regDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193
#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION4_OFFSET                                                                         0x0196
#define regDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197
#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION5_OFFSET                                                                         0x0198
#define regDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199
#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION6_OFFSET                                                                         0x019a
#define regDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b
#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION7_OFFSET                                                                         0x019c
#define regDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d
#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e
#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f
#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0
#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1
#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2
#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3
#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4
#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5
#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6
#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7
#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8
#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9
#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa
#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab
#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac
#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad
#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae
#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af
#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0
#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1
#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2
#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3
#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4
#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5
#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6
#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7
#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8
#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9
#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba
#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb
#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc
#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd
#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be
#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf
#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0
#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1
#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2
#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3
#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4
#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_INTERRUPT_ENABLE                                                                       0x01c5
#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
#define regDMCUB_INTERRUPT_ACK                                                                          0x01c6
#define regDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
#define regDMCUB_INTERRUPT_STATUS                                                                       0x01c7
#define regDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
#define regDMCUB_INTERRUPT_TYPE                                                                         0x01c8
#define regDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
#define regDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9
#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
#define regDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca
#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
#define regDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb
#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
#define regDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc
#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
#define regDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd
#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
#define regDMCUB_SEC_CNTL                                                                               0x01ce
#define regDMCUB_SEC_CNTL_BASE_IDX                                                                      2
#define regDMCUB_MEM_CNTL                                                                               0x01cf
#define regDMCUB_MEM_CNTL_BASE_IDX                                                                      2
#define regDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0
#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_INBOX0_SIZE                                                                            0x01d1
#define regDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
#define regDMCUB_INBOX0_WPTR                                                                            0x01d2
#define regDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
#define regDMCUB_INBOX0_RPTR                                                                            0x01d3
#define regDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
#define regDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4
#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_INBOX1_SIZE                                                                            0x01d5
#define regDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
#define regDMCUB_INBOX1_WPTR                                                                            0x01d6
#define regDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
#define regDMCUB_INBOX1_RPTR                                                                            0x01d7
#define regDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
#define regDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8
#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
#define regDMCUB_OUTBOX0_SIZE                                                                           0x01d9
#define regDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
#define regDMCUB_OUTBOX0_WPTR                                                                           0x01da
#define regDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
#define regDMCUB_OUTBOX0_RPTR                                                                           0x01db
#define regDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
#define regDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc
#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
#define regDMCUB_OUTBOX1_SIZE                                                                           0x01dd
#define regDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
#define regDMCUB_OUTBOX1_WPTR                                                                           0x01de
#define regDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
#define regDMCUB_OUTBOX1_RPTR                                                                           0x01df
#define regDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
#define regDMCUB_TIMER_TRIGGER0                                                                         0x01e0
#define regDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
#define regDMCUB_TIMER_TRIGGER1                                                                         0x01e1
#define regDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
#define regDMCUB_TIMER_WINDOW                                                                           0x01e2
#define regDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
#define regDMCUB_SCRATCH0                                                                               0x01e3
#define regDMCUB_SCRATCH0_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH1                                                                               0x01e4
#define regDMCUB_SCRATCH1_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH2                                                                               0x01e5
#define regDMCUB_SCRATCH2_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH3                                                                               0x01e6
#define regDMCUB_SCRATCH3_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH4                                                                               0x01e7
#define regDMCUB_SCRATCH4_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH5                                                                               0x01e8
#define regDMCUB_SCRATCH5_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH6                                                                               0x01e9
#define regDMCUB_SCRATCH6_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH7                                                                               0x01ea
#define regDMCUB_SCRATCH7_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH8                                                                               0x01eb
#define regDMCUB_SCRATCH8_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH9                                                                               0x01ec
#define regDMCUB_SCRATCH9_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH10                                                                              0x01ed
#define regDMCUB_SCRATCH10_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH11                                                                              0x01ee
#define regDMCUB_SCRATCH11_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH12                                                                              0x01ef
#define regDMCUB_SCRATCH12_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH13                                                                              0x01f0
#define regDMCUB_SCRATCH13_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH14                                                                              0x01f1
#define regDMCUB_SCRATCH14_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH15                                                                              0x01f2
#define regDMCUB_SCRATCH15_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH16                                                                              0x01f3
#define regDMCUB_SCRATCH16_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH17                                                                              0x01f4
#define regDMCUB_SCRATCH17_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH18                                                                              0x01f5
#define regDMCUB_SCRATCH18_BASE_IDX                                                                     2
#define regDMCUB_CNTL                                                                                   0x01f6
#define regDMCUB_CNTL_BASE_IDX                                                                          2
#define regDMCUB_GPINT_DATAIN0                                                                          0x01f7
#define regDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
#define regDMCUB_GPINT_DATAIN1                                                                          0x01f8
#define regDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
#define regDMCUB_GPINT_DATAOUT                                                                          0x01f9
#define regDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa
#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
#define regDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb
#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
#define regDMCUB_MEM_PWR_CNTL                                                                           0x01fc
#define regDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
#define regDMCUB_TIMER_CURRENT                                                                          0x01fd
#define regDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
#define regDMCUB_PROC_ID                                                                                0x01ff
#define regDMCUB_PROC_ID_BASE_IDX                                                                       2
#define regDMCUB_CNTL2                                                                                  0x0200
#define regDMCUB_CNTL2_BASE_IDX                                                                         2
#define regDMCUB_GPINT_DATAIN2                                                                          0x0215
#define regDMCUB_GPINT_DATAIN2_BASE_IDX                                                                 2
#define regDMCUB_GPINT_DATAIN3                                                                          0x0216
#define regDMCUB_GPINT_DATAIN3_BASE_IDX                                                                 2
#define regDMCUB_GPINT_DATAIN4                                                                          0x0217
#define regDMCUB_GPINT_DATAIN4_BASE_IDX                                                                 2
#define regDMCUB_GPINT_DATAIN5                                                                          0x0218
#define regDMCUB_GPINT_DATAIN5_BASE_IDX                                                                 2
#define regDMCUB_GPINT_DATAIN6                                                                          0x0219
#define regDMCUB_GPINT_DATAIN6_BASE_IDX                                                                 2
#define regDMCUB_REGION3_TMR_AXI_SPACE                                                                  0x021a
#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX                                                         2
#define regDMCUB_SCRATCH19                                                                              0x022e
#define regDMCUB_SCRATCH19_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH20                                                                              0x022f
#define regDMCUB_SCRATCH20_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH21                                                                              0x0230
#define regDMCUB_SCRATCH21_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH22                                                                              0x0231
#define regDMCUB_SCRATCH22_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH23                                                                              0x0232
#define regDMCUB_SCRATCH23_BASE_IDX                                                                     2


// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
// base address: 0x0
#define regMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272
#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2
#define regMCIF_WB_BUFMGR_STATUS                                                                        0x0274
#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2
#define regMCIF_WB_BUF_PITCH                                                                            0x0275
#define regMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2
#define regMCIF_WB_BUF_1_STATUS                                                                         0x0276
#define regMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2
#define regMCIF_WB_BUF_1_STATUS2                                                                        0x0277
#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2
#define regMCIF_WB_BUF_2_STATUS                                                                         0x0278
#define regMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2
#define regMCIF_WB_BUF_2_STATUS2                                                                        0x0279
#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2
#define regMCIF_WB_BUF_3_STATUS                                                                         0x027a
#define regMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2
#define regMCIF_WB_BUF_3_STATUS2                                                                        0x027b
#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2
#define regMCIF_WB_BUF_4_STATUS                                                                         0x027c
#define regMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2
#define regMCIF_WB_BUF_4_STATUS2                                                                        0x027d
#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2
#define regMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e
#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2
#define regMCIF_WB_SCLK_CHANGE                                                                          0x027f
#define regMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2
#define regMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282
#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2
#define regMCIF_WB_BUF_1_ADDR_C                                                                         0x0284
#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2
#define regMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286
#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2
#define regMCIF_WB_BUF_2_ADDR_C                                                                         0x0288
#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2
#define regMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a
#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2
#define regMCIF_WB_BUF_3_ADDR_C                                                                         0x028c
#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2
#define regMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e
#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2
#define regMCIF_WB_BUF_4_ADDR_C                                                                         0x0290
#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2
#define regMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292
#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2
#define regMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293
#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2
#define regMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294
#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2
#define regMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296
#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2
#define regMULTI_LEVEL_QOS_CTRL                                                                         0x0297
#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2
#define regMCIF_WB_SECURITY_LEVEL                                                                       0x0298
#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX                                                              2
#define regMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299
#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2
#define regMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a
#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2
#define regMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b
#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c
#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d
#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e
#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f
#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0
#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1
#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2
#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3
#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2
#define regMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4
#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2
#define regMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5
#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2
#define regMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6
#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2
#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI                                                           0x02a7
#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX                                                  2
#define regMCIF_WB_VMID_CONTROL                                                                         0x02a8
#define regMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2
#define regMCIF_WB_MIN_TTO                                                                              0x02a9
#define regMCIF_WB_MIN_TTO_BASE_IDX                                                                     2


// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
// base address: 0x0
#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa
#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2
#define regMCIF_WB_WATERMARK                                                                            0x02ab
#define regMCIF_WB_WATERMARK_BASE_IDX                                                                   2
#define regMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac
#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2
#define regMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad
#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2
#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae
#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2
#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af
#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2
#define regMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0
#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2
#define regMMHUBBUB_MIN_TTO                                                                             0x02b1
#define regMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2
#define regMMHUBBUB_CTRL                                                                                0x0333
#define regMMHUBBUB_CTRL_BASE_IDX                                                                       2
#define regWBIF_SMU_WM_CONTROL                                                                          0x0334
#define regWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2
#define regWBIF0_MISC_CTRL                                                                              0x0335
#define regWBIF0_MISC_CTRL_BASE_IDX                                                                     2
#define regWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0336
#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
#define regWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0337
#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
#define regMMHUBBUB_MEM_PWR_STATUS                                                                      0x033e
#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
#define regMMHUBBUB_MEM_PWR_CNTL                                                                        0x033f
#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
#define regMMHUBBUB_CLOCK_CNTL                                                                          0x0340
#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
#define regMMHUBBUB_SOFT_RESET                                                                          0x0341
#define regMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
#define regDMU_IF_ERR_STATUS                                                                            0x0345
#define regDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
#define regMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0346
#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
#define regMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0348
#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2


// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
// base address: 0xd48
#define regDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x0352
#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2
#define regDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x0353
#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
#define regDC_PERFMON4_PERFCOUNTER_STATE                                                                0x0354
#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2
#define regDC_PERFMON4_PERFMON_CNTL                                                                     0x0355
#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2
#define regDC_PERFMON4_PERFMON_CNTL2                                                                    0x0356
#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2
#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x0357
#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
#define regDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0358
#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
#define regDC_PERFMON4_PERFMON_HI                                                                       0x0359
#define regDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2
#define regDC_PERFMON4_PERFMON_LOW                                                                      0x035a
#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2




// addressBlock: dce_dc_hda_azf0stream0_dispdec
// base address: 0x0
#define regAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dce_dc_hda_azf0stream1_dispdec
// base address: 0x8
#define regAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dce_dc_hda_azf0stream2_dispdec
// base address: 0x10
#define regAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dce_dc_hda_azf0stream3_dispdec
// base address: 0x18
#define regAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dce_dc_hda_azf0stream4_dispdec
// base address: 0x20
#define regAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dce_dc_hda_azf0stream5_dispdec
// base address: 0x28
#define regAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dce_dc_hda_azf0stream6_dispdec
// base address: 0x30
#define regAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dce_dc_hda_azf0stream7_dispdec
// base address: 0x38
#define regAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dce_dc_hda_az_misc_dispdec
// base address: 0x0
#define regAZ_CLOCK_CNTL                                                                                0x0372
#define regAZ_CLOCK_CNTL_BASE_IDX                                                                       2
#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0373
#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          2

// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
// base address: 0xde8
#define regDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x037a
#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2
#define regDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x037b
#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
#define regDC_PERFMON5_PERFCOUNTER_STATE                                                                0x037c
#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2
#define regDC_PERFMON5_PERFMON_CNTL                                                                     0x037d
#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2
#define regDC_PERFMON5_PERFMON_CNTL2                                                                    0x037e
#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2
#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x037f
#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
#define regDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x0380
#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
#define regDC_PERFMON5_PERFMON_HI                                                                       0x0381
#define regDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2
#define regDC_PERFMON5_PERFMON_LOW                                                                      0x0382
#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2



// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
// base address: 0x0
#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
// base address: 0x18
#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
// base address: 0x30
#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
// base address: 0x48
#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
// base address: 0x60
#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
// base address: 0x78
#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
// base address: 0x90
#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
// base address: 0xa8
#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dce_dc_hda_azf0controller_dispdec
// base address: 0x0
#define regAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
#define regAZALIA_AUDIO_DTO                                                                             0x03c3
#define regAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
#define regAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
#define regAZALIA_SOCCLK_CONTROL                                                                        0x03c5
#define regAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
#define regAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
#define regAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
#define regAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
#define regAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
#define regAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
#define regAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
#define regAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
#define regAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
#define regAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
#define regAZALIA_CRC0_CONTROL0                                                                         0x03e3
#define regAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
#define regAZALIA_CRC0_CONTROL1                                                                         0x03e4
#define regAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
#define regAZALIA_CRC0_CONTROL2                                                                         0x03e5
#define regAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
#define regAZALIA_CRC0_CONTROL3                                                                         0x03e6
#define regAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
#define regAZALIA_CRC0_RESULT                                                                           0x03e7
#define regAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
#define regAZALIA_CRC1_CONTROL0                                                                         0x03e8
#define regAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
#define regAZALIA_CRC1_CONTROL1                                                                         0x03e9
#define regAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
#define regAZALIA_CRC1_CONTROL2                                                                         0x03ea
#define regAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
#define regAZALIA_CRC1_CONTROL3                                                                         0x03eb
#define regAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
#define regAZALIA_CRC1_RESULT                                                                           0x03ec
#define regAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
#define regAZALIA_MEM_PWR_CTRL                                                                          0x03ee
#define regAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
#define regAZALIA_MEM_PWR_STATUS                                                                        0x03ef
#define regAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2



// addressBlock: dce_dc_hda_azf0root_dispdec
// base address: 0x0
#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
#define regAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
#define regAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
#define regAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
#define regAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
#define regAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
#define regAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
#define regAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
#define regREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2



// addressBlock: dce_dc_hda_azf0stream8_dispdec
// base address: 0x320
#define regAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dce_dc_hda_azf0stream9_dispdec
// base address: 0x328
#define regAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dce_dc_hda_azf0stream10_dispdec
// base address: 0x330
#define regAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
#define regAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2


// addressBlock: dce_dc_hda_azf0stream11_dispdec
// base address: 0x338
#define regAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
#define regAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2


// addressBlock: dce_dc_hda_azf0stream12_dispdec
// base address: 0x340
#define regAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
#define regAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2


// addressBlock: dce_dc_hda_azf0stream13_dispdec
// base address: 0x348
#define regAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
#define regAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2


// addressBlock: dce_dc_hda_azf0stream14_dispdec
// base address: 0x350
#define regAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
#define regAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2


// addressBlock: dce_dc_hda_azf0stream15_dispdec
// base address: 0x358
#define regAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
#define regAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2



// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
// base address: 0x0
#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
// base address: 0x10
#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
// base address: 0x20
#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
// base address: 0x30
#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
// base address: 0x40
#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
// base address: 0x50
#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
// base address: 0x60
#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
// base address: 0x70
#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2



// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec
// base address: 0x0
#define regDCHUBBUB_SDPIF_CFG0                                                                          0x046f
#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
#define regDCHUBBUB_SDPIF_CFG1                                                                          0x0470
#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
#define regDCHUBBUB_SDPIF_CFG2                                                                          0x0471
#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
#define regVM_REQUEST_PHYSICAL                                                                          0x0472
#define regVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
#define regDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0473
#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
#define regDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0474
#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
#define regDCN_VM_FB_LOCATION_BASE                                                                      0x0475
#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
#define regDCN_VM_FB_LOCATION_TOP                                                                       0x0476
#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
#define regDCN_VM_FB_OFFSET                                                                             0x0477
#define regDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
#define regDCN_VM_AGP_BOT                                                                               0x0478
#define regDCN_VM_AGP_BOT_BASE_IDX                                                                      2
#define regDCN_VM_AGP_TOP                                                                               0x0479
#define regDCN_VM_AGP_TOP_BASE_IDX                                                                      2
#define regDCN_VM_AGP_BASE                                                                              0x047a
#define regDCN_VM_AGP_BASE_BASE_IDX                                                                     2
#define regDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x047b
#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
#define regDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x047c
#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x047d
#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL                                                                  0x047e
#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX                                                         2
#define regDCHUBBUB_SDPIF_PIPE_NOALLOC                                                                  0x047f
#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX                                                         2
#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL                                                           0x0480
#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX                                                  2
#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL                                                          0x0481
#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX                                                 2
#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL                                                          0x0482
#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX                                                 2
#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL                                                            0x0483
#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX                                                   2
#define regSDPIF_REQUEST_RATE_LIMIT                                                                     0x0484
#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX                                                            2
#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x0485
#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x0486
#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2


// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec
// base address: 0x0
#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04af
#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04b0
#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
#define regDCHUBBUB_CRC_CTRL                                                                            0x04b1
#define regDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
#define regDCHUBBUB_CRC0_VAL_R_G                                                                        0x04b2
#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
#define regDCHUBBUB_CRC0_VAL_B_A                                                                        0x04b3
#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
#define regDCHUBBUB_CRC1_VAL_R_G                                                                        0x04b4
#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
#define regDCHUBBUB_CRC1_VAL_B_A                                                                        0x04b5
#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
#define regDCHUBBUB_DCC_STAT_CNTL                                                                       0x04b6
#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX                                                              2
#define regDCHUBBUB_DCC_STAT0                                                                           0x04b7
#define regDCHUBBUB_DCC_STAT0_BASE_IDX                                                                  2
#define regDCHUBBUB_DCC_STAT1                                                                           0x04b8
#define regDCHUBBUB_DCC_STAT1_BASE_IDX                                                                  2
#define regDCHUBBUB_DCC_STAT2                                                                           0x04b9
#define regDCHUBBUB_DCC_STAT2_BASE_IDX                                                                  2
#define regDCHUBBUB_COMPBUF_CTRL                                                                        0x04ba
#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX                                                               2
#define regDCHUBBUB_DET0_CTRL                                                                           0x04bb
#define regDCHUBBUB_DET0_CTRL_BASE_IDX                                                                  2
#define regDCHUBBUB_DET1_CTRL                                                                           0x04bc
#define regDCHUBBUB_DET1_CTRL_BASE_IDX                                                                  2
#define regDCHUBBUB_DET2_CTRL                                                                           0x04bd
#define regDCHUBBUB_DET2_CTRL_BASE_IDX                                                                  2
#define regDCHUBBUB_DET3_CTRL                                                                           0x04be
#define regDCHUBBUB_DET3_CTRL_BASE_IDX                                                                  2
#define regDCHUBBUB_MEM_PWR_MODE_CTRL                                                                   0x04c0
#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX                                                          2
#define regCOMPBUF_MEM_PWR_CTRL_1                                                                       0x04c1
#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX                                                              2
#define regCOMPBUF_MEM_PWR_CTRL_2                                                                       0x04c2
#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX                                                              2
#define regDCHUBBUB_MEM_PWR_STATUS                                                                      0x04c3
#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
#define regCOMPBUF_RESERVED_SPACE                                                                       0x04c4
#define regCOMPBUF_RESERVED_SPACE_BASE_IDX                                                              2
#define regDCHUBBUB_DEBUG_CTRL_0                                                                        0x04c5
#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                                               2


// addressBlock: dce_dc_dchubbubl_hubbub_dispdec
// base address: 0x0
#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x04f9
#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
#define regDCHUBBUB_ARB_SAT_LEVEL                                                                       0x04fa
#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
#define regDCHUBBUB_ARB_QOS_FORCE                                                                       0x04fb
#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
#define regDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x04fc
#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL                                                             0x04fd
#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX                                                    2
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x04fe
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A                                                      0x04ff
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX                                             2
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x0500
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x0501
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A                                                   0x0502
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX                                          2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x0503
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A                                                    0x0504
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX                                           2
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0505
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0506
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x0507
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0508
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x0509
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B                                                      0x050a
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX                                             2
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x050b
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x050c
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B                                                   0x050d
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX                                          2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x050e
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B                                                    0x050f
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX                                           2
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x0510
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x0511
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x0512
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x0513
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0514
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C                                                      0x0515
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX                                             2
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0516
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0517
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C                                                   0x0518
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX                                          2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0519
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C                                                    0x051a
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX                                           2
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x051b
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x051c
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x051d
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x051e
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x051f
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D                                                      0x0520
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX                                             2
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x0521
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x0522
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D                                                   0x0523
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX                                          2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x0524
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D                                                    0x0525
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX                                           2
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x0526
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x0527
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0528
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0529
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
#define regDCHUBBUB_ARB_HOSTVM_CNTL                                                                     0x052a
#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX                                                            2
#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x052b
#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
#define regDCHUBBUB_ARB_MALL_CNTL                                                                       0x052c
#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX                                                              2
#define regDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x052d
#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
#define regDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x052e
#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
#define regSURFACE_CHECK0_ADDRESS_LSB                                                                   0x052f
#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
#define regSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0530
#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
#define regSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0531
#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
#define regSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0532
#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
#define regSURFACE_CHECK2_ADDRESS_LSB                                                                   0x0533
#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
#define regSURFACE_CHECK2_ADDRESS_MSB                                                                   0x0534
#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
#define regSURFACE_CHECK3_ADDRESS_LSB                                                                   0x0535
#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
#define regSURFACE_CHECK3_ADDRESS_MSB                                                                   0x0536
#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
#define regVTG0_CONTROL                                                                                 0x0537
#define regVTG0_CONTROL_BASE_IDX                                                                        2
#define regVTG1_CONTROL                                                                                 0x0538
#define regVTG1_CONTROL_BASE_IDX                                                                        2
#define regVTG2_CONTROL                                                                                 0x0539
#define regVTG2_CONTROL_BASE_IDX                                                                        2
#define regVTG3_CONTROL                                                                                 0x053a
#define regVTG3_CONTROL_BASE_IDX                                                                        2
#define regDCHUBBUB_SOFT_RESET                                                                          0x053b
#define regDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
#define regDCHUBBUB_CLOCK_CNTL                                                                          0x053c
#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
#define regDCFCLK_CNTL                                                                                  0x053d
#define regDCFCLK_CNTL_BASE_IDX                                                                         2
#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x053e
#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x053f
#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
#define regDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0540
#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
#define regDCHUBBUB_CTRL_STATUS                                                                         0x0541
#define regDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x0547
#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x0548
#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x0549
#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
#define regFMON_CTRL                                                                                    0x054a
#define regFMON_CTRL_BASE_IDX                                                                           2
#define regDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x054b
#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2
#define regDCHUBBUB_TEST_DEBUG_DATA                                                                     0x054c
#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2

// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec
// base address: 0x1534
#define regDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x054d
#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2
#define regDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x054e
#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
#define regDC_PERFMON6_PERFCOUNTER_STATE                                                                0x054f
#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2
#define regDC_PERFMON6_PERFMON_CNTL                                                                     0x0550
#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2
#define regDC_PERFMON6_PERFMON_CNTL2                                                                    0x0551
#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2
#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x0552
#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
#define regDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x0553
#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
#define regDC_PERFMON6_PERFMON_HI                                                                       0x0554
#define regDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2
#define regDC_PERFMON6_PERFMON_LOW                                                                      0x0555
#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2


// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec
// base address: 0x0
#define regDCN_VM_CONTEXT0_CNTL                                                                         0x0559
#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT1_CNTL                                                                         0x0560
#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT2_CNTL                                                                         0x0567
#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT3_CNTL                                                                         0x056e
#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT4_CNTL                                                                         0x0575
#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT5_CNTL                                                                         0x057c
#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT6_CNTL                                                                         0x0583
#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT7_CNTL                                                                         0x058a
#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT8_CNTL                                                                         0x0591
#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT9_CNTL                                                                         0x0598
#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT10_CNTL                                                                        0x059f
#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
#define regDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
#define regDCN_VM_FAULT_CNTL                                                                            0x05cb
#define regDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
#define regDCN_VM_FAULT_STATUS                                                                          0x05cc
#define regDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
#define regDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
#define regDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2



// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
// base address: 0x0
#define regHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
#define regHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
#define regHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
#define regHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
#define regHUBP0_DCHUBP_CNTL                                                                            0x05f3
#define regHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
#define regHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
#define regHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
#define regHUBP0_DCHUBP_MALL_CONFIG                                                                     0x05f6
#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
#define regHUBP0_DCHUBP_MALL_SUB_VP                                                                     0x05f7
#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
#define regHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f8
#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
#define regHUBP0_HUBPREQ_DEBUG                                                                          0x05f9
#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fd
#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fe
#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
#define regHUBP0_HUBP_MALL_STATUS                                                                       0x05ff
#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX                                                              2


// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
// base address: 0x0
#define regHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
#define regHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
#define regHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
#define regHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
#define regHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x061f
#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
#define regHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0620
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0621
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0622
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0623
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0624
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0625
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0626
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0627
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
#define regHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0628
#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
#define regHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x0629
#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062a
#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062b
#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062c
#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062d
#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062e
#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x062f
#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0630
#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0631
#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0632
#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0633
#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0634
#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0635
#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0642
#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
#define regHUBPREQ0_BLANK_OFFSET_0                                                                      0x0643
#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
#define regHUBPREQ0_BLANK_OFFSET_1                                                                      0x0644
#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
#define regHUBPREQ0_DST_DIMENSIONS                                                                      0x0645
#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
#define regHUBPREQ0_DST_AFTER_SCALER                                                                    0x0646
#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
#define regHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0647
#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
#define regHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0648
#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
#define regHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x0649
#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
#define regHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064a
#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
#define regHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064b
#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
#define regHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064c
#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
#define regHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064d
#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
#define regHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064e
#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
#define regHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x064f
#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
#define regHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0650
#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
#define regHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0651
#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0652
#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0653
#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0654
#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0655
#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0656
#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0657
#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0658
#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
#define regHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x0659
#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
#define regHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065a
#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
#define regHUBPREQ0_CURSOR_SETTINGS                                                                     0x065b
#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065c
#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065d
#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065e
#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x065f
#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0662
#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
#define regHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0663
#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
#define regHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0664
#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
#define regHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0665
#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
#define regHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0666
#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
#define regHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0667
#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
#define regHUBPREQ0_UCLK_PSTATE_FORCE                                                                   0x0668
#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
#define regHUBPREQ0_HUBPREQ_STATUS_REG0                                                                 0x0669
#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
#define regHUBPREQ0_HUBPREQ_STATUS_REG1                                                                 0x066a
#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
#define regHUBPREQ0_HUBPREQ_STATUS_REG2                                                                 0x066b
#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2


// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
// base address: 0x0
#define regHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
#define regHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
#define regHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
#define regHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
#define regHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
#define regHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2


// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
// base address: 0x0
#define regCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
#define regCURSOR0_0_CURSOR_SIZE                                                                        0x067b
#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
#define regCURSOR0_0_CURSOR_POSITION                                                                    0x067c
#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
#define regCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
#define regCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
#define regCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
#define regCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
#define regCURSOR0_0_DMDATA_CNTL                                                                        0x0684
#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
#define regCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
#define regCURSOR0_0_DMDATA_STATUS                                                                      0x0686
#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
#define regCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
#define regCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2


// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x1a74
#define regDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x069d
#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2
#define regDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x069e
#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
#define regDC_PERFMON7_PERFCOUNTER_STATE                                                                0x069f
#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2
#define regDC_PERFMON7_PERFMON_CNTL                                                                     0x06a0
#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2
#define regDC_PERFMON7_PERFMON_CNTL2                                                                    0x06a1
#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2
#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x06a2
#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
#define regDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x06a3
#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
#define regDC_PERFMON7_PERFMON_HI                                                                       0x06a4
#define regDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2
#define regDC_PERFMON7_PERFMON_LOW                                                                      0x06a5
#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2


// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
// base address: 0x370
#define regHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
#define regHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
#define regHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
#define regHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
#define regHUBP1_DCHUBP_CNTL                                                                            0x06cf
#define regHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
#define regHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
#define regHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
#define regHUBP1_DCHUBP_MALL_CONFIG                                                                     0x06d2
#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
#define regHUBP1_DCHUBP_MALL_SUB_VP                                                                     0x06d3
#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
#define regHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d4
#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
#define regHUBP1_HUBPREQ_DEBUG                                                                          0x06d5
#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d9
#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06da
#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
#define regHUBP1_HUBP_MALL_STATUS                                                                       0x06db
#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX                                                              2


// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
// base address: 0x370
#define regHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
#define regHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
#define regHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
#define regHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
#define regHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fb
#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
#define regHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fc
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fd
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06fe
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x06ff
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0700
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0701
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0702
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0703
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
#define regHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0704
#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
#define regHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0705
#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0706
#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0707
#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0708
#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x0709
#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070a
#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070b
#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070c
#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070d
#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070e
#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x070f
#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0710
#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0711
#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071e
#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
#define regHUBPREQ1_BLANK_OFFSET_0                                                                      0x071f
#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
#define regHUBPREQ1_BLANK_OFFSET_1                                                                      0x0720
#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
#define regHUBPREQ1_DST_DIMENSIONS                                                                      0x0721
#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
#define regHUBPREQ1_DST_AFTER_SCALER                                                                    0x0722
#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
#define regHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0723
#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
#define regHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0724
#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
#define regHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0725
#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
#define regHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0726
#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
#define regHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0727
#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
#define regHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0728
#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
#define regHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x0729
#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
#define regHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072a
#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
#define regHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072b
#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
#define regHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072c
#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
#define regHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072d
#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072e
#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_2                                                                    0x072f
#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0730
#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0731
#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0732
#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0733
#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0734
#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
#define regHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0735
#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
#define regHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0736
#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
#define regHUBPREQ1_CURSOR_SETTINGS                                                                     0x0737
#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0738
#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x0739
#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073a
#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073b
#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073e
#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
#define regHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x073f
#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
#define regHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0740
#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
#define regHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0741
#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
#define regHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0742
#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
#define regHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0743
#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
#define regHUBPREQ1_UCLK_PSTATE_FORCE                                                                   0x0744
#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
#define regHUBPREQ1_HUBPREQ_STATUS_REG0                                                                 0x0745
#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
#define regHUBPREQ1_HUBPREQ_STATUS_REG1                                                                 0x0746
#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
#define regHUBPREQ1_HUBPREQ_STATUS_REG2                                                                 0x0747
#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2


// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
// base address: 0x370
#define regHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
#define regHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
#define regHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
#define regHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
#define regHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
#define regHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2


// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
// base address: 0x370
#define regCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
#define regCURSOR0_1_CURSOR_SIZE                                                                        0x0757
#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
#define regCURSOR0_1_CURSOR_POSITION                                                                    0x0758
#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
#define regCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
#define regCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
#define regCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
#define regCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
#define regCURSOR0_1_DMDATA_CNTL                                                                        0x0760
#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
#define regCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
#define regCURSOR0_1_DMDATA_STATUS                                                                      0x0762
#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
#define regCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
#define regCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2


// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x1de4
#define regDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x0779
#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2
#define regDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x077a
#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
#define regDC_PERFMON8_PERFCOUNTER_STATE                                                                0x077b
#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2
#define regDC_PERFMON8_PERFMON_CNTL                                                                     0x077c
#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2
#define regDC_PERFMON8_PERFMON_CNTL2                                                                    0x077d
#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2
#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x077e
#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
#define regDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x077f
#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
#define regDC_PERFMON8_PERFMON_HI                                                                       0x0780
#define regDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2
#define regDC_PERFMON8_PERFMON_LOW                                                                      0x0781
#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2


// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
// base address: 0x6e0
#define regHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
#define regHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
#define regHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
#define regHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
#define regHUBP2_DCHUBP_CNTL                                                                            0x07ab
#define regHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
#define regHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
#define regHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
#define regHUBP2_DCHUBP_MALL_CONFIG                                                                     0x07ae
#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
#define regHUBP2_DCHUBP_MALL_SUB_VP                                                                     0x07af
#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
#define regHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07b0
#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
#define regHUBP2_HUBPREQ_DEBUG                                                                          0x07b1
#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b5
#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b6
#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
#define regHUBP2_HUBP_MALL_STATUS                                                                       0x07b7
#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX                                                              2


// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
// base address: 0x6e0
#define regHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
#define regHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
#define regHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
#define regHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
#define regHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d7
#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d8
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07d9
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07da
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07db
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dc
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07dd
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07de
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07df
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
#define regHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e0
#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
#define regHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e1
#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e2
#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e3
#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e4
#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e5
#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e6
#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e7
#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e8
#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07e9
#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07ea
#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07eb
#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ec
#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ed
#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fa
#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
#define regHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fb
#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
#define regHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fc
#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
#define regHUBPREQ2_DST_DIMENSIONS                                                                      0x07fd
#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
#define regHUBPREQ2_DST_AFTER_SCALER                                                                    0x07fe
#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
#define regHUBPREQ2_PREFETCH_SETTINGS                                                                   0x07ff
#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
#define regHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0800
#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
#define regHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0801
#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
#define regHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0802
#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
#define regHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0803
#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
#define regHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0804
#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
#define regHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0805
#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
#define regHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0806
#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
#define regHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0807
#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
#define regHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0808
#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
#define regHUBPREQ2_NOM_PARAMETERS_0                                                                    0x0809
#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080a
#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080b
#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080c
#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080d
#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080e
#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_6                                                                    0x080f
#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0810
#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
#define regHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0811
#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
#define regHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0812
#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
#define regHUBPREQ2_CURSOR_SETTINGS                                                                     0x0813
#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0814
#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0815
#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0816
#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0817
#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081a
#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
#define regHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081b
#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
#define regHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081c
#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
#define regHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081d
#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
#define regHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081e
#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
#define regHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x081f
#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
#define regHUBPREQ2_UCLK_PSTATE_FORCE                                                                   0x0820
#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
#define regHUBPREQ2_HUBPREQ_STATUS_REG0                                                                 0x0821
#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
#define regHUBPREQ2_HUBPREQ_STATUS_REG1                                                                 0x0822
#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
#define regHUBPREQ2_HUBPREQ_STATUS_REG2                                                                 0x0823
#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2


// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
// base address: 0x6e0
#define regHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
#define regHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
#define regHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
#define regHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
#define regHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
#define regHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2


// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
// base address: 0x6e0
#define regCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
#define regCURSOR0_2_CURSOR_SIZE                                                                        0x0833
#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
#define regCURSOR0_2_CURSOR_POSITION                                                                    0x0834
#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
#define regCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
#define regCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
#define regCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
#define regCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
#define regCURSOR0_2_DMDATA_CNTL                                                                        0x083c
#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
#define regCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
#define regCURSOR0_2_DMDATA_STATUS                                                                      0x083e
#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
#define regCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
#define regCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2


// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x2154
#define regDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x0855
#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2
#define regDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x0856
#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
#define regDC_PERFMON9_PERFCOUNTER_STATE                                                                0x0857
#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2
#define regDC_PERFMON9_PERFMON_CNTL                                                                     0x0858
#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2
#define regDC_PERFMON9_PERFMON_CNTL2                                                                    0x0859
#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2
#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x085a
#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
#define regDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x085b
#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
#define regDC_PERFMON9_PERFMON_HI                                                                       0x085c
#define regDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2
#define regDC_PERFMON9_PERFMON_LOW                                                                      0x085d
#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2


// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
// base address: 0xa50
#define regHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
#define regHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
#define regHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
#define regHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
#define regHUBP3_DCHUBP_CNTL                                                                            0x0887
#define regHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
#define regHUBP3_HUBP_CLK_CNTL                                                                          0x0888
#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
#define regHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
#define regHUBP3_DCHUBP_MALL_CONFIG                                                                     0x088a
#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
#define regHUBP3_DCHUBP_MALL_SUB_VP                                                                     0x088b
#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
#define regHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088c
#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
#define regHUBP3_HUBPREQ_DEBUG                                                                          0x088d
#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x0891
#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0892
#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
#define regHUBP3_HUBP_MALL_STATUS                                                                       0x0893
#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX                                                              2


// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
// base address: 0xa50
#define regHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
#define regHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
#define regHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
#define regHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
#define regHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b3
#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
#define regHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b4
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b5
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b6
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b7
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b8
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08b9
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08ba
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bb
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
#define regHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bc
#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
#define regHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08bd
#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08be
#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08bf
#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c0
#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c1
#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c2
#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c3
#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c4
#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c5
#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c6
#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c7
#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c8
#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08c9
#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d6
#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
#define regHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d7
#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
#define regHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d8
#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
#define regHUBPREQ3_DST_DIMENSIONS                                                                      0x08d9
#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
#define regHUBPREQ3_DST_AFTER_SCALER                                                                    0x08da
#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
#define regHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08db
#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
#define regHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dc
#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
#define regHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08dd
#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
#define regHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08de
#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
#define regHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08df
#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
#define regHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e0
#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
#define regHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e1
#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
#define regHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e2
#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
#define regHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e3
#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
#define regHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e4
#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
#define regHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e5
#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e6
#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e7
#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e8
#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08e9
#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08ea
#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08eb
#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ec
#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
#define regHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ed
#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
#define regHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ee
#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
#define regHUBPREQ3_CURSOR_SETTINGS                                                                     0x08ef
#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f0
#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f1
#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f2
#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f3
#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f6
#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
#define regHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f7
#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
#define regHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f8
#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
#define regHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08f9
#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
#define regHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fa
#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
#define regHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fb
#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
#define regHUBPREQ3_UCLK_PSTATE_FORCE                                                                   0x08fc
#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
#define regHUBPREQ3_HUBPREQ_STATUS_REG0                                                                 0x08fd
#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
#define regHUBPREQ3_HUBPREQ_STATUS_REG1                                                                 0x08fe
#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
#define regHUBPREQ3_HUBPREQ_STATUS_REG2                                                                 0x08ff
#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2


// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
// base address: 0xa50
#define regHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
#define regHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
#define regHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
#define regHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
#define regHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
#define regHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2


// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
// base address: 0xa50
#define regCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
#define regCURSOR0_3_CURSOR_SIZE                                                                        0x090f
#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
#define regCURSOR0_3_CURSOR_POSITION                                                                    0x0910
#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
#define regCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
#define regCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
#define regCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
#define regCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
#define regCURSOR0_3_DMDATA_CNTL                                                                        0x0918
#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
#define regCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
#define regCURSOR0_3_DMDATA_STATUS                                                                      0x091a
#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
#define regCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
#define regCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2


// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x24c4
#define regDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x0931
#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2
#define regDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x0932
#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
#define regDC_PERFMON10_PERFCOUNTER_STATE                                                               0x0933
#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2
#define regDC_PERFMON10_PERFMON_CNTL                                                                    0x0934
#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2
#define regDC_PERFMON10_PERFMON_CNTL2                                                                   0x0935
#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2
#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x0936
#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
#define regDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x0937
#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
#define regDC_PERFMON10_PERFMON_HI                                                                      0x0938
#define regDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2
#define regDC_PERFMON10_PERFMON_LOW                                                                     0x0939
#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2


// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
// base address: 0x0
#define regDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
#define regDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
#define regDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
#define regDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
#define regDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
#define regDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
#define regDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2


// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
// base address: 0x0
#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
#define regCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
#define regCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
#define regCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
#define regCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
#define regCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
#define regCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
#define regCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
#define regCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
#define regCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
#define regCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
#define regCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
#define regCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
#define regCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
#define regCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde
#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2
#define regCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf
#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2
#define regCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0
#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2
#define regCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1
#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2
#define regCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2
#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2
#define regCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3
#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2
#define regCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4
#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2
#define regCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5
#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2
#define regCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6
#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
#define regCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7
#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
#define regCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8
#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
#define regCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9
#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
#define regCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea
#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
#define regCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb
#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
#define regCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec
#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2
#define regCNVC_CFG0_PRE_DEGAM                                                                          0x0ced
#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2
#define regCNVC_CFG0_PRE_REALPHA                                                                        0x0cee
#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2


// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
// base address: 0x0
#define regCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1
#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
#define regCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2
#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
#define regCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3
#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4
#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2


// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
// base address: 0x0
#define regDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9
#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
#define regDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa
#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
#define regDSCL0_SCL_MODE                                                                               0x0cfb
#define regDSCL0_SCL_MODE_BASE_IDX                                                                      2
#define regDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc
#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
#define regDSCL0_DSCL_CONTROL                                                                           0x0cfd
#define regDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
#define regDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe
#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff
#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00
#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01
#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02
#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03
#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04
#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05
#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06
#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07
#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08
#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09
#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
#define regDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a
#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2
#define regDSCL0_DSCL_UPDATE                                                                            0x0d0b
#define regDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
#define regDSCL0_DSCL_AUTOCAL                                                                           0x0d0c
#define regDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d
#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e
#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
#define regDSCL0_OTG_H_BLANK                                                                            0x0d0f
#define regDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
#define regDSCL0_OTG_V_BLANK                                                                            0x0d10
#define regDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
#define regDSCL0_RECOUT_START                                                                           0x0d11
#define regDSCL0_RECOUT_START_BASE_IDX                                                                  2
#define regDSCL0_RECOUT_SIZE                                                                            0x0d12
#define regDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
#define regDSCL0_MPC_SIZE                                                                               0x0d13
#define regDSCL0_MPC_SIZE_BASE_IDX                                                                      2
#define regDSCL0_LB_DATA_FORMAT                                                                         0x0d14
#define regDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
#define regDSCL0_LB_MEMORY_CTRL                                                                         0x0d15
#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
#define regDSCL0_LB_V_COUNTER                                                                           0x0d16
#define regDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
#define regDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17
#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
#define regDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18
#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
#define regDSCL0_OBUF_CONTROL                                                                           0x0d19
#define regDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
#define regDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a
#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2


// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
// base address: 0x0
#define regCM0_CM_CONTROL                                                                               0x0d20
#define regCM0_CM_CONTROL_BASE_IDX                                                                      2
#define regCM0_CM_POST_CSC_CONTROL                                                                      0x0d21
#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_C11_C12                                                                      0x0d22
#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_C13_C14                                                                      0x0d23
#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_C21_C22                                                                      0x0d24
#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_C23_C24                                                                      0x0d25
#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_C31_C32                                                                      0x0d26
#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_C33_C34                                                                      0x0d27
#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28
#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
#define regCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29
#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
#define regCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a
#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
#define regCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b
#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
#define regCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c
#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
#define regCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d
#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
#define regCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e
#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f
#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30
#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31
#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32
#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33
#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34
#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35
#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
#define regCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36
#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
#define regCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37
#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
#define regCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38
#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
#define regCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39
#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
#define regCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a
#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
#define regCM0_CM_BIAS_CR_R                                                                             0x0d3b
#define regCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
#define regCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c
#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
#define regCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d
#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
#define regCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e
#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
#define regCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f
#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
#define regCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40
#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50
#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
#define regCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51
#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
#define regCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52
#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
#define regCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53
#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54
#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55
#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56
#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57
#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58
#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59
#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a
#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b
#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c
#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d
#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e
#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f
#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60
#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61
#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62
#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63
#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73
#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
#define regCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74
#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
#define regCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75
#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
#define regCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76
#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77
#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78
#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79
#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a
#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b
#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c
#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d
#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e
#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f
#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80
#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81
#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82
#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83
#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84
#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85
#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86
#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
#define regCM0_CM_HDR_MULT_COEF                                                                         0x0d87
#define regCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
#define regCM0_CM_MEM_PWR_CTRL                                                                          0x0d88
#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
#define regCM0_CM_MEM_PWR_STATUS                                                                        0x0d89
#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
#define regCM0_CM_DEALPHA                                                                               0x0d8b
#define regCM0_CM_DEALPHA_BASE_IDX                                                                      2
#define regCM0_CM_COEF_FORMAT                                                                           0x0d8c
#define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
#define regCM0_CM_TEST_DEBUG_INDEX                                                                      0x0d8d
#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
#define regCM0_CM_TEST_DEBUG_DATA                                                                       0x0d8e
#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2


// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x3890
#define regDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x0e24
#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2
#define regDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x0e25
#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
#define regDC_PERFMON11_PERFCOUNTER_STATE                                                               0x0e26
#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2
#define regDC_PERFMON11_PERFMON_CNTL                                                                    0x0e27
#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2
#define regDC_PERFMON11_PERFMON_CNTL2                                                                   0x0e28
#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2
#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x0e29
#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
#define regDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x0e2a
#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
#define regDC_PERFMON11_PERFMON_HI                                                                      0x0e2b
#define regDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2
#define regDC_PERFMON11_PERFMON_LOW                                                                     0x0e2c
#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2


// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
// base address: 0x5ac
#define regDPP_TOP1_DPP_CONTROL                                                                         0x0e30
#define regDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
#define regDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
#define regDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
#define regDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
#define regDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
#define regDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2


// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
// base address: 0x5ac
#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
#define regCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
#define regCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
#define regCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
#define regCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
#define regCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
#define regCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
#define regCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
#define regCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
#define regCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
#define regCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
#define regCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
#define regCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
#define regCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
#define regCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49
#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2
#define regCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a
#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2
#define regCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b
#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2
#define regCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c
#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2
#define regCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d
#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2
#define regCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e
#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2
#define regCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f
#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2
#define regCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50
#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2
#define regCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51
#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
#define regCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52
#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
#define regCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53
#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
#define regCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54
#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
#define regCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55
#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
#define regCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56
#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
#define regCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57
#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2
#define regCNVC_CFG1_PRE_DEGAM                                                                          0x0e58
#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2
#define regCNVC_CFG1_PRE_REALPHA                                                                        0x0e59
#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2


// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
// base address: 0x5ac
#define regCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c
#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
#define regCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d
#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
#define regCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e
#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f
#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2


// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
// base address: 0x5ac
#define regDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64
#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
#define regDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65
#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
#define regDSCL1_SCL_MODE                                                                               0x0e66
#define regDSCL1_SCL_MODE_BASE_IDX                                                                      2
#define regDSCL1_SCL_TAP_CONTROL                                                                        0x0e67
#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
#define regDSCL1_DSCL_CONTROL                                                                           0x0e68
#define regDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
#define regDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69
#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a
#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b
#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c
#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d
#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e
#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f
#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70
#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71
#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72
#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73
#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74
#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
#define regDSCL1_SCL_BLACK_COLOR                                                                        0x0e75
#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2
#define regDSCL1_DSCL_UPDATE                                                                            0x0e76
#define regDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
#define regDSCL1_DSCL_AUTOCAL                                                                           0x0e77
#define regDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78
#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79
#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
#define regDSCL1_OTG_H_BLANK                                                                            0x0e7a
#define regDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
#define regDSCL1_OTG_V_BLANK                                                                            0x0e7b
#define regDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
#define regDSCL1_RECOUT_START                                                                           0x0e7c
#define regDSCL1_RECOUT_START_BASE_IDX                                                                  2
#define regDSCL1_RECOUT_SIZE                                                                            0x0e7d
#define regDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
#define regDSCL1_MPC_SIZE                                                                               0x0e7e
#define regDSCL1_MPC_SIZE_BASE_IDX                                                                      2
#define regDSCL1_LB_DATA_FORMAT                                                                         0x0e7f
#define regDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
#define regDSCL1_LB_MEMORY_CTRL                                                                         0x0e80
#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
#define regDSCL1_LB_V_COUNTER                                                                           0x0e81
#define regDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
#define regDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82
#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
#define regDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83
#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
#define regDSCL1_OBUF_CONTROL                                                                           0x0e84
#define regDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
#define regDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85
#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2


// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
// base address: 0x5ac
#define regCM1_CM_CONTROL                                                                               0x0e8b
#define regCM1_CM_CONTROL_BASE_IDX                                                                      2
#define regCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c
#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d
#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e
#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f
#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_C23_C24                                                                      0x0e90
#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_C31_C32                                                                      0x0e91
#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_C33_C34                                                                      0x0e92
#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93
#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
#define regCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94
#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
#define regCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95
#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
#define regCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96
#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
#define regCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97
#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
#define regCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98
#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
#define regCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99
#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a
#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b
#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c
#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d
#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e
#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f
#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0
#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
#define regCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1
#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
#define regCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2
#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
#define regCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3
#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
#define regCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4
#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
#define regCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5
#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
#define regCM1_CM_BIAS_CR_R                                                                             0x0ea6
#define regCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
#define regCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7
#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
#define regCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8
#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
#define regCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9
#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
#define regCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa
#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
#define regCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab
#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb
#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
#define regCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc
#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
#define regCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd
#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
#define regCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe
#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf
#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0
#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1
#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2
#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3
#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4
#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5
#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6
#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7
#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8
#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9
#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca
#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb
#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc
#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd
#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece
#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede
#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
#define regCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf
#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
#define regCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0
#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
#define regCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1
#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2
#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3
#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4
#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5
#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6
#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7
#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8
#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9
#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea
#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb
#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec
#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed
#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee
#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef
#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0
#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1
#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
#define regCM1_CM_HDR_MULT_COEF                                                                         0x0ef2
#define regCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
#define regCM1_CM_MEM_PWR_CTRL                                                                          0x0ef3
#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
#define regCM1_CM_MEM_PWR_STATUS                                                                        0x0ef4
#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
#define regCM1_CM_DEALPHA                                                                               0x0ef6
#define regCM1_CM_DEALPHA_BASE_IDX                                                                      2
#define regCM1_CM_COEF_FORMAT                                                                           0x0ef7
#define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
#define regCM1_CM_TEST_DEBUG_INDEX                                                                      0x0ef8
#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
#define regCM1_CM_TEST_DEBUG_DATA                                                                       0x0ef9
#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2


// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x3e3c
#define regDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x0f8f
#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2
#define regDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x0f90
#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
#define regDC_PERFMON12_PERFCOUNTER_STATE                                                               0x0f91
#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2
#define regDC_PERFMON12_PERFMON_CNTL                                                                    0x0f92
#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2
#define regDC_PERFMON12_PERFMON_CNTL2                                                                   0x0f93
#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2
#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x0f94
#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
#define regDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x0f95
#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
#define regDC_PERFMON12_PERFMON_HI                                                                      0x0f96
#define regDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2
#define regDC_PERFMON12_PERFMON_LOW                                                                     0x0f97
#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2


// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
// base address: 0xb58
#define regDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
#define regDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
#define regDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
#define regDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
#define regDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
#define regDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
#define regDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2


// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
// base address: 0xb58
#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
#define regCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
#define regCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
#define regCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
#define regCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
#define regCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
#define regCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
#define regCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
#define regCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
#define regCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
#define regCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
#define regCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
#define regCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
#define regCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
#define regCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4
#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2
#define regCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5
#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2
#define regCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6
#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2
#define regCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7
#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2
#define regCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8
#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2
#define regCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9
#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2
#define regCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba
#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2
#define regCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb
#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2
#define regCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc
#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
#define regCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd
#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
#define regCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe
#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
#define regCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf
#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
#define regCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0
#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
#define regCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1
#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
#define regCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2
#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2
#define regCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3
#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2
#define regCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4
#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2


// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
// base address: 0xb58
#define regCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7
#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
#define regCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8
#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
#define regCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9
#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca
#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2


// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
// base address: 0xb58
#define regDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf
#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
#define regDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0
#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
#define regDSCL2_SCL_MODE                                                                               0x0fd1
#define regDSCL2_SCL_MODE_BASE_IDX                                                                      2
#define regDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2
#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
#define regDSCL2_DSCL_CONTROL                                                                           0x0fd3
#define regDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
#define regDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4
#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5
#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6
#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7
#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8
#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9
#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda
#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb
#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc
#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd
#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde
#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf
#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
#define regDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0
#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2
#define regDSCL2_DSCL_UPDATE                                                                            0x0fe1
#define regDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
#define regDSCL2_DSCL_AUTOCAL                                                                           0x0fe2
#define regDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3
#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4
#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
#define regDSCL2_OTG_H_BLANK                                                                            0x0fe5
#define regDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
#define regDSCL2_OTG_V_BLANK                                                                            0x0fe6
#define regDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
#define regDSCL2_RECOUT_START                                                                           0x0fe7
#define regDSCL2_RECOUT_START_BASE_IDX                                                                  2
#define regDSCL2_RECOUT_SIZE                                                                            0x0fe8
#define regDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
#define regDSCL2_MPC_SIZE                                                                               0x0fe9
#define regDSCL2_MPC_SIZE_BASE_IDX                                                                      2
#define regDSCL2_LB_DATA_FORMAT                                                                         0x0fea
#define regDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
#define regDSCL2_LB_MEMORY_CTRL                                                                         0x0feb
#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
#define regDSCL2_LB_V_COUNTER                                                                           0x0fec
#define regDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
#define regDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed
#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
#define regDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee
#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
#define regDSCL2_OBUF_CONTROL                                                                           0x0fef
#define regDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
#define regDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0
#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2


// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
// base address: 0xb58
#define regCM2_CM_CONTROL                                                                               0x0ff6
#define regCM2_CM_CONTROL_BASE_IDX                                                                      2
#define regCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7
#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8
#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9
#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa
#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb
#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc
#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd
#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe
#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
#define regCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff
#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
#define regCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000
#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
#define regCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001
#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
#define regCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002
#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
#define regCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003
#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
#define regCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004
#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005
#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006
#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007
#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008
#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009
#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a
#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b
#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
#define regCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c
#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
#define regCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d
#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
#define regCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e
#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
#define regCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f
#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
#define regCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010
#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
#define regCM2_CM_BIAS_CR_R                                                                             0x1011
#define regCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
#define regCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012
#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
#define regCM2_CM_GAMCOR_CONTROL                                                                        0x1013
#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
#define regCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014
#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
#define regCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015
#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
#define regCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016
#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026
#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
#define regCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027
#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
#define regCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028
#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
#define regCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029
#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a
#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b
#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c
#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d
#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e
#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f
#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030
#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031
#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032
#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033
#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034
#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035
#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036
#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037
#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038
#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039
#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049
#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
#define regCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a
#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
#define regCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b
#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
#define regCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c
#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d
#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e
#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f
#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050
#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051
#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052
#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053
#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054
#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055
#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056
#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057
#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058
#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059
#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a
#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b
#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c
#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
#define regCM2_CM_HDR_MULT_COEF                                                                         0x105d
#define regCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
#define regCM2_CM_MEM_PWR_CTRL                                                                          0x105e
#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
#define regCM2_CM_MEM_PWR_STATUS                                                                        0x105f
#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
#define regCM2_CM_DEALPHA                                                                               0x1061
#define regCM2_CM_DEALPHA_BASE_IDX                                                                      2
#define regCM2_CM_COEF_FORMAT                                                                           0x1062
#define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
#define regCM2_CM_TEST_DEBUG_INDEX                                                                      0x1063
#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
#define regCM2_CM_TEST_DEBUG_DATA                                                                       0x1064
#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2


// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x43e8
#define regDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x10fa
#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2
#define regDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x10fb
#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
#define regDC_PERFMON13_PERFCOUNTER_STATE                                                               0x10fc
#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2
#define regDC_PERFMON13_PERFMON_CNTL                                                                    0x10fd
#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2
#define regDC_PERFMON13_PERFMON_CNTL2                                                                   0x10fe
#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2
#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x10ff
#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
#define regDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x1100
#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
#define regDC_PERFMON13_PERFMON_HI                                                                      0x1101
#define regDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2
#define regDC_PERFMON13_PERFMON_LOW                                                                     0x1102
#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2


// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
// base address: 0x1104
#define regDPP_TOP3_DPP_CONTROL                                                                         0x1106
#define regDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
#define regDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
#define regDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
#define regDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
#define regDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
#define regDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2


// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
// base address: 0x1104
#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
#define regCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
#define regCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
#define regCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
#define regCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
#define regCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
#define regCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
#define regCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
#define regCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
#define regCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
#define regCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
#define regCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
#define regCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
#define regCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
#define regCNVC_CFG3_PRE_DEALPHA                                                                        0x111f
#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2
#define regCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120
#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2
#define regCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121
#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2
#define regCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122
#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2
#define regCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123
#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2
#define regCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124
#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2
#define regCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125
#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2
#define regCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126
#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2
#define regCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127
#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
#define regCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128
#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
#define regCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129
#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
#define regCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a
#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
#define regCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b
#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
#define regCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c
#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
#define regCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d
#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2
#define regCNVC_CFG3_PRE_DEGAM                                                                          0x112e
#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2
#define regCNVC_CFG3_PRE_REALPHA                                                                        0x112f
#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2


// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
// base address: 0x1104
#define regCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132
#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
#define regCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133
#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
#define regCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134
#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135
#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2


// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
// base address: 0x1104
#define regDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a
#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
#define regDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b
#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
#define regDSCL3_SCL_MODE                                                                               0x113c
#define regDSCL3_SCL_MODE_BASE_IDX                                                                      2
#define regDSCL3_SCL_TAP_CONTROL                                                                        0x113d
#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
#define regDSCL3_DSCL_CONTROL                                                                           0x113e
#define regDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
#define regDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f
#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140
#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141
#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142
#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143
#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144
#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145
#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146
#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147
#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148
#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149
#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a
#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
#define regDSCL3_SCL_BLACK_COLOR                                                                        0x114b
#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2
#define regDSCL3_DSCL_UPDATE                                                                            0x114c
#define regDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
#define regDSCL3_DSCL_AUTOCAL                                                                           0x114d
#define regDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e
#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f
#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
#define regDSCL3_OTG_H_BLANK                                                                            0x1150
#define regDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
#define regDSCL3_OTG_V_BLANK                                                                            0x1151
#define regDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
#define regDSCL3_RECOUT_START                                                                           0x1152
#define regDSCL3_RECOUT_START_BASE_IDX                                                                  2
#define regDSCL3_RECOUT_SIZE                                                                            0x1153
#define regDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
#define regDSCL3_MPC_SIZE                                                                               0x1154
#define regDSCL3_MPC_SIZE_BASE_IDX                                                                      2
#define regDSCL3_LB_DATA_FORMAT                                                                         0x1155
#define regDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
#define regDSCL3_LB_MEMORY_CTRL                                                                         0x1156
#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
#define regDSCL3_LB_V_COUNTER                                                                           0x1157
#define regDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
#define regDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158
#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
#define regDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159
#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
#define regDSCL3_OBUF_CONTROL                                                                           0x115a
#define regDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
#define regDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b
#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2


// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
// base address: 0x1104
#define regCM3_CM_CONTROL                                                                               0x1161
#define regCM3_CM_CONTROL_BASE_IDX                                                                      2
#define regCM3_CM_POST_CSC_CONTROL                                                                      0x1162
#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_C11_C12                                                                      0x1163
#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_C13_C14                                                                      0x1164
#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_C21_C22                                                                      0x1165
#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_C23_C24                                                                      0x1166
#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_C31_C32                                                                      0x1167
#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_C33_C34                                                                      0x1168
#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169
#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
#define regCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a
#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
#define regCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b
#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
#define regCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c
#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
#define regCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d
#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
#define regCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e
#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
#define regCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f
#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170
#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171
#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172
#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173
#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174
#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175
#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176
#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
#define regCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177
#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
#define regCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178
#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
#define regCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179
#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
#define regCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a
#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
#define regCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b
#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
#define regCM3_CM_BIAS_CR_R                                                                             0x117c
#define regCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
#define regCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d
#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
#define regCM3_CM_GAMCOR_CONTROL                                                                        0x117e
#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
#define regCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f
#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
#define regCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180
#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
#define regCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181
#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191
#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
#define regCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192
#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
#define regCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193
#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
#define regCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194
#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195
#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196
#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197
#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198
#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199
#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a
#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b
#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c
#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d
#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e
#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f
#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0
#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1
#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2
#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3
#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4
#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4
#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
#define regCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5
#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
#define regCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6
#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
#define regCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7
#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8
#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9
#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba
#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb
#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc
#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd
#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be
#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf
#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0
#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1
#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2
#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3
#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4
#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5
#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6
#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7
#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
#define regCM3_CM_HDR_MULT_COEF                                                                         0x11c8
#define regCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
#define regCM3_CM_MEM_PWR_CTRL                                                                          0x11c9
#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
#define regCM3_CM_MEM_PWR_STATUS                                                                        0x11ca
#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
#define regCM3_CM_DEALPHA                                                                               0x11cc
#define regCM3_CM_DEALPHA_BASE_IDX                                                                      2
#define regCM3_CM_COEF_FORMAT                                                                           0x11cd
#define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
#define regCM3_CM_TEST_DEBUG_INDEX                                                                      0x11ce
#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
#define regCM3_CM_TEST_DEBUG_DATA                                                                       0x11cf
#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2


// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x4994
#define regDC_PERFMON14_PERFCOUNTER_CNTL                                                                0x1265
#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX                                                       2
#define regDC_PERFMON14_PERFCOUNTER_CNTL2                                                               0x1266
#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
#define regDC_PERFMON14_PERFCOUNTER_STATE                                                               0x1267
#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX                                                      2
#define regDC_PERFMON14_PERFMON_CNTL                                                                    0x1268
#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX                                                           2
#define regDC_PERFMON14_PERFMON_CNTL2                                                                   0x1269
#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX                                                          2
#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC                                                         0x126a
#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
#define regDC_PERFMON14_PERFMON_CVALUE_LOW                                                              0x126b
#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
#define regDC_PERFMON14_PERFMON_HI                                                                      0x126c
#define regDC_PERFMON14_PERFMON_HI_BASE_IDX                                                             2
#define regDC_PERFMON14_PERFMON_LOW                                                                     0x126d
#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX                                                            2


// addressBlock: dce_dc_opp_fmt0_dispdec
// base address: 0x0
#define regFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
#define regFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
#define regFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
#define regFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
#define regFMT0_FMT_CONTROL                                                                             0x1840
#define regFMT0_FMT_CONTROL_BASE_IDX                                                                    2
#define regFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
#define regFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
#define regFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
#define regFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
#define regFMT0_FMT_CLAMP_CNTL                                                                          0x1845
#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
#define regFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
#define regFMT0_FMT_422_CONTROL                                                                         0x1849
#define regFMT0_FMT_422_CONTROL_BASE_IDX                                                                2


// addressBlock: dce_dc_opp_dpg0_dispdec
// base address: 0x0
#define regDPG0_DPG_CONTROL                                                                             0x1854
#define regDPG0_DPG_CONTROL_BASE_IDX                                                                    2
#define regDPG0_DPG_RAMP_CONTROL                                                                        0x1855
#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
#define regDPG0_DPG_DIMENSIONS                                                                          0x1856
#define regDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
#define regDPG0_DPG_COLOUR_R_CR                                                                         0x1857
#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
#define regDPG0_DPG_COLOUR_G_Y                                                                          0x1858
#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
#define regDPG0_DPG_COLOUR_B_CB                                                                         0x1859
#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
#define regDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
#define regDPG0_DPG_STATUS                                                                              0x185b
#define regDPG0_DPG_STATUS_BASE_IDX                                                                     2


// addressBlock: dce_dc_opp_oppbuf0_dispdec
// base address: 0x0
#define regOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
#define regOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2


// addressBlock: dce_dc_opp_opp_pipe0_dispdec
// base address: 0x0
#define regOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2


// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
// base address: 0x0
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2


// addressBlock: dce_dc_opp_fmt1_dispdec
// base address: 0x168
#define regFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
#define regFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
#define regFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
#define regFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
#define regFMT1_FMT_CONTROL                                                                             0x189a
#define regFMT1_FMT_CONTROL_BASE_IDX                                                                    2
#define regFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
#define regFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
#define regFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
#define regFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
#define regFMT1_FMT_CLAMP_CNTL                                                                          0x189f
#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
#define regFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
#define regFMT1_FMT_422_CONTROL                                                                         0x18a3
#define regFMT1_FMT_422_CONTROL_BASE_IDX                                                                2


// addressBlock: dce_dc_opp_dpg1_dispdec
// base address: 0x168
#define regDPG1_DPG_CONTROL                                                                             0x18ae
#define regDPG1_DPG_CONTROL_BASE_IDX                                                                    2
#define regDPG1_DPG_RAMP_CONTROL                                                                        0x18af
#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
#define regDPG1_DPG_DIMENSIONS                                                                          0x18b0
#define regDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
#define regDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
#define regDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
#define regDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
#define regDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
#define regDPG1_DPG_STATUS                                                                              0x18b5
#define regDPG1_DPG_STATUS_BASE_IDX                                                                     2

// addressBlock: dce_dc_opp_oppbuf1_dispdec
// base address: 0x168
#define regOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
#define regOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2


// addressBlock: dce_dc_opp_opp_pipe1_dispdec
// base address: 0x168
#define regOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2


// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
// base address: 0x168
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2


// addressBlock: dce_dc_opp_fmt2_dispdec
// base address: 0x2d0
#define regFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
#define regFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
#define regFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
#define regFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
#define regFMT2_FMT_CONTROL                                                                             0x18f4
#define regFMT2_FMT_CONTROL_BASE_IDX                                                                    2
#define regFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
#define regFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
#define regFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
#define regFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
#define regFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
#define regFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
#define regFMT2_FMT_422_CONTROL                                                                         0x18fd
#define regFMT2_FMT_422_CONTROL_BASE_IDX                                                                2


// addressBlock: dce_dc_opp_dpg2_dispdec
// base address: 0x2d0
#define regDPG2_DPG_CONTROL                                                                             0x1908
#define regDPG2_DPG_CONTROL_BASE_IDX                                                                    2
#define regDPG2_DPG_RAMP_CONTROL                                                                        0x1909
#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
#define regDPG2_DPG_DIMENSIONS                                                                          0x190a
#define regDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
#define regDPG2_DPG_COLOUR_R_CR                                                                         0x190b
#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
#define regDPG2_DPG_COLOUR_G_Y                                                                          0x190c
#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
#define regDPG2_DPG_COLOUR_B_CB                                                                         0x190d
#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
#define regDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
#define regDPG2_DPG_STATUS                                                                              0x190f
#define regDPG2_DPG_STATUS_BASE_IDX                                                                     2


// addressBlock: dce_dc_opp_oppbuf2_dispdec
// base address: 0x2d0
#define regOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
#define regOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2


// addressBlock: dce_dc_opp_opp_pipe2_dispdec
// base address: 0x2d0
#define regOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2


// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
// base address: 0x2d0
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2


// addressBlock: dce_dc_opp_fmt3_dispdec
// base address: 0x438
#define regFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
#define regFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
#define regFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
#define regFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
#define regFMT3_FMT_CONTROL                                                                             0x194e
#define regFMT3_FMT_CONTROL_BASE_IDX                                                                    2
#define regFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
#define regFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
#define regFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
#define regFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
#define regFMT3_FMT_CLAMP_CNTL                                                                          0x1953
#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
#define regFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
#define regFMT3_FMT_422_CONTROL                                                                         0x1957
#define regFMT3_FMT_422_CONTROL_BASE_IDX                                                                2


// addressBlock: dce_dc_opp_dpg3_dispdec
// base address: 0x438
#define regDPG3_DPG_CONTROL                                                                             0x1962
#define regDPG3_DPG_CONTROL_BASE_IDX                                                                    2
#define regDPG3_DPG_RAMP_CONTROL                                                                        0x1963
#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
#define regDPG3_DPG_DIMENSIONS                                                                          0x1964
#define regDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
#define regDPG3_DPG_COLOUR_R_CR                                                                         0x1965
#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
#define regDPG3_DPG_COLOUR_G_Y                                                                          0x1966
#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
#define regDPG3_DPG_COLOUR_B_CB                                                                         0x1967
#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
#define regDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
#define regDPG3_DPG_STATUS                                                                              0x1969
#define regDPG3_DPG_STATUS_BASE_IDX                                                                     2


// addressBlock: dce_dc_opp_oppbuf3_dispdec
// base address: 0x438
#define regOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
#define regOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2


// addressBlock: dce_dc_opp_opp_pipe3_dispdec
// base address: 0x438
#define regOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2


// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
// base address: 0x438
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2


// addressBlock: dce_dc_opp_opp_top_dispdec
// base address: 0x0
#define regOPP_TOP_CLK_CONTROL                                                                          0x1a5e
#define regOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
#define regOPP_ABM_CONTROL                                                                              0x1a60
#define regOPP_ABM_CONTROL_BASE_IDX                                                                     2


// addressBlock: dce_dc_opp_dscrm0_dispdec
// base address: 0x0
#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2


// addressBlock: dce_dc_opp_dscrm1_dispdec
// base address: 0x4
#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2


// addressBlock: dce_dc_opp_dscrm2_dispdec
// base address: 0x8
#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2


// addressBlock: dce_dc_opp_dscrm3_dispdec
// base address: 0xc
#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a67
#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2


// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
// base address: 0x6af8
#define regDC_PERFMON16_PERFCOUNTER_CNTL                                                                0x1abe
#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX                                                       2
#define regDC_PERFMON16_PERFCOUNTER_CNTL2                                                               0x1abf
#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
#define regDC_PERFMON16_PERFCOUNTER_STATE                                                               0x1ac0
#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX                                                      2
#define regDC_PERFMON16_PERFMON_CNTL                                                                    0x1ac1
#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX                                                           2
#define regDC_PERFMON16_PERFMON_CNTL2                                                                   0x1ac2
#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX                                                          2
#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC                                                         0x1ac3
#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
#define regDC_PERFMON16_PERFMON_CVALUE_LOW                                                              0x1ac4
#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
#define regDC_PERFMON16_PERFMON_HI                                                                      0x1ac5
#define regDC_PERFMON16_PERFMON_HI_BASE_IDX                                                             2
#define regDC_PERFMON16_PERFMON_LOW                                                                     0x1ac6
#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX                                                            2


// addressBlock: dce_dc_optc_odm0_dispdec
// base address: 0x0
#define regODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
#define regODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
#define regODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
#define regODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
#define regODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
#define regODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
#define regODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
#define regODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2


// addressBlock: dce_dc_optc_odm1_dispdec
// base address: 0x40
#define regODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
#define regODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
#define regODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
#define regODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
#define regODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
#define regODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
#define regODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
#define regODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2


// addressBlock: dce_dc_optc_odm2_dispdec
// base address: 0x80
#define regODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
#define regODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
#define regODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
#define regODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
#define regODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
#define regODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
#define regODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
#define regODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2


// addressBlock: dce_dc_optc_odm3_dispdec
// base address: 0xc0
#define regODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
#define regODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
#define regODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
#define regODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
#define regODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
#define regODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
#define regODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
#define regODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2


// addressBlock: dce_dc_optc_otg0_dispdec
// base address: 0x0
#define regOTG0_OTG_H_TOTAL                                                                             0x1b2a
#define regOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
#define regOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
#define regOTG0_OTG_H_SYNC_A                                                                            0x1b2c
#define regOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
#define regOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
#define regOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
#define regOTG0_OTG_V_TOTAL                                                                             0x1b2f
#define regOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
#define regOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
#define regOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
#define regOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
#define regOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
#define regOTG0_OTG_V_COUNT_STOP_CONTROL                                                                0x1b34
#define regOTG0_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2
#define regOTG0_OTG_V_COUNT_STOP_CONTROL2                                                               0x1b35
#define regOTG0_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2
#define regOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b36
#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
#define regOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b37
#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
#define regOTG0_OTG_V_BLANK_START_END                                                                   0x1b38
#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
#define regOTG0_OTG_V_SYNC_A                                                                            0x1b39
#define regOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
#define regOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b3a
#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
#define regOTG0_OTG_TRIGA_CNTL                                                                          0x1b3b
#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
#define regOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3c
#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
#define regOTG0_OTG_TRIGB_CNTL                                                                          0x1b3d
#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
#define regOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3e
#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3f
#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b41
#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
#define regOTG0_OTG_CONTROL                                                                             0x1b43
#define regOTG0_OTG_CONTROL_BASE_IDX                                                                    2
#define regOTG0_OTG_DLPC_CONTROL                                                                        0x1b44
#define regOTG0_OTG_DLPC_CONTROL_BASE_IDX                                                               2
#define regOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b45
#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
#define regOTG0_OTG_INTERLACE_STATUS                                                                    0x1b46
#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
#define regOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
#define regOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
#define regOTG0_OTG_STATUS                                                                              0x1b49
#define regOTG0_OTG_STATUS_BASE_IDX                                                                     2
#define regOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
#define regOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
#define regOTG0_OTG_LONG_VBLANK_STATUS                                                                  0x1b4b
#define regOTG0_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2
#define regOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4c
#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
#define regOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4d
#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
#define regOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4e
#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
#define regOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4f
#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
#define regOTG0_OTG_COUNT_CONTROL                                                                       0x1b50
#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
#define regOTG0_OTG_COUNT_RESET                                                                         0x1b51
#define regOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b52
#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
#define regOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b53
#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
#define regOTG0_OTG_STEREO_STATUS                                                                       0x1b54
#define regOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
#define regOTG0_OTG_STEREO_CONTROL                                                                      0x1b55
#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
#define regOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b56
#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
#define regOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b57
#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
#define regOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b58
#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
#define regOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b59
#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
#define regOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b5a
#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
#define regOTG0_OTG_UPDATE_LOCK                                                                         0x1b5b
#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5c
#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
#define regOTG0_OTG_MASTER_EN                                                                           0x1b5d
#define regOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b5f
#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b60
#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b61
#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b62
#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b63
#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b64
#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
#define regOTG0_OTG_CRC_CNTL                                                                            0x1b65
#define regOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b66
#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b67
#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b68
#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b69
#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
#define regOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6a
#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
#define regOTG0_OTG_CRC0_DATA_B                                                                         0x1b6b
#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b6c
#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b6d
#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b6e
#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b6f
#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
#define regOTG0_OTG_CRC1_DATA_RG                                                                        0x1b70
#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
#define regOTG0_OTG_CRC1_DATA_B                                                                         0x1b71
#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
#define regOTG0_OTG_CRC2_DATA_RG                                                                        0x1b72
#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
#define regOTG0_OTG_CRC2_DATA_B                                                                         0x1b73
#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
#define regOTG0_OTG_CRC3_DATA_RG                                                                        0x1b74
#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
#define regOTG0_OTG_CRC3_DATA_B                                                                         0x1b75
#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b76
#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b77
#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1b78
#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1b79
#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1b7a
#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1b7b
#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1b7c
#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1b7d
#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1b7e
#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1b7f
#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b80
#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
#define regOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b81
#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
#define regOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b82
#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
#define regOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b83
#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
#define regOTG0_OTG_CLOCK_CONTROL                                                                       0x1b84
#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
#define regOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b85
#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
#define regOTG0_OTG_VUPDATE_PARAM                                                                       0x1b86
#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
#define regOTG0_OTG_VREADY_PARAM                                                                        0x1b87
#define regOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
#define regOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b88
#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
#define regOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b89
#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
#define regOTG0_OTG_GSL_CONTROL                                                                         0x1b8a
#define regOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
#define regOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8b
#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
#define regOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8c
#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
#define regOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8d
#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
#define regOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b8e
#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
#define regOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b8f
#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
#define regOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b90
#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
#define regOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b91
#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
#define regOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b92
#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
#define regOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b93
#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
#define regOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b95
#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b96
#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
#define regOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b97
#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
#define regOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b98
#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
#define regOTG0_OTG_DRR_CONTROL                                                                         0x1b99
#define regOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
#define regOTG0_OTG_DRR_CONTOL2                                                                         0x1b9a
#define regOTG0_OTG_DRR_CONTOL2_BASE_IDX                                                                2
#define regOTG0_OTG_M_CONST_DTO0                                                                        0x1b9b
#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2
#define regOTG0_OTG_M_CONST_DTO1                                                                        0x1b9c
#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2
#define regOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9d
#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
#define regOTG0_OTG_DSC_START_POSITION                                                                  0x1b9e
#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
#define regOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1b9f
#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
#define regOTG0_OTG_SPARE_REGISTER                                                                      0x1ba0
#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2


// addressBlock: dce_dc_optc_otg1_dispdec
// base address: 0x200
#define regOTG1_OTG_H_TOTAL                                                                             0x1baa
#define regOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
#define regOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
#define regOTG1_OTG_H_SYNC_A                                                                            0x1bac
#define regOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
#define regOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
#define regOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
#define regOTG1_OTG_V_TOTAL                                                                             0x1baf
#define regOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
#define regOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
#define regOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
#define regOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
#define regOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
#define regOTG1_OTG_V_COUNT_STOP_CONTROL                                                                0x1bb4
#define regOTG1_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2
#define regOTG1_OTG_V_COUNT_STOP_CONTROL2                                                               0x1bb5
#define regOTG1_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2
#define regOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb6
#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
#define regOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb7
#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
#define regOTG1_OTG_V_BLANK_START_END                                                                   0x1bb8
#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
#define regOTG1_OTG_V_SYNC_A                                                                            0x1bb9
#define regOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
#define regOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bba
#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
#define regOTG1_OTG_TRIGA_CNTL                                                                          0x1bbb
#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
#define regOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bbc
#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
#define regOTG1_OTG_TRIGB_CNTL                                                                          0x1bbd
#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
#define regOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbe
#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbf
#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bc1
#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
#define regOTG1_OTG_CONTROL                                                                             0x1bc3
#define regOTG1_OTG_CONTROL_BASE_IDX                                                                    2
#define regOTG1_OTG_DLPC_CONTROL                                                                        0x1bc4
#define regOTG1_OTG_DLPC_CONTROL_BASE_IDX                                                               2
#define regOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc5
#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
#define regOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc6
#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
#define regOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
#define regOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
#define regOTG1_OTG_STATUS                                                                              0x1bc9
#define regOTG1_OTG_STATUS_BASE_IDX                                                                     2
#define regOTG1_OTG_STATUS_POSITION                                                                     0x1bca
#define regOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
#define regOTG1_OTG_LONG_VBLANK_STATUS                                                                  0x1bcb
#define regOTG1_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2
#define regOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcc
#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
#define regOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcd
#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
#define regOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bce
#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
#define regOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bcf
#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
#define regOTG1_OTG_COUNT_CONTROL                                                                       0x1bd0
#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
#define regOTG1_OTG_COUNT_RESET                                                                         0x1bd1
#define regOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd2
#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
#define regOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd3
#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
#define regOTG1_OTG_STEREO_STATUS                                                                       0x1bd4
#define regOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
#define regOTG1_OTG_STEREO_CONTROL                                                                      0x1bd5
#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
#define regOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd6
#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
#define regOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd7
#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
#define regOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd8
#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
#define regOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd9
#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
#define regOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bda
#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
#define regOTG1_OTG_UPDATE_LOCK                                                                         0x1bdb
#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdc
#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
#define regOTG1_OTG_MASTER_EN                                                                           0x1bdd
#define regOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1bdf
#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be0
#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be1
#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be2
#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be3
#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be4
#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
#define regOTG1_OTG_CRC_CNTL                                                                            0x1be5
#define regOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1be6
#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1be7
#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1be8
#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1be9
#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
#define regOTG1_OTG_CRC0_DATA_RG                                                                        0x1bea
#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
#define regOTG1_OTG_CRC0_DATA_B                                                                         0x1beb
#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bec
#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bed
#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bee
#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bef
#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
#define regOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf0
#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
#define regOTG1_OTG_CRC1_DATA_B                                                                         0x1bf1
#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
#define regOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf2
#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
#define regOTG1_OTG_CRC2_DATA_B                                                                         0x1bf3
#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
#define regOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf4
#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
#define regOTG1_OTG_CRC3_DATA_B                                                                         0x1bf5
#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bf6
#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bf7
#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1bf8
#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1bf9
#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1bfa
#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1bfb
#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1bfc
#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1bfd
#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1bfe
#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1bff
#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c00
#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
#define regOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c01
#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
#define regOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c02
#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
#define regOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c03
#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
#define regOTG1_OTG_CLOCK_CONTROL                                                                       0x1c04
#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
#define regOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c05
#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
#define regOTG1_OTG_VUPDATE_PARAM                                                                       0x1c06
#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
#define regOTG1_OTG_VREADY_PARAM                                                                        0x1c07
#define regOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
#define regOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c08
#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
#define regOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c09
#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
#define regOTG1_OTG_GSL_CONTROL                                                                         0x1c0a
#define regOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
#define regOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0b
#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
#define regOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0c
#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
#define regOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0d
#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
#define regOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c0e
#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
#define regOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c0f
#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
#define regOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c10
#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
#define regOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c11
#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
#define regOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c12
#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
#define regOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c13
#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
#define regOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c15
#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c16
#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
#define regOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c17
#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
#define regOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c18
#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
#define regOTG1_OTG_DRR_CONTROL                                                                         0x1c19
#define regOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
#define regOTG1_OTG_DRR_CONTOL2                                                                         0x1c1a
#define regOTG1_OTG_DRR_CONTOL2_BASE_IDX                                                                2
#define regOTG1_OTG_M_CONST_DTO0                                                                        0x1c1b
#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2
#define regOTG1_OTG_M_CONST_DTO1                                                                        0x1c1c
#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2
#define regOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1d
#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
#define regOTG1_OTG_DSC_START_POSITION                                                                  0x1c1e
#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
#define regOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c1f
#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
#define regOTG1_OTG_SPARE_REGISTER                                                                      0x1c20
#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2


// addressBlock: dce_dc_optc_otg2_dispdec
// base address: 0x400
#define regOTG2_OTG_H_TOTAL                                                                             0x1c2a
#define regOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
#define regOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
#define regOTG2_OTG_H_SYNC_A                                                                            0x1c2c
#define regOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
#define regOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
#define regOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
#define regOTG2_OTG_V_TOTAL                                                                             0x1c2f
#define regOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
#define regOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
#define regOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
#define regOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
#define regOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
#define regOTG2_OTG_V_COUNT_STOP_CONTROL                                                                0x1c34
#define regOTG2_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2
#define regOTG2_OTG_V_COUNT_STOP_CONTROL2                                                               0x1c35
#define regOTG2_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2
#define regOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c36
#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
#define regOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c37
#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
#define regOTG2_OTG_V_BLANK_START_END                                                                   0x1c38
#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
#define regOTG2_OTG_V_SYNC_A                                                                            0x1c39
#define regOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
#define regOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c3a
#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
#define regOTG2_OTG_TRIGA_CNTL                                                                          0x1c3b
#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
#define regOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3c
#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
#define regOTG2_OTG_TRIGB_CNTL                                                                          0x1c3d
#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
#define regOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3e
#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3f
#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c41
#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
#define regOTG2_OTG_CONTROL                                                                             0x1c43
#define regOTG2_OTG_CONTROL_BASE_IDX                                                                    2
#define regOTG2_OTG_DLPC_CONTROL                                                                        0x1c44
#define regOTG2_OTG_DLPC_CONTROL_BASE_IDX                                                               2
#define regOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c45
#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
#define regOTG2_OTG_INTERLACE_STATUS                                                                    0x1c46
#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
#define regOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
#define regOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
#define regOTG2_OTG_STATUS                                                                              0x1c49
#define regOTG2_OTG_STATUS_BASE_IDX                                                                     2
#define regOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
#define regOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
#define regOTG2_OTG_LONG_VBLANK_STATUS                                                                  0x1c4b
#define regOTG2_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2
#define regOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4c
#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
#define regOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4d
#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
#define regOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4e
#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
#define regOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4f
#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
#define regOTG2_OTG_COUNT_CONTROL                                                                       0x1c50
#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
#define regOTG2_OTG_COUNT_RESET                                                                         0x1c51
#define regOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c52
#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
#define regOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c53
#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
#define regOTG2_OTG_STEREO_STATUS                                                                       0x1c54
#define regOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
#define regOTG2_OTG_STEREO_CONTROL                                                                      0x1c55
#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
#define regOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c56
#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
#define regOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c57
#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
#define regOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c58
#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
#define regOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c59
#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
#define regOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c5a
#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
#define regOTG2_OTG_UPDATE_LOCK                                                                         0x1c5b
#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5c
#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
#define regOTG2_OTG_MASTER_EN                                                                           0x1c5d
#define regOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c5f
#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c60
#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c61
#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c62
#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c63
#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c64
#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
#define regOTG2_OTG_CRC_CNTL                                                                            0x1c65
#define regOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c66
#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c67
#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c68
#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c69
#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
#define regOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6a
#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
#define regOTG2_OTG_CRC0_DATA_B                                                                         0x1c6b
#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c6c
#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c6d
#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c6e
#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c6f
#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
#define regOTG2_OTG_CRC1_DATA_RG                                                                        0x1c70
#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
#define regOTG2_OTG_CRC1_DATA_B                                                                         0x1c71
#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
#define regOTG2_OTG_CRC2_DATA_RG                                                                        0x1c72
#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
#define regOTG2_OTG_CRC2_DATA_B                                                                         0x1c73
#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
#define regOTG2_OTG_CRC3_DATA_RG                                                                        0x1c74
#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
#define regOTG2_OTG_CRC3_DATA_B                                                                         0x1c75
#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c76
#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c77
#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1c78
#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1c79
#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1c7a
#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1c7b
#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1c7c
#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1c7d
#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1c7e
#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1c7f
#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c80
#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
#define regOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c81
#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
#define regOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c82
#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
#define regOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c83
#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
#define regOTG2_OTG_CLOCK_CONTROL                                                                       0x1c84
#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
#define regOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c85
#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
#define regOTG2_OTG_VUPDATE_PARAM                                                                       0x1c86
#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
#define regOTG2_OTG_VREADY_PARAM                                                                        0x1c87
#define regOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
#define regOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c88
#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
#define regOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c89
#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
#define regOTG2_OTG_GSL_CONTROL                                                                         0x1c8a
#define regOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
#define regOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8b
#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
#define regOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8c
#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
#define regOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8d
#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
#define regOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c8e
#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
#define regOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c8f
#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
#define regOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c90
#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
#define regOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c91
#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
#define regOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c92
#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
#define regOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c93
#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
#define regOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c95
#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c96
#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
#define regOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c97
#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
#define regOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c98
#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
#define regOTG2_OTG_DRR_CONTROL                                                                         0x1c99
#define regOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
#define regOTG2_OTG_DRR_CONTOL2                                                                         0x1c9a
#define regOTG2_OTG_DRR_CONTOL2_BASE_IDX                                                                2
#define regOTG2_OTG_M_CONST_DTO0                                                                        0x1c9b
#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2
#define regOTG2_OTG_M_CONST_DTO1                                                                        0x1c9c
#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2
#define regOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9d
#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
#define regOTG2_OTG_DSC_START_POSITION                                                                  0x1c9e
#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
#define regOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1c9f
#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
#define regOTG2_OTG_SPARE_REGISTER                                                                      0x1ca0
#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2


// addressBlock: dce_dc_optc_otg3_dispdec
// base address: 0x600
#define regOTG3_OTG_H_TOTAL                                                                             0x1caa
#define regOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
#define regOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
#define regOTG3_OTG_H_SYNC_A                                                                            0x1cac
#define regOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
#define regOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
#define regOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
#define regOTG3_OTG_V_TOTAL                                                                             0x1caf
#define regOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
#define regOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
#define regOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
#define regOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
#define regOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
#define regOTG3_OTG_V_COUNT_STOP_CONTROL                                                                0x1cb4
#define regOTG3_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2
#define regOTG3_OTG_V_COUNT_STOP_CONTROL2                                                               0x1cb5
#define regOTG3_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2
#define regOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb6
#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
#define regOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb7
#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
#define regOTG3_OTG_V_BLANK_START_END                                                                   0x1cb8
#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
#define regOTG3_OTG_V_SYNC_A                                                                            0x1cb9
#define regOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
#define regOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cba
#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
#define regOTG3_OTG_TRIGA_CNTL                                                                          0x1cbb
#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
#define regOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cbc
#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
#define regOTG3_OTG_TRIGB_CNTL                                                                          0x1cbd
#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
#define regOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbe
#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbf
#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cc1
#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
#define regOTG3_OTG_CONTROL                                                                             0x1cc3
#define regOTG3_OTG_CONTROL_BASE_IDX                                                                    2
#define regOTG3_OTG_DLPC_CONTROL                                                                        0x1cc4
#define regOTG3_OTG_DLPC_CONTROL_BASE_IDX                                                               2
#define regOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc5
#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
#define regOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc6
#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
#define regOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
#define regOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
#define regOTG3_OTG_STATUS                                                                              0x1cc9
#define regOTG3_OTG_STATUS_BASE_IDX                                                                     2
#define regOTG3_OTG_STATUS_POSITION                                                                     0x1cca
#define regOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
#define regOTG3_OTG_LONG_VBLANK_STATUS                                                                  0x1ccb
#define regOTG3_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2
#define regOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccc
#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
#define regOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccd
#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
#define regOTG3_OTG_STATUS_VF_COUNT                                                                     0x1cce
#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
#define regOTG3_OTG_STATUS_HV_COUNT                                                                     0x1ccf
#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
#define regOTG3_OTG_COUNT_CONTROL                                                                       0x1cd0
#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
#define regOTG3_OTG_COUNT_RESET                                                                         0x1cd1
#define regOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd2
#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
#define regOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd3
#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
#define regOTG3_OTG_STEREO_STATUS                                                                       0x1cd4
#define regOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
#define regOTG3_OTG_STEREO_CONTROL                                                                      0x1cd5
#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
#define regOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd6
#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
#define regOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd7
#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
#define regOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd8
#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
#define regOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd9
#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
#define regOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cda
#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
#define regOTG3_OTG_UPDATE_LOCK                                                                         0x1cdb
#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdc
#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
#define regOTG3_OTG_MASTER_EN                                                                           0x1cdd
#define regOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1cdf
#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce0
#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce1
#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce2
#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce3
#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce4
#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
#define regOTG3_OTG_CRC_CNTL                                                                            0x1ce5
#define regOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1ce6
#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1ce7
#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1ce8
#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ce9
#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
#define regOTG3_OTG_CRC0_DATA_RG                                                                        0x1cea
#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
#define regOTG3_OTG_CRC0_DATA_B                                                                         0x1ceb
#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cec
#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1ced
#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cee
#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cef
#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
#define regOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf0
#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
#define regOTG3_OTG_CRC1_DATA_B                                                                         0x1cf1
#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
#define regOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf2
#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
#define regOTG3_OTG_CRC2_DATA_B                                                                         0x1cf3
#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
#define regOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf4
#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
#define regOTG3_OTG_CRC3_DATA_B                                                                         0x1cf5
#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cf6
#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cf7
#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1cf8
#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1cf9
#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1cfa
#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1cfb
#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1cfc
#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1cfd
#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1cfe
#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1cff
#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2
#define regOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d00
#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
#define regOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d01
#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
#define regOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d02
#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
#define regOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d03
#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
#define regOTG3_OTG_CLOCK_CONTROL                                                                       0x1d04
#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
#define regOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d05
#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
#define regOTG3_OTG_VUPDATE_PARAM                                                                       0x1d06
#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
#define regOTG3_OTG_VREADY_PARAM                                                                        0x1d07
#define regOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
#define regOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d08
#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
#define regOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d09
#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
#define regOTG3_OTG_GSL_CONTROL                                                                         0x1d0a
#define regOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
#define regOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0b
#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
#define regOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0c
#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
#define regOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0d
#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
#define regOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d0e
#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
#define regOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d0f
#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
#define regOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d10
#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
#define regOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d11
#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
#define regOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d12
#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
#define regOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d13
#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
#define regOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d15
#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d16
#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
#define regOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d17
#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
#define regOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d18
#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
#define regOTG3_OTG_DRR_CONTROL                                                                         0x1d19
#define regOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
#define regOTG3_OTG_DRR_CONTOL2                                                                         0x1d1a
#define regOTG3_OTG_DRR_CONTOL2_BASE_IDX                                                                2
#define regOTG3_OTG_M_CONST_DTO0                                                                        0x1d1b
#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2
#define regOTG3_OTG_M_CONST_DTO1                                                                        0x1d1c
#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2
#define regOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1d
#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
#define regOTG3_OTG_DSC_START_POSITION                                                                  0x1d1e
#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
#define regOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d1f
#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
#define regOTG3_OTG_SPARE_REGISTER                                                                      0x1d20
#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2


// addressBlock: dce_dc_optc_optc_misc_dispdec
// base address: 0x0
#define regGSL_SOURCE_SELECT                                                                            0x1e2b
#define regGSL_SOURCE_SELECT_BASE_IDX                                                                   2
#define regOPTC_DLPC_CONTROL                                                                            0x1e2c
#define regOPTC_DLPC_CONTROL_BASE_IDX                                                                   2
#define regOPTC_CLOCK_CONTROL                                                                           0x1e2d
#define regOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
#define regODM_MEM_PWR_CTRL                                                                             0x1e2e
#define regODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
#define regODM_MEM_PWR_CTRL3                                                                            0x1e30
#define regODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
#define regODM_MEM_PWR_STATUS                                                                           0x1e31
#define regODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
#define regOPTC_MISC_SPARE_REGISTER                                                                     0x1e32
#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2


// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
// base address: 0x79a8
#define regDC_PERFMON17_PERFCOUNTER_CNTL                                                                0x1e6a
#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX                                                       2
#define regDC_PERFMON17_PERFCOUNTER_CNTL2                                                               0x1e6b
#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
#define regDC_PERFMON17_PERFCOUNTER_STATE                                                               0x1e6c
#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX                                                      2
#define regDC_PERFMON17_PERFMON_CNTL                                                                    0x1e6d
#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX                                                           2
#define regDC_PERFMON17_PERFMON_CNTL2                                                                   0x1e6e
#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX                                                          2
#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC                                                         0x1e6f
#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
#define regDC_PERFMON17_PERFMON_CVALUE_LOW                                                              0x1e70
#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
#define regDC_PERFMON17_PERFMON_HI                                                                      0x1e71
#define regDC_PERFMON17_PERFMON_HI_BASE_IDX                                                             2
#define regDC_PERFMON17_PERFMON_LOW                                                                     0x1e72
#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX                                                            2


// addressBlock: dce_dc_dio_dout_i2c_dispdec
// base address: 0x0
#define regDC_I2C_CONTROL                                                                               0x1e98
#define regDC_I2C_CONTROL_BASE_IDX                                                                      2
#define regDC_I2C_ARBITRATION                                                                           0x1e99
#define regDC_I2C_ARBITRATION_BASE_IDX                                                                  2
#define regDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
#define regDC_I2C_SW_STATUS                                                                             0x1e9b
#define regDC_I2C_SW_STATUS_BASE_IDX                                                                    2
#define regDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
#define regDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
#define regDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
#define regDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
#define regDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0
#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2
#define regDC_I2C_DDC1_SPEED                                                                            0x1ea2
#define regDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
#define regDC_I2C_DDC1_SETUP                                                                            0x1ea3
#define regDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
#define regDC_I2C_DDC2_SPEED                                                                            0x1ea4
#define regDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
#define regDC_I2C_DDC2_SETUP                                                                            0x1ea5
#define regDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
#define regDC_I2C_DDC3_SPEED                                                                            0x1ea6
#define regDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
#define regDC_I2C_DDC3_SETUP                                                                            0x1ea7
#define regDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
#define regDC_I2C_DDC4_SPEED                                                                            0x1ea8
#define regDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
#define regDC_I2C_DDC4_SETUP                                                                            0x1ea9
#define regDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
#define regDC_I2C_DDC5_SPEED                                                                            0x1eaa
#define regDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2
#define regDC_I2C_DDC5_SETUP                                                                            0x1eab
#define regDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2
#define regDC_I2C_TRANSACTION0                                                                          0x1eae
#define regDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
#define regDC_I2C_TRANSACTION1                                                                          0x1eaf
#define regDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
#define regDC_I2C_TRANSACTION2                                                                          0x1eb0
#define regDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
#define regDC_I2C_TRANSACTION3                                                                          0x1eb1
#define regDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
#define regDC_I2C_DATA                                                                                  0x1eb2
#define regDC_I2C_DATA_BASE_IDX                                                                         2
#define regDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
#define regDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2


// addressBlock: dce_dc_dio_dio_misc_dispdec
// base address: 0x0
#define regDIO_DCN_STATUS                                                                               0x1ec3
#define regDIO_DCN_STATUS_BASE_IDX                                                                      2
#define regDIO_SCRATCH0                                                                                 0x1eca
#define regDIO_SCRATCH0_BASE_IDX                                                                        2
#define regDIO_SCRATCH1                                                                                 0x1ecb
#define regDIO_SCRATCH1_BASE_IDX                                                                        2
#define regDIO_SCRATCH2                                                                                 0x1ecc
#define regDIO_SCRATCH2_BASE_IDX                                                                        2
#define regDIO_SCRATCH3                                                                                 0x1ecd
#define regDIO_SCRATCH3_BASE_IDX                                                                        2
#define regDIO_SCRATCH4                                                                                 0x1ece
#define regDIO_SCRATCH4_BASE_IDX                                                                        2
#define regDIO_SCRATCH5                                                                                 0x1ecf
#define regDIO_SCRATCH5_BASE_IDX                                                                        2
#define regDIO_SCRATCH6                                                                                 0x1ed0
#define regDIO_SCRATCH6_BASE_IDX                                                                        2
#define regDIO_SCRATCH7                                                                                 0x1ed1
#define regDIO_SCRATCH7_BASE_IDX                                                                        2
#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS                                                          0x1ed3
#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX                                                 2
#define regDIO_MEM_PWR_STATUS                                                                           0x1edd
#define regDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
#define regDIO_MEM_PWR_CTRL                                                                             0x1ede
#define regDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
#define regDIO_MEM_PWR_CTRL2                                                                            0x1edf
#define regDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
#define regDIO_CLK_CNTL                                                                                 0x1ee0
#define regDIO_CLK_CNTL_BASE_IDX                                                                        2
#define regDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
#define regDIO_PSP_INTERRUPT_STATUS                                                                     0x1f00
#define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX                                                            2
#define regDIO_PSP_INTERRUPT_CLEAR                                                                      0x1f01
#define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX                                                             2
#define regDIO_STATUS                                                                                   0x1f02
#define regDIO_STATUS_BASE_IDX                                                                          2
#define regDIO_LINKA_CNTL                                                                               0x1f04
#define regDIO_LINKA_CNTL_BASE_IDX                                                                      2
#define regDIO_LINKB_CNTL                                                                               0x1f05
#define regDIO_LINKB_CNTL_BASE_IDX                                                                      2
#define regDIO_LINKC_CNTL                                                                               0x1f06
#define regDIO_LINKC_CNTL_BASE_IDX                                                                      2
#define regDIO_LINKD_CNTL                                                                               0x1f07
#define regDIO_LINKD_CNTL_BASE_IDX                                                                      2
#define regDIO_LINKE_CNTL                                                                               0x1f08
#define regDIO_LINKE_CNTL_BASE_IDX                                                                      2
#define regDIO_LINKF_CNTL                                                                               0x1f09
#define regDIO_LINKF_CNTL_BASE_IDX                                                                      2


// addressBlock: dce_dc_dio_hpd0_dispdec
// base address: 0x0
#define regHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
#define regHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
#define regHPD0_DC_HPD_CONTROL                                                                          0x1f16
#define regHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
#define regHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2


// addressBlock: dce_dc_dio_hpd1_dispdec
// base address: 0x20
#define regHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
#define regHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
#define regHPD1_DC_HPD_CONTROL                                                                          0x1f1e
#define regHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
#define regHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2


// addressBlock: dce_dc_dio_hpd2_dispdec
// base address: 0x40
#define regHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
#define regHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
#define regHPD2_DC_HPD_CONTROL                                                                          0x1f26
#define regHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
#define regHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2


// addressBlock: dce_dc_dio_hpd3_dispdec
// base address: 0x60
#define regHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
#define regHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
#define regHPD3_DC_HPD_CONTROL                                                                          0x1f2e
#define regHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
#define regHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2


// addressBlock: dce_dc_dio_hpd4_dispdec
// base address: 0x80
#define regHPD4_DC_HPD_INT_STATUS                                                                       0x1f34
#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2
#define regHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35
#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
#define regHPD4_DC_HPD_CONTROL                                                                          0x1f36
#define regHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2
#define regHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37
#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38
#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2


// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
// base address: 0x7d10
#define regDC_PERFMON18_PERFCOUNTER_CNTL                                                                0x1f44
#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX                                                       2
#define regDC_PERFMON18_PERFCOUNTER_CNTL2                                                               0x1f45
#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
#define regDC_PERFMON18_PERFCOUNTER_STATE                                                               0x1f46
#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX                                                      2
#define regDC_PERFMON18_PERFMON_CNTL                                                                    0x1f47
#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX                                                           2
#define regDC_PERFMON18_PERFMON_CNTL2                                                                   0x1f48
#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX                                                          2
#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC                                                         0x1f49
#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
#define regDC_PERFMON18_PERFMON_CVALUE_LOW                                                              0x1f4a
#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
#define regDC_PERFMON18_PERFMON_HI                                                                      0x1f4b
#define regDC_PERFMON18_PERFMON_HI_BASE_IDX                                                             2
#define regDC_PERFMON18_PERFMON_LOW                                                                     0x1f4c
#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX                                                            2


// addressBlock: dce_dc_dio_dp_aux0_dispdec
// base address: 0x0
#define regDP_AUX0_AUX_CONTROL                                                                          0x1f50
#define regDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
#define regDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
#define regDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
#define regDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
#define regDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
#define regDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
#define regDP_AUX0_AUX_SW_DATA                                                                          0x1f56
#define regDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
#define regDP_AUX0_AUX_LS_DATA                                                                          0x1f57
#define regDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
#define regDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
#define regDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
#define regDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
#define regDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
#define regDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
#define regDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
#define regDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
#define regDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2


// addressBlock: dce_dc_dio_dp_aux1_dispdec
// base address: 0x70
#define regDP_AUX1_AUX_CONTROL                                                                          0x1f6c
#define regDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
#define regDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
#define regDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
#define regDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
#define regDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
#define regDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
#define regDP_AUX1_AUX_SW_DATA                                                                          0x1f72
#define regDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
#define regDP_AUX1_AUX_LS_DATA                                                                          0x1f73
#define regDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
#define regDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
#define regDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
#define regDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
#define regDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
#define regDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
#define regDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
#define regDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
#define regDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2


// addressBlock: dce_dc_dio_dp_aux2_dispdec
// base address: 0xe0
#define regDP_AUX2_AUX_CONTROL                                                                          0x1f88
#define regDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
#define regDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
#define regDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
#define regDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
#define regDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
#define regDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
#define regDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
#define regDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
#define regDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
#define regDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
#define regDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
#define regDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
#define regDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
#define regDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
#define regDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
#define regDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
#define regDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
#define regDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2


// addressBlock: dce_dc_dio_dp_aux3_dispdec
// base address: 0x150
#define regDP_AUX3_AUX_CONTROL                                                                          0x1fa4
#define regDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
#define regDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
#define regDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
#define regDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
#define regDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
#define regDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
#define regDP_AUX3_AUX_SW_DATA                                                                          0x1faa
#define regDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
#define regDP_AUX3_AUX_LS_DATA                                                                          0x1fab
#define regDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
#define regDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
#define regDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
#define regDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
#define regDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
#define regDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
#define regDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
#define regDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
#define regDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2


// addressBlock: dce_dc_dio_dp_aux4_dispdec
// base address: 0x1c0
#define regDP_AUX4_AUX_CONTROL                                                                          0x1fc0
#define regDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2
#define regDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1
#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2
#define regDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2
#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2
#define regDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3
#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
#define regDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4
#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2
#define regDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5
#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2
#define regDP_AUX4_AUX_SW_DATA                                                                          0x1fc6
#define regDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2
#define regDP_AUX4_AUX_LS_DATA                                                                          0x1fc7
#define regDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2
#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8
#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
#define regDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9
#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
#define regDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca
#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
#define regDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb
#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
#define regDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc
#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
#define regDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd
#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
#define regDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce
#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf
#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0
#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
#define regDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1
#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
#define regDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6
#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2


// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
// base address: 0x154a0
#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068
#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
#define regVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069
#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a
#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b
#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
#define regVPG0_VPG_GENERIC_STATUS                                                                      0x206c
#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2
#define regVPG0_VPG_MEM_PWR                                                                             0x206d
#define regVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2
#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e
#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
#define regVPG0_VPG_ISRC1_2_DATA                                                                        0x206f
#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
#define regVPG0_VPG_MPEG_INFO0                                                                          0x2070
#define regVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2
#define regVPG0_VPG_MPEG_INFO1                                                                          0x2071
#define regVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2


// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
// base address: 0x154cc
#define regAFMT0_AFMT_ACP                                                                               0x2073
#define regAFMT0_AFMT_ACP_BASE_IDX                                                                      2
#define regAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074
#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075
#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
#define regAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076
#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
#define regAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077
#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
#define regAFMT0_AFMT_60958_0                                                                           0x2078
#define regAFMT0_AFMT_60958_0_BASE_IDX                                                                  2
#define regAFMT0_AFMT_60958_1                                                                           0x2079
#define regAFMT0_AFMT_60958_1_BASE_IDX                                                                  2
#define regAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a
#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
#define regAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b
#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
#define regAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c
#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
#define regAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d
#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
#define regAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e
#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
#define regAFMT0_AFMT_60958_2                                                                           0x207f
#define regAFMT0_AFMT_60958_2_BASE_IDX                                                                  2
#define regAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080
#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
#define regAFMT0_AFMT_STATUS                                                                            0x2081
#define regAFMT0_AFMT_STATUS_BASE_IDX                                                                   2
#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082
#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
#define regAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083
#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
#define regAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084
#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
#define regAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085
#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
#define regAFMT0_AFMT_MEM_PWR                                                                           0x2087
#define regAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2


// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
// base address: 0x15544
#define regDME0_DME_CONTROL                                                                             0x2091
#define regDME0_DME_CONTROL_BASE_IDX                                                                    2
#define regDME0_DME_MEMORY_CONTROL                                                                      0x2092
#define regDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2



// addressBlock: dce_dc_dio_dig0_dispdec
// base address: 0x0
#define regDIG0_DIG_FE_CNTL                                                                             0x2093
#define regDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
#define regDIG0_DIG_FE_CLK_CNTL                                                                         0x2094
#define regDIG0_DIG_FE_CLK_CNTL_BASE_IDX                                                                2
#define regDIG0_DIG_FE_EN_CNTL                                                                          0x2095
#define regDIG0_DIG_FE_EN_CNTL_BASE_IDX                                                                 2
#define regDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x2096
#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
#define regDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x2097
#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
#define regDIG0_DIG_CLOCK_PATTERN                                                                       0x2098
#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
#define regDIG0_DIG_TEST_PATTERN                                                                        0x2099
#define regDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
#define regDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x209a
#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
#define regDIG0_DIG_FIFO_CTRL0                                                                          0x209b
#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
#define regDIG0_DIG_FIFO_CTRL1                                                                          0x209c
#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
#define regDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x209d
#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
#define regDIG0_HDMI_CONTROL                                                                            0x209e
#define regDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
#define regDIG0_HDMI_STATUS                                                                             0x209f
#define regDIG0_HDMI_STATUS_BASE_IDX                                                                    2
#define regDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x20a0
#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
#define regDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x20a1
#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
#define regDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x20a2
#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
#define regDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x20a3
#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
#define regDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x20a4
#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x20a5
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x20a6
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x20a7
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
#define regDIG0_HDMI_GC                                                                                 0x20a8
#define regDIG0_HDMI_GC_BASE_IDX                                                                        2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x20a9
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x20aa
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20ab
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20ac
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20ad
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20ae
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20af
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20b0
#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
#define regDIG0_HDMI_DB_CONTROL                                                                         0x20b1
#define regDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
#define regDIG0_HDMI_ACR_32_0                                                                           0x20b2
#define regDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
#define regDIG0_HDMI_ACR_32_1                                                                           0x20b3
#define regDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
#define regDIG0_HDMI_ACR_44_0                                                                           0x20b4
#define regDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
#define regDIG0_HDMI_ACR_44_1                                                                           0x20b5
#define regDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
#define regDIG0_HDMI_ACR_48_0                                                                           0x20b6
#define regDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
#define regDIG0_HDMI_ACR_48_1                                                                           0x20b7
#define regDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
#define regDIG0_HDMI_ACR_STATUS_0                                                                       0x20b8
#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
#define regDIG0_HDMI_ACR_STATUS_1                                                                       0x20b9
#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
#define regDIG0_AFMT_CNTL                                                                               0x20ba
#define regDIG0_AFMT_CNTL_BASE_IDX                                                                      2
#define regDIG0_DIG_BE_CLK_CNTL                                                                         0x20bb
#define regDIG0_DIG_BE_CLK_CNTL_BASE_IDX                                                                2
#define regDIG0_DIG_BE_CNTL                                                                             0x20bc
#define regDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
#define regDIG0_DIG_BE_EN_CNTL                                                                          0x20bd
#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
#define regDIG0_TMDS_CNTL                                                                               0x20e4
#define regDIG0_TMDS_CNTL_BASE_IDX                                                                      2
#define regDIG0_TMDS_CONTROL_CHAR                                                                       0x20e5
#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
#define regDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20e6
#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
#define regDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20e7
#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20e8
#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20e9
#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
#define regDIG0_TMDS_CTL_BITS                                                                           0x20eb
#define regDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
#define regDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20ec
#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20ed
#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
#define regDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20ee
#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
#define regDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20ef
#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
#define regDIG0_DIG_VERSION                                                                             0x20f1
#define regDIG0_DIG_VERSION_BASE_IDX                                                                    2


// addressBlock: dce_dc_dio_dp0_dispdec
// base address: 0x0
#define regDP0_DP_LINK_CNTL                                                                             0x211e
#define regDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
#define regDP0_DP_PIXEL_FORMAT                                                                          0x211f
#define regDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
#define regDP0_DP_MSA_COLORIMETRY                                                                       0x2120
#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
#define regDP0_DP_CONFIG                                                                                0x2121
#define regDP0_DP_CONFIG_BASE_IDX                                                                       2
#define regDP0_DP_VID_STREAM_CNTL                                                                       0x2122
#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
#define regDP0_DP_STEER_FIFO                                                                            0x2123
#define regDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
#define regDP0_DP_MSA_MISC                                                                              0x2124
#define regDP0_DP_MSA_MISC_BASE_IDX                                                                     2
#define regDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x2125
#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
#define regDP0_DP_VID_TIMING                                                                            0x2126
#define regDP0_DP_VID_TIMING_BASE_IDX                                                                   2
#define regDP0_DP_VID_N                                                                                 0x2127
#define regDP0_DP_VID_N_BASE_IDX                                                                        2
#define regDP0_DP_VID_M                                                                                 0x2128
#define regDP0_DP_VID_M_BASE_IDX                                                                        2
#define regDP0_DP_LINK_FRAMING_CNTL                                                                     0x2129
#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
#define regDP0_DP_HBR2_EYE_PATTERN                                                                      0x212a
#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
#define regDP0_DP_VID_MSA_VBID                                                                          0x212b
#define regDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
#define regDP0_DP_VID_INTERRUPT_CNTL                                                                    0x212c
#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
#define regDP0_DP_DPHY_CNTL                                                                             0x212d
#define regDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x212e
#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
#define regDP0_DP_DPHY_SYM0                                                                             0x212f
#define regDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
#define regDP0_DP_DPHY_SYM1                                                                             0x2130
#define regDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
#define regDP0_DP_DPHY_SYM2                                                                             0x2131
#define regDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
#define regDP0_DP_DPHY_8B10B_CNTL                                                                       0x2132
#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
#define regDP0_DP_DPHY_PRBS_CNTL                                                                        0x2133
#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
#define regDP0_DP_DPHY_SCRAM_CNTL                                                                       0x2134
#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
#define regDP0_DP_DPHY_CRC_EN                                                                           0x2135
#define regDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
#define regDP0_DP_DPHY_CRC_CNTL                                                                         0x2136
#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
#define regDP0_DP_DPHY_CRC_RESULT                                                                       0x2137
#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
#define regDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2138
#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
#define regDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2139
#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
#define regDP0_DP_DPHY_FAST_TRAINING                                                                    0x213a
#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
#define regDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x213b
#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
#define regDP0_DP_SEC_CNTL                                                                              0x2141
#define regDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
#define regDP0_DP_SEC_CNTL1                                                                             0x2142
#define regDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
#define regDP0_DP_SEC_FRAMING1                                                                          0x2143
#define regDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
#define regDP0_DP_SEC_FRAMING2                                                                          0x2144
#define regDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
#define regDP0_DP_SEC_FRAMING3                                                                          0x2145
#define regDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
#define regDP0_DP_SEC_FRAMING4                                                                          0x2146
#define regDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
#define regDP0_DP_SEC_AUD_N                                                                             0x2147
#define regDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
#define regDP0_DP_SEC_AUD_N_READBACK                                                                    0x2148
#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
#define regDP0_DP_SEC_AUD_M                                                                             0x2149
#define regDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
#define regDP0_DP_SEC_AUD_M_READBACK                                                                    0x214a
#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
#define regDP0_DP_SEC_TIMESTAMP                                                                         0x214b
#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
#define regDP0_DP_SEC_PACKET_CNTL                                                                       0x214c
#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
#define regDP0_DP_MSE_RATE_CNTL                                                                         0x214d
#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
#define regDP0_DP_MSE_RATE_UPDATE                                                                       0x214f
#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
#define regDP0_DP_MSE_SAT0                                                                              0x2150
#define regDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
#define regDP0_DP_MSE_SAT1                                                                              0x2151
#define regDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
#define regDP0_DP_MSE_SAT2                                                                              0x2152
#define regDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
#define regDP0_DP_MSE_SAT_UPDATE                                                                        0x2153
#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
#define regDP0_DP_MSE_LINK_TIMING                                                                       0x2154
#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
#define regDP0_DP_MSE_MISC_CNTL                                                                         0x2155
#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x215a
#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x215b
#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
#define regDP0_DP_MSE_SAT0_STATUS                                                                       0x215d
#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
#define regDP0_DP_MSE_SAT1_STATUS                                                                       0x215e
#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
#define regDP0_DP_MSE_SAT2_STATUS                                                                       0x215f
#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
#define regDP0_DP_DPIA_SPARE                                                                            0x2160
#define regDP0_DP_DPIA_SPARE_BASE_IDX                                                                   2
#define regDP0_DP_MSA_TIMING_PARAM1                                                                     0x2162
#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
#define regDP0_DP_MSA_TIMING_PARAM2                                                                     0x2163
#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
#define regDP0_DP_MSA_TIMING_PARAM3                                                                     0x2164
#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
#define regDP0_DP_MSA_TIMING_PARAM4                                                                     0x2165
#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
#define regDP0_DP_MSO_CNTL                                                                              0x2166
#define regDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
#define regDP0_DP_MSO_CNTL1                                                                             0x2167
#define regDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
#define regDP0_DP_DSC_CNTL                                                                              0x2168
#define regDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
#define regDP0_DP_SEC_CNTL2                                                                             0x2169
#define regDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
#define regDP0_DP_SEC_CNTL3                                                                             0x216a
#define regDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
#define regDP0_DP_SEC_CNTL4                                                                             0x216b
#define regDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
#define regDP0_DP_SEC_CNTL5                                                                             0x216c
#define regDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
#define regDP0_DP_SEC_CNTL6                                                                             0x216d
#define regDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
#define regDP0_DP_SEC_CNTL7                                                                             0x216e
#define regDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
#define regDP0_DP_DB_CNTL                                                                               0x216f
#define regDP0_DP_DB_CNTL_BASE_IDX                                                                      2
#define regDP0_DP_MSA_VBID_MISC                                                                         0x2170
#define regDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
#define regDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x2171
#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
#define regDP0_DP_ALPM_CNTL                                                                             0x2173
#define regDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
#define regDP0_DP_GSP8_CNTL                                                                             0x2174
#define regDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2
#define regDP0_DP_GSP9_CNTL                                                                             0x2175
#define regDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2
#define regDP0_DP_GSP10_CNTL                                                                            0x2176
#define regDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2
#define regDP0_DP_GSP11_CNTL                                                                            0x2177
#define regDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2
#define regDP0_DP_GSP_EN_DB_STATUS                                                                      0x2178
#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
#define regDP0_DP_AUXLESS_ALPM_CNTL1                                                                    0x2179
#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
#define regDP0_DP_AUXLESS_ALPM_CNTL2                                                                    0x217a
#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
#define regDP0_DP_AUXLESS_ALPM_CNTL3                                                                    0x217b
#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
#define regDP0_DP_AUXLESS_ALPM_CNTL4                                                                    0x217c
#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
#define regDP0_DP_AUXLESS_ALPM_CNTL5                                                                    0x217d
#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x217e
#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2
#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x217f
#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2
#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x2180
#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2
#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x2181
#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2
#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x2182
#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2


// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
// base address: 0x15930
#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x218c
#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
#define regVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x218d
#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x218e
#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x218f
#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
#define regVPG1_VPG_GENERIC_STATUS                                                                      0x2190
#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2
#define regVPG1_VPG_MEM_PWR                                                                             0x2191
#define regVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2
#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x2192
#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
#define regVPG1_VPG_ISRC1_2_DATA                                                                        0x2193
#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
#define regVPG1_VPG_MPEG_INFO0                                                                          0x2194
#define regVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2
#define regVPG1_VPG_MPEG_INFO1                                                                          0x2195
#define regVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2


// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
// base address: 0x1595c
#define regAFMT1_AFMT_ACP                                                                               0x2197
#define regAFMT1_AFMT_ACP_BASE_IDX                                                                      2
#define regAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2198
#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2199
#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
#define regAFMT1_AFMT_AUDIO_INFO0                                                                       0x219a
#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
#define regAFMT1_AFMT_AUDIO_INFO1                                                                       0x219b
#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
#define regAFMT1_AFMT_60958_0                                                                           0x219c
#define regAFMT1_AFMT_60958_0_BASE_IDX                                                                  2
#define regAFMT1_AFMT_60958_1                                                                           0x219d
#define regAFMT1_AFMT_60958_1_BASE_IDX                                                                  2
#define regAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x219e
#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
#define regAFMT1_AFMT_RAMP_CONTROL0                                                                     0x219f
#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
#define regAFMT1_AFMT_RAMP_CONTROL1                                                                     0x21a0
#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
#define regAFMT1_AFMT_RAMP_CONTROL2                                                                     0x21a1
#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
#define regAFMT1_AFMT_RAMP_CONTROL3                                                                     0x21a2
#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
#define regAFMT1_AFMT_60958_2                                                                           0x21a3
#define regAFMT1_AFMT_60958_2_BASE_IDX                                                                  2
#define regAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x21a4
#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
#define regAFMT1_AFMT_STATUS                                                                            0x21a5
#define regAFMT1_AFMT_STATUS_BASE_IDX                                                                   2
#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x21a6
#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
#define regAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x21a7
#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
#define regAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x21a8
#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
#define regAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x21a9
#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
#define regAFMT1_AFMT_MEM_PWR                                                                           0x21ab
#define regAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2


// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
// base address: 0x159d4
#define regDME1_DME_CONTROL                                                                             0x21b5
#define regDME1_DME_CONTROL_BASE_IDX                                                                    2
#define regDME1_DME_MEMORY_CONTROL                                                                      0x21b6
#define regDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2


// addressBlock: dce_dc_dio_dig1_dispdec
// base address: 0x490
#define regDIG1_DIG_FE_CNTL                                                                             0x21b7
#define regDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
#define regDIG1_DIG_FE_CLK_CNTL                                                                         0x21b8
#define regDIG1_DIG_FE_CLK_CNTL_BASE_IDX                                                                2
#define regDIG1_DIG_FE_EN_CNTL                                                                          0x21b9
#define regDIG1_DIG_FE_EN_CNTL_BASE_IDX                                                                 2
#define regDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x21ba
#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
#define regDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x21bb
#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
#define regDIG1_DIG_CLOCK_PATTERN                                                                       0x21bc
#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
#define regDIG1_DIG_TEST_PATTERN                                                                        0x21bd
#define regDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
#define regDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x21be
#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
#define regDIG1_DIG_FIFO_CTRL0                                                                          0x21bf
#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
#define regDIG1_DIG_FIFO_CTRL1                                                                          0x21c0
#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
#define regDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x21c1
#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
#define regDIG1_HDMI_CONTROL                                                                            0x21c2
#define regDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
#define regDIG1_HDMI_STATUS                                                                             0x21c3
#define regDIG1_HDMI_STATUS_BASE_IDX                                                                    2
#define regDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x21c4
#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
#define regDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x21c5
#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
#define regDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x21c6
#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
#define regDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x21c7
#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
#define regDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x21c8
#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x21c9
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x21ca
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x21cb
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
#define regDIG1_HDMI_GC                                                                                 0x21cc
#define regDIG1_HDMI_GC_BASE_IDX                                                                        2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x21cd
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x21ce
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21cf
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21d0
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21d1
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21d2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21d3
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21d4
#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
#define regDIG1_HDMI_DB_CONTROL                                                                         0x21d5
#define regDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
#define regDIG1_HDMI_ACR_32_0                                                                           0x21d6
#define regDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
#define regDIG1_HDMI_ACR_32_1                                                                           0x21d7
#define regDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
#define regDIG1_HDMI_ACR_44_0                                                                           0x21d8
#define regDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
#define regDIG1_HDMI_ACR_44_1                                                                           0x21d9
#define regDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
#define regDIG1_HDMI_ACR_48_0                                                                           0x21da
#define regDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
#define regDIG1_HDMI_ACR_48_1                                                                           0x21db
#define regDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
#define regDIG1_HDMI_ACR_STATUS_0                                                                       0x21dc
#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
#define regDIG1_HDMI_ACR_STATUS_1                                                                       0x21dd
#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
#define regDIG1_AFMT_CNTL                                                                               0x21de
#define regDIG1_AFMT_CNTL_BASE_IDX                                                                      2
#define regDIG1_DIG_BE_CLK_CNTL                                                                         0x21df
#define regDIG1_DIG_BE_CLK_CNTL_BASE_IDX                                                                2
#define regDIG1_DIG_BE_CNTL                                                                             0x21e0
#define regDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
#define regDIG1_DIG_BE_EN_CNTL                                                                          0x21e1
#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
#define regDIG1_TMDS_CNTL                                                                               0x2208
#define regDIG1_TMDS_CNTL_BASE_IDX                                                                      2
#define regDIG1_TMDS_CONTROL_CHAR                                                                       0x2209
#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
#define regDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x220a
#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
#define regDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x220b
#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x220c
#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x220d
#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
#define regDIG1_TMDS_CTL_BITS                                                                           0x220f
#define regDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
#define regDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x2210
#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x2211
#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
#define regDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x2212
#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
#define regDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x2213
#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
#define regDIG1_DIG_VERSION                                                                             0x2215
#define regDIG1_DIG_VERSION_BASE_IDX                                                                    2


// addressBlock: dce_dc_dio_dp1_dispdec
// base address: 0x490
#define regDP1_DP_LINK_CNTL                                                                             0x2242
#define regDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
#define regDP1_DP_PIXEL_FORMAT                                                                          0x2243
#define regDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
#define regDP1_DP_MSA_COLORIMETRY                                                                       0x2244
#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
#define regDP1_DP_CONFIG                                                                                0x2245
#define regDP1_DP_CONFIG_BASE_IDX                                                                       2
#define regDP1_DP_VID_STREAM_CNTL                                                                       0x2246
#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
#define regDP1_DP_STEER_FIFO                                                                            0x2247
#define regDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
#define regDP1_DP_MSA_MISC                                                                              0x2248
#define regDP1_DP_MSA_MISC_BASE_IDX                                                                     2
#define regDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x2249
#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
#define regDP1_DP_VID_TIMING                                                                            0x224a
#define regDP1_DP_VID_TIMING_BASE_IDX                                                                   2
#define regDP1_DP_VID_N                                                                                 0x224b
#define regDP1_DP_VID_N_BASE_IDX                                                                        2
#define regDP1_DP_VID_M                                                                                 0x224c
#define regDP1_DP_VID_M_BASE_IDX                                                                        2
#define regDP1_DP_LINK_FRAMING_CNTL                                                                     0x224d
#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
#define regDP1_DP_HBR2_EYE_PATTERN                                                                      0x224e
#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
#define regDP1_DP_VID_MSA_VBID                                                                          0x224f
#define regDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
#define regDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2250
#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
#define regDP1_DP_DPHY_CNTL                                                                             0x2251
#define regDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2252
#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
#define regDP1_DP_DPHY_SYM0                                                                             0x2253
#define regDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
#define regDP1_DP_DPHY_SYM1                                                                             0x2254
#define regDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
#define regDP1_DP_DPHY_SYM2                                                                             0x2255
#define regDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
#define regDP1_DP_DPHY_8B10B_CNTL                                                                       0x2256
#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
#define regDP1_DP_DPHY_PRBS_CNTL                                                                        0x2257
#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
#define regDP1_DP_DPHY_SCRAM_CNTL                                                                       0x2258
#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
#define regDP1_DP_DPHY_CRC_EN                                                                           0x2259
#define regDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
#define regDP1_DP_DPHY_CRC_CNTL                                                                         0x225a
#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
#define regDP1_DP_DPHY_CRC_RESULT                                                                       0x225b
#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
#define regDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x225c
#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
#define regDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x225d
#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
#define regDP1_DP_DPHY_FAST_TRAINING                                                                    0x225e
#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
#define regDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x225f
#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
#define regDP1_DP_SEC_CNTL                                                                              0x2265
#define regDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
#define regDP1_DP_SEC_CNTL1                                                                             0x2266
#define regDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
#define regDP1_DP_SEC_FRAMING1                                                                          0x2267
#define regDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
#define regDP1_DP_SEC_FRAMING2                                                                          0x2268
#define regDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
#define regDP1_DP_SEC_FRAMING3                                                                          0x2269
#define regDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
#define regDP1_DP_SEC_FRAMING4                                                                          0x226a
#define regDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
#define regDP1_DP_SEC_AUD_N                                                                             0x226b
#define regDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
#define regDP1_DP_SEC_AUD_N_READBACK                                                                    0x226c
#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
#define regDP1_DP_SEC_AUD_M                                                                             0x226d
#define regDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
#define regDP1_DP_SEC_AUD_M_READBACK                                                                    0x226e
#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
#define regDP1_DP_SEC_TIMESTAMP                                                                         0x226f
#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
#define regDP1_DP_SEC_PACKET_CNTL                                                                       0x2270
#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
#define regDP1_DP_MSE_RATE_CNTL                                                                         0x2271
#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
#define regDP1_DP_MSE_RATE_UPDATE                                                                       0x2273
#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
#define regDP1_DP_MSE_SAT0                                                                              0x2274
#define regDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
#define regDP1_DP_MSE_SAT1                                                                              0x2275
#define regDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
#define regDP1_DP_MSE_SAT2                                                                              0x2276
#define regDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
#define regDP1_DP_MSE_SAT_UPDATE                                                                        0x2277
#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
#define regDP1_DP_MSE_LINK_TIMING                                                                       0x2278
#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
#define regDP1_DP_MSE_MISC_CNTL                                                                         0x2279
#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x227e
#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x227f
#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
#define regDP1_DP_MSE_SAT0_STATUS                                                                       0x2281
#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
#define regDP1_DP_MSE_SAT1_STATUS                                                                       0x2282
#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
#define regDP1_DP_MSE_SAT2_STATUS                                                                       0x2283
#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
#define regDP1_DP_DPIA_SPARE                                                                            0x2284
#define regDP1_DP_DPIA_SPARE_BASE_IDX                                                                   2
#define regDP1_DP_MSA_TIMING_PARAM1                                                                     0x2286
#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
#define regDP1_DP_MSA_TIMING_PARAM2                                                                     0x2287
#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
#define regDP1_DP_MSA_TIMING_PARAM3                                                                     0x2288
#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
#define regDP1_DP_MSA_TIMING_PARAM4                                                                     0x2289
#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
#define regDP1_DP_MSO_CNTL                                                                              0x228a
#define regDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
#define regDP1_DP_MSO_CNTL1                                                                             0x228b
#define regDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
#define regDP1_DP_DSC_CNTL                                                                              0x228c
#define regDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
#define regDP1_DP_SEC_CNTL2                                                                             0x228d
#define regDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
#define regDP1_DP_SEC_CNTL3                                                                             0x228e
#define regDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
#define regDP1_DP_SEC_CNTL4                                                                             0x228f
#define regDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
#define regDP1_DP_SEC_CNTL5                                                                             0x2290
#define regDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
#define regDP1_DP_SEC_CNTL6                                                                             0x2291
#define regDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
#define regDP1_DP_SEC_CNTL7                                                                             0x2292
#define regDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
#define regDP1_DP_DB_CNTL                                                                               0x2293
#define regDP1_DP_DB_CNTL_BASE_IDX                                                                      2
#define regDP1_DP_MSA_VBID_MISC                                                                         0x2294
#define regDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
#define regDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x2295
#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
#define regDP1_DP_ALPM_CNTL                                                                             0x2297
#define regDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
#define regDP1_DP_GSP8_CNTL                                                                             0x2298
#define regDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2
#define regDP1_DP_GSP9_CNTL                                                                             0x2299
#define regDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2
#define regDP1_DP_GSP10_CNTL                                                                            0x229a
#define regDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2
#define regDP1_DP_GSP11_CNTL                                                                            0x229b
#define regDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2
#define regDP1_DP_GSP_EN_DB_STATUS                                                                      0x229c
#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
#define regDP1_DP_AUXLESS_ALPM_CNTL1                                                                    0x229d
#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
#define regDP1_DP_AUXLESS_ALPM_CNTL2                                                                    0x229e
#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
#define regDP1_DP_AUXLESS_ALPM_CNTL3                                                                    0x229f
#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
#define regDP1_DP_AUXLESS_ALPM_CNTL4                                                                    0x22a0
#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
#define regDP1_DP_AUXLESS_ALPM_CNTL5                                                                    0x22a1
#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x22a2
#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2
#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x22a3
#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2
#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x22a4
#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2
#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x22a5
#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2
#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x22a6
#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2


// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
// base address: 0x15dc0
#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x22b0
#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
#define regVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x22b1
#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x22b2
#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x22b3
#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
#define regVPG2_VPG_GENERIC_STATUS                                                                      0x22b4
#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2
#define regVPG2_VPG_MEM_PWR                                                                             0x22b5
#define regVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2
#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x22b6
#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
#define regVPG2_VPG_ISRC1_2_DATA                                                                        0x22b7
#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
#define regVPG2_VPG_MPEG_INFO0                                                                          0x22b8
#define regVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2
#define regVPG2_VPG_MPEG_INFO1                                                                          0x22b9
#define regVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2


// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
// base address: 0x15dec
#define regAFMT2_AFMT_ACP                                                                               0x22bb
#define regAFMT2_AFMT_ACP_BASE_IDX                                                                      2
#define regAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x22bc
#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x22bd
#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
#define regAFMT2_AFMT_AUDIO_INFO0                                                                       0x22be
#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
#define regAFMT2_AFMT_AUDIO_INFO1                                                                       0x22bf
#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
#define regAFMT2_AFMT_60958_0                                                                           0x22c0
#define regAFMT2_AFMT_60958_0_BASE_IDX                                                                  2
#define regAFMT2_AFMT_60958_1                                                                           0x22c1
#define regAFMT2_AFMT_60958_1_BASE_IDX                                                                  2
#define regAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x22c2
#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
#define regAFMT2_AFMT_RAMP_CONTROL0                                                                     0x22c3
#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
#define regAFMT2_AFMT_RAMP_CONTROL1                                                                     0x22c4
#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
#define regAFMT2_AFMT_RAMP_CONTROL2                                                                     0x22c5
#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
#define regAFMT2_AFMT_RAMP_CONTROL3                                                                     0x22c6
#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
#define regAFMT2_AFMT_60958_2                                                                           0x22c7
#define regAFMT2_AFMT_60958_2_BASE_IDX                                                                  2
#define regAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x22c8
#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
#define regAFMT2_AFMT_STATUS                                                                            0x22c9
#define regAFMT2_AFMT_STATUS_BASE_IDX                                                                   2
#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x22ca
#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
#define regAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x22cb
#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
#define regAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x22cc
#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
#define regAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x22cd
#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
#define regAFMT2_AFMT_MEM_PWR                                                                           0x22cf
#define regAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2


// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
// base address: 0x15e64
#define regDME2_DME_CONTROL                                                                             0x22d9
#define regDME2_DME_CONTROL_BASE_IDX                                                                    2
#define regDME2_DME_MEMORY_CONTROL                                                                      0x22da
#define regDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2


// addressBlock: dce_dc_dio_dig2_dispdec
// base address: 0x920
#define regDIG2_DIG_FE_CNTL                                                                             0x22db
#define regDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
#define regDIG2_DIG_FE_CLK_CNTL                                                                         0x22dc
#define regDIG2_DIG_FE_CLK_CNTL_BASE_IDX                                                                2
#define regDIG2_DIG_FE_EN_CNTL                                                                          0x22dd
#define regDIG2_DIG_FE_EN_CNTL_BASE_IDX                                                                 2
#define regDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x22de
#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
#define regDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x22df
#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
#define regDIG2_DIG_CLOCK_PATTERN                                                                       0x22e0
#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
#define regDIG2_DIG_TEST_PATTERN                                                                        0x22e1
#define regDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
#define regDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x22e2
#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
#define regDIG2_DIG_FIFO_CTRL0                                                                          0x22e3
#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
#define regDIG2_DIG_FIFO_CTRL1                                                                          0x22e4
#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
#define regDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x22e5
#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
#define regDIG2_HDMI_CONTROL                                                                            0x22e6
#define regDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
#define regDIG2_HDMI_STATUS                                                                             0x22e7
#define regDIG2_HDMI_STATUS_BASE_IDX                                                                    2
#define regDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x22e8
#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
#define regDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x22e9
#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
#define regDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x22ea
#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
#define regDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x22eb
#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
#define regDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x22ec
#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x22ed
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x22ee
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x22ef
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
#define regDIG2_HDMI_GC                                                                                 0x22f0
#define regDIG2_HDMI_GC_BASE_IDX                                                                        2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x22f1
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x22f2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22f3
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22f4
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22f5
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22f6
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22f7
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22f8
#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
#define regDIG2_HDMI_DB_CONTROL                                                                         0x22f9
#define regDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
#define regDIG2_HDMI_ACR_32_0                                                                           0x22fa
#define regDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
#define regDIG2_HDMI_ACR_32_1                                                                           0x22fb
#define regDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
#define regDIG2_HDMI_ACR_44_0                                                                           0x22fc
#define regDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
#define regDIG2_HDMI_ACR_44_1                                                                           0x22fd
#define regDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
#define regDIG2_HDMI_ACR_48_0                                                                           0x22fe
#define regDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
#define regDIG2_HDMI_ACR_48_1                                                                           0x22ff
#define regDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
#define regDIG2_HDMI_ACR_STATUS_0                                                                       0x2300
#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
#define regDIG2_HDMI_ACR_STATUS_1                                                                       0x2301
#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
#define regDIG2_AFMT_CNTL                                                                               0x2302
#define regDIG2_AFMT_CNTL_BASE_IDX                                                                      2
#define regDIG2_DIG_BE_CLK_CNTL                                                                         0x2303
#define regDIG2_DIG_BE_CLK_CNTL_BASE_IDX                                                                2
#define regDIG2_DIG_BE_CNTL                                                                             0x2304
#define regDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
#define regDIG2_DIG_BE_EN_CNTL                                                                          0x2305
#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
#define regDIG2_TMDS_CNTL                                                                               0x232c
#define regDIG2_TMDS_CNTL_BASE_IDX                                                                      2
#define regDIG2_TMDS_CONTROL_CHAR                                                                       0x232d
#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
#define regDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x232e
#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
#define regDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x232f
#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x2330
#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x2331
#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
#define regDIG2_TMDS_CTL_BITS                                                                           0x2333
#define regDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
#define regDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x2334
#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x2335
#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
#define regDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x2336
#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
#define regDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x2337
#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
#define regDIG2_DIG_VERSION                                                                             0x2339
#define regDIG2_DIG_VERSION_BASE_IDX                                                                    2


// addressBlock: dce_dc_dio_dp2_dispdec
// base address: 0x920
#define regDP2_DP_LINK_CNTL                                                                             0x2366
#define regDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
#define regDP2_DP_PIXEL_FORMAT                                                                          0x2367
#define regDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
#define regDP2_DP_MSA_COLORIMETRY                                                                       0x2368
#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
#define regDP2_DP_CONFIG                                                                                0x2369
#define regDP2_DP_CONFIG_BASE_IDX                                                                       2
#define regDP2_DP_VID_STREAM_CNTL                                                                       0x236a
#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
#define regDP2_DP_STEER_FIFO                                                                            0x236b
#define regDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
#define regDP2_DP_MSA_MISC                                                                              0x236c
#define regDP2_DP_MSA_MISC_BASE_IDX                                                                     2
#define regDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x236d
#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
#define regDP2_DP_VID_TIMING                                                                            0x236e
#define regDP2_DP_VID_TIMING_BASE_IDX                                                                   2
#define regDP2_DP_VID_N                                                                                 0x236f
#define regDP2_DP_VID_N_BASE_IDX                                                                        2
#define regDP2_DP_VID_M                                                                                 0x2370
#define regDP2_DP_VID_M_BASE_IDX                                                                        2
#define regDP2_DP_LINK_FRAMING_CNTL                                                                     0x2371
#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
#define regDP2_DP_HBR2_EYE_PATTERN                                                                      0x2372
#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
#define regDP2_DP_VID_MSA_VBID                                                                          0x2373
#define regDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
#define regDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2374
#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
#define regDP2_DP_DPHY_CNTL                                                                             0x2375
#define regDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2376
#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
#define regDP2_DP_DPHY_SYM0                                                                             0x2377
#define regDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
#define regDP2_DP_DPHY_SYM1                                                                             0x2378
#define regDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
#define regDP2_DP_DPHY_SYM2                                                                             0x2379
#define regDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
#define regDP2_DP_DPHY_8B10B_CNTL                                                                       0x237a
#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
#define regDP2_DP_DPHY_PRBS_CNTL                                                                        0x237b
#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
#define regDP2_DP_DPHY_SCRAM_CNTL                                                                       0x237c
#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
#define regDP2_DP_DPHY_CRC_EN                                                                           0x237d
#define regDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
#define regDP2_DP_DPHY_CRC_CNTL                                                                         0x237e
#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
#define regDP2_DP_DPHY_CRC_RESULT                                                                       0x237f
#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
#define regDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2380
#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
#define regDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2381
#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
#define regDP2_DP_DPHY_FAST_TRAINING                                                                    0x2382
#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
#define regDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2383
#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
#define regDP2_DP_SEC_CNTL                                                                              0x2389
#define regDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
#define regDP2_DP_SEC_CNTL1                                                                             0x238a
#define regDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
#define regDP2_DP_SEC_FRAMING1                                                                          0x238b
#define regDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
#define regDP2_DP_SEC_FRAMING2                                                                          0x238c
#define regDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
#define regDP2_DP_SEC_FRAMING3                                                                          0x238d
#define regDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
#define regDP2_DP_SEC_FRAMING4                                                                          0x238e
#define regDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
#define regDP2_DP_SEC_AUD_N                                                                             0x238f
#define regDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
#define regDP2_DP_SEC_AUD_N_READBACK                                                                    0x2390
#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
#define regDP2_DP_SEC_AUD_M                                                                             0x2391
#define regDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
#define regDP2_DP_SEC_AUD_M_READBACK                                                                    0x2392
#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
#define regDP2_DP_SEC_TIMESTAMP                                                                         0x2393
#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
#define regDP2_DP_SEC_PACKET_CNTL                                                                       0x2394
#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
#define regDP2_DP_MSE_RATE_CNTL                                                                         0x2395
#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
#define regDP2_DP_MSE_RATE_UPDATE                                                                       0x2397
#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
#define regDP2_DP_MSE_SAT0                                                                              0x2398
#define regDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
#define regDP2_DP_MSE_SAT1                                                                              0x2399
#define regDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
#define regDP2_DP_MSE_SAT2                                                                              0x239a
#define regDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
#define regDP2_DP_MSE_SAT_UPDATE                                                                        0x239b
#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
#define regDP2_DP_MSE_LINK_TIMING                                                                       0x239c
#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
#define regDP2_DP_MSE_MISC_CNTL                                                                         0x239d
#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x23a2
#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x23a3
#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
#define regDP2_DP_MSE_SAT0_STATUS                                                                       0x23a5
#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
#define regDP2_DP_MSE_SAT1_STATUS                                                                       0x23a6
#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
#define regDP2_DP_MSE_SAT2_STATUS                                                                       0x23a7
#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
#define regDP2_DP_DPIA_SPARE                                                                            0x23a8
#define regDP2_DP_DPIA_SPARE_BASE_IDX                                                                   2
#define regDP2_DP_MSA_TIMING_PARAM1                                                                     0x23aa
#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
#define regDP2_DP_MSA_TIMING_PARAM2                                                                     0x23ab
#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
#define regDP2_DP_MSA_TIMING_PARAM3                                                                     0x23ac
#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
#define regDP2_DP_MSA_TIMING_PARAM4                                                                     0x23ad
#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
#define regDP2_DP_MSO_CNTL                                                                              0x23ae
#define regDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
#define regDP2_DP_MSO_CNTL1                                                                             0x23af
#define regDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
#define regDP2_DP_DSC_CNTL                                                                              0x23b0
#define regDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
#define regDP2_DP_SEC_CNTL2                                                                             0x23b1
#define regDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
#define regDP2_DP_SEC_CNTL3                                                                             0x23b2
#define regDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
#define regDP2_DP_SEC_CNTL4                                                                             0x23b3
#define regDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
#define regDP2_DP_SEC_CNTL5                                                                             0x23b4
#define regDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
#define regDP2_DP_SEC_CNTL6                                                                             0x23b5
#define regDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
#define regDP2_DP_SEC_CNTL7                                                                             0x23b6
#define regDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
#define regDP2_DP_DB_CNTL                                                                               0x23b7
#define regDP2_DP_DB_CNTL_BASE_IDX                                                                      2
#define regDP2_DP_MSA_VBID_MISC                                                                         0x23b8
#define regDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
#define regDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x23b9
#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
#define regDP2_DP_ALPM_CNTL                                                                             0x23bb
#define regDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
#define regDP2_DP_GSP8_CNTL                                                                             0x23bc
#define regDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2
#define regDP2_DP_GSP9_CNTL                                                                             0x23bd
#define regDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2
#define regDP2_DP_GSP10_CNTL                                                                            0x23be
#define regDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2
#define regDP2_DP_GSP11_CNTL                                                                            0x23bf
#define regDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2
#define regDP2_DP_GSP_EN_DB_STATUS                                                                      0x23c0
#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
#define regDP2_DP_AUXLESS_ALPM_CNTL1                                                                    0x23c1
#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
#define regDP2_DP_AUXLESS_ALPM_CNTL2                                                                    0x23c2
#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
#define regDP2_DP_AUXLESS_ALPM_CNTL3                                                                    0x23c3
#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
#define regDP2_DP_AUXLESS_ALPM_CNTL4                                                                    0x23c4
#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
#define regDP2_DP_AUXLESS_ALPM_CNTL5                                                                    0x23c5
#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x23c6
#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2
#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x23c7
#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2
#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x23c8
#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2
#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x23c9
#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2
#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x23ca
#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2


// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
// base address: 0x16250
#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x23d4
#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
#define regVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x23d5
#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x23d6
#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x23d7
#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
#define regVPG3_VPG_GENERIC_STATUS                                                                      0x23d8
#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2
#define regVPG3_VPG_MEM_PWR                                                                             0x23d9
#define regVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2
#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x23da
#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
#define regVPG3_VPG_ISRC1_2_DATA                                                                        0x23db
#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
#define regVPG3_VPG_MPEG_INFO0                                                                          0x23dc
#define regVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2
#define regVPG3_VPG_MPEG_INFO1                                                                          0x23dd
#define regVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2


// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
// base address: 0x1627c
#define regAFMT3_AFMT_ACP                                                                               0x23df
#define regAFMT3_AFMT_ACP_BASE_IDX                                                                      2
#define regAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x23e0
#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x23e1
#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
#define regAFMT3_AFMT_AUDIO_INFO0                                                                       0x23e2
#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
#define regAFMT3_AFMT_AUDIO_INFO1                                                                       0x23e3
#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
#define regAFMT3_AFMT_60958_0                                                                           0x23e4
#define regAFMT3_AFMT_60958_0_BASE_IDX                                                                  2
#define regAFMT3_AFMT_60958_1                                                                           0x23e5
#define regAFMT3_AFMT_60958_1_BASE_IDX                                                                  2
#define regAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x23e6
#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
#define regAFMT3_AFMT_RAMP_CONTROL0                                                                     0x23e7
#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
#define regAFMT3_AFMT_RAMP_CONTROL1                                                                     0x23e8
#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
#define regAFMT3_AFMT_RAMP_CONTROL2                                                                     0x23e9
#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
#define regAFMT3_AFMT_RAMP_CONTROL3                                                                     0x23ea
#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
#define regAFMT3_AFMT_60958_2                                                                           0x23eb
#define regAFMT3_AFMT_60958_2_BASE_IDX                                                                  2
#define regAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x23ec
#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
#define regAFMT3_AFMT_STATUS                                                                            0x23ed
#define regAFMT3_AFMT_STATUS_BASE_IDX                                                                   2
#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x23ee
#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
#define regAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x23ef
#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
#define regAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x23f0
#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
#define regAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x23f1
#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
#define regAFMT3_AFMT_MEM_PWR                                                                           0x23f3
#define regAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2


// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
// base address: 0x162f4
#define regDME3_DME_CONTROL                                                                             0x23fd
#define regDME3_DME_CONTROL_BASE_IDX                                                                    2
#define regDME3_DME_MEMORY_CONTROL                                                                      0x23fe
#define regDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2


// addressBlock: dce_dc_dio_dig3_dispdec
// base address: 0xdb0
#define regDIG3_DIG_FE_CNTL                                                                             0x23ff
#define regDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
#define regDIG3_DIG_FE_CLK_CNTL                                                                         0x2400
#define regDIG3_DIG_FE_CLK_CNTL_BASE_IDX                                                                2
#define regDIG3_DIG_FE_EN_CNTL                                                                          0x2401
#define regDIG3_DIG_FE_EN_CNTL_BASE_IDX                                                                 2
#define regDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x2402
#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
#define regDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x2403
#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
#define regDIG3_DIG_CLOCK_PATTERN                                                                       0x2404
#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
#define regDIG3_DIG_TEST_PATTERN                                                                        0x2405
#define regDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
#define regDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2406
#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
#define regDIG3_DIG_FIFO_CTRL0                                                                          0x2407
#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
#define regDIG3_DIG_FIFO_CTRL1                                                                          0x2408
#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
#define regDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2409
#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
#define regDIG3_HDMI_CONTROL                                                                            0x240a
#define regDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
#define regDIG3_HDMI_STATUS                                                                             0x240b
#define regDIG3_HDMI_STATUS_BASE_IDX                                                                    2
#define regDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x240c
#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
#define regDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x240d
#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
#define regDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x240e
#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
#define regDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x240f
#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
#define regDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x2410
#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2411
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x2412
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x2413
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
#define regDIG3_HDMI_GC                                                                                 0x2414
#define regDIG3_HDMI_GC_BASE_IDX                                                                        2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2415
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2416
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2417
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2418
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x2419
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x241a
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x241b
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x241c
#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
#define regDIG3_HDMI_DB_CONTROL                                                                         0x241d
#define regDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
#define regDIG3_HDMI_ACR_32_0                                                                           0x241e
#define regDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
#define regDIG3_HDMI_ACR_32_1                                                                           0x241f
#define regDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
#define regDIG3_HDMI_ACR_44_0                                                                           0x2420
#define regDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
#define regDIG3_HDMI_ACR_44_1                                                                           0x2421
#define regDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
#define regDIG3_HDMI_ACR_48_0                                                                           0x2422
#define regDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
#define regDIG3_HDMI_ACR_48_1                                                                           0x2423
#define regDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
#define regDIG3_HDMI_ACR_STATUS_0                                                                       0x2424
#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
#define regDIG3_HDMI_ACR_STATUS_1                                                                       0x2425
#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
#define regDIG3_AFMT_CNTL                                                                               0x2426
#define regDIG3_AFMT_CNTL_BASE_IDX                                                                      2
#define regDIG3_DIG_BE_CLK_CNTL                                                                         0x2427
#define regDIG3_DIG_BE_CLK_CNTL_BASE_IDX                                                                2
#define regDIG3_DIG_BE_CNTL                                                                             0x2428
#define regDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
#define regDIG3_DIG_BE_EN_CNTL                                                                          0x2429
#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
#define regDIG3_TMDS_CNTL                                                                               0x2450
#define regDIG3_TMDS_CNTL_BASE_IDX                                                                      2
#define regDIG3_TMDS_CONTROL_CHAR                                                                       0x2451
#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
#define regDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x2452
#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
#define regDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x2453
#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x2454
#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x2455
#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
#define regDIG3_TMDS_CTL_BITS                                                                           0x2457
#define regDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
#define regDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x2458
#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x2459
#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
#define regDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x245a
#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
#define regDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x245b
#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
#define regDIG3_DIG_VERSION                                                                             0x245d
#define regDIG3_DIG_VERSION_BASE_IDX                                                                    2


// addressBlock: dce_dc_dio_dp3_dispdec
// base address: 0xdb0
#define regDP3_DP_LINK_CNTL                                                                             0x248a
#define regDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
#define regDP3_DP_PIXEL_FORMAT                                                                          0x248b
#define regDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
#define regDP3_DP_MSA_COLORIMETRY                                                                       0x248c
#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
#define regDP3_DP_CONFIG                                                                                0x248d
#define regDP3_DP_CONFIG_BASE_IDX                                                                       2
#define regDP3_DP_VID_STREAM_CNTL                                                                       0x248e
#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
#define regDP3_DP_STEER_FIFO                                                                            0x248f
#define regDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
#define regDP3_DP_MSA_MISC                                                                              0x2490
#define regDP3_DP_MSA_MISC_BASE_IDX                                                                     2
#define regDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x2491
#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
#define regDP3_DP_VID_TIMING                                                                            0x2492
#define regDP3_DP_VID_TIMING_BASE_IDX                                                                   2
#define regDP3_DP_VID_N                                                                                 0x2493
#define regDP3_DP_VID_N_BASE_IDX                                                                        2
#define regDP3_DP_VID_M                                                                                 0x2494
#define regDP3_DP_VID_M_BASE_IDX                                                                        2
#define regDP3_DP_LINK_FRAMING_CNTL                                                                     0x2495
#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
#define regDP3_DP_HBR2_EYE_PATTERN                                                                      0x2496
#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
#define regDP3_DP_VID_MSA_VBID                                                                          0x2497
#define regDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
#define regDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2498
#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
#define regDP3_DP_DPHY_CNTL                                                                             0x2499
#define regDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x249a
#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
#define regDP3_DP_DPHY_SYM0                                                                             0x249b
#define regDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
#define regDP3_DP_DPHY_SYM1                                                                             0x249c
#define regDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
#define regDP3_DP_DPHY_SYM2                                                                             0x249d
#define regDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
#define regDP3_DP_DPHY_8B10B_CNTL                                                                       0x249e
#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
#define regDP3_DP_DPHY_PRBS_CNTL                                                                        0x249f
#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
#define regDP3_DP_DPHY_SCRAM_CNTL                                                                       0x24a0
#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
#define regDP3_DP_DPHY_CRC_EN                                                                           0x24a1
#define regDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
#define regDP3_DP_DPHY_CRC_CNTL                                                                         0x24a2
#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
#define regDP3_DP_DPHY_CRC_RESULT                                                                       0x24a3
#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
#define regDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x24a4
#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
#define regDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x24a5
#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
#define regDP3_DP_DPHY_FAST_TRAINING                                                                    0x24a6
#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
#define regDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x24a7
#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
#define regDP3_DP_SEC_CNTL                                                                              0x24ad
#define regDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
#define regDP3_DP_SEC_CNTL1                                                                             0x24ae
#define regDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
#define regDP3_DP_SEC_FRAMING1                                                                          0x24af
#define regDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
#define regDP3_DP_SEC_FRAMING2                                                                          0x24b0
#define regDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
#define regDP3_DP_SEC_FRAMING3                                                                          0x24b1
#define regDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
#define regDP3_DP_SEC_FRAMING4                                                                          0x24b2
#define regDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
#define regDP3_DP_SEC_AUD_N                                                                             0x24b3
#define regDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
#define regDP3_DP_SEC_AUD_N_READBACK                                                                    0x24b4
#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
#define regDP3_DP_SEC_AUD_M                                                                             0x24b5
#define regDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
#define regDP3_DP_SEC_AUD_M_READBACK                                                                    0x24b6
#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
#define regDP3_DP_SEC_TIMESTAMP                                                                         0x24b7
#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
#define regDP3_DP_SEC_PACKET_CNTL                                                                       0x24b8
#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
#define regDP3_DP_MSE_RATE_CNTL                                                                         0x24b9
#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
#define regDP3_DP_MSE_RATE_UPDATE                                                                       0x24bb
#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
#define regDP3_DP_MSE_SAT0                                                                              0x24bc
#define regDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
#define regDP3_DP_MSE_SAT1                                                                              0x24bd
#define regDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
#define regDP3_DP_MSE_SAT2                                                                              0x24be
#define regDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
#define regDP3_DP_MSE_SAT_UPDATE                                                                        0x24bf
#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
#define regDP3_DP_MSE_LINK_TIMING                                                                       0x24c0
#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
#define regDP3_DP_MSE_MISC_CNTL                                                                         0x24c1
#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x24c6
#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x24c7
#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
#define regDP3_DP_MSE_SAT0_STATUS                                                                       0x24c9
#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
#define regDP3_DP_MSE_SAT1_STATUS                                                                       0x24ca
#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
#define regDP3_DP_MSE_SAT2_STATUS                                                                       0x24cb
#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
#define regDP3_DP_DPIA_SPARE                                                                            0x24cc
#define regDP3_DP_DPIA_SPARE_BASE_IDX                                                                   2
#define regDP3_DP_MSA_TIMING_PARAM1                                                                     0x24ce
#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
#define regDP3_DP_MSA_TIMING_PARAM2                                                                     0x24cf
#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
#define regDP3_DP_MSA_TIMING_PARAM3                                                                     0x24d0
#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
#define regDP3_DP_MSA_TIMING_PARAM4                                                                     0x24d1
#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
#define regDP3_DP_MSO_CNTL                                                                              0x24d2
#define regDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
#define regDP3_DP_MSO_CNTL1                                                                             0x24d3
#define regDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
#define regDP3_DP_DSC_CNTL                                                                              0x24d4
#define regDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
#define regDP3_DP_SEC_CNTL2                                                                             0x24d5
#define regDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
#define regDP3_DP_SEC_CNTL3                                                                             0x24d6
#define regDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
#define regDP3_DP_SEC_CNTL4                                                                             0x24d7
#define regDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
#define regDP3_DP_SEC_CNTL5                                                                             0x24d8
#define regDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
#define regDP3_DP_SEC_CNTL6                                                                             0x24d9
#define regDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
#define regDP3_DP_SEC_CNTL7                                                                             0x24da
#define regDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
#define regDP3_DP_DB_CNTL                                                                               0x24db
#define regDP3_DP_DB_CNTL_BASE_IDX                                                                      2
#define regDP3_DP_MSA_VBID_MISC                                                                         0x24dc
#define regDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
#define regDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x24dd
#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
#define regDP3_DP_ALPM_CNTL                                                                             0x24df
#define regDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
#define regDP3_DP_GSP8_CNTL                                                                             0x24e0
#define regDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2
#define regDP3_DP_GSP9_CNTL                                                                             0x24e1
#define regDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2
#define regDP3_DP_GSP10_CNTL                                                                            0x24e2
#define regDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2
#define regDP3_DP_GSP11_CNTL                                                                            0x24e3
#define regDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2
#define regDP3_DP_GSP_EN_DB_STATUS                                                                      0x24e4
#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
#define regDP3_DP_AUXLESS_ALPM_CNTL1                                                                    0x24e5
#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
#define regDP3_DP_AUXLESS_ALPM_CNTL2                                                                    0x24e6
#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
#define regDP3_DP_AUXLESS_ALPM_CNTL3                                                                    0x24e7
#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
#define regDP3_DP_AUXLESS_ALPM_CNTL4                                                                    0x24e8
#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
#define regDP3_DP_AUXLESS_ALPM_CNTL5                                                                    0x24e9
#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x24ea
#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2
#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x24eb
#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2
#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x24ec
#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2
#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x24ed
#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2
#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x24ee
#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2


// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec
// base address: 0x166e0
#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x24f8
#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
#define regVPG4_VPG_GENERIC_PACKET_DATA                                                                 0x24f9
#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x24fa
#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x24fb
#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
#define regVPG4_VPG_GENERIC_STATUS                                                                      0x24fc
#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX                                                             2
#define regVPG4_VPG_MEM_PWR                                                                             0x24fd
#define regVPG4_VPG_MEM_PWR_BASE_IDX                                                                    2
#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x24fe
#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
#define regVPG4_VPG_ISRC1_2_DATA                                                                        0x24ff
#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
#define regVPG4_VPG_MPEG_INFO0                                                                          0x2500
#define regVPG4_VPG_MPEG_INFO0_BASE_IDX                                                                 2
#define regVPG4_VPG_MPEG_INFO1                                                                          0x2501
#define regVPG4_VPG_MPEG_INFO1_BASE_IDX                                                                 2


// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec
// base address: 0x1670c
#define regAFMT4_AFMT_ACP                                                                               0x2503
#define regAFMT4_AFMT_ACP_BASE_IDX                                                                      2
#define regAFMT4_AFMT_VBI_PACKET_CONTROL                                                                0x2504
#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2505
#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
#define regAFMT4_AFMT_AUDIO_INFO0                                                                       0x2506
#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
#define regAFMT4_AFMT_AUDIO_INFO1                                                                       0x2507
#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
#define regAFMT4_AFMT_60958_0                                                                           0x2508
#define regAFMT4_AFMT_60958_0_BASE_IDX                                                                  2
#define regAFMT4_AFMT_60958_1                                                                           0x2509
#define regAFMT4_AFMT_60958_1_BASE_IDX                                                                  2
#define regAFMT4_AFMT_AUDIO_CRC_CONTROL                                                                 0x250a
#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
#define regAFMT4_AFMT_RAMP_CONTROL0                                                                     0x250b
#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
#define regAFMT4_AFMT_RAMP_CONTROL1                                                                     0x250c
#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
#define regAFMT4_AFMT_RAMP_CONTROL2                                                                     0x250d
#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
#define regAFMT4_AFMT_RAMP_CONTROL3                                                                     0x250e
#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
#define regAFMT4_AFMT_60958_2                                                                           0x250f
#define regAFMT4_AFMT_60958_2_BASE_IDX                                                                  2
#define regAFMT4_AFMT_AUDIO_CRC_RESULT                                                                  0x2510
#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
#define regAFMT4_AFMT_STATUS                                                                            0x2511
#define regAFMT4_AFMT_STATUS_BASE_IDX                                                                   2
#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL                                                              0x2512
#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
#define regAFMT4_AFMT_INFOFRAME_CONTROL0                                                                0x2513
#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
#define regAFMT4_AFMT_INTERRUPT_STATUS                                                                  0x2514
#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
#define regAFMT4_AFMT_AUDIO_SRC_CONTROL                                                                 0x2515
#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
#define regAFMT4_AFMT_MEM_PWR                                                                           0x2517
#define regAFMT4_AFMT_MEM_PWR_BASE_IDX                                                                  2


// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec
// base address: 0x16784
#define regDME4_DME_CONTROL                                                                             0x2521
#define regDME4_DME_CONTROL_BASE_IDX                                                                    2
#define regDME4_DME_MEMORY_CONTROL                                                                      0x2522
#define regDME4_DME_MEMORY_CONTROL_BASE_IDX                                                             2


// addressBlock: dce_dc_dio_dig4_dispdec
// base address: 0x1240
#define regDIG4_DIG_FE_CNTL                                                                             0x2523
#define regDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2
#define regDIG4_DIG_FE_CLK_CNTL                                                                         0x2524
#define regDIG4_DIG_FE_CLK_CNTL_BASE_IDX                                                                2
#define regDIG4_DIG_FE_EN_CNTL                                                                          0x2525
#define regDIG4_DIG_FE_EN_CNTL_BASE_IDX                                                                 2
#define regDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x2526
#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
#define regDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x2527
#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
#define regDIG4_DIG_CLOCK_PATTERN                                                                       0x2528
#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
#define regDIG4_DIG_TEST_PATTERN                                                                        0x2529
#define regDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2
#define regDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x252a
#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
#define regDIG4_DIG_FIFO_CTRL0                                                                          0x252b
#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
#define regDIG4_DIG_FIFO_CTRL1                                                                          0x252c
#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
#define regDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x252d
#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
#define regDIG4_HDMI_CONTROL                                                                            0x252e
#define regDIG4_HDMI_CONTROL_BASE_IDX                                                                   2
#define regDIG4_HDMI_STATUS                                                                             0x252f
#define regDIG4_HDMI_STATUS_BASE_IDX                                                                    2
#define regDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2530
#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
#define regDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2531
#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
#define regDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2532
#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
#define regDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2533
#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
#define regDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x2534
#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2535
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6                                                            0x2536
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x2537
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
#define regDIG4_HDMI_GC                                                                                 0x2538
#define regDIG4_HDMI_GC_BASE_IDX                                                                        2
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2539
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x253a
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x253b
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x253c
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7                                                            0x253d
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8                                                            0x253e
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9                                                            0x253f
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10                                                           0x2540
#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
#define regDIG4_HDMI_DB_CONTROL                                                                         0x2541
#define regDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2
#define regDIG4_HDMI_ACR_32_0                                                                           0x2542
#define regDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2
#define regDIG4_HDMI_ACR_32_1                                                                           0x2543
#define regDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2
#define regDIG4_HDMI_ACR_44_0                                                                           0x2544
#define regDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2
#define regDIG4_HDMI_ACR_44_1                                                                           0x2545
#define regDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2
#define regDIG4_HDMI_ACR_48_0                                                                           0x2546
#define regDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2
#define regDIG4_HDMI_ACR_48_1                                                                           0x2547
#define regDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2
#define regDIG4_HDMI_ACR_STATUS_0                                                                       0x2548
#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
#define regDIG4_HDMI_ACR_STATUS_1                                                                       0x2549
#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
#define regDIG4_AFMT_CNTL                                                                               0x254a
#define regDIG4_AFMT_CNTL_BASE_IDX                                                                      2
#define regDIG4_DIG_BE_CLK_CNTL                                                                         0x254b
#define regDIG4_DIG_BE_CLK_CNTL_BASE_IDX                                                                2
#define regDIG4_DIG_BE_CNTL                                                                             0x254c
#define regDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2
#define regDIG4_DIG_BE_EN_CNTL                                                                          0x254d
#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
#define regDIG4_TMDS_CNTL                                                                               0x2574
#define regDIG4_TMDS_CNTL_BASE_IDX                                                                      2
#define regDIG4_TMDS_CONTROL_CHAR                                                                       0x2575
#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
#define regDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x2576
#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
#define regDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x2577
#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x2578
#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x2579
#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
#define regDIG4_TMDS_CTL_BITS                                                                           0x257b
#define regDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2
#define regDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x257c
#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x257d
#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
#define regDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x257e
#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
#define regDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x257f
#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
#define regDIG4_DIG_VERSION                                                                             0x2581
#define regDIG4_DIG_VERSION_BASE_IDX                                                                    2


// addressBlock: dce_dc_dio_dp4_dispdec
// base address: 0x1240
#define regDP4_DP_LINK_CNTL                                                                             0x25ae
#define regDP4_DP_LINK_CNTL_BASE_IDX                                                                    2
#define regDP4_DP_PIXEL_FORMAT                                                                          0x25af
#define regDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
#define regDP4_DP_MSA_COLORIMETRY                                                                       0x25b0
#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
#define regDP4_DP_CONFIG                                                                                0x25b1
#define regDP4_DP_CONFIG_BASE_IDX                                                                       2
#define regDP4_DP_VID_STREAM_CNTL                                                                       0x25b2
#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
#define regDP4_DP_STEER_FIFO                                                                            0x25b3
#define regDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
#define regDP4_DP_MSA_MISC                                                                              0x25b4
#define regDP4_DP_MSA_MISC_BASE_IDX                                                                     2
#define regDP4_DP_DPHY_INTERNAL_CTRL                                                                    0x25b5
#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
#define regDP4_DP_VID_TIMING                                                                            0x25b6
#define regDP4_DP_VID_TIMING_BASE_IDX                                                                   2
#define regDP4_DP_VID_N                                                                                 0x25b7
#define regDP4_DP_VID_N_BASE_IDX                                                                        2
#define regDP4_DP_VID_M                                                                                 0x25b8
#define regDP4_DP_VID_M_BASE_IDX                                                                        2
#define regDP4_DP_LINK_FRAMING_CNTL                                                                     0x25b9
#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
#define regDP4_DP_HBR2_EYE_PATTERN                                                                      0x25ba
#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
#define regDP4_DP_VID_MSA_VBID                                                                          0x25bb
#define regDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2
#define regDP4_DP_VID_INTERRUPT_CNTL                                                                    0x25bc
#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
#define regDP4_DP_DPHY_CNTL                                                                             0x25bd
#define regDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2
#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x25be
#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
#define regDP4_DP_DPHY_SYM0                                                                             0x25bf
#define regDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2
#define regDP4_DP_DPHY_SYM1                                                                             0x25c0
#define regDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2
#define regDP4_DP_DPHY_SYM2                                                                             0x25c1
#define regDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2
#define regDP4_DP_DPHY_8B10B_CNTL                                                                       0x25c2
#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
#define regDP4_DP_DPHY_PRBS_CNTL                                                                        0x25c3
#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
#define regDP4_DP_DPHY_SCRAM_CNTL                                                                       0x25c4
#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
#define regDP4_DP_DPHY_CRC_EN                                                                           0x25c5
#define regDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
#define regDP4_DP_DPHY_CRC_CNTL                                                                         0x25c6
#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
#define regDP4_DP_DPHY_CRC_RESULT                                                                       0x25c7
#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
#define regDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x25c8
#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
#define regDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x25c9
#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
#define regDP4_DP_DPHY_FAST_TRAINING                                                                    0x25ca
#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
#define regDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x25cb
#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
#define regDP4_DP_SEC_CNTL                                                                              0x25d1
#define regDP4_DP_SEC_CNTL_BASE_IDX                                                                     2
#define regDP4_DP_SEC_CNTL1                                                                             0x25d2
#define regDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2
#define regDP4_DP_SEC_FRAMING1                                                                          0x25d3
#define regDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2
#define regDP4_DP_SEC_FRAMING2                                                                          0x25d4
#define regDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2
#define regDP4_DP_SEC_FRAMING3                                                                          0x25d5
#define regDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2
#define regDP4_DP_SEC_FRAMING4                                                                          0x25d6
#define regDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2
#define regDP4_DP_SEC_AUD_N                                                                             0x25d7
#define regDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2
#define regDP4_DP_SEC_AUD_N_READBACK                                                                    0x25d8
#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
#define regDP4_DP_SEC_AUD_M                                                                             0x25d9
#define regDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2
#define regDP4_DP_SEC_AUD_M_READBACK                                                                    0x25da
#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
#define regDP4_DP_SEC_TIMESTAMP                                                                         0x25db
#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
#define regDP4_DP_SEC_PACKET_CNTL                                                                       0x25dc
#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
#define regDP4_DP_MSE_RATE_CNTL                                                                         0x25dd
#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
#define regDP4_DP_MSE_RATE_UPDATE                                                                       0x25df
#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
#define regDP4_DP_MSE_SAT0                                                                              0x25e0
#define regDP4_DP_MSE_SAT0_BASE_IDX                                                                     2
#define regDP4_DP_MSE_SAT1                                                                              0x25e1
#define regDP4_DP_MSE_SAT1_BASE_IDX                                                                     2
#define regDP4_DP_MSE_SAT2                                                                              0x25e2
#define regDP4_DP_MSE_SAT2_BASE_IDX                                                                     2
#define regDP4_DP_MSE_SAT_UPDATE                                                                        0x25e3
#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
#define regDP4_DP_MSE_LINK_TIMING                                                                       0x25e4
#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
#define regDP4_DP_MSE_MISC_CNTL                                                                         0x25e5
#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x25ea
#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x25eb
#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
#define regDP4_DP_MSE_SAT0_STATUS                                                                       0x25ed
#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
#define regDP4_DP_MSE_SAT1_STATUS                                                                       0x25ee
#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
#define regDP4_DP_MSE_SAT2_STATUS                                                                       0x25ef
#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
#define regDP4_DP_DPIA_SPARE                                                                            0x25f0
#define regDP4_DP_DPIA_SPARE_BASE_IDX                                                                   2
#define regDP4_DP_MSA_TIMING_PARAM1                                                                     0x25f2
#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
#define regDP4_DP_MSA_TIMING_PARAM2                                                                     0x25f3
#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
#define regDP4_DP_MSA_TIMING_PARAM3                                                                     0x25f4
#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
#define regDP4_DP_MSA_TIMING_PARAM4                                                                     0x25f5
#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
#define regDP4_DP_MSO_CNTL                                                                              0x25f6
#define regDP4_DP_MSO_CNTL_BASE_IDX                                                                     2
#define regDP4_DP_MSO_CNTL1                                                                             0x25f7
#define regDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2
#define regDP4_DP_DSC_CNTL                                                                              0x25f8
#define regDP4_DP_DSC_CNTL_BASE_IDX                                                                     2
#define regDP4_DP_SEC_CNTL2                                                                             0x25f9
#define regDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2
#define regDP4_DP_SEC_CNTL3                                                                             0x25fa
#define regDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2
#define regDP4_DP_SEC_CNTL4                                                                             0x25fb
#define regDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2
#define regDP4_DP_SEC_CNTL5                                                                             0x25fc
#define regDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2
#define regDP4_DP_SEC_CNTL6                                                                             0x25fd
#define regDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2
#define regDP4_DP_SEC_CNTL7                                                                             0x25fe
#define regDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2
#define regDP4_DP_DB_CNTL                                                                               0x25ff
#define regDP4_DP_DB_CNTL_BASE_IDX                                                                      2
#define regDP4_DP_MSA_VBID_MISC                                                                         0x2600
#define regDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2
#define regDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x2601
#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
#define regDP4_DP_ALPM_CNTL                                                                             0x2603
#define regDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2
#define regDP4_DP_GSP8_CNTL                                                                             0x2604
#define regDP4_DP_GSP8_CNTL_BASE_IDX                                                                    2
#define regDP4_DP_GSP9_CNTL                                                                             0x2605
#define regDP4_DP_GSP9_CNTL_BASE_IDX                                                                    2
#define regDP4_DP_GSP10_CNTL                                                                            0x2606
#define regDP4_DP_GSP10_CNTL_BASE_IDX                                                                   2
#define regDP4_DP_GSP11_CNTL                                                                            0x2607
#define regDP4_DP_GSP11_CNTL_BASE_IDX                                                                   2
#define regDP4_DP_GSP_EN_DB_STATUS                                                                      0x2608
#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
#define regDP4_DP_AUXLESS_ALPM_CNTL1                                                                    0x2609
#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
#define regDP4_DP_AUXLESS_ALPM_CNTL2                                                                    0x260a
#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
#define regDP4_DP_AUXLESS_ALPM_CNTL3                                                                    0x260b
#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
#define regDP4_DP_AUXLESS_ALPM_CNTL4                                                                    0x260c
#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
#define regDP4_DP_AUXLESS_ALPM_CNTL5                                                                    0x260d
#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
#define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x260e
#define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2
#define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x260f
#define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2
#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x2610
#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2
#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x2611
#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2
#define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x2612
#define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2


// addressBlock: dce_dc_dcio_dcio_dispdec
// base address: 0x0
#define regDC_GENERICA                                                                                  0x2868
#define regDC_GENERICA_BASE_IDX                                                                         2
#define regDC_GENERICB                                                                                  0x2869
#define regDC_GENERICB_BASE_IDX                                                                         2
#define regDCIO_CLOCK_CNTL                                                                              0x286a
#define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
#define regDC_REF_CLK_CNTL                                                                              0x286b
#define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2
#define regUNIPHYA_LINK_CNTL                                                                            0x286d
#define regUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
#define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
#define regUNIPHYB_LINK_CNTL                                                                            0x286f
#define regUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
#define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
#define regUNIPHYC_LINK_CNTL                                                                            0x2871
#define regUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
#define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
#define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
#define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
#define regDCIO_WRCMD_DELAY                                                                             0x287e
#define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
#define regDC_PINSTRAPS                                                                                 0x2880
#define regDC_PINSTRAPS_BASE_IDX                                                                        2
#define regDCIO_SPARE                                                                                   0x2882
#define regDCIO_SPARE_BASE_IDX                                                                          2
#define regINTERCEPT_STATE                                                                              0x2884
#define regINTERCEPT_STATE_BASE_IDX                                                                     2
#define regDCIO_PATTERN_GEN_PAT                                                                         0x2886
#define regDCIO_PATTERN_GEN_PAT_BASE_IDX                                                                2
#define regDCIO_PATTERN_GEN_EN                                                                          0x2887
#define regDCIO_PATTERN_GEN_EN_BASE_IDX                                                                 2
#define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b
#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2
#define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
#define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
#define regDCIO_SOFT_RESET                                                                              0x289e
#define regDCIO_SOFT_RESET_BASE_IDX                                                                     2


// addressBlock: dce_dc_dcio_dcio_chip_dispdec
// base address: 0x0
#define regDC_GPIO_GENERIC_MASK                                                                         0x28c8
#define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
#define regDC_GPIO_GENERIC_A                                                                            0x28c9
#define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
#define regDC_GPIO_GENERIC_EN                                                                           0x28ca
#define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
#define regDC_GPIO_GENERIC_Y                                                                            0x28cb
#define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
#define regDC_GPIO_DDC1_MASK                                                                            0x28d0
#define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
#define regDC_GPIO_DDC1_A                                                                               0x28d1
#define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2
#define regDC_GPIO_DDC1_EN                                                                              0x28d2
#define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
#define regDC_GPIO_DDC1_Y                                                                               0x28d3
#define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
#define regDC_GPIO_DDC2_MASK                                                                            0x28d4
#define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
#define regDC_GPIO_DDC2_A                                                                               0x28d5
#define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2
#define regDC_GPIO_DDC2_EN                                                                              0x28d6
#define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
#define regDC_GPIO_DDC2_Y                                                                               0x28d7
#define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
#define regDC_GPIO_DDC3_MASK                                                                            0x28d8
#define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
#define regDC_GPIO_DDC3_A                                                                               0x28d9
#define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2
#define regDC_GPIO_DDC3_EN                                                                              0x28da
#define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
#define regDC_GPIO_DDC3_Y                                                                               0x28db
#define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
#define regDC_GPIO_DDC4_MASK                                                                            0x28dc
#define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
#define regDC_GPIO_DDC4_A                                                                               0x28dd
#define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2
#define regDC_GPIO_DDC4_EN                                                                              0x28de
#define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
#define regDC_GPIO_DDC4_Y                                                                               0x28df
#define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
#define regDC_GPIO_DDC5_MASK                                                                            0x28e0
#define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
#define regDC_GPIO_DDC5_A                                                                               0x28e1
#define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2
#define regDC_GPIO_DDC5_EN                                                                              0x28e2
#define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
#define regDC_GPIO_DDC5_Y                                                                               0x28e3
#define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
#define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8
#define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
#define regDC_GPIO_DDCVGA_A                                                                             0x28e9
#define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
#define regDC_GPIO_DDCVGA_EN                                                                            0x28ea
#define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
#define regDC_GPIO_DDCVGA_Y                                                                             0x28eb
#define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
#define regDC_GPIO_GENLK_MASK                                                                           0x28f0
#define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
#define regDC_GPIO_GENLK_A                                                                              0x28f1
#define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2
#define regDC_GPIO_GENLK_EN                                                                             0x28f2
#define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
#define regDC_GPIO_GENLK_Y                                                                              0x28f3
#define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
#define regDC_GPIO_HPD_MASK                                                                             0x28f4
#define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
#define regDC_GPIO_HPD_A                                                                                0x28f5
#define regDC_GPIO_HPD_A_BASE_IDX                                                                       2
#define regDC_GPIO_HPD_EN                                                                               0x28f6
#define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2
#define regDC_GPIO_HPD_Y                                                                                0x28f7
#define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2
#define regDC_GPIO_DRIVE_STRENGTH_S0                                                                    0x28f8
#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX                                                           2
#define regDC_GPIO_DRIVE_STRENGTH_S1                                                                    0x28f9
#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX                                                           2
#define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa
#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2
#define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
#define regDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
#define regPHY_AUX_CNTL                                                                                 0x28ff
#define regPHY_AUX_CNTL_BASE_IDX                                                                        2
#define regDC_GPIO_DRIVE_TXIMPSEL                                                                       0x2900
#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX                                                              2
#define regDC_GPIO_PWRSEQ1_EN                                                                           0x2902
#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX                                                                  2
#define regDC_GPIO_TX12_EN                                                                              0x2915
#define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2
#define regDC_GPIO_AUX_CTRL_0                                                                           0x2916
#define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
#define regDC_GPIO_AUX_CTRL_1                                                                           0x2917
#define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
#define regDC_GPIO_AUX_CTRL_2                                                                           0x2918
#define regDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
#define regDC_GPIO_RXEN                                                                                 0x2919
#define regDC_GPIO_RXEN_BASE_IDX                                                                        2
#define regDC_GPIO_PULLUPEN                                                                             0x291a
#define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
#define regDC_GPIO_AUX_CTRL_3                                                                           0x291b
#define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
#define regDC_GPIO_AUX_CTRL_4                                                                           0x291c
#define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
#define regDC_GPIO_AUX_CTRL_5                                                                           0x291d
#define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
#define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2


// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
// base address: 0x0


// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
// base address: 0x360
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39
#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2


// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
// base address: 0x6c0
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11
#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2


// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
// base address: 0xa20
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9
#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2


// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec
// base address: 0xd80
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2c88
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2c89
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2c8a
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2c8b
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2c8c
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2c8d
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2c8e
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2c8f
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2c90
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2c91
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2c92
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2c93
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2c94
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2c95
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2c96
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2c97
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2c98
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2c99
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2c9a
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2c9b
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2c9c
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2c9d
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2c9e
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2c9f
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2ca0
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2ca1
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2ca2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2ca3
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2ca4
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2ca5
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2ca6
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2ca7
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2ca8
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2ca9
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2caa
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2cab
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2cac
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2cad
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2cae
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2caf
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2cb0
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2cb1
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2cb2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2cb3
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2cb4
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2cb5
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2cb6
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2cb7
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2cb8
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2cb9
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2cba
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2cbb
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2cbc
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2cbd
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2cbe
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2cbf
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2cc0
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2cc1
#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2


// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec
// base address: 0x0
#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN                                                                    0x2f10
#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2
#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f11
#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2
#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK                                                                  0x2f12
#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2
#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f13
#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2
#define regPWRSEQ0_PANEL_PWRSEQ_CNTL                                                                    0x2f14
#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2
#define regPWRSEQ0_PANEL_PWRSEQ_STATE                                                                   0x2f15
#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2
#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1                                                                  0x2f16
#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2
#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2                                                                  0x2f17
#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2
#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1                                                                0x2f18
#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2
#define regPWRSEQ0_BL_PWM_CNTL                                                                          0x2f19
#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX                                                                 2
#define regPWRSEQ0_BL_PWM_CNTL2                                                                         0x2f1a
#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX                                                                2
#define regPWRSEQ0_BL_PWM_PERIOD_CNTL                                                                   0x2f1b
#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2
#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK                                                                 0x2f1c
#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2
#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2                                                                0x2f1d
#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2
#define regPWRSEQ0_PWRSEQ_SPARE                                                                         0x2f21
#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX                                                                2


// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec
// base address: 0x1b0
#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN                                                                    0x2f7c
#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2
#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f7d
#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2
#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK                                                                  0x2f7e
#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2
#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f7f
#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2
#define regPWRSEQ1_PANEL_PWRSEQ_CNTL                                                                    0x2f80
#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2
#define regPWRSEQ1_PANEL_PWRSEQ_STATE                                                                   0x2f81
#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2
#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1                                                                  0x2f82
#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2
#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2                                                                  0x2f83
#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2
#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1                                                                0x2f84
#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2
#define regPWRSEQ1_BL_PWM_CNTL                                                                          0x2f85
#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX                                                                 2
#define regPWRSEQ1_BL_PWM_CNTL2                                                                         0x2f86
#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX                                                                2
#define regPWRSEQ1_BL_PWM_PERIOD_CNTL                                                                   0x2f87
#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2
#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK                                                                 0x2f88
#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2
#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2                                                                0x2f89
#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2
#define regPWRSEQ1_PWRSEQ_SPARE                                                                         0x2f8d
#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX                                                                2


// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
// base address: 0x0
#define regDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
#define regDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2


// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
// base address: 0x0
#define regDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
#define regDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2


// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
// base address: 0x0
#define regDSCC0_DSCC_CONFIG0                                                                           0x300a
#define regDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
#define regDSCC0_DSCC_CONFIG1                                                                           0x300b
#define regDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
#define regDSCC0_DSCC_STATUS                                                                            0x300c
#define regDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
#define regDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
#define regDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
#define regDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
#define regDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
#define regDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
#define regDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
#define regDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
#define regDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
#define regDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
#define regDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
#define regDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
#define regDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
#define regDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
#define regDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
#define regDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
#define regDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
#define regDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
#define regDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
#define regDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
#define regDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
#define regDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
#define regDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
#define regDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
#define regDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
#define regDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
#define regDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a
#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2


// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
// base address: 0xc140
#define regDC_PERFMON19_PERFCOUNTER_CNTL                                                                0x3050
#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX                                                       2
#define regDC_PERFMON19_PERFCOUNTER_CNTL2                                                               0x3051
#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
#define regDC_PERFMON19_PERFCOUNTER_STATE                                                               0x3052
#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX                                                      2
#define regDC_PERFMON19_PERFMON_CNTL                                                                    0x3053
#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX                                                           2
#define regDC_PERFMON19_PERFMON_CNTL2                                                                   0x3054
#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX                                                          2
#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC                                                         0x3055
#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
#define regDC_PERFMON19_PERFMON_CVALUE_LOW                                                              0x3056
#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
#define regDC_PERFMON19_PERFMON_HI                                                                      0x3057
#define regDC_PERFMON19_PERFMON_HI_BASE_IDX                                                             2
#define regDC_PERFMON19_PERFMON_LOW                                                                     0x3058
#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX                                                            2


// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
// base address: 0x170
#define regDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
#define regDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2

// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
// base address: 0x170
#define regDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
#define regDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2


// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
// base address: 0x170
#define regDSCC1_DSCC_CONFIG0                                                                           0x3066
#define regDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
#define regDSCC1_DSCC_CONFIG1                                                                           0x3067
#define regDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
#define regDSCC1_DSCC_STATUS                                                                            0x3068
#define regDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
#define regDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
#define regDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
#define regDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
#define regDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
#define regDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
#define regDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
#define regDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
#define regDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
#define regDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
#define regDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
#define regDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
#define regDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
#define regDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
#define regDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
#define regDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
#define regDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
#define regDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
#define regDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
#define regDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
#define regDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
#define regDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
#define regDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
#define regDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
#define regDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
#define regDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
#define regDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096
#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2


// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
// base address: 0xc2b0
#define regDC_PERFMON20_PERFCOUNTER_CNTL                                                                0x30ac
#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX                                                       2
#define regDC_PERFMON20_PERFCOUNTER_CNTL2                                                               0x30ad
#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
#define regDC_PERFMON20_PERFCOUNTER_STATE                                                               0x30ae
#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX                                                      2
#define regDC_PERFMON20_PERFMON_CNTL                                                                    0x30af
#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX                                                           2
#define regDC_PERFMON20_PERFMON_CNTL2                                                                   0x30b0
#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX                                                          2
#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC                                                         0x30b1
#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
#define regDC_PERFMON20_PERFMON_CVALUE_LOW                                                              0x30b2
#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
#define regDC_PERFMON20_PERFMON_HI                                                                      0x30b3
#define regDC_PERFMON20_PERFMON_HI_BASE_IDX                                                             2
#define regDC_PERFMON20_PERFMON_LOW                                                                     0x30b4
#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX                                                            2


// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
// base address: 0x2e0
#define regDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
#define regDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2


// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
// base address: 0x2e0
#define regDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
#define regDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2


// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
// base address: 0x2e0
#define regDSCC2_DSCC_CONFIG0                                                                           0x30c2
#define regDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
#define regDSCC2_DSCC_CONFIG1                                                                           0x30c3
#define regDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
#define regDSCC2_DSCC_STATUS                                                                            0x30c4
#define regDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
#define regDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
#define regDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
#define regDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
#define regDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
#define regDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
#define regDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
#define regDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
#define regDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
#define regDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
#define regDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
#define regDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
#define regDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
#define regDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
#define regDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
#define regDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
#define regDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
#define regDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
#define regDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
#define regDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
#define regDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
#define regDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
#define regDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
#define regDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
#define regDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
#define regDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
#define regDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2
#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2


// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
// base address: 0xc420
#define regDC_PERFMON21_PERFCOUNTER_CNTL                                                                0x3108
#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX                                                       2
#define regDC_PERFMON21_PERFCOUNTER_CNTL2                                                               0x3109
#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
#define regDC_PERFMON21_PERFCOUNTER_STATE                                                               0x310a
#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX                                                      2
#define regDC_PERFMON21_PERFMON_CNTL                                                                    0x310b
#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX                                                           2
#define regDC_PERFMON21_PERFMON_CNTL2                                                                   0x310c
#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX                                                          2
#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC                                                         0x310d
#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
#define regDC_PERFMON21_PERFMON_CVALUE_LOW                                                              0x310e
#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
#define regDC_PERFMON21_PERFMON_HI                                                                      0x310f
#define regDC_PERFMON21_PERFMON_HI_BASE_IDX                                                             2
#define regDC_PERFMON21_PERFMON_LOW                                                                     0x3110
#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX                                                            2


// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
// base address: 0x450
#define regDSC_TOP3_DSC_TOP_CONTROL                                                                     0x3114
#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX                                                            2
#define regDSC_TOP3_DSC_DEBUG_CONTROL                                                                   0x3115
#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX                                                          2


// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
// base address: 0x450
#define regDSCCIF3_DSCCIF_CONFIG0                                                                       0x3119
#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX                                                              2
#define regDSCCIF3_DSCCIF_CONFIG1                                                                       0x311a
#define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX                                                              2


// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
// base address: 0x450
#define regDSCC3_DSCC_CONFIG0                                                                           0x311e
#define regDSCC3_DSCC_CONFIG0_BASE_IDX                                                                  2
#define regDSCC3_DSCC_CONFIG1                                                                           0x311f
#define regDSCC3_DSCC_CONFIG1_BASE_IDX                                                                  2
#define regDSCC3_DSCC_STATUS                                                                            0x3120
#define regDSCC3_DSCC_STATUS_BASE_IDX                                                                   2
#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121
#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
#define regDSCC3_DSCC_PPS_CONFIG0                                                                       0x3122
#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
#define regDSCC3_DSCC_PPS_CONFIG1                                                                       0x3123
#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
#define regDSCC3_DSCC_PPS_CONFIG2                                                                       0x3124
#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
#define regDSCC3_DSCC_PPS_CONFIG3                                                                       0x3125
#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
#define regDSCC3_DSCC_PPS_CONFIG4                                                                       0x3126
#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
#define regDSCC3_DSCC_PPS_CONFIG5                                                                       0x3127
#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
#define regDSCC3_DSCC_PPS_CONFIG6                                                                       0x3128
#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
#define regDSCC3_DSCC_PPS_CONFIG7                                                                       0x3129
#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
#define regDSCC3_DSCC_PPS_CONFIG8                                                                       0x312a
#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
#define regDSCC3_DSCC_PPS_CONFIG9                                                                       0x312b
#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
#define regDSCC3_DSCC_PPS_CONFIG10                                                                      0x312c
#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
#define regDSCC3_DSCC_PPS_CONFIG11                                                                      0x312d
#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
#define regDSCC3_DSCC_PPS_CONFIG12                                                                      0x312e
#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
#define regDSCC3_DSCC_PPS_CONFIG13                                                                      0x312f
#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
#define regDSCC3_DSCC_PPS_CONFIG14                                                                      0x3130
#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
#define regDSCC3_DSCC_PPS_CONFIG15                                                                      0x3131
#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
#define regDSCC3_DSCC_PPS_CONFIG16                                                                      0x3132
#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
#define regDSCC3_DSCC_PPS_CONFIG17                                                                      0x3133
#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
#define regDSCC3_DSCC_PPS_CONFIG18                                                                      0x3134
#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
#define regDSCC3_DSCC_PPS_CONFIG19                                                                      0x3135
#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
#define regDSCC3_DSCC_PPS_CONFIG20                                                                      0x3136
#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
#define regDSCC3_DSCC_PPS_CONFIG21                                                                      0x3137
#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
#define regDSCC3_DSCC_PPS_CONFIG22                                                                      0x3138
#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
#define regDSCC3_DSCC_MEM_POWER_CONTROL                                                                 0x3139
#define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x313a
#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x313b
#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x313c
#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x313d
#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x313e
#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x313f
#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
#define regDSCC3_DSCC_MAX_ABS_ERROR0                                                                    0x3140
#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
#define regDSCC3_DSCC_MAX_ABS_ERROR1                                                                    0x3141
#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x3142
#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x3143
#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3144
#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3145
#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3146
#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3147
#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3148
#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149
#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x314e
#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2


// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
// base address: 0xc590
#define regDC_PERFMON22_PERFCOUNTER_CNTL                                                                0x3164
#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX                                                       2
#define regDC_PERFMON22_PERFCOUNTER_CNTL2                                                               0x3165
#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
#define regDC_PERFMON22_PERFCOUNTER_STATE                                                               0x3166
#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX                                                      2
#define regDC_PERFMON22_PERFMON_CNTL                                                                    0x3167
#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX                                                           2
#define regDC_PERFMON22_PERFMON_CNTL2                                                                   0x3168
#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX                                                          2
#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC                                                         0x3169
#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
#define regDC_PERFMON22_PERFMON_CVALUE_LOW                                                              0x316a
#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
#define regDC_PERFMON22_PERFMON_HI                                                                      0x316b
#define regDC_PERFMON22_PERFMON_HI_BASE_IDX                                                             2
#define regDC_PERFMON22_PERFMON_LOW                                                                     0x316c
#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX                                                            2


// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
// base address: 0x0
#define regDWB_ENABLE_CLK_CTRL                                                                          0x3228
#define regDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2
#define regDWB_MEM_PWR_CTRL                                                                             0x3229
#define regDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2
#define regFC_MODE_CTRL                                                                                 0x322a
#define regFC_MODE_CTRL_BASE_IDX                                                                        2
#define regFC_FLOW_CTRL                                                                                 0x322b
#define regFC_FLOW_CTRL_BASE_IDX                                                                        2
#define regFC_WINDOW_START                                                                              0x322c
#define regFC_WINDOW_START_BASE_IDX                                                                     2
#define regFC_WINDOW_SIZE                                                                               0x322d
#define regFC_WINDOW_SIZE_BASE_IDX                                                                      2
#define regFC_SOURCE_SIZE                                                                               0x322e
#define regFC_SOURCE_SIZE_BASE_IDX                                                                      2
#define regDWB_UPDATE_CTRL                                                                              0x322f
#define regDWB_UPDATE_CTRL_BASE_IDX                                                                     2
#define regDWB_CRC_CTRL                                                                                 0x3230
#define regDWB_CRC_CTRL_BASE_IDX                                                                        2
#define regDWB_CRC_MASK_R_G                                                                             0x3231
#define regDWB_CRC_MASK_R_G_BASE_IDX                                                                    2
#define regDWB_CRC_MASK_B_A                                                                             0x3232
#define regDWB_CRC_MASK_B_A_BASE_IDX                                                                    2
#define regDWB_CRC_VAL_R_G                                                                              0x3233
#define regDWB_CRC_VAL_R_G_BASE_IDX                                                                     2
#define regDWB_CRC_VAL_B_A                                                                              0x3234
#define regDWB_CRC_VAL_B_A_BASE_IDX                                                                     2
#define regDWB_OUT_CTRL                                                                                 0x3235
#define regDWB_OUT_CTRL_BASE_IDX                                                                        2
#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236
#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2
#define regDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237
#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2
#define regDWB_HOST_READ_CONTROL                                                                        0x3238
#define regDWB_HOST_READ_CONTROL_BASE_IDX                                                               2
#define regDWB_OVERFLOW_STATUS                                                                          0x3239
#define regDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2
#define regDWB_OVERFLOW_COUNTER                                                                         0x323a
#define regDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2
#define regDWB_SOFT_RESET                                                                               0x323b
#define regDWB_SOFT_RESET_BASE_IDX                                                                      2


// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
// base address: 0xca20
#define regDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x3288
#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2
#define regDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x3289
#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
#define regDC_PERFMON3_PERFCOUNTER_STATE                                                                0x328a
#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2
#define regDC_PERFMON3_PERFMON_CNTL                                                                     0x328b
#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2
#define regDC_PERFMON3_PERFMON_CNTL2                                                                    0x328c
#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2
#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x328d
#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
#define regDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x328e
#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
#define regDC_PERFMON3_PERFMON_HI                                                                       0x328f
#define regDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2
#define regDC_PERFMON3_PERFMON_LOW                                                                      0x3290
#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2


// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
// base address: 0x0
#define regDWB_HDR_MULT_COEF                                                                            0x3294
#define regDWB_HDR_MULT_COEF_BASE_IDX                                                                   2
#define regDWB_GAMUT_REMAP_MODE                                                                         0x3295
#define regDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2
#define regDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296
#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2
#define regDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297
#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298
#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299
#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a
#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b
#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c
#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d
#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e
#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f
#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0
#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1
#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2
#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2
#define regDWB_OGAM_CONTROL                                                                             0x32a3
#define regDWB_OGAM_CONTROL_BASE_IDX                                                                    2
#define regDWB_OGAM_LUT_INDEX                                                                           0x32a4
#define regDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2
#define regDWB_OGAM_LUT_DATA                                                                            0x32a5
#define regDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2
#define regDWB_OGAM_LUT_CONTROL                                                                         0x32a6
#define regDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2
#define regDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7
#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8
#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9
#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa
#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2
#define regDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac
#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2
#define regDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae
#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2
#define regDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0
#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2
#define regDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1
#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2
#define regDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2
#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2
#define regDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3
#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2
#define regDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4
#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2
#define regDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5
#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2
#define regDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6
#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2
#define regDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7
#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2
#define regDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8
#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2
#define regDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9
#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2
#define regDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba
#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2
#define regDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb
#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2
#define regDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc
#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2
#define regDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd
#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2
#define regDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be
#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf
#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0
#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1
#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2
#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3
#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4
#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5
#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6
#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7
#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8
#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9
#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca
#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb
#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc
#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd
#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2
#define regDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf
#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2
#define regDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1
#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2
#define regDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3
#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2
#define regDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4
#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2
#define regDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5
#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2
#define regDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6
#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2
#define regDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7
#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2
#define regDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8
#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2
#define regDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9
#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2
#define regDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da
#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2
#define regDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db
#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2
#define regDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc
#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2
#define regDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd
#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2
#define regDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de
#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2
#define regDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df
#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2
#define regDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0
#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2
#define regDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1
#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2
#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3
#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4
#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5
#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6
#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7
#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8
#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9
#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea
#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb
#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec
#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2


// addressBlock: dce_dc_dchvm_hvm_dispdec
// base address: 0x0
#define regDCHVM_CTRL0                                                                                  0x3603
#define regDCHVM_CTRL0_BASE_IDX                                                                         2
#define regDCHVM_CTRL1                                                                                  0x3604
#define regDCHVM_CTRL1_BASE_IDX                                                                         2
#define regDCHVM_CLK_CTRL                                                                               0x3605
#define regDCHVM_CLK_CTRL_BASE_IDX                                                                      2
#define regDCHVM_MEM_CTRL                                                                               0x3606
#define regDCHVM_MEM_CTRL_BASE_IDX                                                                      2
#define regDCHVM_RIOMMU_CTRL0                                                                           0x3607
#define regDCHVM_RIOMMU_CTRL0_BASE_IDX                                                                  2
#define regDCHVM_RIOMMU_STAT0                                                                           0x3608
#define regDCHVM_RIOMMU_STAT0_BASE_IDX                                                                  2


// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec
// base address: 0x1ab8c
#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x3623
#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x3624
#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x3625
#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x3626
#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x3627
#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE                                                           0x3628
#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2


// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec
// base address: 0x1abc0
#define regAPG0_APG_CONTROL                                                                             0x3630
#define regAPG0_APG_CONTROL_BASE_IDX                                                                    2
#define regAPG0_APG_CONTROL2                                                                            0x3631
#define regAPG0_APG_CONTROL2_BASE_IDX                                                                   2
#define regAPG0_APG_DBG_GEN_CONTROL                                                                     0x3632
#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
#define regAPG0_APG_PACKET_CONTROL                                                                      0x3633
#define regAPG0_APG_PACKET_CONTROL_BASE_IDX                                                             2
#define regAPG0_APG_AUDIO_CRC_CONTROL                                                                   0x363a
#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
#define regAPG0_APG_AUDIO_CRC_CONTROL2                                                                  0x363b
#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
#define regAPG0_APG_AUDIO_CRC_RESULT                                                                    0x363c
#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
#define regAPG0_APG_STATUS                                                                              0x3641
#define regAPG0_APG_STATUS_BASE_IDX                                                                     2
#define regAPG0_APG_STATUS2                                                                             0x3642
#define regAPG0_APG_STATUS2_BASE_IDX                                                                    2
#define regAPG0_APG_MEM_PWR                                                                             0x3644
#define regAPG0_APG_MEM_PWR_BASE_IDX                                                                    2
#define regAPG0_APG_SPARE                                                                               0x3646
#define regAPG0_APG_SPARE_BASE_IDX                                                                      2


// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec
// base address: 0x1ac38
#define regDME6_DME_CONTROL                                                                             0x364e
#define regDME6_DME_CONTROL_BASE_IDX                                                                    2
#define regDME6_DME_MEMORY_CONTROL                                                                      0x364f
#define regDME6_DME_MEMORY_CONTROL_BASE_IDX                                                             2


// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec
// base address: 0x1ac44
#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3651
#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
#define regVPG6_VPG_GENERIC_PACKET_DATA                                                                 0x3652
#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3653
#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3654
#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
#define regVPG6_VPG_GENERIC_STATUS                                                                      0x3655
#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX                                                             2
#define regVPG6_VPG_MEM_PWR                                                                             0x3656
#define regVPG6_VPG_MEM_PWR_BASE_IDX                                                                    2
#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x3657
#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
#define regVPG6_VPG_ISRC1_2_DATA                                                                        0x3658
#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
#define regVPG6_VPG_MPEG_INFO0                                                                          0x3659
#define regVPG6_VPG_MPEG_INFO0_BASE_IDX                                                                 2
#define regVPG6_VPG_MPEG_INFO1                                                                          0x365a
#define regVPG6_VPG_MPEG_INFO1_BASE_IDX                                                                 2


// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec
// base address: 0x1ac74
#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL                                                           0x365d
#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x365e
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x365f
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3660
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3661
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0                                                          0x3662
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1                                                          0x3663
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2                                                          0x3664
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3                                                          0x3665
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4                                                          0x3666
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5                                                          0x3667
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6                                                          0x3668
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7                                                          0x3669
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8                                                          0x366a
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x366b
#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x366c
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x366d
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x366e
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x366f
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3670
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3671
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3672
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3673
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3674
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3675
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x3676
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x3677
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3678
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3679
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x367a
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL                                                       0x367b
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x367c
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x367d
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x367e
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3683
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3684
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3685
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3686
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3687
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3688
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3689
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x368a
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x368b
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x368c
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x368d
#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE                                                             0x368e
#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2


// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec
// base address: 0x1ad5c
#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL                                                       0x3697
#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE                                                               0x3698
#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX                                                      2


// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec
// base address: 0x1ae00
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL                                                         0x36c0
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS                                                          0x36c1
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE                                                      0x36c4
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x36c5
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x36c6
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x36c7
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x36c8
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0                                                         0x36cb
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1                                                         0x36cc
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2                                                         0x36cd
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3                                                         0x36ce
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x36d1
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x36d2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x36d3
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x36d4
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG                                                       0x36d7
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x36d8
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x36d9
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x36da
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x36db
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x36dc
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x36dd
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x36de
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x36df
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x36e0
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x36e1
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x36e2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x36e3
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x36e4
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x36e5
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x36e6
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x36e7
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS                                                    0x36e8
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x36ea
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0                                            0x36eb
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX                                   2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1                                            0x36ec
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX                                   2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL                                            0x36ed
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX                                   2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x36ee
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x36ef
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS                                                      0x36f0
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT                                                       0x36f1
#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2


// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec
// base address: 0x1aedc
#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x36f7
#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x36f8
#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x36f9
#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x36fa
#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x36fb
#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE                                                           0x36fc
#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2


// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec
// base address: 0x1af10
#define regAPG1_APG_CONTROL                                                                             0x3704
#define regAPG1_APG_CONTROL_BASE_IDX                                                                    2
#define regAPG1_APG_CONTROL2                                                                            0x3705
#define regAPG1_APG_CONTROL2_BASE_IDX                                                                   2
#define regAPG1_APG_DBG_GEN_CONTROL                                                                     0x3706
#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
#define regAPG1_APG_PACKET_CONTROL                                                                      0x3707
#define regAPG1_APG_PACKET_CONTROL                                                                      0x3707
#define regAPG1_APG_PACKET_CONTROL_BASE_IDX                                                             2
#define regAPG1_APG_AUDIO_CRC_CONTROL                                                                   0x370e
#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
#define regAPG1_APG_AUDIO_CRC_CONTROL2                                                                  0x370f
#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
#define regAPG1_APG_AUDIO_CRC_RESULT                                                                    0x3710
#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
#define regAPG1_APG_STATUS                                                                              0x3715
#define regAPG1_APG_STATUS_BASE_IDX                                                                     2
#define regAPG1_APG_STATUS2                                                                             0x3716
#define regAPG1_APG_STATUS2_BASE_IDX                                                                    2
#define regAPG1_APG_MEM_PWR                                                                             0x3718
#define regAPG1_APG_MEM_PWR_BASE_IDX                                                                    2
#define regAPG1_APG_SPARE                                                                               0x371a
#define regAPG1_APG_SPARE_BASE_IDX                                                                      2


// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec
// base address: 0x1af88
#define regDME7_DME_CONTROL                                                                             0x3722
#define regDME7_DME_CONTROL_BASE_IDX                                                                    2
#define regDME7_DME_MEMORY_CONTROL                                                                      0x3723
#define regDME7_DME_MEMORY_CONTROL_BASE_IDX                                                             2


// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec
// base address: 0x1af94
#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3725
#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
#define regVPG7_VPG_GENERIC_PACKET_DATA                                                                 0x3726
#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3727
#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3728
#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
#define regVPG7_VPG_GENERIC_STATUS                                                                      0x3729
#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX                                                             2
#define regVPG7_VPG_MEM_PWR                                                                             0x372a
#define regVPG7_VPG_MEM_PWR_BASE_IDX                                                                    2
#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x372b
#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
#define regVPG7_VPG_ISRC1_2_DATA                                                                        0x372c
#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
#define regVPG7_VPG_MPEG_INFO0                                                                          0x372d
#define regVPG7_VPG_MPEG_INFO0_BASE_IDX                                                                 2
#define regVPG7_VPG_MPEG_INFO1                                                                          0x372e
#define regVPG7_VPG_MPEG_INFO1_BASE_IDX                                                                 2


// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec
// base address: 0x1afc4
#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL                                                           0x3731
#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3732
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3733
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3734
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3735
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0                                                          0x3736
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1                                                          0x3737
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2                                                          0x3738
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3                                                          0x3739
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4                                                          0x373a
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5                                                          0x373b
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6                                                          0x373c
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7                                                          0x373d
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8                                                          0x373e
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x373f
#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3740
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3741
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3742
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3743
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3744
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3745
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3746
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3747
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3748
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3749
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x374a
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x374b
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x374c
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x374d
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x374e
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL                                                       0x374f
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3750
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3751
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3752
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3757
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3758
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3759
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x375a
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x375b
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x375c
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x375d
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x375e
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x375f
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x3760
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3761
#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE                                                             0x3762
#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2


// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec
// base address: 0x1b0ac
#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL                                                       0x376b
#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE                                                               0x376c
#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX                                                      2


// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec
// base address: 0x1b150
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL                                                         0x3794
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS                                                          0x3795
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE                                                      0x3798
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x3799
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x379a
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x379b
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x379c
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0                                                         0x379f
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1                                                         0x37a0
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2                                                         0x37a1
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3                                                         0x37a2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x37a5
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x37a6
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x37a7
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x37a8
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG                                                       0x37ab
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x37ac
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x37ad
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x37ae
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x37af
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x37b0
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x37b1
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x37b2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x37b3
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x37b4
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x37b5
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x37b6
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x37b7
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x37b8
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x37b9
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x37ba
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x37bb
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS                                                    0x37bc
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x37be
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0                                            0x37bf
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX                                   2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1                                            0x37c0
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX                                   2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL                                            0x37c1
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX                                   2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x37c2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x37c3
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS                                                      0x37c4
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT                                                       0x37c5
#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2


// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec
// base address: 0x1b22c
#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x37cb
#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x37cc
#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x37cd
#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x37ce
#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x37cf
#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE                                                           0x37d0
#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2


// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec
// base address: 0x1b260
#define regAPG2_APG_CONTROL                                                                             0x37d8
#define regAPG2_APG_CONTROL_BASE_IDX                                                                    2
#define regAPG2_APG_CONTROL2                                                                            0x37d9
#define regAPG2_APG_CONTROL2_BASE_IDX                                                                   2
#define regAPG2_APG_DBG_GEN_CONTROL                                                                     0x37da
#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
#define regAPG2_APG_PACKET_CONTROL                                                                      0x37db
#define regAPG2_APG_PACKET_CONTROL_BASE_IDX                                                             2
#define regAPG2_APG_AUDIO_CRC_CONTROL                                                                   0x37e2
#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
#define regAPG2_APG_AUDIO_CRC_CONTROL2                                                                  0x37e3
#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
#define regAPG2_APG_AUDIO_CRC_RESULT                                                                    0x37e4
#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
#define regAPG2_APG_STATUS                                                                              0x37e9
#define regAPG2_APG_STATUS_BASE_IDX                                                                     2
#define regAPG2_APG_STATUS2                                                                             0x37ea
#define regAPG2_APG_STATUS2_BASE_IDX                                                                    2
#define regAPG2_APG_MEM_PWR                                                                             0x37ec
#define regAPG2_APG_MEM_PWR_BASE_IDX                                                                    2
#define regAPG2_APG_SPARE                                                                               0x37ee
#define regAPG2_APG_SPARE_BASE_IDX                                                                      2


// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec
// base address: 0x1b2d8
#define regDME8_DME_CONTROL                                                                             0x37f6
#define regDME8_DME_CONTROL_BASE_IDX                                                                    2
#define regDME8_DME_MEMORY_CONTROL                                                                      0x37f7
#define regDME8_DME_MEMORY_CONTROL_BASE_IDX                                                             2


// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec
// base address: 0x1b2e4
#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x37f9
#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
#define regVPG8_VPG_GENERIC_PACKET_DATA                                                                 0x37fa
#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x37fb
#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x37fc
#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
#define regVPG8_VPG_GENERIC_STATUS                                                                      0x37fd
#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX                                                             2
#define regVPG8_VPG_MEM_PWR                                                                             0x37fe
#define regVPG8_VPG_MEM_PWR_BASE_IDX                                                                    2
#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x37ff
#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
#define regVPG8_VPG_ISRC1_2_DATA                                                                        0x3800
#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
#define regVPG8_VPG_MPEG_INFO0                                                                          0x3801
#define regVPG8_VPG_MPEG_INFO0_BASE_IDX                                                                 2
#define regVPG8_VPG_MPEG_INFO1                                                                          0x3802
#define regVPG8_VPG_MPEG_INFO1_BASE_IDX                                                                 2


// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec
// base address: 0x1b314
#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL                                                           0x3805
#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3806
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3807
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3808
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3809
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0                                                          0x380a
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1                                                          0x380b
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2                                                          0x380c
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3                                                          0x380d
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4                                                          0x380e
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5                                                          0x380f
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6                                                          0x3810
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7                                                          0x3811
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8                                                          0x3812
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x3813
#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3814
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3815
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3816
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3817
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3818
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3819
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x381a
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x381b
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x381c
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x381d
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x381e
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x381f
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3820
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3821
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x3822
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL                                                       0x3823
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3824
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3825
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3826
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x382b
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x382c
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x382d
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x382e
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x382f
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3830
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3831
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3832
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x3833
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x3834
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3835
#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE                                                             0x3836
#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2


// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec
// base address: 0x1b57c
#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x389f
#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x38a0
#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x38a1
#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x38a2
#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x38a3
#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE                                                           0x38a4
#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2


// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec
// base address: 0x1b5b0
#define regAPG3_APG_CONTROL                                                                             0x38ac
#define regAPG3_APG_CONTROL_BASE_IDX                                                                    2
#define regAPG3_APG_CONTROL2                                                                            0x38ad
#define regAPG3_APG_CONTROL2_BASE_IDX                                                                   2
#define regAPG3_APG_DBG_GEN_CONTROL                                                                     0x38ae
#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
#define regAPG3_APG_PACKET_CONTROL                                                                      0x38af
#define regAPG3_APG_PACKET_CONTROL_BASE_IDX                                                             2
#define regAPG3_APG_AUDIO_CRC_CONTROL                                                                   0x38b6
#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
#define regAPG3_APG_AUDIO_CRC_CONTROL2                                                                  0x38b7
#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
#define regAPG3_APG_AUDIO_CRC_RESULT                                                                    0x38b8
#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
#define regAPG3_APG_STATUS                                                                              0x38bd
#define regAPG3_APG_STATUS_BASE_IDX                                                                     2
#define regAPG3_APG_STATUS2                                                                             0x38be
#define regAPG3_APG_STATUS2_BASE_IDX                                                                    2
#define regAPG3_APG_MEM_PWR                                                                             0x38c0
#define regAPG3_APG_MEM_PWR_BASE_IDX                                                                    2
#define regAPG3_APG_SPARE                                                                               0x38c2
#define regAPG3_APG_SPARE_BASE_IDX                                                                      2


// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec
// base address: 0x1b628
#define regDME9_DME_CONTROL                                                                             0x38ca
#define regDME9_DME_CONTROL_BASE_IDX                                                                    2
#define regDME9_DME_MEMORY_CONTROL                                                                      0x38cb
#define regDME9_DME_MEMORY_CONTROL_BASE_IDX                                                             2


// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec
// base address: 0x1b634
#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x38cd
#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
#define regVPG9_VPG_GENERIC_PACKET_DATA                                                                 0x38ce
#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x38cf
#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x38d0
#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
#define regVPG9_VPG_GENERIC_STATUS                                                                      0x38d1
#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX                                                             2
#define regVPG9_VPG_MEM_PWR                                                                             0x38d2
#define regVPG9_VPG_MEM_PWR_BASE_IDX                                                                    2
#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x38d3
#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
#define regVPG9_VPG_ISRC1_2_DATA                                                                        0x38d4
#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
#define regVPG9_VPG_MPEG_INFO0                                                                          0x38d5
#define regVPG9_VPG_MPEG_INFO0_BASE_IDX                                                                 2
#define regVPG9_VPG_MPEG_INFO1                                                                          0x38d6
#define regVPG9_VPG_MPEG_INFO1_BASE_IDX                                                                 2


// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec
// base address: 0x1b664
#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL                                                           0x38d9
#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x38da
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x38db
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x38dc
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x38dd
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0                                                          0x38de
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1                                                          0x38df
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2                                                          0x38e0
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3                                                          0x38e1
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4                                                          0x38e2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5                                                          0x38e3
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6                                                          0x38e4
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7                                                          0x38e5
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8                                                          0x38e6
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x38e7
#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x38e8
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x38e9
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x38ea
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x38eb
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x38ec
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x38ed
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x38ee
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x38ef
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x38f0
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x38f1
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x38f2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x38f3
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x38f4
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x38f5
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x38f6
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL                                                       0x38f7
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x38f8
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x38f9
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x38fa
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x38ff
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3900
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3901
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3902
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3903
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3904
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3905
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3906
#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x3907
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x3908
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3909
#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE                                                             0x390a
#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2


// addressBlock: dce_dc_mpc_mpcc0_dispdec
// base address: 0x0
#define regMPCC0_MPCC_TOP_SEL                                                                           0x0000
#define regMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3
#define regMPCC0_MPCC_BOT_SEL                                                                           0x0001
#define regMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3
#define regMPCC0_MPCC_OPP_ID                                                                            0x0002
#define regMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3
#define regMPCC0_MPCC_CONTROL                                                                           0x0003
#define regMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3
#define regMPCC0_MPCC_SM_CONTROL                                                                        0x0004
#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3
#define regMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005
#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
#define regMPCC0_MPCC_TOP_GAIN                                                                          0x0006
#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3
#define regMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007
#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008
#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0009
#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
#define regMPCC0_MPCC_BG_R_CR                                                                           0x000a
#define regMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3
#define regMPCC0_MPCC_BG_G_Y                                                                            0x000b
#define regMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3
#define regMPCC0_MPCC_BG_B_CB                                                                           0x000c
#define regMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3
#define regMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000d
#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
#define regMPCC0_MPCC_STATUS                                                                            0x000e
#define regMPCC0_MPCC_STATUS_BASE_IDX                                                                   3


// addressBlock: dce_dc_mpc_mpcc1_dispdec
// base address: 0x54
#define regMPCC1_MPCC_TOP_SEL                                                                           0x0015
#define regMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3
#define regMPCC1_MPCC_BOT_SEL                                                                           0x0016
#define regMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3
#define regMPCC1_MPCC_OPP_ID                                                                            0x0017
#define regMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3
#define regMPCC1_MPCC_CONTROL                                                                           0x0018
#define regMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3
#define regMPCC1_MPCC_SM_CONTROL                                                                        0x0019
#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3
#define regMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x001a
#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
#define regMPCC1_MPCC_TOP_GAIN                                                                          0x001b
#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3
#define regMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x001c
#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x001d
#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x001e
#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
#define regMPCC1_MPCC_BG_R_CR                                                                           0x001f
#define regMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3
#define regMPCC1_MPCC_BG_G_Y                                                                            0x0020
#define regMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3
#define regMPCC1_MPCC_BG_B_CB                                                                           0x0021
#define regMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3
#define regMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x0022
#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
#define regMPCC1_MPCC_STATUS                                                                            0x0023
#define regMPCC1_MPCC_STATUS_BASE_IDX                                                                   3


// addressBlock: dce_dc_mpc_mpcc2_dispdec
// base address: 0xa8
#define regMPCC2_MPCC_TOP_SEL                                                                           0x002a
#define regMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3
#define regMPCC2_MPCC_BOT_SEL                                                                           0x002b
#define regMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3
#define regMPCC2_MPCC_OPP_ID                                                                            0x002c
#define regMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3
#define regMPCC2_MPCC_CONTROL                                                                           0x002d
#define regMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3
#define regMPCC2_MPCC_SM_CONTROL                                                                        0x002e
#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3
#define regMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x002f
#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
#define regMPCC2_MPCC_TOP_GAIN                                                                          0x0030
#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3
#define regMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0031
#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0032
#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0033
#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
#define regMPCC2_MPCC_BG_R_CR                                                                           0x0034
#define regMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3
#define regMPCC2_MPCC_BG_G_Y                                                                            0x0035
#define regMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3
#define regMPCC2_MPCC_BG_B_CB                                                                           0x0036
#define regMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3
#define regMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x0037
#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
#define regMPCC2_MPCC_STATUS                                                                            0x0038
#define regMPCC2_MPCC_STATUS_BASE_IDX                                                                   3


// addressBlock: dce_dc_mpc_mpcc3_dispdec
// base address: 0xfc
#define regMPCC3_MPCC_TOP_SEL                                                                           0x003f
#define regMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3
#define regMPCC3_MPCC_BOT_SEL                                                                           0x0040
#define regMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3
#define regMPCC3_MPCC_OPP_ID                                                                            0x0041
#define regMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3
#define regMPCC3_MPCC_CONTROL                                                                           0x0042
#define regMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3
#define regMPCC3_MPCC_SM_CONTROL                                                                        0x0043
#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3
#define regMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0044
#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
#define regMPCC3_MPCC_TOP_GAIN                                                                          0x0045
#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3
#define regMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0046
#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0047
#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0048
#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
#define regMPCC3_MPCC_BG_R_CR                                                                           0x0049
#define regMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3
#define regMPCC3_MPCC_BG_G_Y                                                                            0x004a
#define regMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3
#define regMPCC3_MPCC_BG_B_CB                                                                           0x004b
#define regMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3
#define regMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x004c
#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
#define regMPCC3_MPCC_STATUS                                                                            0x004d
#define regMPCC3_MPCC_STATUS_BASE_IDX                                                                   3



// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
// base address: 0x0
#define regMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x00a8
#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x00a9
#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x00aa
#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x00ab
#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x00ac
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x00ad
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x00ae
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x00af
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x00b0
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x00b1
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x00b2
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x00b3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x00b4
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x00b5
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x00b6
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x00b7
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x00b8
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x00b9
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x00ba
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x00bb
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x00bc
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x00bd
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x00be
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x00bf
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x00c0
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x00c1
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x00c2
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x00c3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x00c4
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x00c5
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x00c6
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x00c7
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x00c8
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x00c9
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x00ca
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x00cb
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x00cc
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x00cd
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x00ce
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x00cf
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x00d0
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x00d1
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x00d2
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x00d3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x00d4
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x00d5
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x00d6
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x00d7
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x00d8
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x00d9
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x00da
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x00db
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x00dc
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x00dd
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x00de
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x00df
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x00e0
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x00e1
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x00e2
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x00e3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x00e4
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x00e5
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x00e6
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x00e7
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x00e8
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x00e9
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x00ea
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x00eb
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x00ec
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x00ed
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x00ee
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x00ef
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x00f0
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x00f1
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x00f2
#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x00f3
#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x00f4
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x00f5
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x00f6
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x00f7
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x00f8
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x00f9
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x00fa
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x00fb
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x00fc
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x00fd
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x00fe
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x00ff
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3


// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
// base address: 0x178
#define regMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0106
#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0107
#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0108
#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0109
#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x010a
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x010b
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x010c
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x010d
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x010e
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x010f
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x0110
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x0111
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0112
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0113
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0114
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0115
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0116
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0117
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0118
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0119
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x011a
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x011b
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x011c
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x011d
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x011e
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x011f
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x0120
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x0121
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0122
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0123
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0124
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0125
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0126
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0127
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0128
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0129
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x012a
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x012b
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x012c
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x012d
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x012e
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x012f
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x0130
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x0131
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0132
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0133
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0134
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0135
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0136
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0137
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0138
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0139
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x013a
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x013b
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x013c
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x013d
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x013e
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x013f
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x0140
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x0141
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x0142
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x0143
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0144
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0145
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0146
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0147
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0148
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0149
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x014a
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x014b
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x014c
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x014d
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x014e
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x014f
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x0150
#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x0151
#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x0152
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x0153
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0154
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0155
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0156
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0157
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0158
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0159
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x015a
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x015b
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x015c
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x015d
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3


// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
// base address: 0x2f0
#define regMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0164
#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0165
#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0166
#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0167
#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0168
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0169
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x016a
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x016b
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x016c
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x016d
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x016e
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x016f
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0170
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0171
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0172
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0173
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0174
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0175
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0176
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0177
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0178
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0179
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x017a
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x017b
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x017c
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x017d
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x017e
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x017f
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0180
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0181
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0182
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0183
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0184
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0185
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0186
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0187
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0188
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0189
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x018a
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x018b
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x018c
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x018d
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x018e
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x018f
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0190
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0191
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0192
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0193
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0194
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0195
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0196
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0197
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0198
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0199
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x019a
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x019b
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x019c
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x019d
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x019e
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x019f
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01a0
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01a1
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01a2
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01a3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01a4
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01a5
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01a6
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01a7
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01a8
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01a9
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01aa
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01ab
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01ac
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01ad
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ae
#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x01af
#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01b0
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01b1
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01b2
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01b3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01b4
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01b5
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01b6
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01b7
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01b8
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01b9
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01ba
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01bb
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3


// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
// base address: 0x468
#define regMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x01c2
#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x01c3
#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x01c4
#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x01c5
#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x01c6
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x01c7
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x01c8
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x01c9
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x01ca
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x01cb
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x01cc
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x01cd
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x01ce
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x01cf
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x01d0
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x01d1
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x01d2
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x01d3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x01d4
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x01d5
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x01d6
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x01d7
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x01d8
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x01d9
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x01da
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x01db
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x01dc
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x01dd
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x01de
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x01df
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x01e0
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x01e1
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01e2
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01e3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01e4
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01e5
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01e6
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01e7
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01e8
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01e9
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01ea
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01eb
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01ec
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ed
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ee
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ef
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01f0
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01f1
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01f2
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01f3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01f4
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01f5
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01f6
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01f7
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01f8
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01f9
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01fa
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01fb
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01fc
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01fd
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01fe
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01ff
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0200
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0201
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0202
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0203
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0204
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0205
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0206
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0207
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0208
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0209
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x020a
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x020b
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x020c
#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x020d
#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x020e
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x020f
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0210
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0211
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0212
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0213
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0214
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0215
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0216
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0217
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0218
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0219
#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3


// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
// base address: 0x0
#define regMPC_CLOCK_CONTROL                                                                            0x0398
#define regMPC_CLOCK_CONTROL_BASE_IDX                                                                   3
#define regMPC_SOFT_RESET                                                                               0x0399
#define regMPC_SOFT_RESET_BASE_IDX                                                                      3
#define regMPC_CRC_CTRL                                                                                 0x039a
#define regMPC_CRC_CTRL_BASE_IDX                                                                        3
#define regMPC_CRC_SEL_CONTROL                                                                          0x039b
#define regMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3
#define regMPC_CRC_RESULT_AR                                                                            0x039c
#define regMPC_CRC_RESULT_AR_BASE_IDX                                                                   3
#define regMPC_CRC_RESULT_GB                                                                            0x039d
#define regMPC_CRC_RESULT_GB_BASE_IDX                                                                   3
#define regMPC_CRC_RESULT_C                                                                             0x039e
#define regMPC_CRC_RESULT_C_BASE_IDX                                                                    3
#define regMPC_PERFMON_EVENT_CTRL                                                                       0x03a1
#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX                                                              3
#define regMPC_BYPASS_BG_AR                                                                             0x03a2
#define regMPC_BYPASS_BG_AR_BASE_IDX                                                                    3
#define regMPC_BYPASS_BG_GB                                                                             0x03a3
#define regMPC_BYPASS_BG_GB_BASE_IDX                                                                    3
#define regMPC_HOST_READ_CONTROL                                                                        0x03a4
#define regMPC_HOST_READ_CONTROL_BASE_IDX                                                               3
#define regMPC_DPP_PENDING_STATUS                                                                       0x03a5
#define regMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3
#define regMPC_PENDING_STATUS_MISC                                                                      0x03a6
#define regMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3
#define regADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x03a7
#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3
#define regADR_CFG_VUPDATE_LOCK_SET0                                                                    0x03a8
#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3
#define regADR_VUPDATE_LOCK_SET0                                                                        0x03a9
#define regADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
#define regCFG_VUPDATE_LOCK_SET0                                                                        0x03aa
#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
#define regCUR_VUPDATE_LOCK_SET0                                                                        0x03ab
#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
#define regADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x03ac
#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3
#define regADR_CFG_VUPDATE_LOCK_SET1                                                                    0x03ad
#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3
#define regADR_VUPDATE_LOCK_SET1                                                                        0x03ae
#define regADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
#define regCFG_VUPDATE_LOCK_SET1                                                                        0x03af
#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
#define regCUR_VUPDATE_LOCK_SET1                                                                        0x03b0
#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
#define regADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x03b1
#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3
#define regADR_CFG_VUPDATE_LOCK_SET2                                                                    0x03b2
#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3
#define regADR_VUPDATE_LOCK_SET2                                                                        0x03b3
#define regADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
#define regCFG_VUPDATE_LOCK_SET2                                                                        0x03b4
#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
#define regCUR_VUPDATE_LOCK_SET2                                                                        0x03b5
#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
#define regADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x03b6
#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3
#define regADR_CFG_VUPDATE_LOCK_SET3                                                                    0x03b7
#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3
#define regADR_VUPDATE_LOCK_SET3                                                                        0x03b8
#define regADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
#define regCFG_VUPDATE_LOCK_SET3                                                                        0x03b9
#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
#define regCUR_VUPDATE_LOCK_SET3                                                                        0x03ba
#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
#define regMPC_DWB0_MUX                                                                                 0x03c6
#define regMPC_DWB0_MUX_BASE_IDX                                                                        3


// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
// base address: 0x0
#define regMPC_OUT0_MUX                                                                                 0x03d8
#define regMPC_OUT0_MUX_BASE_IDX                                                                        3
#define regMPC_OUT0_DENORM_CONTROL                                                                      0x03d9
#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3
#define regMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x03da
#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
#define regMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x03db
#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
#define regMPC_OUT1_MUX                                                                                 0x03dc
#define regMPC_OUT1_MUX_BASE_IDX                                                                        3
#define regMPC_OUT1_DENORM_CONTROL                                                                      0x03dd
#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3
#define regMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x03de
#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
#define regMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x03df
#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
#define regMPC_OUT2_MUX                                                                                 0x03e0
#define regMPC_OUT2_MUX_BASE_IDX                                                                        3
#define regMPC_OUT2_DENORM_CONTROL                                                                      0x03e1
#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3
#define regMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x03e2
#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
#define regMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x03e3
#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
#define regMPC_OUT3_MUX                                                                                 0x03e4
#define regMPC_OUT3_MUX_BASE_IDX                                                                        3
#define regMPC_OUT3_DENORM_CONTROL                                                                      0x03e5
#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3
#define regMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x03e6
#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
#define regMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x03e7
#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
#define regMPC_OUT_CSC_COEF_FORMAT                                                                      0x03f0
#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3
#define regMPC_OUT0_CSC_MODE                                                                            0x03f1
#define regMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3
#define regMPC_OUT0_CSC_C11_C12_A                                                                       0x03f2
#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3
#define regMPC_OUT0_CSC_C13_C14_A                                                                       0x03f3
#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3
#define regMPC_OUT0_CSC_C21_C22_A                                                                       0x03f4
#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3
#define regMPC_OUT0_CSC_C23_C24_A                                                                       0x03f5
#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3
#define regMPC_OUT0_CSC_C31_C32_A                                                                       0x03f6
#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3
#define regMPC_OUT0_CSC_C33_C34_A                                                                       0x03f7
#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3
#define regMPC_OUT0_CSC_C11_C12_B                                                                       0x03f8
#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3
#define regMPC_OUT0_CSC_C13_C14_B                                                                       0x03f9
#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3
#define regMPC_OUT0_CSC_C21_C22_B                                                                       0x03fa
#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3
#define regMPC_OUT0_CSC_C23_C24_B                                                                       0x03fb
#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3
#define regMPC_OUT0_CSC_C31_C32_B                                                                       0x03fc
#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3
#define regMPC_OUT0_CSC_C33_C34_B                                                                       0x03fd
#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3
#define regMPC_OUT1_CSC_MODE                                                                            0x03fe
#define regMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3
#define regMPC_OUT1_CSC_C11_C12_A                                                                       0x03ff
#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3
#define regMPC_OUT1_CSC_C13_C14_A                                                                       0x0400
#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3
#define regMPC_OUT1_CSC_C21_C22_A                                                                       0x0401
#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3
#define regMPC_OUT1_CSC_C23_C24_A                                                                       0x0402
#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3
#define regMPC_OUT1_CSC_C31_C32_A                                                                       0x0403
#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3
#define regMPC_OUT1_CSC_C33_C34_A                                                                       0x0404
#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3
#define regMPC_OUT1_CSC_C11_C12_B                                                                       0x0405
#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3
#define regMPC_OUT1_CSC_C13_C14_B                                                                       0x0406
#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3
#define regMPC_OUT1_CSC_C21_C22_B                                                                       0x0407
#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3
#define regMPC_OUT1_CSC_C23_C24_B                                                                       0x0408
#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3
#define regMPC_OUT1_CSC_C31_C32_B                                                                       0x0409
#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3
#define regMPC_OUT1_CSC_C33_C34_B                                                                       0x040a
#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3
#define regMPC_OUT2_CSC_MODE                                                                            0x040b
#define regMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3
#define regMPC_OUT2_CSC_C11_C12_A                                                                       0x040c
#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3
#define regMPC_OUT2_CSC_C13_C14_A                                                                       0x040d
#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3
#define regMPC_OUT2_CSC_C21_C22_A                                                                       0x040e
#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3
#define regMPC_OUT2_CSC_C23_C24_A                                                                       0x040f
#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3
#define regMPC_OUT2_CSC_C31_C32_A                                                                       0x0410
#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3
#define regMPC_OUT2_CSC_C33_C34_A                                                                       0x0411
#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3
#define regMPC_OUT2_CSC_C11_C12_B                                                                       0x0412
#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3
#define regMPC_OUT2_CSC_C13_C14_B                                                                       0x0413
#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3
#define regMPC_OUT2_CSC_C21_C22_B                                                                       0x0414
#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3
#define regMPC_OUT2_CSC_C23_C24_B                                                                       0x0415
#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3
#define regMPC_OUT2_CSC_C31_C32_B                                                                       0x0416
#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3
#define regMPC_OUT2_CSC_C33_C34_B                                                                       0x0417
#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3
#define regMPC_OUT3_CSC_MODE                                                                            0x0418
#define regMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3
#define regMPC_OUT3_CSC_C11_C12_A                                                                       0x0419
#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3
#define regMPC_OUT3_CSC_C13_C14_A                                                                       0x041a
#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3
#define regMPC_OUT3_CSC_C21_C22_A                                                                       0x041b
#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3
#define regMPC_OUT3_CSC_C23_C24_A                                                                       0x041c
#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3
#define regMPC_OUT3_CSC_C31_C32_A                                                                       0x041d
#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3
#define regMPC_OUT3_CSC_C33_C34_A                                                                       0x041e
#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3
#define regMPC_OUT3_CSC_C11_C12_B                                                                       0x041f
#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3
#define regMPC_OUT3_CSC_C13_C14_B                                                                       0x0420
#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3
#define regMPC_OUT3_CSC_C21_C22_B                                                                       0x0421
#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3
#define regMPC_OUT3_CSC_C23_C24_B                                                                       0x0422
#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3
#define regMPC_OUT3_CSC_C31_C32_B                                                                       0x0423
#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3
#define regMPC_OUT3_CSC_C33_C34_B                                                                       0x0424
#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3


// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
// base address: 0x17e1c
#define regDC_PERFMON15_PERFCOUNTER_CNTL                                                                0x0447
#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX                                                       3
#define regDC_PERFMON15_PERFCOUNTER_CNTL2                                                               0x0448
#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX                                                      3
#define regDC_PERFMON15_PERFCOUNTER_STATE                                                               0x0449
#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX                                                      3
#define regDC_PERFMON15_PERFMON_CNTL                                                                    0x044a
#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX                                                           3
#define regDC_PERFMON15_PERFMON_CNTL2                                                                   0x044b
#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX                                                          3
#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC                                                         0x044c
#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3
#define regDC_PERFMON15_PERFMON_CVALUE_LOW                                                              0x044d
#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX                                                     3
#define regDC_PERFMON15_PERFMON_HI                                                                      0x044e
#define regDC_PERFMON15_PERFMON_HI_BASE_IDX                                                             3
#define regDC_PERFMON15_PERFMON_LOW                                                                     0x044f
#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX                                                            3


// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
// base address: 0x2646c
#define regAFMT5_AFMT_ACP                                                                               0x091b
#define regAFMT5_AFMT_ACP_BASE_IDX                                                                      3
#define regAFMT5_AFMT_VBI_PACKET_CONTROL                                                                0x091c
#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       3
#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2                                                             0x091d
#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    3
#define regAFMT5_AFMT_AUDIO_INFO0                                                                       0x091e
#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX                                                              3
#define regAFMT5_AFMT_AUDIO_INFO1                                                                       0x091f
#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX                                                              3
#define regAFMT5_AFMT_60958_0                                                                           0x0920
#define regAFMT5_AFMT_60958_0_BASE_IDX                                                                  3
#define regAFMT5_AFMT_60958_1                                                                           0x0921
#define regAFMT5_AFMT_60958_1_BASE_IDX                                                                  3
#define regAFMT5_AFMT_AUDIO_CRC_CONTROL                                                                 0x0922
#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        3
#define regAFMT5_AFMT_RAMP_CONTROL0                                                                     0x0923
#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX                                                            3
#define regAFMT5_AFMT_RAMP_CONTROL1                                                                     0x0924
#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX                                                            3
#define regAFMT5_AFMT_RAMP_CONTROL2                                                                     0x0925
#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX                                                            3
#define regAFMT5_AFMT_RAMP_CONTROL3                                                                     0x0926
#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX                                                            3
#define regAFMT5_AFMT_60958_2                                                                           0x0927
#define regAFMT5_AFMT_60958_2_BASE_IDX                                                                  3
#define regAFMT5_AFMT_AUDIO_CRC_RESULT                                                                  0x0928
#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         3
#define regAFMT5_AFMT_STATUS                                                                            0x0929
#define regAFMT5_AFMT_STATUS_BASE_IDX                                                                   3
#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL                                                              0x092a
#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     3
#define regAFMT5_AFMT_INFOFRAME_CONTROL0                                                                0x092b
#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       3
#define regAFMT5_AFMT_INTERRUPT_STATUS                                                                  0x092c
#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         3
#define regAFMT5_AFMT_AUDIO_SRC_CONTROL                                                                 0x092d
#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        3
#define regAFMT5_AFMT_MEM_PWR                                                                           0x092f
#define regAFMT5_AFMT_MEM_PWR_BASE_IDX                                                                  3


// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
// base address: 0x264c4
#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x0931
#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 3
#define regVPG5_VPG_GENERIC_PACKET_DATA                                                                 0x0932
#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        3
#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x0933
#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      3
#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x0934
#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  3
#define regVPG5_VPG_GENERIC_STATUS                                                                      0x0935
#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX                                                             3
#define regVPG5_VPG_MEM_PWR                                                                             0x0936
#define regVPG5_VPG_MEM_PWR_BASE_IDX                                                                    3
#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x0937
#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        3
#define regVPG5_VPG_ISRC1_2_DATA                                                                        0x0938
#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX                                                               3
#define regVPG5_VPG_MPEG_INFO0                                                                          0x0939
#define regVPG5_VPG_MPEG_INFO0_BASE_IDX                                                                 3
#define regVPG5_VPG_MPEG_INFO1                                                                          0x093a
#define regVPG5_VPG_MPEG_INFO1_BASE_IDX                                                                 3


// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
// base address: 0x264f0
#define regDME5_DME_CONTROL                                                                             0x093c
#define regDME5_DME_CONTROL_BASE_IDX                                                                    3
#define regDME5_DME_MEMORY_CONTROL                                                                      0x093d
#define regDME5_DME_MEMORY_CONTROL_BASE_IDX                                                             3


// addressBlock: dce_dc_hpo_hpo_top_dispdec
// base address: 0x2790c
#define regHPO_TOP_CLOCK_CONTROL                                                                        0x0e43
#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3
#define regHPO_TOP_HW_CONTROL                                                                           0x0e4a
#define regHPO_TOP_HW_CONTROL_BASE_IDX                                                                  3


// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec
// base address: 0x27958
#define regDP_STREAM_MAPPER_CONTROL0                                                                    0x0e56
#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX                                                           3
#define regDP_STREAM_MAPPER_CONTROL1                                                                    0x0e57
#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX                                                           3
#define regDP_STREAM_MAPPER_CONTROL2                                                                    0x0e58
#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX                                                           3
#define regDP_STREAM_MAPPER_CONTROL3                                                                    0x0e59
#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX                                                           3


// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec
// base address: 0x1a698
#define regDC_PERFMON23_PERFCOUNTER_CNTL                                                                0x0e66
#define regDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX                                                       3
#define regDC_PERFMON23_PERFCOUNTER_CNTL2                                                               0x0e67
#define regDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX                                                      3
#define regDC_PERFMON23_PERFCOUNTER_STATE                                                               0x0e68
#define regDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX                                                      3
#define regDC_PERFMON23_PERFMON_CNTL                                                                    0x0e69
#define regDC_PERFMON23_PERFMON_CNTL_BASE_IDX                                                           3
#define regDC_PERFMON23_PERFMON_CNTL2                                                                   0x0e6a
#define regDC_PERFMON23_PERFMON_CNTL2_BASE_IDX                                                          3
#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC                                                         0x0e6b
#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3
#define regDC_PERFMON23_PERFMON_CVALUE_LOW                                                              0x0e6c
#define regDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX                                                     3
#define regDC_PERFMON23_PERFMON_HI                                                                      0x0e6d
#define regDC_PERFMON23_PERFMON_HI_BASE_IDX                                                             3
#define regDC_PERFMON23_PERFMON_LOW                                                                     0x0e6e
#define regDC_PERFMON23_PERFMON_LOW_BASE_IDX                                                            3



// addressBlock: dce_dc_opp_abm0_dispdec
// base address: 0x0
#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a
#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
#define regABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b
#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
#define regABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c
#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d
#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e
#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f
#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
#define regABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80
#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81
#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
#define regABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82
#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
#define regABM0_DC_ABM1_CNTL                                                                            0x0e83
#define regABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3
#define regABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84
#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0e85
#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0e86
#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0e87
#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0e88
#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0e89
#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
#define regABM0_DC_ABM1_ACE_THRES_12                                                                    0x0e8a
#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
#define regABM0_DC_ABM1_ACE_THRES_34                                                                    0x0e8b
#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
#define regABM0_DC_ABM1_ACE_CNTL_MISC                                                                   0x0e8c
#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e
#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
#define regABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f
#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
#define regABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90
#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91
#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92
#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
#define regABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93
#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94
#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95
#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96
#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
#define regABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97
#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
#define regABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98
#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99
#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a
#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b
#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c
#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d
#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
#define regABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e
#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
#define regABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f
#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
#define regABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0
#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
#define regABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1
#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
#define regABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2
#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
#define regABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3
#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
#define regABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4
#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
#define regABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5
#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
#define regABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6
#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
#define regABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7
#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8
#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9
#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa
#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab
#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac
#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead
#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae
#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf
#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0
#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1
#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2
#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3
#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4
#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
#define regABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5
#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
#define regABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6
#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3


// addressBlock: dce_dc_opp_abm1_dispdec
// base address: 0x104
#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb
#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
#define regABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc
#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
#define regABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd
#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe
#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf
#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0
#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
#define regABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1
#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2
#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
#define regABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3
#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
#define regABM1_DC_ABM1_CNTL                                                                            0x0ec4
#define regABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3
#define regABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5
#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0ec6
#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0ec7
#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0ec8
#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0ec9
#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0eca
#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
#define regABM1_DC_ABM1_ACE_THRES_12                                                                    0x0ecb
#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
#define regABM1_DC_ABM1_ACE_THRES_34                                                                    0x0ecc
#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
#define regABM1_DC_ABM1_ACE_CNTL_MISC                                                                   0x0ecd
#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf
#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
#define regABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0
#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
#define regABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1
#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2
#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3
#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
#define regABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4
#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5
#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6
#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7
#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
#define regABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8
#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
#define regABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9
#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda
#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb
#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc
#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd
#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede
#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
#define regABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf
#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
#define regABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0
#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
#define regABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1
#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
#define regABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2
#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
#define regABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3
#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
#define regABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4
#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
#define regABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5
#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
#define regABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6
#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
#define regABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7
#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
#define regABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8
#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9
#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea
#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb
#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec
#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed
#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee
#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef
#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0
#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1
#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2
#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3
#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4
#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5
#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
#define regABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6
#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
#define regABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7
#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3


// addressBlock: dce_dc_opp_abm2_dispdec
// base address: 0x208
#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc
#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
#define regABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd
#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
#define regABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe
#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff
#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00
#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01
#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
#define regABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02
#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03
#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
#define regABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04
#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
#define regABM2_DC_ABM1_CNTL                                                                            0x0f05
#define regABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3
#define regABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06
#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f07
#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f08
#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f09
#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f0a
#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f0b
#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
#define regABM2_DC_ABM1_ACE_THRES_12                                                                    0x0f0c
#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
#define regABM2_DC_ABM1_ACE_THRES_34                                                                    0x0f0d
#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
#define regABM2_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f0e
#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f10
#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
#define regABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f11
#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
#define regABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f12
#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f13
#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f14
#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
#define regABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f15
#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f16
#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f17
#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f18
#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
#define regABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f19
#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
#define regABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f1a
#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f1b
#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f1c
#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1d
#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1e
#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1f
#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
#define regABM2_DC_ABM1_HG_RESULT_1                                                                     0x0f20
#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
#define regABM2_DC_ABM1_HG_RESULT_2                                                                     0x0f21
#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
#define regABM2_DC_ABM1_HG_RESULT_3                                                                     0x0f22
#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
#define regABM2_DC_ABM1_HG_RESULT_4                                                                     0x0f23
#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
#define regABM2_DC_ABM1_HG_RESULT_5                                                                     0x0f24
#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
#define regABM2_DC_ABM1_HG_RESULT_6                                                                     0x0f25
#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
#define regABM2_DC_ABM1_HG_RESULT_7                                                                     0x0f26
#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
#define regABM2_DC_ABM1_HG_RESULT_8                                                                     0x0f27
#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
#define regABM2_DC_ABM1_HG_RESULT_9                                                                     0x0f28
#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
#define regABM2_DC_ABM1_HG_RESULT_10                                                                    0x0f29
#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_11                                                                    0x0f2a
#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_12                                                                    0x0f2b
#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_13                                                                    0x0f2c
#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_14                                                                    0x0f2d
#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_15                                                                    0x0f2e
#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_16                                                                    0x0f2f
#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_17                                                                    0x0f30
#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_18                                                                    0x0f31
#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_19                                                                    0x0f32
#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_20                                                                    0x0f33
#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_21                                                                    0x0f34
#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_22                                                                    0x0f35
#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_23                                                                    0x0f36
#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
#define regABM2_DC_ABM1_HG_RESULT_24                                                                    0x0f37
#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
#define regABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f38
#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3


// addressBlock: dce_dc_opp_abm3_dispdec
// base address: 0x30c
#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d
#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
#define regABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e
#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
#define regABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f
#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40
#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41
#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42
#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
#define regABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43
#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44
#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
#define regABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45
#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
#define regABM3_DC_ABM1_CNTL                                                                            0x0f46
#define regABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3
#define regABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47
#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f48
#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f49
#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f4a
#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f4b
#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f4c
#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
#define regABM3_DC_ABM1_ACE_THRES_12                                                                    0x0f4d
#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
#define regABM3_DC_ABM1_ACE_THRES_34                                                                    0x0f4e
#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
#define regABM3_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f4f
#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f51
#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
#define regABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f52
#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
#define regABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f53
#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f54
#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f55
#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
#define regABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f56
#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f57
#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f58
#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f59
#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
#define regABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f5a
#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
#define regABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f5b
#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f5c
#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5d
#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5e
#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5f
#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f60
#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
#define regABM3_DC_ABM1_HG_RESULT_1                                                                     0x0f61
#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
#define regABM3_DC_ABM1_HG_RESULT_2                                                                     0x0f62
#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
#define regABM3_DC_ABM1_HG_RESULT_3                                                                     0x0f63
#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
#define regABM3_DC_ABM1_HG_RESULT_4                                                                     0x0f64
#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
#define regABM3_DC_ABM1_HG_RESULT_5                                                                     0x0f65
#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
#define regABM3_DC_ABM1_HG_RESULT_6                                                                     0x0f66
#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
#define regABM3_DC_ABM1_HG_RESULT_7                                                                     0x0f67
#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
#define regABM3_DC_ABM1_HG_RESULT_8                                                                     0x0f68
#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
#define regABM3_DC_ABM1_HG_RESULT_9                                                                     0x0f69
#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
#define regABM3_DC_ABM1_HG_RESULT_10                                                                    0x0f6a
#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_11                                                                    0x0f6b
#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_12                                                                    0x0f6c
#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_13                                                                    0x0f6d
#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_14                                                                    0x0f6e
#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_15                                                                    0x0f6f
#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_16                                                                    0x0f70
#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_17                                                                    0x0f71
#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_18                                                                    0x0f72
#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_19                                                                    0x0f73
#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_20                                                                    0x0f74
#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_21                                                                    0x0f75
#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_22                                                                    0x0f76
#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_23                                                                    0x0f77
#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
#define regABM3_DC_ABM1_HG_RESULT_24                                                                    0x0f78
#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
#define regABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f79
#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3


// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec
// base address: 0x2656c
#define regHDMI_LINK_ENC_CONTROL                                                                        0x095b
#define regHDMI_LINK_ENC_CONTROL_BASE_IDX                                                               3
#define regHDMI_LINK_ENC_CLK_CTRL                                                                       0x095c
#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX                                                              3


// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec
// base address: 0x26594
#define regHDMI_FRL_ENC_CONFIG                                                                          0x0965
#define regHDMI_FRL_ENC_CONFIG_BASE_IDX                                                                 3
#define regHDMI_FRL_ENC_CONFIG2                                                                         0x0966
#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX                                                                3
#define regHDMI_FRL_ENC_METER_BUFFER_STATUS                                                             0x0967
#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX                                                    3
#define regHDMI_FRL_ENC_MEM_CTRL                                                                        0x0968
#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX                                                               3


// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec
// base address: 0x2634c
#define regHDMI_STREAM_ENC_CLOCK_CONTROL                                                                0x08d3
#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                                       3
#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL                                                            0x08d5
#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                                   3
#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                                     0x08d6
#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX                            3
#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                                     0x08d7
#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX                            3
#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2                                     0x08d8
#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX                            3


// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec
// base address: 0x2637c
#define regHDMI_TB_ENC_CONTROL                                                                          0x08df
#define regHDMI_TB_ENC_CONTROL_BASE_IDX                                                                 3
#define regHDMI_TB_ENC_PIXEL_FORMAT                                                                     0x08e0
#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX                                                            3
#define regHDMI_TB_ENC_PACKET_CONTROL                                                                   0x08e1
#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX                                                          3
#define regHDMI_TB_ENC_ACR_PACKET_CONTROL                                                               0x08e2
#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX                                                      3
#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1                                                              0x08e3
#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX                                                     3
#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2                                                              0x08e4
#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX                                                     3
#define regHDMI_TB_ENC_GC_CONTROL                                                                       0x08e5
#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX                                                              3
#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0                                                          0x08e6
#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX                                                 3
#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1                                                          0x08e7
#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX                                                 3
#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2                                                          0x08e8
#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX                                                 3
#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE                                                           0x08e9
#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX                                                  3
#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE                                                           0x08ea
#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX                                                  3
#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE                                                           0x08eb
#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX                                                  3
#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE                                                           0x08ec
#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX                                                  3
#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE                                                           0x08ed
#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX                                                  3
#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE                                                         0x08ee
#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX                                                3
#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE                                                         0x08ef
#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX                                                3
#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE                                                            0x08f0
#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX                                                   3
#define regHDMI_TB_ENC_DB_CONTROL                                                                       0x08f1
#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX                                                              3
#define regHDMI_TB_ENC_ACR_32_0                                                                         0x08f2
#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX                                                                3
#define regHDMI_TB_ENC_ACR_32_1                                                                         0x08f3
#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX                                                                3
#define regHDMI_TB_ENC_ACR_44_0                                                                         0x08f4
#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX                                                                3
#define regHDMI_TB_ENC_ACR_44_1                                                                         0x08f5
#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX                                                                3
#define regHDMI_TB_ENC_ACR_48_0                                                                         0x08f6
#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX                                                                3
#define regHDMI_TB_ENC_ACR_48_1                                                                         0x08f7
#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX                                                                3
#define regHDMI_TB_ENC_ACR_STATUS_0                                                                     0x08f8
#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX                                                            3
#define regHDMI_TB_ENC_ACR_STATUS_1                                                                     0x08f9
#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX                                                            3
#define regHDMI_TB_ENC_BUFFER_CONTROL                                                                   0x08fb
#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX                                                          3
#define regHDMI_TB_ENC_MEM_CTRL                                                                         0x08fe
#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX                                                                3
#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL                                                          0x08ff
#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX                                                 3
#define regHDMI_TB_ENC_H_ACTIVE_BLANK                                                                   0x0900
#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX                                                          3
#define regHDMI_TB_ENC_HC_ACTIVE_BLANK                                                                  0x0901
#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX                                                         3
#define regHDMI_TB_ENC_CRC_CNTL                                                                         0x0903
#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX                                                                3
#define regHDMI_TB_ENC_CRC_RESULT_0                                                                     0x0904
#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX                                                            3
#define regHDMI_TB_ENC_ENCRYPTION_CONTROL                                                               0x0907
#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX                                                      3
#define regHDMI_TB_ENC_MODE                                                                             0x0908
#define regHDMI_TB_ENC_MODE_BASE_IDX                                                                    3
#define regHDMI_TB_ENC_INPUT_FIFO_STATUS                                                                0x0909
#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX                                                       3
#define regHDMI_TB_ENC_CRC_RESULT_1                                                                     0x090a
#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX                                                            3


// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec
// base address: 0x0
#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL                                                            0x0453
#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0454
#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0455
#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0456
#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R                                                            0x0457
#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0458
#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0459
#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA                                                           0x045a
#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x045b
#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x045c
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x045d
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x045e
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x045f
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0460
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0461
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0462
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0463
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0464
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0465
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0466
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0467
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0468
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0469
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x046a
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x046b
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x046c
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x046d
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x046e
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x046f
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0470
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0471
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0472
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0473
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0474
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0475
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0476
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0477
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0478
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0479
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x047a
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x047b
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x047c
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x047d
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x047e
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x047f
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0480
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0481
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0482
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0483
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0484
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0485
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0486
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0487
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0488
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0489
#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE                                                                0x048a
#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX                                                               0x048b
#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA                                                                0x048c
#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x048d
#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x048e
#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x048f
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0490
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0491
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0492
#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL                                                             0x0493
#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0494
#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0495
#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0496
#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0497
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0498
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0499
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x049a
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x049b
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x049c
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x049d
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x049e
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x049f
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x04a0
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x04a1
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x04a2
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x04a3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x04a4
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x04a5
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x04a6
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x04a7
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x04a8
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x04a9
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x04aa
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x04ab
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x04ac
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x04ad
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x04ae
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x04af
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x04b0
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x04b1
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x04b2
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x04b3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x04b4
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x04b5
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x04b6
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x04b7
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x04b8
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x04b9
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x04ba
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x04bb
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x04bc
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x04bd
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x04be
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x04bf
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x04c0
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x04c1
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x04c2
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x04c3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x04c4
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x04c5
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x04c6
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x04c7
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x04c8
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x04c9
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x04ca
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x04cb
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x04cc
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x04cd
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x04ce
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x04cf
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x04d0
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x04d1
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x04d2
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x04d3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x04d4
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x04d5
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x04d6
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x04d7
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x04d8
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x04d9
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x04da
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x04db
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x04dc
#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL                                                              0x04dd
#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3


// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec
// base address: 0x240
#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL                                                            0x04e3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R                                                           0x04e4
#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G                                                           0x04e5
#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B                                                           0x04e6
#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R                                                            0x04e7
#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x04e8
#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x04e9
#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA                                                           0x04ea
#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x04eb
#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x04ec
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x04ed
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x04ee
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x04ef
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x04f0
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x04f1
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x04f2
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x04f3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x04f4
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x04f5
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x04f6
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x04f7
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x04f8
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x04f9
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x04fa
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x04fb
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x04fc
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x04fd
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x04fe
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x04ff
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0500
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0501
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0502
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0503
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0504
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0505
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0506
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0507
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0508
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0509
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x050a
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x050b
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x050c
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x050d
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x050e
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x050f
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0510
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0511
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0512
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0513
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0514
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0515
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0516
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0517
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0518
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0519
#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE                                                                0x051a
#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX                                                               0x051b
#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA                                                                0x051c
#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x051d
#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x051e
#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x051f
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0520
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0521
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0522
#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL                                                             0x0523
#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0524
#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0525
#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0526
#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0527
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0528
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0529
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x052a
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x052b
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x052c
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x052d
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x052e
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x052f
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0530
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0531
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0532
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0533
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0534
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0535
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0536
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0537
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0538
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0539
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x053a
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x053b
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x053c
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x053d
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x053e
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x053f
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0540
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0541
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0542
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0543
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0544
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0545
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0546
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0547
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0548
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0549
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x054a
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x054b
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x054c
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x054d
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x054e
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x054f
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0550
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0551
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0552
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0553
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0554
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0555
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0556
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0557
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0558
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0559
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x055a
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x055b
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x055c
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x055d
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x055e
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x055f
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0560
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0561
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0562
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0563
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0564
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0565
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0566
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0567
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0568
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0569
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x056a
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x056b
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x056c
#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL                                                              0x056d
#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3


// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec
// base address: 0x480
#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL                                                            0x0573
#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0574
#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0575
#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0576
#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R                                                            0x0577
#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0578
#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0579
#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA                                                           0x057a
#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x057b
#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x057c
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x057d
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x057e
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x057f
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0580
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0581
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0582
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0583
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0584
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0585
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0586
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0587
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0588
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0589
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x058a
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x058b
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x058c
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x058d
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x058e
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x058f
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0590
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0591
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0592
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0593
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0594
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0595
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0596
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0597
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0598
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0599
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x059a
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x059b
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x059c
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x059d
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x059e
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x059f
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x05a0
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x05a1
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x05a2
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x05a3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x05a4
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x05a5
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x05a6
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x05a7
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x05a8
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x05a9
#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE                                                                0x05aa
#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX                                                               0x05ab
#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA                                                                0x05ac
#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x05ad
#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x05ae
#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x05af
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x05b0
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x05b1
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x05b2
#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL                                                             0x05b3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x05b4
#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA                                                            0x05b5
#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x05b6
#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x05b7
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x05b8
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x05b9
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x05ba
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x05bb
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x05bc
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x05bd
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x05be
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x05bf
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x05c0
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x05c1
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x05c2
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x05c3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x05c4
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x05c5
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x05c6
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x05c7
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x05c8
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x05c9
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x05ca
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x05cb
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x05cc
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x05cd
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x05ce
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x05cf
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x05d0
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x05d1
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x05d2
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x05d3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x05d4
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x05d5
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x05d6
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x05d7
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x05d8
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x05d9
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x05da
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x05db
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x05dc
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x05dd
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x05de
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x05df
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x05e0
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x05e1
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x05e2
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x05e3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x05e4
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x05e5
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x05e6
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x05e7
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x05e8
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x05e9
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x05ea
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x05eb
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x05ec
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x05ed
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x05ee
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x05ef
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x05f0
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x05f1
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x05f2
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x05f3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x05f4
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x05f5
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x05f6
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x05f7
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x05f8
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x05f9
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x05fa
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x05fb
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x05fc
#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL                                                              0x05fd
#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3


// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec
// base address: 0x6c0
#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL                                                            0x0603
#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0604
#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0605
#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0606
#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R                                                            0x0607
#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0608
#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0609
#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA                                                           0x060a
#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x060b
#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x060c
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x060d
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x060e
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x060f
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0610
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0611
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0612
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0613
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0614
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0615
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0616
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0617
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0618
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0619
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x061a
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x061b
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x061c
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x061d
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x061e
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x061f
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0620
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0621
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0622
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0623
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0624
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0625
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0626
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0627
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0628
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0629
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x062a
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x062b
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x062c
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x062d
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x062e
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x062f
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0630
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0631
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0632
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0633
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0634
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0635
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0636
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0637
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0638
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0639
#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE                                                                0x063a
#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX                                                               0x063b
#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA                                                                0x063c
#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x063d
#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x063e
#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x063f
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0640
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0641
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0642
#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL                                                             0x0643
#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0644
#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0645
#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0646
#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0647
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0648
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0649
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x064a
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x064b
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x064c
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x064d
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x064e
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x064f
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0650
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0651
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0652
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0653
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0654
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0655
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0656
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0657
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0658
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0659
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x065a
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x065b
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x065c
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x065d
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x065e
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x065f
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0660
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0661
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0662
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0663
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0664
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0665
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0666
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0667
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0668
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0669
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x066a
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x066b
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x066c
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x066d
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x066e
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x066f
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0670
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0671
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0672
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0673
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0674
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0675
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0676
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0677
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0678
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0679
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x067a
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x067b
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x067c
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x067d
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x067e
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x067f
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0680
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0681
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0682
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0683
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0684
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0685
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0686
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0687
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0688
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0689
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x068a
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x068b
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x068c
#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL                                                              0x068d
#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3


// addressBlock: dce_dc_dlpc_dlpc_dispdec
// base address: 0x0
#define regDLPC_ENABLE                                                                                  0x2fe8
#define regDLPC_ENABLE_BASE_IDX                                                                         2
#define regDLPC_CURRENT_COUNT                                                                           0x2fe9
#define regDLPC_CURRENT_COUNT_BASE_IDX                                                                  2
#define regDLPC_OPTC_SNAPSHOT                                                                           0x2fea
#define regDLPC_OPTC_SNAPSHOT_BASE_IDX                                                                  2
#define regDLPC_PWRUP                                                                                   0x2feb
#define regDLPC_PWRUP_BASE_IDX                                                                          2
#define regDLPC_OTG_RESYNC                                                                              0x2fec
#define regDLPC_OTG_RESYNC_BASE_IDX                                                                     2
#define regDLPC_DCN_ZSC_LONO_PWRUP                                                                      0x2fed
#define regDLPC_DCN_ZSC_LONO_PWRUP_BASE_IDX                                                             2
#define regDLPC_SPARE                                                                                   0x2fee
#define regDLPC_SPARE_BASE_IDX                                                                          2
#define regDLPC_COUNTER_INIT_VALUE                                                                      0x2fef
#define regDLPC_COUNTER_INIT_VALUE_BASE_IDX                                                             2


// addressBlock: dce_dpia_dpia_mu0_dpiadec
// base address: 0x72000
#define regDPIA_MU_CLOCK_CTRL                                                                           0x13800
#define regDPIA_MU_CLOCK_CTRL_BASE_IDX                                                                  3
#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0                                                                0x13801
#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0_BASE_IDX                                                       3
#define regDPIA_MU_RESET_CTRL_DPIA_PORT0                                                                0x13802
#define regDPIA_MU_RESET_CTRL_DPIA_PORT0_BASE_IDX                                                       3
#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1                                                                0x13803
#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1_BASE_IDX                                                       3
#define regDPIA_MU_RESET_CTRL_DPIA_PORT1                                                                0x13804
#define regDPIA_MU_RESET_CTRL_DPIA_PORT1_BASE_IDX                                                       3
#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2                                                                0x13805
#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2_BASE_IDX                                                       3
#define regDPIA_MU_RESET_CTRL_DPIA_PORT2                                                                0x13806
#define regDPIA_MU_RESET_CTRL_DPIA_PORT2_BASE_IDX                                                       3
#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3                                                                0x13807
#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3_BASE_IDX                                                       3
#define regDPIA_MU_RESET_CTRL_DPIA_PORT3                                                                0x13808
#define regDPIA_MU_RESET_CTRL_DPIA_PORT3_BASE_IDX                                                       3
#define regDPIA_MU_TPI_STATUS_DPIA_PORT0                                                                0x13811
#define regDPIA_MU_TPI_STATUS_DPIA_PORT0_BASE_IDX                                                       3
#define regDPIA_MU_TPI_STATUS_DPIA_PORT1                                                                0x13812
#define regDPIA_MU_TPI_STATUS_DPIA_PORT1_BASE_IDX                                                       3
#define regDPIA_MU_TPI_STATUS_DPIA_PORT2                                                                0x13813
#define regDPIA_MU_TPI_STATUS_DPIA_PORT2_BASE_IDX                                                       3
#define regDPIA_MU_TPI_STATUS_DPIA_PORT3                                                                0x13814
#define regDPIA_MU_TPI_STATUS_DPIA_PORT3_BASE_IDX                                                       3
#define regDPIA_MU_TPI_MAX_CREDIT_COUNT                                                                 0x13819
#define regDPIA_MU_TPI_MAX_CREDIT_COUNT_BASE_IDX                                                        3
#define regDPIA_MU_INTERRUPT_STATUS                                                                     0x1381a
#define regDPIA_MU_INTERRUPT_STATUS_BASE_IDX                                                            3
#define regDPIA_MU_INTERRUPT_CTRL                                                                       0x1381b
#define regDPIA_MU_INTERRUPT_CTRL_BASE_IDX                                                              3
#define regDPIA_MU_LOCAL_INTERRUPT_CTRL                                                                 0x1381c
#define regDPIA_MU_LOCAL_INTERRUPT_CTRL_BASE_IDX                                                        3
#define regDPIA_MU_LOCAL_INTERRUPT_ACK                                                                  0x1381d
#define regDPIA_MU_LOCAL_INTERRUPT_ACK_BASE_IDX                                                         3
#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL                                                                  0x1381e
#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL_BASE_IDX                                                         3
#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2                                                                 0x1381f
#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2_BASE_IDX                                                        3
#define regDPIA_MU_RBBMIF_STATUS                                                                        0x13820
#define regDPIA_MU_RBBMIF_STATUS_BASE_IDX                                                               3
#define regDPIA_MU_MICROSECOND_REF_CTRL                                                                 0x13821
#define regDPIA_MU_MICROSECOND_REF_CTRL_BASE_IDX                                                        3
#define regDPIA_MU_PORT_ADP_STATUS                                                                      0x13822
#define regDPIA_MU_PORT_ADP_STATUS_BASE_IDX                                                             3
#define regDPIA_GLUE_CTRL                                                                               0x13823
#define regDPIA_GLUE_CTRL_BASE_IDX                                                                      3
#define regDPIA_PERF_COUNT_CONTROL0                                                                     0x13825
#define regDPIA_PERF_COUNT_CONTROL0_BASE_IDX                                                            3
#define regDPIA_PERF_COUNT_CONTROL1                                                                     0x13826
#define regDPIA_PERF_COUNT_CONTROL1_BASE_IDX                                                            3
#define regDPIA_PERF_COUNT_CONTROL2                                                                     0x13827
#define regDPIA_PERF_COUNT_CONTROL2_BASE_IDX                                                            3
#define regDPIA_PERF_COUNT_CONTROL3                                                                     0x13828
#define regDPIA_PERF_COUNT_CONTROL3_BASE_IDX                                                            3
#define regDPIA_PERF_COUNT_CONTROL4                                                                     0x13829
#define regDPIA_PERF_COUNT_CONTROL4_BASE_IDX                                                            3
#define regDPIA_PERF_COUNT_CONTROL5                                                                     0x1382a
#define regDPIA_PERF_COUNT_CONTROL5_BASE_IDX                                                            3
#define regDPIA_PERF_COUNT_INDEX                                                                        0x1382b
#define regDPIA_PERF_COUNT_INDEX_BASE_IDX                                                               3
#define regDPIA_PERF_COUNT_DATA_LO                                                                      0x1382c
#define regDPIA_PERF_COUNT_DATA_LO_BASE_IDX                                                             3
#define regDPIA_MU_SPARE                                                                                0x1382d
#define regDPIA_MU_SPARE_BASE_IDX                                                                       3


// addressBlock: dce_dc_hda_azcontroller_azdec
// base address: 0x0
#define regAZCONTROLLER1_CORB_WRITE_POINTER                                                             0x0000
#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX                                                    0
#define regAZCONTROLLER1_CORB_READ_POINTER                                                              0x0000
#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX                                                     0
#define regAZCONTROLLER1_CORB_CONTROL                                                                   0x0001
#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX                                                          0
#define regAZCONTROLLER1_CORB_STATUS                                                                    0x0001
#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX                                                           0
#define regAZCONTROLLER1_CORB_SIZE                                                                      0x0001
#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX                                                             0
#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS                                                        0x0002
#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX                                               0
#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS                                                        0x0003
#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX                                               0
#define regAZCONTROLLER1_RIRB_WRITE_POINTER                                                             0x0004
#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX                                                    0
#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT                                                       0x0004
#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX                                              0
#define regAZCONTROLLER1_RIRB_CONTROL                                                                   0x0005
#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX                                                          0
#define regAZCONTROLLER1_RIRB_STATUS                                                                    0x0005
#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX                                                           0
#define regAZCONTROLLER1_RIRB_SIZE                                                                      0x0005
#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX                                                             0
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE                                             0x0006
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                    0
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                        0x0006
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                               0
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                       0x0006
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                              0
#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE                                             0x0007
#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                    0
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS                                                       0x0008
#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX                                              0
#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS                                                0x000a
#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                       0
#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS                                                0x000b
#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                       0
#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS                                                       0x074c
#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                              1


// addressBlock: dce_dc_hda_azendpoint_azdec
// base address: 0x0
#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x0006
#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                      0
#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x0006
#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                     0


// addressBlock: dce_dc_hda_azinputendpoint_azdec
// base address: 0x0
#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                           0x0006
#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                  0
#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                          0x0006
#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                 0


// addressBlock: dce_dc_dio_dio_dpia_mux0_dispdec
// base address: 0x14de0
#define regDIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL                                                           0x1eb8
#define regDIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL_BASE_IDX                                                  2


// addressBlock: dce_dc_dio_dio_dpia_mux1_dispdec
// base address: 0x14de4
#define regDIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL                                                           0x1eb9
#define regDIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL_BASE_IDX                                                  2


// addressBlock: dce_dc_dio_dio_dpia_mux2_dispdec
// base address: 0x14de8
#define regDIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL                                                           0x1eba
#define regDIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL_BASE_IDX                                                  2


// addressBlock: dce_dc_dio_dio_dpia_mux3_dispdec
// base address: 0x14dec
#define regDIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL                                                           0x1ebb
#define regDIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL_BASE_IDX                                                  2


// addressBlock: dce_dc_dio_dig_stream_mapper_dispdec
// base address: 0x0
#define regDIG0_STREAM_MAPPER_CONTROL                                                                   0x1f0d
#define regDIG0_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2
#define regDIG1_STREAM_MAPPER_CONTROL                                                                   0x1f0e
#define regDIG1_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2
#define regDIG2_STREAM_MAPPER_CONTROL                                                                   0x1f0f
#define regDIG2_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2
#define regDIG3_STREAM_MAPPER_CONTROL                                                                   0x1f10
#define regDIG3_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2
#define regDIG4_STREAM_MAPPER_CONTROL                                                                   0x1f11
#define regDIG4_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2


#endif