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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip SoC HDMI/eDP Transmitter Combo PHY
maintainers:
- Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
properties:
compatible:
enum:
- rockchip,rk3588-hdptx-phy
reg:
maxItems: 1
clocks:
items:
- description: Reference clock
- description: APB clock
clock-names:
items:
- const: ref
- const: apb
"#phy-cells":
const: 0
resets:
items:
- description: PHY reset line
- description: APB reset line
- description: INIT reset line
- description: CMN reset line
- description: LANE reset line
- description: ROPLL reset line
- description: LCPLL reset line
reset-names:
items:
- const: phy
- const: apb
- const: init
- const: cmn
- const: lane
- const: ropll
- const: lcpll
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description: Some PHY related data is accessed through GRF regs.
required:
- compatible
- reg
- clocks
- clock-names
- "#phy-cells"
- resets
- reset-names
- rockchip,grf
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
phy@fed60000 {
compatible = "rockchip,rk3588-hdptx-phy";
reg = <0x0 0xfed60000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
clock-names = "ref", "apb";
#phy-cells = <0>;
resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
<&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
<&cru SRST_HDPTX0_LCPLL>;
reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
rockchip,grf = <&hdptxphy_grf>;
};
};
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