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authorKishon Vijay Abraham I <kishon@ti.com>2020-08-21 08:17:45 +0530
committerKishon Vijay Abraham I <kishon@ti.com>2020-08-21 08:17:45 +0530
commit53de14c602744d5e5fc16b4ddf59515c4c185d4a (patch)
tree88b8066899ac8c1442d508a1eb1435b1f739da59
parent6edf34e41110fcf8bdcbff134f24b74a58e8ae8b (diff)
downloadlinux-dt-53de14c602744d5e5fc16b4ddf59515c4c185d4a.tar.gz
system_test: Add overlays for testing PCIe RC and EP
Add overlays for testing PCIe RC and EP
-rw-r--r--arch/arm64/boot/dts/ti/system_test/pcie/pcie_ep/k3-j7200-common-proc-board-pcie-ep.dtso17
-rw-r--r--arch/arm64/boot/dts/ti/system_test/pcie/pcie_ep/k3-j7200-common-proc-board-pcie.dtso25
2 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/system_test/pcie/pcie_ep/k3-j7200-common-proc-board-pcie-ep.dtso b/arch/arm64/boot/dts/ti/system_test/pcie/pcie_ep/k3-j7200-common-proc-board-pcie-ep.dtso
new file mode 100644
index 0000000..83d08b1
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/system_test/pcie/pcie_ep/k3-j7200-common-proc-board-pcie-ep.dtso
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * Overlay for enabling PCIe on k3-j7200-evm board
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+&pcie1_rc {
+ status = "disabled";
+};
+
+&pcie1_ep {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/system_test/pcie/pcie_ep/k3-j7200-common-proc-board-pcie.dtso b/arch/arm64/boot/dts/ti/system_test/pcie/pcie_ep/k3-j7200-common-proc-board-pcie.dtso
new file mode 100644
index 0000000..dcf133a
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/system_test/pcie/pcie_ep/k3-j7200-common-proc-board-pcie.dtso
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * Overlay for enabling PCIe on k3-j7200-evm board
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/mux/mux-j7200-wiz.h>
+
+&serdes_ln_ctrl {
+ idle-states = <SERDES0_LANE0_PCIE1_LANE0>, <SERDES0_LANE1_PCIE1_LANE1>,
+ <SERDES0_LANE2_PCIE1_LANE2>, <SERDES0_LANE3_PCIE1_LANE3>;
+ status = "okay";
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&pcie1_rc {
+ status = "okay";
+};