Fixes for 5.15

Signed-off-by: Sasha Levin <sashal@kernel.org>

2 files changed, 74 insertions, 0 deletions

diff --git a/queue-5.15/clk-sunxi-ng-h6-reparent-cpux-during-pll-cpux-rate-c.patch b/queue-5.15/clk-sunxi-ng-h6-reparent-cpux-during-pll-cpux-rate-c.patch
new file mode 100644
index 0000000000..a7047cff62
--- /dev/null
+++ b/queue-5.15/clk-sunxi-ng-h6-reparent-cpux-during-pll-cpux-rate-c.patch
@@ -0,0 +1,73 @@
+From d17ddc85bf2e63e090d8e55e8293fa08ff0b401e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 13 Oct 2023 20:17:12 +0200
+Subject: clk: sunxi-ng: h6: Reparent CPUX during PLL CPUX rate change
+
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+
+[ Upstream commit 7e91ed763dc07437777bd012af7a2bd4493731ff ]
+
+While PLL CPUX clock rate change when CPU is running from it works in
+vast majority of cases, now and then it causes instability. This leads
+to system crashes and other undefined behaviour. After a lot of testing
+(30+ hours) while also doing a lot of frequency switches, we can't
+observe any instability issues anymore when doing reparenting to stable
+clock like 24 MHz oscillator.
+
+Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
+Reported-by: Chad Wagner <wagnerch42@gmail.com>
+Link: https://forum.libreelec.tv/thread/27295-orange-pi-3-lts-freezes/
+Tested-by: Chad Wagner <wagnerch42@gmail.com>
+Reviewed-by: Chen-Yu Tsai <wens@csie.org>
+Link: https://lore.kernel.org/r/20231013181712.2128037-1-jernej.skrabec@gmail.com
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 19 +++++++++++++++++--
+ 1 file changed, 17 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+index c0800da2fa3d7..736a781e4007a 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+@@ -1181,12 +1181,19 @@ static const u32 usb2_clk_regs[] = {
+ 	SUN50I_H6_USB3_CLK_REG,
+ };
+ 
++static struct ccu_mux_nb sun50i_h6_cpu_nb = {
++	.common		= &cpux_clk.common,
++	.cm		= &cpux_clk.mux,
++	.delay_us       = 1,
++	.bypass_index   = 0, /* index of 24 MHz oscillator */
++};
++
+ static int sun50i_h6_ccu_probe(struct platform_device *pdev)
+ {
+ 	struct resource *res;
+ 	void __iomem *reg;
++	int i, ret;
+ 	u32 val;
+-	int i;
+ 
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	reg = devm_ioremap_resource(&pdev->dev, res);
+@@ -1240,7 +1247,15 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev)
+ 	val |= BIT(24);
+ 	writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG);
+ 
+-	return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc);
++	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc);
++	if (ret)
++		return ret;
++
++	/* Reparent CPU during PLL CPUX rate changes */
++	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
++				  &sun50i_h6_cpu_nb);
++
++	return 0;
+ }
+ 
+ static const struct of_device_id sun50i_h6_ccu_ids[] = {
+-- 
+2.43.0
+
diff --git a/queue-5.15/series b/queue-5.15/series
index 3d916f8066..db32ea601a 100644
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -61,3 +61,4 @@ s390-qeth-fix-kernel-panic-after-setting-hsuid.patch
 drm-panel-ili9341-respect-deferred-probe.patch
 drm-panel-ili9341-use-predefined-error-codes.patch
 net-gro-add-flush-check-in-udp_gro_receive_segment.patch
+clk-sunxi-ng-h6-reparent-cpux-during-pll-cpux-rate-c.patch