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318ec320c6c7 ("drm/i915: Move the min/max scanline sanity check into intel_vblank_evade()")
b5ad7ce024b3 ("drm/i915: Extract intel_vblank_evade()")
b1f9bc3dbe28 ("drm/i915: Include need_vlv_dsi_wa in intel_vblank_evade_ctx")
637bda52bf36 ("drm/i915: Introduce struct intel_vblank_evade_ctx")
bb83f348ead2 ("drm/i915: Reorder drm_vblank_put() vs. need_vlv_dsi_wa")
c045bc428f77 ("drm/i915: Decouple intel_crtc_vblank_evade_scanlines() from atomic commits")
7678e089bd18 ("drm/i915/dsb: Evade transcoder undelayed vblank when using DSB")
16a9359401ed ("drm/i915: Implement transcoder LRR for TGL+")
26f03ef81663 ("drm/i915: Assert that VRR is off during vblank evasion if necessary")
0ce013a4e840 ("drm/i915: Update VRR parameters in fastset")
8f782270cc14 ("drm/i915: Disable VRR during seamless M/N changes")
6a38b36c274f ("drm/i915: Validate that the timings are within the VRR range")
825edc8bc72f ("drm/i915: Adjust seamless_m_n flag behaviour")
691dec86acc3 ("drm/i915: Enable VRR later during fastsets")
f4b0cece716c ("drm/i915: Extract intel_crtc_vblank_evade_scanlines()")
09f390d4e2f3 ("drm/i915: Change intel_pipe_update_{start,end}() calling convention")
927a8e383ab4 ("drm/i915/hsw: s/HSW/HASWELL for platform/subplatform defines")
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