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| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-14 18:05:00 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-15 10:40:29 +0200 |
| commit | 564c836fd945a94b5dd46597d6b7adb464092650 (patch) | |
| tree | 1c8500388f9aada05ebd9958f2b26b30c72b132f | |
| parent | baf5cb30fbd1c22f6aa03c081794c2ee0f5be4da (diff) | |
| download | uml-564c836fd945a94b5dd46597d6b7adb464092650.tar.gz | |
MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.
Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| -rw-r--r-- | arch/mips/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c95fa3a2484cf0..8f328298f8cc87 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -877,6 +877,7 @@ config SNI_RM select I8253 select I8259 select ISA + select MIPS_L1_CACHE_SHIFT_6 select SWAP_IO_SPACE if CPU_BIG_ENDIAN select SYS_HAS_CPU_R4X00 select SYS_HAS_CPU_R5000 |