diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2018-07-26 18:42:54 +0100 |
|---|---|---|
| committer | Ben Hutchings <ben.hutchings@codethink.co.uk> | 2018-08-24 19:18:26 +0100 |
| commit | 84e6938b46176a6754b93b36606b460fe01cd715 (patch) | |
| tree | 0fc94e164297890eda8b1ac4fe2d347ecab79694 | |
| parent | a4cf7e44df164ce4110746d910bbb91269fa6667 (diff) | |
| download | linux-cip-84e6938b46176a6754b93b36606b460fe01cd715.tar.gz | |
ARM: dts: r8a7743: initial SoC device tree
The initial R8A7743 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 34e8d993a68ae459ad98c27afc07647e439deacc)
(cherry-picked again only to get rst node)
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
| -rw-r--r-- | arch/arm/boot/dts/r8a7743.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index bd0c8b243a1699..2931a026fa921a 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -90,6 +90,11 @@ cpus = <&cpu0 &cpu1>; }; + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7743-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; |