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| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2018-08-24 16:13:08 -0400 |
|---|---|---|
| committer | Paul Gortmaker <paul.gortmaker@windriver.com> | 2018-08-24 16:13:08 -0400 |
| commit | 6fc8ce3e90ee7ef713317cf6a5952cbf13e1293a (patch) | |
| tree | dddd41a93525a769e48abd6ceab874c0634c8d8e | |
| parent | 3461403231f0bb0a7186496cb1adf99f7de47da3 (diff) | |
| download | longterm-queue-4.12-6fc8ce3e90ee7ef713317cf6a5952cbf13e1293a.tar.gz | |
arm: refresh
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| -rw-r--r-- | queue/arm64-Call-ARCH_WORKAROUND_2-on-transitions-between-.patch | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/queue/arm64-Call-ARCH_WORKAROUND_2-on-transitions-between-.patch b/queue/arm64-Call-ARCH_WORKAROUND_2-on-transitions-between-.patch index 1214779..cd9d939 100644 --- a/queue/arm64-Call-ARCH_WORKAROUND_2-on-transitions-between-.patch +++ b/queue/arm64-Call-ARCH_WORKAROUND_2-on-transitions-between-.patch @@ -1,4 +1,4 @@ -From 8e2906245f1e3b0d027169d9f2e55ce0548cb96e Mon Sep 17 00:00:00 2001 +From 48264435031e06902ba08f1a42b5652f17d9b5a6 Mon Sep 17 00:00:00 2001 From: Marc Zyngier <marc.zyngier@arm.com> Date: Tue, 29 May 2018 13:11:06 +0100 Subject: [PATCH] arm64: Call ARCH_WORKAROUND_2 on transitions between EL0 and @@ -19,12 +19,13 @@ Reviewed-by: Julien Grall <julien.grall@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> +Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c -index a900befadfe8..c1eda6be7758 100644 +index 33df38d6c353..e4e40628a798 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c -@@ -232,6 +232,30 @@ enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) +@@ -228,6 +228,30 @@ static int qcom_enable_link_stack_sanitization(void *data) } #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ @@ -52,11 +53,11 @@ index a900befadfe8..c1eda6be7758 100644 +} +#endif /* CONFIG_ARM64_SSBD */ + - #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ - .matches = is_affected_midr_range, \ - .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) + #define MIDR_RANGE(model, min, max) \ + .def_scope = SCOPE_LOCAL_CPU, \ + .matches = is_affected_midr_range, \ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S -index ec2ee720e33e..f33e6aed3037 100644 +index 93958d1341bb..f9473efee9c5 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -18,6 +18,7 @@ @@ -100,7 +101,7 @@ index ec2ee720e33e..f33e6aed3037 100644 mov x29, xzr // fp pointed to user-space .else add x21, sp, #S_FRAME_SIZE -@@ -303,6 +323,8 @@ alternative_if ARM64_WORKAROUND_845719 +@@ -301,6 +321,8 @@ alternative_if ARM64_WORKAROUND_845719 alternative_else_nop_endif #endif 3: |