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| author | Alexandru Elisei <alexandru.elisei@arm.com> | 2020-01-31 16:37:26 +0000 |
|---|---|---|
| committer | Andrew Jones <drjones@redhat.com> | 2020-04-03 09:40:33 +0200 |
| commit | c7d0f5d5966bff0db222a2ae57ae1775347e08a4 (patch) | |
| tree | 391f436661b1377a73a1e230feb95126458ba3c8 | |
| parent | f8f1c623b710592167978beaaac605c05fc3c64d (diff) | |
| download | kvm-unit-tests-c7d0f5d5966bff0db222a2ae57ae1775347e08a4.tar.gz | |
arm64: timer: Check the timer interrupt state
We check that the interrupt is pending (or not) at the GIC level, but we
don't check if the timer is asserting it (or not). Let's make sure we don't
run into a strange situation where the two devices' states aren't
synchronized.
Coincidently, the "interrupt signal no longer pending" test fails for
non-emulated timers (i.e, the virtual timer on a non-vhe host) if the
host kernel doesn't have patch 16e604a437c89 ("KVM: arm/arm64: vgic:
Reevaluate level sensitive interrupts on enable").
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
| -rw-r--r-- | arm/timer.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/arm/timer.c b/arm/timer.c index ba7e8c6..35038f2 100644 --- a/arm/timer.c +++ b/arm/timer.c @@ -183,6 +183,13 @@ static void irq_handler(struct pt_regs *regs) info->irq_received = true; } +/* Check that the timer condition is met. */ +static bool timer_pending(struct timer_info *info) +{ + return (info->read_ctl() & ARCH_TIMER_CTL_ENABLE) && + (info->read_ctl() & ARCH_TIMER_CTL_ISTATUS); +} + static enum gic_state gic_timer_state(struct timer_info *info) { enum gic_state state = GIC_STATE_INACTIVE; @@ -220,7 +227,7 @@ static bool test_cval_10msec(struct timer_info *info) info->write_ctl(ARCH_TIMER_CTL_ENABLE); /* Wait for the timer to fire */ - while (!(info->read_ctl() & ARCH_TIMER_CTL_ISTATUS)) + while (!timer_pending(info)) ; /* It fired, check how long it took */ @@ -253,17 +260,17 @@ static void test_timer(struct timer_info *info) /* Enable the timer, but schedule it for much later */ info->write_cval(later); info->write_ctl(ARCH_TIMER_CTL_ENABLE); - report(gic_timer_state(info) == GIC_STATE_INACTIVE, + report(!timer_pending(info) && gic_timer_state(info) == GIC_STATE_INACTIVE, "not pending before"); info->write_cval(now - 1); - report(gic_timer_state(info) == GIC_STATE_PENDING, + report(timer_pending(info) && gic_timer_state(info) == GIC_STATE_PENDING, "interrupt signal pending"); /* Disable the timer again and prepare to take interrupts */ info->write_ctl(0); set_timer_irq_enabled(info, true); - report(gic_timer_state(info) == GIC_STATE_INACTIVE, + report(!timer_pending(info) && gic_timer_state(info) == GIC_STATE_INACTIVE, "interrupt signal no longer pending"); report(test_cval_10msec(info), "latency within 10 ms"); |