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authorxiong <xiong@qca.qualcomm.com>2012-12-03 18:34:45 -0500
committerLuis R. Rodriguez <mcgrof@do-not-panic.com>2012-12-17 13:18:47 -0800
commitf1fb77cb93c8055a7630bfde676e7db87e0272c3 (patch)
tree4565bd6c65c29609add4fa20c3011f2629294f4b
parent7fe03b3180d486072b94a2d3a251546c691d2407 (diff)
downloadalx-f1fb77cb93c8055a7630bfde676e7db87e0272c3.tar.gz
alx: split register definitions to seperated file
this patch include: 1. split register definitions to alx_reg.h. 2. MAC/DMA is reset when PHY link change Down. 3. fixed all error/warnings found by checkpatch. Signed-off-by: xiong <xiong@qca.qualcomm.com> Signed-off-by: Luis R. Rodriguez <mcgrof@do-not-panic.com>
Diffstat
-rw-r--r--src/alx.h672
-rw-r--r--src/alx_ethtool.c84
-rw-r--r--src/alx_hw.c852
-rw-r--r--src/alx_hw.h2688
-rw-r--r--src/alx_main.c1367
-rw-r--r--src/alx_reg.h2129
6 files changed, 4124 insertions, 3668 deletions
diff --git a/src/alx.h b/src/alx.h
index bd0fa1c..c6ee913 100644
--- a/src/alx.h
+++ b/src/alx.h
@@ -17,485 +17,91 @@
#ifndef _ALX_H_
#define _ALX_H_
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/ip.h>
-#include <linux/ipv6.h>
-#include <linux/if_vlan.h>
-#include <linux/mii.h>
-#include <linux/aer.h>
-#include <linux/bitops.h>
-#include <linux/ethtool.h>
-#include <linux/crc32.h>
-#include <linux/mdio.h>
-#include "alx_hw.h"
-
-/* specific error info */
-#define ALX_ERR_SUCCESS 0x0000
-#define ALX_ERR_ALOAD 0x0001
-#define ALX_ERR_RSTMAC 0x0002
-#define ALX_ERR_PARM 0x0003
-#define ALX_ERR_MIIBUSY 0x0004
-
-
-/* Transmit Packet Descriptor, contains 4 32-bit words.
- *
- * 31 16 0
- * +----------------+----------------+
- * | vlan-tag | buf length |
- * +----------------+----------------+
- * | Word 1 |
- * +----------------+----------------+
- * | Word 2: buf addr lo |
- * +----------------+----------------+
- * | Word 3: buf addr hi |
- * +----------------+----------------+
- *
- * Word 2 and 3 combine to form a 64-bit buffer address
- *
- * Word 1 has three forms, depending on the state of bit 8/12/13:
- * if bit8 =='1', the definition is just for custom checksum offload.
- * if bit8 == '0' && bit12 == '1' && bit13 == '1', the *FIRST* descriptor
- * for the skb is special for LSO V2, Word 2 become total skb length ,
- * Word 3 is meaningless.
- * other condition, the definition is for general skb or ip/tcp/udp
- * checksum or LSO(TSO) offload.
- *
- * Here is the depiction:
- *
- * 0-+ 0-+
- * 1 | 1 |
- * 2 | 2 |
- * 3 | Payload offset 3 | L4 header offset
- * 4 | (7:0) 4 | (7:0)
- * 5 | 5 |
- * 6 | 6 |
- * 7-+ 7-+
- * 8 Custom csum enable = 1 8 Custom csum enable = 0
- * 9 General IPv4 checksum 9 General IPv4 checksum
- * 10 General TCP checksum 10 General TCP checksum
- * 11 General UDP checksum 11 General UDP checksum
- * 12 Large Send Segment enable 12 Large Send Segment enable
- * 13 Large Send Segment type 13 Large Send Segment type
- * 14 VLAN tagged 14 VLAN tagged
- * 15 Insert VLAN tag 15 Insert VLAN tag
- * 16 IPv4 packet 16 IPv4 packet
- * 17 Ethernet frame type 17 Ethernet frame type
- * 18-+ 18-+
- * 19 | 19 |
- * 20 | 20 |
- * 21 | Custom csum offset 21 |
- * 22 | (25:18) 22 |
- * 23 | 23 | MSS (30:18)
- * 24 | 24 |
- * 25-+ 25 |
- * 26-+ 26 |
- * 27 | 27 |
- * 28 | Reserved 28 |
- * 29 | 29 |
- * 30-+ 30-+
- * 31 End of packet 31 End of packet
- */
-
-struct tpd_desc {
- __le32 word0;
- __le32 word1;
- union {
- __le64 addr;
- struct {
- __le32 pkt_len;
- __le32 resvd;
- } l;
- } adrl;
-} __packed;
-
-/* tpd word 0 */
-#define TPD_BUFLEN_MASK 0xFFFF
-#define TPD_BUFLEN_SHIFT 0
-#define TPD_VLTAG_MASK 0xFFFF
-#define TPD_VLTAG_SHIFT 16
-
-/* tpd word 1 */
-#define TPD_CXSUMSTART_MASK 0x00FF
-#define TPD_CXSUMSTART_SHIFT 0
-#define TPD_L4HDROFFSET_MASK 0x00FF
-#define TPD_L4HDROFFSET_SHIFT 0
-#define TPD_CXSUM_EN_MASK 0x0001
-#define TPD_CXSUM_EN_SHIFT 8
-#define TPD_IP_XSUM_MASK 0x0001
-#define TPD_IP_XSUM_SHIFT 9
-#define TPD_TCP_XSUM_MASK 0x0001
-#define TPD_TCP_XSUM_SHIFT 10
-#define TPD_UDP_XSUM_MASK 0x0001
-#define TPD_UDP_XSUm_SHIFT 11
-#define TPD_LSO_EN_MASK 0x0001
-#define TPD_LSO_EN_SHIFT 12
-#define TPD_LSO_V2_MASK 0x0001
-#define TPD_LSO_V2_SHIFT 13
-#define TPD_VLTAGGED_MASK 0x0001
-#define TPD_VLTAGGED_SHIFT 14
-#define TPD_INS_VLTAG_MASK 0x0001
-#define TPD_INS_VLTAG_SHIFT 15
-#define TPD_IPV4_MASK 0x0001
-#define TPD_IPV4_SHIFT 16
-#define TPD_ETHTYPE_MASK 0x0001
-#define TPD_ETHTYPE_SHIFT 17
-#define TPD_CXSUMOFFSET_MASK 0x00FF
-#define TPD_CXSUMOFFSET_SHIFT 18
-#define TPD_MSS_MASK 0x1FFF
-#define TPD_MSS_SHIFT 18
-#define TPD_EOP_MASK 0x0001
-#define TPD_EOP_SHIFT 31
-
-#define DESC_GET(_x, _name) ((_x) >> _name##SHIFT & _name##MASK)
-
-/* Receive Free Descriptor */
-struct rfd_desc {
- __le64 addr; /* data buffer address, length is
- * declared in register --- every
- * buffer has the same size
- */
-} __packed;
-
-/* Receive Return Descriptor, contains 4 32-bit words.
- *
- * 31 16 0
- * +----------------+----------------+
- * | Word 0 |
- * +----------------+----------------+
- * | Word 1: RSS Hash value |
- * +----------------+----------------+
- * | Word 2 |
- * +----------------+----------------+
- * | Word 3 |
- * +----------------+----------------+
- *
- * Word 0 depiction & Word 2 depiction:
- *
- * 0--+ 0--+
- * 1 | 1 |
- * 2 | 2 |
- * 3 | 3 |
- * 4 | 4 |
- * 5 | 5 |
- * 6 | 6 |
- * 7 | IP payload checksum 7 | VLAN tag
- * 8 | (15:0) 8 | (15:0)
- * 9 | 9 |
- * 10 | 10 |
- * 11 | 11 |
- * 12 | 12 |
- * 13 | 13 |
- * 14 | 14 |
- * 15-+ 15-+
- * 16-+ 16-+
- * 17 | Number of RFDs 17 |
- * 18 | (19:16) 18 |
- * 19-+ 19 | Protocol ID
- * 20-+ 20 | (23:16)
- * 21 | 21 |
- * 22 | 22 |
- * 23 | 23-+
- * 24 | 24 | Reserved
- * 25 | Start index of RFD-ring 25-+
- * 26 | (31:20) 26 | RSS Q-num (27:25)
- * 27 | 27-+
- * 28 | 28-+
- * 29 | 29 | RSS Hash algorithm
- * 30 | 30 | (31:28)
- * 31-+ 31-+
- *
- * Word 3 depiction:
- *
- * 0--+
- * 1 |
- * 2 |
- * 3 |
- * 4 |
- * 5 |
- * 6 |
- * 7 | Packet length (include FCS)
- * 8 | (13:0)
- * 9 |
- * 10 |
- * 11 |
- * 12 |
- * 13-+
- * 14 L4 Header checksum error
- * 15 IPv4 checksum error
- * 16 VLAN tagged
- * 17-+
- * 18 | Protocol ID (19:17)
- * 19-+
- * 20 Receive error summary
- * 21 FCS(CRC) error
- * 22 Frame alignment error
- * 23 Truncated packet
- * 24 Runt packet
- * 25 Incomplete packet due to insufficient rx-desc
- * 26 Broadcast packet
- * 27 Multicast packet
- * 28 Ethernet type (EII or 802.3)
- * 29 FIFO overflow
- * 30 Length error (for 802.3, length field mismatch with actual len)
- * 31 Updated, indicate to driver that this RRD is refreshed.
- */
-
-struct rrd_desc {
- __le32 word0;
- __le32 rss_hash;
- __le32 word2;
- __le32 word3;
-} __packed;
-
-/* rrd word 0 */
-#define RRD_XSUM_MASK 0xFFFF
-#define RRD_XSUM_SHIFT 0
-#define RRD_NOR_MASK 0x000F
-#define RRD_NOR_SHIFT 16
-#define RRD_SI_MASK 0x0FFF
-#define RRD_SI_SHIFT 20
-
-/* rrd word 2 */
-#define RRD_VLTAG_MASK 0xFFFF
-#define RRD_VLTAG_SHIFT 0
-#define RRD_PID_MASK 0x00FF
-#define RRD_PID_SHIFT 16
-#define RRD_PID_NONIP 0 /* non-ip packet */
-#define RRD_PID_IPV4 1 /* ipv4(only) */
-#define RRD_PID_IPV6TCP 2 /* tcp/ipv6 */
-#define RRD_PID_IPV4TCP 3 /* tcp/ipv4 */
-#define RRD_PID_IPV6UDP 4 /* udp/ipv6 */
-#define RRD_PID_IPV4UDP 5 /* udp/ipv4 */
-#define RRD_PID_IPV6 6 /* ipv6(only) */
-#define RRD_PID_LLDP 7 /* LLDP packet */
-#define RRD_PID_1588 8 /* 1588 packet */
-#define RRD_RSSQ_MASK 0x0007
-#define RRD_RSSQ_SHIFT 25
-#define RRD_RSSALG_MASK 0x000F
-#define RRD_RSSALG_SHIFT 28
-#define RRD_RSSALG_TCPV6 0x1 /* TCP(IPV6) hash algorithm */
-#define RRD_RSSALG_IPV6 0x2 /* IPV6 hash algorithm */
-#define RRD_RSSALG_TCPV4 0x4 /* TCP(IPV4) hash algorithm */
-#define RRD_RSSALG_IPV4 0x8 /* IPV4 hash algorithm */
-
-/* rrd word 3 */
-#define RRD_PKTLEN_MASK 0x3FFF
-#define RRD_PKTLEN_SHIFT 0
-#define RRD_ERR_L4_MASK 0x0001
-#define RRD_ERR_L4_SHIFT 14
-#define RRD_ERR_IPV4_MASK 0x0001
-#define RRD_ERR_IPV4_SHIFT 15
-#define RRD_VLTAGGED_MASK 0x0001
-#define RRD_VLTAGGED_SHIFT 16
-#define RRD_OLD_PID_MASK 0x0007
-#define RRD_OLD_PID_SHIFT 17
-#define RRD_ERR_RES_MASK 0x0001
-#define RRD_ERR_RES_SHIFT 20
-#define RRD_ERR_FCS_MASK 0x0001
-#define RRD_ERR_FCS_SHIFT 21
-#define RRD_ERR_FAE_MASK 0x0001
-#define RRD_ERR_FAE_SHIFT 22
-#define RRD_ERR_TRUNC_MASK 0x0001
-#define RRD_ERR_TRUNC_SHIFT 23
-#define RRD_ERR_RUNT_MASK 0x0001
-#define RRD_ERR_RUNT_SHIFT 24
-#define RRD_ERR_ICMP_MASK 0x0001
-#define RRD_ERR_ICMP_SHIFT 25
-#define RRD_BCAST_MASK 0x0001
-#define RRD_BCAST_SHIFT 26
-#define RRD_MCAST_MASK 0x0001
-#define RRD_MCAST_SHIFT 27
-#define RRD_ETHTYPE_MASK 0x0001
-#define RRD_ETHTYPE_SHIFT 28
-#define RRD_ERR_FIFOV_MASK 0x0001
-#define RRD_ERR_FIFOV_SHIFT 29
-#define RRD_ERR_LEN_MASK 0x0001
-#define RRD_ERR_LEN_SHIFT 30
-#define RRD_UPDATED_MASK 0x0001
-#define RRD_UPDATED_SHIFT 31
-
-
-/* Statistics counters collected by the MAC */
-struct alx_hw_stats {
- /* rx */
- unsigned long rx_ok;
- unsigned long rx_bcast;
- unsigned long rx_mcast;
- unsigned long rx_pause;
- unsigned long rx_ctrl;
- unsigned long rx_fcs_err;
- unsigned long rx_len_err;
- unsigned long rx_byte_cnt;
- unsigned long rx_runt;
- unsigned long rx_frag;
- unsigned long rx_sz_64B;
- unsigned long rx_sz_127B;
- unsigned long rx_sz_255B;
- unsigned long rx_sz_511B;
- unsigned long rx_sz_1023B;
- unsigned long rx_sz_1518B;
- unsigned long rx_sz_max;
- unsigned long rx_ov_sz;
- unsigned long rx_ov_rxf;
- unsigned long rx_ov_rrd;
- unsigned long rx_align_err;
- unsigned long rx_bc_byte_cnt;
- unsigned long rx_mc_byte_cnt;
- unsigned long rx_err_addr;
-
- /* tx */
- unsigned long tx_ok;
- unsigned long tx_bcast;
- unsigned long tx_mcast;
- unsigned long tx_pause;
- unsigned long tx_exc_defer;
- unsigned long tx_ctrl;
- unsigned long tx_defer;
- unsigned long tx_byte_cnt;
- unsigned long tx_sz_64B;
- unsigned long tx_sz_127B;
- unsigned long tx_sz_255B;
- unsigned long tx_sz_511B;
- unsigned long tx_sz_1023B;
- unsigned long tx_sz_1518B;
- unsigned long tx_sz_max;
- unsigned long tx_single_col;
- unsigned long tx_multi_col;
- unsigned long tx_late_col;
- unsigned long tx_abort_col;
- unsigned long tx_underrun;
- unsigned long tx_trd_eop;
- unsigned long tx_len_err;
- unsigned long tx_trunc;
- unsigned long tx_bc_byte_cnt;
- unsigned long tx_mc_byte_cnt;
- unsigned long update;
-};
-
-#define SPEED_0 0
-#define HALF_DUPLEX 1
-#define FULL_DUPLEX 2
-#define ALX_MAX_SETUP_LNK_CYCLE 50
-
-#define ALX_SPEED_TO_ETHADV(_speed) (\
-(_speed) == SPEED_1000 + FULL_DUPLEX ? ADVERTISED_1000baseT_Full : \
-(_speed) == SPEED_100 + FULL_DUPLEX ? ADVERTISED_100baseT_Full : \
-(_speed) == SPEED_100 + HALF_DUPLEX ? ADVERTISED_10baseT_Half : \
-(_speed) == SPEED_10 + FULL_DUPLEX ? ADVERTISED_10baseT_Full : \
-(_speed) == SPEED_10 + HALF_DUPLEX ? ADVERTISED_10baseT_Half : \
-0)
-
-
-#define ALX_DEF_RXBUF_SIZE 1536
-#define ALX_MAX_JUMBO_PKT_SIZE (9*1024)
-#define ALX_MAX_TSO_PKT_SIZE (7*1024)
-#define ALX_MAX_FRAME_SIZE ALX_MAX_JUMBO_PKT_SIZE
-#define ALX_MIN_FRAME_SIZE 68
-#define ALX_RAW_MTU(_mtu) (_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
-
-#define ALX_MAX_RX_QUEUES 8 /* for RSS */
-#define ALX_MAX_TX_QUEUES 4 /* multiple tx queues */
-#define ALX_MAX_HANDLED_INTRS 5
-
-#define ALX_ISR_MISC (\
- ALX_ISR_PCIE_LNKDOWN | \
- ALX_ISR_PHY | \
- ALX_ISR_DMAW | \
- ALX_ISR_DMAR | \
- ALX_ISR_SMB | \
- ALX_ISR_MANU | \
- ALX_ISR_TIMER | \
- ALX_ISR_RXF_OV | \
- ALX_ISR_TXF_UR | \
- ALX_ISR_RFD_UR)
-
-#define ALX_ISR_FATAL (\
- ALX_ISR_PCIE_LNKDOWN | \
- ALX_ISR_DMAW | \
- ALX_ISR_DMAR)
-
-#define ALX_ISR_ALERT (\
- ALX_ISR_RXF_OV | \
- ALX_ISR_TXF_UR | \
- ALX_ISR_RFD_UR)
-
-#define ALX_ISR_ALL_QUEUES (\
- ALX_ISR_TX_Q0 | \
- ALX_ISR_TX_Q1 | \
- ALX_ISR_TX_Q2 | \
- ALX_ISR_TX_Q3 | \
- ALX_ISR_RX_Q0 | \
- ALX_ISR_RX_Q1 | \
- ALX_ISR_RX_Q2 | \
- ALX_ISR_RX_Q3 | \
- ALX_ISR_RX_Q4 | \
- ALX_ISR_RX_Q5 | \
- ALX_ISR_RX_Q6 | \
- ALX_ISR_RX_Q7)
-
-#define ALX_MAX_MSIX_INTRS 16 /* maximum interrupt vectors for msix */
#define ALX_WATCHDOG_TIME (5 * HZ)
-/*
- * alx_ring_header is a single, contiguous block of memory space
+/* alx_ring_header is a single, contiguous block of memory space
* used by the three descriptor rings (tpd, rfd, rrd)
*/
struct alx_ring_header {
- void *desc; /* virt addr */
- dma_addr_t dma; /* phy addr */
- u32 size; /* length in bytes */
+ /* virt addr */
+ void *desc;
+ /* phy addr */
+ dma_addr_t dma;
+ u32 size;
};
-/*
- * alx_buffer wraps around a pointer to a socket buffer
+/* alx_buffer wraps around a pointer to a socket buffer
* so a DMA physical address can be stored along with the skb
*/
struct alx_buffer {
- struct sk_buff *skb; /* socket buffer */
- DEFINE_DMA_UNMAP_ADDR(dma); /* DMA address */
- DEFINE_DMA_UNMAP_LEN(size); /* buffer size */
- u16 flags; /* information of this buffer */
+ struct sk_buff *skb;
+ /* DMA address */
+ DEFINE_DMA_UNMAP_ADDR(dma);
+ /* buffer size */
+ DEFINE_DMA_UNMAP_LEN(size);
+ /* information of this buffer */
+ u16 flags;
};
#define ALX_BUF_TX_FIRSTFRAG 0x1
/* rx queue */
struct alx_rx_queue {
struct net_device *netdev;
- struct device *dev; /* device pointer for dma operation */
- struct rrd_desc *rrd_hdr; /* rrd ring virtual addr */
- dma_addr_t rrd_dma; /* rrd ring physical addr */
- struct rfd_desc *rfd_hdr; /* rfd ring virtual addr */
- dma_addr_t rfd_dma; /* rfd ring physical addr */
- struct alx_buffer *bf_info; /* info for rx-skbs */
-
- u16 count; /* number of ring elements */
- u16 pidx; /* rfd producer index */
- u16 cidx; /* rfd consumer index */
+ /* device pointer for dma operation */
+ struct device *dev;
+ /* rrd ring virtual addr */
+ struct rrd_desc *rrd_hdr;
+ /* rrd ring physical addr */
+ dma_addr_t rrd_dma;
+ /* rfd ring virtual addr */
+ struct rfd_desc *rfd_hdr;
+ /* rfd ring physical addr */
+ dma_addr_t rfd_dma;
+ /* info for rx-skbs */
+ struct alx_buffer *bf_info;
+
+ /* number of ring elements */
+ u16 count;
+ /* rfd producer index */
+ u16 pidx;
+ /* rfd consumer index */
+ u16 cidx;
u16 rrd_cidx;
- u16 p_reg; /* register saving producer index */
- u16 c_reg; /* register saving consumer index */
- u16 qidx; /* queue index */
+ /* register saving producer index */
+ u16 p_reg;
+ /* register saving consumer index */
+ u16 c_reg;
+ /* queue index */
+ u16 qidx;
unsigned long flag;
struct sk_buff_head list;
};
#define ALX_RQ_USING 1
#define ALX_RX_ALLOC_THRESH 32
+
/* tx queue */
struct alx_tx_queue {
struct net_device *netdev;
- struct device *dev; /* device pointer for dma operation */
- struct tpd_desc *tpd_hdr; /* tpd ring virtual addr */
- dma_addr_t tpd_dma; /* tpd ring physical addr */
- struct alx_buffer *bf_info; /* info for tx-skbs pending on HW */
- u16 count; /* number of ring elements */
- u16 pidx; /* producer index */
- atomic_t cidx; /* consumer index */
- u16 p_reg; /* register saving producer index */
- u16 c_reg; /* register saving consumer index */
- u16 qidx; /* queue index */
+ /* device pointer for dma operation */
+ struct device *dev;
+ /* tpd ring virtual addr */
+ struct tpd_desc *tpd_hdr;
+ dma_addr_t tpd_dma;
+ /* info for tx-skbs pending on HW */
+ struct alx_buffer *bf_info;
+ /* number of ring elements */
+ u16 count;
+ /* producer index */
+ u16 pidx;
+ /* consumer index */
+ atomic_t cidx;
+ /* register saving producer index */
+ u16 p_reg;
+ /* register saving consumer index */
+ u16 c_reg;
+ /* queue index */
+ u16 qidx;
};
#define ALX_TX_WAKEUP_THRESH(_tq) ((_tq)->count / 4)
@@ -512,46 +118,36 @@ struct alx_napi {
};
enum ALX_FLAGS {
- ALX_FLAG_CAP_GIGA = 0, /* support gigabit speed */
- ALX_FLAG_CAP_PTP, /* support 1588 */
- ALX_FLAG_CAP_AZ, /* support EEE */
- ALX_FLAG_CAP_L0S, /* support ASPM L0S */
- ALX_FLAG_CAP_L1, /* support ASPM L1 */
- ALX_FLAG_CAP_SWOI, /* support SWOI feature */
- ALX_FLAG_CAP_RSS, /* support RSS */
- ALX_FLAG_CAP_MSIX, /* support MSI-X */
- ALX_FLAG_CAP_MTQ, /* support Multi-TX-Q */
- ALX_FLAG_CAP_MRQ, /* support Multi-RX-Q */
- ALX_FLAG_USING_MSIX, /* using MSI-X */
- ALX_FLAG_USING_MSI, /* using MSI */
- ALX_FLAG_RESETING, /* hw is in reset process */
- ALX_FLAG_TESTING, /* self testing */
- ALX_FLAG_HALT, /* hw is down */
- ALX_FLAG_FPGA, /* FPGA, not ASIC */
- ALX_FLAG_TASK_PENDING, /* work is pending */
- ALX_FLAG_TASK_CHK_LINK, /* check PHY link */
- ALX_FLAG_TASK_RESET, /* reset whole chip */
- ALX_FLAG_TASK_UPDATE_SMB, /* update SMB */
+ ALX_FLAG_USING_MSIX = 0,
+ ALX_FLAG_USING_MSI,
+ ALX_FLAG_RESETING,
+ ALX_FLAG_TESTING,
+ ALX_FLAG_HALT,
+ ALX_FLAG_FPGA,
+ ALX_FLAG_TASK_PENDING,
+ ALX_FLAG_TASK_CHK_LINK,
+ ALX_FLAG_TASK_RESET,
+ ALX_FLAG_TASK_UPDATE_SMB,
ALX_FLAG_NUMBER_OF_FLAGS,
};
+
+struct alx_hw;
/*
*board specific private data structure
*/
struct alx_adapter {
- u8 __iomem *hw_addr; /* memory mapped PCI base address */
-
- u8 mac_addr[ETH_ALEN]; /* current mac address */
- u8 perm_addr[ETH_ALEN]; /* permanent mac address */
-
struct net_device *netdev;
struct pci_dev *pdev;
- u16 bd_number; /* board number;*/
+ struct alx_hw hw;
+
+ u16 bd_number;
- unsigned int nr_vec; /* totally msix vectors */
- struct msix_entry *msix_ent; /* msix entries */
+ /* totally msix vectors */
+ int nr_vec;
+ struct msix_entry *msix_ent;
/* all descriptor memory */
struct alx_ring_header ring_header;
@@ -560,104 +156,34 @@ struct alx_adapter {
int rxbuf_size;
struct alx_napi *qnapi[8];
- int nr_txq; /* number of napi for TX-Q */
- int nr_rxq; /* number of napi for RX-Q */
- int nr_napi; /* total napi for TX-Q/RX-Q */
- u16 mtu; /* MTU */
- u16 imt; /* interrupt moderation timer */
- u8 dma_chnl; /* number of DMA channels */
- u8 max_dma_chnl;
- u32 rx_ctrl; /* main rx control */
- u32 mc_hash[2]; /* multicast addr hash table */
-
- u8 rss_key[40]; /* RSS hash algorithm key */
- u32 rss_idt[32]; /* RSS indirection table */
- u16 rss_idt_size; /* RSS indirection table size */
- u8 rss_hash_type; /* RSS hash type */
-
- u32 wrr[ALX_MAX_TX_QUEUES]; /* weight round robin
- * for multiple-tx-Q */
- u32 wrr_ctrl; /* prioirty control */
-
- u32 imask; /* interrupt mask for ALX_IMR */
- u32 smb_timer; /* statistic counts refresh
- * timeout, million-seconds */
- spinlock_t smb_lock; /* lock for updating stats */
-
- bool link_up; /* link up flag */
- u16 link_speed; /* current link speed */
- u8 link_duplex; /* current link duplex */
-
- u32 adv_cfg; /* auto-neg advertisement
- * or force mode config
- */
- u8 flowctrl; /* flow control */
-
- struct work_struct task; /* any delayed work */
- struct net_device_stats net_stats; /* statistics counters */
- struct alx_hw_stats hw_stats; /* statistics counters,
- * same order with hw
- */
- u32 sleep_ctrl; /* control used when sleep */
- atomic_t irq_sem; /* interrupt sync */
- u16 msg_enable; /* msg level */
-
- DECLARE_BITMAP(flags, ALX_FLAG_NUMBER_OF_FLAGS);
-
- spinlock_t mdio_lock; /* used for MII bus access */
- struct mdio_if_info mdio;
- u16 phy_id[2];
-
- bool lnk_patch; /* PHY link patch flag */
- bool hib_patch; /* PHY hibernation patch flag */
+ /* number of napi for TX-Q */
+ int nr_txq;
+ /* number of napi for RX-Q */
+ int nr_rxq;
+ /* number independent hw RX-Q */
+ int nr_hwrxq;
+ /* total napi for TX-Q/RX-Q */
+ int nr_napi;
+
+ /* lock for updating stats */
+ spinlock_t smb_lock;
+
+ struct work_struct task;
+ struct net_device_stats net_stats;
+ atomic_t irq_sem;
+ u16 msg_enable;
+
+ unsigned long flags;
};
-#define ALX_VID(_a) ((_a)->pdev->vendor)
-#define ALX_DID(_a) ((_a)->pdev->device)
-#define ALX_SUB_VID(_a) ((_a)->pdev->subsystem_vendor)
-#define ALX_SUB_DID(_a) ((_a)->pdev->subsystem_device)
-#define ALX_REVID(_a) ((_a)->pdev->revision >> ALX_PCI_REVID_SHIFT)
-#define ALX_WITH_CR(_a) ((_a)->pdev->revision & 1)
#define ALX_FLAG(_adpt, _FLAG) (\
- test_bit(ALX_FLAG_##_FLAG, (_adpt)->flags))
+ test_bit(ALX_FLAG_##_FLAG, &(_adpt)->flags))
#define ALX_FLAG_SET(_adpt, _FLAG) (\
- set_bit(ALX_FLAG_##_FLAG, (_adpt)->flags))
+ set_bit(ALX_FLAG_##_FLAG, &(_adpt)->flags))
#define ALX_FLAG_CLEAR(_adpt, _FLAG) (\
- clear_bit(ALX_FLAG_##_FLAG, (_adpt)->flags))
-
-
-/* write to 8bit register via pci memory space */
-#define ALX_MEM_W8(s, reg, val) (writeb((val), ((s)->hw_addr + reg)))
-
-/* read from 8bit register via pci memory space */
-#define ALX_MEM_R8(s, reg, pdat) (\
- *(u8 *)(pdat) = readb((s)->hw_addr + reg))
-
-/* write to 16bit register via pci memory space */
-#define ALX_MEM_W16(s, reg, val) (writew((val), ((s)->hw_addr + reg)))
-
-/* read from 16bit register via pci memory space */
-#define ALX_MEM_R16(s, reg, pdat) (\
- *(u16 *)(pdat) = readw((s)->hw_addr + reg))
-
-/* write to 32bit register via pci memory space */
-#define ALX_MEM_W32(s, reg, val) (writel((val), ((s)->hw_addr + reg)))
-
-/* read from 32bit register via pci memory space */
-#define ALX_MEM_R32(s, reg, pdat) (\
- *(u32 *)(pdat) = readl((s)->hw_addr + reg))
-
-/* read from 16bit register via pci config space */
-#define ALX_CFG_R16(s, reg, pdat) (\
- pci_read_config_word((s)->pdev, (reg), (pdat)))
-
-/* write to 16bit register via pci config space */
-#define ALX_CFG_W16(s, reg, val) (\
- pci_write_config_word((s)->pdev, (reg), (val)))
+ clear_bit(ALX_FLAG_##_FLAG, &(_adpt)->flags))
-/* flush regs */
-#define ALX_MEM_FLUSH(s) (readl((s)->hw_addr))
/* needed by alx_ethtool.c */
extern void alx_reinit(struct alx_adapter *adpt);
@@ -665,4 +191,4 @@ extern void __devinit alx_set_ethtool_ops(struct net_device *dev);
extern char alx_drv_name[];
-#endif /* _ALX_H_ */
+#endif
diff --git a/src/alx_ethtool.c b/src/alx_ethtool.c
index d32372c..0c04f56 100644
--- a/src/alx_ethtool.c
+++ b/src/alx_ethtool.c
@@ -15,14 +15,20 @@
*/
#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
#include <linux/ethtool.h>
+#include <linux/mdio.h>
+#include "alx_reg.h"
+#include "alx_hw.h"
#include "alx.h"
static int alx_get_settings(struct net_device *netdev,
struct ethtool_cmd *ecmd)
{
struct alx_adapter *adpt = netdev_priv(netdev);
+ struct alx_hw *hw = &adpt->hw;
ecmd->supported = (SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
@@ -30,22 +36,22 @@ static int alx_get_settings(struct net_device *netdev,
SUPPORTED_100baseT_Full |
SUPPORTED_Autoneg |
SUPPORTED_TP);
- if (ALX_FLAG(adpt, CAP_GIGA))
+ if (ALX_CAP(hw, GIGA))
ecmd->supported |= SUPPORTED_1000baseT_Full;
ecmd->advertising = ADVERTISED_TP;
- if (adpt->adv_cfg & ADVERTISED_Autoneg)
- ecmd->advertising |= adpt->adv_cfg;
+ if (hw->adv_cfg & ADVERTISED_Autoneg)
+ ecmd->advertising |= hw->adv_cfg;
ecmd->port = PORT_TP;
ecmd->phy_address = 0;
- ecmd->autoneg = (adpt->adv_cfg & ADVERTISED_Autoneg) ?
+ ecmd->autoneg = (hw->adv_cfg & ADVERTISED_Autoneg) ?
AUTONEG_ENABLE : AUTONEG_DISABLE;
ecmd->transceiver = XCVR_INTERNAL;
- if (adpt->link_up) {
- ethtool_cmd_speed_set(ecmd, adpt->link_speed);
- ecmd->duplex = adpt->link_duplex;
+ if (hw->link_up) {
+ ethtool_cmd_speed_set(ecmd, hw->link_speed);
+ ecmd->duplex = hw->link_duplex;
} else {
ethtool_cmd_speed_set(ecmd, -1);
ecmd->duplex = -1;
@@ -58,10 +64,11 @@ static int alx_set_settings(struct net_device *netdev,
struct ethtool_cmd *ecmd)
{
struct alx_adapter *adpt = netdev_priv(netdev);
+ struct alx_hw *hw = &adpt->hw;
u32 adv_cfg;
int err = 0;
- while (test_and_set_bit(ALX_FLAG_RESETING, adpt->flags))
+ while (test_and_set_bit(ALX_FLAG_RESETING, &adpt->flags))
msleep(20);
if (ecmd->autoneg == AUTONEG_ENABLE) {
@@ -71,7 +78,7 @@ static int alx_set_settings(struct net_device *netdev,
return -EINVAL;
}
adv_cfg = ecmd->advertising | ADVERTISED_Autoneg;
- } else { /* force mode */
+ } else {
int speed = ethtool_cmd_speed(ecmd);
switch (speed + ecmd->duplex) {
@@ -94,8 +101,8 @@ static int alx_set_settings(struct net_device *netdev,
}
if (!err) {
- adpt->adv_cfg = adv_cfg;
- err = alx_setup_speed_duplex(adpt, adv_cfg, adpt->flowctrl);
+ hw->adv_cfg = adv_cfg;
+ err = alx_setup_speed_duplex(hw, adv_cfg, hw->flowctrl);
if (err) {
dev_warn(&adpt->pdev->dev,
"config PHY speed/duplex failed,err=%d\n",
@@ -113,19 +120,20 @@ static void alx_get_pauseparam(struct net_device *netdev,
struct ethtool_pauseparam *pause)
{
struct alx_adapter *adpt = netdev_priv(netdev);
+ struct alx_hw *hw = &adpt->hw;
- if (adpt->flowctrl & ALX_FC_ANEG &&
- adpt->adv_cfg & ADVERTISED_Autoneg)
+ if (hw->flowctrl & ALX_FC_ANEG &&
+ hw->adv_cfg & ADVERTISED_Autoneg)
pause->autoneg = AUTONEG_ENABLE;
else
pause->autoneg = AUTONEG_DISABLE;
- if (adpt->flowctrl & ALX_FC_TX)
+ if (hw->flowctrl & ALX_FC_TX)
pause->tx_pause = 1;
else
pause->tx_pause = 0;
- if (adpt->flowctrl & ALX_FC_RX)
+ if (hw->flowctrl & ALX_FC_RX)
pause->rx_pause = 1;
else
pause->rx_pause = 0;
@@ -136,6 +144,7 @@ static int alx_set_pauseparam(struct net_device *netdev,
struct ethtool_pauseparam *pause)
{
struct alx_adapter *adpt = netdev_priv(netdev);
+ struct alx_hw *hw = &adpt->hw;
int err = 0;
bool reconfig_phy = false;
u8 fc = 0;
@@ -147,20 +156,20 @@ static int alx_set_pauseparam(struct net_device *netdev,
if (pause->autoneg)
fc |= ALX_FC_ANEG;
- while (test_and_set_bit(ALX_FLAG_RESETING, adpt->flags))
+ while (test_and_set_bit(ALX_FLAG_RESETING, &adpt->flags))
msleep(20);
/* restart auto-neg for auto-mode */
- if (adpt->adv_cfg & ADVERTISED_Autoneg) {
- if (!((fc ^ adpt->flowctrl) & ALX_FC_ANEG))
- reconfig_phy = true; /* auto/force change */
- if (fc & adpt->flowctrl & ALX_FC_ANEG &&
- (fc ^ adpt->flowctrl) & (ALX_FC_RX | ALX_FC_TX))
+ if (hw->adv_cfg & ADVERTISED_Autoneg) {
+ if (!((fc ^ hw->flowctrl) & ALX_FC_ANEG))
+ reconfig_phy = true;
+ if (fc & hw->flowctrl & ALX_FC_ANEG &&
+ (fc ^ hw->flowctrl) & (ALX_FC_RX | ALX_FC_TX))
reconfig_phy = true;
}
if (reconfig_phy) {
- err = alx_setup_speed_duplex(adpt, adpt->adv_cfg, fc);
+ err = alx_setup_speed_duplex(hw, hw->adv_cfg, fc);
if (err) {
dev_warn(&adpt->pdev->dev,
"config PHY flow control failed,err=%d\n",
@@ -170,10 +179,10 @@ static int alx_set_pauseparam(struct net_device *netdev,
}
/* flow control on mac */
- if ((fc ^ adpt->flowctrl) & (ALX_FC_RX | ALX_FC_TX))
- alx_cfg_mac_fc(adpt, fc);
+ if ((fc ^ hw->flowctrl) & (ALX_FC_RX | ALX_FC_TX))
+ alx_cfg_mac_fc(hw, fc);
- adpt->flowctrl = fc;
+ hw->flowctrl = fc;
ALX_FLAG_CLEAR(adpt, RESETING);
@@ -237,18 +246,19 @@ static void alx_get_regs(struct net_device *netdev,
struct ethtool_regs *regs, void *buff)
{
struct alx_adapter *adpt = netdev_priv(netdev);
+ struct alx_hw *hw = &adpt->hw;
u32 *p = buff;
int i;
- regs->version = (ALX_DID(adpt) << 16) | (ALX_REVID(adpt) << 8) | 1;
+ regs->version = (ALX_DID(hw) << 16) | (ALX_REVID(hw) << 8) | 1;
memset(buff, 0, (ARRAY_SIZE(hw_regs) + 1) * 4);
for (i = 0; i < ARRAY_SIZE(hw_regs); i++, p++)
- ALX_MEM_R32(adpt, hw_regs[i], p);
+ ALX_MEM_R32(hw, hw_regs[i], p);
/* last one for PHY Link Status */
- alx_read_phy_reg(adpt, MII_BMSR, (u16 *)p);
+ alx_read_phy_reg(hw, MII_BMSR, (u16 *)p);
}
static void alx_get_drvinfo(struct net_device *netdev,
@@ -270,34 +280,38 @@ static void alx_get_wol(struct net_device *netdev,
struct ethtool_wolinfo *wol)
{
struct alx_adapter *adpt = netdev_priv(netdev);
+ struct alx_hw *hw = &adpt->hw;
wol->supported = WAKE_MAGIC | WAKE_PHY;
wol->wolopts = 0;
- if (adpt->sleep_ctrl & ALX_SLEEP_WOL_MAGIC)
+ if (hw->sleep_ctrl & ALX_SLEEP_WOL_MAGIC)
wol->wolopts |= WAKE_MAGIC;
- if (adpt->sleep_ctrl & ALX_SLEEP_WOL_PHY)
+ if (hw->sleep_ctrl & ALX_SLEEP_WOL_PHY)
wol->wolopts |= WAKE_PHY;
- netdev_info(adpt->netdev, "wolopts = %x\n", wol->wolopts);
+ netif_info(adpt, wol, adpt->netdev,
+ "wolopts = %x\n",
+ wol->wolopts);
}
static int alx_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
{
struct alx_adapter *adpt = netdev_priv(netdev);
+ struct alx_hw *hw = &adpt->hw;
if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE |
WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
return -EOPNOTSUPP;
- adpt->sleep_ctrl = 0;
+ hw->sleep_ctrl = 0;
if (wol->wolopts & WAKE_MAGIC)
- adpt->sleep_ctrl |= ALX_SLEEP_WOL_MAGIC;
+ hw->sleep_ctrl |= ALX_SLEEP_WOL_MAGIC;
if (wol->wolopts & WAKE_PHY)
- adpt->sleep_ctrl |= ALX_SLEEP_WOL_PHY;
+ hw->sleep_ctrl |= ALX_SLEEP_WOL_PHY;
- device_set_wakeup_enable(&adpt->pdev->dev, adpt->sleep_ctrl);
+ device_set_wakeup_enable(&adpt->pdev->dev, hw->sleep_ctrl);
return 0;
}
diff --git a/src/alx_hw.c b/src/alx_hw.c
index 6310984..7a220c6 100644
--- a/src/alx_hw.c
+++ b/src/alx_hw.c
@@ -13,19 +13,18 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
-
-#include <linux/pci_regs.h>
-#include <linux/mii.h>
-#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <linux/crc32.h>
#include <linux/etherdevice.h>
+#include <linux/mdio.h>
-#include "alx.h"
-
-#define ALX_REV_A(_r) ((_r) == ALX_REV_A0 || (_r) == ALX_REV_A1)
+#include "alx_reg.h"
+#include "alx_hw.h"
+#define ALX_REV_A(_r) ((_r) == ALX_REV_A0 || (_r) == ALX_REV_A1)
/* get permanent mac address from */
-int alx_get_perm_macaddr(struct alx_adapter *adpt, u8 *addr)
+int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr)
{
u32 val, mac0, mac1;
u16 flag, i;
@@ -39,8 +38,8 @@ int alx_get_perm_macaddr(struct alx_adapter *adpt, u8 *addr)
read_mcadr:
/* get it from register first */
- ALX_MEM_R32(adpt, ALX_STAD0, &mac0);
- ALX_MEM_R32(adpt, ALX_STAD1, &mac1);
+ ALX_MEM_R32(hw, ALX_STAD0, &mac0);
+ ALX_MEM_R32(hw, ALX_STAD1, &mac1);
/* addr should be big-endian */
*(__be32 *)(addr + 2) = cpu_to_be32(mac0);
@@ -52,17 +51,17 @@ read_mcadr:
if ((flag & INTN_LOADED) == 0) {
/* load from efuse ? */
for (i = 0; i < ALX_SLD_MAX_TO; i++) {
- ALX_MEM_R32(adpt, ALX_SLD, &val);
+ ALX_MEM_R32(hw, ALX_SLD, &val);
if ((val & (ALX_SLD_STAT | ALX_SLD_START)) == 0)
break;
mdelay(1);
}
if (i == ALX_SLD_MAX_TO)
goto out;
- ALX_MEM_W32(adpt, ALX_SLD, val | ALX_SLD_START);
+ ALX_MEM_W32(hw, ALX_SLD, val | ALX_SLD_START);
for (i = 0; i < ALX_SLD_MAX_TO; i++) {
mdelay(1);
- ALX_MEM_R32(adpt, ALX_SLD, &val);
+ ALX_MEM_R32(hw, ALX_SLD, &val);
if ((val & ALX_SLD_START) == 0)
break;
}
@@ -73,11 +72,11 @@ read_mcadr:
}
if ((flag & EXTN_LOADED) == 0) {
- ALX_MEM_R32(adpt, ALX_EFLD, &val);
+ ALX_MEM_R32(hw, ALX_EFLD, &val);
if ((val & (ALX_EFLD_F_EXIST | ALX_EFLD_E_EXIST)) != 0) {
/* load from eeprom/flash ? */
for (i = 0; i < ALX_SLD_MAX_TO; i++) {
- ALX_MEM_R32(adpt, ALX_EFLD, &val);
+ ALX_MEM_R32(hw, ALX_EFLD, &val);
if ((val & (ALX_EFLD_STAT |
ALX_EFLD_START)) == 0) {
break;
@@ -86,10 +85,10 @@ read_mcadr:
}
if (i == ALX_SLD_MAX_TO)
goto out;
- ALX_MEM_W32(adpt, ALX_EFLD, val | ALX_EFLD_START);
+ ALX_MEM_W32(hw, ALX_EFLD, val | ALX_EFLD_START);
for (i = 0; i < ALX_SLD_MAX_TO; i++) {
mdelay(1);
- ALX_MEM_R32(adpt, ALX_EFLD, &val);
+ ALX_MEM_R32(hw, ALX_EFLD, &val);
if ((val & ALX_EFLD_START) == 0)
break;
}
@@ -104,42 +103,60 @@ out:
return ALX_ERR_ALOAD;
}
-void alx_set_macaddr(struct alx_adapter *adpt, u8 *addr)
+void alx_set_macaddr(struct alx_hw *hw, u8 *addr)
{
u32 val;
- /* for example: 00-0B-6A-F6-00-DC
- * STAD0=6AF600DC, STAD1=000B.
- */
+ /* for example: 00-0B-6A-F6-00-DC * STAD0=6AF600DC, STAD1=000B */
val = be32_to_cpu(*(__be32 *)(addr + 2));
- ALX_MEM_W32(adpt, ALX_STAD0, val);
+ ALX_MEM_W32(hw, ALX_STAD0, val);
val = be16_to_cpu(*(__be16 *)addr);
- ALX_MEM_W32(adpt, ALX_STAD1, val);
+ ALX_MEM_W32(hw, ALX_STAD1, val);
+}
+
+void alx_add_mc_addr(struct alx_hw *hw, u8 *addr)
+{
+ u32 crc32, bit, reg;
+
+ crc32 = ether_crc(ETH_ALEN, addr);
+
+ /* The HASH Table is a register array of 2 32-bit registers.
+ * It is treated like an array of 64 bits. We want to set
+ * bit BitArray[hash_value]. So we figure out what register
+ * the bit is in, read it, OR in the new bit, then write
+ * back the new value. The register is determined by the
+ * upper 7 bits of the hash value and the bit within that
+ * register are determined by the lower 5 bits of the value.
+ */
+ reg = (crc32 >> 31) & 0x1;
+ bit = (crc32 >> 26) & 0x1F;
+
+ hw->mc_hash[reg] |= (0x1 << bit);
}
-void alx_enable_osc(struct alx_adapter *adpt)
+void alx_enable_osc(struct alx_hw *hw)
{
u32 val;
/* rising edge */
- ALX_MEM_R32(adpt, ALX_MISC, &val);
- ALX_MEM_W32(adpt, ALX_MISC, val & ~ALX_MISC_INTNLOSC_OPEN);
- ALX_MEM_W32(adpt, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
+ ALX_MEM_R32(hw, ALX_MISC, &val);
+ ALX_MEM_W32(hw, ALX_MISC, val & ~ALX_MISC_INTNLOSC_OPEN);
+ ALX_MEM_W32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
}
-void alx_reset_osc(struct alx_adapter *adpt, u8 rev)
+void alx_reset_osc(struct alx_hw *hw, u8 rev)
{
u32 val, val2;
/* clear Internal OSC settings, switching OSC by hw itself */
- ALX_MEM_R32(adpt, ALX_MISC3, &val);
- ALX_MEM_W32(adpt, ALX_MISC3,
+ ALX_MEM_R32(hw, ALX_MISC3, &val);
+ ALX_MEM_W32(hw, ALX_MISC3,
(val & ~ALX_MISC3_25M_BY_SW) | ALX_MISC3_25M_NOTO_INTNL);
/* 25M clk from chipset may be unstable 1s after de-assert of
* PERST, driver need re-calibrate before enter Sleep for WoL
*/
- ALX_MEM_R32(adpt, ALX_MISC, &val);
+ ALX_MEM_R32(hw, ALX_MISC, &val);
if (rev == ALX_REV_B0) {
/* restore over current protection def-val,
* this val could be reset by MAC-RST
@@ -147,27 +164,27 @@ void alx_reset_osc(struct alx_adapter *adpt, u8 rev)
FIELD_SET32(val, ALX_MISC_PSW_OCP, ALX_MISC_PSW_OCP_DEF);
/* a 0->1 change will update the internal val of osc */
val &= ~ALX_MISC_INTNLOSC_OPEN;
- ALX_MEM_W32(adpt, ALX_MISC, val);
- ALX_MEM_W32(adpt, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
+ ALX_MEM_W32(hw, ALX_MISC, val);
+ ALX_MEM_W32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
/* hw will automatically dis OSC after cab. */
- ALX_MEM_R32(adpt, ALX_MSIC2, &val2);
+ ALX_MEM_R32(hw, ALX_MSIC2, &val2);
val2 &= ~ALX_MSIC2_CALB_START;
- ALX_MEM_W32(adpt, ALX_MSIC2, val2);
- ALX_MEM_W32(adpt, ALX_MSIC2, val2 | ALX_MSIC2_CALB_START);
+ ALX_MEM_W32(hw, ALX_MSIC2, val2);
+ ALX_MEM_W32(hw, ALX_MSIC2, val2 | ALX_MSIC2_CALB_START);
} else {
val &= ~ALX_MISC_INTNLOSC_OPEN;
/* disable isoloate for A0 */
if (ALX_REV_A(rev))
val &= ~ALX_MISC_ISO_EN;
- ALX_MEM_W32(adpt, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
- ALX_MEM_W32(adpt, ALX_MISC, val);
+ ALX_MEM_W32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
+ ALX_MEM_W32(hw, ALX_MISC, val);
}
udelay(20);
}
-int alx_reset_mac(struct alx_adapter *adpt)
+int alx_reset_mac(struct alx_hw *hw)
{
u32 val, pmctrl;
int i, ret;
@@ -175,46 +192,46 @@ int alx_reset_mac(struct alx_adapter *adpt)
bool a_cr;
pmctrl = 0;
- rev = (u8)ALX_REVID(adpt);
- a_cr = ALX_REV_A(rev) && ALX_WITH_CR(adpt);
+ rev = (u8)ALX_REVID(hw);
+ a_cr = ALX_REV_A(rev) && ALX_WITH_CR(hw);
/* disable all interrupts, RXQ/TXQ */
- ALX_MEM_W32(adpt, ALX_MSIX_MASK, 0xFFFFFFFF); /* msi-x */
- ALX_MEM_W32(adpt, ALX_IMR, 0);
- ALX_MEM_W32(adpt, ALX_ISR, ALX_ISR_DIS);
+ ALX_MEM_W32(hw, ALX_MSIX_MASK, 0xFFFFFFFF);
+ ALX_MEM_W32(hw, ALX_IMR, 0);
+ ALX_MEM_W32(hw, ALX_ISR, ALX_ISR_DIS);
- ret = alx_stop_mac(adpt);
+ ret = alx_stop_mac(hw);
if (ret)
return ret;
/* mac reset workaroud */
- ALX_MEM_W32(adpt, ALX_RFD_PIDX, 1);
+ ALX_MEM_W32(hw, ALX_RFD_PIDX, 1);
/* dis l0s/l1 before mac reset */
if (a_cr) {
- ALX_MEM_R32(adpt, ALX_PMCTRL, &pmctrl);
+ ALX_MEM_R32(hw, ALX_PMCTRL, &pmctrl);
if ((pmctrl & (ALX_PMCTRL_L1_EN | ALX_PMCTRL_L0S_EN)) != 0) {
- ALX_MEM_W32(adpt, ALX_PMCTRL,
+ ALX_MEM_W32(hw, ALX_PMCTRL,
pmctrl & ~(ALX_PMCTRL_L1_EN |
ALX_PMCTRL_L0S_EN));
}
}
/* reset whole mac safely */
- ALX_MEM_R32(adpt, ALX_MASTER, &val);
- ALX_MEM_W32(adpt, ALX_MASTER,
+ ALX_MEM_R32(hw, ALX_MASTER, &val);
+ ALX_MEM_W32(hw, ALX_MASTER,
val | ALX_MASTER_DMA_MAC_RST | ALX_MASTER_OOB_DIS);
/* make sure it's real idle */
udelay(10);
for (i = 0; i < ALX_DMA_MAC_RST_TO; i++) {
- ALX_MEM_R32(adpt, ALX_RFD_PIDX, &val);
+ ALX_MEM_R32(hw, ALX_RFD_PIDX, &val);
if (val == 0)
break;
udelay(10);
}
for (; i < ALX_DMA_MAC_RST_TO; i++) {
- ALX_MEM_R32(adpt, ALX_MASTER, &val);
+ ALX_MEM_R32(hw, ALX_MASTER, &val);
if ((val & ALX_MASTER_DMA_MAC_RST) == 0)
break;
udelay(10);
@@ -225,32 +242,32 @@ int alx_reset_mac(struct alx_adapter *adpt)
if (a_cr) {
/* set ALX_MASTER_PCLKSEL_SRDS (affect by soft-rst, PERST) */
- ALX_MEM_W32(adpt, ALX_MASTER, val | ALX_MASTER_PCLKSEL_SRDS);
+ ALX_MEM_W32(hw, ALX_MASTER, val | ALX_MASTER_PCLKSEL_SRDS);
/* resoter l0s / l1 */
if (pmctrl & (ALX_PMCTRL_L1_EN | ALX_PMCTRL_L0S_EN))
- ALX_MEM_W32(adpt, ALX_PMCTRL, pmctrl);
+ ALX_MEM_W32(hw, ALX_PMCTRL, pmctrl);
}
- alx_reset_osc(adpt, rev);
+ alx_reset_osc(hw, rev);
/* clear Internal OSC settings, switching OSC by hw itself,
* disable isoloate for A version
*/
- ALX_MEM_R32(adpt, ALX_MISC3, &val);
- ALX_MEM_W32(adpt, ALX_MISC3,
+ ALX_MEM_R32(hw, ALX_MISC3, &val);
+ ALX_MEM_W32(hw, ALX_MISC3,
(val & ~ALX_MISC3_25M_BY_SW) | ALX_MISC3_25M_NOTO_INTNL);
- ALX_MEM_R32(adpt, ALX_MISC, &val);
+ ALX_MEM_R32(hw, ALX_MISC, &val);
val &= ~ALX_MISC_INTNLOSC_OPEN;
if (ALX_REV_A(rev))
val &= ~ALX_MISC_ISO_EN;
- ALX_MEM_W32(adpt, ALX_MISC, val);
+ ALX_MEM_W32(hw, ALX_MISC, val);
udelay(20);
/* driver control speed/duplex, hash-alg */
- ALX_MEM_W32(adpt, ALX_MAC_CTRL, adpt->rx_ctrl);
+ ALX_MEM_W32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
/* clk sw */
- ALX_MEM_R32(adpt, ALX_SERDES, &val);
- ALX_MEM_W32(adpt, ALX_SERDES,
+ ALX_MEM_R32(hw, ALX_SERDES, &val);
+ ALX_MEM_W32(hw, ALX_SERDES,
val | ALX_SERDES_MACCLK_SLWDWN | ALX_SERDES_PHYCLK_SLWDWN);
return ret;
@@ -260,14 +277,14 @@ int alx_reset_mac(struct alx_adapter *adpt)
* completely reset phy, all settings/workaround will be re-configureed
* hib_en: enable/disable hibernation on PHY
*/
-void alx_reset_phy(struct alx_adapter *adpt, bool hib_en)
+void alx_reset_phy(struct alx_hw *hw, bool hib_en)
{
int i;
u32 val;
u16 phy_val;
/* (DSP)reset PHY core */
- ALX_MEM_R32(adpt, ALX_PHY_CTRL, &val);
+ ALX_MEM_R32(hw, ALX_PHY_CTRL, &val);
val &= ~(ALX_PHY_CTRL_DSPRST_OUT | ALX_PHY_CTRL_IDDQ |
ALX_PHY_CTRL_GATE_25M | ALX_PHY_CTRL_POWER_DOWN |
ALX_PHY_CTRL_CLS);
@@ -277,9 +294,9 @@ void alx_reset_phy(struct alx_adapter *adpt, bool hib_en)
val |= (ALX_PHY_CTRL_HIB_PULSE | ALX_PHY_CTRL_HIB_EN);
else
val &= ~(ALX_PHY_CTRL_HIB_PULSE | ALX_PHY_CTRL_HIB_EN);
- ALX_MEM_W32(adpt, ALX_PHY_CTRL, val);
- udelay(10); /* 5us is enough */
- ALX_MEM_W32(adpt, ALX_PHY_CTRL, val | ALX_PHY_CTRL_DSPRST_OUT);
+ ALX_MEM_W32(hw, ALX_PHY_CTRL, val);
+ udelay(10);
+ ALX_MEM_W32(hw, ALX_PHY_CTRL, val | ALX_PHY_CTRL_DSPRST_OUT);
/* delay 800us */
for (i = 0; i < ALX_PHY_CTRL_DSPRST_TO; i++)
@@ -287,68 +304,68 @@ void alx_reset_phy(struct alx_adapter *adpt, bool hib_en)
/* phy power saving & hib */
if (hib_en) {
- alx_write_phy_dbg(adpt, ALX_MIIDBG_LEGCYPS, ALX_LEGCYPS_DEF);
- alx_write_phy_dbg(adpt, ALX_MIIDBG_SYSMODCTRL,
+ alx_write_phy_dbg(hw, ALX_MIIDBG_LEGCYPS, ALX_LEGCYPS_DEF);
+ alx_write_phy_dbg(hw, ALX_MIIDBG_SYSMODCTRL,
ALX_SYSMODCTRL_IECHOADJ_DEF);
- alx_write_phy_ext(adpt, ALX_MIIEXT_PCS, ALX_MIIEXT_VDRVBIAS,
+ alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_VDRVBIAS,
ALX_VDRVBIAS_DEF);
} else {
- alx_write_phy_dbg(adpt, ALX_MIIDBG_LEGCYPS,
+ alx_write_phy_dbg(hw, ALX_MIIDBG_LEGCYPS,
ALX_LEGCYPS_DEF & ~ALX_LEGCYPS_EN);
- alx_write_phy_dbg(adpt, ALX_MIIDBG_HIBNEG, ALX_HIBNEG_NOHIB);
- alx_write_phy_dbg(adpt, ALX_MIIDBG_GREENCFG, ALX_GREENCFG_DEF);
+ alx_write_phy_dbg(hw, ALX_MIIDBG_HIBNEG, ALX_HIBNEG_NOHIB);
+ alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG, ALX_GREENCFG_DEF);
}
/* EEE advertisement */
- if (ALX_FLAG(adpt, CAP_AZ)) {
- alx_write_phy_ext(adpt, ALX_MIIEXT_ANEG,
+ if (ALX_CAP(hw, AZ)) {
+ alx_write_phy_ext(hw, ALX_MIIEXT_ANEG,
ALX_MIIEXT_LOCAL_EEEADV,
- ALX_FLAG(adpt, CAP_GIGA) ?
+ ALX_CAP(hw, GIGA) ?
ALX_LOCAL_EEEADV_1000BT | ALX_LOCAL_EEEADV_100BT :
ALX_LOCAL_EEEADV_100BT);
/* half amplify */
- alx_write_phy_dbg(adpt, ALX_MIIDBG_AZ_ANADECT,
+ alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT,
ALX_AZ_ANADECT_DEF);
- } else { /* disable az */
- ALX_MEM_R32(adpt, ALX_LPI_CTRL, &val);
- ALX_MEM_W32(adpt, ALX_LPI_CTRL, val & ~ALX_LPI_CTRL_EN);
- alx_write_phy_ext(adpt, ALX_MIIEXT_ANEG,
+ } else {
+ ALX_MEM_R32(hw, ALX_LPI_CTRL, &val);
+ ALX_MEM_W32(hw, ALX_LPI_CTRL, val & ~ALX_LPI_CTRL_EN);
+ alx_write_phy_ext(hw, ALX_MIIEXT_ANEG,
ALX_MIIEXT_LOCAL_EEEADV, 0);
}
/* phy power saving */
- alx_write_phy_dbg(adpt, ALX_MIIDBG_TST10BTCFG, ALX_TST10BTCFG_DEF);
- alx_write_phy_dbg(adpt, ALX_MIIDBG_SRDSYSMOD, ALX_SRDSYSMOD_DEF);
- alx_write_phy_dbg(adpt, ALX_MIIDBG_TST100BTCFG, ALX_TST100BTCFG_DEF);
- alx_write_phy_dbg(adpt, ALX_MIIDBG_ANACTRL, ALX_ANACTRL_DEF);
- alx_read_phy_dbg(adpt, ALX_MIIDBG_GREENCFG2, &phy_val);
- alx_write_phy_dbg(adpt, ALX_MIIDBG_GREENCFG2,
+ alx_write_phy_dbg(hw, ALX_MIIDBG_TST10BTCFG, ALX_TST10BTCFG_DEF);
+ alx_write_phy_dbg(hw, ALX_MIIDBG_SRDSYSMOD, ALX_SRDSYSMOD_DEF);
+ alx_write_phy_dbg(hw, ALX_MIIDBG_TST100BTCFG, ALX_TST100BTCFG_DEF);
+ alx_write_phy_dbg(hw, ALX_MIIDBG_ANACTRL, ALX_ANACTRL_DEF);
+ alx_read_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, &phy_val);
+ alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG2,
phy_val & ~ALX_GREENCFG2_GATE_DFSE_EN);
/* rtl8139c, 120m issue */
- alx_write_phy_ext(adpt, ALX_MIIEXT_ANEG, ALX_MIIEXT_NLP78,
+ alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_NLP78,
ALX_MIIEXT_NLP78_120M_DEF);
- alx_write_phy_ext(adpt, ALX_MIIEXT_ANEG, ALX_MIIEXT_S3DIG10,
+ alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_S3DIG10,
ALX_MIIEXT_S3DIG10_DEF);
- if (adpt->lnk_patch) {
+ if (hw->lnk_patch) {
/* Turn off half amplitude */
- alx_read_phy_ext(adpt, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3,
+ alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3,
&phy_val);
- alx_write_phy_ext(adpt, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3,
+ alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3,
phy_val | ALX_CLDCTRL3_BP_CABLE1TH_DET_GT);
/* Turn off Green feature */
- alx_read_phy_dbg(adpt, ALX_MIIDBG_GREENCFG2, &phy_val);
- alx_write_phy_dbg(adpt, ALX_MIIDBG_GREENCFG2,
+ alx_read_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, &phy_val);
+ alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG2,
phy_val | ALX_GREENCFG2_BP_GREEN);
/* Turn off half Bias */
- alx_read_phy_ext(adpt, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5,
+ alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5,
&phy_val);
- alx_write_phy_ext(adpt, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5,
+ alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5,
phy_val | ALX_CLDCTRL5_BP_VD_HLFBIAS);
}
/* set phy interrupt mask */
- alx_write_phy_reg(adpt, ALX_MII_IER,
+ alx_write_phy_reg(hw, ALX_MII_IER,
ALX_IER_LINK_UP | ALX_IER_LINK_DOWN);
}
@@ -360,54 +377,52 @@ void alx_reset_phy(struct alx_adapter *adpt, bool hib_en)
* alx_reset_pcie
* reset pcie relative registers (pci command, clk, aspm...)
*/
-void alx_reset_pcie(struct alx_adapter *adpt)
+void alx_reset_pcie(struct alx_hw *hw)
{
u32 val;
u16 val16;
- u8 rev = (u8)ALX_REVID(adpt);
+ u8 rev = (u8)ALX_REVID(hw);
/* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
- ALX_CFG_R16(adpt, PCI_COMMAND, &val16);
+ ALX_CFG_R16(hw, PCI_COMMAND, &val16);
if (!(val16 & ALX_PCI_CMD) || (val16 & PCI_COMMAND_INTX_DISABLE)) {
val16 = (val16 | ALX_PCI_CMD) & ~PCI_COMMAND_INTX_DISABLE;
- ALX_CFG_W16(adpt, PCI_COMMAND, val16);
+ ALX_CFG_W16(hw, PCI_COMMAND, val16);
}
/* clear WoL setting/status */
- ALX_MEM_R32(adpt, ALX_WOL0, &val);
- ALX_MEM_W32(adpt, ALX_WOL0, 0);
+ ALX_MEM_R32(hw, ALX_WOL0, &val);
+ ALX_MEM_W32(hw, ALX_WOL0, 0);
/* deflt val of PDLL D3PLLOFF */
- ALX_MEM_R32(adpt, ALX_PDLL_TRNS1, &val);
- ALX_MEM_W32(adpt, ALX_PDLL_TRNS1, val & ~ALX_PDLL_TRNS1_D3PLLOFF_EN);
+ ALX_MEM_R32(hw, ALX_PDLL_TRNS1, &val);
+ ALX_MEM_W32(hw, ALX_PDLL_TRNS1, val & ~ALX_PDLL_TRNS1_D3PLLOFF_EN);
/* mask some pcie error bits */
- ALX_MEM_R32(adpt, ALX_UE_SVRT, &val);
+ ALX_MEM_R32(hw, ALX_UE_SVRT, &val);
val &= ~(ALX_UE_SVRT_DLPROTERR | ALX_UE_SVRT_FCPROTERR);
- ALX_MEM_W32(adpt, ALX_UE_SVRT, val);
+ ALX_MEM_W32(hw, ALX_UE_SVRT, val);
/* wol 25M & pclk */
- ALX_MEM_R32(adpt, ALX_MASTER, &val);
- if (ALX_REV_A(rev) && ALX_WITH_CR(adpt)) {
+ ALX_MEM_R32(hw, ALX_MASTER, &val);
+ if (ALX_REV_A(rev) && ALX_WITH_CR(hw)) {
if ((val & ALX_MASTER_WAKEN_25M) == 0 ||
(val & ALX_MASTER_PCLKSEL_SRDS) == 0) {
- ALX_MEM_W32(adpt, ALX_MASTER,
+ ALX_MEM_W32(hw, ALX_MASTER,
val | ALX_MASTER_PCLKSEL_SRDS |
ALX_MASTER_WAKEN_25M);
}
} else {
if ((val & ALX_MASTER_WAKEN_25M) == 0 ||
(val & ALX_MASTER_PCLKSEL_SRDS) != 0) {
- ALX_MEM_W32(adpt, ALX_MASTER,
+ ALX_MEM_W32(hw, ALX_MASTER,
(val & ~ALX_MASTER_PCLKSEL_SRDS) |
ALX_MASTER_WAKEN_25M);
}
}
/* ASPM setting */
- alx_enable_aspm(adpt,
- ALX_FLAG(adpt, CAP_L0S),
- ALX_FLAG(adpt, CAP_L1));
+ alx_enable_aspm(hw, ALX_CAP(hw, L0S), ALX_CAP(hw, L1));
udelay(10);
}
@@ -416,23 +431,23 @@ void alx_reset_pcie(struct alx_adapter *adpt)
* stop the mac, transmit & receive modules
* return : 0 if ok, none-0 if busy
*/
-int alx_stop_mac(struct alx_adapter *adpt)
+int alx_stop_mac(struct alx_hw *hw)
{
u32 rxq, txq, val;
u16 i;
- ALX_MEM_R32(adpt, ALX_RXQ0, &rxq);
- ALX_MEM_W32(adpt, ALX_RXQ0, rxq & ~ALX_RXQ0_EN);
- ALX_MEM_R32(adpt, ALX_TXQ0, &txq);
- ALX_MEM_W32(adpt, ALX_TXQ0, txq & ~ALX_TXQ0_EN);
+ ALX_MEM_R32(hw, ALX_RXQ0, &rxq);
+ ALX_MEM_W32(hw, ALX_RXQ0, rxq & ~ALX_RXQ0_EN);
+ ALX_MEM_R32(hw, ALX_TXQ0, &txq);
+ ALX_MEM_W32(hw, ALX_TXQ0, txq & ~ALX_TXQ0_EN);
udelay(40);
- adpt->rx_ctrl &= ~(ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN);
- ALX_MEM_W32(adpt, ALX_MAC_CTRL, adpt->rx_ctrl);
+ hw->rx_ctrl &= ~(ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN);
+ ALX_MEM_W32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
for (i = 0; i < ALX_DMA_MAC_RST_TO; i++) {
- ALX_MEM_R32(adpt, ALX_MAC_STS, &val);
+ ALX_MEM_R32(hw, ALX_MAC_STS, &val);
if (!(val & ALX_MAC_STS_IDLE))
break;
udelay(10);
@@ -444,56 +459,56 @@ int alx_stop_mac(struct alx_adapter *adpt)
/* alx_start_mac
* enable rx/tx MAC module
*/
-void alx_start_mac(struct alx_adapter *adpt)
+void alx_start_mac(struct alx_hw *hw)
{
u32 mac, txq, rxq;
- ALX_MEM_R32(adpt, ALX_RXQ0, &rxq);
- ALX_MEM_W32(adpt, ALX_RXQ0, rxq | ALX_RXQ0_EN);
- ALX_MEM_R32(adpt, ALX_TXQ0, &txq);
- ALX_MEM_W32(adpt, ALX_TXQ0, txq | ALX_TXQ0_EN);
+ ALX_MEM_R32(hw, ALX_RXQ0, &rxq);
+ ALX_MEM_W32(hw, ALX_RXQ0, rxq | ALX_RXQ0_EN);
+ ALX_MEM_R32(hw, ALX_TXQ0, &txq);
+ ALX_MEM_W32(hw, ALX_TXQ0, txq | ALX_TXQ0_EN);
- mac = adpt->rx_ctrl;
- if (adpt->link_duplex == FULL_DUPLEX)
+ mac = hw->rx_ctrl;
+ if (hw->link_duplex == FULL_DUPLEX)
mac |= ALX_MAC_CTRL_FULLD;
else
mac &= ~ALX_MAC_CTRL_FULLD;
- FIELD_SET32(mac, ALX_MAC_CTRL_SPEED, adpt->link_speed == SPEED_1000 ?
+ FIELD_SET32(mac, ALX_MAC_CTRL_SPEED, hw->link_speed == SPEED_1000 ?
ALX_MAC_CTRL_SPEED_1000 : ALX_MAC_CTRL_SPEED_10_100);
mac |= ALX_MAC_CTRL_TX_EN | ALX_MAC_CTRL_RX_EN;
- adpt->rx_ctrl = mac;
- ALX_MEM_W32(adpt, ALX_MAC_CTRL, mac);
+ hw->rx_ctrl = mac;
+ ALX_MEM_W32(hw, ALX_MAC_CTRL, mac);
}
/* set flow control on MAC side */
-void alx_cfg_mac_fc(struct alx_adapter *adpt, u8 fc)
+void alx_cfg_mac_fc(struct alx_hw *hw, u8 fc)
{
if (fc & ALX_FC_RX)
- adpt->rx_ctrl |= ALX_MAC_CTRL_RX_EN;
+ hw->rx_ctrl |= ALX_MAC_CTRL_RXFC_EN;
else
- adpt->rx_ctrl &= ~ALX_MAC_CTRL_RX_EN;
+ hw->rx_ctrl &= ~ALX_MAC_CTRL_RXFC_EN;
if (fc & ALX_FC_TX)
- adpt->rx_ctrl |= ALX_MAC_CTRL_TX_EN;
+ hw->rx_ctrl |= ALX_MAC_CTRL_TXFC_EN;
else
- adpt->rx_ctrl &= ~ALX_MAC_CTRL_TX_EN;
+ hw->rx_ctrl &= ~ALX_MAC_CTRL_TXFC_EN;
- ALX_MEM_W32(adpt, ALX_MAC_CTRL, adpt->rx_ctrl);
+ ALX_MEM_W32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
}
/* enable/disable aspm support */
-void alx_enable_aspm(struct alx_adapter *adpt, bool l0s_en, bool l1_en)
+void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en)
{
u32 pmctrl;
- u8 rev = (u8)ALX_REVID(adpt);
+ u8 rev = (u8)ALX_REVID(hw);
- ALX_MEM_R32(adpt, ALX_PMCTRL, &pmctrl);
+ ALX_MEM_R32(hw, ALX_PMCTRL, &pmctrl);
FIELD_SET32(pmctrl, ALX_PMCTRL_LCKDET_TIMER,
ALX_PMCTRL_LCKDET_TIMER_DEF);
- pmctrl |= ALX_PMCTRL_RCVR_WT_1US | /* wait 1us */
- ALX_PMCTRL_L1_CLKSW_EN | /* pcie clk sw */
- ALX_PMCTRL_L1_SRDSRX_PWD ; /* pwd serdes */
+ pmctrl |= ALX_PMCTRL_RCVR_WT_1US |
+ ALX_PMCTRL_L1_CLKSW_EN |
+ ALX_PMCTRL_L1_SRDSRX_PWD ;
FIELD_SET32(pmctrl, ALX_PMCTRL_L1REQ_TO, ALX_PMCTRL_L1REG_TO_DEF);
FIELD_SET32(pmctrl, ALX_PMCTRL_L1_TIMER, ALX_PMCTRL_L1_TIMER_16US);
pmctrl &= ~(ALX_PMCTRL_L1_SRDS_EN |
@@ -507,7 +522,7 @@ void alx_enable_aspm(struct alx_adapter *adpt, bool l0s_en, bool l1_en)
ALX_PMCTRL_TXL1_AFTER_L0S |
ALX_PMCTRL_RXL1_AFTER_L0S
);
- if (ALX_REV_A(rev) && ALX_WITH_CR(adpt))
+ if (ALX_REV_A(rev) && ALX_WITH_CR(hw))
pmctrl |= ALX_PMCTRL_L1_SRDS_EN | ALX_PMCTRL_L1_SRDSPLL_EN;
if (l0s_en)
@@ -515,16 +530,16 @@ void alx_enable_aspm(struct alx_adapter *adpt, bool l0s_en, bool l1_en)
if (l1_en)
pmctrl |= (ALX_PMCTRL_L1_EN | ALX_PMCTRL_ASPM_FCEN);
- ALX_MEM_W32(adpt, ALX_PMCTRL, pmctrl);
+ ALX_MEM_W32(hw, ALX_PMCTRL, pmctrl);
}
/* translate ethtool adv /speed/duplex settting to hw specific value */
-u32 ethadv_to_hw_cfg(struct alx_adapter *adpt, u32 ethadv_cfg)
+u32 ethadv_to_hw_cfg(struct alx_hw *hw, u32 ethadv_cfg)
{
u32 cfg = 0;
- if (ethadv_cfg & ADVERTISED_Autoneg) { /* auto-neg */
+ if (ethadv_cfg & ADVERTISED_Autoneg) {
cfg |= ALX_DRV_PHY_AUTO;
if (ethadv_cfg & ADVERTISED_10baseT_Half)
cfg |= ALX_DRV_PHY_10;
@@ -542,9 +557,9 @@ u32 ethadv_to_hw_cfg(struct alx_adapter *adpt, u32 ethadv_cfg)
cfg |= ADVERTISE_PAUSE_CAP;
if (ethadv_cfg & ADVERTISED_Asym_Pause)
cfg |= ADVERTISE_PAUSE_ASYM;
- if (ALX_FLAG(adpt, CAP_AZ))
+ if (ALX_CAP(hw, AZ))
cfg |= ALX_DRV_PHY_EEE;
- } else { /* force mode */
+ } else {
switch (ethadv_cfg) {
case ADVERTISED_10baseT_Half:
cfg |= ALX_DRV_PHY_10;
@@ -568,18 +583,18 @@ u32 ethadv_to_hw_cfg(struct alx_adapter *adpt, u32 ethadv_cfg)
* ethadv:
* format from ethtool, we use it for both autoneg and force mode
*/
-int alx_setup_speed_duplex(struct alx_adapter *adpt, u32 ethadv, u8 flowctrl)
+int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl)
{
u16 adv, giga, cr;
u32 val;
int err = 0;
/* clear flag */
- alx_write_phy_reg(adpt, ALX_MII_DBG_ADDR, 0);
- ALX_MEM_R32(adpt, ALX_DRV, &val);
+ alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, 0);
+ ALX_MEM_R32(hw, ALX_DRV, &val);
FIELD_SET32(val, ALX_DRV_PHY, 0);
- if (ethadv & ADVERTISED_Autoneg) { /* auto-neg */
+ if (ethadv & ADVERTISED_Autoneg) {
adv = ADVERTISE_CSMA;
adv |= ethtool_adv_to_mii_adv_t(ethadv);
@@ -592,16 +607,16 @@ int alx_setup_speed_duplex(struct alx_adapter *adpt, u32 ethadv, u8 flowctrl)
adv |= ADVERTISED_Asym_Pause;
}
giga = 0;
- if (ALX_FLAG(adpt, CAP_GIGA))
+ if (ALX_CAP(hw, GIGA))
giga = ethtool_adv_to_mii_ctrl1000_t(ethadv);
cr = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART;
- if (alx_write_phy_reg(adpt, MII_ADVERTISE, adv) ||
- alx_write_phy_reg(adpt, MII_CTRL1000, giga) ||
- alx_write_phy_reg(adpt, MII_BMCR, cr))
+ if (alx_write_phy_reg(hw, MII_ADVERTISE, adv) ||
+ alx_write_phy_reg(hw, MII_CTRL1000, giga) ||
+ alx_write_phy_reg(hw, MII_BMCR, cr))
err = ALX_ERR_MIIBUSY;
- } else { /* force mode */
+ } else {
cr = BMCR_RESET;
if (ethadv == ADVERTISED_100baseT_Half ||
ethadv == ADVERTISED_100baseT_Full)
@@ -610,26 +625,26 @@ int alx_setup_speed_duplex(struct alx_adapter *adpt, u32 ethadv, u8 flowctrl)
ethadv == ADVERTISED_100baseT_Full)
cr |= BMCR_FULLDPLX;
- err = alx_write_phy_reg(adpt, MII_BMCR, cr);
+ err = alx_write_phy_reg(hw, MII_BMCR, cr);
}
if (!err) {
- alx_write_phy_reg(adpt, ALX_MII_DBG_ADDR, ALX_PHY_INITED);
+ alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, ALX_PHY_INITED);
/* save config to HW */
- val |= ethadv_to_hw_cfg(adpt, ethadv);
+ val |= ethadv_to_hw_cfg(hw, ethadv);
}
- ALX_MEM_W32(adpt, ALX_DRV, val);
+ ALX_MEM_W32(hw, ALX_DRV, val);
return err;
}
/* do post setting on phy if link up/down event occur */
-void alx_post_phy_link(struct alx_adapter *adpt, u16 speed, bool az_en)
+void alx_post_phy_link(struct alx_hw *hw, u16 speed, bool az_en)
{
u16 phy_val, len, agc;
- u8 revid = (u8)ALX_REVID(adpt);
+ u8 revid = (u8)ALX_REVID(hw);
bool adj_th;
if (revid != ALX_REV_B0 &&
@@ -640,11 +655,11 @@ void alx_post_phy_link(struct alx_adapter *adpt, u16 speed, bool az_en)
adj_th = (revid == ALX_REV_B0) ? true : false;
/* 1000BT/AZ, wrong cable length */
- if (speed != SPEED_0) { /* link up */
- alx_read_phy_ext(adpt, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL6,
+ if (speed != SPEED_0) {
+ alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL6,
&phy_val);
len = FIELD_GETX(phy_val, ALX_CLDCTRL6_CAB_LEN);
- alx_read_phy_dbg(adpt, ALX_MIIDBG_AGC, &phy_val);
+ alx_read_phy_dbg(hw, ALX_MIIDBG_AGC, &phy_val);
agc = FIELD_GETX(phy_val, ALX_AGC_2_VGA);
if ((speed == SPEED_1000 &&
@@ -653,59 +668,59 @@ void alx_post_phy_link(struct alx_adapter *adpt, u16 speed, bool az_en)
(speed == SPEED_100 &&
(len > ALX_CLDCTRL6_CAB_LEN_SHORT100M ||
(0 == len && agc > ALX_AGC_LONG100M_LIMT)))) {
- alx_write_phy_dbg(adpt, ALX_MIIDBG_AZ_ANADECT,
+ alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT,
ALX_AZ_ANADECT_LONG);
- alx_read_phy_ext(adpt, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
+ alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
&phy_val);
- alx_write_phy_ext(adpt, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
+ alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
phy_val | ALX_AFE_10BT_100M_TH);
} else {
- alx_write_phy_dbg(adpt, ALX_MIIDBG_AZ_ANADECT,
+ alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT,
ALX_AZ_ANADECT_DEF);
- alx_read_phy_ext(adpt, ALX_MIIEXT_ANEG,
+ alx_read_phy_ext(hw, ALX_MIIEXT_ANEG,
ALX_MIIEXT_AFE, &phy_val);
- alx_write_phy_ext(adpt, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
+ alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
phy_val & ~ALX_AFE_10BT_100M_TH);
}
/* threashold adjust */
- if (adj_th && adpt->lnk_patch) {
+ if (adj_th && hw->lnk_patch) {
if (speed == SPEED_100) {
- alx_write_phy_dbg(adpt, ALX_MIIDBG_MSE16DB,
+ alx_write_phy_dbg(hw, ALX_MIIDBG_MSE16DB,
ALX_MSE16DB_UP);
} else if (speed == SPEED_1000) {
/*
* Giga link threshold, raise the tolerance of
* noise 50%
*/
- alx_read_phy_dbg(adpt, ALX_MIIDBG_MSE20DB,
+ alx_read_phy_dbg(hw, ALX_MIIDBG_MSE20DB,
&phy_val);
FIELD_SETS(phy_val, ALX_MSE20DB_TH,
ALX_MSE20DB_TH_HI);
- alx_write_phy_dbg(adpt, ALX_MIIDBG_MSE20DB,
+ alx_write_phy_dbg(hw, ALX_MIIDBG_MSE20DB,
phy_val);
}
}
/* phy link-down in 1000BT/AZ mode */
if (az_en && revid == ALX_REV_B0 && speed == SPEED_1000) {
- alx_write_phy_dbg(adpt, ALX_MIIDBG_SRDSYSMOD,
+ alx_write_phy_dbg(hw, ALX_MIIDBG_SRDSYSMOD,
ALX_SRDSYSMOD_DEF & ~ALX_SRDSYSMOD_DEEMP_EN);
}
} else {
- alx_read_phy_ext(adpt, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
+ alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
&phy_val);
- alx_write_phy_ext(adpt, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
+ alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
phy_val & ~ALX_AFE_10BT_100M_TH);
- if (adj_th && adpt->lnk_patch) {
- alx_write_phy_dbg(adpt, ALX_MIIDBG_MSE16DB,
+ if (adj_th && hw->lnk_patch) {
+ alx_write_phy_dbg(hw, ALX_MIIDBG_MSE16DB,
ALX_MSE16DB_DOWN);
- alx_read_phy_dbg(adpt, ALX_MIIDBG_MSE20DB, &phy_val);
+ alx_read_phy_dbg(hw, ALX_MIIDBG_MSE20DB, &phy_val);
FIELD_SETS(phy_val, ALX_MSE20DB_TH, ALX_MSE20DB_TH_DEF);
- alx_write_phy_dbg(adpt, ALX_MIIDBG_MSE20DB, phy_val);
+ alx_write_phy_dbg(hw, ALX_MIIDBG_MSE20DB, phy_val);
}
if (az_en && revid == ALX_REV_B0) {
- alx_write_phy_dbg(adpt, ALX_MIIDBG_SRDSYSMOD,
+ alx_write_phy_dbg(hw, ALX_MIIDBG_SRDSYSMOD,
ALX_SRDSYSMOD_DEF);
}
}
@@ -717,75 +732,75 @@ void alx_post_phy_link(struct alx_adapter *adpt, u16 speed, bool az_en)
* 1. phy link must be established before calling this function
* 2. wol option (pattern,magic,link,etc.) is configed before call it.
*/
-int alx_pre_suspend(struct alx_adapter *adpt, u16 speed)
+int alx_pre_suspend(struct alx_hw *hw, u16 speed)
{
u32 master, mac, phy, val;
int err = 0;
- ALX_MEM_R32(adpt, ALX_MASTER, &master);
+ ALX_MEM_R32(hw, ALX_MASTER, &master);
master &= ~ALX_MASTER_PCLKSEL_SRDS;
- mac = adpt->rx_ctrl;
+ mac = hw->rx_ctrl;
/* 10/100 half */
FIELD_SET32(mac, ALX_MAC_CTRL_SPEED, ALX_MAC_CTRL_SPEED_10_100);
mac &= ~(ALX_MAC_CTRL_FULLD | ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN);
- ALX_MEM_R32(adpt, ALX_PHY_CTRL, &phy);
+ ALX_MEM_R32(hw, ALX_PHY_CTRL, &phy);
phy &= ~(ALX_PHY_CTRL_DSPRST_OUT | ALX_PHY_CTRL_CLS);
phy |= ALX_PHY_CTRL_RST_ANALOG | ALX_PHY_CTRL_HIB_PULSE |
ALX_PHY_CTRL_HIB_EN;
/* without any activity */
- if (!(adpt->sleep_ctrl & ALX_SLEEP_ACTIVE)) {
- err = alx_write_phy_reg(adpt, ALX_MII_IER, 0);
+ if (!(hw->sleep_ctrl & ALX_SLEEP_ACTIVE)) {
+ err = alx_write_phy_reg(hw, ALX_MII_IER, 0);
phy |= ALX_PHY_CTRL_IDDQ | ALX_PHY_CTRL_POWER_DOWN;
goto config_reg;
}
- if (adpt->sleep_ctrl & (ALX_SLEEP_WOL_MAGIC | ALX_SLEEP_CIFS))
+ if (hw->sleep_ctrl & (ALX_SLEEP_WOL_MAGIC | ALX_SLEEP_CIFS))
mac |= ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_BRD_EN;
- if (adpt->sleep_ctrl & ALX_SLEEP_CIFS)
+ if (hw->sleep_ctrl & ALX_SLEEP_CIFS)
mac |= ALX_MAC_CTRL_TX_EN;
if (speed % 10 == FULL_DUPLEX)
mac |= ALX_MAC_CTRL_FULLD;
if (speed >= SPEED_1000)
FIELD_SET32(mac, ALX_MAC_CTRL_SPEED, ALX_MAC_CTRL_SPEED_1000);
phy |= ALX_PHY_CTRL_DSPRST_OUT;
- if (adpt->sleep_ctrl & ALX_SLEEP_WOL_PHY)
- err = alx_write_phy_reg(adpt, ALX_MII_IER, ALX_IER_LINK_UP);
+ if (hw->sleep_ctrl & ALX_SLEEP_WOL_PHY)
+ err = alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP);
if (!err)
- err = alx_write_phy_ext(adpt, ALX_MIIEXT_ANEG,
+ err = alx_write_phy_ext(hw, ALX_MIIEXT_ANEG,
ALX_MIIEXT_S3DIG10, ALX_MIIEXT_S3DIG10_SL);
config_reg:
if (!err) {
- alx_enable_osc(adpt);
- adpt->rx_ctrl = mac;
- ALX_MEM_W32(adpt, ALX_MASTER, master);
- ALX_MEM_W32(adpt, ALX_MAC_CTRL, mac);
- ALX_MEM_W32(adpt, ALX_PHY_CTRL, phy);
+ alx_enable_osc(hw);
+ hw->rx_ctrl = mac;
+ ALX_MEM_W32(hw, ALX_MASTER, master);
+ ALX_MEM_W32(hw, ALX_MAC_CTRL, mac);
+ ALX_MEM_W32(hw, ALX_PHY_CTRL, phy);
/* set val of PDLL D3PLLOFF */
- ALX_MEM_R32(adpt, ALX_PDLL_TRNS1, &val);
+ ALX_MEM_R32(hw, ALX_PDLL_TRNS1, &val);
val |= ALX_PDLL_TRNS1_D3PLLOFF_EN;
- ALX_MEM_W32(adpt, ALX_PDLL_TRNS1, val);
+ ALX_MEM_W32(hw, ALX_PDLL_TRNS1, val);
}
return err;
}
/* wait mdio module to be idle */
-bool __alx_wait_mdio_idle(struct alx_adapter *adpt)
+bool __alx_wait_mdio_idle(struct alx_hw *hw)
{
u32 val;
int i;
for (i = 0; i < ALX_MDIO_MAX_AC_TO; i++) {
- ALX_MEM_R32(adpt, ALX_MDIO, &val);
+ ALX_MEM_R32(hw, ALX_MDIO, &val);
if (!(val & ALX_MDIO_BUSY))
break;
udelay(10);
}
- return i == ALX_MDIO_MAX_AC_TO;
+ return i != ALX_MDIO_MAX_AC_TO;
}
/* __alx_read_phy_core
@@ -794,7 +809,7 @@ bool __alx_wait_mdio_idle(struct alx_adapter *adpt)
* dev: device address (see IEEE 802.3 DEVAD, PRTAD is fixed to 0)
* reg: register to read
*/
-int __alx_read_phy_core(struct alx_adapter *adpt, bool ext, u8 dev,
+int __alx_read_phy_core(struct alx_hw *hw, bool ext, u8 dev,
u16 reg, u16 *phy_data)
{
u32 val, clk_sel;
@@ -803,13 +818,13 @@ int __alx_read_phy_core(struct alx_adapter *adpt, bool ext, u8 dev,
*phy_data = 0;
/* use slow clock when it's in hibernation status */
- clk_sel = adpt->link_up ?
+ clk_sel = hw->link_up ?
ALX_MDIO_CLK_SEL_25MD128 : ALX_MDIO_CLK_SEL_25MD4;
if (ext) {
val = FIELDX(ALX_MDIO_EXTN_DEVAD, dev) |
FIELDX(ALX_MDIO_EXTN_REG, reg);
- ALX_MEM_W32(adpt, ALX_MDIO_EXTN, val);
+ ALX_MEM_W32(hw, ALX_MDIO_EXTN, val);
val = ALX_MDIO_SPRES_PRMBL |
FIELDX(ALX_MDIO_CLK_SEL, clk_sel) |
@@ -823,12 +838,12 @@ int __alx_read_phy_core(struct alx_adapter *adpt, bool ext, u8 dev,
ALX_MDIO_START |
ALX_MDIO_OP_READ;
}
- ALX_MEM_W32(adpt, ALX_MDIO, val);
+ ALX_MEM_W32(hw, ALX_MDIO, val);
- if (unlikely(!__alx_wait_mdio_idle(adpt)))
+ if (unlikely(!__alx_wait_mdio_idle(hw)))
err = ALX_ERR_MIIBUSY;
else {
- ALX_MEM_R32(adpt, ALX_MDIO, &val);
+ ALX_MEM_R32(hw, ALX_MDIO, &val);
*phy_data = (u16)FIELD_GETX(val, ALX_MDIO_DATA);
err = 0;
}
@@ -842,20 +857,20 @@ int __alx_read_phy_core(struct alx_adapter *adpt, bool ext, u8 dev,
* dev: device address (see IEEE 802.3 DEVAD, PRTAD is fixed to 0)
* reg: register to write
*/
-int __alx_write_phy_core(struct alx_adapter *adpt, bool ext, u8 dev,
+int __alx_write_phy_core(struct alx_hw *hw, bool ext, u8 dev,
u16 reg, u16 phy_data)
{
u32 val, clk_sel;
int err = 0;
/* use slow clock when it's in hibernation status */
- clk_sel = adpt->link_up ?
+ clk_sel = hw->link_up ?
ALX_MDIO_CLK_SEL_25MD128 : ALX_MDIO_CLK_SEL_25MD4;
if (ext) {
val = FIELDX(ALX_MDIO_EXTN_DEVAD, dev) |
FIELDX(ALX_MDIO_EXTN_REG, reg);
- ALX_MEM_W32(adpt, ALX_MDIO_EXTN, val);
+ ALX_MEM_W32(hw, ALX_MDIO_EXTN, val);
val = ALX_MDIO_SPRES_PRMBL |
FIELDX(ALX_MDIO_CLK_SEL, clk_sel) |
@@ -869,175 +884,175 @@ int __alx_write_phy_core(struct alx_adapter *adpt, bool ext, u8 dev,
FIELDX(ALX_MDIO_DATA, phy_data) |
ALX_MDIO_START;
}
- ALX_MEM_W32(adpt, ALX_MDIO, val);
+ ALX_MEM_W32(hw, ALX_MDIO, val);
- if (unlikely(!__alx_wait_mdio_idle(adpt)))
+ if (unlikely(!__alx_wait_mdio_idle(hw)))
err = ALX_ERR_MIIBUSY;
return err;
}
/* read from PHY normal register */
-int __alx_read_phy_reg(struct alx_adapter *adpt, u16 reg, u16 *phy_data)
+int __alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data)
{
- return __alx_read_phy_core(adpt, false, 0, reg, phy_data);
+ return __alx_read_phy_core(hw, false, 0, reg, phy_data);
}
/* write to PHY normal register */
-int __alx_write_phy_reg(struct alx_adapter *adpt, u16 reg, u16 phy_data)
+int __alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data)
{
- return __alx_write_phy_core(adpt, false, 0, reg, phy_data);
+ return __alx_write_phy_core(hw, false, 0, reg, phy_data);
}
/* read from PHY extension register */
-int __alx_read_phy_ext(struct alx_adapter *adpt, u8 dev, u16 reg, u16 *pdata)
+int __alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata)
{
- return __alx_read_phy_core(adpt, true, dev, reg, pdata);
+ return __alx_read_phy_core(hw, true, dev, reg, pdata);
}
/* write to PHY extension register */
-int __alx_write_phy_ext(struct alx_adapter *adpt, u8 dev, u16 reg, u16 data)
+int __alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data)
{
- return __alx_write_phy_core(adpt, true, dev, reg, data);
+ return __alx_write_phy_core(hw, true, dev, reg, data);
}
/* read from PHY debug port */
-int __alx_read_phy_dbg(struct alx_adapter *adpt, u16 reg, u16 *pdata)
+int __alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata)
{
int err;
- err = __alx_write_phy_reg(adpt, ALX_MII_DBG_ADDR, reg);
+ err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg);
if (unlikely(err))
return err;
else
- err = __alx_read_phy_reg(adpt, ALX_MII_DBG_DATA, pdata);
+ err = __alx_read_phy_reg(hw, ALX_MII_DBG_DATA, pdata);
return err;
}
/* write to PHY debug port */
-int __alx_write_phy_dbg(struct alx_adapter *adpt, u16 reg, u16 data)
+int __alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data)
{
int err;
- err = __alx_write_phy_reg(adpt, ALX_MII_DBG_ADDR, reg);
+ err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg);
if (unlikely(err))
return err;
else
- err = __alx_write_phy_reg(adpt, ALX_MII_DBG_DATA, data);
+ err = __alx_write_phy_reg(hw, ALX_MII_DBG_DATA, data);
return err;
}
-int alx_read_phy_reg(struct alx_adapter *adpt, u16 reg, u16 *phy_data)
+int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data)
{
int err;
- spin_lock(&adpt->mdio_lock);
- err = __alx_read_phy_reg(adpt, reg, phy_data);
- spin_unlock(&adpt->mdio_lock);
+ spin_lock(&hw->mdio_lock);
+ err = __alx_read_phy_reg(hw, reg, phy_data);
+ spin_unlock(&hw->mdio_lock);
return err;
}
-int alx_write_phy_reg(struct alx_adapter *adpt, u16 reg, u16 phy_data)
+int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data)
{
int err;
- spin_lock(&adpt->mdio_lock);
- err = __alx_write_phy_reg(adpt, reg, phy_data);
- spin_unlock(&adpt->mdio_lock);
+ spin_lock(&hw->mdio_lock);
+ err = __alx_write_phy_reg(hw, reg, phy_data);
+ spin_unlock(&hw->mdio_lock);
return err;
}
-int alx_read_phy_ext(struct alx_adapter *adpt, u8 dev, u16 reg, u16 *pdata)
+int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata)
{
int err;
- spin_lock(&adpt->mdio_lock);
- err = __alx_read_phy_ext(adpt, dev, reg, pdata);
- spin_unlock(&adpt->mdio_lock);
+ spin_lock(&hw->mdio_lock);
+ err = __alx_read_phy_ext(hw, dev, reg, pdata);
+ spin_unlock(&hw->mdio_lock);
return err;
}
-int alx_write_phy_ext(struct alx_adapter *adpt, u8 dev, u16 reg, u16 data)
+int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data)
{
int err;
- spin_lock(&adpt->mdio_lock);
- err = __alx_write_phy_ext(adpt, dev, reg, data);
- spin_unlock(&adpt->mdio_lock);
+ spin_lock(&hw->mdio_lock);
+ err = __alx_write_phy_ext(hw, dev, reg, data);
+ spin_unlock(&hw->mdio_lock);
return err;
}
-int alx_read_phy_dbg(struct alx_adapter *adpt, u16 reg, u16 *pdata)
+int alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata)
{
int err;
- spin_lock(&adpt->mdio_lock);
- err = __alx_read_phy_dbg(adpt, reg, pdata);
- spin_unlock(&adpt->mdio_lock);
+ spin_lock(&hw->mdio_lock);
+ err = __alx_read_phy_dbg(hw, reg, pdata);
+ spin_unlock(&hw->mdio_lock);
return err;
}
-int alx_write_phy_dbg(struct alx_adapter *adpt, u16 reg, u16 data)
+int alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data)
{
int err;
- spin_lock(&adpt->mdio_lock);
- err = __alx_write_phy_dbg(adpt, reg, data);
- spin_unlock(&adpt->mdio_lock);
+ spin_lock(&hw->mdio_lock);
+ err = __alx_write_phy_dbg(hw, reg, data);
+ spin_unlock(&hw->mdio_lock);
return err;
}
-u16 alx_get_phy_config(struct alx_adapter *adpt)
+u16 alx_get_phy_config(struct alx_hw *hw)
{
u32 val;
u16 phy_val;
- ALX_MEM_R32(adpt, ALX_PHY_CTRL, &val);
+ ALX_MEM_R32(hw, ALX_PHY_CTRL, &val);
/* phy in rst */
if ((val & ALX_PHY_CTRL_DSPRST_OUT) == 0)
return ALX_DRV_PHY_UNKNOWN;
- ALX_MEM_R32(adpt, ALX_DRV, &val);
+ ALX_MEM_R32(hw, ALX_DRV, &val);
val = FIELD_GETX(val, ALX_DRV_PHY);
if (ALX_DRV_PHY_UNKNOWN == val)
return ALX_DRV_PHY_UNKNOWN;
- alx_read_phy_reg(adpt, ALX_MII_DBG_ADDR, &phy_val);
+ alx_read_phy_reg(hw, ALX_MII_DBG_ADDR, &phy_val);
if (ALX_PHY_INITED == phy_val)
return (u16) val;
return ALX_DRV_PHY_UNKNOWN;
}
-bool alx_phy_configed(struct alx_adapter *adpt)
+bool alx_phy_configed(struct alx_hw *hw)
{
u32 cfg, hw_cfg;
- cfg = ethadv_to_hw_cfg(adpt, adpt->adv_cfg);
+ cfg = ethadv_to_hw_cfg(hw, hw->adv_cfg);
cfg = FIELD_GETX(cfg, ALX_DRV_PHY);
- hw_cfg = alx_get_phy_config(adpt);
+ hw_cfg = alx_get_phy_config(hw);
if (hw_cfg == ALX_DRV_PHY_UNKNOWN)
return false;
return cfg == hw_cfg;
}
-int alx_get_phy_link(struct alx_adapter *adpt, bool *link_up, u16 *speed)
+int alx_get_phy_link(struct alx_hw *hw, bool *link_up, u16 *speed)
{
- struct pci_dev *pdev = adpt->pdev;
+ struct pci_dev *pdev = hw->pdev;
u16 bmsr, giga;
int err;
- err = alx_read_phy_reg(adpt, MII_BMSR, &bmsr);
- err = alx_read_phy_reg(adpt, MII_BMSR, &bmsr);
+ err = alx_read_phy_reg(hw, MII_BMSR, &bmsr);
+ err = alx_read_phy_reg(hw, MII_BMSR, &bmsr);
if (unlikely(err))
goto out;
@@ -1049,7 +1064,7 @@ int alx_get_phy_link(struct alx_adapter *adpt, bool *link_up, u16 *speed)
*link_up = true;
/* speed/duplex result is saved in PHY Specific Status Register */
- err = alx_read_phy_reg(adpt, ALX_MII_GIGA_PSSR, &giga);
+ err = alx_read_phy_reg(hw, ALX_MII_GIGA_PSSR, &giga);
if (unlikely(err))
goto out;
@@ -1079,35 +1094,322 @@ out:
return err;
}
-int alx_clear_phy_intr(struct alx_adapter *adpt)
+int alx_clear_phy_intr(struct alx_hw *hw)
{
u16 isr;
/* clear interrupt status by read it */
- return alx_read_phy_reg(adpt, ALX_MII_ISR, &isr);
+ return alx_read_phy_reg(hw, ALX_MII_ISR, &isr);
}
-int alx_config_wol(struct alx_adapter *adpt)
+int alx_config_wol(struct alx_hw *hw)
{
u32 wol;
int err = 0;
wol = 0;
/* turn on magic packet event */
- if (adpt->sleep_ctrl & ALX_SLEEP_WOL_MAGIC) {
+ if (hw->sleep_ctrl & ALX_SLEEP_WOL_MAGIC) {
wol |= ALX_WOL0_MAGIC_EN | ALX_WOL0_PME_MAGIC_EN;
/* magic packet maybe Broadcast&multicast&Unicast frame */
/* mac |= MAC_CTRL_BC_EN; */
}
/* turn on link up event */
- if (adpt->sleep_ctrl & ALX_SLEEP_WOL_PHY) {
+ if (hw->sleep_ctrl & ALX_SLEEP_WOL_PHY) {
wol |= ALX_WOL0_LINK_EN | ALX_WOL0_PME_LINK;
/* only link up can wake up */
- err = alx_write_phy_reg(adpt, ALX_MII_IER, ALX_IER_LINK_UP);
+ err = alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP);
+ }
+ ALX_MEM_W32(hw, ALX_WOL0, wol);
+
+ return err;
+}
+
+void alx_configure_rss(struct alx_hw *hw, bool en)
+{
+ u32 ctrl;
+ int i;
+
+ ALX_MEM_R32(hw, ALX_RXQ0, &ctrl);
+
+ if (en) {
+ for (i = 0; i < sizeof(hw->rss_key); i++) {
+ /* rss key should be saved in chip with
+ * reversed order.
+ */
+ int j = sizeof(hw->rss_key) - i - 1;
+
+ ALX_MEM_W8(hw, ALX_RSS_KEY0 + j, hw->rss_key[i]);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(hw->rss_idt); i++)
+ ALX_MEM_W32(hw, ALX_RSS_IDT_TBL0, hw->rss_idt[i]);
+
+ FIELD_SET32(ctrl, ALX_RXQ0_RSS_HSTYP, hw->rss_hash_type);
+ FIELD_SET32(ctrl, ALX_RXQ0_RSS_MODE, ALX_RXQ0_RSS_MODE_MQMI);
+ FIELD_SET32(ctrl, ALX_RXQ0_IDT_TBL_SIZE, hw->rss_idt_size);
+ ctrl |= ALX_RXQ0_RSS_HASH_EN;
+ } else {
+ ctrl &= ~ALX_RXQ0_RSS_HASH_EN;
+ }
+
+ ALX_MEM_W32(hw, ALX_RXQ0, ctrl);
+}
+
+void alx_configure_basic(struct alx_hw *hw)
+{
+ u32 val, raw_mtu, max_payload;
+ u16 val16;
+ u8 chip_rev = ALX_REVID(hw);
+
+ /* mac address */
+ alx_set_macaddr(hw, hw->mac_addr);
+
+ /* clk gating */
+ ALX_MEM_W32(hw, ALX_CLK_GATE, ALX_CLK_GATE_ALL_A0);
+
+ /* idle timeout to switch clk_125M */
+ if (chip_rev == ALX_REV_B0) {
+ ALX_MEM_W32(hw, ALX_IDLE_DECISN_TIMER,
+ ALX_IDLE_DECISN_TIMER_DEF);
+ }
+
+ /* stats refresh timeout */
+ ALX_MEM_W32(hw, ALX_SMB_TIMER, hw->smb_timer * 500UL);
+
+ /* intr moduration */
+ ALX_MEM_R32(hw, ALX_MASTER, &val);
+ val = val | ALX_MASTER_IRQMOD2_EN |
+ ALX_MASTER_IRQMOD1_EN |
+ ALX_MASTER_SYSALVTIMER_EN;
+ ALX_MEM_W32(hw, ALX_MASTER, val);
+ ALX_MEM_W32(hw, ALX_IRQ_MODU_TIMER,
+ FIELDX(ALX_IRQ_MODU_TIMER1, hw->imt >> 1));
+ /* intr re-trig timeout */
+ ALX_MEM_W32(hw, ALX_INT_RETRIG, ALX_INT_RETRIG_TO);
+ /* tpd threshold to trig int */
+ ALX_MEM_W32(hw, ALX_TINT_TPD_THRSHLD, hw->ith_tpd);
+ ALX_MEM_W32(hw, ALX_TINT_TIMER, hw->imt);
+
+ /* mtu, 8:fcs+vlan */
+ raw_mtu = hw->mtu + ETH_HLEN;
+ ALX_MEM_W32(hw, ALX_MTU, raw_mtu + 8);
+ if (raw_mtu > ALX_MTU_JUMBO_TH)
+ hw->rx_ctrl &= ~ALX_MAC_CTRL_FAST_PAUSE;
+
+ /* txq */
+ if ((raw_mtu + 8) < ALX_TXQ1_JUMBO_TSO_TH)
+ val = (raw_mtu + 8 + 7) >> 3;
+ else
+ val = ALX_TXQ1_JUMBO_TSO_TH >> 3;
+ ALX_MEM_W32(hw, ALX_TXQ1, val | ALX_TXQ1_ERRLGPKT_DROP_EN);
+ max_payload = alx_get_readrq(hw) >> 8;
+ /*
+ * if BIOS had changed the default dma read max length,
+ * restore it to default value
+ */
+ if (max_payload < ALX_DEV_CTRL_MAXRRS_MIN)
+ alx_set_readrq(hw, 128 << ALX_DEV_CTRL_MAXRRS_MIN);
+
+ val = FIELDX(ALX_TXQ0_TPD_BURSTPREF, ALX_TXQ_TPD_BURSTPREF_DEF) |
+ ALX_TXQ0_MODE_ENHANCE |
+ ALX_TXQ0_LSO_8023_EN |
+ ALX_TXQ0_SUPT_IPOPT |
+ FIELDX(ALX_TXQ0_TXF_BURST_PREF, ALX_TXQ_TXF_BURST_PREF_DEF);
+ ALX_MEM_W32(hw, ALX_TXQ0, val);
+ val = FIELDX(ALX_HQTPD_Q1_NUMPREF, ALX_TXQ_TPD_BURSTPREF_DEF) |
+ FIELDX(ALX_HQTPD_Q2_NUMPREF, ALX_TXQ_TPD_BURSTPREF_DEF) |
+ FIELDX(ALX_HQTPD_Q3_NUMPREF, ALX_TXQ_TPD_BURSTPREF_DEF) |
+ ALX_HQTPD_BURST_EN;
+ ALX_MEM_W32(hw, ALX_HQTPD, val);
+
+ /* rxq, flow control */
+ ALX_MEM_R32(hw, ALX_SRAM5, &val);
+ val = FIELD_GETX(val, ALX_SRAM_RXF_LEN) << 3;
+ if (val > ALX_SRAM_RXF_LEN_8K) {
+ val16 = ALX_MTU_STD_ALGN >> 3;
+ val = (val - ALX_RXQ2_RXF_FLOW_CTRL_RSVD) >> 3;
+ } else {
+ val16 = ALX_MTU_STD_ALGN >> 3;
+ val = (val - ALX_MTU_STD_ALGN) >> 3;
+ }
+ ALX_MEM_W32(hw, ALX_RXQ2,
+ FIELDX(ALX_RXQ2_RXF_XOFF_THRESH, val16) |
+ FIELDX(ALX_RXQ2_RXF_XON_THRESH, val));
+ val = FIELDX(ALX_RXQ0_NUM_RFD_PREF, ALX_RXQ0_NUM_RFD_PREF_DEF) |
+ FIELDX(ALX_RXQ0_RSS_MODE, ALX_RXQ0_RSS_MODE_DIS) |
+ FIELDX(ALX_RXQ0_IDT_TBL_SIZE, ALX_RXQ0_IDT_TBL_SIZE_DEF) |
+ ALX_RXQ0_RSS_HSTYP_ALL |
+ ALX_RXQ0_RSS_HASH_EN |
+ ALX_RXQ0_IPV6_PARSE_EN;
+ if (ALX_CAP(hw, GIGA)) {
+ FIELD_SET32(val, ALX_RXQ0_ASPM_THRESH,
+ ALX_RXQ0_ASPM_THRESH_100M);
+ }
+ ALX_MEM_W32(hw, ALX_RXQ0, val);
+
+ /* DMA */
+ ALX_MEM_R32(hw, ALX_DMA, &val);
+ val = FIELDX(ALX_DMA_RORDER_MODE, ALX_DMA_RORDER_MODE_OUT) |
+ ALX_DMA_RREQ_PRI_DATA |
+ FIELDX(ALX_DMA_RREQ_BLEN, max_payload) |
+ FIELDX(ALX_DMA_WDLY_CNT, ALX_DMA_WDLY_CNT_DEF) |
+ FIELDX(ALX_DMA_RDLY_CNT, ALX_DMA_RDLY_CNT_DEF) |
+ FIELDX(ALX_DMA_RCHNL_SEL, hw->dma_chnl - 1);
+ ALX_MEM_W32(hw, ALX_DMA, val);
+
+ /* multi-tx-q weight */
+ if (ALX_CAP(hw, MTQ)) {
+ val = FIELDX(ALX_WRR_PRI, hw->wrr_ctrl) |
+ FIELDX(ALX_WRR_PRI0, hw->wrr[0]) |
+ FIELDX(ALX_WRR_PRI1, hw->wrr[1]) |
+ FIELDX(ALX_WRR_PRI2, hw->wrr[2]) |
+ FIELDX(ALX_WRR_PRI3, hw->wrr[3]);
+ ALX_MEM_W32(hw, ALX_WRR, val);
+ }
+}
+
+void alx_mask_msix(struct alx_hw *hw, int index, bool mask)
+{
+ u32 reg, val;
+
+ reg = ALX_MSIX_ENTRY_BASE + index * PCI_MSIX_ENTRY_SIZE +
+ PCI_MSIX_ENTRY_VECTOR_CTRL;
+
+ val = mask ? PCI_MSIX_ENTRY_CTRL_MASKBIT : 0;
+
+ ALX_MEM_W32(hw, reg, val);
+ ALX_MEM_FLUSH(hw);
+}
+
+int alx_select_powersaving_speed(struct alx_hw *hw, u16 *speed)
+{
+ int i, err;
+ u16 spd, lpa;
+ bool linkup;
+
+ err = alx_get_phy_link(hw, &linkup, &spd);
+ if (err)
+ goto out;
+
+ if (!linkup) {
+ *speed = SPEED_0;
+ goto out;
+ }
+
+ err = alx_read_phy_reg(hw, MII_LPA, &lpa);
+ if (err)
+ goto out;
+
+ if (!(lpa & LPA_LPACK)) {
+ *speed = spd;
+ goto out;
+ }
+ if (lpa & LPA_100FULL)
+ *speed = SPEED_100 + FULL_DUPLEX;
+ else if (lpa & LPA_100HALF)
+ *speed = SPEED_100 + HALF_DUPLEX;
+ else if (lpa & LPA_10FULL)
+ *speed = SPEED_10 + FULL_DUPLEX;
+ else
+ *speed = SPEED_10 + HALF_DUPLEX;
+
+ if (*speed != spd) {
+
+ err = alx_setup_speed_duplex(hw,
+ ALX_SPEED_TO_ETHADV(*speed) | ADVERTISED_Autoneg,
+ ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX);
+ if (err)
+ goto out;
+
+ /* wait for linkup */
+ for (i = 0; i < ALX_MAX_SETUP_LNK_CYCLE; i++) {
+ u16 speed2;
+ bool link_on;
+
+ msleep(100);
+ err = alx_get_phy_link(hw, &link_on, &speed2);
+ if (err)
+ goto out;
+ if (link_on)
+ break;
+ }
+ if (i == ALX_MAX_SETUP_LNK_CYCLE) {
+ err = ALX_LINK_TIMEOUT;
+ goto out;
+ }
}
- ALX_MEM_W32(adpt, ALX_WOL0, wol);
+out:
return err;
}
+void __alx_update_hw_stats(struct alx_hw *hw)
+{
+ u16 reg;
+ u32 data;
+ unsigned long *p;
+
+ /* RX stats */
+ reg = ALX_RX_STATS_BIN;
+ p = &hw->stats.rx_ok;
+ while (reg <= ALX_RX_STATS_END) {
+ ALX_MEM_R32(hw, reg, &data);
+ *p++ += data;
+ reg += 4;
+ }
+
+ /* TX stats */
+ reg = ALX_TX_STATS_BIN;
+ p = &hw->stats.tx_ok;
+ while (reg <= ALX_TX_STATS_END) {
+ ALX_MEM_R32(hw, reg, &data);
+ *p++ += data;
+ reg += 4;
+ }
+}
+
+static const struct alx_platform_patch plats[] __devinitdata = {
+{0x1091, 0x00, 0x1969, 0x0091, 0x1001},
+{0},
+};
+
+void __devinit alx_patch_assign(struct alx_hw *hw)
+{
+ int i = 0;
+
+ while (plats[i].pci_did != 0) {
+ if (plats[i].pci_did == ALX_DID(hw) &&
+ plats[i].subsystem_vid == ALX_SUB_VID(hw) &&
+ plats[i].subsystem_did == ALX_SUB_DID(hw) &&
+ (plats[i].pflag & ALX_PF_ANY_REV ||
+ plats[i].pci_rev == hw->revision)) {
+ if (plats[i].pflag & ALX_PF_LINK)
+ hw->lnk_patch = true;
+ if (plats[i].pflag & ALX_PF_HIB)
+ hw->hib_patch = true;
+ }
+ i++;
+ }
+}
+
+bool __devinit alx_get_phy_info(struct alx_hw *hw)
+{
+ u16 devs1, devs2;
+
+ if (alx_read_phy_reg(hw, MII_PHYSID1, &hw->phy_id[0]) ||
+ alx_read_phy_reg(hw, MII_PHYSID2, &hw->phy_id[1]))
+ return false;
+
+ /* since we haven't PMA/PMD status2 register, we can't
+ * use mdio45_probe function for prtad and mmds.
+ * use fixed MMD3 to get mmds.
+ */
+ if (alx_read_phy_ext(hw, 3, MDIO_DEVS1, &devs1) ||
+ alx_read_phy_ext(hw, 3, MDIO_DEVS2, &devs2))
+ return false;
+ hw->mdio.mmds = devs1 | devs2 << 16;
+
+ return true;
+}
diff --git a/src/alx_hw.h b/src/alx_hw.h
index fc7f602..8790869 100644
--- a/src/alx_hw.h
+++ b/src/alx_hw.h
@@ -17,2098 +17,370 @@
#ifndef ALX_HW_H_
#define ALX_HW_H_
-#include <linux/types.h>
-#include <linux/mii.h>
-#include "alx.h"
-
-#define FIELD_GETX(_x, _name) (((_x) >> (_name##_SHIFT)) & (_name##_MASK))
-#define FIELD_SETS(_x, _name, _v) (\
-(_x) = \
-((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\
-(((u16)(_v) & (_name##_MASK)) << (_name##_SHIFT)))
-#define FIELD_SET32(_x, _name, _v) (\
-(_x) = \
-((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\
-(((_v) & (_name##_MASK)) << (_name##_SHIFT)))
-#define FIELDX(_name, _v) (((_v) & (_name##_MASK)) << (_name##_SHIFT))
-
-/******************************************************************************/
-struct alx_adapter;
-/* function prototype */
-
-int alx_get_perm_macaddr(struct alx_adapter *adpt, u8 *addr);
-void alx_reset_phy(struct alx_adapter *adpt, bool hib_en);
-void alx_reset_pcie(struct alx_adapter *adpt);
-void alx_enable_aspm(struct alx_adapter *adpt, bool l0s_en, bool l1_en);
-int alx_setup_speed_duplex(struct alx_adapter *adpt, u32 ethadv, u8 flowctrl);
-void alx_post_phy_link(struct alx_adapter *adpt, u16 speed, bool az_en);
-int alx_pre_suspend(struct alx_adapter *adpt, u16 speed);
-int alx_read_phy_reg(struct alx_adapter *adpt, u16 reg, u16 *phy_data);
-int alx_write_phy_reg(struct alx_adapter *adpt, u16 reg, u16 phy_data);
-int alx_read_phy_ext(struct alx_adapter *adpt, u8 dev, u16 reg, u16 *pdata);
-int alx_write_phy_ext(struct alx_adapter *adpt, u8 dev, u16 reg, u16 data);
-int alx_read_phy_dbg(struct alx_adapter *adpt, u16 reg, u16 *pdata);
-int alx_write_phy_dbg(struct alx_adapter *adpt, u16 reg, u16 data);
-int alx_get_phy_link(struct alx_adapter *adpt, bool *link_up, u16 *speed);
-int alx_clear_phy_intr(struct alx_adapter *adpt);
-int alx_config_wol(struct alx_adapter *adpt);
-void alx_cfg_mac_fc(struct alx_adapter *adpt, u8 fc);
-void alx_start_mac(struct alx_adapter *adpt);
-int alx_stop_mac(struct alx_adapter *adpt);
-int alx_reset_mac(struct alx_adapter *adpt);
-void alx_set_macaddr(struct alx_adapter *adpt, u8 *addr);
-bool alx_phy_configed(struct alx_adapter *adpt);
-
-/******************************************************************************/
-/* register definition */
-#define ALX_VENDOR_ID PCI_VENDOR_ID_ATTANSIC
-
-/* pci dev-id */
-#define ALX_DEV_ID_AR8161 0x1091 /* l1f */
-#define ALX_DEV_ID_AR8162 0x1090 /* l2f */
-#define ALX_DEV_ID_AR8171 0x10A1
-#define ALX_DEV_ID_AR8172 0x10A0
-
-/* rev definition */
-#define ALX_PCI_REVID_WTH_CR BIT(1) /* bit1: with CardReader */
-#define ALX_PCI_REVID_WTH_XD BIT(0) /* bit0: with xD support */
-#define ALX_PCI_REVID_MASK 0x1FU /* bit[7:2]: real revision */
-#define ALX_PCI_REVID_SHIFT 3
-#define ALX_REV_A0 0
-#define ALX_REV_A1 1
-#define ALX_REV_B0 2
-#define ALX_REV_C0 3
-
-#define ALX_PM_CSR 0x0044 /* 16bit */
-#define ALX_PM_CSR_PME_STAT BIT(15)
-#define ALX_PM_CSR_DSCAL_MASK 0x3U
-#define ALX_PM_CSR_DSCAL_SHIFT 13
-#define ALX_PM_CSR_DSEL_MASK 0xFU
-#define ALX_PM_CSR_DSEL_SHIFT 9
-#define ALX_PM_CSR_PME_EN BIT(8)
-#define ALX_PM_CSR_PWST_MASK 0x3U
-#define ALX_PM_CSR_PWST_SHIFT 0
-
-#define ALX_DEV_CAP 0x005C
-#define ALX_DEV_CAP_SPLSL_MASK 0x3UL
-#define ALX_DEV_CAP_SPLSL_SHIFT 26
-#define ALX_DEV_CAP_SPLV_MASK 0xFFUL
-#define ALX_DEV_CAP_SPLV_SHIFT 18
-#define ALX_DEV_CAP_RBER BIT(15)
-#define ALX_DEV_CAP_PIPRS BIT(14)
-#define ALX_DEV_CAP_AIPRS BIT(13)
-#define ALX_DEV_CAP_ABPRS BIT(12)
-#define ALX_DEV_CAP_L1ACLAT_MASK 0x7UL
-#define ALX_DEV_CAP_L1ACLAT_SHIFT 9
-#define ALX_DEV_CAP_L0SACLAT_MASK 0x7UL
-#define ALX_DEV_CAP_L0SACLAT_SHIFT 6
-#define ALX_DEV_CAP_EXTAG BIT(5)
-#define ALX_DEV_CAP_PHANTOM BIT(4)
-#define ALX_DEV_CAP_MPL_MASK 0x7UL
-#define ALX_DEV_CAP_MPL_SHIFT 0
-#define ALX_DEV_CAP_MPL_128 1
-#define ALX_DEV_CAP_MPL_256 2
-#define ALX_DEV_CAP_MPL_512 3
-#define ALX_DEV_CAP_MPL_1024 4
-#define ALX_DEV_CAP_MPL_2048 5
-#define ALX_DEV_CAP_MPL_4096 6
-
-#define ALX_DEV_CTRL 0x0060 /* 16bit */
-#define ALX_DEV_CTRL_MAXRRS_MASK 0x7U
-#define ALX_DEV_CTRL_MAXRRS_SHIFT 12
-#define ALX_DEV_CTRL_MAXRRS_MIN 2
-#define ALX_DEV_CTRL_NOSNP_EN BIT(11)
-#define ALX_DEV_CTRL_AUXPWR_EN BIT(10)
-#define ALX_DEV_CTRL_PHANTOM_EN BIT(9)
-#define ALX_DEV_CTRL_EXTAG_EN BIT(8)
-#define ALX_DEV_CTRL_MPL_MASK 0x7U
-#define ALX_DEV_CTRL_MPL_SHIFT 5
-#define ALX_DEV_CTRL_RELORD_EN BIT(4)
-#define ALX_DEV_CTRL_URR_EN BIT(3)
-#define ALX_DEV_CTRL_FERR_EN BIT(2)
-#define ALX_DEV_CTRL_NFERR_EN BIT(1)
-#define ALX_DEV_CTRL_CERR_EN BIT(0)
-
-
-#define ALX_DEV_STAT 0x0062 /* 16bit */
-#define ALX_DEV_STAT_XS_PEND BIT(5)
-#define ALX_DEV_STAT_AUXPWR BIT(4)
-#define ALX_DEV_STAT_UR BIT(3)
-#define ALX_DEV_STAT_FERR BIT(2)
-#define ALX_DEV_STAT_NFERR BIT(1)
-#define ALX_DEV_STAT_CERR BIT(0)
-
-#define ALX_LNK_CAP 0x0064
-#define ALX_LNK_CAP_PRTNUM_MASK 0xFFUL
-#define ALX_LNK_CAP_PRTNUM_SHIFT 24
-#define ALX_LNK_CAP_CLK_PM BIT(18)
-#define ALX_LNK_CAP_L1EXTLAT_MASK 0x7UL
-#define ALX_LNK_CAP_L1EXTLAT_SHIFT 15
-#define ALX_LNK_CAP_L0SEXTLAT_MASK 0x7UL
-#define ALX_LNK_CAP_L0SEXTLAT_SHIFT 12
-#define ALX_LNK_CAP_ASPM_SUP_MASK 0x3UL
-#define ALX_LNK_CAP_ASPM_SUP_SHIFT 10
-#define ALX_LNK_CAP_ASPM_SUP_L0S 1
-#define ALX_LNK_CAP_ASPM_SUP_L0SL1 3
-#define ALX_LNK_CAP_MAX_LWH_MASK 0x3FUL
-#define ALX_LNK_CAP_MAX_LWH_SHIFT 4
-#define ALX_LNK_CAP_MAX_LSPD_MASK 0xFUL
-#define ALX_LNK_CAP_MAX_LSPD_SHIFT 0
-
-#define ALX_LNK_CTRL 0x0068 /* 16bit */
-#define ALX_LNK_CTRL_CLK_PM_EN BIT(8)
-#define ALX_LNK_CTRL_EXTSYNC BIT(7)
-#define ALX_LNK_CTRL_CMNCLK_CFG BIT(6)
-#define ALX_LNK_CTRL_RCB_128B BIT(3) /* 0:64b,1:128b */
-#define ALX_LNK_CTRL_ASPM_MASK 0x3U
-#define ALX_LNK_CTRL_ASPM_SHIFT 0
-#define ALX_LNK_CTRL_ASPM_DIS 0
-#define ALX_LNK_CTRL_ASPM_ENL0S 1
-#define ALX_LNK_CTRL_ASPM_ENL1 2
-#define ALX_LNK_CTRL_ASPM_ENL0SL1 3
-
-#define ALX_LNK_STAT 0x006A /* 16bit */
-#define ALX_LNK_STAT_SCLKCFG BIT(12)
-#define ALX_LNK_STAT_LNKTRAIN BIT(11)
-#define ALX_LNK_STAT_TRNERR BIT(10)
-#define ALX_LNK_STAT_LNKSPD_MASK 0xFU
-#define ALX_LNK_STAT_LNKSPD_SHIFT 0
-#define ALX_LNK_STAT_NEGLW_MASK 0x3FU
-#define ALX_LNK_STAT_NEGLW_SHIFT 4
-
-#define ALX_MSIX_MASK 0x0090
-#define ALX_MSIX_PENDING 0x0094
-
-#define ALX_UE_SVRT 0x010C
-#define ALX_UE_SVRT_UR BIT(20)
-#define ALX_UE_SVRT_ECRCERR BIT(19)
-#define ALX_UE_SVRT_MTLP BIT(18)
-#define ALX_UE_SVRT_RCVOVFL BIT(17)
-#define ALX_UE_SVRT_UNEXPCPL BIT(16)
-#define ALX_UE_SVRT_CPLABRT BIT(15)
-#define ALX_UE_SVRT_CPLTO BIT(14)
-#define ALX_UE_SVRT_FCPROTERR BIT(13)
-#define ALX_UE_SVRT_PTLP BIT(12)
-#define ALX_UE_SVRT_DLPROTERR BIT(4)
-#define ALX_UE_SVRT_TRNERR BIT(0)
-
-#define ALX_EFLD 0x0204 /* eeprom/flash load */
-#define ALX_EFLD_F_ENDADDR_MASK 0x3FFUL
-#define ALX_EFLD_F_ENDADDR_SHIFT 16
-#define ALX_EFLD_F_EXIST BIT(10)
-#define ALX_EFLD_E_EXIST BIT(9)
-#define ALX_EFLD_EXIST BIT(8)
-#define ALX_EFLD_STAT BIT(5) /* 0:finish,1:in progress */
-#define ALX_EFLD_IDLE BIT(4)
-#define ALX_EFLD_START BIT(0)
-
-#define ALX_SLD 0x0218 /* efuse load */
-#define ALX_SLD_FREQ_MASK 0x3UL
-#define ALX_SLD_FREQ_SHIFT 24
-#define ALX_SLD_FREQ_100K 0
-#define ALX_SLD_FREQ_200K 1
-#define ALX_SLD_FREQ_300K 2
-#define ALX_SLD_FREQ_400K 3
-#define ALX_SLD_EXIST BIT(23)
-#define ALX_SLD_SLVADDR_MASK 0x7FUL
-#define ALX_SLD_SLVADDR_SHIFT 16
-#define ALX_SLD_IDLE BIT(13)
-#define ALX_SLD_STAT BIT(12) /* 0:finish,1:in progress */
-#define ALX_SLD_START BIT(11)
-#define ALX_SLD_STARTADDR_MASK 0xFFUL
-#define ALX_SLD_STARTADDR_SHIFT 0
-#define ALX_SLD_MAX_TO 100
-
-#define ALX_PCIE_MSIC 0x021C
-#define ALX_PCIE_MSIC_MSIX_DIS BIT(22)
-#define ALX_PCIE_MSIC_MSI_DIS BIT(21)
-
-#define ALX_PPHY_MISC1 0x1000
-#define ALX_PPHY_MISC1_RCVDET BIT(2)
-#define ALX_PPHY_MISC1_NFTS_MASK 0xFFUL
-#define ALX_PPHY_MISC1_NFTS_SHIFT 16
-#define ALX_PPHY_MISC1_NFTS_HIPERF 0xA0
-
-#define ALX_PPHY_MISC2 0x1004
-#define ALX_PPHY_MISC2_L0S_TH_MASK 0x3UL
-#define ALX_PPHY_MISC2_L0S_TH_SHIFT 18
-#define ALX_PPHY_MISC2_CDR_BW_MASK 0x3UL
-#define ALX_PPHY_MISC2_CDR_BW_SHIFT 16
-
-#define ALX_PDLL_TRNS1 0x1104
-#define ALX_PDLL_TRNS1_D3PLLOFF_EN BIT(11)
-#define ALX_PDLL_TRNS1_REGCLK_SEL_NORM BIT(10)
-#define ALX_PDLL_TRNS1_REPLY_TO_MASK 0x3FFUL
-#define ALX_PDLL_TRNS1_REPLY_TO_SHIFT 0
-
-
-#define ALX_TLEXTN_STATS 0x1208
-#define ALX_TLEXTN_STATS_DEVNO_MASK 0x1FUL
-#define ALX_TLEXTN_STATS_DEVNO_SHIFT 16
-#define ALX_TLEXTN_STATS_BUSNO_MASK 0xFFUL
-#define ALX_TLEXTN_STATS_BUSNO_SHIFT 8
-
-#define ALX_EFUSE_CTRL 0x12C0
-#define ALX_EFUSE_CTRL_FLAG BIT(31) /* 0:read,1:write */
-#define ALX_EUFSE_CTRL_ACK BIT(30)
-#define ALX_EFUSE_CTRL_ADDR_MASK 0x3FFUL
-#define ALX_EFUSE_CTRL_ADDR_SHIFT 16
-
-#define ALX_EFUSE_DATA 0x12C4
-
-#define ALX_SPI_OP1 0x12C8
-#define ALX_SPI_OP1_RDID_MASK 0xFFUL
-#define ALX_SPI_OP1_RDID_SHIFT 24
-#define ALX_SPI_OP1_CE_MASK 0xFFUL
-#define ALX_SPI_OP1_CE_SHIFT 16
-#define ALX_SPI_OP1_SE_MASK 0xFFUL
-#define ALX_SPI_OP1_SE_SHIFT 8
-#define ALX_SPI_OP1_PRGRM_MASK 0xFFUL
-#define ALX_SPI_OP1_PRGRM_SHIFT 0
-
-#define ALX_SPI_OP2 0x12CC
-#define ALX_SPI_OP2_READ_MASK 0xFFUL
-#define ALX_SPI_OP2_READ_SHIFT 24
-#define ALX_SPI_OP2_WRSR_MASK 0xFFUL
-#define ALX_SPI_OP2_WRSR_SHIFT 16
-#define ALX_SPI_OP2_RDSR_MASK 0xFFUL
-#define ALX_SPI_OP2_RDSR_SHIFT 8
-#define ALX_SPI_OP2_WREN_MASK 0xFFUL
-#define ALX_SPI_OP2_WREN_SHIFT 0
-
-#define ALX_SPI_OP3 0x12E4
-#define ALX_SPI_OP3_WRDI_MASK 0xFFUL
-#define ALX_SPI_OP3_WRDI_SHIFT 8
-#define ALX_SPI_OP3_EWSR_MASK 0xFFUL
-#define ALX_SPI_OP3_EWSR_SHIFT 0
-
-#define ALX_EF_CTRL 0x12D0
-#define ALX_EF_CTRL_FSTS_MASK 0xFFUL
-#define ALX_EF_CTRL_FSTS_SHIFT 20
-#define ALX_EF_CTRL_CLASS_MASK 0x7UL
-#define ALX_EF_CTRL_CLASS_SHIFT 16
-#define ALX_EF_CTRL_CLASS_F_UNKNOWN 0
-#define ALX_EF_CTRL_CLASS_F_STD 1
-#define ALX_EF_CTRL_CLASS_F_SST 2
-#define ALX_EF_CTRL_CLASS_E_UNKNOWN 0
-#define ALX_EF_CTRL_CLASS_E_1K 1
-#define ALX_EF_CTRL_CLASS_E_4K 2
-#define ALX_EF_CTRL_FRET BIT(15) /* 0:OK,1:fail */
-#define ALX_EF_CTRL_TYP_MASK 0x3UL
-#define ALX_EF_CTRL_TYP_SHIFT 12
-#define ALX_EF_CTRL_TYP_NONE 0
-#define ALX_EF_CTRL_TYP_F 1
-#define ALX_EF_CTRL_TYP_E 2
-#define ALX_EF_CTRL_TYP_UNKNOWN 3
-#define ALX_EF_CTRL_ONE_CLK BIT(10)
-#define ALX_EF_CTRL_ECLK_MASK 0x3UL
-#define ALX_EF_CTRL_ECLK_SHIFT 8
-#define ALX_EF_CTRL_ECLK_125K 0
-#define ALX_EF_CTRL_ECLK_250K 1
-#define ALX_EF_CTRL_ECLK_500K 2
-#define ALX_EF_CTRL_ECLK_1M 3
-#define ALX_EF_CTRL_FBUSY BIT(7)
-#define ALX_EF_CTRL_ACTION BIT(6) /* 1:start,0:stop */
-#define ALX_EF_CTRL_AUTO_OP BIT(5)
-#define ALX_EF_CTRL_SST_MODE BIT(4) /* force using sst */
-#define ALX_EF_CTRL_INST_MASK 0xFUL
-#define ALX_EF_CTRL_INST_SHIFT 0
-#define ALX_EF_CTRL_INST_NONE 0
-#define ALX_EF_CTRL_INST_READ 1 /* for flash & eeprom */
-#define ALX_EF_CTRL_INST_RDID 2
-#define ALX_EF_CTRL_INST_RDSR 3
-#define ALX_EF_CTRL_INST_WREN 4
-#define ALX_EF_CTRL_INST_PRGRM 5
-#define ALX_EF_CTRL_INST_SE 6
-#define ALX_EF_CTRL_INST_CE 7
-#define ALX_EF_CTRL_INST_WRSR 10
-#define ALX_EF_CTRL_INST_EWSR 11
-#define ALX_EF_CTRL_INST_WRDI 12
-#define ALX_EF_CTRL_INST_WRITE 2 /* only for eeprom */
-
-#define ALX_EF_ADDR 0x12D4
-#define ALX_EF_DATA 0x12D8
-#define ALX_SPI_ID 0x12DC
-
-#define ALX_SPI_CFG_START 0x12E0
-
-#define ALX_PMCTRL 0x12F8
-#define ALX_PMCTRL_HOTRST_WTEN BIT(31)
-#define ALX_PMCTRL_ASPM_FCEN BIT(30) /* L0s/L1 dis by MAC based on
- * thrghput(setting in 15A0)
- */
-#define ALX_PMCTRL_SADLY_EN BIT(29)
-#define ALX_PMCTRL_L0S_BUFSRX_EN BIT(28)
-#define ALX_PMCTRL_LCKDET_TIMER_MASK 0xFUL
-#define ALX_PMCTRL_LCKDET_TIMER_SHIFT 24
-#define ALX_PMCTRL_LCKDET_TIMER_DEF 0xC
-#define ALX_PMCTRL_L1REQ_TO_MASK 0xFUL
-#define ALX_PMCTRL_L1REQ_TO_SHIFT 20 /* pm_request_l1 time > @
- * ->L0s not L1
- */
-#define ALX_PMCTRL_L1REG_TO_DEF 0xF
-#define ALX_PMCTRL_TXL1_AFTER_L0S BIT(19)
-#define ALX_PMCTRL_L1_TIMER_MASK 0x7UL
-#define ALX_PMCTRL_L1_TIMER_SHIFT 16
-#define ALX_PMCTRL_L1_TIMER_DIS 0
-#define ALX_PMCTRL_L1_TIMER_2US 1
-#define ALX_PMCTRL_L1_TIMER_4US 2
-#define ALX_PMCTRL_L1_TIMER_8US 3
-#define ALX_PMCTRL_L1_TIMER_16US 4
-#define ALX_PMCTRL_L1_TIMER_24US 5
-#define ALX_PMCTRL_L1_TIMER_32US 6
-#define ALX_PMCTRL_L1_TIMER_63US 7
-#define ALX_PMCTRL_RCVR_WT_1US BIT(15) /* 1:1us, 0:2ms */
-#define ALX_PMCTRL_PWM_VER_11 BIT(14) /* 0:1.0a,1:1.1 */
-#define ALX_PMCTRL_L1_CLKSW_EN BIT(13) /* en pcie clk sw in L1 */
-#define ALX_PMCTRL_L0S_EN BIT(12)
-#define ALX_PMCTRL_RXL1_AFTER_L0S BIT(11)
-#define ALX_PMCTRL_L0S_TIMER_MASK 0x7UL
-#define ALX_PMCTRL_L0S_TIMER_SHIFT 8
-#define ALX_PMCTRL_L1_BUFSRX_EN BIT(7)
-#define ALX_PMCTRL_L1_SRDSRX_PWD BIT(6) /* power down serdes rx */
-#define ALX_PMCTRL_L1_SRDSPLL_EN BIT(5)
-#define ALX_PMCTRL_L1_SRDS_EN BIT(4)
-#define ALX_PMCTRL_L1_EN BIT(3)
-#define ALX_PMCTRL_CLKREQ_EN BIT(2)
-#define ALX_PMCTRL_RBER_EN BIT(1)
-#define ALX_PMCTRL_SPRSDWER_EN BIT(0)
-
-#define ALX_LTSSM_CTRL 0x12FC
-#define ALX_LTSSM_WRO_EN BIT(12)
-
-
-/******************************************************************************/
-
-#define ALX_MASTER 0x1400
-#define ALX_MASTER_OTP_FLG BIT(31)
-#define ALX_MASTER_DEV_NUM_MASK 0x7FUL
-#define ALX_MASTER_DEV_NUM_SHIFT 24
-#define ALX_MASTER_REV_NUM_MASK 0xFFUL
-#define ALX_MASTER_REV_NUM_SHIFT 16
-#define ALX_MASTER_DEASSRT BIT(15) /*ISSUE DE-ASSERT MSG */
-#define ALX_MASTER_RDCLR_INT BIT(14)
-#define ALX_MASTER_DMA_RST BIT(13)
-#define ALX_MASTER_PCLKSEL_SRDS BIT(12) /* 1:alwys sel pclk from
- * serdes, not sw to 25M */
-#define ALX_MASTER_IRQMOD2_EN BIT(11) /* IRQ MODURATION FOR RX */
-#define ALX_MASTER_IRQMOD1_EN BIT(10) /* MODURATION FOR TX/RX */
-#define ALX_MASTER_MANU_INT BIT(9) /* SOFT MANUAL INT */
-#define ALX_MASTER_MANUTIMER_EN BIT(8)
-#define ALX_MASTER_SYSALVTIMER_EN BIT(7) /* SYS ALIVE TIMER EN */
-#define ALX_MASTER_OOB_DIS BIT(6) /* OUT OF BOX DIS */
-#define ALX_MASTER_WAKEN_25M BIT(5) /* WAKE WO. PCIE CLK */
-#define ALX_MASTER_BERT_START BIT(4)
-#define ALX_MASTER_PCIE_TSTMOD_MASK 0x3UL
-#define ALX_MASTER_PCIE_TSTMOD_SHIFT 2
-#define ALX_MASTER_PCIE_RST BIT(1)
-#define ALX_MASTER_DMA_MAC_RST BIT(0) /* RST MAC & DMA */
-#define ALX_DMA_MAC_RST_TO 50
-
-#define ALX_MANU_TIMER 0x1404
-
-#define ALX_IRQ_MODU_TIMER 0x1408
-#define ALX_IRQ_MODU_TIMER2_MASK 0xFFFFUL
-#define ALX_IRQ_MODU_TIMER2_SHIFT 16 /* ONLY FOR RX */
-#define ALX_IRQ_MODU_TIMER1_MASK 0xFFFFUL
-#define ALX_IRQ_MODU_TIMER1_SHIFT 0
-
-#define ALX_PHY_CTRL 0x140C
-#define ALX_PHY_CTRL_ADDR_MASK 0x1FUL
-#define ALX_PHY_CTRL_ADDR_SHIFT 19
-#define ALX_PHY_CTRL_BP_VLTGSW BIT(18)
-#define ALX_PHY_CTRL_100AB_EN BIT(17)
-#define ALX_PHY_CTRL_10AB_EN BIT(16)
-#define ALX_PHY_CTRL_PLL_BYPASS BIT(15)
-#define ALX_PHY_CTRL_POWER_DOWN BIT(14) /* affect MAC & PHY,
- * go to low power sts
- */
-#define ALX_PHY_CTRL_PLL_ON BIT(13) /* 1:PLL ALWAYS ON
- * 0:CAN SWITCH IN LPW
- */
-#define ALX_PHY_CTRL_RST_ANALOG BIT(12)
-#define ALX_PHY_CTRL_HIB_PULSE BIT(11)
-#define ALX_PHY_CTRL_HIB_EN BIT(10)
-#define ALX_PHY_CTRL_GIGA_DIS BIT(9)
-#define ALX_PHY_CTRL_IDDQ_DIS BIT(8) /* POWER ON RST */
-#define ALX_PHY_CTRL_IDDQ BIT(7) /* WHILE REBOOT, BIT8(1)
- * EFFECTS BIT7
- */
-#define ALX_PHY_CTRL_LPW_EXIT BIT(6)
-#define ALX_PHY_CTRL_GATE_25M BIT(5)
-#define ALX_PHY_CTRL_RVRS_ANEG BIT(4)
-#define ALX_PHY_CTRL_ANEG_NOW BIT(3)
-#define ALX_PHY_CTRL_LED_MODE BIT(2)
-#define ALX_PHY_CTRL_RTL_MODE BIT(1)
-#define ALX_PHY_CTRL_DSPRST_OUT BIT(0) /* OUT OF DSP RST STATE */
-#define ALX_PHY_CTRL_DSPRST_TO 80
-#define ALX_PHY_CTRL_CLS (\
- ALX_PHY_CTRL_LED_MODE |\
- ALX_PHY_CTRL_100AB_EN |\
- ALX_PHY_CTRL_PLL_ON)
-
-#define ALX_MAC_STS 0x1410
-#define ALX_MAC_STS_SFORCE_MASK 0xFUL
-#define ALX_MAC_STS_SFORCE_SHIFT 14
-#define ALX_MAC_STS_CALIB_DONE BIT13
-#define ALX_MAC_STS_CALIB_RES_MASK 0x1FUL
-#define ALX_MAC_STS_CALIB_RES_SHIFT 8
-#define ALX_MAC_STS_CALIBERR_MASK 0xFUL
-#define ALX_MAC_STS_CALIBERR_SHIFT 4
-#define ALX_MAC_STS_TXQ_BUSY BIT(3)
-#define ALX_MAC_STS_RXQ_BUSY BIT(2)
-#define ALX_MAC_STS_TXMAC_BUSY BIT(1)
-#define ALX_MAC_STS_RXMAC_BUSY BIT(0)
-#define ALX_MAC_STS_IDLE (\
- ALX_MAC_STS_TXQ_BUSY |\
- ALX_MAC_STS_RXQ_BUSY |\
- ALX_MAC_STS_TXMAC_BUSY |\
- ALX_MAC_STS_RXMAC_BUSY)
-
-#define ALX_MDIO 0x1414
-#define ALX_MDIO_MODE_EXT BIT(30) /* 0:normal,1:ext */
-#define ALX_MDIO_POST_READ BIT(29)
-#define ALX_MDIO_AUTO_POLLING BIT(28)
-#define ALX_MDIO_BUSY BIT(27)
-#define ALX_MDIO_CLK_SEL_MASK 0x7UL
-#define ALX_MDIO_CLK_SEL_SHIFT 24
-#define ALX_MDIO_CLK_SEL_25MD4 0 /* 25M DIV 4 */
-#define ALX_MDIO_CLK_SEL_25MD6 2
-#define ALX_MDIO_CLK_SEL_25MD8 3
-#define ALX_MDIO_CLK_SEL_25MD10 4
-#define ALX_MDIO_CLK_SEL_25MD32 5
-#define ALX_MDIO_CLK_SEL_25MD64 6
-#define ALX_MDIO_CLK_SEL_25MD128 7
-#define ALX_MDIO_START BIT(23)
-#define ALX_MDIO_SPRES_PRMBL BIT(22)
-#define ALX_MDIO_OP_READ BIT(21) /* 1:read,0:write */
-#define ALX_MDIO_REG_MASK 0x1FUL
-#define ALX_MDIO_REG_SHIFT 16
-#define ALX_MDIO_DATA_MASK 0xFFFFUL
-#define ALX_MDIO_DATA_SHIFT 0
-#define ALX_MDIO_MAX_AC_TO 120
-
-#define ALX_MDIO_EXTN 0x1448
-#define ALX_MDIO_EXTN_PORTAD_MASK 0x1FUL
-#define ALX_MDIO_EXTN_PORTAD_SHIFT 21
-#define ALX_MDIO_EXTN_DEVAD_MASK 0x1FUL
-#define ALX_MDIO_EXTN_DEVAD_SHIFT 16
-#define ALX_MDIO_EXTN_REG_MASK 0xFFFFUL
-#define ALX_MDIO_EXTN_REG_SHIFT 0
-
-#define ALX_PHY_STS 0x1418
-#define ALX_PHY_STS_LPW BIT(31)
-#define ALX_PHY_STS_LPI BIT(30)
-#define ALX_PHY_STS_PWON_STRIP_MASK 0xFFFUL
-#define ALX_PHY_STS_PWON_STRIP_SHIFT 16
-
-#define ALX_PHY_STS_DUPLEX BIT(3)
-#define ALX_PHY_STS_LINKUP BIT(2)
-#define ALX_PHY_STS_SPEED_MASK 0x3UL
-#define ALX_PHY_STS_SPEED_SHIFT 0
-#define ALX_PHY_STS_SPEED_1000M 2
-#define ALX_PHY_STS_SPEED_100M 1
-#define ALX_PHY_STS_SPEED_10M 0
-
-#define ALX_BIST0 0x141C
-#define ALX_BIST0_COL_MASK 0x3FUL
-#define ALX_BIST0_COL_SHIFT 24
-#define ALX_BIST0_ROW_MASK 0xFFFUL
-#define ALX_BIST0_ROW_SHIFT 12
-#define ALX_BIST0_STEP_MASK 0xFUL
-#define ALX_BIST0_STEP_SHIFT 8
-#define ALX_BIST0_PATTERN_MASK 0x7UL
-#define ALX_BIST0_PATTERN_SHIFT 4
-#define ALX_BIST0_CRIT BIT(3)
-#define ALX_BIST0_FIXED BIT(2)
-#define ALX_BIST0_FAIL BIT(1)
-#define ALX_BIST0_START BIT(0)
-
-#define ALX_BIST1 0x1420
-#define ALX_BIST1_COL_MASK 0x3FUL
-#define ALX_BIST1_COL_SHIFT 24
-#define ALX_BIST1_ROW_MASK 0xFFFUL
-#define ALX_BIST1_ROW_SHIFT 12
-#define ALX_BIST1_STEP_MASK 0xFUL
-#define ALX_BIST1_STEP_SHIFT 8
-#define ALX_BIST1_PATTERN_MASK 0x7UL
-#define ALX_BIST1_PATTERN_SHIFT 4
-#define ALX_BIST1_CRIT BIT(3)
-#define ALX_BIST1_FIXED BIT(2)
-#define ALX_BIST1_FAIL BIT(1)
-#define ALX_BIST1_START BIT(0)
-
-#define ALX_SERDES 0x1424
-#define ALX_SERDES_PHYCLK_SLWDWN BIT(18)
-#define ALX_SERDES_MACCLK_SLWDWN BIT(17)
-#define ALX_SERDES_SELFB_PLL_MASK 0x3UL
-#define ALX_SERDES_SELFB_PLL_SHIFT 14
-#define ALX_SERDES_PHYCLK_SEL_GTX BIT(13) /* 1:gtx_clk, 0:25M */
-#define ALX_SERDES_PCIECLK_SEL_SRDS BIT(12) /* 1:serdes,0:25M */
-#define ALX_SERDES_BUFS_RX_EN BIT(11)
-#define ALX_SERDES_PD_RX BIT(10)
-#define ALX_SERDES_PLL_EN BIT(9)
-#define ALX_SERDES_EN BIT(8)
-#define ALX_SERDES_SELFB_PLL_SEL_CSR BIT(6) /* 0:state-machine,1:csr */
-#define ALX_SERDES_SELFB_PLL_CSR_MASK 0x3UL
-#define ALX_SERDES_SELFB_PLL_CSR_SHIFT 4
-#define ALX_SERDES_SELFB_PLL_CSR_4 3 /* 4-12% OV-CLK */
-#define ALX_SERDES_SELFB_PLL_CSR_0 2 /* 0-4% OV-CLK */
-#define ALX_SERDES_SELFB_PLL_CSR_12 1 /* 12-18% OV-CLK */
-#define ALX_SERDES_SELFB_PLL_CSR_18 0 /* 18-25% OV-CLK */
-#define ALX_SERDES_VCO_SLOW BIT(3)
-#define ALX_SERDES_VCO_FAST BIT(2)
-#define ALX_SERDES_LOCKDCT_EN BIT(1)
-#define ALX_SERDES_LOCKDCTED BIT(0)
-
-#define ALX_LED_CTRL 0x1428
-#define ALX_LED_CTRL_PATMAP2_MASK 0x3UL
-#define ALX_LED_CTRL_PATMAP2_SHIFT 8
-#define ALX_LED_CTRL_PATMAP1_MASK 0x3UL
-#define ALX_LED_CTRL_PATMAP1_SHIFT 6
-#define ALX_LED_CTRL_PATMAP0_MASK 0x3UL
-#define ALX_LED_CTRL_PATMAP0_SHIFT 4
-#define ALX_LED_CTRL_D3_MODE_MASK 0x3UL
-#define ALX_LED_CTRL_D3_MODE_SHIFT 2
-#define ALX_LED_CTRL_D3_MODE_NORMAL 0
-#define ALX_LED_CTRL_D3_MODE_WOL_DIS 1
-#define ALX_LED_CTRL_D3_MODE_WOL_ANY 2
-#define ALX_LED_CTRL_D3_MODE_WOL_EN 3
-#define ALX_LED_CTRL_DUTY_CYCL_MASK 0x3UL
-#define ALX_LED_CTRL_DUTY_CYCL_SHIFT 0
-#define ALX_LED_CTRL_DUTY_CYCL_50 0 /* 50% */
-#define ALX_LED_CTRL_DUTY_CYCL_125 1 /* 12.5% */
-#define ALX_LED_CTRL_DUTY_CYCL_25 2 /* 25% */
-#define ALX_LED_CTRL_DUTY_CYCL_75 3 /* 75% */
-
-#define ALX_LED_PATN 0x142C
-#define ALX_LED_PATN1_MASK 0xFFFFUL
-#define ALX_LED_PATN1_SHIFT 16
-#define ALX_LED_PATN0_MASK 0xFFFFUL
-#define ALX_LED_PATN0_SHIFT 0
-
-#define ALX_LED_PATN2 0x1430
-#define ALX_LED_PATN2_MASK 0xFFFFUL
-#define ALX_LED_PATN2_SHIFT 0
-
-#define ALX_SYSALV 0x1434
-#define ALX_SYSALV_FLAG BIT(0)
-
-#define ALX_PCIERR_INST 0x1438
-#define ALX_PCIERR_INST_TX_RATE_MASK 0xFUL
-#define ALX_PCIERR_INST_TX_RATE_SHIFT 4
-#define ALX_PCIERR_INST_RX_RATE_MASK 0xFUL
-#define ALX_PCIERR_INST_RX_RATE_SHIFT 0
-
-#define ALX_LPI_DECISN_TIMER 0x143C
-
-#define ALX_LPI_CTRL 0x1440
-#define ALX_LPI_CTRL_CHK_DA BIT(31)
-#define ALX_LPI_CTRL_ENH_TO_MASK 0x1FFFUL
-#define ALX_LPI_CTRL_ENH_TO_SHIFT 12
-#define ALX_LPI_CTRL_ENH_TH_MASK 0x1FUL
-#define ALX_LPI_CTRL_ENH_TH_SHIFT 6
-#define ALX_LPI_CTRL_ENH_EN BIT(5)
-#define ALX_LPI_CTRL_CHK_RX BIT(4)
-#define ALX_LPI_CTRL_CHK_STATE BIT(3)
-#define ALX_LPI_CTRL_GMII BIT(2)
-#define ALX_LPI_CTRL_TO_PHY BIT(1)
-#define ALX_LPI_CTRL_EN BIT(0)
-
-#define ALX_LPI_WAIT 0x1444
-#define ALX_LPI_WAIT_TIMER_MASK 0xFFFFUL
-#define ALX_LPI_WAIT_TIMER_SHIFT 0
-
-#define ALX_HRTBT_VLAN 0x1450 /* HEARTBEAT, FOR CIFS */
-#define ALX_HRTBT_VLANID_MASK 0xFFFFUL /* OR CLOUD */
-#define ALX_HRRBT_VLANID_SHIFT 0
-
-#define ALX_HRTBT_CTRL 0x1454
-#define ALX_HRTBT_CTRL_EN BIT(31)
-#define ALX_HRTBT_CTRL_PERIOD_MASK 0x3FUL
-#define ALX_HRTBT_CTRL_PERIOD_SHIFT 25
-#define ALX_HRTBT_CTRL_HASVLAN BIT(24)
-#define ALX_HRTBT_CTRL_HDRADDR_MASK 0xFFFUL /* A0 */
-#define ALX_HRTBT_CTRL_HDRADDR_SHIFT 12
-#define ALX_HRTBT_CTRL_HDRADDRB0_MASK 0x7FFUL /* B0 */
-#define ALX_HRTBT_CTRL_HDRADDRB0_SHIFT 13
-#define ALX_HRTBT_CTRL_PKT_FRAG BIT(12) /* B0 */
-#define ALX_HRTBT_CTRL_PKTLEN_MASK 0xFFFUL
-#define ALX_HRTBT_CTRL_PKTLEN_SHIFT 0
-
-#define ALX_HRTBT_EXT_CTRL 0x1AD0 /* B0 */
-#define ALX_HRTBT_EXT_CTRL_NS_EN BIT(12)
-#define ALX_HRTBT_EXT_CTRL_FRAG_LEN_MASK 0xFFUL
-#define ALX_HRTBT_EXT_CTRL_FRAG_LEN_SHIFT 4
-#define ALX_HRTBT_EXT_CTRL_IS_8023 BIT(3)
-#define ALX_HRTBT_EXT_CTRL_IS_IPV6 BIT(2)
-#define ALX_HRTBT_EXT_CTRL_WAKEUP_EN BIT(1)
-#define ALX_HRTBT_EXT_CTRL_ARP_EN BIT(0)
-
-#define ALX_HRTBT_REM_IPV4_ADDR 0x1AD4
-#define ALX_HRTBT_HOST_IPV4_ADDR 0x1478/*use ALX_TRD_BUBBLE_DA_IP4*/
-#define ALX_HRTBT_REM_IPV6_ADDR3 0x1AD8
-#define ALX_HRTBT_REM_IPV6_ADDR2 0x1ADC
-#define ALX_HRTBT_REM_IPV6_ADDR1 0x1AE0
-#define ALX_HRTBT_REM_IPV6_ADDR0 0x1AE4
-/*SWOI_HOST_IPV6_ADDR reuse reg1a60-1a6c, 1a70-1a7c, 1aa0-1aac, 1ab0-1abc.*/
-#define ALX_HRTBT_WAKEUP_PORT 0x1AE8
-#define ALX_HRTBT_WAKEUP_PORT_SRC_MASK 0xFFFFUL
-#define ALX_HRTBT_WAKEUP_PORT_SRC_SHIFT 16
-#define ALX_HRTBT_WAKEUP_PORT_DEST_MASK 0xFFFFUL
-#define ALX_HRTBT_WAKEUP_PORT_DEST_SHIFT 0
-
-#define ALX_HRTBT_WAKEUP_DATA7 0x1AEC
-#define ALX_HRTBT_WAKEUP_DATA6 0x1AF0
-#define ALX_HRTBT_WAKEUP_DATA5 0x1AF4
-#define ALX_HRTBT_WAKEUP_DATA4 0x1AF8
-#define ALX_HRTBT_WAKEUP_DATA3 0x1AFC
-#define ALX_HRTBT_WAKEUP_DATA2 0x1B80
-#define ALX_HRTBT_WAKEUP_DATA1 0x1B84
-#define ALX_HRTBT_WAKEUP_DATA0 0x1B88
-
-#define ALX_RXPARSE 0x1458
-#define ALX_RXPARSE_FLT6_L4_MASK 0x3UL
-#define ALX_RXPARSE_FLT6_L4_SHIFT 30
-#define ALX_RXPARSE_FLT6_L3_MASK 0x3UL
-#define ALX_RXPARSE_FLT6_L3_SHIFT 28
-#define ALX_RXPARSE_FLT5_L4_MASK 0x3UL
-#define ALX_RXPARSE_FLT5_L4_SHIFT 26
-#define ALX_RXPARSE_FLT5_L3_MASK 0x3UL
-#define ALX_RXPARSE_FLT5_L3_SHIFT 24
-#define ALX_RXPARSE_FLT4_L4_MASK 0x3UL
-#define ALX_RXPARSE_FLT4_L4_SHIFT 22
-#define ALX_RXPARSE_FLT4_L3_MASK 0x3UL
-#define ALX_RXPARSE_FLT4_L3_SHIFT 20
-#define ALX_RXPARSE_FLT3_L4_MASK 0x3UL
-#define ALX_RXPARSE_FLT3_L4_SHIFT 18
-#define ALX_RXPARSE_FLT3_L3_MASK 0x3UL
-#define ALX_RXPARSE_FLT3_L3_SHIFT 16
-#define ALX_RXPARSE_FLT2_L4_MASK 0x3UL
-#define ALX_RXPARSE_FLT2_L4_SHIFT 14
-#define ALX_RXPARSE_FLT2_L3_MASK 0x3UL
-#define ALX_RXPARSE_FLT2_L3_SHIFT 12
-#define ALX_RXPARSE_FLT1_L4_MASK 0x3UL
-#define ALX_RXPARSE_FLT1_L4_SHIFT 10
-#define ALX_RXPARSE_FLT1_L3_MASK 0x3UL
-#define ALX_RXPARSE_FLT1_L3_SHIFT 8
-#define ALX_RXPARSE_FLT6_EN BIT(5)
-#define ALX_RXPARSE_FLT5_EN BIT(4)
-#define ALX_RXPARSE_FLT4_EN BIT(3)
-#define ALX_RXPARSE_FLT3_EN BIT(2)
-#define ALX_RXPARSE_FLT2_EN BIT(1)
-#define ALX_RXPARSE_FLT1_EN BIT(0)
-#define ALX_RXPARSE_FLT_L4_UDP 0
-#define ALX_RXPARSE_FLT_L4_TCP 1
-#define ALX_RXPARSE_FLT_L4_BOTH 2
-#define ALX_RXPARSE_FLT_L4_NONE 3
-#define ALX_RXPARSE_FLT_L3_IPV6 0
-#define ALX_RXPARSE_FLT_L3_IPV4 1
-#define ALX_RXPARSE_FLT_L3_BOTH 2
-
-/* Terodo support */
-#define ALX_TRD_CTRL 0x145C
-#define ALX_TRD_CTRL_EN BIT(31)
-#define ALX_TRD_CTRL_BUBBLE_WAKE_EN BIT(30)
-#define ALX_TRD_CTRL_PREFIX_CMP_HW BIT(28)
-#define ALX_TRD_CTRL_RSHDR_ADDR_MASK 0xFFFUL
-#define ALX_TRD_CTRL_RSHDR_ADDR_SHIFT 16
-#define ALX_TRD_CTRL_SINTV_MAX_MASK 0xFFUL
-#define ALX_TRD_CTRL_SINTV_MAX_SHIFT 8
-#define ALX_TRD_CTRL_SINTV_MIN_MASK 0xFFUL
-#define ALX_TRD_CTRL_SINTV_MIN_SHIFT 0
-
-#define ALX_TRD_RS 0x1460
-#define ALX_TRD_RS_SZ_MASK 0xFFFUL
-#define ALX_TRD_RS_SZ_SHIFT 20
-#define ALX_TRD_RS_NONCE_OFS_MASK 0xFFFUL
-#define ALX_TRD_RS_NONCE_OFS_SHIFT 8
-#define ALX_TRD_RS_SEQ_OFS_MASK 0xFFUL
-#define ALX_TRD_RS_SEQ_OFS_SHIFT 0
-
-#define ALX_TRD_SRV_IP4 0x1464
-
-#define ALX_TRD_CLNT_EXTNL_IP4 0x1468
-
-#define ALX_TRD_PORT 0x146C
-#define ALX_TRD_PORT_CLNT_EXTNL_MASK 0xFFFFUL
-#define ALX_TRD_PORT_CLNT_EXTNL_SHIFT 16
-#define ALX_TRD_PORT_SRV_MASK 0xFFFFUL
-#define ALX_TRD_PORT_SRV_SHIFT 0
-
-#define ALX_TRD_PREFIX 0x1470
-
-#define ALX_TRD_BUBBLE_DA_IP4 0x1478
-
-#define ALX_TRD_BUBBLE_DA_PORT 0x147C
-
-
-#define ALX_IDLE_DECISN_TIMER 0x1474 /* B0 */
-#define ALX_IDLE_DECISN_TIMER_DEF 0x400 /* 1ms */
-
-
-#define ALX_MAC_CTRL 0x1480
-#define ALX_MAC_CTRL_FAST_PAUSE BIT(31)
-#define ALX_MAC_CTRL_WOLSPED_SWEN BIT(30)
-#define ALX_MAC_CTRL_MHASH_ALG_HI5B BIT(29) /* 1:legacy, 0:marvl(low5b)*/
-#define ALX_MAC_CTRL_SPAUSE_EN BIT(28)
-#define ALX_MAC_CTRL_DBG_EN BIT(27)
-#define ALX_MAC_CTRL_BRD_EN BIT(26)
-#define ALX_MAC_CTRL_MULTIALL_EN BIT(25)
-#define ALX_MAC_CTRL_RX_XSUM_EN BIT(24)
-#define ALX_MAC_CTRL_THUGE BIT(23)
-#define ALX_MAC_CTRL_MBOF BIT(22)
-#define ALX_MAC_CTRL_SPEED_MASK 0x3UL
-#define ALX_MAC_CTRL_SPEED_SHIFT 20
-#define ALX_MAC_CTRL_SPEED_10_100 1
-#define ALX_MAC_CTRL_SPEED_1000 2
-#define ALX_MAC_CTRL_SIMR BIT(19)
-#define ALX_MAC_CTRL_SSTCT BIT(17)
-#define ALX_MAC_CTRL_TPAUSE BIT(16)
-#define ALX_MAC_CTRL_PROMISC_EN BIT(15)
-#define ALX_MAC_CTRL_VLANSTRIP BIT(14)
-#define ALX_MAC_CTRL_PRMBLEN_MASK 0xFUL
-#define ALX_MAC_CTRL_PRMBLEN_SHIFT 10
-#define ALX_MAC_CTRL_RHUGE_EN BIT(9)
-#define ALX_MAC_CTRL_FLCHK BIT(8)
-#define ALX_MAC_CTRL_PCRCE BIT(7)
-#define ALX_MAC_CTRL_CRCE BIT(6)
-#define ALX_MAC_CTRL_FULLD BIT(5)
-#define ALX_MAC_CTRL_LPBACK_EN BIT(4)
-#define ALX_MAC_CTRL_RXFC_EN BIT(3)
-#define ALX_MAC_CTRL_TXFC_EN BIT(2)
-#define ALX_MAC_CTRL_RX_EN BIT(1)
-#define ALX_MAC_CTRL_TX_EN BIT(0)
-
-#define ALX_GAP 0x1484
-#define ALX_GAP_IPGR2_MASK 0x7FUL
-#define ALX_GAP_IPGR2_SHIFT 24
-#define ALX_GAP_IPGR1_MASK 0x7FUL
-#define ALX_GAP_IPGR1_SHIFT 16
-#define ALX_GAP_MIN_IFG_MASK 0xFFUL
-#define ALX_GAP_MIN_IFG_SHIFT 8
-#define ALX_GAP_IPGT_MASK 0x7FUL /* A0 diff with B0 */
-#define ALX_GAP_IPGT_SHIFT 0
-
-#define ALX_STAD0 0x1488
-#define ALX_STAD1 0x148C
-
-#define ALX_HASH_TBL0 0x1490
-#define ALX_HASH_TBL1 0x1494
-
-#define ALX_HALFD 0x1498
-#define ALX_HALFD_JAM_IPG_MASK 0xFUL
-#define ALX_HALFD_JAM_IPG_SHIFT 24
-#define ALX_HALFD_ABEBT_MASK 0xFUL
-#define ALX_HALFD_ABEBT_SHIFT 20
-#define ALX_HALFD_ABEBE BIT(19)
-#define ALX_HALFD_BPNB BIT(18)
-#define ALX_HALFD_NOBO BIT(17)
-#define ALX_HALFD_EDXSDFR BIT(16)
-#define ALX_HALFD_RETRY_MASK 0xFUL
-#define ALX_HALFD_RETRY_SHIFT 12
-#define ALX_HALFD_LCOL_MASK 0x3FFUL
-#define ALX_HALFD_LCOL_SHIFT 0
-
-#define ALX_MTU 0x149C
-#define ALX_MTU_JUMBO_TH 1514
-#define ALX_MTU_STD_ALGN 1536
-#define ALX_MTU_MIN 64
-
-#define ALX_SRAM0 0x1500
-#define ALX_SRAM_RFD_TAIL_ADDR_MASK 0xFFFUL
-#define ALX_SRAM_RFD_TAIL_ADDR_SHIFT 16
-#define ALX_SRAM_RFD_HEAD_ADDR_MASK 0xFFFUL
-#define ALX_SRAM_RFD_HEAD_ADDR_SHIFT 0
-
-#define ALX_SRAM1 0x1510
-#define ALX_SRAM_RFD_LEN_MASK 0xFFFUL /* 8BYTES UNIT */
-#define ALX_SRAM_RFD_LEN_SHIFT 0
-
-#define ALX_SRAM2 0x1518
-#define ALX_SRAM_TRD_TAIL_ADDR_MASK 0xFFFUL
-#define ALX_SRAM_TRD_TAIL_ADDR_SHIFT 16
-#define ALX_SRMA_TRD_HEAD_ADDR_MASK 0xFFFUL
-#define ALX_SRAM_TRD_HEAD_ADDR_SHIFT 0
-
-#define ALX_SRAM3 0x151C
-#define ALX_SRAM_TRD_LEN_MASK 0xFFFUL /* 8BYTES UNIT */
-#define ALX_SRAM_TRD_LEN_SHIFT 0
-
-#define ALX_SRAM4 0x1520
-#define ALX_SRAM_RXF_TAIL_ADDR_MASK 0xFFFUL
-#define ALX_SRAM_RXF_TAIL_ADDR_SHIFT 16
-#define ALX_SRAM_RXF_HEAD_ADDR_MASK 0xFFFUL
-#define ALX_SRAM_RXF_HEAD_ADDR_SHIFT 0
-
-#define ALX_SRAM5 0x1524
-#define ALX_SRAM_RXF_LEN_MASK 0xFFFUL /* 8BYTES UNIT */
-#define ALX_SRAM_RXF_LEN_SHIFT 0
-#define ALX_SRAM_RXF_LEN_8K (8*1024)
-
-#define ALX_SRAM6 0x1528
-#define ALX_SRAM_TXF_TAIL_ADDR_MASK 0xFFFUL
-#define ALX_SRAM_TXF_TAIL_ADDR_SHIFT 16
-#define ALX_SRAM_TXF_HEAD_ADDR_MASK 0xFFFUL
-#define ALX_SRAM_TXF_HEAD_ADDR_SHIFT 0
-
-#define ALX_SRAM7 0x152C
-#define ALX_SRAM_TXF_LEN_MASK 0xFFFUL /* 8BYTES UNIT */
-#define ALX_SRAM_TXF_LEN_SHIFT 0
-
-#define ALX_SRAM8 0x1530
-#define ALX_SRAM_PATTERN_ADDR_MASK 0xFFFUL
-#define ALX_SRAM_PATTERN_ADDR_SHIFT 16
-#define ALX_SRAM_TSO_ADDR_MASK 0xFFFUL
-#define ALX_SRAM_TSO_ADDR_SHIFT 0
-
-#define ALX_SRAM9 0x1534
-#define ALX_SRAM_LOAD_PTR BIT(0)
-
-#define ALX_RX_BASE_ADDR_HI 0x1540
-
-#define ALX_TX_BASE_ADDR_HI 0x1544
-
-#define ALX_RFD_ADDR_LO 0x1550
-#define ALX_RFD_RING_SZ 0x1560
-#define ALX_RFD_BUF_SZ 0x1564
-#define ALX_RFD_BUF_SZ_MASK 0xFFFFUL
-#define ALX_RFD_BUF_SZ_SHIFT 0
-
-#define ALX_RRD_ADDR_LO 0x1568
-#define ALX_RRD_RING_SZ 0x1578
-#define ALX_RRD_RING_SZ_MASK 0xFFFUL
-#define ALX_RRD_RING_SZ_SHIFT 0
-
-#define ALX_TPD_PRI3_ADDR_LO 0x14E4 /* HIGHEST PRIORITY */
-#define ALX_TPD_PRI2_ADDR_LO 0x14E0
-#define ALX_TPD_PRI1_ADDR_LO 0x157C
-#define ALX_TPD_PRI0_ADDR_LO 0x1580 /* LOWEST PRORITY */
-
-#define ALX_TPD_PRI3_PIDX 0x1618 /* 16BIT */
-#define ALX_TPD_PRI2_PIDX 0x161A /* 16BIT */
-#define ALX_TPD_PRI1_PIDX 0x15F0 /* 16BIT */
-#define ALX_TPD_PRI0_PIDX 0x15F2 /* 16BIT */
-
-#define ALX_TPD_PRI3_CIDX 0x161C /* 16BIT */
-#define ALX_TPD_PRI2_CIDX 0x161E /* 16BIT */
-#define ALX_TPD_PRI1_CIDX 0x15F4 /* 16BIT */
-#define ALX_TPD_PRI0_CIDX 0x15F6 /* 16BIT */
-
-#define ALX_TPD_RING_SZ 0x1584
-#define ALX_TPD_RING_SZ_MASK 0xFFFFUL
-#define ALX_TPD_RING_SZ_SHIFT 0
-
-#define ALX_CMB_ADDR_LO 0x1588 /* NOT USED */
-
-#define ALX_TXQ0 0x1590
-#define ALX_TXQ0_TXF_BURST_PREF_MASK 0xFFFFUL
-#define ALX_TXQ0_TXF_BURST_PREF_SHIFT 16
-#define ALX_TXQ_TXF_BURST_PREF_DEF 0x200
-#define ALX_TXQ0_PEDING_CLR BIT(8)
-#define ALX_TXQ0_LSO_8023_EN BIT(7)
-#define ALX_TXQ0_MODE_ENHANCE BIT(6)
-#define ALX_TXQ0_EN BIT(5)
-#define ALX_TXQ0_SUPT_IPOPT BIT(4)
-#define ALX_TXQ0_TPD_BURSTPREF_MASK 0xFUL
-#define ALX_TXQ0_TPD_BURSTPREF_SHIFT 0
-#define ALX_TXQ_TPD_BURSTPREF_DEF 5
-
-#define ALX_TXQ1 0x1594
-#define ALX_TXQ1_ERRLGPKT_DROP_EN BIT(11) /* drop error large
- * (>rfd buf) packet
- */
-#define ALX_TXQ1_JUMBO_TSOTHR_MASK 0x7FFUL /* 8BYTES UNIT */
-#define ALX_TXQ1_JUMBO_TSOTHR_SHIFT 0
-#define ALX_TXQ1_JUMBO_TSO_TH (7*1024) /* byte */
-
-#define ALX_TXQ2 0x1598 /* ENTER L1 CONTROL */
-#define ALX_TXQ2_BURST_EN BIT(31)
-#define ALX_TXQ2_BURST_HI_WM_MASK 0xFFFUL
-#define ALX_TXQ2_BURST_HI_WM_SHIFT 16
-#define ALX_TXQ2_BURST_LO_WM_MASK 0xFFFUL
-#define ALX_TXQ2_BURST_LO_WM_SHIFT 0
-
-#define ALX_RXQ0 0x15A0
-#define ALX_RXQ0_EN BIT(31)
-#define ALX_RXQ0_CUT_THRU_EN BIT(30)
-#define ALX_RXQ0_RSS_HASH_EN BIT(29)
-#define ALX_RXQ0_NON_IP_QTBL BIT(28) /* 0:q0,1:table */
-#define ALX_RXQ0_RSS_MODE_MASK 0x3UL
-#define ALX_RXQ0_RSS_MODE_SHIFT 26
-#define ALX_RXQ0_RSS_MODE_DIS 0
-#define ALX_RXQ0_RSS_MODE_SQSI 1
-#define ALX_RXQ0_RSS_MODE_MQSI 2
-#define ALX_RXQ0_RSS_MODE_MQMI 3
-#define ALX_RXQ0_NUM_RFD_PREF_MASK 0x3FUL
-#define ALX_RXQ0_NUM_RFD_PREF_SHIFT 20
-#define ALX_RXQ0_NUM_RFD_PREF_DEF 8
-#define ALX_RXQ0_IDT_TBL_SIZE_MASK 0x1FFUL
-#define ALX_RXQ0_IDT_TBL_SIZE_SHIFT 8
-#define ALX_RXQ0_IDT_TBL_SIZE_DEF 0x100
-#define ALX_RXQ0_IPV6_PARSE_EN BIT(7)
-#define ALX_RXQ0_RSS_HSTYP_MASK 0xFUL
-#define ALX_RXQ0_RSS_HSTYP_SHIFT 2
-#define ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN BIT(5)
-#define ALX_RXQ0_RSS_HSTYP_IPV6_EN BIT(4)
-#define ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN BIT(3)
-#define ALX_RXQ0_RSS_HSTYP_IPV4_EN BIT(2)
-#define ALX_RXQ0_RSS_HSTYP_ALL (\
- ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN |\
- ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN |\
- ALX_RXQ0_RSS_HSTYP_IPV6_EN |\
- ALX_RXQ0_RSS_HSTYP_IPV4_EN)
-#define ALX_RXQ0_ASPM_THRESH_MASK 0x3UL
-#define ALX_RXQ0_ASPM_THRESH_SHIFT 0
-#define ALX_RXQ0_ASPM_THRESH_NO 0
-#define ALX_RXQ0_ASPM_THRESH_1M 1
-#define ALX_RXQ0_ASPM_THRESH_10M 2
-#define ALX_RXQ0_ASPM_THRESH_100M 3
-
-#define ALX_RXQ1 0x15A4
-#define ALX_RXQ1_JUMBO_LKAH_MASK 0xFUL /* 32BYTES UNIT */
-#define ALX_RXQ1_JUMBO_LKAH_SHIFT 12
-#define ALX_RXQ1_RFD_PREF_DOWN_MASK 0x3FUL
-#define ALX_RXQ1_RFD_PREF_DOWN_SHIFT 6
-#define ALX_RXQ1_RFD_PREF_UP_MASK 0x3FUL
-#define ALX_RXQ1_RFD_PREF_UP_SHIFT 0
-
-#define ALX_RXQ2 0x15A8
-/* XOFF: USED SRAM LOWER THAN IT, THEN NOTIFY THE PEER TO SEND AGAIN */
-#define ALX_RXQ2_RXF_XOFF_THRESH_MASK 0xFFFUL
-#define ALX_RXQ2_RXF_XOFF_THRESH_SHIFT 16
-#define ALX_RXQ2_RXF_XON_THRESH_MASK 0xFFFUL
-#define ALX_RXQ2_RXF_XON_THRESH_SHIFT 0
-/* Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) +
- * rx-packet(1522) + delay-of-link(64)
- * = 3212.
+/* specific error info */
+#define ALX_ERR_SUCCESS 0x0000
+#define ALX_ERR_ALOAD 0x0001
+#define ALX_ERR_RSTMAC 0x0002
+#define ALX_ERR_PARM 0x0003
+#define ALX_ERR_MIIBUSY 0x0004
+#define ALX_LINK_TIMEOUT 0x0008
+
+/* Transmit Packet Descriptor, contains 4 32-bit words.
+ *
+ * 31 16 0
+ * +----------------+----------------+
+ * | vlan-tag | buf length |
+ * +----------------+----------------+
+ * | Word 1 |
+ * +----------------+----------------+
+ * | Word 2: buf addr lo |
+ * +----------------+----------------+
+ * | Word 3: buf addr hi |
+ * +----------------+----------------+
+ *
+ * Word 2 and 3 combine to form a 64-bit buffer address
+ *
+ * Word 1 has three forms, depending on the state of bit 8/12/13:
+ * if bit8 =='1', the definition is just for custom checksum offload.
+ * if bit8 == '0' && bit12 == '1' && bit13 == '1', the *FIRST* descriptor
+ * for the skb is special for LSO V2, Word 2 become total skb length ,
+ * Word 3 is meaningless.
+ * other condition, the definition is for general skb or ip/tcp/udp
+ * checksum or LSO(TSO) offload.
+ *
+ * Here is the depiction:
+ *
+ * 0-+ 0-+
+ * 1 | 1 |
+ * 2 | 2 |
+ * 3 | Payload offset 3 | L4 header offset
+ * 4 | (7:0) 4 | (7:0)
+ * 5 | 5 |
+ * 6 | 6 |
+ * 7-+ 7-+
+ * 8 Custom csum enable = 1 8 Custom csum enable = 0
+ * 9 General IPv4 checksum 9 General IPv4 checksum
+ * 10 General TCP checksum 10 General TCP checksum
+ * 11 General UDP checksum 11 General UDP checksum
+ * 12 Large Send Segment enable 12 Large Send Segment enable
+ * 13 Large Send Segment type 13 Large Send Segment type
+ * 14 VLAN tagged 14 VLAN tagged
+ * 15 Insert VLAN tag 15 Insert VLAN tag
+ * 16 IPv4 packet 16 IPv4 packet
+ * 17 Ethernet frame type 17 Ethernet frame type
+ * 18-+ 18-+
+ * 19 | 19 |
+ * 20 | 20 |
+ * 21 | Custom csum offset 21 |
+ * 22 | (25:18) 22 |
+ * 23 | 23 | MSS (30:18)
+ * 24 | 24 |
+ * 25-+ 25 |
+ * 26-+ 26 |
+ * 27 | 27 |
+ * 28 | Reserved 28 |
+ * 29 | 29 |
+ * 30-+ 30-+
+ * 31 End of packet 31 End of packet
*/
-#define ALX_RXQ2_RXF_FLOW_CTRL_RSVD 3212
-
-#define ALX_RXQ3 0x15AC
-#define ALX_RXQ3_RXD_TIMER_MASK 0x7FFFUL
-#define ALX_RXQ3_RXD_TIMER_SHIFT 16
-#define ALX_RXQ3_RXD_THRESH_MASK 0xFFFUL /* 8BYTES UNIT */
-#define ALX_RXQ3_RXD_THRESH_SHIFT 0
-
-#define ALX_DMA 0x15C0
-#define ALX_DMA_SMB_NOW BIT(31)
-#define ALX_DMA_WPEND_CLR BIT(30)
-#define ALX_DMA_RPEND_CLR BIT(29)
-#define ALX_DMA_WSRAM_RDCTRL BIT(28)
-#define ALX_DMA_RCHNL_SEL_MASK 0x3UL
-#define ALX_DMA_RCHNL_SEL_SHIFT 26
-#define ALX_DMA_RCHNL_SEL_1 0
-#define ALX_DMA_RCHNL_SEL_2 1
-#define ALX_DMA_RCHNL_SEL_3 2
-#define ALX_DMA_RCHNL_SEL_4 3
-#define ALX_DMA_SMB_EN BIT(21) /* smb dma enable */
-#define ALX_DMA_WDLY_CNT_MASK 0xFUL
-#define ALX_DMA_WDLY_CNT_SHIFT 16
-#define ALX_DMA_WDLY_CNT_DEF 4
-#define ALX_DMA_RDLY_CNT_MASK 0x1FUL
-#define ALX_DMA_RDLY_CNT_SHIFT 11
-#define ALX_DMA_RDLY_CNT_DEF 15
-#define ALX_DMA_RREQ_PRI_DATA BIT(10) /* 0:tpd, 1:data */
-#define ALX_DMA_WREQ_BLEN_MASK 0x7UL
-#define ALX_DMA_WREQ_BLEN_SHIFT 7
-#define ALX_DMA_RREQ_BLEN_MASK 0x7UL
-#define ALX_DMA_RREQ_BLEN_SHIFT 4
-#define ALX_DMA_PENDING_AUTO_RST BIT(3)
-#define ALX_DMA_RORDER_MODE_MASK 0x7UL
-#define ALX_DMA_RORDER_MODE_SHIFT 0
-#define ALX_DMA_RORDER_MODE_OUT 4
-#define ALX_DMA_RORDER_MODE_ENHANCE 2
-#define ALX_DMA_RORDER_MODE_IN 1
-
-#define ALX_WOL0 0x14A0
-#define ALX_WOL0_PT7_MATCH BIT(31)
-#define ALX_WOL0_PT6_MATCH BIT(30)
-#define ALX_WOL0_PT5_MATCH BIT(29)
-#define ALX_WOL0_PT4_MATCH BIT(28)
-#define ALX_WOL0_PT3_MATCH BIT(27)
-#define ALX_WOL0_PT2_MATCH BIT(26)
-#define ALX_WOL0_PT1_MATCH BIT(25)
-#define ALX_WOL0_PT0_MATCH BIT(24)
-#define ALX_WOL0_PT7_EN BIT(23)
-#define ALX_WOL0_PT6_EN BIT(22)
-#define ALX_WOL0_PT5_EN BIT(21)
-#define ALX_WOL0_PT4_EN BIT(20)
-#define ALX_WOL0_PT3_EN BIT(19)
-#define ALX_WOL0_PT2_EN BIT(18)
-#define ALX_WOL0_PT1_EN BIT(17)
-#define ALX_WOL0_PT0_EN BIT(16)
-#define ALX_WOL0_IPV4_SYNC_EVT BIT(14)
-#define ALX_WOL0_IPV6_SYNC_EVT BIT(13)
-#define ALX_WOL0_LINK_EVT BIT(10)
-#define ALX_WOL0_MAGIC_EVT BIT(9)
-#define ALX_WOL0_PATTERN_EVT BIT(8)
-#define ALX_WOL0_SWOI_EVT BIT(7)
-#define ALX_WOL0_OOB_EN BIT(6)
-#define ALX_WOL0_PME_LINK BIT(5)
-#define ALX_WOL0_LINK_EN BIT(4)
-#define ALX_WOL0_PME_MAGIC_EN BIT(3)
-#define ALX_WOL0_MAGIC_EN BIT(2)
-#define ALX_WOL0_PME_PATTERN_EN BIT(1)
-#define ALX_WOL0_PATTERN_EN BIT(0)
-
-#define ALX_WOL1 0x14A4
-#define ALX_WOL1_PT3_LEN_MASK 0xFFUL
-#define ALX_WOL1_PT3_LEN_SHIFT 24
-#define ALX_WOL1_PT2_LEN_MASK 0xFFUL
-#define ALX_WOL1_PT2_LEN_SHIFT 16
-#define ALX_WOL1_PT1_LEN_MASK 0xFFUL
-#define ALX_WOL1_PT1_LEN_SHIFT 8
-#define ALX_WOL1_PT0_LEN_MASK 0xFFUL
-#define ALX_WOL1_PT0_LEN_SHIFT 0
-
-#define ALX_WOL2 0x14A8
-#define ALX_WOL2_PT7_LEN_MASK 0xFFUL
-#define ALX_WOL2_PT7_LEN_SHIFT 24
-#define ALX_WOL2_PT6_LEN_MASK 0xFFUL
-#define ALX_WOL2_PT6_LEN_SHIFT 16
-#define ALX_WOL2_PT5_LEN_MASK 0xFFUL
-#define ALX_WOL2_PT5_LEN_SHIFT 8
-#define ALX_WOL2_PT4_LEN_MASK 0xFFUL
-#define ALX_WOL2_PT4_LEN_SHIFT 0
-
-#define ALX_RFD_PIDX 0x15E0
-#define ALX_RFD_PIDX_MASK 0xFFFUL
-#define ALX_RFD_PIDX_SHIFT 0
-
-#define ALX_RFD_CIDX 0x15F8
-#define ALX_RFD_CIDX_MASK 0xFFFUL
-#define ALX_RFD_CIDX_SHIFT 0
-
-/* MIB */
-#define ALX_MIB_BASE 0x1700
-#define ALX_MIB_RX_OK (ALX_MIB_BASE + 0)
-#define ALX_MIB_RX_BC (ALX_MIB_BASE + 4)
-#define ALX_MIB_RX_MC (ALX_MIB_BASE + 8)
-#define ALX_MIB_RX_PAUSE (ALX_MIB_BASE + 12)
-#define ALX_MIB_RX_CTRL (ALX_MIB_BASE + 16)
-#define ALX_MIB_RX_FCS (ALX_MIB_BASE + 20)
-#define ALX_MIB_RX_LENERR (ALX_MIB_BASE + 24)
-#define ALX_MIB_RX_BYTCNT (ALX_MIB_BASE + 28)
-#define ALX_MIB_RX_RUNT (ALX_MIB_BASE + 32)
-#define ALX_MIB_RX_FRAGMENT (ALX_MIB_BASE + 36)
-#define ALX_MIB_RX_64B (ALX_MIB_BASE + 40)
-#define ALX_MIB_RX_127B (ALX_MIB_BASE + 44)
-#define ALX_MIB_RX_255B (ALX_MIB_BASE + 48)
-#define ALX_MIB_RX_511B (ALX_MIB_BASE + 52)
-#define ALX_MIB_RX_1023B (ALX_MIB_BASE + 56)
-#define ALX_MIB_RX_1518B (ALX_MIB_BASE + 60)
-#define ALX_MIB_RX_SZMAX (ALX_MIB_BASE + 64)
-#define ALX_MIB_RX_OVSZ (ALX_MIB_BASE + 68)
-#define ALX_MIB_RXF_OV (ALX_MIB_BASE + 72)
-#define ALX_MIB_RRD_OV (ALX_MIB_BASE + 76)
-#define ALX_MIB_RX_ALIGN (ALX_MIB_BASE + 80)
-#define ALX_MIB_RX_BCCNT (ALX_MIB_BASE + 84)
-#define ALX_MIB_RX_MCCNT (ALX_MIB_BASE + 88)
-#define ALX_MIB_RX_ERRADDR (ALX_MIB_BASE + 92)
-#define ALX_MIB_TX_OK (ALX_MIB_BASE + 96)
-#define ALX_MIB_TX_BC (ALX_MIB_BASE + 100)
-#define ALX_MIB_TX_MC (ALX_MIB_BASE + 104)
-#define ALX_MIB_TX_PAUSE (ALX_MIB_BASE + 108)
-#define ALX_MIB_TX_EXCDEFER (ALX_MIB_BASE + 112)
-#define ALX_MIB_TX_CTRL (ALX_MIB_BASE + 116)
-#define ALX_MIB_TX_DEFER (ALX_MIB_BASE + 120)
-#define ALX_MIB_TX_BYTCNT (ALX_MIB_BASE + 124)
-#define ALX_MIB_TX_64B (ALX_MIB_BASE + 128)
-#define ALX_MIB_TX_127B (ALX_MIB_BASE + 132)
-#define ALX_MIB_TX_255B (ALX_MIB_BASE + 136)
-#define ALX_MIB_TX_511B (ALX_MIB_BASE + 140)
-#define ALX_MIB_TX_1023B (ALX_MIB_BASE + 144)
-#define ALX_MIB_TX_1518B (ALX_MIB_BASE + 148)
-#define ALX_MIB_TX_SZMAX (ALX_MIB_BASE + 152)
-#define ALX_MIB_TX_1COL (ALX_MIB_BASE + 156)
-#define ALX_MIB_TX_2COL (ALX_MIB_BASE + 160)
-#define ALX_MIB_TX_LATCOL (ALX_MIB_BASE + 164)
-#define ALX_MIB_TX_ABRTCOL (ALX_MIB_BASE + 168)
-#define ALX_MIB_TX_UNDRUN (ALX_MIB_BASE + 172)
-#define ALX_MIB_TX_TRDBEOP (ALX_MIB_BASE + 176)
-#define ALX_MIB_TX_LENERR (ALX_MIB_BASE + 180)
-#define ALX_MIB_TX_TRUNC (ALX_MIB_BASE + 184)
-#define ALX_MIB_TX_BCCNT (ALX_MIB_BASE + 188)
-#define ALX_MIB_TX_MCCNT (ALX_MIB_BASE + 192)
-#define ALX_MIB_UPDATE (ALX_MIB_BASE + 196)
-
-#define ALX_RX_STATS_BIN ALX_MIB_RX_OK
-#define ALX_RX_STATS_END ALX_MIB_RX_ERRADDR
-#define ALX_TX_STATS_BIN ALX_MIB_TX_OK
-#define ALX_TX_STATS_END ALX_MIB_TX_MCCNT
-/******************************************************************************/
-
-#define ALX_ISR 0x1600
-#define ALX_ISR_DIS BIT(31)
-#define ALX_ISR_RX_Q7 BIT(30)
-#define ALX_ISR_RX_Q6 BIT(29)
-#define ALX_ISR_RX_Q5 BIT(28)
-#define ALX_ISR_RX_Q4 BIT(27)
-#define ALX_ISR_PCIE_LNKDOWN BIT(26)
-#define ALX_ISR_PCIE_CERR BIT(25)
-#define ALX_ISR_PCIE_NFERR BIT(24)
-#define ALX_ISR_PCIE_FERR BIT(23)
-#define ALX_ISR_PCIE_UR BIT(22)
-#define ALX_ISR_MAC_TX BIT(21)
-#define ALX_ISR_MAC_RX BIT(20)
-#define ALX_ISR_RX_Q3 BIT(19)
-#define ALX_ISR_RX_Q2 BIT(18)
-#define ALX_ISR_RX_Q1 BIT(17)
-#define ALX_ISR_RX_Q0 BIT(16)
-#define ALX_ISR_TX_Q0 BIT(15)
-#define ALX_ISR_TXQ_TO BIT(14)
-#define ALX_ISR_PHY_LPW BIT(13)
-#define ALX_ISR_PHY BIT(12)
-#define ALX_ISR_TX_CREDIT BIT(11)
-#define ALX_ISR_DMAW BIT(10)
-#define ALX_ISR_DMAR BIT(9)
-#define ALX_ISR_TXF_UR BIT(8)
-#define ALX_ISR_TX_Q3 BIT(7)
-#define ALX_ISR_TX_Q2 BIT(6)
-#define ALX_ISR_TX_Q1 BIT(5)
-#define ALX_ISR_RFD_UR BIT(4)
-#define ALX_ISR_RXF_OV BIT(3)
-#define ALX_ISR_MANU BIT(2)
-#define ALX_ISR_TIMER BIT(1)
-#define ALX_ISR_SMB BIT(0)
-
-#define ALX_IMR 0x1604
-
-#define ALX_INT_RETRIG 0x1608 /* re-send deassrt/assert
- * if sw no reflect
- */
-#define ALX_INT_RETRIG_TIMER_MASK 0xFFFFUL
-#define ALX_INT_RETRIG_TIMER_SHIFT 0
-#define ALX_INT_RETRIG_TO 20000 /* 40ms */
-
-#define ALX_INT_DEASST_TIMER 0x1614 /* re-send deassert
- * if sw no reflect
- */
-
-#define ALX_PATTERN_MASK 0x1620 /* 128bytes, sleep state */
-#define ALX_PATTERN_MASK_LEN 128
-
-
-#define ALX_FLT1_SRC_IP0 0x1A00
-#define ALX_FLT1_SRC_IP1 0x1A04
-#define ALX_FLT1_SRC_IP2 0x1A08
-#define ALX_FLT1_SRC_IP3 0x1A0C
-#define ALX_FLT1_DST_IP0 0x1A10
-#define ALX_FLT1_DST_IP1 0x1A14
-#define ALX_FLT1_DST_IP2 0x1A18
-#define ALX_FLT1_DST_IP3 0x1A1C
-#define ALX_FLT1_PORT 0x1A20
-#define ALX_FLT1_PORT_DST_MASK 0xFFFFUL
-#define ALX_FLT1_PORT_DST_SHIFT 16
-#define ALX_FLT1_PORT_SRC_MASK 0xFFFFUL
-#define ALX_FLT1_PORT_SRC_SHIFT 0
-
-#define ALX_FLT2_SRC_IP0 0x1A24
-#define ALX_FLT2_SRC_IP1 0x1A28
-#define ALX_FLT2_SRC_IP2 0x1A2C
-#define ALX_FLT2_SRC_IP3 0x1A30
-#define ALX_FLT2_DST_IP0 0x1A34
-#define ALX_FLT2_DST_IP1 0x1A38
-#define ALX_FLT2_DST_IP2 0x1A40
-#define ALX_FLT2_DST_IP3 0x1A44
-#define ALX_FLT2_PORT 0x1A48
-#define ALX_FLT2_PORT_DST_MASK 0xFFFFUL
-#define ALX_FLT2_PORT_DST_SHIFT 16
-#define ALX_FLT2_PORT_SRC_MASK 0xFFFFUL
-#define ALX_FLT2_PORT_SRC_SHIFT 0
-
-#define ALX_FLT3_SRC_IP0 0x1A4C
-#define ALX_FLT3_SRC_IP1 0x1A50
-#define ALX_FLT3_SRC_IP2 0x1A54
-#define ALX_FLT3_SRC_IP3 0x1A58
-#define ALX_FLT3_DST_IP0 0x1A5C
-#define ALX_FLT3_DST_IP1 0x1A60
-#define ALX_FLT3_DST_IP2 0x1A64
-#define ALX_FLT3_DST_IP3 0x1A68
-#define ALX_FLT3_PORT 0x1A6C
-#define ALX_FLT3_PORT_DST_MASK 0xFFFFUL
-#define ALX_FLT3_PORT_DST_SHIFT 16
-#define ALX_FLT3_PORT_SRC_MASK 0xFFFFUL
-#define ALX_FLT3_PORT_SRC_SHIFT 0
-
-#define ALX_FLT4_SRC_IP0 0x1A70
-#define ALX_FLT4_SRC_IP1 0x1A74
-#define ALX_FLT4_SRC_IP2 0x1A78
-#define ALX_FLT4_SRC_IP3 0x1A7C
-#define ALX_FLT4_DST_IP0 0x1A80
-#define ALX_FLT4_DST_IP1 0x1A84
-#define ALX_FLT4_DST_IP2 0x1A88
-#define ALX_FLT4_DST_IP3 0x1A8C
-#define ALX_FLT4_PORT 0x1A90
-#define ALX_FLT4_PORT_DST_MASK 0xFFFFUL
-#define ALX_FLT4_PORT_DST_SHIFT 16
-#define ALX_FLT4_PORT_SRC_MASK 0xFFFFUL
-#define ALX_FLT4_PORT_SRC_SHIFT 0
-
-#define ALX_FLT5_SRC_IP0 0x1A94
-#define ALX_FLT5_SRC_IP1 0x1A98
-#define ALX_FLT5_SRC_IP2 0x1A9C
-#define ALX_FLT5_SRC_IP3 0x1AA0
-#define ALX_FLT5_DST_IP0 0x1AA4
-#define ALX_FLT5_DST_IP1 0x1AA8
-#define ALX_FLT5_DST_IP2 0x1AAC
-#define ALX_FLT5_DST_IP3 0x1AB0
-#define ALX_FLT5_PORT 0x1AB4
-#define ALX_FLT5_PORT_DST_MASK 0xFFFFUL
-#define ALX_FLT5_PORT_DST_SHIFT 16
-#define ALX_FLT5_PORT_SRC_MASK 0xFFFFUL
-#define ALX_FLT5_PORT_SRC_SHIFT 0
-
-#define ALX_FLT6_SRC_IP0 0x1AB8
-#define ALX_FLT6_SRC_IP1 0x1ABC
-#define ALX_FLT6_SRC_IP2 0x1AC0
-#define ALX_FLT6_SRC_IP3 0x1AC8
-#define ALX_FLT6_DST_IP0 0x1620 /* only S0 state */
-#define ALX_FLT6_DST_IP1 0x1624
-#define ALX_FLT6_DST_IP2 0x1628
-#define ALX_FLT6_DST_IP3 0x162C
-#define ALX_FLT6_PORT 0x1630
-#define ALX_FLT6_PORT_DST_MASK 0xFFFFUL
-#define ALX_FLT6_PORT_DST_SHIFT 16
-#define ALX_FLT6_PORT_SRC_MASK 0xFFFFUL
-#define ALX_FLT6_PORT_SRC_SHIFT 0
-
-#define ALX_FLTCTRL 0x1634
-#define ALX_FLTCTRL_PSTHR_TIMER_MASK 0xFFUL
-#define ALX_FLTCTRL_PSTHR_TIMER_SHIFT 24
-#define ALX_FLTCTRL_CHK_DSTPRT6 BIT(23)
-#define ALX_FLTCTRL_CHK_SRCPRT6 BIT(22)
-#define ALX_FLTCTRL_CHK_DSTIP6 BIT(21)
-#define ALX_FLTCTRL_CHK_SRCIP6 BIT(20)
-#define ALX_FLTCTRL_CHK_DSTPRT5 BIT(19)
-#define ALX_FLTCTRL_CHK_SRCPRT5 BIT(18)
-#define ALX_FLTCTRL_CHK_DSTIP5 BIT(17)
-#define ALX_FLTCTRL_CHK_SRCIP5 BIT(16)
-#define ALX_FLTCTRL_CHK_DSTPRT4 BIT(15)
-#define ALX_FLTCTRL_CHK_SRCPRT4 BIT(14)
-#define ALX_FLTCTRL_CHK_DSTIP4 BIT(13)
-#define ALX_FLTCTRL_CHK_SRCIP4 BIT(12)
-#define ALX_FLTCTRL_CHK_DSTPRT3 BIT(11)
-#define ALX_FLTCTRL_CHK_SRCPRT3 BIT(10)
-#define ALX_FLTCTRL_CHK_DSTIP3 BIT(9)
-#define ALX_FLTCTRL_CHK_SRCIP3 BIT(8)
-#define ALX_FLTCTRL_CHK_DSTPRT2 BIT(7)
-#define ALX_FLTCTRL_CHK_SRCPRT2 BIT(6)
-#define ALX_FLTCTRL_CHK_DSTIP2 BIT(5)
-#define ALX_FLTCTRL_CHK_SRCIP2 BIT(4)
-#define ALX_FLTCTRL_CHK_DSTPRT1 BIT(3)
-#define ALX_FLTCTRL_CHK_SRCPRT1 BIT(2)
-#define ALX_FLTCTRL_CHK_DSTIP1 BIT(1)
-#define ALX_FLTCTRL_CHK_SRCIP1 BIT(0)
-
-#define ALX_DROP_ALG1 0x1638
-#define ALX_DROP_ALG1_BWCHGVAL_MASK 0xFFFFFUL
-#define ALX_DROP_ALG1_BWCHGVAL_SHIFT 12
-#define ALX_DROP_ALG1_BWCHGSCL_6 BIT(11) /* 0:3.125%, 1:6.25% */
-#define ALX_DROP_ALG1_ASUR_LWQ_EN BIT(10)
-#define ALX_DROP_ALG1_BWCHGVAL_EN BIT(9)
-#define ALX_DROP_ALG1_BWCHGSCL_EN BIT(8)
-#define ALX_DROP_ALG1_PSTHR_AUTO BIT(7) /* 0:manual, 1:auto */
-#define ALX_DROP_ALG1_MIN_PSTHR_MASK 0x3UL
-#define ALX_DROP_ALG1_MIN_PSTHR_SHIFT 5
-#define ALX_DROP_ALG1_MIN_PSTHR_1_16 0
-#define ALX_DROP_ALG1_MIN_PSTHR_1_8 1
-#define ALX_DROP_ALG1_MIN_PSTHR_1_4 2
-#define ALX_DROP_ALG1_MIN_PSTHR_1_2 3
-#define ALX_DROP_ALG1_PSCL_MASK 0x3UL
-#define ALX_DROP_ALG1_PSCL_SHIFT 3
-#define ALX_DROP_ALG1_PSCL_1_4 0
-#define ALX_DROP_ALG1_PSCL_1_8 1
-#define ALX_DROP_ALG1_PSCL_1_16 2
-#define ALX_DROP_ALG1_PSCL_1_32 3
-#define ALX_DROP_ALG1_TIMESLOT_MASK 0x7UL
-#define ALX_DROP_ALG1_TIMESLOT_SHIFT 0
-#define ALX_DROP_ALG1_TIMESLOT_4MS 0
-#define ALX_DROP_ALG1_TIMESLOT_8MS 1
-#define ALX_DROP_ALG1_TIMESLOT_16MS 2
-#define ALX_DROP_ALG1_TIMESLOT_32MS 3
-#define ALX_DROP_ALG1_TIMESLOT_64MS 4
-#define ALX_DROP_ALG1_TIMESLOT_128MS 5
-#define ALX_DROP_ALG1_TIMESLOT_256MS 6
-#define ALX_DROP_ALG1_TIMESLOT_512MS 7
-
-#define ALX_DROP_ALG2 0x163C
-#define ALX_DROP_ALG2_SMPLTIME_MASK 0xFUL
-#define ALX_DROP_ALG2_SMPLTIME_SHIFT 24
-#define ALX_DROP_ALG2_LWQBW_MASK 0xFFFFFFUL
-#define ALX_DROP_ALG2_LWQBW_SHIFT 0
-
-#define ALX_SMB_TIMER 0x15C4
-
-#define ALX_TINT_TPD_THRSHLD 0x15C8
-
-#define ALX_TINT_TIMER 0x15CC
-
-#define ALX_CLK_GATE 0x1814
-#define ALX_CLK_GATE_125M_SW_DIS_CR BIT(8) /* B0 */
-#define ALX_CLK_GATE_125M_SW_AZ BIT(7) /* B0 */
-#define ALX_CLK_GATE_125M_SW_IDLE BIT(6) /* B0 */
-#define ALX_CLK_GATE_RXMAC BIT(5)
-#define ALX_CLK_GATE_TXMAC BIT(4)
-#define ALX_CLK_GATE_RXQ BIT(3)
-#define ALX_CLK_GATE_TXQ BIT(2)
-#define ALX_CLK_GATE_DMAR BIT(1)
-#define ALX_CLK_GATE_DMAW BIT(0)
-#define ALX_CLK_GATE_ALL_A0 (\
- ALX_CLK_GATE_RXMAC |\
- ALX_CLK_GATE_TXMAC |\
- ALX_CLK_GATE_RXQ |\
- ALX_CLK_GATE_TXQ |\
- ALX_CLK_GATE_DMAR |\
- ALX_CLK_GATE_DMAW)
-#define ALX_CLK_GATE_ALL_B0 (\
- ALX_CLK_GATE_ALL_A0)
-
-
-
-
-
-#define ALX_BTROM_CFG 0x1800 /* pwon rst */
-
-/* interop between drivers */
-#define ALX_DRV 0x1804
-#define ALX_DRV_PHY_AUTO BIT(28) /* 1:auto, 0:force */
-#define ALX_DRV_PHY_1000 BIT(27)
-#define ALX_DRV_PHY_100 BIT(26)
-#define ALX_DRV_PHY_10 BIT(25)
-#define ALX_DRV_PHY_DUPLEX BIT(24) /* 1:full, 0:half */
-#define ALX_DRV_PHY_PAUSE BIT(23) /* adv Pause */
-#define ALX_DRV_PHY_APAUSE BIT(22) /* adv Asym Pause */
-#define ALX_DRV_PHY_EEE BIT(21) /* 1:en AZ */
-#define ALX_DRV_PHY_MASK 0xFFUL
-#define ALX_DRV_PHY_SHIFT 21
-#define ALX_DRV_PHY_UNKNOWN 0
-#define ALX_DRV_DISABLE BIT(18)
-#define ALX_DRV_WOLS5_EN BIT(17)
-#define ALX_DRV_WOLS5_BIOS_EN BIT(16)
-#define ALX_DRV_AZ_EN BIT(12)
-#define ALX_DRV_WOLPATTERN_EN BIT(11)
-#define ALX_DRV_WOLLINKUP_EN BIT(10)
-#define ALX_DRV_WOLMAGIC_EN BIT(9)
-#define ALX_DRV_WOLCAP_BIOS_EN BIT(8)
-#define ALX_DRV_ASPM_SPD1000LMT_MASK 0x3UL
-#define ALX_DRV_ASPM_SPD1000LMT_SHIFT 4
-#define ALX_DRV_ASPM_SPD1000LMT_100M 0
-#define ALX_DRV_ASPM_SPD1000LMT_NO 1
-#define ALX_DRV_ASPM_SPD1000LMT_1M 2
-#define ALX_DRV_ASPM_SPD1000LMT_10M 3
-#define ALX_DRV_ASPM_SPD100LMT_MASK 0x3UL
-#define ALX_DRV_ASPM_SPD100LMT_SHIFT 2
-#define ALX_DRV_ASPM_SPD100LMT_1M 0
-#define ALX_DRV_ASPM_SPD100LMT_10M 1
-#define ALX_DRV_ASPM_SPD100LMT_100M 2
-#define ALX_DRV_ASPM_SPD100LMT_NO 3
-#define ALX_DRV_ASPM_SPD10LMT_MASK 0x3UL
-#define ALX_DRV_ASPM_SPD10LMT_SHIFT 0
-#define ALX_DRV_ASPM_SPD10LMT_1M 0
-#define ALX_DRV_ASPM_SPD10LMT_10M 1
-#define ALX_DRV_ASPM_SPD10LMT_100M 2
-#define ALX_DRV_ASPM_SPD10LMT_NO 3
-
-/* flag of phy inited */
-#define ALX_PHY_INITED 0x003F
-
-#define ALX_DRV_ERR1 0x1808 /* perst */
-#define ALX_DRV_ERR1_GEN BIT(31) /* geneneral err */
-#define ALX_DRV_ERR1_NOR BIT(30) /* rrd.nor */
-#define ALX_DRV_ERR1_TRUNC BIT(29)
-#define ALX_DRV_ERR1_RES BIT(28)
-#define ALX_DRV_ERR1_INTFATAL BIT(27)
-#define ALX_DRV_ERR1_TXQPEND BIT(26)
-#define ALX_DRV_ERR1_DMAW BIT(25)
-#define ALX_DRV_ERR1_DMAR BIT(24)
-#define ALX_DRV_ERR1_PCIELNKDWN BIT(23)
-#define ALX_DRV_ERR1_PKTSIZE BIT(22)
-#define ALX_DRV_ERR1_FIFOFUL BIT(21)
-#define ALX_DRV_ERR1_RFDUR BIT(20)
-#define ALX_DRV_ERR1_RRDSI BIT(19)
-#define ALX_DRV_ERR1_UPDATE BIT(18)
-
-#define ALX_DRV_ERR2 0x180C
-
-#define ALX_DBG_ADDR 0x1900 /* DWORD reg */
-#define ALX_DBG_DATA 0x1904 /* DWORD reg */
-
-#define ALX_SYNC_IPV4_SA 0x1A00
-#define ALX_SYNC_IPV4_DA 0x1A04
-
-#define ALX_SYNC_V4PORT 0x1A08
-#define ALX_SYNC_V4PORT_DST_MASK 0xFFFFUL
-#define ALX_SYNC_V4PORT_DST_SHIFT 16
-#define ALX_SYNC_V4PORT_SRC_MASK 0xFFFFUL
-#define ALX_SYNC_V4PORT_SRC_SHIFT 0
-
-#define ALX_SYNC_IPV6_SA0 0x1A0C
-#define ALX_SYNC_IPV6_SA1 0x1A10
-#define ALX_SYNC_IPV6_SA2 0x1A14
-#define ALX_SYNC_IPV6_SA3 0x1A18
-#define ALX_SYNC_IPV6_DA0 0x1A1C
-#define ALX_SYNC_IPV6_DA1 0x1A20
-#define ALX_SYNC_IPV6_DA2 0x1A24
-#define ALX_SYNC_IPV6_DA3 0x1A28
-
-#define ALX_SYNC_V6PORT 0x1A2C
-#define ALX_SYNC_V6PORT_DST_MASK 0xFFFFUL
-#define ALX_SYNC_V6PORT_DST_SHIFT 16
-#define ALX_SYNC_V6PORT_SRC_MASK 0xFFFFUL
-#define ALX_SYNC_V6PORT_SRC_SHIFT 0
-
-#define ALX_ARP_REMOTE_IPV4 0x1A30
-#define ALX_ARP_HOST_IPV4 0x1A34
-#define ALX_ARP_MAC0 0x1A38
-#define ALX_ARP_MAC1 0x1A3C
-
-#define ALX_1ST_REMOTE_IPV6_0 0x1A40
-#define ALX_1ST_REMOTE_IPV6_1 0x1A44
-#define ALX_1ST_REMOTE_IPV6_2 0x1A48
-#define ALX_1ST_REMOTE_IPV6_3 0x1A4C
-
-#define ALX_1ST_SN_IPV6_0 0x1A50
-#define ALX_1ST_SN_IPV6_1 0x1A54
-#define ALX_1ST_SN_IPV6_2 0x1A58
-#define ALX_1ST_SN_IPV6_3 0x1A5C
-
-#define ALX_1ST_TAR_IPV6_1_0 0x1A60
-#define ALX_1ST_TAR_IPV6_1_1 0x1A64
-#define ALX_1ST_TAR_IPV6_1_2 0x1A68
-#define ALX_1ST_TAR_IPV6_1_3 0x1A6C
-#define ALX_1ST_TAR_IPV6_2_0 0x1A70
-#define ALX_1ST_TAR_IPV6_2_1 0x1A74
-#define ALX_1ST_TAR_IPV6_2_2 0x1A78
-#define ALX_1ST_TAR_IPV6_2_3 0x1A7C
-
-#define ALX_2ND_REMOTE_IPV6_0 0x1A80
-#define ALX_2ND_REMOTE_IPV6_1 0x1A84
-#define ALX_2ND_REMOTE_IPV6_2 0x1A88
-#define ALX_2ND_REMOTE_IPV6_3 0x1A8C
-
-#define ALX_2ND_SN_IPV6_0 0x1A90
-#define ALX_2ND_SN_IPV6_1 0x1A94
-#define ALX_2ND_SN_IPV6_2 0x1A98
-#define ALX_2ND_SN_IPV6_3 0x1A9C
-
-#define ALX_2ND_TAR_IPV6_1_0 0x1AA0
-#define ALX_2ND_TAR_IPV6_1_1 0x1AA4
-#define ALX_2ND_TAR_IPV6_1_2 0x1AA8
-#define ALX_2ND_TAR_IPV6_1_3 0x1AAC
-#define ALX_2ND_TAR_IPV6_2_0 0x1AB0
-#define ALX_2ND_TAR_IPV6_2_1 0x1AB4
-#define ALX_2ND_TAR_IPV6_2_2 0x1AB8
-#define ALX_2ND_TAR_IPV6_2_3 0x1ABC
-
-#define ALX_1ST_NS_MAC0 0x1AC0
-#define ALX_1ST_NS_MAC1 0x1AC4
-
-#define ALX_2ND_NS_MAC0 0x1AC8
-#define ALX_2ND_NS_MAC1 0x1ACC
-
-#define ALX_PMOFLD 0x144C
-#define ALX_PMOFLD_ECMA_IGNR_FRG_SSSR BIT(11) /* B0 */
-#define ALX_PMOFLD_ARP_CNFLCT_WAKEUP BIT(10) /* B0 */
-#define ALX_PMOFLD_MULTI_SOLD BIT(9)
-#define ALX_PMOFLD_ICMP_XSUM BIT(8)
-#define ALX_PMOFLD_GARP_REPLY BIT(7)
-#define ALX_PMOFLD_SYNCV6_ANY BIT(6)
-#define ALX_PMOFLD_SYNCV4_ANY BIT(5)
-#define ALX_PMOFLD_BY_HW BIT(4)
-#define ALX_PMOFLD_NS_EN BIT(3)
-#define ALX_PMOFLD_ARP_EN BIT(2)
-#define ALX_PMOFLD_SYNCV6_EN BIT(1)
-#define ALX_PMOFLD_SYNCV4_EN BIT(0)
-
-#define ALX_RSS_KEY0 0x14B0
-#define ALX_RSS_KEY1 0x14B4
-#define ALX_RSS_KEY2 0x14B8
-#define ALX_RSS_KEY3 0x14BC
-#define ALX_RSS_KEY4 0x14C0
-#define ALX_RSS_KEY5 0x14C4
-#define ALX_RSS_KEY6 0x14C8
-#define ALX_RSS_KEY7 0x14CC
-#define ALX_RSS_KEY8 0x14D0
-#define ALX_RSS_KEY9 0x14D4
-
-#define ALX_RSS_IDT_TBL0 0x1B00
-#define ALX_RSS_IDT_TBL1 0x1B04
-#define ALX_RSS_IDT_TBL2 0x1B08
-#define ALX_RSS_IDT_TBL3 0x1B0C
-#define ALX_RSS_IDT_TBL4 0x1B10
-#define ALX_RSS_IDT_TBL5 0x1B14
-#define ALX_RSS_IDT_TBL6 0x1B18
-#define ALX_RSS_IDT_TBL7 0x1B1C
-#define ALX_RSS_IDT_TBL8 0x1B20
-#define ALX_RSS_IDT_TBL9 0x1B24
-#define ALX_RSS_IDT_TBL10 0x1B28
-#define ALX_RSS_IDT_TBL11 0x1B2C
-#define ALX_RSS_IDT_TBL12 0x1B30
-#define ALX_RSS_IDT_TBL13 0x1B34
-#define ALX_RSS_IDT_TBL14 0x1B38
-#define ALX_RSS_IDT_TBL15 0x1B3C
-#define ALX_RSS_IDT_TBL16 0x1B40
-#define ALX_RSS_IDT_TBL17 0x1B44
-#define ALX_RSS_IDT_TBL18 0x1B48
-#define ALX_RSS_IDT_TBL19 0x1B4C
-#define ALX_RSS_IDT_TBL20 0x1B50
-#define ALX_RSS_IDT_TBL21 0x1B54
-#define ALX_RSS_IDT_TBL22 0x1B58
-#define ALX_RSS_IDT_TBL23 0x1B5C
-#define ALX_RSS_IDT_TBL24 0x1B60
-#define ALX_RSS_IDT_TBL25 0x1B64
-#define ALX_RSS_IDT_TBL26 0x1B68
-#define ALX_RSS_IDT_TBL27 0x1B6C
-#define ALX_RSS_IDT_TBL28 0x1B70
-#define ALX_RSS_IDT_TBL29 0x1B74
-#define ALX_RSS_IDT_TBL30 0x1B78
-#define ALX_RSS_IDT_TBL31 0x1B7C
-
-#define ALX_RSS_HASH_VAL 0x15B0
-#define ALX_RSS_HASH_FLAG 0x15B4
-
-#define ALX_RSS_BASE_CPU_NUM 0x15B8
-
-#define ALX_MSI_MAP_TBL1 0x15D0
-#define ALX_MSI_MAP_TBL1_ALERT_MASK 0xFUL
-#define ALX_MSI_MAP_TBL1_ALERT_SHIFT 28
-#define ALX_MSI_MAP_TBL1_TIMER_MASK 0xFUL
-#define ALX_MSI_MAP_TBL1_TIMER_SHIFT 24
-#define ALX_MSI_MAP_TBL1_TXQ1_MASK 0xFUL
-#define ALX_MSI_MAP_TBL1_TXQ1_SHIFT 20
-#define ALX_MSI_MAP_TBL1_TXQ0_MASK 0xFUL
-#define ALX_MSI_MAP_TBL1_TXQ0_SHIFT 16
-#define ALX_MSI_MAP_TBL1_RXQ3_MASK 0xFUL
-#define ALX_MSI_MAP_TBL1_RXQ3_SHIFT 12
-#define ALX_MSI_MAP_TBL1_RXQ2_MASK 0xFUL
-#define ALX_MSI_MAP_TBL1_RXQ2_SHIFT 8
-#define ALX_MSI_MAP_TBL1_RXQ1_MASK 0xFUL
-#define ALX_MSI_MAP_TBL1_RXQ1_SHIFT 4
-#define ALX_MSI_MAP_TBL1_RXQ0_MASK 0xFUL
-#define ALX_MSI_MAP_TBL1_RXQ0_SHIFT 0
-
-#define ALX_MSI_MAP_TBL2 0x15D8
-#define ALX_MSI_MAP_TBL2_PHY_MASK 0xFUL
-#define ALX_MSI_MAP_TBL2_PHY_SHIFT 28
-#define ALX_MSI_MAP_TBL2_SMB_MASK 0xFUL
-#define ALX_MSI_MAP_TBL2_SMB_SHIFT 24
-#define ALX_MSI_MAP_TBL2_TXQ3_MASK 0xFUL
-#define ALX_MSI_MAP_TBL2_TXQ3_SHIFT 20
-#define ALX_MSI_MAP_TBL2_TXQ2_MASK 0xFUL
-#define ALX_MSI_MAP_TBL2_TXQ2_SHIFT 16
-#define ALX_MSI_MAP_TBL2_RXQ7_MASK 0xFUL
-#define ALX_MSI_MAP_TBL2_RXQ7_SHIFT 12
-#define ALX_MSI_MAP_TBL2_RXQ6_MASK 0xFUL
-#define ALX_MSI_MAP_TBL2_RXQ6_SHIFT 8
-#define ALX_MSI_MAP_TBL2_RXQ5_MASK 0xFUL
-#define ALX_MSI_MAP_TBL2_RXQ5_SHIFT 4
-#define ALX_MSI_MAP_TBL2_RXQ4_MASK 0xFUL
-#define ALX_MSI_MAP_TBL2_RXQ4_SHIFT 0
-
-#define ALX_MSI_ID_MAP 0x15D4
-#define ALX_MSI_ID_MAP_RXQ7 BIT(30)
-#define ALX_MSI_ID_MAP_RXQ6 BIT(29)
-#define ALX_MSI_ID_MAP_RXQ5 BIT(28)
-#define ALX_MSI_ID_MAP_RXQ4 BIT(27)
-#define ALX_MSI_ID_MAP_PCIELNKDW BIT(26) /* 0:common,1:timer */
-#define ALX_MSI_ID_MAP_PCIECERR BIT(25)
-#define ALX_MSI_ID_MAP_PCIENFERR BIT(24)
-#define ALX_MSI_ID_MAP_PCIEFERR BIT(23)
-#define ALX_MSI_ID_MAP_PCIEUR BIT(22)
-#define ALX_MSI_ID_MAP_MACTX BIT(21)
-#define ALX_MSI_ID_MAP_MACRX BIT(20)
-#define ALX_MSI_ID_MAP_RXQ3 BIT(19)
-#define ALX_MSI_ID_MAP_RXQ2 BIT(18)
-#define ALX_MSI_ID_MAP_RXQ1 BIT(17)
-#define ALX_MSI_ID_MAP_RXQ0 BIT(16)
-#define ALX_MSI_ID_MAP_TXQ0 BIT(15)
-#define ALX_MSI_ID_MAP_TXQTO BIT(14)
-#define ALX_MSI_ID_MAP_LPW BIT(13)
-#define ALX_MSI_ID_MAP_PHY BIT(12)
-#define ALX_MSI_ID_MAP_TXCREDIT BIT(11)
-#define ALX_MSI_ID_MAP_DMAW BIT(10)
-#define ALX_MSI_ID_MAP_DMAR BIT(9)
-#define ALX_MSI_ID_MAP_TXFUR BIT(8)
-#define ALX_MSI_ID_MAP_TXQ3 BIT(7)
-#define ALX_MSI_ID_MAP_TXQ2 BIT(6)
-#define ALX_MSI_ID_MAP_TXQ1 BIT(5)
-#define ALX_MSI_ID_MAP_RFDUR BIT(4)
-#define ALX_MSI_ID_MAP_RXFOV BIT(3)
-#define ALX_MSI_ID_MAP_MANU BIT(2)
-#define ALX_MSI_ID_MAP_TIMER BIT(1)
-#define ALX_MSI_ID_MAP_SMB BIT(0)
-
-#define ALX_MSI_RETRANS_TIMER 0x1920
-#define ALX_MSI_MASK_SEL_LINE BIT(16) /* 1:line,0:standard*/
-#define ALX_MSI_RETRANS_TM_MASK 0xFFFFUL
-#define ALX_MSI_RETRANS_TM_SHIFT 0
-
-#define ALX_CR_DMA_CTRL 0x1930
-#define ALX_CR_DMA_CTRL_PRI BIT(22)
-#define ALX_CR_DMA_CTRL_RRDRXD_JOINT BIT(21)
-#define ALX_CR_DMA_CTRL_BWCREDIT_MASK 0x3UL
-#define ALX_CR_DMA_CTRL_BWCREDIT_SHIFT 19
-#define ALX_CR_DMA_CTRL_BWCREDIT_2KB 0
-#define ALX_CR_DMA_CTRL_BWCREDIT_1KB 1
-#define ALX_CR_DMA_CTRL_BWCREDIT_4KB 2
-#define ALX_CR_DMA_CTRL_BWCREDIT_8KB 3
-#define ALX_CR_DMA_CTRL_BW_EN BIT(18)
-#define ALX_CR_DMA_CTRL_BW_RATIO_MASK 0x3UL
-#define ALX_CR_DMA_CTRL_BW_RATIO_1_2 0
-#define ALX_CR_DMA_CTRL_BW_RATIO_1_4 1
-#define ALX_CR_DMA_CTRL_BW_RATIO_1_8 2
-#define ALX_CR_DMA_CTRL_BW_RATIO_2_1 3
-#define ALX_CR_DMA_CTRL_SOFT_RST BIT(11)
-#define ALX_CR_DMA_CTRL_TXEARLY_EN BIT(10)
-#define ALX_CR_DMA_CTRL_RXEARLY_EN BIT(9)
-#define ALX_CR_DMA_CTRL_WEARLY_EN BIT(8)
-#define ALX_CR_DMA_CTRL_RXTH_MASK 0xFUL
-#define ALX_CR_DMA_CTRL_WTH_MASK 0xFUL
-
-
-#define ALX_EFUSE_BIST 0x1934
-#define ALX_EFUSE_BIST_COL_MASK 0x3FUL
-#define ALX_EFUSE_BIST_COL_SHIFT 24
-#define ALX_EFUSE_BIST_ROW_MASK 0x7FUL
-#define ALX_EFUSE_BIST_ROW_SHIFT 12
-#define ALX_EFUSE_BIST_STEP_MASK 0xFUL
-#define ALX_EFUSE_BIST_STEP_SHIFT 8
-#define ALX_EFUSE_BIST_PAT_MASK 0x7UL
-#define ALX_EFUSE_BIST_PAT_SHIFT 4
-#define ALX_EFUSE_BIST_CRITICAL BIT(3)
-#define ALX_EFUSE_BIST_FIXED BIT(2)
-#define ALX_EFUSE_BIST_FAIL BIT(1)
-#define ALX_EFUSE_BIST_NOW BIT(0)
-
-/* CR DMA ctrl */
-
-/* TX QoS */
-#define ALX_WRR 0x1938
-#define ALX_WRR_PRI_MASK 0x3UL
-#define ALX_WRR_PRI_SHIFT 29
-#define ALX_WRR_PRI_RESTRICT_ALL 0
-#define ALX_WRR_PRI_RESTRICT_HI 1
-#define ALX_WRR_PRI_RESTRICT_HI2 2
-#define ALX_WRR_PRI_RESTRICT_NONE 3
-#define ALX_WRR_PRI3_MASK 0x1FUL
-#define ALX_WRR_PRI3_SHIFT 24
-#define ALX_WRR_PRI2_MASK 0x1FUL
-#define ALX_WRR_PRI2_SHIFT 16
-#define ALX_WRR_PRI1_MASK 0x1FUL
-#define ALX_WRR_PRI1_SHIFT 8
-#define ALX_WRR_PRI0_MASK 0x1FUL
-#define ALX_WRR_PRI0_SHIFT 0
-
-#define ALX_HQTPD 0x193C
-#define ALX_HQTPD_BURST_EN BIT(31)
-#define ALX_HQTPD_Q3_NUMPREF_MASK 0xFUL
-#define ALX_HQTPD_Q3_NUMPREF_SHIFT 8
-#define ALX_HQTPD_Q2_NUMPREF_MASK 0xFUL
-#define ALX_HQTPD_Q2_NUMPREF_SHIFT 4
-#define ALX_HQTPD_Q1_NUMPREF_MASK 0xFUL
-#define ALX_HQTPD_Q1_NUMPREF_SHIFT 0
-
-#define ALX_CPUMAP1 0x19A0
-#define ALX_CPUMAP1_VCT7_MASK 0xFUL
-#define ALX_CPUMAP1_VCT7_SHIFT 28
-#define ALX_CPUMAP1_VCT6_MASK 0xFUL
-#define ALX_CPUMAP1_VCT6_SHIFT 24
-#define ALX_CPUMAP1_VCT5_MASK 0xFUL
-#define ALX_CPUMAP1_VCT5_SHIFT 20
-#define ALX_CPUMAP1_VCT4_MASK 0xFUL
-#define ALX_CPUMAP1_VCT4_SHIFT 16
-#define ALX_CPUMAP1_VCT3_MASK 0xFUL
-#define ALX_CPUMAP1_VCT3_SHIFT 12
-#define ALX_CPUMAP1_VCT2_MASK 0xFUL
-#define ALX_CPUMAP1_VCT2_SHIFT 8
-#define ALX_CPUMAP1_VCT1_MASK 0xFUL
-#define ALX_CPUMAP1_VCT1_SHIFT 4
-#define ALX_CPUMAP1_VCT0_MASK 0xFUL
-#define ALX_CPUMAP1_VCT0_SHIFT 0
-
-#define ALX_CPUMAP2 0x19A4
-#define ALX_CPUMAP2_VCT15_MASK 0xFUL
-#define ALX_CPUMAP2_VCT15_SHIFT 28
-#define ALX_CPUMAP2_VCT14_MASK 0xFUL
-#define ALX_CPUMAP2_VCT14_SHIFT 24
-#define ALX_CPUMAP2_VCT13_MASK 0xFUL
-#define ALX_CPUMAP2_VCT13_SHIFT 20
-#define ALX_CPUMAP2_VCT12_MASK 0xFUL
-#define ALX_CPUMAP2_VCT12_SHIFT 16
-#define ALX_CPUMAP2_VCT11_MASK 0xFUL
-#define ALX_CPUMAP2_VCT11_SHIFT 12
-#define ALX_CPUMAP2_VCT10_MASK 0xFUL
-#define ALX_CPUMAP2_VCT10_SHIFT 8
-#define ALX_CPUMAP2_VCT9_MASK 0xFUL
-#define ALX_CPUMAP2_VCT9_SHIFT 4
-#define ALX_CPUMAP2_VCT8_MASK 0xFUL
-#define ALX_CPUMAP2_VCT8_SHIFT 0
-
-#define ALX_MISC 0x19C0
-#define ALX_MISC_MODU BIT(31) /* 0:vector,1:cpu */
-#define ALX_MISC_OVERCUR BIT(29)
-#define ALX_MISC_PSWR_EN BIT(28)
-#define ALX_MISC_PSW_CTRL_MASK 0xFUL
-#define ALX_MISC_PSW_CTRL_SHIFT 24
-#define ALX_MISC_PSW_OCP_MASK 0x7UL
-#define ALX_MISC_PSW_OCP_SHIFT 21
-#define ALX_MISC_PSW_OCP_DEF 0x7
-#define ALX_MISC_V18_HIGH BIT(20)
-#define ALX_MISC_LPO_CTRL_MASK 0xFUL
-#define ALX_MISC_LPO_CTRL_SHIFT 16
-#define ALX_MISC_ISO_EN BIT(12)
-#define ALX_MISC_XSTANA_ALWAYS_ON BIT(11)
-#define ALX_MISC_SYS25M_SEL_ADAPTIVE BIT(10)
-#define ALX_MISC_SPEED_SIM BIT(9)
-#define ALX_MISC_S1_LWP_EN BIT(8)
-#define ALX_MISC_MACLPW BIT(7) /* pcie/mac do pwsaving
- * as phy in lpw state
- */
-#define ALX_MISC_125M_SW BIT(6)
-#define ALX_MISC_INTNLOSC_OFF_EN BIT(5)
-#define ALX_MISC_EXTN25M_SEL BIT(4) /* 0:chipset,1:cystle */
-#define ALX_MISC_INTNLOSC_OPEN BIT(3)
-#define ALX_MISC_SMBUS_AT_LED BIT(2)
-#define ALX_MISC_PPS_AT_LED_MASK 0x3UL
-#define ALX_MISC_PPS_AT_LED_SHIFT 0
-#define ALX_MISC_PPS_AT_LED_ACT 1
-#define ALX_MISC_PPS_AT_LED_10_100 2
-#define ALX_MISC_PPS_AT_LED_1000 3
-
-#define ALX_MISC1 0x19C4
-#define ALX_MSC1_BLK_CRASPM_REQ BIT(15)
-
-#define ALX_MSIC2 0x19C8
-#define ALX_MSIC2_CALB_START BIT(0)
-
-#define ALX_MISC3 0x19CC
-#define ALX_MISC3_25M_BY_SW BIT(1) /* 1:Software control 25M */
-#define ALX_MISC3_25M_NOTO_INTNL BIT(0) /* 0:25M switch to intnl OSC */
-
-#define ALX_MSIX_ENTRY_BASE 0x2000 /* MSIX tbl in memory space */
-
-/***************************** IO mapping registers ***************************/
-#define ALX_IO_ADDR 0x00 /* DWORD reg */
-#define ALX_IO_DATA 0x04 /* DWORD reg */
-#define ALX_IO_MASTER 0x08 /* DWORD same as reg0x1400 */
-#define ALX_IO_MAC_CTRL 0x0C /* DWORD same as reg0x1480*/
-#define ALX_IO_ISR 0x10 /* DWORD same as reg0x1600 */
-#define ALX_IO_IMR 0x14 /* DWORD same as reg0x1604 */
-#define ALX_IO_TPD_PRI1_PIDX 0x18 /* WORD same as reg0x15F0 */
-#define ALX_IO_TPD_PRI0_PIDX 0x1A /* WORD same as reg0x15F2 */
-#define ALX_IO_TPD_PRI1_CIDX 0x1C /* WORD same as reg0x15F4 */
-#define ALX_IO_TPD_PRI0_CIDX 0x1E /* WORD same as reg0x15F6 */
-#define ALX_IO_RFD_PIDX 0x20 /* WORD same as reg0x15E0 */
-#define ALX_IO_RFD_CIDX 0x30 /* WORD same as reg0x15F8 */
-#define ALX_IO_MDIO 0x38 /* WORD same as reg0x1414 */
-#define ALX_IO_PHY_CTRL 0x3C /* DWORD same as reg0x140C */
-
-
-/********************* PHY regs definition ***************************/
-
-/* Autoneg Advertisement Register */
-#define ALX_ADVERTISE_SPEED_MASK 0x01E0
-#define ALX_ADVERTISE_DEFAULT_CAP 0x1DE0 /* diff with L1C */
-
-/* 1000BASE-T Control Register (0x9) */
-#define ALX_GIGA_CR_1000T_HD_CAPS 0x0100
-#define ALX_GIGA_CR_1000T_FD_CAPS 0x0200
-#define ALX_GIGA_CR_1000T_REPEATER_DTE 0x0400
-
-#define ALX_GIGA_CR_1000T_MS_VALUE 0x0800
-
-#define ALX_GIGA_CR_1000T_MS_ENABLE 0x1000
-
-#define ALX_GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000
-#define ALX_GIGA_CR_1000T_TEST_MODE_1 0x2000
-#define ALX_GIGA_CR_1000T_TEST_MODE_2 0x4000
-#define ALX_GIGA_CR_1000T_TEST_MODE_3 0x6000
-#define ALX_GIGA_CR_1000T_TEST_MODE_4 0x8000
-#define ALX_GIGA_CR_1000T_SPEED_MASK 0x0300
-#define ALX_GIGA_CR_1000T_DEFAULT_CAP 0x0300
-
-/* 1000BASE-T Status Register */
-#define ALX_MII_GIGA_SR 0x0A
-
-/* PHY Specific Status Register */
-#define ALX_MII_GIGA_PSSR 0x11
-#define ALX_GIGA_PSSR_FC_RXEN 0x0004
-#define ALX_GIGA_PSSR_FC_TXEN 0x0008
-#define ALX_GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800
-#define ALX_GIGA_PSSR_DPLX 0x2000
-#define ALX_GIGA_PSSR_SPEED 0xC000
-#define ALX_GIGA_PSSR_10MBS 0x0000
-#define ALX_GIGA_PSSR_100MBS 0x4000
-#define ALX_GIGA_PSSR_1000MBS 0x8000
-
-/* PHY Interrupt Enable Register */
-#define ALX_MII_IER 0x12
-#define ALX_IER_LINK_UP 0x0400
-#define ALX_IER_LINK_DOWN 0x0800
-
-/* PHY Interrupt Status Register */
-#define ALX_MII_ISR 0x13
-#define ALX_ISR_LINK_UP 0x0400
-#define ALX_ISR_LINK_DOWN 0x0800
-
-/* Cable-Detect-Test Control Register */
-#define ALX_MII_CDTC 0x16
-#define ALX_CDTC_EN 1 /* sc */
-#define ALX_CDTC_PAIR_MASK 0x3U
-#define ALX_CDTC_PAIR_SHIFT 8
-
-
-/* Cable-Detect-Test Status Register */
-#define ALX_MII_CDTS 0x1C
-#define ALX_CDTS_STATUS_MASK 0x3U
-#define ALX_CDTS_STATUS_SHIFT 8
-#define ALX_CDTS_STATUS_NORMAL 0
-#define ALX_CDTS_STATUS_SHORT 1
-#define ALX_CDTS_STATUS_OPEN 2
-#define ALX_CDTS_STATUS_INVALID 3
-
-#define ALX_MII_DBG_ADDR 0x1D
-#define ALX_MII_DBG_DATA 0x1E
-
-/***************************** debug port *************************************/
-
-#define ALX_MIIDBG_ANACTRL 0x00
-#define ALX_ANACTRL_CLK125M_DELAY_EN 0x8000
-#define ALX_ANACTRL_VCO_FAST 0x4000
-#define ALX_ANACTRL_VCO_SLOW 0x2000
-#define ALX_ANACTRL_AFE_MODE_EN 0x1000
-#define ALX_ANACTRL_LCKDET_PHY 0x0800
-#define ALX_ANACTRL_LCKDET_EN 0x0400
-#define ALX_ANACTRL_OEN_125M 0x0200
-#define ALX_ANACTRL_HBIAS_EN 0x0100
-#define ALX_ANACTRL_HB_EN 0x0080
-#define ALX_ANACTRL_SEL_HSP 0x0040
-#define ALX_ANACTRL_CLASSA_EN 0x0020
-#define ALX_ANACTRL_MANUSWON_SWR_MASK 0x3U
-#define ALX_ANACTRL_MANUSWON_SWR_SHIFT 2
-#define ALX_ANACTRL_MANUSWON_SWR_2V 0
-#define ALX_ANACTRL_MANUSWON_SWR_1P9V 1
-#define ALX_ANACTRL_MANUSWON_SWR_1P8V 2
-#define ALX_ANACTRL_MANUSWON_SWR_1P7V 3
-#define ALX_ANACTRL_MANUSWON_BW3_4M 0x0002
-#define ALX_ANACTRL_RESTART_CAL 0x0001
-#define ALX_ANACTRL_DEF 0x02EF
-
-
-#define ALX_MIIDBG_SYSMODCTRL 0x04
-#define ALX_SYSMODCTRL_IECHOADJ_PFMH_PHY 0x8000
-#define ALX_SYSMODCTRL_IECHOADJ_BIASGEN 0x4000
-#define ALX_SYSMODCTRL_IECHOADJ_PFML_PHY 0x2000
-#define ALX_SYSMODCTRL_IECHOADJ_PS_MASK 0x3U
-#define ALX_SYSMODCTRL_IECHOADJ_PS_SHIFT 10
-#define ALX_SYSMODCTRL_IECHOADJ_PS_40 3
-#define ALX_SYSMODCTRL_IECHOADJ_PS_20 2
-#define ALX_SYSMODCTRL_IECHOADJ_PS_0 1
-#define ALX_SYSMODCTRL_IECHOADJ_10BT_100MV 0x0040 /* 1:100mv, 0:200mv */
-#define ALX_SYSMODCTRL_IECHOADJ_HLFAP_MASK 0x3U
-#define ALX_SYSMODCTRL_IECHOADJ_HLFAP_SHIFT 4
-#define ALX_SYSMODCTRL_IECHOADJ_VDFULBW 0x0008
-#define ALX_SYSMODCTRL_IECHOADJ_VDBIASHLF 0x0004
-#define ALX_SYSMODCTRL_IECHOADJ_VDAMPHLF 0x0002
-#define ALX_SYSMODCTRL_IECHOADJ_VDLANSW 0x0001
-#define ALX_SYSMODCTRL_IECHOADJ_DEF 0xBB8B /* en half bias */
-
-
-#define ALX_MIIDBG_SRDSYSMOD 0x05
-#define ALX_SRDSYSMOD_LCKDET_EN 0x2000
-#define ALX_SRDSYSMOD_PLL_EN 0x0800
-#define ALX_SRDSYSMOD_SEL_HSP 0x0400
-#define ALX_SRDSYSMOD_HLFTXDR 0x0200
-#define ALX_SRDSYSMOD_TXCLK_DELAY_EN 0x0100
-#define ALX_SRDSYSMOD_TXELECIDLE 0x0080
-#define ALX_SRDSYSMOD_DEEMP_EN 0x0040
-#define ALX_SRDSYSMOD_MS_PAD 0x0004
-#define ALX_SRDSYSMOD_CDR_ADC_VLTG 0x0002
-#define ALX_SRDSYSMOD_CDR_DAC_1MA 0x0001
-#define ALX_SRDSYSMOD_DEF 0x2C46
-
-
-#define ALX_MIIDBG_HIBNEG 0x0B
-#define ALX_HIBNEG_PSHIB_EN 0x8000
-#define ALX_HIBNEG_WAKE_BOTH 0x4000
-#define ALX_HIBNEG_ONOFF_ANACHG_SUDEN 0x2000
-#define ALX_HIBNEG_HIB_PULSE 0x1000
-#define ALX_HIBNEG_GATE_25M_EN 0x0800
-#define ALX_HIBNEG_RST_80U 0x0400
-#define ALX_HIBNEG_RST_TIMER_MASK 0x3U
-#define ALX_HIBNEG_RST_TIMER_SHIFT 8
-#define ALX_HIBNEG_GTX_CLK_DELAY_MASK 0x3U
-#define ALX_HIBNEG_GTX_CLK_DELAY_SHIFT 5
-#define ALX_HIBNEG_BYPSS_BRKTIMER 0x0010
-#define ALX_HIBNEG_DEF 0xBC40
-#define ALX_HIBNEG_NOHIB (\
-ALX_HIBNEG_DEF & ~(ALX_HIBNEG_PSHIB_EN | ALX_HIBNEG_HIB_PULSE))
-
-#define ALX_MIIDBG_TST10BTCFG 0x12
-#define ALX_TST10BTCFG_INTV_TIMER_MASK 0x3U
-#define ALX_TST10BTCFG_INTV_TIMER_SHIFT 14
-#define ALX_TST10BTCFG_TRIGER_TIMER_MASK 0x3U
-#define ALX_TST10BTCFG_TRIGER_TIMER_SHIFT 12
-#define ALX_TST10BTCFG_DIV_MAN_MLT3_EN 0x0800
-#define ALX_TST10BTCFG_OFF_DAC_IDLE 0x0400
-#define ALX_TST10BTCFG_LPBK_DEEP 0x0004 /* 1:deep,0:shallow */
-#define ALX_TST10BTCFG_DEF 0x4C04
-
-#define ALX_MIIDBG_AZ_ANADECT 0x15
-#define ALX_AZ_ANADECT_10BTRX_TH 0x8000
-#define ALX_AZ_ANADECT_BOTH_01CHNL 0x4000
-#define ALX_AZ_ANADECT_INTV_MASK 0x3FU
-#define ALX_AZ_ANADECT_INTV_SHIFT 8
-#define ALX_AZ_ANADECT_THRESH_MASK 0xFU
-#define ALX_AZ_ANADECT_THRESH_SHIFT 4
-#define ALX_AZ_ANADECT_CHNL_MASK 0xFU
-#define ALX_AZ_ANADECT_CHNL_SHIFT 0
-#define ALX_AZ_ANADECT_DEF 0x3220
-#define ALX_AZ_ANADECT_LONG 0x3210
-
-#define ALX_MIIDBG_MSE16DB 0x18
-#define ALX_MSE16DB_UP 0x05EA
-#define ALX_MSE16DB_DOWN 0x02EA
-
-#define ALX_MIIDBG_MSE20DB 0x1C
-#define ALX_MSE20DB_TH_MASK 0x7F
-#define ALX_MSE20DB_TH_SHIFT 2
-#define ALX_MSE20DB_TH_DEF 0x2E
-#define ALX_MSE20DB_TH_HI 0x54
-
-#define ALX_MIIDBG_AGC 0x23
-#define ALX_AGC_2_VGA_MASK 0x3FU
-#define ALX_AGC_2_VGA_SHIFT 8
-#define ALX_AGC_LONG1G_LIMT 40
-#define ALX_AGC_LONG100M_LIMT 44
-
-#define ALX_MIIDBG_LEGCYPS 0x29
-#define ALX_LEGCYPS_EN 0x8000
-#define ALX_LEGCYPS_DAC_AMP1000_MASK 0x7U
-#define ALX_LEGCYPS_DAC_AMP1000_SHIFT 12
-#define ALX_LEGCYPS_DAC_AMP100_MASK 0x7U
-#define ALX_LEGCYPS_DAC_AMP100_SHIFT 9
-#define ALX_LEGCYPS_DAC_AMP10_MASK 0x7U
-#define ALX_LEGCYPS_DAC_AMP10_SHIFT 6
-#define ALX_LEGCYPS_UNPLUG_TIMER_MASK 0x7U
-#define ALX_LEGCYPS_UNPLUG_TIMER_SHIFT 3
-#define ALX_LEGCYPS_UNPLUG_DECT_EN 0x0004
-#define ALX_LEGCYPS_ECNC_PS_EN 0x0001
-#define ALX_LEGCYPS_DEF 0x129D
-
-#define ALX_MIIDBG_TST100BTCFG 0x36
-#define ALX_TST100BTCFG_NORMAL_BW_EN 0x8000
-#define ALX_TST100BTCFG_BADLNK_BYPASS 0x4000
-#define ALX_TST100BTCFG_SHORTCABL_TH_MASK 0x3FU
-#define ALX_TST100BTCFG_SHORTCABL_TH_SHIFT 8
-#define ALX_TST100BTCFG_LITCH_EN 0x0080
-#define ALX_TST100BTCFG_VLT_SW 0x0040
-#define ALX_TST100BTCFG_LONGCABL_TH_MASK 0x3FU
-#define ALX_TST100BTCFG_LONGCABL_TH_SHIFT 0
-#define ALX_TST100BTCFG_DEF 0xE12C
-
-#define ALX_MIIDBG_GREENCFG 0x3B
-#define ALX_GREENCFG_MSTPS_MSETH2_MASK 0xFFU
-#define ALX_GREENCFG_MSTPS_MSETH2_SHIFT 8
-#define ALX_GREENCFG_MSTPS_MSETH1_MASK 0xFFU
-#define ALX_GREENCFG_MSTPS_MSETH1_SHIFT 0
-#define ALX_GREENCFG_DEF 0x7078
-
-#define ALX_MIIDBG_GREENCFG2 0x3D
-#define ALX_GREENCFG2_BP_GREEN 0x8000
-#define ALX_GREENCFG2_GATE_DFSE_EN 0x0080
-
-
-/***************************** extension **************************************/
-
-/******* dev 3 *********/
-#define ALX_MIIEXT_PCS 3
-
-#define ALX_MIIEXT_CLDCTRL3 0x8003
-#define ALX_CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000
-#define ALX_CLDCTRL3_AZ_DISAMP 0x1000
-
-#define ALX_MIIEXT_CLDCTRL5 0x8005
-#define ALX_CLDCTRL5_BP_VD_HLFBIAS 0x4000
-
-#define ALX_MIIEXT_CLDCTRL6 0x8006
-#define ALX_CLDCTRL6_CAB_LEN_MASK 0xFFU
-#define ALX_CLDCTRL6_CAB_LEN_SHIFT 0
-#define ALX_CLDCTRL6_CAB_LEN_SHORT1G 116
-#define ALX_CLDCTRL6_CAB_LEN_SHORT100M 152
-
-#define ALX_MIIEXT_CLDCTRL7 0x8007
-#define ALX_CLDCTRL7_VDHLF_BIAS_TH_MASK 0x7FU
-#define ALX_CLDCTRL7_VDHLF_BIAS_TH_SHIFT 9
-#define ALX_CLDCTRL7_AFE_AZ_MASK 0x1FU
-#define ALX_CLDCTRL7_AFE_AZ_SHIFT 4
-#define ALX_CLDCTRL7_SIDE_PEAK_TH_MASK 0xFU
-#define ALX_CLDCTRL7_SIDE_PEAK_TH_SHIFT 0
-#define ALX_CLDCTRL7_DEF 0x6BF6
-
-#define ALX_MIIEXT_AZCTRL 0x8008
-#define ALX_AZCTRL_SHORT_TH_MASK 0xFFU
-#define ALX_AZCTRL_SHORT_TH_SHIFT 8
-#define ALX_AZCTRL_LONG_TH_MASK 0xFFU
-#define ALX_AZCTRL_LONG_TH_SHIFT 0
-#define ALX_AZCTRL_DEF 0x1629
-
-#define ALX_MIIEXT_AZCTRL2 0x8009
-#define ALX_AZCTRL2_WAKETRNING_MASK 0xFFU
-#define ALX_AZCTRL2_WAKETRNING_SHIFT 8
-#define ALX_AZCTRL2_QUIET_TIMER_MASK 0x3U
-#define ALX_AZCTRL2_QUIET_TIMER_SHIFT 6
-#define ALX_AZCTRL2_PHAS_JMP2 0x0010
-#define ALX_AZCTRL2_CLKTRCV_125MD16 0x0008
-#define ALX_AZCTRL2_GATE1000_EN 0x0004
-#define ALX_AZCTRL2_AVRG_FREQ 0x0002
-#define ALX_AZCTRL2_PHAS_JMP4 0x0001
-#define ALX_AZCTRL2_DEF 0x32C0
-
-#define ALX_MIIEXT_AZCTRL6 0x800D
-
-#define ALX_MIIEXT_VDRVBIAS 0x8062
-#define ALX_VDRVBIAS_SEL_MASK 0x3U
-#define ALX_VDRVBIAS_SEL_SHIFT 0
-#define ALX_VDRVBIAS_DEF 0x3
-
-/********* dev 7 **********/
-#define ALX_MIIEXT_ANEG 7
-
-#define ALX_MIIEXT_LOCAL_EEEADV 0x3C
-#define ALX_LOCAL_EEEADV_1000BT 0x0004
-#define ALX_LOCAL_EEEADV_100BT 0x0002
-
-#define ALX_MIIEXT_REMOTE_EEEADV 0x3D
-#define ALX_REMOTE_EEEADV_1000BT 0x0004
-#define ALX_REMOTE_EEEADV_100BT 0x0002
-
-#define ALX_MIIEXT_EEE_ANEG 0x8000
-#define ALX_EEE_ANEG_1000M 0x0004
-#define ALX_EEE_ANEG_100M 0x0002
-
-#define ALX_MIIEXT_AFE 0x801A
-#define ALX_AFE_10BT_100M_TH 0x0040
-
-#define ALX_MIIEXT_S3DIG10 0x8023
-#define ALX_MIIEXT_S3DIG10_SL 0x0001 /* 1=bypass 10BT rx fifo */
-#define ALX_MIIEXT_S3DIG10_DEF 0 /* 0= original 10BT rx */
-
-#define ALX_MIIEXT_NLP34 0x8025
-#define ALX_MIIEXT_NLP34_DEF 0x1010 /* for 160m */
-
-#define ALX_MIIEXT_NLP56 0x8026
-#define ALX_MIIEXT_NLP56_DEF 0x1010 /* for 160m */
-
-#define ALX_MIIEXT_NLP78 0x8027
-#define ALX_MIIEXT_NLP78_160M_DEF 0x8D05 /* for 160m */
-#define ALX_MIIEXT_NLP78_120M_DEF 0x8A05 /* for 120m */
+struct tpd_desc {
+ __le32 word0;
+ __le32 word1;
+ union {
+ __le64 addr;
+ struct {
+ __le32 pkt_len;
+ __le32 resvd;
+ } l;
+ } adrl;
+} __packed;
+
+/* tpd word 0 */
+#define TPD_BUFLEN_MASK 0xFFFF
+#define TPD_BUFLEN_SHIFT 0
+#define TPD_VLTAG_MASK 0xFFFF
+#define TPD_VLTAG_SHIFT 16
+
+/* tpd word 1 */
+#define TPD_CXSUMSTART_MASK 0x00FF
+#define TPD_CXSUMSTART_SHIFT 0
+#define TPD_L4HDROFFSET_MASK 0x00FF
+#define TPD_L4HDROFFSET_SHIFT 0
+#define TPD_CXSUM_EN_MASK 0x0001
+#define TPD_CXSUM_EN_SHIFT 8
+#define TPD_IP_XSUM_MASK 0x0001
+#define TPD_IP_XSUM_SHIFT 9
+#define TPD_TCP_XSUM_MASK 0x0001
+#define TPD_TCP_XSUM_SHIFT 10
+#define TPD_UDP_XSUM_MASK 0x0001
+#define TPD_UDP_XSUm_SHIFT 11
+#define TPD_LSO_EN_MASK 0x0001
+#define TPD_LSO_EN_SHIFT 12
+#define TPD_LSO_V2_MASK 0x0001
+#define TPD_LSO_V2_SHIFT 13
+#define TPD_VLTAGGED_MASK 0x0001
+#define TPD_VLTAGGED_SHIFT 14
+#define TPD_INS_VLTAG_MASK 0x0001
+#define TPD_INS_VLTAG_SHIFT 15
+#define TPD_IPV4_MASK 0x0001
+#define TPD_IPV4_SHIFT 16
+#define TPD_ETHTYPE_MASK 0x0001
+#define TPD_ETHTYPE_SHIFT 17
+#define TPD_CXSUMOFFSET_MASK 0x00FF
+#define TPD_CXSUMOFFSET_SHIFT 18
+#define TPD_MSS_MASK 0x1FFF
+#define TPD_MSS_SHIFT 18
+#define TPD_EOP_MASK 0x0001
+#define TPD_EOP_SHIFT 31
+
+#define DESC_GET(_x, _name) ((_x) >> _name##SHIFT & _name##MASK)
+
+/* Receive Free Descriptor */
+struct rfd_desc {
+ __le64 addr; /* data buffer address, length is
+ * declared in register --- every
+ * buffer has the same size
+ */
+} __packed;
+
+/* Receive Return Descriptor, contains 4 32-bit words.
+ *
+ * 31 16 0
+ * +----------------+----------------+
+ * | Word 0 |
+ * +----------------+----------------+
+ * | Word 1: RSS Hash value |
+ * +----------------+----------------+
+ * | Word 2 |
+ * +----------------+----------------+
+ * | Word 3 |
+ * +----------------+----------------+
+ *
+ * Word 0 depiction & Word 2 depiction:
+ *
+ * 0--+ 0--+
+ * 1 | 1 |
+ * 2 | 2 |
+ * 3 | 3 |
+ * 4 | 4 |
+ * 5 | 5 |
+ * 6 | 6 |
+ * 7 | IP payload checksum 7 | VLAN tag
+ * 8 | (15:0) 8 | (15:0)
+ * 9 | 9 |
+ * 10 | 10 |
+ * 11 | 11 |
+ * 12 | 12 |
+ * 13 | 13 |
+ * 14 | 14 |
+ * 15-+ 15-+
+ * 16-+ 16-+
+ * 17 | Number of RFDs 17 |
+ * 18 | (19:16) 18 |
+ * 19-+ 19 | Protocol ID
+ * 20-+ 20 | (23:16)
+ * 21 | 21 |
+ * 22 | 22 |
+ * 23 | 23-+
+ * 24 | 24 | Reserved
+ * 25 | Start index of RFD-ring 25-+
+ * 26 | (31:20) 26 | RSS Q-num (27:25)
+ * 27 | 27-+
+ * 28 | 28-+
+ * 29 | 29 | RSS Hash algorithm
+ * 30 | 30 | (31:28)
+ * 31-+ 31-+
+ *
+ * Word 3 depiction:
+ *
+ * 0--+
+ * 1 |
+ * 2 |
+ * 3 |
+ * 4 |
+ * 5 |
+ * 6 |
+ * 7 | Packet length (include FCS)
+ * 8 | (13:0)
+ * 9 |
+ * 10 |
+ * 11 |
+ * 12 |
+ * 13-+
+ * 14 L4 Header checksum error
+ * 15 IPv4 checksum error
+ * 16 VLAN tagged
+ * 17-+
+ * 18 | Protocol ID (19:17)
+ * 19-+
+ * 20 Receive error summary
+ * 21 FCS(CRC) error
+ * 22 Frame alignment error
+ * 23 Truncated packet
+ * 24 Runt packet
+ * 25 Incomplete packet due to insufficient rx-desc
+ * 26 Broadcast packet
+ * 27 Multicast packet
+ * 28 Ethernet type (EII or 802.3)
+ * 29 FIFO overflow
+ * 30 Length error (for 802.3, length field mismatch with actual len)
+ * 31 Updated, indicate to driver that this RRD is refreshed.
+ */
-/******************************************************************************/
-/* HW. related setting used by SW. */
+struct rrd_desc {
+ __le32 word0;
+ __le32 rss_hash;
+ __le32 word2;
+ __le32 word3;
+} __packed;
+
+/* rrd word 0 */
+#define RRD_XSUM_MASK 0xFFFF
+#define RRD_XSUM_SHIFT 0
+#define RRD_NOR_MASK 0x000F
+#define RRD_NOR_SHIFT 16
+#define RRD_SI_MASK 0x0FFF
+#define RRD_SI_SHIFT 20
+
+/* rrd word 2 */
+#define RRD_VLTAG_MASK 0xFFFF
+#define RRD_VLTAG_SHIFT 0
+#define RRD_PID_MASK 0x00FF
+#define RRD_PID_SHIFT 16
+/* non-ip packet */
+#define RRD_PID_NONIP 0
+/* ipv4(only) */
+#define RRD_PID_IPV4 1
+/* tcp/ipv6 */
+#define RRD_PID_IPV6TCP 2
+/* tcp/ipv4 */
+#define RRD_PID_IPV4TCP 3
+/* udp/ipv6 */
+#define RRD_PID_IPV6UDP 4
+/* udp/ipv4 */
+#define RRD_PID_IPV4UDP 5
+/* ipv6(only) */
+#define RRD_PID_IPV6 6
+/* LLDP packet */
+#define RRD_PID_LLDP 7
+/* 1588 packet */
+#define RRD_PID_1588 8
+#define RRD_RSSQ_MASK 0x0007
+#define RRD_RSSQ_SHIFT 25
+#define RRD_RSSALG_MASK 0x000F
+#define RRD_RSSALG_SHIFT 28
+#define RRD_RSSALG_TCPV6 0x1
+#define RRD_RSSALG_IPV6 0x2
+#define RRD_RSSALG_TCPV4 0x4
+#define RRD_RSSALG_IPV4 0x8
+
+/* rrd word 3 */
+#define RRD_PKTLEN_MASK 0x3FFF
+#define RRD_PKTLEN_SHIFT 0
+#define RRD_ERR_L4_MASK 0x0001
+#define RRD_ERR_L4_SHIFT 14
+#define RRD_ERR_IPV4_MASK 0x0001
+#define RRD_ERR_IPV4_SHIFT 15
+#define RRD_VLTAGGED_MASK 0x0001
+#define RRD_VLTAGGED_SHIFT 16
+#define RRD_OLD_PID_MASK 0x0007
+#define RRD_OLD_PID_SHIFT 17
+#define RRD_ERR_RES_MASK 0x0001
+#define RRD_ERR_RES_SHIFT 20
+#define RRD_ERR_FCS_MASK 0x0001
+#define RRD_ERR_FCS_SHIFT 21
+#define RRD_ERR_FAE_MASK 0x0001
+#define RRD_ERR_FAE_SHIFT 22
+#define RRD_ERR_TRUNC_MASK 0x0001
+#define RRD_ERR_TRUNC_SHIFT 23
+#define RRD_ERR_RUNT_MASK 0x0001
+#define RRD_ERR_RUNT_SHIFT 24
+#define RRD_ERR_ICMP_MASK 0x0001
+#define RRD_ERR_ICMP_SHIFT 25
+#define RRD_BCAST_MASK 0x0001
+#define RRD_BCAST_SHIFT 26
+#define RRD_MCAST_MASK 0x0001
+#define RRD_MCAST_SHIFT 27
+#define RRD_ETHTYPE_MASK 0x0001
+#define RRD_ETHTYPE_SHIFT 28
+#define RRD_ERR_FIFOV_MASK 0x0001
+#define RRD_ERR_FIFOV_SHIFT 29
+#define RRD_ERR_LEN_MASK 0x0001
+#define RRD_ERR_LEN_SHIFT 30
+#define RRD_UPDATED_MASK 0x0001
+#define RRD_UPDATED_SHIFT 31
+
+
+/* Statistics counters collected by the MAC */
+struct alx_hw_stats {
+ /* rx */
+ unsigned long rx_ok;
+ unsigned long rx_bcast;
+ unsigned long rx_mcast;
+ unsigned long rx_pause;
+ unsigned long rx_ctrl;
+ unsigned long rx_fcs_err;
+ unsigned long rx_len_err;
+ unsigned long rx_byte_cnt;
+ unsigned long rx_runt;
+ unsigned long rx_frag;
+ unsigned long rx_sz_64B;
+ unsigned long rx_sz_127B;
+ unsigned long rx_sz_255B;
+ unsigned long rx_sz_511B;
+ unsigned long rx_sz_1023B;
+ unsigned long rx_sz_1518B;
+ unsigned long rx_sz_max;
+ unsigned long rx_ov_sz;
+ unsigned long rx_ov_rxf;
+ unsigned long rx_ov_rrd;
+ unsigned long rx_align_err;
+ unsigned long rx_bc_byte_cnt;
+ unsigned long rx_mc_byte_cnt;
+ unsigned long rx_err_addr;
+
+ /* tx */
+ unsigned long tx_ok;
+ unsigned long tx_bcast;
+ unsigned long tx_mcast;
+ unsigned long tx_pause;
+ unsigned long tx_exc_defer;
+ unsigned long tx_ctrl;
+ unsigned long tx_defer;
+ unsigned long tx_byte_cnt;
+ unsigned long tx_sz_64B;
+ unsigned long tx_sz_127B;
+ unsigned long tx_sz_255B;
+ unsigned long tx_sz_511B;
+ unsigned long tx_sz_1023B;
+ unsigned long tx_sz_1518B;
+ unsigned long tx_sz_max;
+ unsigned long tx_single_col;
+ unsigned long tx_multi_col;
+ unsigned long tx_late_col;
+ unsigned long tx_abort_col;
+ unsigned long tx_underrun;
+ unsigned long tx_trd_eop;
+ unsigned long tx_len_err;
+ unsigned long tx_trunc;
+ unsigned long tx_bc_byte_cnt;
+ unsigned long tx_mc_byte_cnt;
+ unsigned long update;
+};
+
+#define SPEED_0 0
+#define HALF_DUPLEX 1
+#define FULL_DUPLEX 2
+#define ALX_MAX_SETUP_LNK_CYCLE 50
+
+#define ALX_SPEED_TO_ETHADV(_speed) (\
+(_speed) == SPEED_1000 + FULL_DUPLEX ? ADVERTISED_1000baseT_Full : \
+(_speed) == SPEED_100 + FULL_DUPLEX ? ADVERTISED_100baseT_Full : \
+(_speed) == SPEED_100 + HALF_DUPLEX ? ADVERTISED_10baseT_Half : \
+(_speed) == SPEED_10 + FULL_DUPLEX ? ADVERTISED_10baseT_Full : \
+(_speed) == SPEED_10 + HALF_DUPLEX ? ADVERTISED_10baseT_Half : \
+0)
/* for FlowControl */
#define ALX_FC_RX 0x01
@@ -2116,9 +388,9 @@ ALX_HIBNEG_DEF & ~(ALX_HIBNEG_PSHIB_EN | ALX_HIBNEG_HIB_PULSE))
#define ALX_FC_ANEG 0x04
/* for sleep control */
-#define ALX_SLEEP_WOL_PHY 0x00000001 /* WoL / PHY Status Change */
-#define ALX_SLEEP_WOL_MAGIC 0x00000002 /* WoL/ Magic Packet */
-#define ALX_SLEEP_CIFS 0x00000004 /* CIFS active */
+#define ALX_SLEEP_WOL_PHY 0x00000001
+#define ALX_SLEEP_WOL_MAGIC 0x00000002
+#define ALX_SLEEP_CIFS 0x00000004
#define ALX_SLEEP_ACTIVE (\
ALX_SLEEP_WOL_PHY | \
ALX_SLEEP_WOL_MAGIC | \
@@ -2134,6 +406,236 @@ ALX_HIBNEG_DEF & ~(ALX_HIBNEG_PSHIB_EN | ALX_HIBNEG_HIB_PULSE))
ALX_RSS_HASH_TYPE_IPV4_TCP |\
ALX_RSS_HASH_TYPE_IPV6 |\
ALX_RSS_HASH_TYPE_IPV6_TCP)
+#define ALX_DEF_RXBUF_SIZE 1536
+#define ALX_MAX_JUMBO_PKT_SIZE (9*1024)
+#define ALX_MAX_TSO_PKT_SIZE (7*1024)
+#define ALX_MAX_FRAME_SIZE ALX_MAX_JUMBO_PKT_SIZE
+#define ALX_MIN_FRAME_SIZE 68
+#define ALX_RAW_MTU(_mtu) (_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
+
+#define ALX_MAX_RX_QUEUES 8
+#define ALX_MAX_TX_QUEUES 4
+#define ALX_MAX_HANDLED_INTRS 5
+
+#define ALX_ISR_MISC (\
+ ALX_ISR_PCIE_LNKDOWN | \
+ ALX_ISR_DMAW | \
+ ALX_ISR_DMAR | \
+ ALX_ISR_SMB | \
+ ALX_ISR_MANU | \
+ ALX_ISR_TIMER)
+
+#define ALX_ISR_FATAL (\
+ ALX_ISR_PCIE_LNKDOWN | \
+ ALX_ISR_DMAW | \
+ ALX_ISR_DMAR)
+
+#define ALX_ISR_ALERT (\
+ ALX_ISR_RXF_OV | \
+ ALX_ISR_TXF_UR | \
+ ALX_ISR_RFD_UR)
+
+#define ALX_ISR_ALL_QUEUES (\
+ ALX_ISR_TX_Q0 | \
+ ALX_ISR_TX_Q1 | \
+ ALX_ISR_TX_Q2 | \
+ ALX_ISR_TX_Q3 | \
+ ALX_ISR_RX_Q0 | \
+ ALX_ISR_RX_Q1 | \
+ ALX_ISR_RX_Q2 | \
+ ALX_ISR_RX_Q3 | \
+ ALX_ISR_RX_Q4 | \
+ ALX_ISR_RX_Q5 | \
+ ALX_ISR_RX_Q6 | \
+ ALX_ISR_RX_Q7)
+
+/* maximum interrupt vectors for msix */
+#define ALX_MAX_MSIX_INTRS 16
+#define FIELD_GETX(_x, _name) (((_x) >> (_name##_SHIFT)) & (_name##_MASK))
+#define FIELD_SETS(_x, _name, _v) (\
+(_x) = \
+((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\
+(((u16)(_v) & (_name##_MASK)) << (_name##_SHIFT)))
+#define FIELD_SET32(_x, _name, _v) (\
+(_x) = \
+((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\
+(((_v) & (_name##_MASK)) << (_name##_SHIFT)))
+#define FIELDX(_name, _v) (((_v) & (_name##_MASK)) << (_name##_SHIFT))
-#endif/*ALX_HW_H_*/
+struct alx_hw {
+ void *pdev;
+ u8 __iomem *hw_addr;
+
+ /* pci regs */
+ u16 device_id;
+ u16 subdev_id;
+ u16 subven_id;
+ u8 revision;
+
+ unsigned long capability;
+
+ /* current & permanent mac addr */
+ u8 mac_addr[ETH_ALEN];
+ u8 perm_addr[ETH_ALEN];
+
+ u16 mtu;
+ u16 imt;
+ u8 dma_chnl;
+ u8 max_dma_chnl;
+ /* tpd threshold to trig INT */
+ u32 ith_tpd;
+ u32 rx_ctrl;
+ u32 mc_hash[2];
+
+ u8 rss_key[40];
+ u32 rss_idt[32];
+ u16 rss_idt_size;
+ u8 rss_hash_type;
+
+ /* weight round robin for multiple-tx-Q */
+ u32 wrr[ALX_MAX_TX_QUEUES];
+ /* prioirty control */
+ u32 wrr_ctrl;
+
+ /* interrupt mask for ALX_IMR */
+ u32 imask;
+ u32 smb_timer;
+ bool link_up;
+ u16 link_speed;
+ u8 link_duplex;
+
+ /* auto-neg advertisement or force mode config */
+ u32 adv_cfg;
+ u8 flowctrl;
+
+ struct alx_hw_stats hw_stats;
+ u32 sleep_ctrl;
+
+ spinlock_t mdio_lock;
+ struct mdio_if_info mdio;
+ u16 phy_id[2];
+
+ struct alx_hw_stats stats;
+ /* PHY link patch flag */
+ bool lnk_patch;
+ /* PHY hibernation patch flag */
+ bool hib_patch;
+};
+
+#define ALX_DID(_hw) ((_hw)->device_id)
+#define ALX_SUB_VID(_hw) ((_hw)->subven_id)
+#define ALX_SUB_DID(_hw) ((_hw)->subdev_id)
+#define ALX_REVID(_hw) ((_hw)->revision >> ALX_PCI_REVID_SHIFT)
+#define ALX_WITH_CR(_hw) ((_hw)->revision & 1)
+
+enum ALX_CAPS {
+ ALX_CAP_GIGA = 0,
+ ALX_CAP_PTP,
+ ALX_CAP_AZ,
+ ALX_CAP_L0S,
+ ALX_CAP_L1,
+ ALX_CAP_SWOI,
+ ALX_CAP_RSS,
+ ALX_CAP_MSIX,
+ /* support Multi-TX-Q */
+ ALX_CAP_MTQ,
+ /* support Multi-RX-Q */
+ ALX_CAP_MRQ,
+};
+#define ALX_CAP(_hw, _cap) (\
+ test_bit(ALX_CAP_##_cap, &(_hw)->capability))
+#define ALX_CAP_SET(_hw, _cap) (\
+ set_bit(ALX_CAP_##_cap, &(_hw)->capability))
+#define ALX_CAP_CLEAR(_hw, _cap) (\
+ clear_bit(ALX_CAP_##_cap, &(_hw)->capability))
+
+/* write to 8bit register via pci memory space */
+#define ALX_MEM_W8(s, reg, val) (writeb((val), ((s)->hw_addr + reg)))
+
+/* read from 8bit register via pci memory space */
+#define ALX_MEM_R8(s, reg, pdat) (\
+ *(u8 *)(pdat) = readb((s)->hw_addr + reg))
+
+/* write to 16bit register via pci memory space */
+#define ALX_MEM_W16(s, reg, val) (writew((val), ((s)->hw_addr + reg)))
+
+/* read from 16bit register via pci memory space */
+#define ALX_MEM_R16(s, reg, pdat) (\
+ *(u16 *)(pdat) = readw((s)->hw_addr + reg))
+
+/* write to 32bit register via pci memory space */
+#define ALX_MEM_W32(s, reg, val) (writel((val), ((s)->hw_addr + reg)))
+
+/* read from 32bit register via pci memory space */
+#define ALX_MEM_R32(s, reg, pdat) (\
+ *(u32 *)(pdat) = readl((s)->hw_addr + reg))
+
+/* read from 16bit register via pci config space */
+#define ALX_CFG_R16(s, reg, pdat) (\
+ pci_read_config_word((s)->pdev, (reg), (pdat)))
+
+/* write to 16bit register via pci config space */
+#define ALX_CFG_W16(s, reg, val) (\
+ pci_write_config_word((s)->pdev, (reg), (val)))
+
+/* flush regs */
+#define ALX_MEM_FLUSH(s) (readl((s)->hw_addr))
+
+
+int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr);
+void alx_add_mc_addr(struct alx_hw *hw, u8 *addr);
+void alx_reset_phy(struct alx_hw *hw, bool hib_en);
+void alx_reset_pcie(struct alx_hw *hw);
+void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en);
+int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl);
+void alx_post_phy_link(struct alx_hw *hw, u16 speed, bool az_en);
+int alx_pre_suspend(struct alx_hw *hw, u16 speed);
+int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data);
+int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
+int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata);
+int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data);
+int alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata);
+int alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data);
+int alx_get_phy_link(struct alx_hw *hw, bool *link_up, u16 *speed);
+int alx_clear_phy_intr(struct alx_hw *hw);
+int alx_config_wol(struct alx_hw *hw);
+void alx_cfg_mac_fc(struct alx_hw *hw, u8 fc);
+void alx_start_mac(struct alx_hw *hw);
+int alx_stop_mac(struct alx_hw *hw);
+int alx_reset_mac(struct alx_hw *hw);
+void alx_set_macaddr(struct alx_hw *hw, u8 *addr);
+bool alx_phy_configed(struct alx_hw *hw);
+void alx_configure_basic(struct alx_hw *hw);
+void alx_configure_rss(struct alx_hw *hw, bool en);
+void alx_mask_msix(struct alx_hw *hw, int index, bool mask);
+int alx_select_powersaving_speed(struct alx_hw *hw, u16 *speed);
+void __alx_update_hw_stats(struct alx_hw *hw);
+
+#define alx_get_readrq(_hw) pcie_get_readrq((_hw)->pdev)
+#define alx_set_readrq(_hw, _v) pcie_set_readrq((_hw)->pdev, _v)
+
+
+/* some issues are relavant to specific platforms
+ * we assign those patches for the chip by pci device id
+ * vendor id, subsystem id and revision number
+ */
+struct alx_platform_patch {
+ u16 pci_did;
+ u8 pci_rev;
+ u16 subsystem_vid;
+ u16 subsystem_did;
+ u32 pflag;
+};
+/* PHY link issue */
+#define ALX_PF_LINK 0x00001
+/* Hibernatation issue */
+#define ALX_PF_HIB 0x00002
+/* not care revision number */
+#define ALX_PF_ANY_REV 0x10000
+
+
+void __devinit alx_patch_assign(struct alx_hw *hw);
+bool __devinit alx_get_phy_info(struct alx_hw *hw);
+
+#endif
diff --git a/src/alx_main.c b/src/alx_main.c
index 008bb5f..23b93f8 100644
--- a/src/alx_main.c
+++ b/src/alx_main.c
@@ -21,8 +21,14 @@
#include <linux/ipv6.h>
#include <linux/if_vlan.h>
#include <linux/mii.h>
+#include <linux/mdio.h>
#include <linux/aer.h>
+#include <linux/bitops.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include "alx_reg.h"
+#include "alx_hw.h"
#include "alx.h"
char alx_drv_name[] = "alx";
@@ -59,62 +65,42 @@ static irqreturn_t alx_intr_msix_misc(int irq, void *data);
static irqreturn_t alx_intr_msi(int irq, void *data);
static irqreturn_t alx_intr_legacy(int irq, void *data);
static void alx_init_ring_ptrs(struct alx_adapter *adpt);
+static int alx_reinit_rings(struct alx_adapter *adpt);
static inline void alx_schedule_work(struct alx_adapter *adpt)
{
- if (!ALX_FLAG(adpt, HALT) &&
- !ALX_FLAG(adpt, TASK_PENDING)) {
- ALX_FLAG_SET(adpt, TASK_PENDING);
+ if (!ALX_FLAG(adpt, HALT))
schedule_work(&adpt->task);
- }
}
static inline void alx_cancel_work(struct alx_adapter *adpt)
{
- ALX_FLAG_CLEAR(adpt, TASK_PENDING);
cancel_work_sync(&adpt->task);
}
-void alx_add_mc_addr(struct alx_adapter *adpt, u8 *addr)
-{
- u32 crc32, bit, reg;
-
- crc32 = ether_crc(ETH_ALEN, addr);
-
- /* The HASH Table is a register array of 2 32-bit registers.
- * It is treated like an array of 64 bits. We want to set
- * bit BitArray[hash_value]. So we figure out what register
- * the bit is in, read it, OR in the new bit, then write
- * back the new value. The register is determined by the
- * upper 7 bits of the hash value and the bit within that
- * register are determined by the lower 5 bits of the value.
- */
- reg = (crc32 >> 31) & 0x1;
- bit = (crc32 >> 26) & 0x1F;
-
- adpt->mc_hash[reg] |= (0x1 << bit);
-}
static void __alx_set_rx_mode(struct net_device *netdev)
{
struct alx_adapter *adpt = netdev_priv(netdev);
+ struct alx_hw *hw = &adpt->hw;
struct netdev_hw_addr *ha;
+
/* comoute mc addresses' hash value ,and put it into hash table */
netdev_for_each_mc_addr(ha, netdev)
- alx_add_mc_addr(adpt, ha->addr);
+ alx_add_mc_addr(hw, ha->addr);
- ALX_MEM_W32(adpt, ALX_HASH_TBL0, adpt->mc_hash[0]);
- ALX_MEM_W32(adpt, ALX_HASH_TBL1, adpt->mc_hash[1]);
+ ALX_MEM_W32(hw, ALX_HASH_TBL0, hw->mc_hash[0]);
+ ALX_MEM_W32(hw, ALX_HASH_TBL1, hw->mc_hash[1]);
/* check for Promiscuous and All Multicast modes */
- adpt->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN);
+ hw->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN);
if (netdev->flags & IFF_PROMISC)
- adpt->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN;
+ hw->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN;
if (netdev->flags & IFF_ALLMULTI)
- adpt->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN;
+ hw->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN;
- ALX_MEM_W32(adpt, ALX_MAC_CTRL, adpt->rx_ctrl);
+ ALX_MEM_W32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
}
/* alx_set_rx_mode - Multicast and Promiscuous mode set */
@@ -128,6 +114,7 @@ static void alx_set_rx_mode(struct net_device *netdev)
static int alx_set_mac_address(struct net_device *netdev, void *data)
{
struct alx_adapter *adpt = netdev_priv(netdev);
+ struct alx_hw *hw = &adpt->hw;
struct sockaddr *addr = data;
if (!is_valid_ether_addr(addr->sa_data))
@@ -137,8 +124,8 @@ static int alx_set_mac_address(struct net_device *netdev, void *data)
netdev->addr_assign_type ^= NET_ADDR_RANDOM;
memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
- memcpy(adpt->mac_addr, addr->sa_data, netdev->addr_len);
- alx_set_macaddr(adpt, adpt->mac_addr);
+ memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len);
+ alx_set_macaddr(hw, hw->mac_addr);
return 0;
}
@@ -173,12 +160,13 @@ static u32 rx_vect_mask[] = {ALX_ISR_RX_Q0, ALX_ISR_RX_Q1,
ALX_ISR_RX_Q6, ALX_ISR_RX_Q7};
static int alx_alloc_napis(struct alx_adapter *adpt)
{
+ struct alx_hw *hw = &adpt->hw;
struct alx_napi *np;
struct alx_rx_queue *rxq;
struct alx_tx_queue *txq;
int i;
- adpt->imask &= ~ALX_ISR_ALL_QUEUES;
+ hw->imask &= ~ALX_ISR_ALL_QUEUES;
/* alloc alx_napi */
for (i = 0; i < adpt->nr_napi; i++) {
@@ -203,7 +191,7 @@ static int alx_alloc_napis(struct alx_adapter *adpt)
txq->count = adpt->tx_ringsz;
txq->qidx = (u16)i;
np->vec_mask |= tx_vect_mask[i];
- adpt->imask |= tx_vect_mask[i];
+ hw->imask |= tx_vect_mask[i];
}
/* alloc rx queue */
@@ -217,8 +205,9 @@ static int alx_alloc_napis(struct alx_adapter *adpt)
rxq->c_reg = ALX_RFD_CIDX;
rxq->count = adpt->rx_ringsz;
rxq->qidx = (u16)i;
+ __skb_queue_head_init(&rxq->list);
np->vec_mask |= rx_vect_mask[i];
- adpt->imask |= rx_vect_mask[i];
+ hw->imask |= rx_vect_mask[i];
}
return 0;
@@ -233,23 +222,22 @@ static int alx_alloc_rings(struct alx_adapter *adpt)
struct alx_buffer *bf;
u8 *desc;
dma_addr_t dma;
- int i, size, hw_rxrng, offset;
+ int i, size, offset;
/* alx_buffer */
size = sizeof(struct alx_buffer) * adpt->nr_txq * adpt->tx_ringsz +
- sizeof(struct alx_buffer) * adpt->nr_rxq * adpt->rx_ringsz;
+ sizeof(struct alx_buffer) * adpt->nr_hwrxq * adpt->rx_ringsz;
bf = vzalloc(size);
if (!bf)
goto err_out;
/* physical rx rings */
- hw_rxrng = ALX_FLAG(adpt, CAP_MRQ) ? adpt->nr_rxq : 1;
size = sizeof(struct tpd_desc) * adpt->tx_ringsz * adpt->nr_txq +
(sizeof(struct rrd_desc) + sizeof(struct rfd_desc)) *
- adpt->rx_ringsz * hw_rxrng +
- adpt->nr_txq * 8 + /* tx align */
- hw_rxrng * 8; /* rx align */
+ adpt->rx_ringsz * adpt->nr_hwrxq +
+ adpt->nr_txq * 8 +
+ adpt->nr_hwrxq * 8;
desc = dma_alloc_coherent(&adpt->pdev->dev, size, &dma, GFP_KERNEL);
if (!desc)
goto err_out;
@@ -275,20 +263,19 @@ static int alx_alloc_rings(struct alx_adapter *adpt)
bf += adpt->tx_ringsz;
}
size = sizeof(struct rrd_desc) * adpt->rx_ringsz;
- for (i = 0; i < hw_rxrng; i++) {
+ for (i = 0; i < adpt->nr_hwrxq; i++) {
offset = ALIGN(dma, 8) - dma;
desc += offset;
dma += offset;
- adpt->qnapi[i]->rxq->netdev = adpt->netdev;
- adpt->qnapi[i]->rxq->dev = &adpt->pdev->dev;
adpt->qnapi[i]->rxq->rrd_hdr = (struct rrd_desc *)desc;
adpt->qnapi[i]->rxq->rrd_dma = dma;
- adpt->qnapi[i]->rxq->count = adpt->rx_ringsz;
+ adpt->qnapi[i]->rxq->bf_info = bf;
desc += size;
dma += size;
+ bf += adpt->rx_ringsz;
}
size = sizeof(struct rfd_desc) * adpt->rx_ringsz;
- for (i = 0; i < hw_rxrng; i++) {
+ for (i = 0; i < adpt->nr_hwrxq; i++) {
offset = ALIGN(dma, 8) - dma;
desc += offset;
dma += offset;
@@ -298,8 +285,9 @@ static int alx_alloc_rings(struct alx_adapter *adpt)
dma += size;
}
for (i = 0; i < adpt->nr_rxq; i++) {
- adpt->qnapi[i]->rxq->bf_info = bf;
- bf += adpt->rx_ringsz;
+ adpt->qnapi[i]->rxq->netdev = adpt->netdev;
+ adpt->qnapi[i]->rxq->dev = &adpt->pdev->dev;
+ adpt->qnapi[i]->rxq->count = adpt->rx_ringsz;
}
return 0;
@@ -334,6 +322,55 @@ static void alx_free_rings(struct alx_adapter *adpt)
}
}
+/* dequeue skb from RXQ, return true if the RXQ is empty */
+static inline bool alx_skb_dequeue_n(struct alx_rx_queue *rxq, int max_pkts,
+ struct sk_buff_head *list)
+{
+ struct alx_adapter *adpt = netdev_priv(rxq->netdev);
+ bool use_lock = !ALX_CAP(&adpt->hw, MRQ);
+ bool empty;
+ struct sk_buff *skb;
+ int count = 0;
+
+ if (use_lock)
+ spin_lock(&rxq->list.lock);
+
+ while (count < max_pkts || max_pkts == -1) {
+ skb = __skb_dequeue(&rxq->list);
+ if (skb) {
+ __skb_queue_tail(list, skb);
+ count++;
+ } else
+ break;
+ }
+
+ empty = skb_queue_empty(&rxq->list);
+
+ if (use_lock)
+ spin_unlock(&rxq->list.lock);
+
+ netif_info(adpt, rx_status, adpt->netdev,
+ "RX %d packets\n",
+ count);
+
+ return empty;
+}
+
+static inline void alx_skb_queue_tail(struct alx_rx_queue *rxq,
+ struct sk_buff *skb)
+{
+ struct alx_adapter *adpt = netdev_priv(rxq->netdev);
+ bool use_lock = !ALX_CAP(&adpt->hw, MRQ);
+
+ if (use_lock)
+ spin_lock(&rxq->list.lock);
+
+ __skb_queue_tail(&rxq->list, skb);
+
+ if (use_lock)
+ spin_unlock(&rxq->list.lock);
+}
+
static int alx_alloc_rxring_buf(struct alx_adapter *adpt,
struct alx_rx_queue *rxq)
{
@@ -381,7 +418,7 @@ static int alx_alloc_rxring_buf(struct alx_adapter *adpt,
if (count) {
wmb();
rxq->pidx = cur;
- ALX_MEM_W16(adpt, rxq->p_reg, (u16)cur);
+ ALX_MEM_W16(&adpt->hw, rxq->p_reg, (u16)cur);
}
return count;
@@ -390,6 +427,7 @@ static int alx_alloc_rxring_buf(struct alx_adapter *adpt,
static void alx_free_rxring_buf(struct alx_rx_queue *rxq)
{
struct alx_buffer *cur_buf;
+ struct sk_buff_head list;
u16 i;
if (rxq == NULL)
@@ -408,6 +446,17 @@ static void alx_free_rxring_buf(struct alx_rx_queue *rxq)
dma_unmap_addr_set(cur_buf, dma, 0);
}
}
+
+ /* some skbs might be pending in the list */
+ __skb_queue_head_init(&list);
+ alx_skb_dequeue_n(rxq, -1, &list);
+ while (!skb_queue_empty(&list)) {
+ struct sk_buff *skb;
+
+ skb = __skb_dequeue(&list);
+ dev_kfree_skb(skb);
+ }
+
rxq->pidx = 0;
rxq->cidx = 0;
rxq->rrd_cidx = 0;
@@ -415,30 +464,23 @@ static void alx_free_rxring_buf(struct alx_rx_queue *rxq)
static int alx_setup_all_ring_resources(struct alx_adapter *adpt)
{
- int err, i;
+ int err;
err = alx_alloc_napis(adpt);
if (err)
goto out;
+
err = alx_alloc_rings(adpt);
if (err)
goto out;
- /* set ring headers to HW register */
- alx_init_ring_ptrs(adpt);
+ err = alx_reinit_rings(adpt);
- for (i = 0; i < adpt->nr_rxq; i++) {
- err = alx_alloc_rxring_buf(adpt, adpt->qnapi[i]->rxq);
- if (!err) {
- err = -ENOMEM;
- goto out;
- }
- }
out:
if (unlikely(err)) {
- dev_err(&adpt->pdev->dev,
- "setup_all_ring_resources fail %d\n",
- err);
+ netif_err(adpt, ifup, adpt->netdev,
+ "setup_all_ring_resources fail %d\n",
+ err);
}
return err;
}
@@ -491,10 +533,12 @@ static void alx_free_all_rings_buf(struct alx_adapter *adpt)
int i;
for (i = 0; i < adpt->nr_txq; i++)
- alx_free_txring_buf(adpt->qnapi[i]->txq);
+ if (adpt->qnapi[i])
+ alx_free_txring_buf(adpt->qnapi[i]->txq);
- for (i = 0; i < adpt->nr_rxq; i++)
- alx_free_rxring_buf(adpt->qnapi[i]->rxq);
+ for (i = 0; i < adpt->nr_hwrxq; i++)
+ if (adpt->qnapi[i])
+ alx_free_rxring_buf(adpt->qnapi[i]->rxq);
}
static void alx_free_all_ring_resources(struct alx_adapter *adpt)
@@ -529,29 +573,31 @@ static bool alx_clean_tx_irq(struct alx_tx_queue *txq)
netque = netdev_get_tx_queue(adpt->netdev, txq->qidx);
sw_cidx = atomic_read(&txq->cidx);
- ALX_MEM_R16(adpt, txq->c_reg, &hw_cidx);
+ ALX_MEM_R16(&adpt->hw, txq->c_reg, &hw_cidx);
- netdev_info(adpt->netdev,
- "TX[Preg:%x]: consumer = 0x%x, hw-consumer = 0x%x\n",
- txq->p_reg, sw_cidx, hw_cidx);
+ if (sw_cidx != hw_cidx) {
- while (sw_cidx != hw_cidx && budget > 0) {
- struct sk_buff *skb;
+ netif_info(adpt, tx_done, adpt->netdev,
+ "TX[Q:%d, Preg:%x]: cons = 0x%x, hw-cons = 0x%x\n",
+ txq->qidx, txq->p_reg, sw_cidx, hw_cidx);
- skb = txq->bf_info[sw_cidx].skb;
- if (skb) {
- total_bytes += skb->len;
- total_packets++;
- budget--;
+ while (sw_cidx != hw_cidx && budget > 0) {
+ struct sk_buff *skb;
+
+ skb = txq->bf_info[sw_cidx].skb;
+ if (skb) {
+ total_bytes += skb->len;
+ total_packets++;
+ budget--;
+ }
+ alx_txbuf_unmap_and_free(txq, sw_cidx);
+ if (++sw_cidx == txq->count)
+ sw_cidx = 0;
}
- alx_txbuf_unmap_and_free(txq, sw_cidx);
+ atomic_set(&txq->cidx, sw_cidx);
- if (++sw_cidx == txq->count)
- sw_cidx = 0;
+ netdev_tx_completed_queue(netque, total_packets, total_bytes);
}
- atomic_set(&txq->cidx, sw_cidx);
-
- netdev_tx_completed_queue(netque, total_packets, total_bytes);
if (unlikely(netif_tx_queue_stopped(netque) &&
netif_carrier_ok(adpt->netdev) &&
@@ -563,50 +609,6 @@ static bool alx_clean_tx_irq(struct alx_tx_queue *txq)
return sw_cidx == hw_cidx;
}
-static inline bool alx_skb_dequeue_n(struct alx_rx_queue *rxq, int max_pkts,
- struct sk_buff_head *list)
-{
- struct alx_adapter *adpt = netdev_priv(rxq->netdev);
- bool use_lock = !ALX_FLAG(adpt, CAP_MRQ);
- bool empty;
- struct sk_buff *skb;
- int count = 0;
-
- if (use_lock)
- spin_lock(&rxq->list.lock);
-
- while (count < max_pkts) {
- skb = __skb_dequeue(&rxq->list);
- if (skb) {
- __skb_queue_tail(list, skb);
- count++;
- } else
- break;
- }
-
- empty = count == 0;
-
- if (use_lock)
- spin_unlock(&rxq->list.lock);
-
- return empty;
-}
-
-static inline void alx_skb_queue_tail(struct alx_rx_queue *rxq,
- struct sk_buff *skb)
-{
- struct alx_adapter *adpt = netdev_priv(rxq->netdev);
- bool use_lock = !ALX_FLAG(adpt, CAP_MRQ);
-
- if (use_lock)
- spin_lock(&rxq->list.lock);
-
- __skb_queue_tail(&rxq->list, skb);
-
- if (use_lock)
- spin_unlock(&rxq->list.lock);
-}
-
static bool alx_dispatch_skb(struct alx_rx_queue *rxq)
{
struct alx_adapter *adpt = netdev_priv(rxq->netdev);
@@ -628,9 +630,9 @@ static bool alx_dispatch_skb(struct alx_rx_queue *rxq)
if (unlikely(FIELD_GETX(rrd->word0, RRD_SI) != rxq->cidx ||
FIELD_GETX(rrd->word0, RRD_NOR) != 1)) {
- netdev_err(adpt->netdev,
- "wrong rrd-SI/NOR packet! rrd->word0 is %08x\n",
- rrd->word0);
+ netif_err(adpt, rx_err, adpt->netdev,
+ "wrong SI/NOR packet! rrd->word0= %08x\n",
+ rrd->word0);
/* reset chip */
ALX_FLAG_SET(adpt, TASK_RESET);
alx_schedule_work(adpt);
@@ -683,7 +685,7 @@ static bool alx_dispatch_skb(struct alx_rx_queue *rxq)
__vlan_hwaccel_put_tag(skb, ntohs(tag));
}
qnum = FIELD_GETX(rrd->word2, RRD_RSSQ) % adpt->nr_rxq;
- tmp_rxq = ALX_FLAG(adpt, CAP_MRQ) ?
+ tmp_rxq = ALX_CAP(&adpt->hw, MRQ) ?
rxq : adpt->qnapi[qnum]->rxq;
alx_skb_queue_tail(tmp_rxq, skb);
@@ -710,39 +712,7 @@ static inline struct alx_rx_queue *alx_hw_rxq(struct alx_rx_queue *rxq)
{
struct alx_adapter *adpt = netdev_priv(rxq->netdev);
- return ALX_FLAG(adpt, CAP_MRQ) ? rxq : adpt->qnapi[0]->rxq;
-}
-
-static void __alx_configure_rss(struct alx_adapter *adpt)
-{
- u32 ctrl;
- int i;
-
- ALX_MEM_R32(adpt, ALX_RXQ0, &ctrl);
-
- if (adpt->nr_rxq > 1) { /* RSS enable */
-
- for (i = 0; i < sizeof(adpt->rss_key); i++) {
- /* rss key should be saved in chip with
- * reversed order.
- */
- int j = sizeof(adpt->rss_key) - i - 1;
-
- ALX_MEM_W8(adpt, ALX_RSS_KEY0 + j, adpt->rss_key[i]);
- }
-
- for (i = 0; i < ARRAY_SIZE(adpt->rss_idt); i++)
- ALX_MEM_W32(adpt, ALX_RSS_IDT_TBL0, adpt->rss_idt[i]);
-
- FIELD_SET32(ctrl, ALX_RXQ0_RSS_HSTYP, adpt->rss_hash_type);
- FIELD_SET32(ctrl, ALX_RXQ0_RSS_MODE, ALX_RXQ0_RSS_MODE_MQMI);
- FIELD_SET32(ctrl, ALX_RXQ0_IDT_TBL_SIZE, adpt->rss_idt_size);
- ctrl |= ALX_RXQ0_RSS_HASH_EN;
- } else { /* RSS disable */
- ctrl &= ~ALX_RXQ0_RSS_HASH_EN;
- }
-
- ALX_MEM_W32(adpt, ALX_RXQ0, ctrl);
+ return ALX_CAP(&adpt->hw, MRQ) ? rxq : adpt->qnapi[0]->rxq;
}
static inline struct napi_struct *alx_rxq_to_napi(
@@ -756,11 +726,10 @@ static inline struct napi_struct *alx_rxq_to_napi(
static bool alx_clean_rx_irq(struct alx_rx_queue *rxq, int budget)
{
struct sk_buff_head list;
- int empty;
- bool collect;
+ bool empty;
__skb_queue_head_init(&list);
- collect = alx_dispatch_skb(alx_hw_rxq(rxq));
+ alx_dispatch_skb(alx_hw_rxq(rxq));
empty = alx_skb_dequeue_n(rxq, budget, &list);
if (!skb_queue_empty(&list)) {
struct napi_struct *napi;
@@ -771,9 +740,15 @@ static bool alx_clean_rx_irq(struct alx_rx_queue *rxq, int budget)
skb = __skb_dequeue(&list);
napi_gro_receive(napi, skb);
}
+ } else {
+ struct alx_adapter *adpt = netdev_priv(rxq->netdev);
+
+ netif_info(adpt, rx_status, adpt->netdev,
+ "no packet received for this rxQ\n");
}
- return collect && empty;
+
+ return empty;
}
static int alx_request_msix(struct alx_adapter *adpt)
@@ -826,19 +801,6 @@ static void alx_disable_msix(struct alx_adapter *adpt)
ALX_FLAG_CLEAR(adpt, USING_MSIX);
}
-static void alx_mask_msix(struct alx_adapter *adpt, int index, bool mask)
-{
- u32 reg, val;
-
- reg = ALX_MSIX_ENTRY_BASE + index * PCI_MSIX_ENTRY_SIZE +
- PCI_MSIX_ENTRY_VECTOR_CTRL;
-
- val = mask ? PCI_MSIX_ENTRY_CTRL_MASKBIT : 0;
-
- ALX_MEM_W32(adpt, reg, val);
- ALX_MEM_FLUSH(adpt);
-}
-
static void alx_disable_msi(struct alx_adapter *adpt)
{
if (ALX_FLAG(adpt, USING_MSI)) {
@@ -847,45 +809,92 @@ static void alx_disable_msi(struct alx_adapter *adpt)
}
}
+static int txq_vec_mapping_shift[] = {
+ 0, ALX_MSI_MAP_TBL1_TXQ0_SHIFT,
+ 0, ALX_MSI_MAP_TBL1_TXQ1_SHIFT,
+ 1, ALX_MSI_MAP_TBL2_TXQ2_SHIFT,
+ 1, ALX_MSI_MAP_TBL2_TXQ3_SHIFT,
+};
+static int rxq_vec_mapping_shift[] = {
+ 0, ALX_MSI_MAP_TBL1_RXQ0_SHIFT,
+ 0, ALX_MSI_MAP_TBL1_RXQ1_SHIFT,
+ 0, ALX_MSI_MAP_TBL1_RXQ2_SHIFT,
+ 0, ALX_MSI_MAP_TBL1_RXQ3_SHIFT,
+ 1, ALX_MSI_MAP_TBL2_RXQ4_SHIFT,
+ 1, ALX_MSI_MAP_TBL2_RXQ5_SHIFT,
+ 1, ALX_MSI_MAP_TBL2_RXQ6_SHIFT,
+ 1, ALX_MSI_MAP_TBL2_RXQ7_SHIFT,
+};
+static void alx_config_vector_mapping(struct alx_adapter *adpt)
+{
+ struct alx_hw *hw = &adpt->hw;
+ u32 tbl[2];
+ int vect, idx, shft;
+ int i;
+
+ tbl[0] = tbl[1] = 0;
+
+ if (ALX_FLAG(adpt, USING_MSIX)) {
+ for (vect = 1, i = 0; i < adpt->nr_txq; i++, vect++) {
+ idx = txq_vec_mapping_shift[i * 2];
+ shft = txq_vec_mapping_shift[i * 2 + 1];
+ tbl[idx] |= vect << shft;
+ }
+ for (vect = 1, i = 0; i < adpt->nr_rxq; i++, vect++) {
+ idx = rxq_vec_mapping_shift[i * 2];
+ shft = rxq_vec_mapping_shift[i * 2 + 1];
+ tbl[idx] |= vect << shft;
+ }
+ }
+ ALX_MEM_W32(hw, ALX_MSI_MAP_TBL1, tbl[0]);
+ ALX_MEM_W32(hw, ALX_MSI_MAP_TBL2, tbl[1]);
+ ALX_MEM_W32(hw, ALX_MSI_ID_MAP, 0);
+}
+
static void alx_disable_advanced_intr(struct alx_adapter *adpt)
{
alx_disable_msix(adpt);
alx_disable_msi(adpt);
+
+ /* clear vector/intr-event mapping */
+ alx_config_vector_mapping(adpt);
}
static void alx_irq_enable(struct alx_adapter *adpt)
{
+ struct alx_hw *hw = &adpt->hw;
int i;
if (!atomic_dec_and_test(&adpt->irq_sem))
return;
/* level-1 interrupt switch */
- ALX_MEM_W32(adpt, ALX_ISR, 0);
- ALX_MEM_W32(adpt, ALX_IMR, adpt->imask);
- ALX_MEM_FLUSH(adpt);
+ ALX_MEM_W32(hw, ALX_ISR, 0);
+ ALX_MEM_W32(hw, ALX_IMR, hw->imask);
+ ALX_MEM_FLUSH(hw);
if (!ALX_FLAG(adpt, USING_MSIX))
return;
/* enable all individual MSIX IRQs */
for (i = 0; i < adpt->nr_vec; i++)
- alx_mask_msix(adpt, i, false);
+ alx_mask_msix(hw, i, false);
}
static void alx_irq_disable(struct alx_adapter *adpt)
{
+ struct alx_hw *hw = &adpt->hw;
int i;
atomic_inc(&adpt->irq_sem);
- ALX_MEM_W32(adpt, ALX_ISR, ALX_ISR_DIS);
- ALX_MEM_W32(adpt, ALX_IMR, 0);
- ALX_MEM_FLUSH(adpt);
+ ALX_MEM_W32(hw, ALX_ISR, ALX_ISR_DIS);
+ ALX_MEM_W32(hw, ALX_IMR, 0);
+ ALX_MEM_FLUSH(hw);
if (ALX_FLAG(adpt, USING_MSIX)) {
for (i = 0; i < adpt->nr_vec; i++) {
- alx_mask_msix(adpt, i, true);
+ alx_mask_msix(hw, i, true);
synchronize_irq(adpt->msix_ent[i].vector);
}
} else {
@@ -896,14 +905,14 @@ static void alx_irq_disable(struct alx_adapter *adpt)
static int alx_request_irq(struct alx_adapter *adpt)
{
struct pci_dev *pdev = adpt->pdev;
+ struct alx_hw *hw = &adpt->hw;
int err;
u32 msi_ctrl;
- adpt->imask = ALX_ISR_MISC;
- msi_ctrl = FIELDX(ALX_MSI_RETRANS_TM, adpt->imt >> 1);
+ msi_ctrl = FIELDX(ALX_MSI_RETRANS_TM, hw->imt >> 1);
if (ALX_FLAG(adpt, USING_MSIX)) {
- ALX_MEM_W32(adpt, ALX_MSI_RETRANS_TIMER, msi_ctrl);
+ ALX_MEM_W32(hw, ALX_MSI_RETRANS_TIMER, msi_ctrl);
err = alx_request_msix(adpt);
if (!err)
goto out;
@@ -916,25 +925,20 @@ static int alx_request_irq(struct alx_adapter *adpt)
adpt->nr_txq = 1;
adpt->nr_napi = 1;
adpt->nr_vec = 1;
- __alx_configure_rss(adpt); /* disable RSS */
+ adpt->nr_hwrxq = 1;
+ alx_configure_rss(hw, false);
netif_set_real_num_tx_queues(adpt->netdev, adpt->nr_txq);
netif_set_real_num_rx_queues(adpt->netdev, adpt->nr_rxq);
if (!pci_enable_msi(pdev))
ALX_FLAG_SET(adpt, USING_MSI);
err = alx_setup_all_ring_resources(adpt);
- if (err) {
- dev_err(&pdev->dev,
- "Unable to allocate enough memory err=%d\n",
- err);
+ if (err)
goto out;
- }
}
- adpt->imask = ALX_ISR_MISC | ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
-
if (ALX_FLAG(adpt, USING_MSI)) {
- ALX_MEM_W32(adpt, ALX_MSI_RETRANS_TIMER,
+ ALX_MEM_W32(hw, ALX_MSI_RETRANS_TIMER,
msi_ctrl | ALX_MSI_MASK_SEL_LINE);
err = request_irq(pdev->irq, alx_intr_msi, 0,
adpt->netdev->name, adpt);
@@ -944,18 +948,30 @@ static int alx_request_irq(struct alx_adapter *adpt)
alx_disable_msi(adpt);
}
- ALX_MEM_W32(adpt, ALX_MSI_RETRANS_TIMER, 0);
+ ALX_MEM_W32(hw, ALX_MSI_RETRANS_TIMER, 0);
err = request_irq(pdev->irq, alx_intr_legacy, IRQF_SHARED,
adpt->netdev->name, adpt);
if (err)
- dev_err(&pdev->dev,
- "request shared irq failed, err = %d\n",
- err);
+ netif_err(adpt, intr, adpt->netdev,
+ "request shared irq failed, err = %d\n",
+ err);
out:
- if (unlikely(err))
- dev_err(&pdev->dev, "register IRQ fail %d\n", err);
+ if (likely(!err)) {
+ alx_config_vector_mapping(adpt);
+ netif_info(adpt, intr, adpt->netdev,
+ "nr_rxq=%d, nr_txq=%d, nr_napi=%d, nr_vec=%d\n",
+ adpt->nr_rxq, adpt->nr_txq,
+ adpt->nr_napi, adpt->nr_vec);
+ netif_info(adpt, intr, adpt->netdev,
+ "Interrupt Mode: %s\n",
+ ALX_FLAG(adpt, USING_MSIX) ? "MSIX" :
+ ALX_FLAG(adpt, USING_MSI) ? "MSI" : "INTx");
+ } else
+ netdev_err(adpt->netdev,
+ "register IRQ fail %d\n",
+ err);
return err;
}
@@ -979,10 +995,18 @@ static void alx_free_irq(struct alx_adapter *adpt)
static int __devinit alx_identify_hw(struct alx_adapter *adpt)
{
- int rev = ALX_REVID(adpt);
+ struct pci_dev *pdev = adpt->pdev;
+ struct alx_hw *hw = &adpt->hw;
+ int rev;
int err = -EINVAL;
- switch (ALX_DID(adpt)) {
+ hw->device_id = pdev->device;
+ hw->subdev_id = pdev->subsystem_device;
+ hw->subven_id = pdev->subsystem_vendor;
+ hw->revision = pdev->revision;
+ rev = ALX_REVID(hw);
+
+ switch (ALX_DID(hw)) {
case ALX_DEV_ID_AR8161:
case ALX_DEV_ID_AR8162:
case ALX_DEV_ID_AR8171:
@@ -990,70 +1014,22 @@ static int __devinit alx_identify_hw(struct alx_adapter *adpt)
if (rev > ALX_REV_B0)
break;
err = 0;
- ALX_FLAG_SET(adpt, CAP_L0S);
- ALX_FLAG_SET(adpt, CAP_L1);
- adpt->max_dma_chnl = rev == ALX_REV_B0 ? 4 : 2;
+ ALX_CAP_SET(hw, L0S);
+ ALX_CAP_SET(hw, L1);
+ ALX_CAP_SET(hw, MTQ);
+ ALX_CAP_SET(hw, RSS);
+ ALX_CAP_SET(hw, MSIX);
+ ALX_CAP_SET(hw, SWOI);
+ hw->max_dma_chnl = rev == ALX_REV_B0 ? 4 : 2;
break;
}
- if (!err && ALX_DID(adpt) & 1) { /* id-bit0: gigabit flag */
- ALX_FLAG_SET(adpt, CAP_GIGA);
- }
+ if (!err && ALX_DID(hw) & 1)
+ ALX_CAP_SET(hw, GIGA);
return err;
}
-static bool __devinit alx_get_phy_id(struct alx_adapter *adpt)
-{
- /* prtad is fixed to 0 for all of chips */
- if (mdio45_probe(&adpt->mdio, 0))
- return false;
-
- if (alx_read_phy_reg(adpt, MII_PHYSID1, &adpt->phy_id[0]) ||
- alx_read_phy_reg(adpt, MII_PHYSID2, &adpt->phy_id[1]))
- return false;
-
- return true;
-}
-
-/* some issues are relavant to specific platforms
- * we assign those patches for the chip by pci device id
- * vendor id, subsystem id and revision number
- */
-struct alx_platform_patch {
- u16 pci_did; /* pci device id */
- u8 pci_rev; /* pci revision id */
- u16 subsystem_vid;
- u16 subsystem_did;
- u32 pflag; /* patch flag */
-#define ALX_PF_LINK 0x00001 /* PHY link issue */
-#define ALX_PF_HIB 0x00002 /* Hibernatation issue */
-#define ALX_PF_ANY_REV 0x10000 /* not care revision number */
-};
-
-static const struct alx_platform_patch plats[] __devinitdata = {
-{0x1091, 0x00, 0x1969, 0x0091, 0x1001},
-{0},
-};
-
-static void __devinit alx_patch_assign(struct alx_adapter *adpt)
-{
- int i = 0;
-
- while (plats[i].pci_did != 0) {
- if (plats[i].pci_did == ALX_DID(adpt) &&
- plats[i].subsystem_vid == ALX_SUB_VID(adpt) &&
- plats[i].subsystem_did == ALX_SUB_DID(adpt) &&
- (plats[i].pflag & ALX_PF_ANY_REV ||
- plats[i].pci_rev == adpt->pdev->revision)) {
- if (plats[i].pflag & ALX_PF_LINK)
- adpt->lnk_patch = true;
- if (plats[i].pflag & ALX_PF_HIB)
- adpt->hib_patch = true;
- }
- i++;
- }
-}
static const u8 def_rss_key[40] __devinitdata = {
0xE2, 0x91, 0xD7, 0x3D, 0x18, 0x05, 0xEC, 0x6C,
@@ -1065,18 +1041,18 @@ static const u8 def_rss_key[40] __devinitdata = {
static void alx_init_def_rss_idt(struct alx_adapter *adpt)
{
+ struct alx_hw *hw = &adpt->hw;
int i, x, y;
u32 val;
- for (i = 0; i < adpt->rss_idt_size; i++) {
+ for (i = 0; i < hw->rss_idt_size; i++) {
val = ethtool_rxfh_indir_default(i, adpt->nr_rxq);
x = i >> 3;
y = i * 4 & 0x1F;
- adpt->rss_idt[x] &= ~(0xF << y);
- adpt->rss_idt[x] |= (val & 0xF) << y;
+ hw->rss_idt[x] &= ~(0xF << y);
+ hw->rss_idt[x] |= (val & 0xF) << y;
}
}
-
/* alx_init_adapter -
* initialize general software structure (struct alx_adapter).
* fields are inited based on PCI device information.
@@ -1084,6 +1060,7 @@ static void alx_init_def_rss_idt(struct alx_adapter *adpt)
static int __devinit alx_init_sw(struct alx_adapter *adpt)
{
struct pci_dev *pdev = adpt->pdev;
+ struct alx_hw *hw = &adpt->hw;
int i, err;
err = alx_identify_hw(adpt);
@@ -1093,35 +1070,42 @@ static int __devinit alx_init_sw(struct alx_adapter *adpt)
}
/* assign patch flag for specific platforms */
- alx_patch_assign(adpt);
-
- memcpy(adpt->rss_key, def_rss_key, sizeof(def_rss_key));
- adpt->rss_idt_size = 0x100;
- adpt->rss_hash_type = ALX_RSS_HASH_TYPE_ALL;
- adpt->smb_timer = 400; /* trigger stats interrupt per 400ms */
- adpt->mtu = adpt->netdev->mtu;
- adpt->rxbuf_size = ALIGN(ALX_RAW_MTU(adpt->mtu), 8);
+ alx_patch_assign(hw);
+
+ memcpy(hw->rss_key, def_rss_key, sizeof(def_rss_key));
+ hw->rss_idt_size = 0x100;
+ hw->rss_hash_type = ALX_RSS_HASH_TYPE_ALL;
+ hw->smb_timer = 400;
+ hw->mtu = adpt->netdev->mtu;
+ adpt->rxbuf_size = ALIGN(ALX_RAW_MTU(hw->mtu), 8);
adpt->tx_ringsz = 256;
adpt->rx_ringsz = 512;
- adpt->sleep_ctrl = ALX_SLEEP_WOL_MAGIC | ALX_SLEEP_WOL_PHY;
- adpt->imt = 200; /* 200us */
- adpt->dma_chnl = adpt->max_dma_chnl;
- adpt->link_up = false; /* PHY init status */
- adpt->link_duplex = 0;
- adpt->link_speed = SPEED_0;
- adpt->adv_cfg = ADVERTISED_Autoneg |
+ hw->sleep_ctrl = ALX_SLEEP_WOL_MAGIC | ALX_SLEEP_WOL_PHY;
+ hw->imt = 200;
+ hw->imask = ALX_ISR_MISC;
+ hw->dma_chnl = hw->max_dma_chnl;
+ hw->ith_tpd = adpt->tx_ringsz / 3;
+ hw->link_up = false;
+ hw->link_duplex = 0;
+ hw->link_speed = SPEED_0;
+ hw->adv_cfg = ADVERTISED_Autoneg |
ADVERTISED_10baseT_Half |
ADVERTISED_10baseT_Full |
ADVERTISED_100baseT_Full |
ADVERTISED_10baseT_Half |
ADVERTISED_1000baseT_Full;
- adpt->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX;
- adpt->wrr_ctrl = ALX_WRR_PRI_RESTRICT_NONE;
- for (i = 0; i < ARRAY_SIZE(adpt->wrr); i++)
- adpt->wrr[i] = 4;
+ hw->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX;
+ hw->wrr_ctrl = ALX_WRR_PRI_RESTRICT_NONE;
+ for (i = 0; i < ARRAY_SIZE(hw->wrr); i++)
+ hw->wrr[i] = 4;
- adpt->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN |
+ hw->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN |
ALX_MAC_CTRL_MHASH_ALG_HI5B |
+ ALX_MAC_CTRL_BRD_EN |
+ ALX_MAC_CTRL_PCRCE |
+ ALX_MAC_CTRL_CRCE |
+ ALX_MAC_CTRL_RXFC_EN |
+ ALX_MAC_CTRL_TXFC_EN |
FIELDX(ALX_MAC_CTRL_PRMBLEN, 7);
atomic_set(&adpt->irq_sem, 1);
@@ -1130,6 +1114,19 @@ static int __devinit alx_init_sw(struct alx_adapter *adpt)
return err;
}
+
+static void alx_set_vlan_mode(struct alx_hw *hw,
+ netdev_features_t features)
+{
+ if (features & NETIF_F_HW_VLAN_RX)
+ hw->rx_ctrl |= ALX_MAC_CTRL_VLANSTRIP;
+ else
+ hw->rx_ctrl &= ~ALX_MAC_CTRL_VLANSTRIP;
+
+ ALX_MEM_W32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
+}
+
+
static netdev_features_t alx_fix_features(struct net_device *netdev,
netdev_features_t features)
{
@@ -1158,12 +1155,7 @@ static int alx_set_features(struct net_device *netdev,
if (!(changed & NETIF_F_HW_VLAN_RX))
return 0;
- if (features & NETIF_F_HW_VLAN_RX)
- adpt->rx_ctrl |= ALX_MAC_CTRL_VLANSTRIP;
- else
- adpt->rx_ctrl &= ~ALX_MAC_CTRL_VLANSTRIP;
-
- ALX_MEM_W32(adpt, ALX_MAC_CTRL, adpt->rx_ctrl);
+ alx_set_vlan_mode(&adpt->hw, features);
return 0;
}
@@ -1177,15 +1169,18 @@ static int alx_change_mtu(struct net_device *netdev, int new_mtu)
if ((max_frame < ALX_MIN_FRAME_SIZE) ||
(max_frame > ALX_MAX_FRAME_SIZE)) {
- netdev_err(netdev, "invalid MTU setting\n");
+ netif_err(adpt, hw, netdev,
+ "invalid MTU setting (%x)\n",
+ new_mtu);
return -EINVAL;
}
/* set MTU */
if (old_mtu != new_mtu && netif_running(netdev)) {
- netdev_info(adpt->netdev,
+ netif_info(adpt, drv, adpt->netdev,
"changing MTU from %d to %d\n",
netdev->mtu, new_mtu);
netdev->mtu = new_mtu;
+ adpt->hw.mtu = new_mtu;
adpt->rxbuf_size = new_mtu > ALX_DEF_RXBUF_SIZE ?
ALIGN(max_frame, 8) : ALX_DEF_RXBUF_SIZE;
netdev_update_features(netdev);
@@ -1201,131 +1196,38 @@ static int alx_change_mtu(struct net_device *netdev, int new_mtu)
*/
static void alx_configure(struct alx_adapter *adpt)
{
- u32 val, raw_mtu, max_payload;
- u16 val16;
- u8 chip_rev = ALX_REVID(adpt);
-
- /* mac address */
- alx_set_macaddr(adpt, adpt->mac_addr);
+ struct alx_hw *hw = &adpt->hw;
-#if 0
- /* clear WoL setting/status */
- ALX_MEM_R32(hw, ALX_WOL0, &val);
- ALX_MEM_W32(hw, ALX_WOL0, 0);
-#endif
- /* clk gating */
- ALX_MEM_W32(adpt, ALX_CLK_GATE, ALX_CLK_GATE_ALL_A0);
-
- /* idle timeout to switch clk_125M */
- if (chip_rev == ALX_REV_B0) {
- ALX_MEM_W32(adpt, ALX_IDLE_DECISN_TIMER,
- ALX_IDLE_DECISN_TIMER_DEF);
- }
-
- /* stats refresh timeout */
- ALX_MEM_W32(adpt, ALX_SMB_TIMER, adpt->smb_timer * 500UL);
-
- /* intr moduration */
- ALX_MEM_R32(adpt, ALX_MASTER, &val);
- val = val | ALX_MASTER_IRQMOD2_EN |
- ALX_MASTER_IRQMOD1_EN |
- ALX_MASTER_SYSALVTIMER_EN; /* sysalive */
- ALX_MEM_W32(adpt, ALX_MASTER, val);
- ALX_MEM_W32(adpt, ALX_IRQ_MODU_TIMER,
- FIELDX(ALX_IRQ_MODU_TIMER1, adpt->imt >> 1));
- /* intr re-trig timeout */
- ALX_MEM_W32(adpt, ALX_INT_RETRIG, ALX_INT_RETRIG_TO);
- /* tpd threshold to trig int */
- ALX_MEM_W32(adpt, ALX_TINT_TPD_THRSHLD, adpt->tx_ringsz / 3);
- ALX_MEM_W32(adpt, ALX_TINT_TIMER, adpt->imt);
-
- /* mtu */
- raw_mtu = adpt->mtu + ETH_HLEN;
- ALX_MEM_W32(adpt, ALX_MTU, raw_mtu + 8); /* crc + vlan */
- if (raw_mtu > ALX_MTU_JUMBO_TH)
- adpt->rx_ctrl &= ~ALX_MAC_CTRL_FAST_PAUSE;
-
- /* txq */
- if ((raw_mtu + 8) < ALX_TXQ1_JUMBO_TSO_TH)
- val = (raw_mtu + 8 + 7) >> 3; /* 7 for QWORD align */
- else
- val = ALX_TXQ1_JUMBO_TSO_TH >> 3;
- ALX_MEM_W32(adpt, ALX_TXQ1, val | ALX_TXQ1_ERRLGPKT_DROP_EN);
- max_payload = pcie_get_readrq(adpt->pdev) >> 8;
- /*
- * if BIOS had changed the default dma read max length,
- * restore it to default value
- */
- if (max_payload < ALX_DEV_CTRL_MAXRRS_MIN)
- pcie_set_readrq(adpt->pdev, 128 << ALX_DEV_CTRL_MAXRRS_MIN);
-
- val = FIELDX(ALX_TXQ0_TPD_BURSTPREF, ALX_TXQ_TPD_BURSTPREF_DEF) |
- ALX_TXQ0_MODE_ENHANCE |
- ALX_TXQ0_LSO_8023_EN |
- ALX_TXQ0_SUPT_IPOPT |
- FIELDX(ALX_TXQ0_TXF_BURST_PREF, ALX_TXQ_TXF_BURST_PREF_DEF);
- ALX_MEM_W32(adpt, ALX_TXQ0, val);
- val = FIELDX(ALX_HQTPD_Q1_NUMPREF, ALX_TXQ_TPD_BURSTPREF_DEF) |
- FIELDX(ALX_HQTPD_Q2_NUMPREF, ALX_TXQ_TPD_BURSTPREF_DEF) |
- FIELDX(ALX_HQTPD_Q3_NUMPREF, ALX_TXQ_TPD_BURSTPREF_DEF) |
- ALX_HQTPD_BURST_EN;
- ALX_MEM_W32(adpt, ALX_HQTPD, val);
-
- /* rxq, flow control */
- ALX_MEM_R32(adpt, ALX_SRAM5, &val);
- val = FIELD_GETX(val, ALX_SRAM_RXF_LEN) << 3; /* bytes */
- if (val > ALX_SRAM_RXF_LEN_8K) {
- val16 = ALX_MTU_STD_ALGN >> 3;
- val = (val - ALX_RXQ2_RXF_FLOW_CTRL_RSVD) >> 3;
- } else {
- val16 = ALX_MTU_STD_ALGN >> 3;
- val = (val - ALX_MTU_STD_ALGN) >> 3;
- }
- ALX_MEM_W32(adpt, ALX_RXQ2,
- FIELDX(ALX_RXQ2_RXF_XOFF_THRESH, val16) |
- FIELDX(ALX_RXQ2_RXF_XON_THRESH, val));
- val = FIELDX(ALX_RXQ0_NUM_RFD_PREF, ALX_RXQ0_NUM_RFD_PREF_DEF) |
- FIELDX(ALX_RXQ0_RSS_MODE, ALX_RXQ0_RSS_MODE_DIS) |
- FIELDX(ALX_RXQ0_IDT_TBL_SIZE, ALX_RXQ0_IDT_TBL_SIZE_DEF) |
- ALX_RXQ0_RSS_HSTYP_ALL |
- ALX_RXQ0_RSS_HASH_EN |
- ALX_RXQ0_IPV6_PARSE_EN;
- if (ALX_FLAG(adpt, CAP_GIGA)) {
- FIELD_SET32(val, ALX_RXQ0_ASPM_THRESH,
- ALX_RXQ0_ASPM_THRESH_100M);
- }
- ALX_MEM_W32(adpt, ALX_RXQ0, val);
-
- /* DMA */
- ALX_MEM_R32(adpt, ALX_DMA, &val);
- val = FIELDX(ALX_DMA_RORDER_MODE, ALX_DMA_RORDER_MODE_OUT) |
- ALX_DMA_RREQ_PRI_DATA |
- FIELDX(ALX_DMA_RREQ_BLEN, max_payload) |
- FIELDX(ALX_DMA_WDLY_CNT, ALX_DMA_WDLY_CNT_DEF) |
- FIELDX(ALX_DMA_RDLY_CNT, ALX_DMA_RDLY_CNT_DEF) |
- FIELDX(ALX_DMA_RCHNL_SEL, adpt->dma_chnl - 1);
- ALX_MEM_W32(adpt, ALX_DMA, val);
-
- /* multi-tx-q weight */
- if (ALX_FLAG(adpt, CAP_MTQ)) {
- val = FIELDX(ALX_WRR_PRI, adpt->wrr_ctrl) |
- FIELDX(ALX_WRR_PRI0, adpt->wrr[0]) |
- FIELDX(ALX_WRR_PRI1, adpt->wrr[1]) |
- FIELDX(ALX_WRR_PRI2, adpt->wrr[2]) |
- FIELDX(ALX_WRR_PRI3, adpt->wrr[3]);
- ALX_MEM_W32(adpt, ALX_WRR, val);
- }
-
- /* multi-rx-q */
- __alx_configure_rss(adpt);
-
- /* rx mode */
+ alx_configure_basic(hw);
+ alx_configure_rss(hw, adpt->nr_rxq > 1);
__alx_set_rx_mode(adpt->netdev);
+ alx_set_vlan_mode(hw, adpt->netdev->features);
+}
+
+static void alx_netif_stop(struct alx_adapter *adpt)
+{
+ int i;
+
+ adpt->netdev->trans_start = jiffies;
+ netif_carrier_off(adpt->netdev);
+ netif_tx_disable(adpt->netdev);
+ for (i = 0; i < adpt->nr_napi; i++)
+ napi_disable(&adpt->qnapi[i]->napi);
+}
+
+static void alx_netif_start(struct alx_adapter *adpt)
+{
+ int i;
+
+ netif_tx_wake_all_queues(adpt->netdev);
+ for (i = 0; i < adpt->nr_napi; i++)
+ napi_enable(&adpt->qnapi[i]->napi);
+ netif_carrier_on(adpt->netdev);
}
static int __alx_open(struct alx_adapter *adpt)
{
- int i, err;
+ int err;
netif_carrier_off(adpt->netdev);
@@ -1343,11 +1245,8 @@ static int __alx_open(struct alx_adapter *adpt)
ALX_FLAG_CLEAR(adpt, HALT);
- for (i = 0; i < adpt->nr_napi; i++)
- napi_enable(&(adpt->qnapi[i]->napi));
-
/* clear old interrupts */
- ALX_MEM_W32(adpt, ALX_ISR, (u32)~ALX_ISR_DIS);
+ ALX_MEM_W32(&adpt->hw, ALX_ISR, (u32)~ALX_ISR_DIS);
alx_irq_enable(adpt);
@@ -1366,50 +1265,31 @@ err_out:
static void alx_halt(struct alx_adapter *adpt)
{
- struct net_device *netdev = adpt->netdev;
- int i;
+ struct alx_hw *hw = &adpt->hw;
ALX_FLAG_SET(adpt, HALT);
-
alx_cancel_work(adpt);
- /* stop TX/RX */
- alx_stop_mac(adpt);
- /* disable L0S/L1 */
- alx_enable_aspm(adpt, false, false);
-
- netif_carrier_off(netdev);
- for (i = 0; i < adpt->nr_napi; i++)
- napi_disable(&(adpt->qnapi[i]->napi));
-
- netif_tx_disable(netdev);
+ alx_netif_stop(adpt);
+ alx_reset_mac(hw);
+ /* disable l0s/l1 */
+ alx_enable_aspm(hw, false, false);
alx_irq_disable(adpt);
-
alx_free_all_rings_buf(adpt);
}
static void alx_activate(struct alx_adapter *adpt)
{
- int i;
-
- for (i = 0; i < adpt->nr_rxq; i++)
- alx_alloc_rxring_buf(adpt, adpt->qnapi[i]->rxq);
-
/* hardware setting lost, restore it */
+ alx_reinit_rings(adpt);
alx_configure(adpt);
ALX_FLAG_CLEAR(adpt, HALT);
-
- for (i = 0; i < adpt->nr_napi; i++)
- napi_enable(&(adpt->qnapi[i]->napi));
-
/* clear old interrupts */
- ALX_MEM_W32(adpt, ALX_ISR, (u32)~ALX_ISR_DIS);
+ ALX_MEM_W32(&adpt->hw, ALX_ISR, (u32)~ALX_ISR_DIS);
alx_irq_enable(adpt);
- netif_tx_wake_all_queues(adpt->netdev);
-
ALX_FLAG_SET(adpt, TASK_CHK_LINK);
alx_schedule_work(adpt);
}
@@ -1435,16 +1315,17 @@ static bool alx_enable_msix(struct alx_adapter *adpt)
vec_req = max_t(int, nr_txq, nr_rxq) + 1;
if (vec_req <= 2) {
- netdev_info(adpt->netdev,
- "cpu core num is less, MSI-X isn't necessary\n");
- return false; /* try msi */
+ netif_info(adpt, intr, adpt->netdev,
+ "cpu core num is less, MSI-X isn't necessary\n");
+ return false;
}
adpt->msix_ent = kcalloc(vec_req,
sizeof(struct msix_entry),
GFP_KERNEL);
if (!adpt->msix_ent) {
- netdev_info(adpt->netdev, "can't alloc msix entries\n");
+ netif_warn(adpt, intr, adpt->netdev,
+ "can't alloc msix entries\n");
return false;
}
for (i = 0; i < vec_req; i++)
@@ -1454,7 +1335,8 @@ static bool alx_enable_msix(struct alx_adapter *adpt)
if (err) {
kfree(adpt->msix_ent);
adpt->msix_ent = NULL;
- netdev_info(adpt->netdev, "can't enable MSI-X interrupt\n");
+ netif_warn(adpt, intr, adpt->netdev,
+ "can't enable MSI-X interrupt\n");
return false;
}
@@ -1462,31 +1344,38 @@ static bool alx_enable_msix(struct alx_adapter *adpt)
adpt->nr_rxq = nr_rxq;
adpt->nr_vec = vec_req;
adpt->nr_napi = vec_req - 1;
+ adpt->nr_hwrxq = ALX_CAP(&adpt->hw, MRQ) ? adpt->nr_rxq : 1;
return true;
}
static void alx_init_intr(struct alx_adapter *adpt)
{
- if ((ALX_FLAG(adpt, CAP_MTQ) || ALX_FLAG(adpt, CAP_RSS)) &&
- ALX_FLAG(adpt, CAP_MSIX)) {
+ struct alx_hw *hw = &adpt->hw;
+
+ if ((ALX_CAP(hw, MTQ) || ALX_CAP(hw, RSS)) && ALX_CAP(hw, MSIX)) {
if (alx_enable_msix(adpt))
ALX_FLAG_SET(adpt, USING_MSIX);
}
if (!ALX_FLAG(adpt, USING_MSIX)) {
- adpt->nr_txq = ALX_FLAG(adpt, CAP_MTQ) ?
- ALX_MAX_TX_QUEUES : 1;
+ adpt->nr_txq = ALX_CAP(hw, MTQ) ? ALX_MAX_TX_QUEUES : 1;
adpt->nr_rxq = 1;
adpt->nr_napi = 1;
adpt->nr_vec = 1;
+ adpt->nr_hwrxq = 1;
+
+ if (!pci_enable_msi(adpt->pdev))
+ ALX_FLAG_SET(adpt, USING_MSI);
}
netif_set_real_num_tx_queues(adpt->netdev, adpt->nr_txq);
netif_set_real_num_rx_queues(adpt->netdev, adpt->nr_rxq);
+
}
static void alx_init_ring_ptrs(struct alx_adapter *adpt)
{
+ struct alx_hw *hw = &adpt->hw;
struct alx_napi *np;
int i, tx_idx, rx_idx;
u32 addr_hi;
@@ -1503,10 +1392,10 @@ static void alx_init_ring_ptrs(struct alx_adapter *adpt)
np->rxq->pidx = 0;
np->rxq->cidx = 0;
np->rxq->rrd_cidx = 0;
- if (!ALX_FLAG(adpt, CAP_MRQ) && rx_idx == 0) {
- ALX_MEM_W32(adpt, rfdring_header_reg[0],
+ if (!ALX_CAP(hw, MRQ) && rx_idx == 0) {
+ ALX_MEM_W32(hw, rfdring_header_reg[0],
np->rxq->rfd_dma);
- ALX_MEM_W32(adpt, rrdring_header_reg[0],
+ ALX_MEM_W32(hw, rrdring_header_reg[0],
np->rxq->rrd_dma);
}
rx_idx++;
@@ -1514,24 +1403,25 @@ static void alx_init_ring_ptrs(struct alx_adapter *adpt)
if (np->txq) {
np->txq->pidx = 0;
atomic_set(&np->txq->cidx, 0);
- ALX_MEM_W32(adpt, txring_header_reg[tx_idx],
+ ALX_MEM_W32(hw, txring_header_reg[tx_idx],
np->txq->tpd_dma);
tx_idx++;
}
}
addr_hi = ((u64)adpt->ring_header.dma) >> 32;
- ALX_MEM_W32(adpt, ALX_TX_BASE_ADDR_HI, addr_hi);
- ALX_MEM_W32(adpt, ALX_RX_BASE_ADDR_HI, addr_hi);
- ALX_MEM_W32(adpt, ALX_TPD_RING_SZ, adpt->tx_ringsz);
- ALX_MEM_W32(adpt, ALX_RRD_RING_SZ, adpt->rx_ringsz);
- ALX_MEM_W32(adpt, ALX_RFD_RING_SZ, adpt->rx_ringsz);
+ ALX_MEM_W32(hw, ALX_TX_BASE_ADDR_HI, addr_hi);
+ ALX_MEM_W32(hw, ALX_RX_BASE_ADDR_HI, addr_hi);
+ ALX_MEM_W32(hw, ALX_TPD_RING_SZ, adpt->tx_ringsz);
+ ALX_MEM_W32(hw, ALX_RRD_RING_SZ, adpt->rx_ringsz);
+ ALX_MEM_W32(hw, ALX_RFD_RING_SZ, adpt->rx_ringsz);
+ ALX_MEM_W32(hw, ALX_RFD_BUF_SZ, adpt->rxbuf_size);
/* load these ptrs into chip internal */
- ALX_MEM_W32(adpt, ALX_SRAM9, ALX_SRAM_LOAD_PTR);
+ ALX_MEM_W32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR);
}
-static void alx_show_speed(struct net_device *dev, u16 speed)
+static void alx_show_speed(struct alx_adapter *adpt, u16 speed)
{
char *desc;
@@ -1546,70 +1436,115 @@ static void alx_show_speed(struct net_device *dev, u16 speed)
speed == SPEED_10 + HALF_DUPLEX ?
"10 Mbps Duplex Half" :
"Unknown speed";
- netdev_info(dev, "NIC Link Up: %s\n", desc);
+ netif_info(adpt, link, adpt->netdev,
+ "NIC Link Up: %s\n",
+ desc);
+}
+
+static int alx_reinit_rings(struct alx_adapter *adpt)
+{
+ int i, err = 0;
+
+ alx_free_all_rings_buf(adpt);
+
+ /* set rings' header to HW register */
+ alx_init_ring_ptrs(adpt);
+
+ /* alloc hw-rxing buf */
+ for (i = 0; i < adpt->nr_hwrxq; i++) {
+ int count;
+
+ count = alx_alloc_rxring_buf(adpt, adpt->qnapi[i]->rxq);
+ if (unlikely(!count)) {
+ err = -ENOMEM;
+ break;
+ }
+ }
+
+ return err;
}
+
+
static void alx_check_link(struct alx_adapter *adpt)
{
+ struct alx_hw *hw = &adpt->hw;
u16 speed, old_speed;
- bool link_up;
- int i, err;
+ bool link_up, old_link_up;
+ int err;
if (ALX_FLAG(adpt, HALT))
return;
- err = alx_get_phy_link(adpt, &link_up, &speed);
+ /* clear PHY internal interrupt status,
+ * otherwise the Main interrupt status will be asserted
+ * for ever.
+ */
+ alx_clear_phy_intr(hw);
+
+ err = alx_get_phy_link(hw, &link_up, &speed);
if (err)
goto out;
/* open interrutp mask */
- adpt->imask |= ALX_ISR_PHY;
- ALX_MEM_W32(adpt, ALX_IMR, adpt->imask);
+ hw->imask |= ALX_ISR_PHY;
+ ALX_MEM_W32(hw, ALX_IMR, hw->imask);
- if (!link_up && !adpt->link_up)
+ if (!link_up && !hw->link_up)
goto out;
- old_speed = adpt->link_speed + adpt->link_duplex;
+ old_speed = hw->link_speed + hw->link_duplex;
+ old_link_up = hw->link_up;
if (link_up) {
- if (adpt->link_up && old_speed == speed)
- goto out; /* same speed */
-
- alx_show_speed(adpt->netdev, speed);
- adpt->link_duplex = speed % 10;
- adpt->link_speed = speed - adpt->link_duplex;
- adpt->link_up = true;
- alx_post_phy_link(adpt, adpt->link_speed,
- ALX_FLAG(adpt, CAP_AZ));
-
- alx_enable_aspm(adpt, ALX_FLAG(adpt, CAP_L0S),
- ALX_FLAG(adpt, CAP_L1));
- alx_start_mac(adpt);
+ /* same speed ? */
+ if (old_link_up && old_speed == speed)
+ goto out;
+
+ alx_show_speed(adpt, speed);
+ hw->link_duplex = speed % 10;
+ hw->link_speed = speed - hw->link_duplex;
+ hw->link_up = true;
+ alx_post_phy_link(hw, hw->link_speed, ALX_CAP(hw, AZ));
+ alx_enable_aspm(hw, ALX_CAP(hw, L0S), ALX_CAP(hw, L1));
+ alx_start_mac(hw);
+
/* link kept, just speed changed */
- if (adpt->link_up)
+ if (old_link_up)
goto out;
/* link changed from 'down' to 'up' */
- netif_tx_wake_all_queues(adpt->netdev);
- netif_carrier_on(adpt->netdev);
+ alx_netif_start(adpt);
goto out;
}
/* link changed from 'up' to 'down' */
- netif_carrier_off(adpt->netdev);
- adpt->link_up = false;
- adpt->link_speed = SPEED_0;
- netdev_info(adpt->netdev, "NIC Link Down\n");
-
- alx_stop_mac(adpt);
- alx_enable_aspm(adpt, false, ALX_FLAG(adpt, CAP_L1));
- alx_post_phy_link(adpt, SPEED_0, ALX_FLAG(adpt, CAP_AZ));
+ alx_netif_stop(adpt);
+ hw->link_up = false;
+ hw->link_speed = SPEED_0;
+ netif_info(adpt, link, adpt->netdev, "NIC Link Down\n");
+ err = alx_reset_mac(hw);
+ if (err) {
+ netif_err(adpt, hw, adpt->netdev,
+ "linkdown:reset_mac fail %d\n", err);
+ err = -EIO;
+ goto out;
+ }
+ alx_irq_disable(adpt);
- /* free any pending tx skbs */
- netif_tx_disable(adpt->netdev);
- for (i = 0; i < adpt->nr_txq; i++)
- alx_free_txring_buf(adpt->qnapi[i]->txq);
+ /* reset-mac cause all settings on HW lost,
+ * following steps restore all of them and
+ * refresh whole RX/TX rings
+ */
+ err = alx_reinit_rings(adpt);
+ if (err)
+ goto out;
+ alx_configure(adpt);
+ alx_enable_aspm(hw, false, ALX_CAP(hw, L1));
+ alx_post_phy_link(hw, SPEED_0, ALX_CAP(hw, AZ));
+ alx_irq_enable(adpt);
out:
+
if (err) {
ALX_FLAG_SET(adpt, TASK_RESET);
alx_schedule_work(adpt);
@@ -1622,6 +1557,10 @@ static int alx_open(struct net_device *netdev)
struct alx_adapter *adpt = netdev_priv(netdev);
int err;
+ /* during diag running, disallow open */
+ if (ALX_FLAG(adpt, TESTING))
+ return -EBUSY;
+
/* decide interrupt mode, some resources allocation depend on it */
alx_init_intr(adpt);
@@ -1640,80 +1579,18 @@ static int alx_stop(struct net_device *netdev)
WARN_ON(ALX_FLAG(adpt, RESETING));
+ netif_info(adpt, ifdown, adpt->netdev, "alx_stop\n");
+
__alx_stop(adpt);
return 0;
}
-static int alx_select_powersaving_speed(struct alx_adapter *adpt, u16 *speed)
-{
- int i, err;
- u16 spd, lpa;
- bool linkup;
-
- err = alx_get_phy_link(adpt, &linkup, &spd);
- if (err)
- goto out;
-
- if (!linkup) {
- *speed = SPEED_0;
- goto out;
- }
-
- err = alx_read_phy_reg(adpt, MII_LPA, &lpa);
- if (err)
- goto out;
-
- if (!(lpa & LPA_LPACK)) { /* force mode */
- *speed = spd;
- goto out;
- }
- if (lpa & LPA_100FULL)
- *speed = SPEED_100 + FULL_DUPLEX;
- else if (lpa & LPA_100HALF)
- *speed = SPEED_100 + HALF_DUPLEX;
- else if (lpa & LPA_10FULL)
- *speed = SPEED_10 + FULL_DUPLEX;
- else
- *speed = SPEED_10 + HALF_DUPLEX;
-
- if (*speed != spd) { /* restart PHY link phase */
-
- err = alx_setup_speed_duplex(adpt,
- ALX_SPEED_TO_ETHADV(*speed) | ADVERTISED_Autoneg,
- ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX);
- if (err)
- goto out;
-
- /* wait for linkup */
- for (i = 0; i < ALX_MAX_SETUP_LNK_CYCLE; i++) {
- u16 speed2;
- bool link_on;
-
- msleep(100);
- err = alx_get_phy_link(adpt, &link_on, &speed2);
- if (err)
- goto out;
- if (link_on)
- break;
- }
- if (i == ALX_MAX_SETUP_LNK_CYCLE) {
- netdev_err(adpt->netdev,
- "config PHY speed/duplex failed,err=%d\n",
- err);
- err = -EIO;
- goto out;
- }
- }
-
-out:
- return err;
-}
-
static int __alx_shutdown(struct pci_dev *pdev, bool *wol_en)
{
struct alx_adapter *adpt = pci_get_drvdata(pdev);
struct net_device *netdev = adpt->netdev;
+ struct alx_hw *hw = &adpt->hw;
int err;
u16 speed;
@@ -1727,18 +1604,18 @@ static int __alx_shutdown(struct pci_dev *pdev, bool *wol_en)
goto out;
#endif
- err = alx_select_powersaving_speed(adpt, &speed);
+ err = alx_select_powersaving_speed(hw, &speed);
if (!err)
- err = alx_clear_phy_intr(adpt);
+ err = alx_clear_phy_intr(hw);
if (!err)
- err = alx_config_wol(adpt);
+ err = alx_config_wol(hw);
if (!err)
- err = alx_pre_suspend(adpt, speed);
+ err = alx_pre_suspend(hw, speed);
if (err)
goto out;
*wol_en = false;
- if (adpt->sleep_ctrl & ALX_SLEEP_ACTIVE) {
+ if (hw->sleep_ctrl & ALX_SLEEP_ACTIVE) {
device_set_wakeup_enable(&pdev->dev, true);
*wol_en = true;
}
@@ -1746,6 +1623,13 @@ static int __alx_shutdown(struct pci_dev *pdev, bool *wol_en)
pci_disable_device(pdev);
out:
+ if (unlikely(err)) {
+ netif_info(adpt, hw, netdev,
+ "shutown err(%x)\n",
+ err);
+ err = -EIO;
+ }
+
return err;
}
@@ -1774,6 +1658,7 @@ static int alx_suspend(struct device *dev)
err = __alx_shutdown(pdev, &wol_en);
if (unlikely(err)) {
dev_err(&pdev->dev, "shutdown fail in suspend %d\n", err);
+ err = -EIO;
goto out;
}
if (wol_en) {
@@ -1792,6 +1677,7 @@ static int alx_resume(struct device *dev)
struct pci_dev *pdev = to_pci_dev(dev);
struct alx_adapter *adpt = pci_get_drvdata(pdev);
struct net_device *netdev = adpt->netdev;
+ struct alx_hw *hw = &adpt->hw;
int err;
if (!netif_running(netdev))
@@ -1804,22 +1690,24 @@ static int alx_resume(struct device *dev)
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3cold, 0);
- adpt->link_up = false;
- adpt->link_speed = SPEED_0;
+ hw->link_up = false;
+ hw->link_speed = SPEED_0;
- alx_reset_pcie(adpt);
- alx_reset_phy(adpt, !adpt->hib_patch);
- err = alx_reset_mac(adpt);
+ alx_reset_pcie(hw);
+ alx_reset_phy(hw, !hw->hib_patch);
+ err = alx_reset_mac(hw);
if (err) {
- dev_err(&pdev->dev, "resume:reset_mac fail %d\n", err);
- return err;
+ netif_err(adpt, hw, adpt->netdev,
+ "resume:reset_mac fail %d\n",
+ err);
+ return -EIO;
}
- err = alx_setup_speed_duplex(adpt, adpt->adv_cfg, adpt->flowctrl);
+ err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl);
if (err) {
- dev_err(&pdev->dev ,
- "resume:setup_speed_duplex fail %d\n",
- err);
- return err;
+ netif_err(adpt, hw, adpt->netdev,
+ "resume:setup_speed_duplex fail %d\n",
+ err);
+ return -EIO;
}
if (netif_running(netdev)) {
@@ -1839,30 +1727,10 @@ static int alx_resume(struct device *dev)
/* alx_update_hw_stats - Update the board statistics counters. */
static void alx_update_hw_stats(struct alx_adapter *adpt)
{
- u16 reg;
- u32 data;
- unsigned long *p;
-
if (ALX_FLAG(adpt, HALT) || ALX_FLAG(adpt, RESETING))
return;
- /* RX stats */
- reg = ALX_RX_STATS_BIN;
- p = &adpt->hw_stats.rx_ok;
- while (reg <= ALX_RX_STATS_END) {
- ALX_MEM_R32(adpt, reg, &data);
- *p++ += data;
- reg += 4;
- }
-
- /* TX stats */
- reg = ALX_TX_STATS_BIN;
- p = &adpt->hw_stats.tx_ok;
- while (reg <= ALX_TX_STATS_END) {
- ALX_MEM_R32(adpt, reg, &data);
- *p++ += data;
- reg += 4;
- }
+ __alx_update_hw_stats(&adpt->hw);
}
/* alx_get_stats - Get System Network Statistics
@@ -1874,7 +1742,7 @@ static struct net_device_stats *alx_get_stats(struct net_device *netdev)
{
struct alx_adapter *adpt = netdev_priv(netdev);
struct net_device_stats *net_stats = &netdev->stats;
- struct alx_hw_stats *hw_stats = &adpt->hw_stats;
+ struct alx_hw_stats *hw_stats = &adpt->hw.stats;
spin_lock(&adpt->smb_lock);
@@ -1924,7 +1792,7 @@ void alx_reinit(struct alx_adapter *adpt)
{
WARN_ON(in_interrupt());
- while (test_and_set_bit(ALX_FLAG_RESETING, adpt->flags))
+ while (test_and_set_bit(ALX_FLAG_RESETING, &adpt->flags))
msleep(20);
if (ALX_FLAG(adpt, HALT))
@@ -1942,19 +1810,22 @@ static void alx_task(struct work_struct *work)
struct alx_adapter *adpt = container_of(work, struct alx_adapter, task);
/* don't support reentrance */
- while (test_and_set_bit(ALX_FLAG_TASK_PENDING, adpt->flags))
+ while (test_and_set_bit(ALX_FLAG_TASK_PENDING, &adpt->flags))
msleep(20);
if (ALX_FLAG(adpt, HALT))
goto out;
- if (!test_and_clear_bit(ALX_FLAG_TASK_RESET, adpt->flags))
+ if (test_and_clear_bit(ALX_FLAG_TASK_RESET, &adpt->flags)) {
+ netif_info(adpt, hw, adpt->netdev,
+ "task:alx_reinit\n");
alx_reinit(adpt);
+ }
- if (!test_and_clear_bit(ALX_FLAG_TASK_UPDATE_SMB, adpt->flags))
+ if (test_and_clear_bit(ALX_FLAG_TASK_UPDATE_SMB, &adpt->flags))
alx_update_stats(adpt);
- if (!test_and_clear_bit(ALX_FLAG_TASK_CHK_LINK, adpt->flags))
+ if (test_and_clear_bit(ALX_FLAG_TASK_CHK_LINK, &adpt->flags))
alx_check_link(adpt);
out:
@@ -1966,25 +1837,26 @@ static irqreturn_t alx_msix_ring(int irq, void *data)
{
struct alx_napi *np = data;
struct alx_adapter *adpt = np->adpt;
- u32 intr;
+ struct alx_hw *hw = &adpt->hw;
/* mask interrupt to ACK chip */
- alx_mask_msix(adpt, np->vec_idx, true);
- ALX_MEM_R32(adpt, ALX_ISR, &intr);
- intr &= ~np->vec_mask;
+ alx_mask_msix(hw, np->vec_idx, true);
+ /* clear interrutp status */
+ ALX_MEM_W32(hw, ALX_ISR, np->vec_mask);
if (!ALX_FLAG(adpt, HALT))
napi_schedule(&np->napi);
- /* clear interrutp status */
- ALX_MEM_W32(adpt, ALX_ISR, intr);
-
return IRQ_HANDLED;
}
static inline bool alx_handle_intr_misc(struct alx_adapter *adpt, u32 intr)
{
+ struct alx_hw *hw = &adpt->hw;
+
if (unlikely(intr & ALX_ISR_FATAL)) {
+ netif_info(adpt, hw, adpt->netdev,
+ "intr-fatal:%08X\n", intr);
ALX_FLAG_SET(adpt, TASK_RESET);
alx_schedule_work(adpt);
return true;
@@ -2003,8 +1875,8 @@ static inline bool alx_handle_intr_misc(struct alx_adapter *adpt, u32 intr)
* is from PHY internal. only the internal status
* is cleared, the interrupt status could be cleared.
*/
- adpt->imask &= ~ALX_ISR_PHY;
- ALX_MEM_W32(adpt, ALX_IMR, adpt->imask);
+ hw->imask &= ~ALX_ISR_PHY;
+ ALX_MEM_W32(hw, ALX_IMR, hw->imask);
ALX_FLAG_SET(adpt, TASK_CHK_LINK);
alx_schedule_work(adpt);
}
@@ -2015,33 +1887,39 @@ static inline bool alx_handle_intr_misc(struct alx_adapter *adpt, u32 intr)
static irqreturn_t alx_intr_msix_misc(int irq, void *data)
{
struct alx_adapter *adpt = data;
+ struct alx_hw *hw = &adpt->hw;
u32 intr;
/* mask interrupt to ACK chip */
- alx_mask_msix(adpt, 0, true);
+ alx_mask_msix(hw, 0, true);
/* read interrupt status */
- ALX_MEM_R32(adpt, ALX_ISR, &intr);
- intr &= (adpt->imask & ~ALX_ISR_ALL_QUEUES);
+ ALX_MEM_R32(hw, ALX_ISR, &intr);
+ intr &= (hw->imask & ~ALX_ISR_ALL_QUEUES);
if (alx_handle_intr_misc(adpt, intr))
return IRQ_HANDLED;
/* clear interrupt status */
- ALX_MEM_W32(adpt, ALX_ISR, intr);
+ ALX_MEM_W32(hw, ALX_ISR, intr);
/* enable interrupt again */
if (!ALX_FLAG(adpt, HALT))
- alx_mask_msix(adpt, 0, false);
+ alx_mask_msix(hw, 0, false);
return IRQ_HANDLED;
}
static inline irqreturn_t alx_intr_1(struct alx_adapter *adpt, u32 intr)
{
+ struct alx_hw *hw = &adpt->hw;
+
/* ACK interrupt */
- ALX_MEM_W32(adpt, ALX_ISR, ALX_ISR_DIS);
- intr &= adpt->imask;
+ netif_info(adpt, intr, adpt->netdev,
+ "ACK interrupt: 0x%lx\n",
+ intr | ALX_ISR_DIS);
+ ALX_MEM_W32(hw, ALX_ISR, intr | ALX_ISR_DIS);
+ intr &= hw->imask;
if (alx_handle_intr_misc(adpt, intr))
return IRQ_HANDLED;
@@ -2049,11 +1927,11 @@ static inline irqreturn_t alx_intr_1(struct alx_adapter *adpt, u32 intr)
if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) {
napi_schedule(&adpt->qnapi[0]->napi);
/* mask rx/tx interrupt, enable them when napi complete */
- ALX_MEM_W32(adpt, ALX_IMR, adpt->imask & ~ALX_ISR_ALL_QUEUES);
+ hw->imask &= ~ALX_ISR_ALL_QUEUES;
+ ALX_MEM_W32(hw, ALX_IMR, hw->imask);
}
- /* clear interrupt status */
- ALX_MEM_W32(adpt, ALX_ISR, intr & ~ALX_ISR_DIS);
+ ALX_MEM_W32(hw, ALX_ISR, 0);
return IRQ_HANDLED;
}
@@ -2065,7 +1943,7 @@ static irqreturn_t alx_intr_msi(int irq, void *data)
u32 intr;
/* read interrupt status */
- ALX_MEM_R32(adpt, ALX_ISR, &intr);
+ ALX_MEM_R32(&adpt->hw, ALX_ISR, &intr);
return alx_intr_1(adpt, intr);
}
@@ -2073,12 +1951,21 @@ static irqreturn_t alx_intr_msi(int irq, void *data)
static irqreturn_t alx_intr_legacy(int irq, void *data)
{
struct alx_adapter *adpt = data;
+ struct alx_hw *hw = &adpt->hw;
u32 intr;
/* read interrupt status */
- ALX_MEM_R32(adpt, ALX_ISR, &intr);
- if (intr & ALX_ISR_DIS || 0 == (intr & adpt->imask))
+ ALX_MEM_R32(hw, ALX_ISR, &intr);
+ if (intr & ALX_ISR_DIS || 0 == (intr & hw->imask)) {
+ u32 mask;
+
+ ALX_MEM_R32(hw, ALX_IMR, &mask);
+ netif_info(adpt, intr, adpt->netdev,
+ "seems a wild interrupt, intr=%X, imask=%X, %X\n",
+ intr, hw->imask, mask);
+
return IRQ_NONE;
+ }
return alx_intr_1(adpt, intr);
}
@@ -2090,6 +1977,10 @@ static int alx_poll(struct napi_struct *napi, int budget)
struct alx_adapter *adpt = np->adpt;
bool complete = true;
+ netif_info(adpt, intr, adpt->netdev,
+ "alx_poll, budget(%d)\n",
+ budget);
+
if (np->txq)
complete = alx_clean_tx_irq(np->txq);
if (np->rxq)
@@ -2103,11 +1994,16 @@ static int alx_poll(struct napi_struct *napi, int budget)
/* enable interrupt */
if (!ALX_FLAG(adpt, HALT)) {
+ struct alx_hw *hw = &adpt->hw;
+
if (ALX_FLAG(adpt, USING_MSIX))
- alx_mask_msix(adpt, np->vec_idx, false);
- else
- ALX_MEM_W32(adpt, ALX_IMR, adpt->imask);
- ALX_MEM_FLUSH(adpt);
+ alx_mask_msix(hw, np->vec_idx, false);
+ else {
+ /* TODO: need irq spinlock for imask ?? */
+ hw->imask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
+ ALX_MEM_W32(hw, ALX_IMR, hw->imask);
+ }
+ ALX_MEM_FLUSH(hw);
}
return 0;
@@ -2136,6 +2032,12 @@ static inline int alx_tpd_req(struct sk_buff *skb)
return num;
}
+/* get custom checksum offload params
+ * return val:
+ * neg-val: drop this skb
+ * 0: no custom checksum offload
+ * pos-val: have custom cksum offload
+ */
static int alx_tx_csum(struct sk_buff *skb, struct tpd_desc *first)
{
u8 cso, css;
@@ -2145,7 +2047,7 @@ static int alx_tx_csum(struct sk_buff *skb, struct tpd_desc *first)
cso = skb_checksum_start_offset(skb);
if (cso & 0x1)
- return -1; /* drop it */
+ return -1;
css = cso + skb->csum_offset;
first->word1 |= FIELDX(TPD_CXSUMSTART, cso >> 1);
@@ -2160,7 +2062,8 @@ static int alx_tso(struct sk_buff *skb, struct tpd_desc *first)
int hdr_len;
int err;
- if (!skb_is_gso(skb))
+ if (skb->ip_summed != CHECKSUM_PARTIAL ||
+ !skb_is_gso(skb))
return 0;
if (skb_header_cloned(skb)) {
@@ -2251,7 +2154,7 @@ static int alx_tx_map(struct alx_tx_queue *txq, struct sk_buff *skb)
dma_unmap_addr_set(buf, dma, dma);
tpd->adrl.addr = cpu_to_le64(dma);
- tpd->word0 |= FIELDX(TPD_BUFLEN, maplen);
+ FIELD_SET32(tpd->word0, TPD_BUFLEN, maplen);
for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
struct skb_frag_struct *frag;
@@ -2272,7 +2175,7 @@ static int alx_tx_map(struct alx_tx_queue *txq, struct sk_buff *skb)
dma_unmap_addr_set(buf, dma, dma);
tpd->adrl.addr = cpu_to_le64(dma);
- tpd->word0 |= FIELDX(TPD_BUFLEN, maplen);
+ FIELD_SET32(tpd->word0, TPD_BUFLEN, maplen);
}
/* last TPD */
tpd->word1 |= 1 << TPD_EOP_SHIFT;
@@ -2303,6 +2206,7 @@ static netdev_tx_t alx_start_xmit_ring(struct alx_tx_queue *txq,
struct netdev_queue *netque;
struct tpd_desc *first;
int budget, tpdreq;
+ int do_tso;
adpt = netdev_priv(txq->netdev);
netque = netdev_get_tx_queue(txq->netdev, skb_get_queue_mapping(skb));
@@ -2326,8 +2230,8 @@ static netdev_tx_t alx_start_xmit_ring(struct alx_tx_queue *txq,
netif_tx_wake_queue(netque);
goto tx_conti;
}
- netdev_err(adpt->netdev,
- "TPD Ring is full when queue awake!\n");
+ netif_err(adpt, tx_err, adpt->netdev,
+ "TPD Ring is full when queue awake!\n");
}
return NETDEV_TX_BUSY;
}
@@ -2346,24 +2250,32 @@ tx_conti:
first->word1 |= 1 << TPD_VLTAGGED_SHIFT;
if (skb_network_offset(skb) != ETH_HLEN)
first->word1 |= 1 << TPD_ETHTYPE_SHIFT;
- if (alx_tx_csum(skb, first) < 0)
+
+ do_tso = alx_tso(skb, first);
+ if (do_tso < 0)
goto drop;
- if (alx_tso(skb, first) < 0)
+ else if (!do_tso && alx_tx_csum(skb, first) < 0)
goto drop;
+
if (alx_tx_map(txq, skb) < 0)
goto drop;
+ netdev_tx_sent_queue(netque, skb->len);
+
/* refresh produce idx on HW */
wmb();
- ALX_MEM_W16(adpt, txq->p_reg, txq->pidx);
+ ALX_MEM_W16(&adpt->hw, txq->p_reg, txq->pidx);
- netdev_info(adpt->netdev,
- "TX[Preg:%X]: producer = 0x%x, consumer = 0x%x\n",
- txq->p_reg, txq->pidx, atomic_read(&txq->cidx));
+ netif_info(adpt, tx_done, adpt->netdev,
+ "TX[Preg:%X]: producer = 0x%x, consumer = 0x%x\n",
+ txq->p_reg, txq->pidx, atomic_read(&txq->cidx));
return NETDEV_TX_OK;
drop:
+ netif_info(adpt, tx_done, adpt->netdev,
+ "tx-skb(%d) dropped\n",
+ skb->len);
memset(first, 0, sizeof(struct tpd_desc));
dev_kfree_skb(skb);
@@ -2388,12 +2300,60 @@ static netdev_tx_t alx_start_xmit(struct sk_buff *skb,
return alx_start_xmit_ring(alx_tx_queue_mapping(adpt, skb), skb);
}
+
+static void alx_dump_state(struct alx_adapter *adpt)
+{
+ struct alx_hw *hw = &adpt->hw;
+ struct alx_tx_queue *txq;
+ struct tpd_desc *tpd;
+ u16 begin, end;
+ int i;
+
+ for (i = 0; i < adpt->nr_txq; i++) {
+
+ txq = adpt->qnapi[i]->txq;
+ begin = txq->pidx >= 16 ? (txq->pidx - 16) :
+ (txq->count + txq->pidx - 16);
+ end = txq->pidx + 4;
+ if (end >= txq->count)
+ end -= txq->count;
+
+ netif_err(adpt, tx_err, adpt->netdev,
+ "-----------------TPD-ring(%d)------------------\n",
+ i);
+
+ while (begin != end) {
+ tpd = txq->tpd_hdr + begin;
+ netif_err(adpt, tx_err, adpt->netdev,
+ "%X: W0=%08X, W1=%08X, W2=%X\n",
+ begin, tpd->word0, tpd->word1,
+ tpd->adrl.l.pkt_len);
+ if (++begin >= txq->count)
+ begin = 0;
+ }
+ }
+
+ netif_err(adpt, tx_err, adpt->netdev,
+ "---------------dump registers-----------------\n");
+ end = 0x2000;
+ for (begin = 0; begin < end; begin += 16) {
+ u32 v1, v2, v3, v4;
+
+ ALX_MEM_R32(hw, begin, &v1);
+ ALX_MEM_R32(hw, begin+4, &v2);
+ ALX_MEM_R32(hw, begin+8, &v3);
+ ALX_MEM_R32(hw, begin+12, &v4);
+ netif_err(adpt, tx_err, adpt->netdev,
+ "%04X: %08X,%08X,%08X,%08X\n",
+ begin, v1, v2, v3, v4);
+ }
+}
+
static void alx_tx_timeout(struct net_device *dev)
{
struct alx_adapter *adpt = netdev_priv(dev);
- netdev_err(adpt->netdev, "tx timeout, reset\n");
- // ???? alx_dump_state(adpt);
+ alx_dump_state(adpt);
ALX_FLAG_SET(adpt, TASK_RESET);
alx_schedule_work(adpt);
@@ -2403,16 +2363,21 @@ static int alx_mdio_read(struct net_device *netdev,
int prtad, int devad, u16 addr)
{
struct alx_adapter *adpt = netdev_priv(netdev);
+ struct alx_hw *hw = &adpt->hw;
u16 val;
int err;
- if (prtad != adpt->mdio.prtad)
+ netif_dbg(adpt, hw, netdev,
+ "alx_mdio_read, prtad=%d, devad=%d, addr=%X\n",
+ prtad, devad, addr);
+
+ if (prtad != hw->mdio.prtad)
return -EINVAL;
if (devad != MDIO_DEVAD_NONE)
- err = alx_read_phy_ext(adpt, devad, addr, &val);
+ err = alx_read_phy_ext(hw, devad, addr, &val);
else
- err = alx_read_phy_reg(adpt, addr, &val);
+ err = alx_read_phy_reg(hw, addr, &val);
return err ? -EIO : val;
}
@@ -2421,15 +2386,20 @@ static int alx_mdio_write(struct net_device *netdev,
int prtad, int devad, u16 addr, u16 val)
{
struct alx_adapter *adpt = netdev_priv(netdev);
+ struct alx_hw *hw = &adpt->hw;
int err;
- if (prtad != adpt->mdio.prtad)
+ netif_dbg(adpt, hw, netdev,
+ "alx_mdio_write: prtad=%d, devad=%d, addr=%X, val=%X\n",
+ prtad, devad, addr, val);
+
+ if (prtad != hw->mdio.prtad)
return -EINVAL;
if (devad != MDIO_DEVAD_NONE)
- err = alx_write_phy_ext(adpt, devad, addr, val);
+ err = alx_write_phy_ext(hw, devad, addr, val);
else
- err = alx_write_phy_reg(adpt, addr, val);
+ err = alx_write_phy_reg(hw, addr, val);
return err ? -EIO : 0;
}
@@ -2441,7 +2411,7 @@ static int alx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
if (!netif_running(netdev))
return -EAGAIN;
- return mdio_mii_ioctl(&adpt->mdio, if_mii(ifr), cmd);
+ return mdio_mii_ioctl(&adpt->hw.mdio, if_mii(ifr), cmd);
}
#ifdef CONFIG_NET_POLL_CONTROLLER
@@ -2489,6 +2459,7 @@ alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct net_device *netdev;
struct alx_adapter *adpt = NULL;
+ struct alx_hw *hw;
bool phy_cfged;
int bars, pm_cap, err;
static int cards_found;
@@ -2506,7 +2477,7 @@ alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
*/
if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
!dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
- dev_info(&pdev->dev, "DMA to 64-BIT addresses\n");
+ dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n");
} else {
err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
if (err) {
@@ -2557,15 +2528,22 @@ alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
}
SET_NETDEV_DEV(netdev, &pdev->dev);
- pci_set_drvdata(pdev, adpt);
adpt = netdev_priv(netdev);
adpt->netdev = netdev;
adpt->pdev = pdev;
- adpt->msg_enable = 0;
+ adpt->msg_enable = NETIF_MSG_LINK |
+ NETIF_MSG_HW |
+ NETIF_MSG_IFUP |
+ NETIF_MSG_TX_ERR |
+ NETIF_MSG_RX_ERR |
+ NETIF_MSG_WOL;
adpt->bd_number = cards_found;
+ hw = &adpt->hw;
+ hw->pdev = pdev;
+ pci_set_drvdata(pdev, adpt);
- adpt->hw_addr = pci_ioremap_bar(pdev, 0);
- if (!adpt->hw_addr) {
+ hw->hw_addr = pci_ioremap_bar(pdev, 0);
+ if (!hw->hw_addr) {
dev_err(&pdev->dev, "cannot map device registers\n");
err = -EIO;
goto err_iomap;
@@ -2584,17 +2562,17 @@ alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
}
/* reset pcie */
- alx_reset_pcie(adpt);
+ alx_reset_pcie(hw);
/* check if phy already configed by ohter driver */
- phy_cfged = alx_phy_configed(adpt);
+ phy_cfged = alx_phy_configed(hw);
/* reset PHY to a known stable status */
if (!phy_cfged)
- alx_reset_phy(adpt, !adpt->hib_patch);
+ alx_reset_phy(hw, !hw->hib_patch);
/* reset mac/dma controller */
- err = alx_reset_mac(adpt);
+ err = alx_reset_mac(hw);
if (err) {
dev_err(&pdev->dev, "MAC Reset failed, error = %d\n", err);
err = -EIO;
@@ -2603,8 +2581,8 @@ alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
/* setup link to put it in a known good starting state */
if (!phy_cfged) {
- err = alx_setup_speed_duplex(adpt,
- adpt->adv_cfg, adpt->flowctrl);
+ err = alx_setup_speed_duplex(hw,
+ hw->adv_cfg, hw->flowctrl);
if (err) {
dev_err(&pdev->dev,
"config PHY speed/duplex failed,err=%d\n",
@@ -2622,25 +2600,25 @@ alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_TX;
/* read permanent mac addr from register or eFuse */
- if (alx_get_perm_macaddr(adpt, adpt->perm_addr)) {
+ if (alx_get_perm_macaddr(hw, hw->perm_addr)) {
dev_warn(&pdev->dev, "invalid perm-address, use random one\n");
eth_hw_addr_random(netdev);
- memcpy(adpt->perm_addr, netdev->dev_addr, netdev->addr_len);
+ memcpy(hw->perm_addr, netdev->dev_addr, netdev->addr_len);
}
/* using permanent address as current address */
- memcpy(adpt->mac_addr, adpt->perm_addr, ETH_ALEN);
- memcpy(netdev->dev_addr, adpt->mac_addr, ETH_ALEN);
- memcpy(netdev->perm_addr, adpt->perm_addr, ETH_ALEN);
+ memcpy(hw->mac_addr, hw->perm_addr, ETH_ALEN);
+ memcpy(netdev->dev_addr, hw->mac_addr, ETH_ALEN);
+ memcpy(netdev->perm_addr, hw->perm_addr, ETH_ALEN);
/* PHY mdio */
- adpt->mdio.prtad = MDIO_PRTAD_NONE;
- adpt->mdio.mmds = 0;
- adpt->mdio.dev = netdev;
- adpt->mdio.mode_support =
+ hw->mdio.prtad = 0;
+ hw->mdio.mmds = 0;
+ hw->mdio.dev = netdev;
+ hw->mdio.mode_support =
MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22 | MDIO_EMULATE_C22;
- adpt->mdio.mdio_read = alx_mdio_read;
- adpt->mdio.mdio_write = alx_mdio_write;
- if (!alx_get_phy_id(adpt)) {
+ hw->mdio.mdio_read = alx_mdio_read;
+ hw->mdio.mdio_write = alx_mdio_write;
+ if (!alx_get_phy_info(hw)) {
dev_err(&pdev->dev, "identify PHY failed\n");
err = -EIO;
goto err_id_phy;
@@ -2657,7 +2635,7 @@ alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
/* carrier off reporting is important to ethtool even BEFORE open */
netif_carrier_off(netdev);
- device_set_wakeup_enable(&pdev->dev, adpt->sleep_ctrl);
+ device_set_wakeup_enable(&pdev->dev, hw->sleep_ctrl);
cards_found++;
dev_info(&pdev->dev,
@@ -2671,7 +2649,7 @@ err_register_netdev:
err_setup_link:
err_rst_mac:
err_init_sw:
- iounmap(adpt->hw_addr);
+ iounmap(hw->hw_addr);
err_iomap:
free_netdev(netdev);
err_alloc_ethdev:
@@ -2688,23 +2666,28 @@ err_dma_mask:
static void __devexit alx_remove(struct pci_dev *pdev)
{
struct alx_adapter *adpt = pci_get_drvdata(pdev);
- struct net_device *netdev = adpt->netdev;
+ struct alx_hw *hw = &adpt->hw;
+ struct net_device *netdev;
+
+ if (!adpt)
+ return;
+
+ netdev = adpt->netdev;
ALX_FLAG_SET(adpt, HALT);
alx_cancel_work(adpt);
/* restore permanent mac address */
- alx_set_macaddr(adpt, adpt->perm_addr);
+ alx_set_macaddr(hw, hw->perm_addr);
unregister_netdev(netdev);
- iounmap(adpt->hw_addr);
+ iounmap(hw->hw_addr);
pci_release_selected_regions(pdev,
pci_select_bars(pdev, IORESOURCE_MEM));
-
- dev_info(&pdev->dev, "dev removed\n");
free_netdev(netdev);
pci_disable_pcie_error_reporting(pdev);
pci_disable_device(pdev);
+ pci_set_drvdata(pdev, NULL);
}
/* alx_pci_error_detected */
@@ -2735,6 +2718,7 @@ static pci_ers_result_t alx_pci_error_detected(struct pci_dev *pdev,
static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev)
{
struct alx_adapter *adpt = pci_get_drvdata(pdev);
+ struct alx_hw *hw = &adpt->hw;
pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
rtnl_lock();
@@ -2748,8 +2732,8 @@ static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev)
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3cold, 0);
- alx_reset_pcie(adpt);
- if (!alx_reset_mac(adpt))
+ alx_reset_pcie(hw);
+ if (!alx_reset_mac(hw))
rc = PCI_ERS_RESULT_RECOVERED;
out:
pci_cleanup_aer_uncorrect_error_status(pdev);
@@ -2807,7 +2791,6 @@ static int __init alx_init_module(void)
}
module_init(alx_init_module);
-
static void __exit alx_exit_module(void)
{
pci_unregister_driver(&alx_driver);
diff --git a/src/alx_reg.h b/src/alx_reg.h
new file mode 100644
index 0000000..a91d716
--- /dev/null
+++ b/src/alx_reg.h
@@ -0,0 +1,2129 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef ALX_REG_H
+#define ALX_REG_H
+
+/**********************************************************************/
+/* following registers are mapped to both pci config and memory space */
+/**********************************************************************/
+
+#define ALX_VENDOR_ID PCI_VENDOR_ID_ATTANSIC
+
+/* pci dev-ids */
+#define ALX_DEV_ID_AR8161 0x1091
+#define ALX_DEV_ID_AR8162 0x1090
+#define ALX_DEV_ID_AR8171 0x10A1
+#define ALX_DEV_ID_AR8172 0x10A0
+
+/* rev definition,
+ * bit(0): with xD support
+ * bit(1): with Card Reader function
+ * bit(7:2): real revision
+ */
+#define ALX_PCI_REVID_WTH_CR BIT(1)
+#define ALX_PCI_REVID_WTH_XD BIT(0)
+#define ALX_PCI_REVID_MASK 0x1FU
+#define ALX_PCI_REVID_SHIFT 3
+#define ALX_REV_A0 0
+#define ALX_REV_A1 1
+#define ALX_REV_B0 2
+#define ALX_REV_C0 3
+
+#define ALX_PM_CSR 0x0044
+#define ALX_PM_CSR_PME_STAT BIT(15)
+#define ALX_PM_CSR_DSCAL_MASK 0x3U
+#define ALX_PM_CSR_DSCAL_SHIFT 13
+#define ALX_PM_CSR_DSEL_MASK 0xFU
+#define ALX_PM_CSR_DSEL_SHIFT 9
+#define ALX_PM_CSR_PME_EN BIT(8)
+#define ALX_PM_CSR_PWST_MASK 0x3U
+#define ALX_PM_CSR_PWST_SHIFT 0
+
+#define ALX_DEV_CAP 0x005C
+#define ALX_DEV_CAP_SPLSL_MASK 0x3UL
+#define ALX_DEV_CAP_SPLSL_SHIFT 26
+#define ALX_DEV_CAP_SPLV_MASK 0xFFUL
+#define ALX_DEV_CAP_SPLV_SHIFT 18
+#define ALX_DEV_CAP_RBER BIT(15)
+#define ALX_DEV_CAP_PIPRS BIT(14)
+#define ALX_DEV_CAP_AIPRS BIT(13)
+#define ALX_DEV_CAP_ABPRS BIT(12)
+#define ALX_DEV_CAP_L1ACLAT_MASK 0x7UL
+#define ALX_DEV_CAP_L1ACLAT_SHIFT 9
+#define ALX_DEV_CAP_L0SACLAT_MASK 0x7UL
+#define ALX_DEV_CAP_L0SACLAT_SHIFT 6
+#define ALX_DEV_CAP_EXTAG BIT(5)
+#define ALX_DEV_CAP_PHANTOM BIT(4)
+#define ALX_DEV_CAP_MPL_MASK 0x7UL
+#define ALX_DEV_CAP_MPL_SHIFT 0
+#define ALX_DEV_CAP_MPL_128 1
+#define ALX_DEV_CAP_MPL_256 2
+#define ALX_DEV_CAP_MPL_512 3
+#define ALX_DEV_CAP_MPL_1024 4
+#define ALX_DEV_CAP_MPL_2048 5
+#define ALX_DEV_CAP_MPL_4096 6
+
+#define ALX_DEV_CTRL 0x0060
+#define ALX_DEV_CTRL_MAXRRS_MASK 0x7U
+#define ALX_DEV_CTRL_MAXRRS_SHIFT 12
+#define ALX_DEV_CTRL_MAXRRS_MIN 2
+#define ALX_DEV_CTRL_NOSNP_EN BIT(11)
+#define ALX_DEV_CTRL_AUXPWR_EN BIT(10)
+#define ALX_DEV_CTRL_PHANTOM_EN BIT(9)
+#define ALX_DEV_CTRL_EXTAG_EN BIT(8)
+#define ALX_DEV_CTRL_MPL_MASK 0x7U
+#define ALX_DEV_CTRL_MPL_SHIFT 5
+#define ALX_DEV_CTRL_RELORD_EN BIT(4)
+#define ALX_DEV_CTRL_URR_EN BIT(3)
+#define ALX_DEV_CTRL_FERR_EN BIT(2)
+#define ALX_DEV_CTRL_NFERR_EN BIT(1)
+#define ALX_DEV_CTRL_CERR_EN BIT(0)
+
+#define ALX_DEV_STAT 0x0062
+#define ALX_DEV_STAT_XS_PEND BIT(5)
+#define ALX_DEV_STAT_AUXPWR BIT(4)
+#define ALX_DEV_STAT_UR BIT(3)
+#define ALX_DEV_STAT_FERR BIT(2)
+#define ALX_DEV_STAT_NFERR BIT(1)
+#define ALX_DEV_STAT_CERR BIT(0)
+
+#define ALX_LNK_CAP 0x0064
+#define ALX_LNK_CAP_PRTNUM_MASK 0xFFUL
+#define ALX_LNK_CAP_PRTNUM_SHIFT 24
+#define ALX_LNK_CAP_CLK_PM BIT(18)
+#define ALX_LNK_CAP_L1EXTLAT_MASK 0x7UL
+#define ALX_LNK_CAP_L1EXTLAT_SHIFT 15
+#define ALX_LNK_CAP_L0SEXTLAT_MASK 0x7UL
+#define ALX_LNK_CAP_L0SEXTLAT_SHIFT 12
+#define ALX_LNK_CAP_ASPM_SUP_MASK 0x3UL
+#define ALX_LNK_CAP_ASPM_SUP_SHIFT 10
+#define ALX_LNK_CAP_ASPM_SUP_L0S 1
+#define ALX_LNK_CAP_ASPM_SUP_L0SL1 3
+#define ALX_LNK_CAP_MAX_LWH_MASK 0x3FUL
+#define ALX_LNK_CAP_MAX_LWH_SHIFT 4
+#define ALX_LNK_CAP_MAX_LSPD_MASK 0xFUL
+#define ALX_LNK_CAP_MAX_LSPD_SHIFT 0
+
+#define ALX_LNK_CTRL 0x0068
+#define ALX_LNK_CTRL_CLK_PM_EN BIT(8)
+#define ALX_LNK_CTRL_EXTSYNC BIT(7)
+#define ALX_LNK_CTRL_CMNCLK_CFG BIT(6)
+#define ALX_LNK_CTRL_RCB_128B BIT(3)
+#define ALX_LNK_CTRL_ASPM_MASK 0x3U
+#define ALX_LNK_CTRL_ASPM_SHIFT 0
+#define ALX_LNK_CTRL_ASPM_DIS 0
+#define ALX_LNK_CTRL_ASPM_ENL0S 1
+#define ALX_LNK_CTRL_ASPM_ENL1 2
+#define ALX_LNK_CTRL_ASPM_ENL0SL1 3
+
+#define ALX_LNK_STAT 0x006A
+#define ALX_LNK_STAT_SCLKCFG BIT(12)
+#define ALX_LNK_STAT_LNKTRAIN BIT(11)
+#define ALX_LNK_STAT_TRNERR BIT(10)
+#define ALX_LNK_STAT_LNKSPD_MASK 0xFU
+#define ALX_LNK_STAT_LNKSPD_SHIFT 0
+#define ALX_LNK_STAT_NEGLW_MASK 0x3FU
+#define ALX_LNK_STAT_NEGLW_SHIFT 4
+
+#define ALX_MSIX_MASK 0x0090
+#define ALX_MSIX_PENDING 0x0094
+
+#define ALX_UE_SVRT 0x010C
+#define ALX_UE_SVRT_UR BIT(20)
+#define ALX_UE_SVRT_ECRCERR BIT(19)
+#define ALX_UE_SVRT_MTLP BIT(18)
+#define ALX_UE_SVRT_RCVOVFL BIT(17)
+#define ALX_UE_SVRT_UNEXPCPL BIT(16)
+#define ALX_UE_SVRT_CPLABRT BIT(15)
+#define ALX_UE_SVRT_CPLTO BIT(14)
+#define ALX_UE_SVRT_FCPROTERR BIT(13)
+#define ALX_UE_SVRT_PTLP BIT(12)
+#define ALX_UE_SVRT_DLPROTERR BIT(4)
+#define ALX_UE_SVRT_TRNERR BIT(0)
+
+/* eeprom & flash load register */
+#define ALX_EFLD 0x0204
+#define ALX_EFLD_F_ENDADDR_MASK 0x3FFUL
+#define ALX_EFLD_F_ENDADDR_SHIFT 16
+#define ALX_EFLD_F_EXIST BIT(10)
+#define ALX_EFLD_E_EXIST BIT(9)
+#define ALX_EFLD_EXIST BIT(8)
+#define ALX_EFLD_STAT BIT(5)
+#define ALX_EFLD_IDLE BIT(4)
+#define ALX_EFLD_START BIT(0)
+
+/* eFuse load register */
+#define ALX_SLD 0x0218
+#define ALX_SLD_FREQ_MASK 0x3UL
+#define ALX_SLD_FREQ_SHIFT 24
+#define ALX_SLD_FREQ_100K 0
+#define ALX_SLD_FREQ_200K 1
+#define ALX_SLD_FREQ_300K 2
+#define ALX_SLD_FREQ_400K 3
+#define ALX_SLD_EXIST BIT(23)
+#define ALX_SLD_SLVADDR_MASK 0x7FUL
+#define ALX_SLD_SLVADDR_SHIFT 16
+#define ALX_SLD_IDLE BIT(13)
+#define ALX_SLD_STAT BIT(12)
+#define ALX_SLD_START BIT(11)
+#define ALX_SLD_STARTADDR_MASK 0xFFUL
+#define ALX_SLD_STARTADDR_SHIFT 0
+#define ALX_SLD_MAX_TO 100
+
+#define ALX_PCIE_MSIC 0x021C
+#define ALX_PCIE_MSIC_MSIX_DIS BIT(22)
+#define ALX_PCIE_MSIC_MSI_DIS BIT(21)
+
+#define ALX_PPHY_MISC1 0x1000
+#define ALX_PPHY_MISC1_RCVDET BIT(2)
+#define ALX_PPHY_MISC1_NFTS_MASK 0xFFUL
+#define ALX_PPHY_MISC1_NFTS_SHIFT 16
+#define ALX_PPHY_MISC1_NFTS_HIPERF 0xA0
+
+#define ALX_PPHY_MISC2 0x1004
+#define ALX_PPHY_MISC2_L0S_TH_MASK 0x3UL
+#define ALX_PPHY_MISC2_L0S_TH_SHIFT 18
+#define ALX_PPHY_MISC2_CDR_BW_MASK 0x3UL
+#define ALX_PPHY_MISC2_CDR_BW_SHIFT 16
+
+#define ALX_PDLL_TRNS1 0x1104
+#define ALX_PDLL_TRNS1_D3PLLOFF_EN BIT(11)
+#define ALX_PDLL_TRNS1_REGCLK_SEL_NORM BIT(10)
+#define ALX_PDLL_TRNS1_REPLY_TO_MASK 0x3FFUL
+#define ALX_PDLL_TRNS1_REPLY_TO_SHIFT 0
+
+#define ALX_TLEXTN_STATS 0x1208
+#define ALX_TLEXTN_STATS_DEVNO_MASK 0x1FUL
+#define ALX_TLEXTN_STATS_DEVNO_SHIFT 16
+#define ALX_TLEXTN_STATS_BUSNO_MASK 0xFFUL
+#define ALX_TLEXTN_STATS_BUSNO_SHIFT 8
+
+#define ALX_EFUSE_CTRL 0x12C0
+#define ALX_EFUSE_CTRL_FLAG BIT(31)
+#define ALX_EUFSE_CTRL_ACK BIT(30)
+#define ALX_EFUSE_CTRL_ADDR_MASK 0x3FFUL
+#define ALX_EFUSE_CTRL_ADDR_SHIFT 16
+
+#define ALX_EFUSE_DATA 0x12C4
+
+#define ALX_SPI_OP1 0x12C8
+#define ALX_SPI_OP1_RDID_MASK 0xFFUL
+#define ALX_SPI_OP1_RDID_SHIFT 24
+#define ALX_SPI_OP1_CE_MASK 0xFFUL
+#define ALX_SPI_OP1_CE_SHIFT 16
+#define ALX_SPI_OP1_SE_MASK 0xFFUL
+#define ALX_SPI_OP1_SE_SHIFT 8
+#define ALX_SPI_OP1_PRGRM_MASK 0xFFUL
+#define ALX_SPI_OP1_PRGRM_SHIFT 0
+
+#define ALX_SPI_OP2 0x12CC
+#define ALX_SPI_OP2_READ_MASK 0xFFUL
+#define ALX_SPI_OP2_READ_SHIFT 24
+#define ALX_SPI_OP2_WRSR_MASK 0xFFUL
+#define ALX_SPI_OP2_WRSR_SHIFT 16
+#define ALX_SPI_OP2_RDSR_MASK 0xFFUL
+#define ALX_SPI_OP2_RDSR_SHIFT 8
+#define ALX_SPI_OP2_WREN_MASK 0xFFUL
+#define ALX_SPI_OP2_WREN_SHIFT 0
+
+#define ALX_SPI_OP3 0x12E4
+#define ALX_SPI_OP3_WRDI_MASK 0xFFUL
+#define ALX_SPI_OP3_WRDI_SHIFT 8
+#define ALX_SPI_OP3_EWSR_MASK 0xFFUL
+#define ALX_SPI_OP3_EWSR_SHIFT 0
+
+#define ALX_EF_CTRL 0x12D0
+#define ALX_EF_CTRL_FSTS_MASK 0xFFUL
+#define ALX_EF_CTRL_FSTS_SHIFT 20
+#define ALX_EF_CTRL_CLASS_MASK 0x7UL
+#define ALX_EF_CTRL_CLASS_SHIFT 16
+#define ALX_EF_CTRL_CLASS_F_UNKNOWN 0
+#define ALX_EF_CTRL_CLASS_F_STD 1
+#define ALX_EF_CTRL_CLASS_F_SST 2
+#define ALX_EF_CTRL_CLASS_E_UNKNOWN 0
+#define ALX_EF_CTRL_CLASS_E_1K 1
+#define ALX_EF_CTRL_CLASS_E_4K 2
+#define ALX_EF_CTRL_FRET BIT(15)
+#define ALX_EF_CTRL_TYP_MASK 0x3UL
+#define ALX_EF_CTRL_TYP_SHIFT 12
+#define ALX_EF_CTRL_TYP_NONE 0
+#define ALX_EF_CTRL_TYP_F 1
+#define ALX_EF_CTRL_TYP_E 2
+#define ALX_EF_CTRL_TYP_UNKNOWN 3
+#define ALX_EF_CTRL_ONE_CLK BIT(10)
+#define ALX_EF_CTRL_ECLK_MASK 0x3UL
+#define ALX_EF_CTRL_ECLK_SHIFT 8
+#define ALX_EF_CTRL_ECLK_125K 0
+#define ALX_EF_CTRL_ECLK_250K 1
+#define ALX_EF_CTRL_ECLK_500K 2
+#define ALX_EF_CTRL_ECLK_1M 3
+#define ALX_EF_CTRL_FBUSY BIT(7)
+#define ALX_EF_CTRL_ACTION BIT(6)
+#define ALX_EF_CTRL_AUTO_OP BIT(5)
+#define ALX_EF_CTRL_SST_MODE BIT(4)
+#define ALX_EF_CTRL_INST_MASK 0xFUL
+#define ALX_EF_CTRL_INST_SHIFT 0
+#define ALX_EF_CTRL_INST_NONE 0
+#define ALX_EF_CTRL_INST_READ 1
+#define ALX_EF_CTRL_INST_RDID 2
+#define ALX_EF_CTRL_INST_RDSR 3
+#define ALX_EF_CTRL_INST_WREN 4
+#define ALX_EF_CTRL_INST_PRGRM 5
+#define ALX_EF_CTRL_INST_SE 6
+#define ALX_EF_CTRL_INST_CE 7
+#define ALX_EF_CTRL_INST_WRSR 10
+#define ALX_EF_CTRL_INST_EWSR 11
+#define ALX_EF_CTRL_INST_WRDI 12
+#define ALX_EF_CTRL_INST_WRITE 2
+
+#define ALX_EF_ADDR 0x12D4
+#define ALX_EF_DATA 0x12D8
+#define ALX_SPI_ID 0x12DC
+
+#define ALX_SPI_CFG_START 0x12E0
+
+#define ALX_PMCTRL 0x12F8
+#define ALX_PMCTRL_HOTRST_WTEN BIT(31)
+/* bit30: L0s/L1 controlled by MAC based on throughput(setting in 15A0) */
+#define ALX_PMCTRL_ASPM_FCEN BIT(30)
+#define ALX_PMCTRL_SADLY_EN BIT(29)
+#define ALX_PMCTRL_L0S_BUFSRX_EN BIT(28)
+#define ALX_PMCTRL_LCKDET_TIMER_MASK 0xFUL
+#define ALX_PMCTRL_LCKDET_TIMER_SHIFT 24
+#define ALX_PMCTRL_LCKDET_TIMER_DEF 0xC
+/* bit[23:20] if pm_request_l1 time > @, then enter L0s not L1 */
+#define ALX_PMCTRL_L1REQ_TO_MASK 0xFUL
+#define ALX_PMCTRL_L1REQ_TO_SHIFT 20
+#define ALX_PMCTRL_L1REG_TO_DEF 0xF
+#define ALX_PMCTRL_TXL1_AFTER_L0S BIT(19)
+#define ALX_PMCTRL_L1_TIMER_MASK 0x7UL
+#define ALX_PMCTRL_L1_TIMER_SHIFT 16
+#define ALX_PMCTRL_L1_TIMER_DIS 0
+#define ALX_PMCTRL_L1_TIMER_2US 1
+#define ALX_PMCTRL_L1_TIMER_4US 2
+#define ALX_PMCTRL_L1_TIMER_8US 3
+#define ALX_PMCTRL_L1_TIMER_16US 4
+#define ALX_PMCTRL_L1_TIMER_24US 5
+#define ALX_PMCTRL_L1_TIMER_32US 6
+#define ALX_PMCTRL_L1_TIMER_63US 7
+#define ALX_PMCTRL_RCVR_WT_1US BIT(15)
+#define ALX_PMCTRL_PWM_VER_11 BIT(14)
+/* bit13: enable pcie clk switch in L1 state */
+#define ALX_PMCTRL_L1_CLKSW_EN BIT(13)
+#define ALX_PMCTRL_L0S_EN BIT(12)
+#define ALX_PMCTRL_RXL1_AFTER_L0S BIT(11)
+#define ALX_PMCTRL_L0S_TIMER_MASK 0x7UL
+#define ALX_PMCTRL_L0S_TIMER_SHIFT 8
+#define ALX_PMCTRL_L1_BUFSRX_EN BIT(7)
+/* bit6: power down serdes RX */
+#define ALX_PMCTRL_L1_SRDSRX_PWD BIT(6)
+#define ALX_PMCTRL_L1_SRDSPLL_EN BIT(5)
+#define ALX_PMCTRL_L1_SRDS_EN BIT(4)
+#define ALX_PMCTRL_L1_EN BIT(3)
+#define ALX_PMCTRL_CLKREQ_EN BIT(2)
+#define ALX_PMCTRL_RBER_EN BIT(1)
+#define ALX_PMCTRL_SPRSDWER_EN BIT(0)
+
+#define ALX_LTSSM_CTRL 0x12FC
+#define ALX_LTSSM_WRO_EN BIT(12)
+
+/*******************************************************/
+/* following registers are mapped only to memory space */
+/*******************************************************/
+
+#define ALX_MASTER 0x1400
+#define ALX_MASTER_OTP_FLG BIT(31)
+#define ALX_MASTER_DEV_NUM_MASK 0x7FUL
+#define ALX_MASTER_DEV_NUM_SHIFT 24
+#define ALX_MASTER_REV_NUM_MASK 0xFFUL
+#define ALX_MASTER_REV_NUM_SHIFT 16
+#define ALX_MASTER_DEASSRT BIT(15)
+#define ALX_MASTER_RDCLR_INT BIT(14)
+#define ALX_MASTER_DMA_RST BIT(13)
+/* bit12: 1:alwys select pclk from serdes, not sw to 25M */
+#define ALX_MASTER_PCLKSEL_SRDS BIT(12)
+/* bit11: irq moduration for rx */
+#define ALX_MASTER_IRQMOD2_EN BIT(11)
+/* bit10: irq moduration for tx/rx */
+#define ALX_MASTER_IRQMOD1_EN BIT(10)
+#define ALX_MASTER_MANU_INT BIT(9)
+#define ALX_MASTER_MANUTIMER_EN BIT(8)
+#define ALX_MASTER_SYSALVTIMER_EN BIT(7)
+#define ALX_MASTER_OOB_DIS BIT(6)
+/* bit5: wakeup without pcie clk */
+#define ALX_MASTER_WAKEN_25M BIT(5)
+#define ALX_MASTER_BERT_START BIT(4)
+#define ALX_MASTER_PCIE_TSTMOD_MASK 0x3UL
+#define ALX_MASTER_PCIE_TSTMOD_SHIFT 2
+#define ALX_MASTER_PCIE_RST BIT(1)
+/* bit0: MAC & DMA reset */
+#define ALX_MASTER_DMA_MAC_RST BIT(0)
+#define ALX_DMA_MAC_RST_TO 50
+
+#define ALX_MANU_TIMER 0x1404
+
+#define ALX_IRQ_MODU_TIMER 0x1408
+/* hi-16bit is only for RX */
+#define ALX_IRQ_MODU_TIMER2_MASK 0xFFFFUL
+#define ALX_IRQ_MODU_TIMER2_SHIFT 16
+#define ALX_IRQ_MODU_TIMER1_MASK 0xFFFFUL
+#define ALX_IRQ_MODU_TIMER1_SHIFT 0
+
+#define ALX_PHY_CTRL 0x140C
+#define ALX_PHY_CTRL_ADDR_MASK 0x1FUL
+#define ALX_PHY_CTRL_ADDR_SHIFT 19
+#define ALX_PHY_CTRL_BP_VLTGSW BIT(18)
+#define ALX_PHY_CTRL_100AB_EN BIT(17)
+#define ALX_PHY_CTRL_10AB_EN BIT(16)
+#define ALX_PHY_CTRL_PLL_BYPASS BIT(15)
+/* bit14: affect MAC & PHY, go to low power sts */
+#define ALX_PHY_CTRL_POWER_DOWN BIT(14)
+/* bit13: 1:pll always ON, 0:can switch in lpw */
+#define ALX_PHY_CTRL_PLL_ON BIT(13)
+#define ALX_PHY_CTRL_RST_ANALOG BIT(12)
+#define ALX_PHY_CTRL_HIB_PULSE BIT(11)
+#define ALX_PHY_CTRL_HIB_EN BIT(10)
+#define ALX_PHY_CTRL_GIGA_DIS BIT(9)
+/* bit8: poweron rst */
+#define ALX_PHY_CTRL_IDDQ_DIS BIT(8)
+/* bit7: while reboot, it affects bit8 */
+#define ALX_PHY_CTRL_IDDQ BIT(7)
+#define ALX_PHY_CTRL_LPW_EXIT BIT(6)
+#define ALX_PHY_CTRL_GATE_25M BIT(5)
+#define ALX_PHY_CTRL_RVRS_ANEG BIT(4)
+#define ALX_PHY_CTRL_ANEG_NOW BIT(3)
+#define ALX_PHY_CTRL_LED_MODE BIT(2)
+#define ALX_PHY_CTRL_RTL_MODE BIT(1)
+/* bit0: out of dsp RST state */
+#define ALX_PHY_CTRL_DSPRST_OUT BIT(0)
+#define ALX_PHY_CTRL_DSPRST_TO 80
+#define ALX_PHY_CTRL_CLS (\
+ ALX_PHY_CTRL_LED_MODE |\
+ ALX_PHY_CTRL_100AB_EN |\
+ ALX_PHY_CTRL_PLL_ON)
+
+#define ALX_MAC_STS 0x1410
+#define ALX_MAC_STS_SFORCE_MASK 0xFUL
+#define ALX_MAC_STS_SFORCE_SHIFT 14
+#define ALX_MAC_STS_CALIB_DONE BIT13
+#define ALX_MAC_STS_CALIB_RES_MASK 0x1FUL
+#define ALX_MAC_STS_CALIB_RES_SHIFT 8
+#define ALX_MAC_STS_CALIBERR_MASK 0xFUL
+#define ALX_MAC_STS_CALIBERR_SHIFT 4
+#define ALX_MAC_STS_TXQ_BUSY BIT(3)
+#define ALX_MAC_STS_RXQ_BUSY BIT(2)
+#define ALX_MAC_STS_TXMAC_BUSY BIT(1)
+#define ALX_MAC_STS_RXMAC_BUSY BIT(0)
+#define ALX_MAC_STS_IDLE (\
+ ALX_MAC_STS_TXQ_BUSY |\
+ ALX_MAC_STS_RXQ_BUSY |\
+ ALX_MAC_STS_TXMAC_BUSY |\
+ ALX_MAC_STS_RXMAC_BUSY)
+
+#define ALX_MDIO 0x1414
+#define ALX_MDIO_MODE_EXT BIT(30)
+#define ALX_MDIO_POST_READ BIT(29)
+#define ALX_MDIO_AUTO_POLLING BIT(28)
+#define ALX_MDIO_BUSY BIT(27)
+#define ALX_MDIO_CLK_SEL_MASK 0x7UL
+#define ALX_MDIO_CLK_SEL_SHIFT 24
+#define ALX_MDIO_CLK_SEL_25MD4 0
+#define ALX_MDIO_CLK_SEL_25MD6 2
+#define ALX_MDIO_CLK_SEL_25MD8 3
+#define ALX_MDIO_CLK_SEL_25MD10 4
+#define ALX_MDIO_CLK_SEL_25MD32 5
+#define ALX_MDIO_CLK_SEL_25MD64 6
+#define ALX_MDIO_CLK_SEL_25MD128 7
+#define ALX_MDIO_START BIT(23)
+#define ALX_MDIO_SPRES_PRMBL BIT(22)
+/* bit21: 1:read,0:write */
+#define ALX_MDIO_OP_READ BIT(21)
+#define ALX_MDIO_REG_MASK 0x1FUL
+#define ALX_MDIO_REG_SHIFT 16
+#define ALX_MDIO_DATA_MASK 0xFFFFUL
+#define ALX_MDIO_DATA_SHIFT 0
+#define ALX_MDIO_MAX_AC_TO 120
+
+#define ALX_MDIO_EXTN 0x1448
+#define ALX_MDIO_EXTN_PORTAD_MASK 0x1FUL
+#define ALX_MDIO_EXTN_PORTAD_SHIFT 21
+#define ALX_MDIO_EXTN_DEVAD_MASK 0x1FUL
+#define ALX_MDIO_EXTN_DEVAD_SHIFT 16
+#define ALX_MDIO_EXTN_REG_MASK 0xFFFFUL
+#define ALX_MDIO_EXTN_REG_SHIFT 0
+
+#define ALX_PHY_STS 0x1418
+#define ALX_PHY_STS_LPW BIT(31)
+#define ALX_PHY_STS_LPI BIT(30)
+#define ALX_PHY_STS_PWON_STRIP_MASK 0xFFFUL
+#define ALX_PHY_STS_PWON_STRIP_SHIFT 16
+
+#define ALX_PHY_STS_DUPLEX BIT(3)
+#define ALX_PHY_STS_LINKUP BIT(2)
+#define ALX_PHY_STS_SPEED_MASK 0x3UL
+#define ALX_PHY_STS_SPEED_SHIFT 0
+#define ALX_PHY_STS_SPEED_1000M 2
+#define ALX_PHY_STS_SPEED_100M 1
+#define ALX_PHY_STS_SPEED_10M 0
+
+#define ALX_BIST0 0x141C
+#define ALX_BIST0_COL_MASK 0x3FUL
+#define ALX_BIST0_COL_SHIFT 24
+#define ALX_BIST0_ROW_MASK 0xFFFUL
+#define ALX_BIST0_ROW_SHIFT 12
+#define ALX_BIST0_STEP_MASK 0xFUL
+#define ALX_BIST0_STEP_SHIFT 8
+#define ALX_BIST0_PATTERN_MASK 0x7UL
+#define ALX_BIST0_PATTERN_SHIFT 4
+#define ALX_BIST0_CRIT BIT(3)
+#define ALX_BIST0_FIXED BIT(2)
+#define ALX_BIST0_FAIL BIT(1)
+#define ALX_BIST0_START BIT(0)
+
+#define ALX_BIST1 0x1420
+#define ALX_BIST1_COL_MASK 0x3FUL
+#define ALX_BIST1_COL_SHIFT 24
+#define ALX_BIST1_ROW_MASK 0xFFFUL
+#define ALX_BIST1_ROW_SHIFT 12
+#define ALX_BIST1_STEP_MASK 0xFUL
+#define ALX_BIST1_STEP_SHIFT 8
+#define ALX_BIST1_PATTERN_MASK 0x7UL
+#define ALX_BIST1_PATTERN_SHIFT 4
+#define ALX_BIST1_CRIT BIT(3)
+#define ALX_BIST1_FIXED BIT(2)
+#define ALX_BIST1_FAIL BIT(1)
+#define ALX_BIST1_START BIT(0)
+
+#define ALX_SERDES 0x1424
+#define ALX_SERDES_PHYCLK_SLWDWN BIT(18)
+#define ALX_SERDES_MACCLK_SLWDWN BIT(17)
+#define ALX_SERDES_SELFB_PLL_MASK 0x3UL
+#define ALX_SERDES_SELFB_PLL_SHIFT 14
+/* bit13: 1:gtx_clk, 0:25M */
+#define ALX_SERDES_PHYCLK_SEL_GTX BIT(13)
+/* bit12: 1:serdes,0:25M */
+#define ALX_SERDES_PCIECLK_SEL_SRDS BIT(12)
+#define ALX_SERDES_BUFS_RX_EN BIT(11)
+#define ALX_SERDES_PD_RX BIT(10)
+#define ALX_SERDES_PLL_EN BIT(9)
+#define ALX_SERDES_EN BIT(8)
+/* bit6: 0:state-machine,1:csr */
+#define ALX_SERDES_SELFB_PLL_SEL_CSR BIT(6)
+#define ALX_SERDES_SELFB_PLL_CSR_MASK 0x3UL
+#define ALX_SERDES_SELFB_PLL_CSR_SHIFT 4
+/* 4-12% OV-CLK */
+#define ALX_SERDES_SELFB_PLL_CSR_4 3
+/* 0-4% OV-CLK */
+#define ALX_SERDES_SELFB_PLL_CSR_0 2
+/* 12-18% OV-CLK */
+#define ALX_SERDES_SELFB_PLL_CSR_12 1
+/* 18-25% OV-CLK */
+#define ALX_SERDES_SELFB_PLL_CSR_18 0
+#define ALX_SERDES_VCO_SLOW BIT(3)
+#define ALX_SERDES_VCO_FAST BIT(2)
+#define ALX_SERDES_LOCKDCT_EN BIT(1)
+#define ALX_SERDES_LOCKDCTED BIT(0)
+
+#define ALX_LED_CTRL 0x1428
+#define ALX_LED_CTRL_PATMAP2_MASK 0x3UL
+#define ALX_LED_CTRL_PATMAP2_SHIFT 8
+#define ALX_LED_CTRL_PATMAP1_MASK 0x3UL
+#define ALX_LED_CTRL_PATMAP1_SHIFT 6
+#define ALX_LED_CTRL_PATMAP0_MASK 0x3UL
+#define ALX_LED_CTRL_PATMAP0_SHIFT 4
+#define ALX_LED_CTRL_D3_MODE_MASK 0x3UL
+#define ALX_LED_CTRL_D3_MODE_SHIFT 2
+#define ALX_LED_CTRL_D3_MODE_NORMAL 0
+#define ALX_LED_CTRL_D3_MODE_WOL_DIS 1
+#define ALX_LED_CTRL_D3_MODE_WOL_ANY 2
+#define ALX_LED_CTRL_D3_MODE_WOL_EN 3
+#define ALX_LED_CTRL_DUTY_CYCL_MASK 0x3UL
+#define ALX_LED_CTRL_DUTY_CYCL_SHIFT 0
+/* 50% */
+#define ALX_LED_CTRL_DUTY_CYCL_50 0
+/* 12.5% */
+#define ALX_LED_CTRL_DUTY_CYCL_125 1
+/* 25% */
+#define ALX_LED_CTRL_DUTY_CYCL_25 2
+/* 75% */
+#define ALX_LED_CTRL_DUTY_CYCL_75 3
+
+#define ALX_LED_PATN 0x142C
+#define ALX_LED_PATN1_MASK 0xFFFFUL
+#define ALX_LED_PATN1_SHIFT 16
+#define ALX_LED_PATN0_MASK 0xFFFFUL
+#define ALX_LED_PATN0_SHIFT 0
+
+#define ALX_LED_PATN2 0x1430
+#define ALX_LED_PATN2_MASK 0xFFFFUL
+#define ALX_LED_PATN2_SHIFT 0
+
+#define ALX_SYSALV 0x1434
+#define ALX_SYSALV_FLAG BIT(0)
+
+#define ALX_PCIERR_INST 0x1438
+#define ALX_PCIERR_INST_TX_RATE_MASK 0xFUL
+#define ALX_PCIERR_INST_TX_RATE_SHIFT 4
+#define ALX_PCIERR_INST_RX_RATE_MASK 0xFUL
+#define ALX_PCIERR_INST_RX_RATE_SHIFT 0
+
+#define ALX_LPI_DECISN_TIMER 0x143C
+
+#define ALX_LPI_CTRL 0x1440
+#define ALX_LPI_CTRL_CHK_DA BIT(31)
+#define ALX_LPI_CTRL_ENH_TO_MASK 0x1FFFUL
+#define ALX_LPI_CTRL_ENH_TO_SHIFT 12
+#define ALX_LPI_CTRL_ENH_TH_MASK 0x1FUL
+#define ALX_LPI_CTRL_ENH_TH_SHIFT 6
+#define ALX_LPI_CTRL_ENH_EN BIT(5)
+#define ALX_LPI_CTRL_CHK_RX BIT(4)
+#define ALX_LPI_CTRL_CHK_STATE BIT(3)
+#define ALX_LPI_CTRL_GMII BIT(2)
+#define ALX_LPI_CTRL_TO_PHY BIT(1)
+#define ALX_LPI_CTRL_EN BIT(0)
+
+#define ALX_LPI_WAIT 0x1444
+#define ALX_LPI_WAIT_TIMER_MASK 0xFFFFUL
+#define ALX_LPI_WAIT_TIMER_SHIFT 0
+
+/* heart-beat, for swoi/cifs */
+#define ALX_HRTBT_VLAN 0x1450
+#define ALX_HRTBT_VLANID_MASK 0xFFFFUL
+#define ALX_HRRBT_VLANID_SHIFT 0
+
+#define ALX_HRTBT_CTRL 0x1454
+#define ALX_HRTBT_CTRL_EN BIT(31)
+#define ALX_HRTBT_CTRL_PERIOD_MASK 0x3FUL
+#define ALX_HRTBT_CTRL_PERIOD_SHIFT 25
+#define ALX_HRTBT_CTRL_HASVLAN BIT(24)
+#define ALX_HRTBT_CTRL_HDRADDR_MASK 0xFFFUL
+#define ALX_HRTBT_CTRL_HDRADDR_SHIFT 12
+#define ALX_HRTBT_CTRL_HDRADDRB0_MASK 0x7FFUL
+#define ALX_HRTBT_CTRL_HDRADDRB0_SHIFT 13
+#define ALX_HRTBT_CTRL_PKT_FRAG BIT(12)
+#define ALX_HRTBT_CTRL_PKTLEN_MASK 0xFFFUL
+#define ALX_HRTBT_CTRL_PKTLEN_SHIFT 0
+
+/* for B0 */
+#define ALX_HRTBT_EXT_CTRL 0x1AD0
+#define ALX_HRTBT_EXT_CTRL_NS_EN BIT(12)
+#define ALX_HRTBT_EXT_CTRL_FRAG_LEN_MASK 0xFFUL
+#define ALX_HRTBT_EXT_CTRL_FRAG_LEN_SHIFT 4
+#define ALX_HRTBT_EXT_CTRL_IS_8023 BIT(3)
+#define ALX_HRTBT_EXT_CTRL_IS_IPV6 BIT(2)
+#define ALX_HRTBT_EXT_CTRL_WAKEUP_EN BIT(1)
+#define ALX_HRTBT_EXT_CTRL_ARP_EN BIT(0)
+
+#define ALX_HRTBT_REM_IPV4_ADDR 0x1AD4
+#define ALX_HRTBT_HOST_IPV4_ADDR 0x1478
+#define ALX_HRTBT_REM_IPV6_ADDR3 0x1AD8
+#define ALX_HRTBT_REM_IPV6_ADDR2 0x1ADC
+#define ALX_HRTBT_REM_IPV6_ADDR1 0x1AE0
+#define ALX_HRTBT_REM_IPV6_ADDR0 0x1AE4
+/*SWOI_HOST_IPV6_ADDR reuse reg1a60-1a6c, 1a70-1a7c, 1aa0-1aac, 1ab0-1abc.*/
+#define ALX_HRTBT_WAKEUP_PORT 0x1AE8
+#define ALX_HRTBT_WAKEUP_PORT_SRC_MASK 0xFFFFUL
+#define ALX_HRTBT_WAKEUP_PORT_SRC_SHIFT 16
+#define ALX_HRTBT_WAKEUP_PORT_DEST_MASK 0xFFFFUL
+#define ALX_HRTBT_WAKEUP_PORT_DEST_SHIFT 0
+
+#define ALX_HRTBT_WAKEUP_DATA7 0x1AEC
+#define ALX_HRTBT_WAKEUP_DATA6 0x1AF0
+#define ALX_HRTBT_WAKEUP_DATA5 0x1AF4
+#define ALX_HRTBT_WAKEUP_DATA4 0x1AF8
+#define ALX_HRTBT_WAKEUP_DATA3 0x1AFC
+#define ALX_HRTBT_WAKEUP_DATA2 0x1B80
+#define ALX_HRTBT_WAKEUP_DATA1 0x1B84
+#define ALX_HRTBT_WAKEUP_DATA0 0x1B88
+
+#define ALX_RXPARSE 0x1458
+#define ALX_RXPARSE_FLT6_L4_MASK 0x3UL
+#define ALX_RXPARSE_FLT6_L4_SHIFT 30
+#define ALX_RXPARSE_FLT6_L3_MASK 0x3UL
+#define ALX_RXPARSE_FLT6_L3_SHIFT 28
+#define ALX_RXPARSE_FLT5_L4_MASK 0x3UL
+#define ALX_RXPARSE_FLT5_L4_SHIFT 26
+#define ALX_RXPARSE_FLT5_L3_MASK 0x3UL
+#define ALX_RXPARSE_FLT5_L3_SHIFT 24
+#define ALX_RXPARSE_FLT4_L4_MASK 0x3UL
+#define ALX_RXPARSE_FLT4_L4_SHIFT 22
+#define ALX_RXPARSE_FLT4_L3_MASK 0x3UL
+#define ALX_RXPARSE_FLT4_L3_SHIFT 20
+#define ALX_RXPARSE_FLT3_L4_MASK 0x3UL
+#define ALX_RXPARSE_FLT3_L4_SHIFT 18
+#define ALX_RXPARSE_FLT3_L3_MASK 0x3UL
+#define ALX_RXPARSE_FLT3_L3_SHIFT 16
+#define ALX_RXPARSE_FLT2_L4_MASK 0x3UL
+#define ALX_RXPARSE_FLT2_L4_SHIFT 14
+#define ALX_RXPARSE_FLT2_L3_MASK 0x3UL
+#define ALX_RXPARSE_FLT2_L3_SHIFT 12
+#define ALX_RXPARSE_FLT1_L4_MASK 0x3UL
+#define ALX_RXPARSE_FLT1_L4_SHIFT 10
+#define ALX_RXPARSE_FLT1_L3_MASK 0x3UL
+#define ALX_RXPARSE_FLT1_L3_SHIFT 8
+#define ALX_RXPARSE_FLT6_EN BIT(5)
+#define ALX_RXPARSE_FLT5_EN BIT(4)
+#define ALX_RXPARSE_FLT4_EN BIT(3)
+#define ALX_RXPARSE_FLT3_EN BIT(2)
+#define ALX_RXPARSE_FLT2_EN BIT(1)
+#define ALX_RXPARSE_FLT1_EN BIT(0)
+#define ALX_RXPARSE_FLT_L4_UDP 0
+#define ALX_RXPARSE_FLT_L4_TCP 1
+#define ALX_RXPARSE_FLT_L4_BOTH 2
+#define ALX_RXPARSE_FLT_L4_NONE 3
+#define ALX_RXPARSE_FLT_L3_IPV6 0
+#define ALX_RXPARSE_FLT_L3_IPV4 1
+#define ALX_RXPARSE_FLT_L3_BOTH 2
+
+/* Terodo support */
+#define ALX_TRD_CTRL 0x145C
+#define ALX_TRD_CTRL_EN BIT(31)
+#define ALX_TRD_CTRL_BUBBLE_WAKE_EN BIT(30)
+#define ALX_TRD_CTRL_PREFIX_CMP_HW BIT(28)
+#define ALX_TRD_CTRL_RSHDR_ADDR_MASK 0xFFFUL
+#define ALX_TRD_CTRL_RSHDR_ADDR_SHIFT 16
+#define ALX_TRD_CTRL_SINTV_MAX_MASK 0xFFUL
+#define ALX_TRD_CTRL_SINTV_MAX_SHIFT 8
+#define ALX_TRD_CTRL_SINTV_MIN_MASK 0xFFUL
+#define ALX_TRD_CTRL_SINTV_MIN_SHIFT 0
+
+#define ALX_TRD_RS 0x1460
+#define ALX_TRD_RS_SZ_MASK 0xFFFUL
+#define ALX_TRD_RS_SZ_SHIFT 20
+#define ALX_TRD_RS_NONCE_OFS_MASK 0xFFFUL
+#define ALX_TRD_RS_NONCE_OFS_SHIFT 8
+#define ALX_TRD_RS_SEQ_OFS_MASK 0xFFUL
+#define ALX_TRD_RS_SEQ_OFS_SHIFT 0
+
+#define ALX_TRD_SRV_IP4 0x1464
+
+#define ALX_TRD_CLNT_EXTNL_IP4 0x1468
+
+#define ALX_TRD_PORT 0x146C
+#define ALX_TRD_PORT_CLNT_EXTNL_MASK 0xFFFFUL
+#define ALX_TRD_PORT_CLNT_EXTNL_SHIFT 16
+#define ALX_TRD_PORT_SRV_MASK 0xFFFFUL
+#define ALX_TRD_PORT_SRV_SHIFT 0
+
+#define ALX_TRD_PREFIX 0x1470
+
+#define ALX_TRD_BUBBLE_DA_IP4 0x1478
+
+#define ALX_TRD_BUBBLE_DA_PORT 0x147C
+
+/* for B0 */
+#define ALX_IDLE_DECISN_TIMER 0x1474
+/* 1ms */
+#define ALX_IDLE_DECISN_TIMER_DEF 0x400
+
+
+#define ALX_MAC_CTRL 0x1480
+#define ALX_MAC_CTRL_FAST_PAUSE BIT(31)
+#define ALX_MAC_CTRL_WOLSPED_SWEN BIT(30)
+/* bit29: 1:legacy(hi5b), 0:marvl(lo5b)*/
+#define ALX_MAC_CTRL_MHASH_ALG_HI5B BIT(29)
+#define ALX_MAC_CTRL_SPAUSE_EN BIT(28)
+#define ALX_MAC_CTRL_DBG_EN BIT(27)
+#define ALX_MAC_CTRL_BRD_EN BIT(26)
+#define ALX_MAC_CTRL_MULTIALL_EN BIT(25)
+#define ALX_MAC_CTRL_RX_XSUM_EN BIT(24)
+#define ALX_MAC_CTRL_THUGE BIT(23)
+#define ALX_MAC_CTRL_MBOF BIT(22)
+#define ALX_MAC_CTRL_SPEED_MASK 0x3UL
+#define ALX_MAC_CTRL_SPEED_SHIFT 20
+#define ALX_MAC_CTRL_SPEED_10_100 1
+#define ALX_MAC_CTRL_SPEED_1000 2
+#define ALX_MAC_CTRL_SIMR BIT(19)
+#define ALX_MAC_CTRL_SSTCT BIT(17)
+#define ALX_MAC_CTRL_TPAUSE BIT(16)
+#define ALX_MAC_CTRL_PROMISC_EN BIT(15)
+#define ALX_MAC_CTRL_VLANSTRIP BIT(14)
+#define ALX_MAC_CTRL_PRMBLEN_MASK 0xFUL
+#define ALX_MAC_CTRL_PRMBLEN_SHIFT 10
+#define ALX_MAC_CTRL_RHUGE_EN BIT(9)
+#define ALX_MAC_CTRL_FLCHK BIT(8)
+#define ALX_MAC_CTRL_PCRCE BIT(7)
+#define ALX_MAC_CTRL_CRCE BIT(6)
+#define ALX_MAC_CTRL_FULLD BIT(5)
+#define ALX_MAC_CTRL_LPBACK_EN BIT(4)
+#define ALX_MAC_CTRL_RXFC_EN BIT(3)
+#define ALX_MAC_CTRL_TXFC_EN BIT(2)
+#define ALX_MAC_CTRL_RX_EN BIT(1)
+#define ALX_MAC_CTRL_TX_EN BIT(0)
+
+#define ALX_GAP 0x1484
+#define ALX_GAP_IPGR2_MASK 0x7FUL
+#define ALX_GAP_IPGR2_SHIFT 24
+#define ALX_GAP_IPGR1_MASK 0x7FUL
+#define ALX_GAP_IPGR1_SHIFT 16
+#define ALX_GAP_MIN_IFG_MASK 0xFFUL
+#define ALX_GAP_MIN_IFG_SHIFT 8
+#define ALX_GAP_IPGT_MASK 0x7FUL
+#define ALX_GAP_IPGT_SHIFT 0
+
+#define ALX_STAD0 0x1488
+#define ALX_STAD1 0x148C
+
+#define ALX_HASH_TBL0 0x1490
+#define ALX_HASH_TBL1 0x1494
+
+#define ALX_HALFD 0x1498
+#define ALX_HALFD_JAM_IPG_MASK 0xFUL
+#define ALX_HALFD_JAM_IPG_SHIFT 24
+#define ALX_HALFD_ABEBT_MASK 0xFUL
+#define ALX_HALFD_ABEBT_SHIFT 20
+#define ALX_HALFD_ABEBE BIT(19)
+#define ALX_HALFD_BPNB BIT(18)
+#define ALX_HALFD_NOBO BIT(17)
+#define ALX_HALFD_EDXSDFR BIT(16)
+#define ALX_HALFD_RETRY_MASK 0xFUL
+#define ALX_HALFD_RETRY_SHIFT 12
+#define ALX_HALFD_LCOL_MASK 0x3FFUL
+#define ALX_HALFD_LCOL_SHIFT 0
+
+#define ALX_MTU 0x149C
+#define ALX_MTU_JUMBO_TH 1514
+#define ALX_MTU_STD_ALGN 1536
+#define ALX_MTU_MIN 64
+
+#define ALX_SRAM0 0x1500
+#define ALX_SRAM_RFD_TAIL_ADDR_MASK 0xFFFUL
+#define ALX_SRAM_RFD_TAIL_ADDR_SHIFT 16
+#define ALX_SRAM_RFD_HEAD_ADDR_MASK 0xFFFUL
+#define ALX_SRAM_RFD_HEAD_ADDR_SHIFT 0
+
+#define ALX_SRAM1 0x1510
+#define ALX_SRAM_RFD_LEN_MASK 0xFFFUL
+#define ALX_SRAM_RFD_LEN_SHIFT 0
+
+#define ALX_SRAM2 0x1518
+#define ALX_SRAM_TRD_TAIL_ADDR_MASK 0xFFFUL
+#define ALX_SRAM_TRD_TAIL_ADDR_SHIFT 16
+#define ALX_SRMA_TRD_HEAD_ADDR_MASK 0xFFFUL
+#define ALX_SRAM_TRD_HEAD_ADDR_SHIFT 0
+
+#define ALX_SRAM3 0x151C
+#define ALX_SRAM_TRD_LEN_MASK 0xFFFUL
+#define ALX_SRAM_TRD_LEN_SHIFT 0
+
+#define ALX_SRAM4 0x1520
+#define ALX_SRAM_RXF_TAIL_ADDR_MASK 0xFFFUL
+#define ALX_SRAM_RXF_TAIL_ADDR_SHIFT 16
+#define ALX_SRAM_RXF_HEAD_ADDR_MASK 0xFFFUL
+#define ALX_SRAM_RXF_HEAD_ADDR_SHIFT 0
+
+#define ALX_SRAM5 0x1524
+#define ALX_SRAM_RXF_LEN_MASK 0xFFFUL
+#define ALX_SRAM_RXF_LEN_SHIFT 0
+#define ALX_SRAM_RXF_LEN_8K (8*1024)
+
+#define ALX_SRAM6 0x1528
+#define ALX_SRAM_TXF_TAIL_ADDR_MASK 0xFFFUL
+#define ALX_SRAM_TXF_TAIL_ADDR_SHIFT 16
+#define ALX_SRAM_TXF_HEAD_ADDR_MASK 0xFFFUL
+#define ALX_SRAM_TXF_HEAD_ADDR_SHIFT 0
+
+#define ALX_SRAM7 0x152C
+#define ALX_SRAM_TXF_LEN_MASK 0xFFFUL
+#define ALX_SRAM_TXF_LEN_SHIFT 0
+
+#define ALX_SRAM8 0x1530
+#define ALX_SRAM_PATTERN_ADDR_MASK 0xFFFUL
+#define ALX_SRAM_PATTERN_ADDR_SHIFT 16
+#define ALX_SRAM_TSO_ADDR_MASK 0xFFFUL
+#define ALX_SRAM_TSO_ADDR_SHIFT 0
+
+#define ALX_SRAM9 0x1534
+#define ALX_SRAM_LOAD_PTR BIT(0)
+
+#define ALX_RX_BASE_ADDR_HI 0x1540
+
+#define ALX_TX_BASE_ADDR_HI 0x1544
+
+#define ALX_RFD_ADDR_LO 0x1550
+#define ALX_RFD_RING_SZ 0x1560
+#define ALX_RFD_BUF_SZ 0x1564
+#define ALX_RFD_BUF_SZ_MASK 0xFFFFUL
+#define ALX_RFD_BUF_SZ_SHIFT 0
+
+#define ALX_RRD_ADDR_LO 0x1568
+#define ALX_RRD_RING_SZ 0x1578
+#define ALX_RRD_RING_SZ_MASK 0xFFFUL
+#define ALX_RRD_RING_SZ_SHIFT 0
+
+/* pri3: highest, pri0: lowest */
+#define ALX_TPD_PRI3_ADDR_LO 0x14E4
+#define ALX_TPD_PRI2_ADDR_LO 0x14E0
+#define ALX_TPD_PRI1_ADDR_LO 0x157C
+#define ALX_TPD_PRI0_ADDR_LO 0x1580
+
+/* producer index is 16bit */
+#define ALX_TPD_PRI3_PIDX 0x1618
+#define ALX_TPD_PRI2_PIDX 0x161A
+#define ALX_TPD_PRI1_PIDX 0x15F0
+#define ALX_TPD_PRI0_PIDX 0x15F2
+
+/* consumer index is 16bit */
+#define ALX_TPD_PRI3_CIDX 0x161C
+#define ALX_TPD_PRI2_CIDX 0x161E
+#define ALX_TPD_PRI1_CIDX 0x15F4
+#define ALX_TPD_PRI0_CIDX 0x15F6
+
+#define ALX_TPD_RING_SZ 0x1584
+#define ALX_TPD_RING_SZ_MASK 0xFFFFUL
+#define ALX_TPD_RING_SZ_SHIFT 0
+
+#define ALX_CMB_ADDR_LO 0x1588
+
+#define ALX_TXQ0 0x1590
+#define ALX_TXQ0_TXF_BURST_PREF_MASK 0xFFFFUL
+#define ALX_TXQ0_TXF_BURST_PREF_SHIFT 16
+#define ALX_TXQ_TXF_BURST_PREF_DEF 0x200
+#define ALX_TXQ0_PEDING_CLR BIT(8)
+#define ALX_TXQ0_LSO_8023_EN BIT(7)
+#define ALX_TXQ0_MODE_ENHANCE BIT(6)
+#define ALX_TXQ0_EN BIT(5)
+#define ALX_TXQ0_SUPT_IPOPT BIT(4)
+#define ALX_TXQ0_TPD_BURSTPREF_MASK 0xFUL
+#define ALX_TXQ0_TPD_BURSTPREF_SHIFT 0
+#define ALX_TXQ_TPD_BURSTPREF_DEF 5
+
+#define ALX_TXQ1 0x1594
+/* bit11: drop large packet, len > (rfd buf) */
+#define ALX_TXQ1_ERRLGPKT_DROP_EN BIT(11)
+/* bit[9:0]: 8bytes unit */
+#define ALX_TXQ1_JUMBO_TSOTHR_MASK 0x7FFUL
+#define ALX_TXQ1_JUMBO_TSOTHR_SHIFT 0
+#define ALX_TXQ1_JUMBO_TSO_TH (7*1024)
+
+/* L1 entrance control */
+#define ALX_TXQ2 0x1598
+#define ALX_TXQ2_BURST_EN BIT(31)
+#define ALX_TXQ2_BURST_HI_WM_MASK 0xFFFUL
+#define ALX_TXQ2_BURST_HI_WM_SHIFT 16
+#define ALX_TXQ2_BURST_LO_WM_MASK 0xFFFUL
+#define ALX_TXQ2_BURST_LO_WM_SHIFT 0
+
+#define ALX_RXQ0 0x15A0
+#define ALX_RXQ0_EN BIT(31)
+#define ALX_RXQ0_CUT_THRU_EN BIT(30)
+#define ALX_RXQ0_RSS_HASH_EN BIT(29)
+/* bit28: 0:goto Q0, 1:as table */
+#define ALX_RXQ0_NON_IP_QTBL BIT(28)
+#define ALX_RXQ0_RSS_MODE_MASK 0x3UL
+#define ALX_RXQ0_RSS_MODE_SHIFT 26
+#define ALX_RXQ0_RSS_MODE_DIS 0
+#define ALX_RXQ0_RSS_MODE_SQSI 1
+#define ALX_RXQ0_RSS_MODE_MQSI 2
+#define ALX_RXQ0_RSS_MODE_MQMI 3
+#define ALX_RXQ0_NUM_RFD_PREF_MASK 0x3FUL
+#define ALX_RXQ0_NUM_RFD_PREF_SHIFT 20
+#define ALX_RXQ0_NUM_RFD_PREF_DEF 8
+#define ALX_RXQ0_IDT_TBL_SIZE_MASK 0x1FFUL
+#define ALX_RXQ0_IDT_TBL_SIZE_SHIFT 8
+#define ALX_RXQ0_IDT_TBL_SIZE_DEF 0x100
+#define ALX_RXQ0_IPV6_PARSE_EN BIT(7)
+#define ALX_RXQ0_RSS_HSTYP_MASK 0xFUL
+#define ALX_RXQ0_RSS_HSTYP_SHIFT 2
+#define ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN BIT(5)
+#define ALX_RXQ0_RSS_HSTYP_IPV6_EN BIT(4)
+#define ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN BIT(3)
+#define ALX_RXQ0_RSS_HSTYP_IPV4_EN BIT(2)
+#define ALX_RXQ0_RSS_HSTYP_ALL (\
+ ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN |\
+ ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN |\
+ ALX_RXQ0_RSS_HSTYP_IPV6_EN |\
+ ALX_RXQ0_RSS_HSTYP_IPV4_EN)
+#define ALX_RXQ0_ASPM_THRESH_MASK 0x3UL
+#define ALX_RXQ0_ASPM_THRESH_SHIFT 0
+#define ALX_RXQ0_ASPM_THRESH_NO 0
+#define ALX_RXQ0_ASPM_THRESH_1M 1
+#define ALX_RXQ0_ASPM_THRESH_10M 2
+#define ALX_RXQ0_ASPM_THRESH_100M 3
+
+#define ALX_RXQ1 0x15A4
+/* 32bytes unit */
+#define ALX_RXQ1_JUMBO_LKAH_MASK 0xFUL
+#define ALX_RXQ1_JUMBO_LKAH_SHIFT 12
+#define ALX_RXQ1_RFD_PREF_DOWN_MASK 0x3FUL
+#define ALX_RXQ1_RFD_PREF_DOWN_SHIFT 6
+#define ALX_RXQ1_RFD_PREF_UP_MASK 0x3FUL
+#define ALX_RXQ1_RFD_PREF_UP_SHIFT 0
+
+#define ALX_RXQ2 0x15A8
+/* XOFF: USED SRAM LOWER THAN IT, THEN NOTIFY THE PEER TO SEND AGAIN */
+#define ALX_RXQ2_RXF_XOFF_THRESH_MASK 0xFFFUL
+#define ALX_RXQ2_RXF_XOFF_THRESH_SHIFT 16
+#define ALX_RXQ2_RXF_XON_THRESH_MASK 0xFFFUL
+#define ALX_RXQ2_RXF_XON_THRESH_SHIFT 0
+/* Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) +
+ * rx-packet(1522) + delay-of-link(64)
+ * = 3212.
+ */
+#define ALX_RXQ2_RXF_FLOW_CTRL_RSVD 3212
+
+#define ALX_RXQ3 0x15AC
+#define ALX_RXQ3_RXD_TIMER_MASK 0x7FFFUL
+#define ALX_RXQ3_RXD_TIMER_SHIFT 16
+/* 8bytes unit */
+#define ALX_RXQ3_RXD_THRESH_MASK 0xFFFUL
+#define ALX_RXQ3_RXD_THRESH_SHIFT 0
+
+#define ALX_DMA 0x15C0
+#define ALX_DMA_SMB_NOW BIT(31)
+#define ALX_DMA_WPEND_CLR BIT(30)
+#define ALX_DMA_RPEND_CLR BIT(29)
+#define ALX_DMA_WSRAM_RDCTRL BIT(28)
+#define ALX_DMA_RCHNL_SEL_MASK 0x3UL
+#define ALX_DMA_RCHNL_SEL_SHIFT 26
+#define ALX_DMA_RCHNL_SEL_1 0
+#define ALX_DMA_RCHNL_SEL_2 1
+#define ALX_DMA_RCHNL_SEL_3 2
+#define ALX_DMA_RCHNL_SEL_4 3
+#define ALX_DMA_SMB_EN BIT(21)
+#define ALX_DMA_WDLY_CNT_MASK 0xFUL
+#define ALX_DMA_WDLY_CNT_SHIFT 16
+#define ALX_DMA_WDLY_CNT_DEF 4
+#define ALX_DMA_RDLY_CNT_MASK 0x1FUL
+#define ALX_DMA_RDLY_CNT_SHIFT 11
+#define ALX_DMA_RDLY_CNT_DEF 15
+/* bit10: 0:tpd with pri, 1: data */
+#define ALX_DMA_RREQ_PRI_DATA BIT(10)
+#define ALX_DMA_WREQ_BLEN_MASK 0x7UL
+#define ALX_DMA_WREQ_BLEN_SHIFT 7
+#define ALX_DMA_RREQ_BLEN_MASK 0x7UL
+#define ALX_DMA_RREQ_BLEN_SHIFT 4
+#define ALX_DMA_PENDING_AUTO_RST BIT(3)
+#define ALX_DMA_RORDER_MODE_MASK 0x7UL
+#define ALX_DMA_RORDER_MODE_SHIFT 0
+#define ALX_DMA_RORDER_MODE_OUT 4
+#define ALX_DMA_RORDER_MODE_ENHANCE 2
+#define ALX_DMA_RORDER_MODE_IN 1
+
+#define ALX_WOL0 0x14A0
+#define ALX_WOL0_PT7_MATCH BIT(31)
+#define ALX_WOL0_PT6_MATCH BIT(30)
+#define ALX_WOL0_PT5_MATCH BIT(29)
+#define ALX_WOL0_PT4_MATCH BIT(28)
+#define ALX_WOL0_PT3_MATCH BIT(27)
+#define ALX_WOL0_PT2_MATCH BIT(26)
+#define ALX_WOL0_PT1_MATCH BIT(25)
+#define ALX_WOL0_PT0_MATCH BIT(24)
+#define ALX_WOL0_PT7_EN BIT(23)
+#define ALX_WOL0_PT6_EN BIT(22)
+#define ALX_WOL0_PT5_EN BIT(21)
+#define ALX_WOL0_PT4_EN BIT(20)
+#define ALX_WOL0_PT3_EN BIT(19)
+#define ALX_WOL0_PT2_EN BIT(18)
+#define ALX_WOL0_PT1_EN BIT(17)
+#define ALX_WOL0_PT0_EN BIT(16)
+#define ALX_WOL0_IPV4_SYNC_EVT BIT(14)
+#define ALX_WOL0_IPV6_SYNC_EVT BIT(13)
+#define ALX_WOL0_LINK_EVT BIT(10)
+#define ALX_WOL0_MAGIC_EVT BIT(9)
+#define ALX_WOL0_PATTERN_EVT BIT(8)
+#define ALX_WOL0_SWOI_EVT BIT(7)
+#define ALX_WOL0_OOB_EN BIT(6)
+#define ALX_WOL0_PME_LINK BIT(5)
+#define ALX_WOL0_LINK_EN BIT(4)
+#define ALX_WOL0_PME_MAGIC_EN BIT(3)
+#define ALX_WOL0_MAGIC_EN BIT(2)
+#define ALX_WOL0_PME_PATTERN_EN BIT(1)
+#define ALX_WOL0_PATTERN_EN BIT(0)
+
+#define ALX_WOL1 0x14A4
+#define ALX_WOL1_PT3_LEN_MASK 0xFFUL
+#define ALX_WOL1_PT3_LEN_SHIFT 24
+#define ALX_WOL1_PT2_LEN_MASK 0xFFUL
+#define ALX_WOL1_PT2_LEN_SHIFT 16
+#define ALX_WOL1_PT1_LEN_MASK 0xFFUL
+#define ALX_WOL1_PT1_LEN_SHIFT 8
+#define ALX_WOL1_PT0_LEN_MASK 0xFFUL
+#define ALX_WOL1_PT0_LEN_SHIFT 0
+
+#define ALX_WOL2 0x14A8
+#define ALX_WOL2_PT7_LEN_MASK 0xFFUL
+#define ALX_WOL2_PT7_LEN_SHIFT 24
+#define ALX_WOL2_PT6_LEN_MASK 0xFFUL
+#define ALX_WOL2_PT6_LEN_SHIFT 16
+#define ALX_WOL2_PT5_LEN_MASK 0xFFUL
+#define ALX_WOL2_PT5_LEN_SHIFT 8
+#define ALX_WOL2_PT4_LEN_MASK 0xFFUL
+#define ALX_WOL2_PT4_LEN_SHIFT 0
+
+#define ALX_RFD_PIDX 0x15E0
+#define ALX_RFD_PIDX_MASK 0xFFFUL
+#define ALX_RFD_PIDX_SHIFT 0
+
+#define ALX_RFD_CIDX 0x15F8
+#define ALX_RFD_CIDX_MASK 0xFFFUL
+#define ALX_RFD_CIDX_SHIFT 0
+
+/* MIB */
+#define ALX_MIB_BASE 0x1700
+#define ALX_MIB_RX_OK (ALX_MIB_BASE + 0)
+#define ALX_MIB_RX_BC (ALX_MIB_BASE + 4)
+#define ALX_MIB_RX_MC (ALX_MIB_BASE + 8)
+#define ALX_MIB_RX_PAUSE (ALX_MIB_BASE + 12)
+#define ALX_MIB_RX_CTRL (ALX_MIB_BASE + 16)
+#define ALX_MIB_RX_FCS (ALX_MIB_BASE + 20)
+#define ALX_MIB_RX_LENERR (ALX_MIB_BASE + 24)
+#define ALX_MIB_RX_BYTCNT (ALX_MIB_BASE + 28)
+#define ALX_MIB_RX_RUNT (ALX_MIB_BASE + 32)
+#define ALX_MIB_RX_FRAGMENT (ALX_MIB_BASE + 36)
+#define ALX_MIB_RX_64B (ALX_MIB_BASE + 40)
+#define ALX_MIB_RX_127B (ALX_MIB_BASE + 44)
+#define ALX_MIB_RX_255B (ALX_MIB_BASE + 48)
+#define ALX_MIB_RX_511B (ALX_MIB_BASE + 52)
+#define ALX_MIB_RX_1023B (ALX_MIB_BASE + 56)
+#define ALX_MIB_RX_1518B (ALX_MIB_BASE + 60)
+#define ALX_MIB_RX_SZMAX (ALX_MIB_BASE + 64)
+#define ALX_MIB_RX_OVSZ (ALX_MIB_BASE + 68)
+#define ALX_MIB_RXF_OV (ALX_MIB_BASE + 72)
+#define ALX_MIB_RRD_OV (ALX_MIB_BASE + 76)
+#define ALX_MIB_RX_ALIGN (ALX_MIB_BASE + 80)
+#define ALX_MIB_RX_BCCNT (ALX_MIB_BASE + 84)
+#define ALX_MIB_RX_MCCNT (ALX_MIB_BASE + 88)
+#define ALX_MIB_RX_ERRADDR (ALX_MIB_BASE + 92)
+#define ALX_MIB_TX_OK (ALX_MIB_BASE + 96)
+#define ALX_MIB_TX_BC (ALX_MIB_BASE + 100)
+#define ALX_MIB_TX_MC (ALX_MIB_BASE + 104)
+#define ALX_MIB_TX_PAUSE (ALX_MIB_BASE + 108)
+#define ALX_MIB_TX_EXCDEFER (ALX_MIB_BASE + 112)
+#define ALX_MIB_TX_CTRL (ALX_MIB_BASE + 116)
+#define ALX_MIB_TX_DEFER (ALX_MIB_BASE + 120)
+#define ALX_MIB_TX_BYTCNT (ALX_MIB_BASE + 124)
+#define ALX_MIB_TX_64B (ALX_MIB_BASE + 128)
+#define ALX_MIB_TX_127B (ALX_MIB_BASE + 132)
+#define ALX_MIB_TX_255B (ALX_MIB_BASE + 136)
+#define ALX_MIB_TX_511B (ALX_MIB_BASE + 140)
+#define ALX_MIB_TX_1023B (ALX_MIB_BASE + 144)
+#define ALX_MIB_TX_1518B (ALX_MIB_BASE + 148)
+#define ALX_MIB_TX_SZMAX (ALX_MIB_BASE + 152)
+#define ALX_MIB_TX_1COL (ALX_MIB_BASE + 156)
+#define ALX_MIB_TX_2COL (ALX_MIB_BASE + 160)
+#define ALX_MIB_TX_LATCOL (ALX_MIB_BASE + 164)
+#define ALX_MIB_TX_ABRTCOL (ALX_MIB_BASE + 168)
+#define ALX_MIB_TX_UNDRUN (ALX_MIB_BASE + 172)
+#define ALX_MIB_TX_TRDBEOP (ALX_MIB_BASE + 176)
+#define ALX_MIB_TX_LENERR (ALX_MIB_BASE + 180)
+#define ALX_MIB_TX_TRUNC (ALX_MIB_BASE + 184)
+#define ALX_MIB_TX_BCCNT (ALX_MIB_BASE + 188)
+#define ALX_MIB_TX_MCCNT (ALX_MIB_BASE + 192)
+#define ALX_MIB_UPDATE (ALX_MIB_BASE + 196)
+
+#define ALX_RX_STATS_BIN ALX_MIB_RX_OK
+#define ALX_RX_STATS_END ALX_MIB_RX_ERRADDR
+#define ALX_TX_STATS_BIN ALX_MIB_TX_OK
+#define ALX_TX_STATS_END ALX_MIB_TX_MCCNT
+
+#define ALX_ISR 0x1600
+#define ALX_ISR_DIS BIT(31)
+#define ALX_ISR_RX_Q7 BIT(30)
+#define ALX_ISR_RX_Q6 BIT(29)
+#define ALX_ISR_RX_Q5 BIT(28)
+#define ALX_ISR_RX_Q4 BIT(27)
+#define ALX_ISR_PCIE_LNKDOWN BIT(26)
+#define ALX_ISR_PCIE_CERR BIT(25)
+#define ALX_ISR_PCIE_NFERR BIT(24)
+#define ALX_ISR_PCIE_FERR BIT(23)
+#define ALX_ISR_PCIE_UR BIT(22)
+#define ALX_ISR_MAC_TX BIT(21)
+#define ALX_ISR_MAC_RX BIT(20)
+#define ALX_ISR_RX_Q3 BIT(19)
+#define ALX_ISR_RX_Q2 BIT(18)
+#define ALX_ISR_RX_Q1 BIT(17)
+#define ALX_ISR_RX_Q0 BIT(16)
+#define ALX_ISR_TX_Q0 BIT(15)
+#define ALX_ISR_TXQ_TO BIT(14)
+#define ALX_ISR_PHY_LPW BIT(13)
+#define ALX_ISR_PHY BIT(12)
+#define ALX_ISR_TX_CREDIT BIT(11)
+#define ALX_ISR_DMAW BIT(10)
+#define ALX_ISR_DMAR BIT(9)
+#define ALX_ISR_TXF_UR BIT(8)
+#define ALX_ISR_TX_Q3 BIT(7)
+#define ALX_ISR_TX_Q2 BIT(6)
+#define ALX_ISR_TX_Q1 BIT(5)
+#define ALX_ISR_RFD_UR BIT(4)
+#define ALX_ISR_RXF_OV BIT(3)
+#define ALX_ISR_MANU BIT(2)
+#define ALX_ISR_TIMER BIT(1)
+#define ALX_ISR_SMB BIT(0)
+
+#define ALX_IMR 0x1604
+
+/* re-send assert msg if SW no response */
+#define ALX_INT_RETRIG 0x1608
+#define ALX_INT_RETRIG_TIMER_MASK 0xFFFFUL
+#define ALX_INT_RETRIG_TIMER_SHIFT 0
+/* 40ms */
+#define ALX_INT_RETRIG_TO 20000
+
+/* re-send deassert msg if SW no response */
+#define ALX_INT_DEASST_TIMER 0x1614
+
+/* reg1620 used for sleep status */
+#define ALX_PATTERN_MASK 0x1620
+#define ALX_PATTERN_MASK_LEN 128
+
+
+#define ALX_FLT1_SRC_IP0 0x1A00
+#define ALX_FLT1_SRC_IP1 0x1A04
+#define ALX_FLT1_SRC_IP2 0x1A08
+#define ALX_FLT1_SRC_IP3 0x1A0C
+#define ALX_FLT1_DST_IP0 0x1A10
+#define ALX_FLT1_DST_IP1 0x1A14
+#define ALX_FLT1_DST_IP2 0x1A18
+#define ALX_FLT1_DST_IP3 0x1A1C
+#define ALX_FLT1_PORT 0x1A20
+#define ALX_FLT1_PORT_DST_MASK 0xFFFFUL
+#define ALX_FLT1_PORT_DST_SHIFT 16
+#define ALX_FLT1_PORT_SRC_MASK 0xFFFFUL
+#define ALX_FLT1_PORT_SRC_SHIFT 0
+
+#define ALX_FLT2_SRC_IP0 0x1A24
+#define ALX_FLT2_SRC_IP1 0x1A28
+#define ALX_FLT2_SRC_IP2 0x1A2C
+#define ALX_FLT2_SRC_IP3 0x1A30
+#define ALX_FLT2_DST_IP0 0x1A34
+#define ALX_FLT2_DST_IP1 0x1A38
+#define ALX_FLT2_DST_IP2 0x1A40
+#define ALX_FLT2_DST_IP3 0x1A44
+#define ALX_FLT2_PORT 0x1A48
+#define ALX_FLT2_PORT_DST_MASK 0xFFFFUL
+#define ALX_FLT2_PORT_DST_SHIFT 16
+#define ALX_FLT2_PORT_SRC_MASK 0xFFFFUL
+#define ALX_FLT2_PORT_SRC_SHIFT 0
+
+#define ALX_FLT3_SRC_IP0 0x1A4C
+#define ALX_FLT3_SRC_IP1 0x1A50
+#define ALX_FLT3_SRC_IP2 0x1A54
+#define ALX_FLT3_SRC_IP3 0x1A58
+#define ALX_FLT3_DST_IP0 0x1A5C
+#define ALX_FLT3_DST_IP1 0x1A60
+#define ALX_FLT3_DST_IP2 0x1A64
+#define ALX_FLT3_DST_IP3 0x1A68
+#define ALX_FLT3_PORT 0x1A6C
+#define ALX_FLT3_PORT_DST_MASK 0xFFFFUL
+#define ALX_FLT3_PORT_DST_SHIFT 16
+#define ALX_FLT3_PORT_SRC_MASK 0xFFFFUL
+#define ALX_FLT3_PORT_SRC_SHIFT 0
+
+#define ALX_FLT4_SRC_IP0 0x1A70
+#define ALX_FLT4_SRC_IP1 0x1A74
+#define ALX_FLT4_SRC_IP2 0x1A78
+#define ALX_FLT4_SRC_IP3 0x1A7C
+#define ALX_FLT4_DST_IP0 0x1A80
+#define ALX_FLT4_DST_IP1 0x1A84
+#define ALX_FLT4_DST_IP2 0x1A88
+#define ALX_FLT4_DST_IP3 0x1A8C
+#define ALX_FLT4_PORT 0x1A90
+#define ALX_FLT4_PORT_DST_MASK 0xFFFFUL
+#define ALX_FLT4_PORT_DST_SHIFT 16
+#define ALX_FLT4_PORT_SRC_MASK 0xFFFFUL
+#define ALX_FLT4_PORT_SRC_SHIFT 0
+
+#define ALX_FLT5_SRC_IP0 0x1A94
+#define ALX_FLT5_SRC_IP1 0x1A98
+#define ALX_FLT5_SRC_IP2 0x1A9C
+#define ALX_FLT5_SRC_IP3 0x1AA0
+#define ALX_FLT5_DST_IP0 0x1AA4
+#define ALX_FLT5_DST_IP1 0x1AA8
+#define ALX_FLT5_DST_IP2 0x1AAC
+#define ALX_FLT5_DST_IP3 0x1AB0
+#define ALX_FLT5_PORT 0x1AB4
+#define ALX_FLT5_PORT_DST_MASK 0xFFFFUL
+#define ALX_FLT5_PORT_DST_SHIFT 16
+#define ALX_FLT5_PORT_SRC_MASK 0xFFFFUL
+#define ALX_FLT5_PORT_SRC_SHIFT 0
+
+#define ALX_FLT6_SRC_IP0 0x1AB8
+#define ALX_FLT6_SRC_IP1 0x1ABC
+#define ALX_FLT6_SRC_IP2 0x1AC0
+#define ALX_FLT6_SRC_IP3 0x1AC8
+#define ALX_FLT6_DST_IP0 0x1620
+#define ALX_FLT6_DST_IP1 0x1624
+#define ALX_FLT6_DST_IP2 0x1628
+#define ALX_FLT6_DST_IP3 0x162C
+#define ALX_FLT6_PORT 0x1630
+#define ALX_FLT6_PORT_DST_MASK 0xFFFFUL
+#define ALX_FLT6_PORT_DST_SHIFT 16
+#define ALX_FLT6_PORT_SRC_MASK 0xFFFFUL
+#define ALX_FLT6_PORT_SRC_SHIFT 0
+
+#define ALX_FLTCTRL 0x1634
+#define ALX_FLTCTRL_PSTHR_TIMER_MASK 0xFFUL
+#define ALX_FLTCTRL_PSTHR_TIMER_SHIFT 24
+#define ALX_FLTCTRL_CHK_DSTPRT6 BIT(23)
+#define ALX_FLTCTRL_CHK_SRCPRT6 BIT(22)
+#define ALX_FLTCTRL_CHK_DSTIP6 BIT(21)
+#define ALX_FLTCTRL_CHK_SRCIP6 BIT(20)
+#define ALX_FLTCTRL_CHK_DSTPRT5 BIT(19)
+#define ALX_FLTCTRL_CHK_SRCPRT5 BIT(18)
+#define ALX_FLTCTRL_CHK_DSTIP5 BIT(17)
+#define ALX_FLTCTRL_CHK_SRCIP5 BIT(16)
+#define ALX_FLTCTRL_CHK_DSTPRT4 BIT(15)
+#define ALX_FLTCTRL_CHK_SRCPRT4 BIT(14)
+#define ALX_FLTCTRL_CHK_DSTIP4 BIT(13)
+#define ALX_FLTCTRL_CHK_SRCIP4 BIT(12)
+#define ALX_FLTCTRL_CHK_DSTPRT3 BIT(11)
+#define ALX_FLTCTRL_CHK_SRCPRT3 BIT(10)
+#define ALX_FLTCTRL_CHK_DSTIP3 BIT(9)
+#define ALX_FLTCTRL_CHK_SRCIP3 BIT(8)
+#define ALX_FLTCTRL_CHK_DSTPRT2 BIT(7)
+#define ALX_FLTCTRL_CHK_SRCPRT2 BIT(6)
+#define ALX_FLTCTRL_CHK_DSTIP2 BIT(5)
+#define ALX_FLTCTRL_CHK_SRCIP2 BIT(4)
+#define ALX_FLTCTRL_CHK_DSTPRT1 BIT(3)
+#define ALX_FLTCTRL_CHK_SRCPRT1 BIT(2)
+#define ALX_FLTCTRL_CHK_DSTIP1 BIT(1)
+#define ALX_FLTCTRL_CHK_SRCIP1 BIT(0)
+
+#define ALX_DROP_ALG1 0x1638
+#define ALX_DROP_ALG1_BWCHGVAL_MASK 0xFFFFFUL
+#define ALX_DROP_ALG1_BWCHGVAL_SHIFT 12
+/* bit11: 0:3.125%, 1:6.25% */
+#define ALX_DROP_ALG1_BWCHGSCL_6 BIT(11)
+#define ALX_DROP_ALG1_ASUR_LWQ_EN BIT(10)
+#define ALX_DROP_ALG1_BWCHGVAL_EN BIT(9)
+#define ALX_DROP_ALG1_BWCHGSCL_EN BIT(8)
+#define ALX_DROP_ALG1_PSTHR_AUTO BIT(7)
+#define ALX_DROP_ALG1_MIN_PSTHR_MASK 0x3UL
+#define ALX_DROP_ALG1_MIN_PSTHR_SHIFT 5
+#define ALX_DROP_ALG1_MIN_PSTHR_1_16 0
+#define ALX_DROP_ALG1_MIN_PSTHR_1_8 1
+#define ALX_DROP_ALG1_MIN_PSTHR_1_4 2
+#define ALX_DROP_ALG1_MIN_PSTHR_1_2 3
+#define ALX_DROP_ALG1_PSCL_MASK 0x3UL
+#define ALX_DROP_ALG1_PSCL_SHIFT 3
+#define ALX_DROP_ALG1_PSCL_1_4 0
+#define ALX_DROP_ALG1_PSCL_1_8 1
+#define ALX_DROP_ALG1_PSCL_1_16 2
+#define ALX_DROP_ALG1_PSCL_1_32 3
+#define ALX_DROP_ALG1_TIMESLOT_MASK 0x7UL
+#define ALX_DROP_ALG1_TIMESLOT_SHIFT 0
+#define ALX_DROP_ALG1_TIMESLOT_4MS 0
+#define ALX_DROP_ALG1_TIMESLOT_8MS 1
+#define ALX_DROP_ALG1_TIMESLOT_16MS 2
+#define ALX_DROP_ALG1_TIMESLOT_32MS 3
+#define ALX_DROP_ALG1_TIMESLOT_64MS 4
+#define ALX_DROP_ALG1_TIMESLOT_128MS 5
+#define ALX_DROP_ALG1_TIMESLOT_256MS 6
+#define ALX_DROP_ALG1_TIMESLOT_512MS 7
+
+#define ALX_DROP_ALG2 0x163C
+#define ALX_DROP_ALG2_SMPLTIME_MASK 0xFUL
+#define ALX_DROP_ALG2_SMPLTIME_SHIFT 24
+#define ALX_DROP_ALG2_LWQBW_MASK 0xFFFFFFUL
+#define ALX_DROP_ALG2_LWQBW_SHIFT 0
+
+#define ALX_SMB_TIMER 0x15C4
+
+#define ALX_TINT_TPD_THRSHLD 0x15C8
+
+#define ALX_TINT_TIMER 0x15CC
+
+#define ALX_CLK_GATE 0x1814
+/* bit[8:6]: for B0+ */
+#define ALX_CLK_GATE_125M_SW_DIS_CR BIT(8)
+#define ALX_CLK_GATE_125M_SW_AZ BIT(7)
+#define ALX_CLK_GATE_125M_SW_IDLE BIT(6)
+#define ALX_CLK_GATE_RXMAC BIT(5)
+#define ALX_CLK_GATE_TXMAC BIT(4)
+#define ALX_CLK_GATE_RXQ BIT(3)
+#define ALX_CLK_GATE_TXQ BIT(2)
+#define ALX_CLK_GATE_DMAR BIT(1)
+#define ALX_CLK_GATE_DMAW BIT(0)
+#define ALX_CLK_GATE_ALL_A0 (\
+ ALX_CLK_GATE_RXMAC |\
+ ALX_CLK_GATE_TXMAC |\
+ ALX_CLK_GATE_RXQ |\
+ ALX_CLK_GATE_TXQ |\
+ ALX_CLK_GATE_DMAR |\
+ ALX_CLK_GATE_DMAW)
+#define ALX_CLK_GATE_ALL_B0 (\
+ ALX_CLK_GATE_ALL_A0)
+
+/* PORST affect */
+#define ALX_BTROM_CFG 0x1800
+
+/* interop between drivers */
+#define ALX_DRV 0x1804
+#define ALX_DRV_PHY_AUTO BIT(28)
+#define ALX_DRV_PHY_1000 BIT(27)
+#define ALX_DRV_PHY_100 BIT(26)
+#define ALX_DRV_PHY_10 BIT(25)
+#define ALX_DRV_PHY_DUPLEX BIT(24)
+/* bit23: adv Pause */
+#define ALX_DRV_PHY_PAUSE BIT(23)
+/* bit22: adv Asym Pause */
+#define ALX_DRV_PHY_APAUSE BIT(22)
+/* bit21: 1:en AZ */
+#define ALX_DRV_PHY_EEE BIT(21)
+#define ALX_DRV_PHY_MASK 0xFFUL
+#define ALX_DRV_PHY_SHIFT 21
+#define ALX_DRV_PHY_UNKNOWN 0
+#define ALX_DRV_DISABLE BIT(18)
+#define ALX_DRV_WOLS5_EN BIT(17)
+#define ALX_DRV_WOLS5_BIOS_EN BIT(16)
+#define ALX_DRV_AZ_EN BIT(12)
+#define ALX_DRV_WOLPATTERN_EN BIT(11)
+#define ALX_DRV_WOLLINKUP_EN BIT(10)
+#define ALX_DRV_WOLMAGIC_EN BIT(9)
+#define ALX_DRV_WOLCAP_BIOS_EN BIT(8)
+#define ALX_DRV_ASPM_SPD1000LMT_MASK 0x3UL
+#define ALX_DRV_ASPM_SPD1000LMT_SHIFT 4
+#define ALX_DRV_ASPM_SPD1000LMT_100M 0
+#define ALX_DRV_ASPM_SPD1000LMT_NO 1
+#define ALX_DRV_ASPM_SPD1000LMT_1M 2
+#define ALX_DRV_ASPM_SPD1000LMT_10M 3
+#define ALX_DRV_ASPM_SPD100LMT_MASK 0x3UL
+#define ALX_DRV_ASPM_SPD100LMT_SHIFT 2
+#define ALX_DRV_ASPM_SPD100LMT_1M 0
+#define ALX_DRV_ASPM_SPD100LMT_10M 1
+#define ALX_DRV_ASPM_SPD100LMT_100M 2
+#define ALX_DRV_ASPM_SPD100LMT_NO 3
+#define ALX_DRV_ASPM_SPD10LMT_MASK 0x3UL
+#define ALX_DRV_ASPM_SPD10LMT_SHIFT 0
+#define ALX_DRV_ASPM_SPD10LMT_1M 0
+#define ALX_DRV_ASPM_SPD10LMT_10M 1
+#define ALX_DRV_ASPM_SPD10LMT_100M 2
+#define ALX_DRV_ASPM_SPD10LMT_NO 3
+
+/* flag of phy inited */
+#define ALX_PHY_INITED 0x003F
+
+/* PERST affect */
+#define ALX_DRV_ERR1 0x1808
+#define ALX_DRV_ERR1_GEN BIT(31)
+#define ALX_DRV_ERR1_NOR BIT(30)
+#define ALX_DRV_ERR1_TRUNC BIT(29)
+#define ALX_DRV_ERR1_RES BIT(28)
+#define ALX_DRV_ERR1_INTFATAL BIT(27)
+#define ALX_DRV_ERR1_TXQPEND BIT(26)
+#define ALX_DRV_ERR1_DMAW BIT(25)
+#define ALX_DRV_ERR1_DMAR BIT(24)
+#define ALX_DRV_ERR1_PCIELNKDWN BIT(23)
+#define ALX_DRV_ERR1_PKTSIZE BIT(22)
+#define ALX_DRV_ERR1_FIFOFUL BIT(21)
+#define ALX_DRV_ERR1_RFDUR BIT(20)
+#define ALX_DRV_ERR1_RRDSI BIT(19)
+#define ALX_DRV_ERR1_UPDATE BIT(18)
+
+#define ALX_DRV_ERR2 0x180C
+
+#define ALX_DBG_ADDR 0x1900
+#define ALX_DBG_DATA 0x1904
+
+#define ALX_SYNC_IPV4_SA 0x1A00
+#define ALX_SYNC_IPV4_DA 0x1A04
+
+#define ALX_SYNC_V4PORT 0x1A08
+#define ALX_SYNC_V4PORT_DST_MASK 0xFFFFUL
+#define ALX_SYNC_V4PORT_DST_SHIFT 16
+#define ALX_SYNC_V4PORT_SRC_MASK 0xFFFFUL
+#define ALX_SYNC_V4PORT_SRC_SHIFT 0
+
+#define ALX_SYNC_IPV6_SA0 0x1A0C
+#define ALX_SYNC_IPV6_SA1 0x1A10
+#define ALX_SYNC_IPV6_SA2 0x1A14
+#define ALX_SYNC_IPV6_SA3 0x1A18
+#define ALX_SYNC_IPV6_DA0 0x1A1C
+#define ALX_SYNC_IPV6_DA1 0x1A20
+#define ALX_SYNC_IPV6_DA2 0x1A24
+#define ALX_SYNC_IPV6_DA3 0x1A28
+
+#define ALX_SYNC_V6PORT 0x1A2C
+#define ALX_SYNC_V6PORT_DST_MASK 0xFFFFUL
+#define ALX_SYNC_V6PORT_DST_SHIFT 16
+#define ALX_SYNC_V6PORT_SRC_MASK 0xFFFFUL
+#define ALX_SYNC_V6PORT_SRC_SHIFT 0
+
+#define ALX_ARP_REMOTE_IPV4 0x1A30
+#define ALX_ARP_HOST_IPV4 0x1A34
+#define ALX_ARP_MAC0 0x1A38
+#define ALX_ARP_MAC1 0x1A3C
+
+#define ALX_1ST_REMOTE_IPV6_0 0x1A40
+#define ALX_1ST_REMOTE_IPV6_1 0x1A44
+#define ALX_1ST_REMOTE_IPV6_2 0x1A48
+#define ALX_1ST_REMOTE_IPV6_3 0x1A4C
+
+#define ALX_1ST_SN_IPV6_0 0x1A50
+#define ALX_1ST_SN_IPV6_1 0x1A54
+#define ALX_1ST_SN_IPV6_2 0x1A58
+#define ALX_1ST_SN_IPV6_3 0x1A5C
+
+#define ALX_1ST_TAR_IPV6_1_0 0x1A60
+#define ALX_1ST_TAR_IPV6_1_1 0x1A64
+#define ALX_1ST_TAR_IPV6_1_2 0x1A68
+#define ALX_1ST_TAR_IPV6_1_3 0x1A6C
+#define ALX_1ST_TAR_IPV6_2_0 0x1A70
+#define ALX_1ST_TAR_IPV6_2_1 0x1A74
+#define ALX_1ST_TAR_IPV6_2_2 0x1A78
+#define ALX_1ST_TAR_IPV6_2_3 0x1A7C
+
+#define ALX_2ND_REMOTE_IPV6_0 0x1A80
+#define ALX_2ND_REMOTE_IPV6_1 0x1A84
+#define ALX_2ND_REMOTE_IPV6_2 0x1A88
+#define ALX_2ND_REMOTE_IPV6_3 0x1A8C
+
+#define ALX_2ND_SN_IPV6_0 0x1A90
+#define ALX_2ND_SN_IPV6_1 0x1A94
+#define ALX_2ND_SN_IPV6_2 0x1A98
+#define ALX_2ND_SN_IPV6_3 0x1A9C
+
+#define ALX_2ND_TAR_IPV6_1_0 0x1AA0
+#define ALX_2ND_TAR_IPV6_1_1 0x1AA4
+#define ALX_2ND_TAR_IPV6_1_2 0x1AA8
+#define ALX_2ND_TAR_IPV6_1_3 0x1AAC
+#define ALX_2ND_TAR_IPV6_2_0 0x1AB0
+#define ALX_2ND_TAR_IPV6_2_1 0x1AB4
+#define ALX_2ND_TAR_IPV6_2_2 0x1AB8
+#define ALX_2ND_TAR_IPV6_2_3 0x1ABC
+
+#define ALX_1ST_NS_MAC0 0x1AC0
+#define ALX_1ST_NS_MAC1 0x1AC4
+
+#define ALX_2ND_NS_MAC0 0x1AC8
+#define ALX_2ND_NS_MAC1 0x1ACC
+
+#define ALX_PMOFLD 0x144C
+/* bit[11:10]: for B0+ */
+#define ALX_PMOFLD_ECMA_IGNR_FRG_SSSR BIT(11)
+#define ALX_PMOFLD_ARP_CNFLCT_WAKEUP BIT(10)
+#define ALX_PMOFLD_MULTI_SOLD BIT(9)
+#define ALX_PMOFLD_ICMP_XSUM BIT(8)
+#define ALX_PMOFLD_GARP_REPLY BIT(7)
+#define ALX_PMOFLD_SYNCV6_ANY BIT(6)
+#define ALX_PMOFLD_SYNCV4_ANY BIT(5)
+#define ALX_PMOFLD_BY_HW BIT(4)
+#define ALX_PMOFLD_NS_EN BIT(3)
+#define ALX_PMOFLD_ARP_EN BIT(2)
+#define ALX_PMOFLD_SYNCV6_EN BIT(1)
+#define ALX_PMOFLD_SYNCV4_EN BIT(0)
+
+#define ALX_RSS_KEY0 0x14B0
+#define ALX_RSS_KEY1 0x14B4
+#define ALX_RSS_KEY2 0x14B8
+#define ALX_RSS_KEY3 0x14BC
+#define ALX_RSS_KEY4 0x14C0
+#define ALX_RSS_KEY5 0x14C4
+#define ALX_RSS_KEY6 0x14C8
+#define ALX_RSS_KEY7 0x14CC
+#define ALX_RSS_KEY8 0x14D0
+#define ALX_RSS_KEY9 0x14D4
+
+#define ALX_RSS_IDT_TBL0 0x1B00
+#define ALX_RSS_IDT_TBL1 0x1B04
+#define ALX_RSS_IDT_TBL2 0x1B08
+#define ALX_RSS_IDT_TBL3 0x1B0C
+#define ALX_RSS_IDT_TBL4 0x1B10
+#define ALX_RSS_IDT_TBL5 0x1B14
+#define ALX_RSS_IDT_TBL6 0x1B18
+#define ALX_RSS_IDT_TBL7 0x1B1C
+#define ALX_RSS_IDT_TBL8 0x1B20
+#define ALX_RSS_IDT_TBL9 0x1B24
+#define ALX_RSS_IDT_TBL10 0x1B28
+#define ALX_RSS_IDT_TBL11 0x1B2C
+#define ALX_RSS_IDT_TBL12 0x1B30
+#define ALX_RSS_IDT_TBL13 0x1B34
+#define ALX_RSS_IDT_TBL14 0x1B38
+#define ALX_RSS_IDT_TBL15 0x1B3C
+#define ALX_RSS_IDT_TBL16 0x1B40
+#define ALX_RSS_IDT_TBL17 0x1B44
+#define ALX_RSS_IDT_TBL18 0x1B48
+#define ALX_RSS_IDT_TBL19 0x1B4C
+#define ALX_RSS_IDT_TBL20 0x1B50
+#define ALX_RSS_IDT_TBL21 0x1B54
+#define ALX_RSS_IDT_TBL22 0x1B58
+#define ALX_RSS_IDT_TBL23 0x1B5C
+#define ALX_RSS_IDT_TBL24 0x1B60
+#define ALX_RSS_IDT_TBL25 0x1B64
+#define ALX_RSS_IDT_TBL26 0x1B68
+#define ALX_RSS_IDT_TBL27 0x1B6C
+#define ALX_RSS_IDT_TBL28 0x1B70
+#define ALX_RSS_IDT_TBL29 0x1B74
+#define ALX_RSS_IDT_TBL30 0x1B78
+#define ALX_RSS_IDT_TBL31 0x1B7C
+
+#define ALX_RSS_HASH_VAL 0x15B0
+#define ALX_RSS_HASH_FLAG 0x15B4
+
+#define ALX_RSS_BASE_CPU_NUM 0x15B8
+
+#define ALX_MSI_MAP_TBL1 0x15D0
+#define ALX_MSI_MAP_TBL1_ALERT_MASK 0xFUL
+#define ALX_MSI_MAP_TBL1_ALERT_SHIFT 28
+#define ALX_MSI_MAP_TBL1_TIMER_MASK 0xFUL
+#define ALX_MSI_MAP_TBL1_TIMER_SHIFT 24
+#define ALX_MSI_MAP_TBL1_TXQ1_MASK 0xFUL
+#define ALX_MSI_MAP_TBL1_TXQ1_SHIFT 20
+#define ALX_MSI_MAP_TBL1_TXQ0_MASK 0xFUL
+#define ALX_MSI_MAP_TBL1_TXQ0_SHIFT 16
+#define ALX_MSI_MAP_TBL1_RXQ3_MASK 0xFUL
+#define ALX_MSI_MAP_TBL1_RXQ3_SHIFT 12
+#define ALX_MSI_MAP_TBL1_RXQ2_MASK 0xFUL
+#define ALX_MSI_MAP_TBL1_RXQ2_SHIFT 8
+#define ALX_MSI_MAP_TBL1_RXQ1_MASK 0xFUL
+#define ALX_MSI_MAP_TBL1_RXQ1_SHIFT 4
+#define ALX_MSI_MAP_TBL1_RXQ0_MASK 0xFUL
+#define ALX_MSI_MAP_TBL1_RXQ0_SHIFT 0
+
+#define ALX_MSI_MAP_TBL2 0x15D8
+#define ALX_MSI_MAP_TBL2_PHY_MASK 0xFUL
+#define ALX_MSI_MAP_TBL2_PHY_SHIFT 28
+#define ALX_MSI_MAP_TBL2_SMB_MASK 0xFUL
+#define ALX_MSI_MAP_TBL2_SMB_SHIFT 24
+#define ALX_MSI_MAP_TBL2_TXQ3_MASK 0xFUL
+#define ALX_MSI_MAP_TBL2_TXQ3_SHIFT 20
+#define ALX_MSI_MAP_TBL2_TXQ2_MASK 0xFUL
+#define ALX_MSI_MAP_TBL2_TXQ2_SHIFT 16
+#define ALX_MSI_MAP_TBL2_RXQ7_MASK 0xFUL
+#define ALX_MSI_MAP_TBL2_RXQ7_SHIFT 12
+#define ALX_MSI_MAP_TBL2_RXQ6_MASK 0xFUL
+#define ALX_MSI_MAP_TBL2_RXQ6_SHIFT 8
+#define ALX_MSI_MAP_TBL2_RXQ5_MASK 0xFUL
+#define ALX_MSI_MAP_TBL2_RXQ5_SHIFT 4
+#define ALX_MSI_MAP_TBL2_RXQ4_MASK 0xFUL
+#define ALX_MSI_MAP_TBL2_RXQ4_SHIFT 0
+
+#define ALX_MSI_ID_MAP 0x15D4
+#define ALX_MSI_ID_MAP_RXQ7 BIT(30)
+#define ALX_MSI_ID_MAP_RXQ6 BIT(29)
+#define ALX_MSI_ID_MAP_RXQ5 BIT(28)
+#define ALX_MSI_ID_MAP_RXQ4 BIT(27)
+/* bit26: 0:common,1:timer */
+#define ALX_MSI_ID_MAP_PCIELNKDW BIT(26)
+#define ALX_MSI_ID_MAP_PCIECERR BIT(25)
+#define ALX_MSI_ID_MAP_PCIENFERR BIT(24)
+#define ALX_MSI_ID_MAP_PCIEFERR BIT(23)
+#define ALX_MSI_ID_MAP_PCIEUR BIT(22)
+#define ALX_MSI_ID_MAP_MACTX BIT(21)
+#define ALX_MSI_ID_MAP_MACRX BIT(20)
+#define ALX_MSI_ID_MAP_RXQ3 BIT(19)
+#define ALX_MSI_ID_MAP_RXQ2 BIT(18)
+#define ALX_MSI_ID_MAP_RXQ1 BIT(17)
+#define ALX_MSI_ID_MAP_RXQ0 BIT(16)
+#define ALX_MSI_ID_MAP_TXQ0 BIT(15)
+#define ALX_MSI_ID_MAP_TXQTO BIT(14)
+#define ALX_MSI_ID_MAP_LPW BIT(13)
+#define ALX_MSI_ID_MAP_PHY BIT(12)
+#define ALX_MSI_ID_MAP_TXCREDIT BIT(11)
+#define ALX_MSI_ID_MAP_DMAW BIT(10)
+#define ALX_MSI_ID_MAP_DMAR BIT(9)
+#define ALX_MSI_ID_MAP_TXFUR BIT(8)
+#define ALX_MSI_ID_MAP_TXQ3 BIT(7)
+#define ALX_MSI_ID_MAP_TXQ2 BIT(6)
+#define ALX_MSI_ID_MAP_TXQ1 BIT(5)
+#define ALX_MSI_ID_MAP_RFDUR BIT(4)
+#define ALX_MSI_ID_MAP_RXFOV BIT(3)
+#define ALX_MSI_ID_MAP_MANU BIT(2)
+#define ALX_MSI_ID_MAP_TIMER BIT(1)
+#define ALX_MSI_ID_MAP_SMB BIT(0)
+
+#define ALX_MSI_RETRANS_TIMER 0x1920
+/* bit16: 1:line,0:standard */
+#define ALX_MSI_MASK_SEL_LINE BIT(16)
+#define ALX_MSI_RETRANS_TM_MASK 0xFFFFUL
+#define ALX_MSI_RETRANS_TM_SHIFT 0
+
+#define ALX_CR_DMA_CTRL 0x1930
+#define ALX_CR_DMA_CTRL_PRI BIT(22)
+#define ALX_CR_DMA_CTRL_RRDRXD_JOINT BIT(21)
+#define ALX_CR_DMA_CTRL_BWCREDIT_MASK 0x3UL
+#define ALX_CR_DMA_CTRL_BWCREDIT_SHIFT 19
+#define ALX_CR_DMA_CTRL_BWCREDIT_2KB 0
+#define ALX_CR_DMA_CTRL_BWCREDIT_1KB 1
+#define ALX_CR_DMA_CTRL_BWCREDIT_4KB 2
+#define ALX_CR_DMA_CTRL_BWCREDIT_8KB 3
+#define ALX_CR_DMA_CTRL_BW_EN BIT(18)
+#define ALX_CR_DMA_CTRL_BW_RATIO_MASK 0x3UL
+#define ALX_CR_DMA_CTRL_BW_RATIO_1_2 0
+#define ALX_CR_DMA_CTRL_BW_RATIO_1_4 1
+#define ALX_CR_DMA_CTRL_BW_RATIO_1_8 2
+#define ALX_CR_DMA_CTRL_BW_RATIO_2_1 3
+#define ALX_CR_DMA_CTRL_SOFT_RST BIT(11)
+#define ALX_CR_DMA_CTRL_TXEARLY_EN BIT(10)
+#define ALX_CR_DMA_CTRL_RXEARLY_EN BIT(9)
+#define ALX_CR_DMA_CTRL_WEARLY_EN BIT(8)
+#define ALX_CR_DMA_CTRL_RXTH_MASK 0xFUL
+#define ALX_CR_DMA_CTRL_WTH_MASK 0xFUL
+
+
+#define ALX_EFUSE_BIST 0x1934
+#define ALX_EFUSE_BIST_COL_MASK 0x3FUL
+#define ALX_EFUSE_BIST_COL_SHIFT 24
+#define ALX_EFUSE_BIST_ROW_MASK 0x7FUL
+#define ALX_EFUSE_BIST_ROW_SHIFT 12
+#define ALX_EFUSE_BIST_STEP_MASK 0xFUL
+#define ALX_EFUSE_BIST_STEP_SHIFT 8
+#define ALX_EFUSE_BIST_PAT_MASK 0x7UL
+#define ALX_EFUSE_BIST_PAT_SHIFT 4
+#define ALX_EFUSE_BIST_CRITICAL BIT(3)
+#define ALX_EFUSE_BIST_FIXED BIT(2)
+#define ALX_EFUSE_BIST_FAIL BIT(1)
+#define ALX_EFUSE_BIST_NOW BIT(0)
+
+/* CR DMA ctrl */
+
+/* TX QoS */
+#define ALX_WRR 0x1938
+#define ALX_WRR_PRI_MASK 0x3UL
+#define ALX_WRR_PRI_SHIFT 29
+#define ALX_WRR_PRI_RESTRICT_ALL 0
+#define ALX_WRR_PRI_RESTRICT_HI 1
+#define ALX_WRR_PRI_RESTRICT_HI2 2
+#define ALX_WRR_PRI_RESTRICT_NONE 3
+#define ALX_WRR_PRI3_MASK 0x1FUL
+#define ALX_WRR_PRI3_SHIFT 24
+#define ALX_WRR_PRI2_MASK 0x1FUL
+#define ALX_WRR_PRI2_SHIFT 16
+#define ALX_WRR_PRI1_MASK 0x1FUL
+#define ALX_WRR_PRI1_SHIFT 8
+#define ALX_WRR_PRI0_MASK 0x1FUL
+#define ALX_WRR_PRI0_SHIFT 0
+
+#define ALX_HQTPD 0x193C
+#define ALX_HQTPD_BURST_EN BIT(31)
+#define ALX_HQTPD_Q3_NUMPREF_MASK 0xFUL
+#define ALX_HQTPD_Q3_NUMPREF_SHIFT 8
+#define ALX_HQTPD_Q2_NUMPREF_MASK 0xFUL
+#define ALX_HQTPD_Q2_NUMPREF_SHIFT 4
+#define ALX_HQTPD_Q1_NUMPREF_MASK 0xFUL
+#define ALX_HQTPD_Q1_NUMPREF_SHIFT 0
+
+#define ALX_CPUMAP1 0x19A0
+#define ALX_CPUMAP1_VCT7_MASK 0xFUL
+#define ALX_CPUMAP1_VCT7_SHIFT 28
+#define ALX_CPUMAP1_VCT6_MASK 0xFUL
+#define ALX_CPUMAP1_VCT6_SHIFT 24
+#define ALX_CPUMAP1_VCT5_MASK 0xFUL
+#define ALX_CPUMAP1_VCT5_SHIFT 20
+#define ALX_CPUMAP1_VCT4_MASK 0xFUL
+#define ALX_CPUMAP1_VCT4_SHIFT 16
+#define ALX_CPUMAP1_VCT3_MASK 0xFUL
+#define ALX_CPUMAP1_VCT3_SHIFT 12
+#define ALX_CPUMAP1_VCT2_MASK 0xFUL
+#define ALX_CPUMAP1_VCT2_SHIFT 8
+#define ALX_CPUMAP1_VCT1_MASK 0xFUL
+#define ALX_CPUMAP1_VCT1_SHIFT 4
+#define ALX_CPUMAP1_VCT0_MASK 0xFUL
+#define ALX_CPUMAP1_VCT0_SHIFT 0
+
+#define ALX_CPUMAP2 0x19A4
+#define ALX_CPUMAP2_VCT15_MASK 0xFUL
+#define ALX_CPUMAP2_VCT15_SHIFT 28
+#define ALX_CPUMAP2_VCT14_MASK 0xFUL
+#define ALX_CPUMAP2_VCT14_SHIFT 24
+#define ALX_CPUMAP2_VCT13_MASK 0xFUL
+#define ALX_CPUMAP2_VCT13_SHIFT 20
+#define ALX_CPUMAP2_VCT12_MASK 0xFUL
+#define ALX_CPUMAP2_VCT12_SHIFT 16
+#define ALX_CPUMAP2_VCT11_MASK 0xFUL
+#define ALX_CPUMAP2_VCT11_SHIFT 12
+#define ALX_CPUMAP2_VCT10_MASK 0xFUL
+#define ALX_CPUMAP2_VCT10_SHIFT 8
+#define ALX_CPUMAP2_VCT9_MASK 0xFUL
+#define ALX_CPUMAP2_VCT9_SHIFT 4
+#define ALX_CPUMAP2_VCT8_MASK 0xFUL
+#define ALX_CPUMAP2_VCT8_SHIFT 0
+
+#define ALX_MISC 0x19C0
+/* bit31: 0:vector,1:cpu */
+#define ALX_MISC_MODU BIT(31)
+#define ALX_MISC_OVERCUR BIT(29)
+#define ALX_MISC_PSWR_EN BIT(28)
+#define ALX_MISC_PSW_CTRL_MASK 0xFUL
+#define ALX_MISC_PSW_CTRL_SHIFT 24
+#define ALX_MISC_PSW_OCP_MASK 0x7UL
+#define ALX_MISC_PSW_OCP_SHIFT 21
+#define ALX_MISC_PSW_OCP_DEF 0x7
+#define ALX_MISC_V18_HIGH BIT(20)
+#define ALX_MISC_LPO_CTRL_MASK 0xFUL
+#define ALX_MISC_LPO_CTRL_SHIFT 16
+#define ALX_MISC_ISO_EN BIT(12)
+#define ALX_MISC_XSTANA_ALWAYS_ON BIT(11)
+#define ALX_MISC_SYS25M_SEL_ADAPTIVE BIT(10)
+#define ALX_MISC_SPEED_SIM BIT(9)
+#define ALX_MISC_S1_LWP_EN BIT(8)
+/* bit7: pcie/mac do pwsaving as phy in lpw state */
+#define ALX_MISC_MACLPW BIT(7)
+#define ALX_MISC_125M_SW BIT(6)
+#define ALX_MISC_INTNLOSC_OFF_EN BIT(5)
+/* bit4: 0:chipset,1:crystle */
+#define ALX_MISC_EXTN25M_SEL BIT(4)
+#define ALX_MISC_INTNLOSC_OPEN BIT(3)
+#define ALX_MISC_SMBUS_AT_LED BIT(2)
+#define ALX_MISC_PPS_AT_LED_MASK 0x3UL
+#define ALX_MISC_PPS_AT_LED_SHIFT 0
+#define ALX_MISC_PPS_AT_LED_ACT 1
+#define ALX_MISC_PPS_AT_LED_10_100 2
+#define ALX_MISC_PPS_AT_LED_1000 3
+
+#define ALX_MISC1 0x19C4
+#define ALX_MSC1_BLK_CRASPM_REQ BIT(15)
+
+#define ALX_MSIC2 0x19C8
+#define ALX_MSIC2_CALB_START BIT(0)
+
+#define ALX_MISC3 0x19CC
+/* bit1: 1:Software control 25M */
+#define ALX_MISC3_25M_BY_SW BIT(1)
+/* bit0: 25M switch to intnl OSC */
+#define ALX_MISC3_25M_NOTO_INTNL BIT(0)
+
+/* MSIX tbl in memory space */
+#define ALX_MSIX_ENTRY_BASE 0x2000
+
+/***************************** IO mapping registers ***************************/
+#define ALX_IO_ADDR 0x00
+#define ALX_IO_DATA 0x04
+/* same as reg1400 */
+#define ALX_IO_MASTER 0x08
+/* same as reg1480 */
+#define ALX_IO_MAC_CTRL 0x0C
+/* same as reg1600 */
+#define ALX_IO_ISR 0x10
+/* same as reg 1604 */
+#define ALX_IO_IMR 0x14
+/* word, same as reg15F0 */
+#define ALX_IO_TPD_PRI1_PIDX 0x18
+/* word, same as reg15F2 */
+#define ALX_IO_TPD_PRI0_PIDX 0x1A
+/* word, same as reg15F4 */
+#define ALX_IO_TPD_PRI1_CIDX 0x1C
+/* word, same as reg15F6 */
+#define ALX_IO_TPD_PRI0_CIDX 0x1E
+/* word, same as reg15E0 */
+#define ALX_IO_RFD_PIDX 0x20
+/* word, same as reg15F8 */
+#define ALX_IO_RFD_CIDX 0x30
+/* same as reg1414 */
+#define ALX_IO_MDIO 0x38
+/* same as reg140C */
+#define ALX_IO_PHY_CTRL 0x3C
+
+
+/********************* PHY regs definition ***************************/
+
+/* Autoneg Advertisement Register */
+#define ALX_ADVERTISE_SPEED_MASK 0x01E0
+#define ALX_ADVERTISE_DEFAULT_CAP 0x1DE0
+
+/* 1000BASE-T Control Register (0x9) */
+#define ALX_GIGA_CR_1000T_HD_CAPS 0x0100
+#define ALX_GIGA_CR_1000T_FD_CAPS 0x0200
+#define ALX_GIGA_CR_1000T_REPEATER_DTE 0x0400
+
+#define ALX_GIGA_CR_1000T_MS_VALUE 0x0800
+
+#define ALX_GIGA_CR_1000T_MS_ENABLE 0x1000
+
+#define ALX_GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000
+#define ALX_GIGA_CR_1000T_TEST_MODE_1 0x2000
+#define ALX_GIGA_CR_1000T_TEST_MODE_2 0x4000
+#define ALX_GIGA_CR_1000T_TEST_MODE_3 0x6000
+#define ALX_GIGA_CR_1000T_TEST_MODE_4 0x8000
+#define ALX_GIGA_CR_1000T_SPEED_MASK 0x0300
+#define ALX_GIGA_CR_1000T_DEFAULT_CAP 0x0300
+
+/* 1000BASE-T Status Register */
+#define ALX_MII_GIGA_SR 0x0A
+
+/* PHY Specific Status Register */
+#define ALX_MII_GIGA_PSSR 0x11
+#define ALX_GIGA_PSSR_FC_RXEN 0x0004
+#define ALX_GIGA_PSSR_FC_TXEN 0x0008
+#define ALX_GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800
+#define ALX_GIGA_PSSR_DPLX 0x2000
+#define ALX_GIGA_PSSR_SPEED 0xC000
+#define ALX_GIGA_PSSR_10MBS 0x0000
+#define ALX_GIGA_PSSR_100MBS 0x4000
+#define ALX_GIGA_PSSR_1000MBS 0x8000
+
+/* PHY Interrupt Enable Register */
+#define ALX_MII_IER 0x12
+#define ALX_IER_LINK_UP 0x0400
+#define ALX_IER_LINK_DOWN 0x0800
+
+/* PHY Interrupt Status Register */
+#define ALX_MII_ISR 0x13
+#define ALX_ISR_LINK_UP 0x0400
+#define ALX_ISR_LINK_DOWN 0x0800
+
+/* Cable-Detect-Test Control Register */
+#define ALX_MII_CDTC 0x16
+/* self clear */
+#define ALX_CDTC_EN 1
+#define ALX_CDTC_PAIR_MASK 0x3U
+#define ALX_CDTC_PAIR_SHIFT 8
+
+
+/* Cable-Detect-Test Status Register */
+#define ALX_MII_CDTS 0x1C
+#define ALX_CDTS_STATUS_MASK 0x3U
+#define ALX_CDTS_STATUS_SHIFT 8
+#define ALX_CDTS_STATUS_NORMAL 0
+#define ALX_CDTS_STATUS_SHORT 1
+#define ALX_CDTS_STATUS_OPEN 2
+#define ALX_CDTS_STATUS_INVALID 3
+
+#define ALX_MII_DBG_ADDR 0x1D
+#define ALX_MII_DBG_DATA 0x1E
+
+/***************************** debug port *************************************/
+
+#define ALX_MIIDBG_ANACTRL 0x00
+#define ALX_ANACTRL_CLK125M_DELAY_EN 0x8000
+#define ALX_ANACTRL_VCO_FAST 0x4000
+#define ALX_ANACTRL_VCO_SLOW 0x2000
+#define ALX_ANACTRL_AFE_MODE_EN 0x1000
+#define ALX_ANACTRL_LCKDET_PHY 0x0800
+#define ALX_ANACTRL_LCKDET_EN 0x0400
+#define ALX_ANACTRL_OEN_125M 0x0200
+#define ALX_ANACTRL_HBIAS_EN 0x0100
+#define ALX_ANACTRL_HB_EN 0x0080
+#define ALX_ANACTRL_SEL_HSP 0x0040
+#define ALX_ANACTRL_CLASSA_EN 0x0020
+#define ALX_ANACTRL_MANUSWON_SWR_MASK 0x3U
+#define ALX_ANACTRL_MANUSWON_SWR_SHIFT 2
+#define ALX_ANACTRL_MANUSWON_SWR_2V 0
+#define ALX_ANACTRL_MANUSWON_SWR_1P9V 1
+#define ALX_ANACTRL_MANUSWON_SWR_1P8V 2
+#define ALX_ANACTRL_MANUSWON_SWR_1P7V 3
+#define ALX_ANACTRL_MANUSWON_BW3_4M 0x0002
+#define ALX_ANACTRL_RESTART_CAL 0x0001
+#define ALX_ANACTRL_DEF 0x02EF
+
+
+#define ALX_MIIDBG_SYSMODCTRL 0x04
+#define ALX_SYSMODCTRL_IECHOADJ_PFMH_PHY 0x8000
+#define ALX_SYSMODCTRL_IECHOADJ_BIASGEN 0x4000
+#define ALX_SYSMODCTRL_IECHOADJ_PFML_PHY 0x2000
+#define ALX_SYSMODCTRL_IECHOADJ_PS_MASK 0x3U
+#define ALX_SYSMODCTRL_IECHOADJ_PS_SHIFT 10
+#define ALX_SYSMODCTRL_IECHOADJ_PS_40 3
+#define ALX_SYSMODCTRL_IECHOADJ_PS_20 2
+#define ALX_SYSMODCTRL_IECHOADJ_PS_0 1
+#define ALX_SYSMODCTRL_IECHOADJ_10BT_100MV 0x0040
+#define ALX_SYSMODCTRL_IECHOADJ_HLFAP_MASK 0x3U
+#define ALX_SYSMODCTRL_IECHOADJ_HLFAP_SHIFT 4
+#define ALX_SYSMODCTRL_IECHOADJ_VDFULBW 0x0008
+#define ALX_SYSMODCTRL_IECHOADJ_VDBIASHLF 0x0004
+#define ALX_SYSMODCTRL_IECHOADJ_VDAMPHLF 0x0002
+#define ALX_SYSMODCTRL_IECHOADJ_VDLANSW 0x0001
+/* en half bias */
+#define ALX_SYSMODCTRL_IECHOADJ_DEF 0xBB8B
+
+
+#define ALX_MIIDBG_SRDSYSMOD 0x05
+#define ALX_SRDSYSMOD_LCKDET_EN 0x2000
+#define ALX_SRDSYSMOD_PLL_EN 0x0800
+#define ALX_SRDSYSMOD_SEL_HSP 0x0400
+#define ALX_SRDSYSMOD_HLFTXDR 0x0200
+#define ALX_SRDSYSMOD_TXCLK_DELAY_EN 0x0100
+#define ALX_SRDSYSMOD_TXELECIDLE 0x0080
+#define ALX_SRDSYSMOD_DEEMP_EN 0x0040
+#define ALX_SRDSYSMOD_MS_PAD 0x0004
+#define ALX_SRDSYSMOD_CDR_ADC_VLTG 0x0002
+#define ALX_SRDSYSMOD_CDR_DAC_1MA 0x0001
+#define ALX_SRDSYSMOD_DEF 0x2C46
+
+
+#define ALX_MIIDBG_HIBNEG 0x0B
+#define ALX_HIBNEG_PSHIB_EN 0x8000
+#define ALX_HIBNEG_WAKE_BOTH 0x4000
+#define ALX_HIBNEG_ONOFF_ANACHG_SUDEN 0x2000
+#define ALX_HIBNEG_HIB_PULSE 0x1000
+#define ALX_HIBNEG_GATE_25M_EN 0x0800
+#define ALX_HIBNEG_RST_80U 0x0400
+#define ALX_HIBNEG_RST_TIMER_MASK 0x3U
+#define ALX_HIBNEG_RST_TIMER_SHIFT 8
+#define ALX_HIBNEG_GTX_CLK_DELAY_MASK 0x3U
+#define ALX_HIBNEG_GTX_CLK_DELAY_SHIFT 5
+#define ALX_HIBNEG_BYPSS_BRKTIMER 0x0010
+#define ALX_HIBNEG_DEF 0xBC40
+#define ALX_HIBNEG_NOHIB (\
+ALX_HIBNEG_DEF & ~(ALX_HIBNEG_PSHIB_EN | ALX_HIBNEG_HIB_PULSE))
+
+#define ALX_MIIDBG_TST10BTCFG 0x12
+#define ALX_TST10BTCFG_INTV_TIMER_MASK 0x3U
+#define ALX_TST10BTCFG_INTV_TIMER_SHIFT 14
+#define ALX_TST10BTCFG_TRIGER_TIMER_MASK 0x3U
+#define ALX_TST10BTCFG_TRIGER_TIMER_SHIFT 12
+#define ALX_TST10BTCFG_DIV_MAN_MLT3_EN 0x0800
+#define ALX_TST10BTCFG_OFF_DAC_IDLE 0x0400
+#define ALX_TST10BTCFG_LPBK_DEEP 0x0004
+#define ALX_TST10BTCFG_DEF 0x4C04
+
+#define ALX_MIIDBG_AZ_ANADECT 0x15
+#define ALX_AZ_ANADECT_10BTRX_TH 0x8000
+#define ALX_AZ_ANADECT_BOTH_01CHNL 0x4000
+#define ALX_AZ_ANADECT_INTV_MASK 0x3FU
+#define ALX_AZ_ANADECT_INTV_SHIFT 8
+#define ALX_AZ_ANADECT_THRESH_MASK 0xFU
+#define ALX_AZ_ANADECT_THRESH_SHIFT 4
+#define ALX_AZ_ANADECT_CHNL_MASK 0xFU
+#define ALX_AZ_ANADECT_CHNL_SHIFT 0
+#define ALX_AZ_ANADECT_DEF 0x3220
+#define ALX_AZ_ANADECT_LONG 0x3210
+
+#define ALX_MIIDBG_MSE16DB 0x18
+#define ALX_MSE16DB_UP 0x05EA
+#define ALX_MSE16DB_DOWN 0x02EA
+
+#define ALX_MIIDBG_MSE20DB 0x1C
+#define ALX_MSE20DB_TH_MASK 0x7F
+#define ALX_MSE20DB_TH_SHIFT 2
+#define ALX_MSE20DB_TH_DEF 0x2E
+#define ALX_MSE20DB_TH_HI 0x54
+
+#define ALX_MIIDBG_AGC 0x23
+#define ALX_AGC_2_VGA_MASK 0x3FU
+#define ALX_AGC_2_VGA_SHIFT 8
+#define ALX_AGC_LONG1G_LIMT 40
+#define ALX_AGC_LONG100M_LIMT 44
+
+#define ALX_MIIDBG_LEGCYPS 0x29
+#define ALX_LEGCYPS_EN 0x8000
+#define ALX_LEGCYPS_DAC_AMP1000_MASK 0x7U
+#define ALX_LEGCYPS_DAC_AMP1000_SHIFT 12
+#define ALX_LEGCYPS_DAC_AMP100_MASK 0x7U
+#define ALX_LEGCYPS_DAC_AMP100_SHIFT 9
+#define ALX_LEGCYPS_DAC_AMP10_MASK 0x7U
+#define ALX_LEGCYPS_DAC_AMP10_SHIFT 6
+#define ALX_LEGCYPS_UNPLUG_TIMER_MASK 0x7U
+#define ALX_LEGCYPS_UNPLUG_TIMER_SHIFT 3
+#define ALX_LEGCYPS_UNPLUG_DECT_EN 0x0004
+#define ALX_LEGCYPS_ECNC_PS_EN 0x0001
+#define ALX_LEGCYPS_DEF 0x129D
+
+#define ALX_MIIDBG_TST100BTCFG 0x36
+#define ALX_TST100BTCFG_NORMAL_BW_EN 0x8000
+#define ALX_TST100BTCFG_BADLNK_BYPASS 0x4000
+#define ALX_TST100BTCFG_SHORTCABL_TH_MASK 0x3FU
+#define ALX_TST100BTCFG_SHORTCABL_TH_SHIFT 8
+#define ALX_TST100BTCFG_LITCH_EN 0x0080
+#define ALX_TST100BTCFG_VLT_SW 0x0040
+#define ALX_TST100BTCFG_LONGCABL_TH_MASK 0x3FU
+#define ALX_TST100BTCFG_LONGCABL_TH_SHIFT 0
+#define ALX_TST100BTCFG_DEF 0xE12C
+
+#define ALX_MIIDBG_GREENCFG 0x3B
+#define ALX_GREENCFG_MSTPS_MSETH2_MASK 0xFFU
+#define ALX_GREENCFG_MSTPS_MSETH2_SHIFT 8
+#define ALX_GREENCFG_MSTPS_MSETH1_MASK 0xFFU
+#define ALX_GREENCFG_MSTPS_MSETH1_SHIFT 0
+#define ALX_GREENCFG_DEF 0x7078
+
+#define ALX_MIIDBG_GREENCFG2 0x3D
+#define ALX_GREENCFG2_BP_GREEN 0x8000
+#define ALX_GREENCFG2_GATE_DFSE_EN 0x0080
+
+
+/***************************** extension **************************************/
+
+/******* dev 3 *********/
+#define ALX_MIIEXT_PCS 3
+
+#define ALX_MIIEXT_CLDCTRL3 0x8003
+#define ALX_CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000
+#define ALX_CLDCTRL3_AZ_DISAMP 0x1000
+
+#define ALX_MIIEXT_CLDCTRL5 0x8005
+#define ALX_CLDCTRL5_BP_VD_HLFBIAS 0x4000
+
+#define ALX_MIIEXT_CLDCTRL6 0x8006
+#define ALX_CLDCTRL6_CAB_LEN_MASK 0xFFU
+#define ALX_CLDCTRL6_CAB_LEN_SHIFT 0
+#define ALX_CLDCTRL6_CAB_LEN_SHORT1G 116
+#define ALX_CLDCTRL6_CAB_LEN_SHORT100M 152
+
+#define ALX_MIIEXT_CLDCTRL7 0x8007
+#define ALX_CLDCTRL7_VDHLF_BIAS_TH_MASK 0x7FU
+#define ALX_CLDCTRL7_VDHLF_BIAS_TH_SHIFT 9
+#define ALX_CLDCTRL7_AFE_AZ_MASK 0x1FU
+#define ALX_CLDCTRL7_AFE_AZ_SHIFT 4
+#define ALX_CLDCTRL7_SIDE_PEAK_TH_MASK 0xFU
+#define ALX_CLDCTRL7_SIDE_PEAK_TH_SHIFT 0
+#define ALX_CLDCTRL7_DEF 0x6BF6
+
+#define ALX_MIIEXT_AZCTRL 0x8008
+#define ALX_AZCTRL_SHORT_TH_MASK 0xFFU
+#define ALX_AZCTRL_SHORT_TH_SHIFT 8
+#define ALX_AZCTRL_LONG_TH_MASK 0xFFU
+#define ALX_AZCTRL_LONG_TH_SHIFT 0
+#define ALX_AZCTRL_DEF 0x1629
+
+#define ALX_MIIEXT_AZCTRL2 0x8009
+#define ALX_AZCTRL2_WAKETRNING_MASK 0xFFU
+#define ALX_AZCTRL2_WAKETRNING_SHIFT 8
+#define ALX_AZCTRL2_QUIET_TIMER_MASK 0x3U
+#define ALX_AZCTRL2_QUIET_TIMER_SHIFT 6
+#define ALX_AZCTRL2_PHAS_JMP2 0x0010
+#define ALX_AZCTRL2_CLKTRCV_125MD16 0x0008
+#define ALX_AZCTRL2_GATE1000_EN 0x0004
+#define ALX_AZCTRL2_AVRG_FREQ 0x0002
+#define ALX_AZCTRL2_PHAS_JMP4 0x0001
+#define ALX_AZCTRL2_DEF 0x32C0
+
+#define ALX_MIIEXT_AZCTRL6 0x800D
+
+#define ALX_MIIEXT_VDRVBIAS 0x8062
+#define ALX_VDRVBIAS_SEL_MASK 0x3U
+#define ALX_VDRVBIAS_SEL_SHIFT 0
+#define ALX_VDRVBIAS_DEF 0x3
+
+/********* dev 7 **********/
+#define ALX_MIIEXT_ANEG 7
+
+#define ALX_MIIEXT_LOCAL_EEEADV 0x3C
+#define ALX_LOCAL_EEEADV_1000BT 0x0004
+#define ALX_LOCAL_EEEADV_100BT 0x0002
+
+#define ALX_MIIEXT_REMOTE_EEEADV 0x3D
+#define ALX_REMOTE_EEEADV_1000BT 0x0004
+#define ALX_REMOTE_EEEADV_100BT 0x0002
+
+#define ALX_MIIEXT_EEE_ANEG 0x8000
+#define ALX_EEE_ANEG_1000M 0x0004
+#define ALX_EEE_ANEG_100M 0x0002
+
+#define ALX_MIIEXT_AFE 0x801A
+#define ALX_AFE_10BT_100M_TH 0x0040
+
+#define ALX_MIIEXT_S3DIG10 0x8023
+/* bit0: 1:bypass 10BT rx fifo, 0:riginal 10BT rx */
+#define ALX_MIIEXT_S3DIG10_SL 0x0001
+#define ALX_MIIEXT_S3DIG10_DEF 0
+
+#define ALX_MIIEXT_NLP34 0x8025
+/* for 160m */
+#define ALX_MIIEXT_NLP34_DEF 0x1010
+
+#define ALX_MIIEXT_NLP56 0x8026
+/* for 160m */
+#define ALX_MIIEXT_NLP56_DEF 0x1010
+
+#define ALX_MIIEXT_NLP78 0x8027
+/* for 160m */
+#define ALX_MIIEXT_NLP78_160M_DEF 0x8D05
+#define ALX_MIIEXT_NLP78_120M_DEF 0x8A05
+
+#endif
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-15 10:16:11 +0000