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| author | Jean-Philippe Brucker <jean-philippe.brucker@arm.com> | 2015-12-04 16:42:42 +0000 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2016-06-14 17:49:43 +0100 |
| commit | fc4857f4292d0dfc40b5c32d80f16d47e27f98cc (patch) | |
| tree | 25e898f9d4c183a3c19eeb3ee2ad2ebbe01a86ea | |
| parent | abd980e0f52240a46f6815001cdf44fa387c2c80 (diff) | |
| download | boot-wrapper-aarch64-fc4857f4292d0dfc40b5c32d80f16d47e27f98cc.tar.gz | |
AArch64: clean common.S
Remove macro drop_el since its only user is now boot.S, and move all
defines to cpu.h.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
| -rw-r--r-- | arch/aarch64/boot.S | 4 | ||||
| -rw-r--r-- | arch/aarch64/common.S | 26 | ||||
| -rw-r--r-- | arch/aarch64/include/asm/cpu.h | 17 |
3 files changed, 20 insertions, 27 deletions
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 67d9294..8bb536f 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -79,7 +79,9 @@ jump_kernel: mov x4, #SPSR_KERNEL adr x5, el2_trampoline - drop_el x4, x5 + msr elr_el3, x5 + msr spsr_el3, x4 + eret el2_trampoline: bl flush_caches diff --git a/arch/aarch64/common.S b/arch/aarch64/common.S index 5a0baa9..c7171a9 100644 --- a/arch/aarch64/common.S +++ b/arch/aarch64/common.S @@ -9,32 +9,6 @@ #include <cpu.h> -#define CURRENTEL_EL3 (3 << 2) - -/* - * RES1 bits, little-endian, caches and MMU off, no alignment checking, - * no WXN. - */ -#define SCTLR_EL2_RESET (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 | 1 << 11 | 3 << 4) - -#define SPSR_A (1 << 8) /* System Error masked */ -#define SPSR_D (1 << 9) /* Debug masked */ -#define SPSR_I (1 << 7) /* IRQ masked */ -#define SPSR_F (1 << 6) /* FIQ masked */ -#define SPSR_EL2H (9 << 0) /* EL2 Handler mode */ - -#define SPSR_KERNEL (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H) - - /* - * Drop EL to that specified by the spsr value in register mode, at - * the address specified in register addr. - */ - .macro drop_el mode addr - msr elr_el3, \addr - msr spsr_el3, \mode - eret - .endm - /* Put MPIDR into \dest, clobber \tmp and flags */ .macro cpuid dest, tmp mrs \dest, mpidr_el1 diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 12f7a08..249ce09 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -11,6 +11,23 @@ #define MPIDR_ID_BITS 0xff00ffffff +#define CURRENTEL_EL3 (3 << 2) + +/* + * RES1 bits, little-endian, caches and MMU off, no alignment checking, + * no WXN. + */ +#define SCTLR_EL2_RESET (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 | 1 << 11 | 3 << 4) + +#define SPSR_A (1 << 8) /* System Error masked */ +#define SPSR_D (1 << 9) /* Debug masked */ +#define SPSR_I (1 << 7) /* IRQ masked */ +#define SPSR_F (1 << 6) /* FIQ masked */ +#define SPSR_T (1 << 5) /* Thumb */ +#define SPSR_EL2H (9 << 0) /* EL2 Handler mode */ + +#define SPSR_KERNEL (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H) + #ifndef __ASSEMBLY__ #define sevl() asm volatile ("sevl\n" : : : "memory") |