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| author | Alexandru Elisei <alexandru.elisei@arm.com> | 2021-08-17 17:34:20 +0100 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2021-08-18 15:12:30 +0100 |
| commit | ada217d48ba82906028042a53f12905c1107addf (patch) | |
| tree | 81121fd5e5abeb31df7d08ef3d5e5b53202ca35a | |
| parent | bc6a9380eb3c5afc96735a54d455f2487df48700 (diff) | |
| download | boot-wrapper-aarch64-ada217d48ba82906028042a53f12905c1107addf.tar.gz | |
aarch64: Do not trap PMSNEVFR_EL1
FEAT_PMUv1p2 adds a new register, PMSNEVFR_EL1, and a new MDCR_EL3 trap bit
for it, EnPMSN. Set the bit to 1 to allow lower exception levels direct
access to the register.
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
[Mark: use ORR (Imm) to enable SPE, use 1f label, re-order comment]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
| -rw-r--r-- | arch/aarch64/boot.S | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 2215f7e..d8d7ccd 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -88,8 +88,12 @@ ASM_FUNC(_start) cbz x1, 1f // Enable SPE for the non-secure world. - ldr x1, =(0x3 << 12) - orr x0, x0, x1 + orr x0, x0, #(0x3 << 12) + + // Do not trap PMSNEVFR_EL1 if present + cmp x1, #3 + b.lt 1f + orr x0, x0, #(1 << 36) 1: mrs x1, id_aa64dfr0_el1 ubfx x1, x1, #44, #4 |