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| author | Marc Zyngier <marc.zyngier@arm.com> | 2014-08-06 15:45:10 +0100 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2014-11-06 17:34:24 +0000 |
| commit | 955cb98c8b6c47dddc4191011ec0c45f51d6da09 (patch) | |
| tree | c0ceaf2db653f8601d0aa9ec2dd34bc5c5c979a5 | |
| parent | 877b6eea207b0d89a236abc152a301cdb5f0d358 (diff) | |
| download | boot-wrapper-aarch64-955cb98c8b6c47dddc4191011ec0c45f51d6da09.tar.gz | |
boot-wrapper: arm64: gicv3: skip GIC init if not available
Rather than exploding very early on, just skip the GICv3 initialization
if no GICv3 CPU interface is reported available.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[Mark: amend comment]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
| -rw-r--r-- | gic-v3.S | 11 |
1 files changed, 11 insertions, 0 deletions
@@ -15,6 +15,16 @@ gic_secure_init: /* + * If GICv3 is not available, skip initialisation. The OS will probably + * fail with a warning, but this should be easier to debug than a + * failure within the boot wrapper. + */ + mrs x0, id_aa64pfr0_el1 + ubfx x0, x0, #24, #4 + cmp x0, #1 + b.ne skip_gicv3 + + /* * Only the primary CPU setups the (re)distributors. */ mrs x0, mpidr_el1 @@ -86,4 +96,5 @@ setup_cpu_if: msr ICC_CTLR_EL3, xzr isb +skip_gicv3: ret |