diff options
author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-08-02 18:41:31 -0700 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-08-02 18:41:31 -0700 |
commit | 2e19797cebcd5b0261310aac3713075b3021a271 (patch) | |
tree | fc5e448320e22163163b9834634c170d6c0b0760 | |
parent | 306e22d431132079c1b5d8eeacfc29c89314a1f5 (diff) | |
download | ltsi-kernel-2e19797cebcd5b0261310aac3713075b3021a271.tar.gz |
Second set of Renesas patches added.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
256 files changed, 23504 insertions, 0 deletions
diff --git a/patches.renesas/0001-drm-bridge-adv7511-Initialize-regulators.patch b/patches.renesas/0001-drm-bridge-adv7511-Initialize-regulators.patch new file mode 100644 index 0000000000000..3126469a3b422 --- /dev/null +++ b/patches.renesas/0001-drm-bridge-adv7511-Initialize-regulators.patch @@ -0,0 +1,194 @@ +From 49d75597cc0116d54a98d1aecd36ae7c90bb4520 Mon Sep 17 00:00:00 2001 +From: Archit Taneja <architt@codeaurora.org> +Date: Wed, 11 Jan 2017 12:22:27 +0530 +Subject: [PATCH 001/255] drm/bridge: adv7511: Initialize regulators + +Maintain a table of regulator names expected by ADV7511 and ADV7533. +Use regulator_bulk_* api to configure these. + +Initialize and enable the regulators during probe itself. Controlling +these dynamically is left for later. + +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/1484117547-26417-3-git-send-email-architt@codeaurora.org +(cherry picked from commit 5b06ba2378e177fdb8f100adda6e55b205308202) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/adv7511/adv7511.h | 4 + + drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 86 ++++++++++++++++++++++++--- + 2 files changed, 81 insertions(+), 9 deletions(-) + +--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h ++++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h +@@ -12,6 +12,7 @@ + #include <linux/hdmi.h> + #include <linux/i2c.h> + #include <linux/regmap.h> ++#include <linux/regulator/consumer.h> + + #include <drm/drm_crtc_helper.h> + #include <drm/drm_mipi_dsi.h> +@@ -329,6 +330,9 @@ struct adv7511 { + + struct gpio_desc *gpio_pd; + ++ struct regulator_bulk_data *supplies; ++ unsigned int num_supplies; ++ + /* ADV7533 DSI RX related params */ + struct device_node *host_node; + struct mipi_dsi_device *dsi; +--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c ++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +@@ -839,6 +839,58 @@ static struct drm_bridge_funcs adv7511_b + * Probe & remove + */ + ++static const char * const adv7511_supply_names[] = { ++ "avdd", ++ "dvdd", ++ "pvdd", ++ "bgvdd", ++ "dvdd-3v", ++}; ++ ++static const char * const adv7533_supply_names[] = { ++ "avdd", ++ "dvdd", ++ "pvdd", ++ "a2vdd", ++ "v3p3", ++ "v1p2", ++}; ++ ++static int adv7511_init_regulators(struct adv7511 *adv) ++{ ++ struct device *dev = &adv->i2c_main->dev; ++ const char * const *supply_names; ++ unsigned int i; ++ int ret; ++ ++ if (adv->type == ADV7511) { ++ supply_names = adv7511_supply_names; ++ adv->num_supplies = ARRAY_SIZE(adv7511_supply_names); ++ } else { ++ supply_names = adv7533_supply_names; ++ adv->num_supplies = ARRAY_SIZE(adv7533_supply_names); ++ } ++ ++ adv->supplies = devm_kcalloc(dev, adv->num_supplies, ++ sizeof(*adv->supplies), GFP_KERNEL); ++ if (!adv->supplies) ++ return -ENOMEM; ++ ++ for (i = 0; i < adv->num_supplies; i++) ++ adv->supplies[i].supply = supply_names[i]; ++ ++ ret = devm_regulator_bulk_get(dev, adv->num_supplies, adv->supplies); ++ if (ret) ++ return ret; ++ ++ return regulator_bulk_enable(adv->num_supplies, adv->supplies); ++} ++ ++static void adv7511_uninit_regulators(struct adv7511 *adv) ++{ ++ regulator_bulk_disable(adv->num_supplies, adv->supplies); ++} ++ + static int adv7511_parse_dt(struct device_node *np, + struct adv7511_link_config *config) + { +@@ -939,6 +991,7 @@ static int adv7511_probe(struct i2c_clie + if (!adv7511) + return -ENOMEM; + ++ adv7511->i2c_main = i2c; + adv7511->powered = false; + adv7511->status = connector_status_disconnected; + +@@ -956,13 +1009,21 @@ static int adv7511_probe(struct i2c_clie + if (ret) + return ret; + ++ ret = adv7511_init_regulators(adv7511); ++ if (ret) { ++ dev_err(dev, "failed to init regulators\n"); ++ return ret; ++ } ++ + /* + * The power down GPIO is optional. If present, toggle it from active to + * inactive to wake up the encoder. + */ + adv7511->gpio_pd = devm_gpiod_get_optional(dev, "pd", GPIOD_OUT_HIGH); +- if (IS_ERR(adv7511->gpio_pd)) +- return PTR_ERR(adv7511->gpio_pd); ++ if (IS_ERR(adv7511->gpio_pd)) { ++ ret = PTR_ERR(adv7511->gpio_pd); ++ goto uninit_regulators; ++ } + + if (adv7511->gpio_pd) { + mdelay(5); +@@ -970,12 +1031,14 @@ static int adv7511_probe(struct i2c_clie + } + + adv7511->regmap = devm_regmap_init_i2c(i2c, &adv7511_regmap_config); +- if (IS_ERR(adv7511->regmap)) +- return PTR_ERR(adv7511->regmap); ++ if (IS_ERR(adv7511->regmap)) { ++ ret = PTR_ERR(adv7511->regmap); ++ goto uninit_regulators; ++ } + + ret = regmap_read(adv7511->regmap, ADV7511_REG_CHIP_REVISION, &val); + if (ret) +- return ret; ++ goto uninit_regulators; + dev_dbg(dev, "Rev. %d\n", val); + + if (adv7511->type == ADV7511) +@@ -985,7 +1048,7 @@ static int adv7511_probe(struct i2c_clie + else + ret = adv7533_patch_registers(adv7511); + if (ret) +- return ret; ++ goto uninit_regulators; + + regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR, edid_i2c_addr); + regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR, +@@ -995,10 +1058,11 @@ static int adv7511_probe(struct i2c_clie + + adv7511_packet_disable(adv7511, 0xffff); + +- adv7511->i2c_main = i2c; + adv7511->i2c_edid = i2c_new_dummy(i2c->adapter, edid_i2c_addr >> 1); +- if (!adv7511->i2c_edid) +- return -ENOMEM; ++ if (!adv7511->i2c_edid) { ++ ret = -ENOMEM; ++ goto uninit_regulators; ++ } + + if (adv7511->type == ADV7533) { + ret = adv7533_init_cec(adv7511); +@@ -1045,6 +1109,8 @@ err_unregister_cec: + adv7533_uninit_cec(adv7511); + err_i2c_unregister_edid: + i2c_unregister_device(adv7511->i2c_edid); ++uninit_regulators: ++ adv7511_uninit_regulators(adv7511); + + return ret; + } +@@ -1058,6 +1124,8 @@ static int adv7511_remove(struct i2c_cli + adv7533_uninit_cec(adv7511); + } + ++ adv7511_uninit_regulators(adv7511); ++ + drm_bridge_remove(&adv7511->bridge); + + adv7511_audio_exit(adv7511); diff --git a/patches.renesas/0002-drm-bridge-adv7511-Use-work_struct-to-defer-hotplug-.patch b/patches.renesas/0002-drm-bridge-adv7511-Use-work_struct-to-defer-hotplug-.patch new file mode 100644 index 0000000000000..c8881752f4e89 --- /dev/null +++ b/patches.renesas/0002-drm-bridge-adv7511-Use-work_struct-to-defer-hotplug-.patch @@ -0,0 +1,83 @@ +From 4f389283ad4ecc0bceb09cccb825df1822fca6e3 Mon Sep 17 00:00:00 2001 +From: John Stultz <john.stultz@linaro.org> +Date: Mon, 16 Jan 2017 16:52:47 -0800 +Subject: [PATCH 002/255] drm/bridge: adv7511: Use work_struct to defer hotplug + handing to out of irq context + +I was recently seeing issues with EDID probing, where +the logic to wait for the EDID read bit to be set by the +IRQ wasn't happening and the code would time out and fail. + +Digging deeper, I found this was due to the fact that +IRQs were disabled as we were running in IRQ context from +the HPD signal. + +Thus this patch changes the logic to handle the HPD signal +via a work_struct so we can be out of irq context. + +With this patch, the EDID probing on hotplug does not time +out. + +Cc: David Airlie <airlied@linux.ie> +Cc: Archit Taneja <architt@codeaurora.org> +Cc: Wolfram Sang <wsa+renesas@sang-engineering.com> +Cc: Lars-Peter Clausen <lars@metafoo.de> +Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Cc: dri-devel@lists.freedesktop.org +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: John Stultz <john.stultz@linaro.org> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/1484614372-15342-2-git-send-email-john.stultz@linaro.org +(cherry picked from commit 518cb7057a59b9441336d2e88a396d52b6ab0cce) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/adv7511/adv7511.h | 2 ++ + drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 11 ++++++++++- + 2 files changed, 12 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h ++++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h +@@ -318,6 +318,8 @@ struct adv7511 { + bool edid_read; + + wait_queue_head_t wq; ++ struct work_struct hpd_work; ++ + struct drm_bridge bridge; + struct drm_connector connector; + +--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c ++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +@@ -402,6 +402,13 @@ static bool adv7511_hpd(struct adv7511 * + return false; + } + ++static void adv7511_hpd_work(struct work_struct *work) ++{ ++ struct adv7511 *adv7511 = container_of(work, struct adv7511, hpd_work); ++ ++ drm_helper_hpd_irq_event(adv7511->connector.dev); ++} ++ + static int adv7511_irq_process(struct adv7511 *adv7511, bool process_hpd) + { + unsigned int irq0, irq1; +@@ -419,7 +426,7 @@ static int adv7511_irq_process(struct ad + regmap_write(adv7511->regmap, ADV7511_REG_INT(1), irq1); + + if (process_hpd && irq0 & ADV7511_INT0_HPD && adv7511->bridge.encoder) +- drm_helper_hpd_irq_event(adv7511->connector.dev); ++ schedule_work(&adv7511->hpd_work); + + if (irq0 & ADV7511_INT0_EDID_READY || irq1 & ADV7511_INT1_DDC_ERROR) { + adv7511->edid_read = true; +@@ -1070,6 +1077,8 @@ static int adv7511_probe(struct i2c_clie + goto err_i2c_unregister_edid; + } + ++ INIT_WORK(&adv7511->hpd_work, adv7511_hpd_work); ++ + if (i2c->irq) { + init_waitqueue_head(&adv7511->wq); + diff --git a/patches.renesas/0003-drm-bridge-adv7511-Switch-to-using-drm_kms_helper_ho.patch b/patches.renesas/0003-drm-bridge-adv7511-Switch-to-using-drm_kms_helper_ho.patch new file mode 100644 index 0000000000000..2ed38c015e163 --- /dev/null +++ b/patches.renesas/0003-drm-bridge-adv7511-Switch-to-using-drm_kms_helper_ho.patch @@ -0,0 +1,59 @@ +From 399870f6fae9864ccc6a72db51b05cbdddfe5af5 Mon Sep 17 00:00:00 2001 +From: John Stultz <john.stultz@linaro.org> +Date: Mon, 16 Jan 2017 16:52:48 -0800 +Subject: [PATCH 003/255] drm/bridge: adv7511: Switch to using + drm_kms_helper_hotplug_event() + +In chasing down a previous issue with EDID probing from calling +drm_helper_hpd_irq_event() from irq context, Laurent noticed +that the DRM documentation suggests that +drm_kms_helper_hotplug_event() should be used instead. + +Thus this patch replaces drm_helper_hpd_irq_event() with +drm_kms_helper_hotplug_event(), which requires we update the +connector.status entry and only call _hotplug_event() when the +status changes. + +Cc: David Airlie <airlied@linux.ie> +Cc: Archit Taneja <architt@codeaurora.org> +Cc: Wolfram Sang <wsa+renesas@sang-engineering.com> +Cc: Lars-Peter Clausen <lars@metafoo.de> +Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Cc: dri-devel@lists.freedesktop.org +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: John Stultz <john.stultz@linaro.org> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/1484614372-15342-3-git-send-email-john.stultz@linaro.org +(cherry picked from commit 6d5104c5a6b56385426e15047050584794bb6254) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 16 +++++++++++++++- + 1 file changed, 15 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c ++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +@@ -405,8 +405,22 @@ static bool adv7511_hpd(struct adv7511 * + static void adv7511_hpd_work(struct work_struct *work) + { + struct adv7511 *adv7511 = container_of(work, struct adv7511, hpd_work); ++ enum drm_connector_status status; ++ unsigned int val; ++ int ret; + +- drm_helper_hpd_irq_event(adv7511->connector.dev); ++ ret = regmap_read(adv7511->regmap, ADV7511_REG_STATUS, &val); ++ if (ret < 0) ++ status = connector_status_disconnected; ++ else if (val & ADV7511_STATUS_HPD) ++ status = connector_status_connected; ++ else ++ status = connector_status_disconnected; ++ ++ if (adv7511->connector.status != status) { ++ adv7511->connector.status = status; ++ drm_kms_helper_hotplug_event(adv7511->connector.dev); ++ } + } + + static int adv7511_irq_process(struct adv7511 *adv7511, bool process_hpd) diff --git a/patches.renesas/0004-drm-bridge-adv7511-Enable-HPD-interrupts-to-support-.patch b/patches.renesas/0004-drm-bridge-adv7511-Enable-HPD-interrupts-to-support-.patch new file mode 100644 index 0000000000000..177fba00b89c1 --- /dev/null +++ b/patches.renesas/0004-drm-bridge-adv7511-Enable-HPD-interrupts-to-support-.patch @@ -0,0 +1,57 @@ +From 90d20bb5e94027fe643733b1ca8a97fd87cdf41e Mon Sep 17 00:00:00 2001 +From: Archit Taneja <architt@codeaurora.org> +Date: Mon, 16 Jan 2017 16:52:49 -0800 +Subject: [PATCH 004/255] drm/bridge: adv7511: Enable HPD interrupts to support + hotplug and improve monitor detection + +On some adv7511 implementations, we can get some spurious +disconnect signals which can cause monitor probing to fail. + +This patch enables HPD (hot plug detect) interrupt support +which allows the monitor to be properly re-initialized when +the spurious disconnect signal goes away. + +This also enables proper hotplug support. + +Cc: David Airlie <airlied@linux.ie> +Cc: Archit Taneja <architt@codeaurora.org> +Cc: Wolfram Sang <wsa+renesas@sang-engineering.com> +Cc: Lars-Peter Clausen <lars@metafoo.de> +Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Cc: dri-devel@lists.freedesktop.org +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Originally-by: Archit Taneja <architt@codeaurora.org> +[jstultz: Added proper commit message] +Signed-off-by: John Stultz <john.stultz@linaro.org> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/1484614372-15342-4-git-send-email-john.stultz@linaro.org + +(cherry picked from commit 40d86d2d22b04c2b2e48e2fe7054b85cf5021f25) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c ++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +@@ -338,7 +338,7 @@ static void adv7511_power_on(struct adv7 + * Still, let's be safe and stick to the documentation. + */ + regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(0), +- ADV7511_INT0_EDID_READY); ++ ADV7511_INT0_EDID_READY | ADV7511_INT0_HPD); + regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(1), + ADV7511_INT1_DDC_ERROR); + } +@@ -846,6 +846,10 @@ static int adv7511_bridge_attach(struct + if (adv->type == ADV7533) + ret = adv7533_attach_dsi(adv); + ++ if (adv->i2c_main->irq) ++ regmap_write(adv->regmap, ADV7511_REG_INT_ENABLE(0), ++ ADV7511_INT0_HPD); ++ + return ret; + } + diff --git a/patches.renesas/0005-drm-bridge-adv7511-Rework-adv7511_power_on-off-so-th.patch b/patches.renesas/0005-drm-bridge-adv7511-Rework-adv7511_power_on-off-so-th.patch new file mode 100644 index 0000000000000..7683862137f3a --- /dev/null +++ b/patches.renesas/0005-drm-bridge-adv7511-Rework-adv7511_power_on-off-so-th.patch @@ -0,0 +1,78 @@ +From d353ad784f84b18975bc5d256fa79c883fbca75e Mon Sep 17 00:00:00 2001 +From: John Stultz <john.stultz@linaro.org> +Date: Mon, 16 Jan 2017 16:52:50 -0800 +Subject: [PATCH 005/255] drm/bridge: adv7511: Rework adv7511_power_on/off() so + they can be reused internally + +In chasing down issues with EDID probing, I found some +duplicated but incomplete logic used to power the chip on and +off. + +This patch refactors the adv7511_power_on/off functions, so +they can be used for internal needs. + +Cc: David Airlie <airlied@linux.ie> +Cc: Archit Taneja <architt@codeaurora.org> +Cc: Wolfram Sang <wsa+renesas@sang-engineering.com> +Cc: Lars-Peter Clausen <lars@metafoo.de> +Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Cc: dri-devel@lists.freedesktop.org +Signed-off-by: John Stultz <john.stultz@linaro.org> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/1484614372-15342-5-git-send-email-john.stultz@linaro.org +(cherry picked from commit 651e4769ba2a9f20c4b8a823ae2727bf7fa9c9f0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 15 +++++++++++---- + 1 file changed, 11 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c ++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +@@ -325,7 +325,7 @@ static void adv7511_set_link_config(stru + adv7511->rgb = config->input_colorspace == HDMI_COLORSPACE_RGB; + } + +-static void adv7511_power_on(struct adv7511 *adv7511) ++static void __adv7511_power_on(struct adv7511 *adv7511) + { + adv7511->current_edid_segment = -1; + +@@ -354,6 +354,11 @@ static void adv7511_power_on(struct adv7 + regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2, + ADV7511_REG_POWER2_HPD_SRC_MASK, + ADV7511_REG_POWER2_HPD_SRC_NONE); ++} ++ ++static void adv7511_power_on(struct adv7511 *adv7511) ++{ ++ __adv7511_power_on(adv7511); + + /* + * Most of the registers are reset during power down or when HPD is low. +@@ -362,21 +367,23 @@ static void adv7511_power_on(struct adv7 + + if (adv7511->type == ADV7533) + adv7533_dsi_power_on(adv7511); +- + adv7511->powered = true; + } + +-static void adv7511_power_off(struct adv7511 *adv7511) ++static void __adv7511_power_off(struct adv7511 *adv7511) + { + /* TODO: setup additional power down modes */ + regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, + ADV7511_POWER_POWER_DOWN, + ADV7511_POWER_POWER_DOWN); + regcache_mark_dirty(adv7511->regmap); ++} + ++static void adv7511_power_off(struct adv7511 *adv7511) ++{ ++ __adv7511_power_off(adv7511); + if (adv7511->type == ADV7533) + adv7533_dsi_power_off(adv7511); +- + adv7511->powered = false; + } + diff --git a/patches.renesas/0006-drm-bridge-adv7511-Reuse-__adv7511_power_on-off-when.patch b/patches.renesas/0006-drm-bridge-adv7511-Reuse-__adv7511_power_on-off-when.patch new file mode 100644 index 0000000000000..b6cd406e74314 --- /dev/null +++ b/patches.renesas/0006-drm-bridge-adv7511-Reuse-__adv7511_power_on-off-when.patch @@ -0,0 +1,64 @@ +From f6e9751f27fe8a40cc5d3e6df1edb37ff8ab851e Mon Sep 17 00:00:00 2001 +From: John Stultz <john.stultz@linaro.org> +Date: Mon, 16 Jan 2017 16:52:51 -0800 +Subject: [PATCH 006/255] drm/bridge: adv7511: Reuse __adv7511_power_on/off() + when probing EDID + +Thus this patch changes the EDID probing logic so that we +re-use the __adv7511_power_on/off() calls instead of duplciating +logic. + +This does change behavior slightly as it adds the HPD signal +pulse to the EDID probe path, but Archit has had a patch to +add HPD signal pulse to the EDID probe path before, so this +should address the cases where that helped. Another difference +is that regcache_mark_dirty() is also called in the power off +path once EDID is probed. + +Cc: David Airlie <airlied@linux.ie> +Cc: Archit Taneja <architt@codeaurora.org> +Cc: Wolfram Sang <wsa+renesas@sang-engineering.com> +Cc: Lars-Peter Clausen <lars@metafoo.de> +Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Cc: dri-devel@lists.freedesktop.org +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: John Stultz <john.stultz@linaro.org> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/1484614372-15342-6-git-send-email-john.stultz@linaro.org +(cherry picked from commit 4226d9b127cf4758ba0e07931b3f0d59f1b1a50c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 17 +++-------------- + 1 file changed, 3 insertions(+), 14 deletions(-) + +--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c ++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +@@ -573,24 +573,13 @@ static int adv7511_get_modes(struct adv7 + unsigned int count; + + /* Reading the EDID only works if the device is powered */ +- if (!adv7511->powered) { +- regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, +- ADV7511_POWER_POWER_DOWN, 0); +- if (adv7511->i2c_main->irq) { +- regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(0), +- ADV7511_INT0_EDID_READY); +- regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(1), +- ADV7511_INT1_DDC_ERROR); +- } +- adv7511->current_edid_segment = -1; +- } ++ if (!adv7511->powered) ++ __adv7511_power_on(adv7511); + + edid = drm_do_get_edid(connector, adv7511_get_edid_block, adv7511); + + if (!adv7511->powered) +- regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, +- ADV7511_POWER_POWER_DOWN, +- ADV7511_POWER_POWER_DOWN); ++ __adv7511_power_off(adv7511); + + kfree(adv7511->edid); + adv7511->edid = edid; diff --git a/patches.renesas/0007-drm-bridge-adv7511-Re-write-the-i2c-address-before-E.patch b/patches.renesas/0007-drm-bridge-adv7511-Re-write-the-i2c-address-before-E.patch new file mode 100644 index 0000000000000..10cfbe18232e6 --- /dev/null +++ b/patches.renesas/0007-drm-bridge-adv7511-Re-write-the-i2c-address-before-E.patch @@ -0,0 +1,56 @@ +From 854043ead1064d575a48475d2728ef7eff0a5fd9 Mon Sep 17 00:00:00 2001 +From: John Stultz <john.stultz@linaro.org> +Date: Mon, 16 Jan 2017 16:52:52 -0800 +Subject: [PATCH 007/255] drm/bridge: adv7511: Re-write the i2c address before + EDID probing + +I've found that by just turning the chip on and off via the +POWER_DOWN register, I end up getting i2c_transfer errors on +HiKey. + +Investigating further, it turns out that some of the register +state in hardware is getting lost, as the device registers are +reset when the chip is powered down. + +Thus this patch simply re-writes the i2c address to the +ADV7511_REG_EDID_I2C_ADDR register to ensure its properly set +before we try to read the EDID data. + +Cc: David Airlie <airlied@linux.ie> +Cc: Archit Taneja <architt@codeaurora.org> +Cc: Wolfram Sang <wsa+renesas@sang-engineering.com> +Cc: Lars-Peter Clausen <lars@metafoo.de> +Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Cc: dri-devel@lists.freedesktop.org +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: John Stultz <john.stultz@linaro.org> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/1484614372-15342-7-git-send-email-john.stultz@linaro.org +(cherry picked from commit 3587c856675c45809010c2cee5b21096f6e8e938) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c ++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +@@ -573,9 +573,17 @@ static int adv7511_get_modes(struct adv7 + unsigned int count; + + /* Reading the EDID only works if the device is powered */ +- if (!adv7511->powered) ++ if (!adv7511->powered) { ++ unsigned int edid_i2c_addr = ++ (adv7511->i2c_main->addr << 1) + 4; ++ + __adv7511_power_on(adv7511); + ++ /* Reset the EDID_I2C_ADDR register as it might be cleared */ ++ regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR, ++ edid_i2c_addr); ++ } ++ + edid = drm_do_get_edid(connector, adv7511_get_edid_block, adv7511); + + if (!adv7511->powered) diff --git a/patches.renesas/0008-ASoC-ak4642-Replace-mdelay-function-to-msleep.patch b/patches.renesas/0008-ASoC-ak4642-Replace-mdelay-function-to-msleep.patch new file mode 100644 index 0000000000000..1ca4d1f451346 --- /dev/null +++ b/patches.renesas/0008-ASoC-ak4642-Replace-mdelay-function-to-msleep.patch @@ -0,0 +1,29 @@ +From 053281ae9ff6250c8d50ddaeaa2275ad05f4d855 Mon Sep 17 00:00:00 2001 +From: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> +Date: Wed, 11 Jan 2017 04:32:43 +0000 +Subject: [PATCH 008/255] ASoC: ak4642: Replace mdelay function to msleep + +Replace mdelay to msleep to avoid busy loop on ak4642_lout_event(). +Otherwise, sometimes playback doesn't work correctly when pulseaudio +was used. + +Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit fc1e65c3a858fe9a454da9e9fd180834ed089cbd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/codecs/ak4642.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/sound/soc/codecs/ak4642.c ++++ b/sound/soc/codecs/ak4642.c +@@ -189,7 +189,7 @@ static int ak4642_lout_event(struct snd_ + case SND_SOC_DAPM_POST_PMU: + case SND_SOC_DAPM_POST_PMD: + /* Power save mode OFF */ +- mdelay(300); ++ msleep(300); + snd_soc_update_bits(codec, SG_SL2, LOPS, 0); + break; + } diff --git a/patches.renesas/0009-clk-renesas-r8a7796-Add-CAN-peripheral-clock.patch b/patches.renesas/0009-clk-renesas-r8a7796-Add-CAN-peripheral-clock.patch new file mode 100644 index 0000000000000..dcbce9d7115a8 --- /dev/null +++ b/patches.renesas/0009-clk-renesas-r8a7796-Add-CAN-peripheral-clock.patch @@ -0,0 +1,26 @@ +From d860150628106aaf2b364090290c0b4fdfe54b7b Mon Sep 17 00:00:00 2001 +From: Chris Paterson <chris.paterson2@renesas.com> +Date: Tue, 22 Nov 2016 13:46:00 +0000 +Subject: [PATCH 009/255] clk: renesas: r8a7796: Add CAN peripheral clock + +Based on a patch for r8a7795 by Ramesh Shanmugasundaram. + +Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit e00d20c99d39a554bb90de853f33afeffa7ce2e1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c +@@ -181,6 +181,8 @@ static const struct mssr_mod_clk r8a7796 + DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4), + DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4), + DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4), ++ DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4), ++ DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4), + DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), + DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6), + DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6), diff --git a/patches.renesas/0010-clk-renesas-r8a7796-Add-CANFD-clock.patch b/patches.renesas/0010-clk-renesas-r8a7796-Add-CANFD-clock.patch new file mode 100644 index 0000000000000..23a79f0c9663d --- /dev/null +++ b/patches.renesas/0010-clk-renesas-r8a7796-Add-CANFD-clock.patch @@ -0,0 +1,25 @@ +From ae7a1af011c2dc22c6c9d3238a6a9d2445a6d348 Mon Sep 17 00:00:00 2001 +From: Chris Paterson <chris.paterson2@renesas.com> +Date: Tue, 22 Nov 2016 13:46:01 +0000 +Subject: [PATCH 010/255] clk: renesas: r8a7796: Add CANFD clock + +Based on a patch for r8a7795 by Ramesh Shanmugasundaram. + +Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 9e620beecdf40303c950f344806730093e5d08ae) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c +@@ -103,6 +103,7 @@ static const struct cpg_core_clk r8a7796 + DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), + ++ DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244), + DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), + + DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), diff --git a/patches.renesas/0011-clk-renesas-r8a7796-Add-CAN-FD-peripheral-clock.patch b/patches.renesas/0011-clk-renesas-r8a7796-Add-CAN-FD-peripheral-clock.patch new file mode 100644 index 0000000000000..a3c3ee975aeb2 --- /dev/null +++ b/patches.renesas/0011-clk-renesas-r8a7796-Add-CAN-FD-peripheral-clock.patch @@ -0,0 +1,25 @@ +From 471c880ad7b5a982edd355c1250caf41fcad8f14 Mon Sep 17 00:00:00 2001 +From: Chris Paterson <chris.paterson2@renesas.com> +Date: Tue, 22 Nov 2016 13:46:02 +0000 +Subject: [PATCH 011/255] clk: renesas: r8a7796: Add CAN FD peripheral clock + +Based on a patch for r8a7795 by Ramesh Shanmugasundaram. + +Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 0ece46c24f5fdc29fc17bfb019a4e64ebe0d6b56) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c +@@ -182,6 +182,7 @@ static const struct mssr_mod_clk r8a7796 + DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4), + DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4), + DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4), ++ DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2), + DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4), + DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4), + DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), diff --git a/patches.renesas/0012-clk-renesas-r8a7796-Add-MSIOF-controller-clocks.patch b/patches.renesas/0012-clk-renesas-r8a7796-Add-MSIOF-controller-clocks.patch new file mode 100644 index 0000000000000..1758e05813438 --- /dev/null +++ b/patches.renesas/0012-clk-renesas-r8a7796-Add-MSIOF-controller-clocks.patch @@ -0,0 +1,37 @@ +From 17eacb01b5f6bb8ba6dcf18117c50e52ef830c5a Mon Sep 17 00:00:00 2001 +From: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> +Date: Tue, 15 Mar 2016 16:07:29 +0900 +Subject: [PATCH 012/255] clk: renesas: r8a7796: Add MSIOF controller clocks + +This patch adds MSIOF{0,1,2,3} clocks for R8A7796 SoC. + +Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit e6bdf28eff475a026b922abe78ae710e7179bdf7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7796-cpg-mssr.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c +@@ -105,6 +105,7 @@ static const struct cpg_core_clk r8a7796 + + DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244), + DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), ++ DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014), + + DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), + DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), +@@ -118,6 +119,10 @@ static const struct mssr_mod_clk r8a7796 + DEF_MOD("scif3", 204, R8A7796_CLK_S3D4), + DEF_MOD("scif1", 206, R8A7796_CLK_S3D4), + DEF_MOD("scif0", 207, R8A7796_CLK_S3D4), ++ DEF_MOD("msiof3", 208, R8A7796_CLK_MSO), ++ DEF_MOD("msiof2", 209, R8A7796_CLK_MSO), ++ DEF_MOD("msiof1", 210, R8A7796_CLK_MSO), ++ DEF_MOD("msiof0", 211, R8A7796_CLK_MSO), + DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3), + DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3), + DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3), diff --git a/patches.renesas/0013-clk-renesas-cpg-mssr-Migrate-to-CLK_IS_CRITICAL.patch b/patches.renesas/0013-clk-renesas-cpg-mssr-Migrate-to-CLK_IS_CRITICAL.patch new file mode 100644 index 0000000000000..12c5fcaf960fe --- /dev/null +++ b/patches.renesas/0013-clk-renesas-cpg-mssr-Migrate-to-CLK_IS_CRITICAL.patch @@ -0,0 +1,48 @@ +From be0a02d89ccba2fbdb86ae03712e3f6d62e9f582 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 16 Jan 2017 16:15:50 +0100 +Subject: [PATCH 013/255] clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICAL + +When the Renesas CPG/MSSR driver was introduced, it was anticipated that +critical clocks would be handled through a new CLK_ENABLE_HAND_OFF flag +soon. However, CLK_ENABLE_HAND_OFF never made it upstream. + +Instead, commit 32b9b10961860860 ("clk: Allow clocks to be marked as +CRITICAL") introduced CLK_IS_CRITICAL, a flag with slightly differing +semantics. Still, it can be used to prevent e.g. the GIC module clock +from being turned off, until the GIC-400 driver has full support for +Runtime PM. + +Hence migrate the Renesas CPG/MSSR driver from CLK_ENABLE_HAND_OFF to +CLK_IS_CRITICAL. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +(cherry picked from commit 72f5df2c2bbb66d4a555cb51eb9f412abf1af77f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/renesas-cpg-mssr.c | 11 ++--------- + 1 file changed, 2 insertions(+), 9 deletions(-) + +--- a/drivers/clk/renesas/renesas-cpg-mssr.c ++++ b/drivers/clk/renesas/renesas-cpg-mssr.c +@@ -346,17 +346,10 @@ static void __init cpg_mssr_register_mod + init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; + for (i = 0; i < info->num_crit_mod_clks; i++) + if (id == info->crit_mod_clks[i]) { +-#ifdef CLK_ENABLE_HAND_OFF +- dev_dbg(dev, "MSTP %s setting CLK_ENABLE_HAND_OFF\n", ++ dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", + mod->name); +- init.flags |= CLK_ENABLE_HAND_OFF; ++ init.flags |= CLK_IS_CRITICAL; + break; +-#else +- dev_dbg(dev, "Ignoring MSTP %s to prevent disabling\n", +- mod->name); +- kfree(clock); +- return; +-#endif + } + + parent_name = __clk_get_name(parent); diff --git a/patches.renesas/0014-clk-renesas-mstp-Make-INTC-SYS-a-critical-clock.patch b/patches.renesas/0014-clk-renesas-mstp-Make-INTC-SYS-a-critical-clock.patch new file mode 100644 index 0000000000000..91a2a4246d2e2 --- /dev/null +++ b/patches.renesas/0014-clk-renesas-mstp-Make-INTC-SYS-a-critical-clock.patch @@ -0,0 +1,51 @@ +From 9dde2addb9d9d5f356e3b37b0e0222e12c93cdad Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 17 Mar 2015 17:20:52 +0100 +Subject: [PATCH 014/255] clk: renesas: mstp: Make INTC-SYS a critical clock + +INTC-SYS is the module clock for the GIC. Accessing the GIC while it is +disabled causes: + + Unhandled fault: asynchronous external abort (0x1211) at 0x00000000 + +Currently, the GIC-400 driver cannot enable its module clock for several +reasons: + - It does not use a platform device, so Runtime PM is not an option, + - gic_of_init() runs before any clocks are registered, so it cannot + enable the clock explicitly, + - gic_of_init() cannot return -EPROBE_DEFER, as IRQCHIP_DECLARE() + doesn't support deferred probing. + +Hence we have to keep on relying on the boot loader for enabling the +module clock. + +To prevent the module clock from being disabled when the CCF core thinks +it is unused, and thus causing a system lock-up, add a check to the MSTP +clock driver and enable CLK_IS_CRITICAL. This will make sure the module +clock is never disabled. + +This is a hard dependency for describing the INTC-SYS clock in DT on +R-Mobile APE6 and R-Car Gen2. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +(cherry picked from commit e34084fb9a023d1dd008c989523af5a037f1d692) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/clk-mstp.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/clk/renesas/clk-mstp.c ++++ b/drivers/clk/renesas/clk-mstp.c +@@ -158,6 +158,11 @@ cpg_mstp_clock_register(const char *name + init.name = name; + init.ops = &cpg_mstp_clock_ops; + init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; ++ /* INTC-SYS is the module clock of the GIC, and must not be disabled */ ++ if (!strcmp(name, "intc-sys")) { ++ pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name); ++ init.flags |= CLK_IS_CRITICAL; ++ } + init.parent_names = &parent_name; + init.num_parents = 1; + diff --git a/patches.renesas/0015-ARM-dts-r7s72100-add-ostm-clock-to-device-tree.patch b/patches.renesas/0015-ARM-dts-r7s72100-add-ostm-clock-to-device-tree.patch new file mode 100644 index 0000000000000..c699d5324afdc --- /dev/null +++ b/patches.renesas/0015-ARM-dts-r7s72100-add-ostm-clock-to-device-tree.patch @@ -0,0 +1,46 @@ +From 4f53e25aca63ba026bfdfeff70bdedadbd8a2d65 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Mon, 23 Jan 2017 08:55:18 -0500 +Subject: [PATCH 015/255] ARM: dts: r7s72100: add ostm clock to device tree + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cfddd3db08f619bf0c1764b3103caedb6793bc48) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100.dtsi | 9 +++++++++ + include/dt-bindings/clock/r7s72100-clock.h | 4 ++++ + 2 files changed, 13 insertions(+) + +--- a/arch/arm/boot/dts/r7s72100.dtsi ++++ b/arch/arm/boot/dts/r7s72100.dtsi +@@ -108,6 +108,15 @@ + clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; + }; + ++ mstp5_clks: mstp5_clks@fcfe0428 { ++ #clock-cells = <1>; ++ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; ++ reg = <0xfcfe0428 4>; ++ clocks = <&p0_clk>, <&p0_clk>; ++ clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>; ++ clock-output-names = "ostm0", "ostm1"; ++ }; ++ + mstp7_clks: mstp7_clks@fcfe0430 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; +--- a/include/dt-bindings/clock/r7s72100-clock.h ++++ b/include/dt-bindings/clock/r7s72100-clock.h +@@ -25,6 +25,10 @@ + #define R7S72100_CLK_SCIF6 1 + #define R7S72100_CLK_SCIF7 0 + ++/* MSTP5 */ ++#define R7S72100_CLK_OSTM0 1 ++#define R7S72100_CLK_OSTM1 0 ++ + /* MSTP7 */ + #define R7S72100_CLK_ETHER 4 + diff --git a/patches.renesas/0016-clk-renesas-mstp-Reformat-cpg_mstp_clock_register-fo.patch b/patches.renesas/0016-clk-renesas-mstp-Reformat-cpg_mstp_clock_register-fo.patch new file mode 100644 index 0000000000000..a98a3f1342175 --- /dev/null +++ b/patches.renesas/0016-clk-renesas-mstp-Reformat-cpg_mstp_clock_register-fo.patch @@ -0,0 +1,35 @@ +From be0bdb4df687cae3729d2aa5b64de0d044877654 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 23 Jan 2017 10:48:21 +0100 +Subject: [PATCH 016/255] clk: renesas: mstp: Reformat + cpg_mstp_clock_register() for git diff + +As the function header of cpg_mstp_clock_register() is split in an +unusual way, "git diff" gets confused when changes to the body of +the function are made, and attributes them to the wrong function. + +Reformat the function header to fix this. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +(cherry picked from commit 1ce87dd2f0bb8dee1378ec3bff94c4454feaaa30) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/clk-mstp.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/clk/renesas/clk-mstp.c ++++ b/drivers/clk/renesas/clk-mstp.c +@@ -141,9 +141,9 @@ static const struct clk_ops cpg_mstp_clo + .is_enabled = cpg_mstp_clock_is_enabled, + }; + +-static struct clk * __init +-cpg_mstp_clock_register(const char *name, const char *parent_name, +- unsigned int index, struct mstp_clock_group *group) ++static struct clk * __init cpg_mstp_clock_register(const char *name, ++ const char *parent_name, unsigned int index, ++ struct mstp_clock_group *group) + { + struct clk_init_data init; + struct mstp_clock *clock; diff --git a/patches.renesas/0017-dt-bindings-clock-renesas-cpg-mssr-Document-reset-co.patch b/patches.renesas/0017-dt-bindings-clock-renesas-cpg-mssr-Document-reset-co.patch new file mode 100644 index 0000000000000..e194349d0ecd2 --- /dev/null +++ b/patches.renesas/0017-dt-bindings-clock-renesas-cpg-mssr-Document-reset-co.patch @@ -0,0 +1,45 @@ +From 1b3bf792cac3ad001c2fe839a6088ddc69c97207 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 12 Oct 2015 11:35:34 +0200 +Subject: [PATCH 017/255] dt-bindings: clock: renesas: cpg-mssr: Document reset + control support + +Document properties needed to use the Reset Control feature of the +Renesas Clock Pulse Generator / Module Standby and Software Reset +module. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 98aabfff7df441597c27a57584f8a1d5cfd506b7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt ++++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +@@ -42,6 +42,10 @@ Required Properties: + Domain bindings in + Documentation/devicetree/bindings/power/power_domain.txt. + ++ - #reset-cells: Must be 1 ++ - The single reset specifier cell must be the module number, as defined ++ in the datasheet. ++ + + Examples + -------- +@@ -55,6 +59,7 @@ Examples + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; ++ #reset-cells = <1>; + }; + + +@@ -69,5 +74,6 @@ Examples + dmas = <&dmac1 0x13>, <&dmac1 0x12>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; ++ resets = <&cpg 310>; + status = "disabled"; + }; diff --git a/patches.renesas/0018-clk-renesas-cpg-mssr-Document-suitability-for-RZ-G1.patch b/patches.renesas/0018-clk-renesas-cpg-mssr-Document-suitability-for-RZ-G1.patch new file mode 100644 index 0000000000000..5e77b8c7a8f4f --- /dev/null +++ b/patches.renesas/0018-clk-renesas-cpg-mssr-Document-suitability-for-RZ-G1.patch @@ -0,0 +1,29 @@ +From 76dd5074ed5143524cea1cda3be9b4e441d1fd31 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 20 Jan 2017 10:53:11 +0100 +Subject: [PATCH 018/255] clk: renesas: cpg-mssr: Document suitability for + RZ/G1 + +The Renesas CPG/MSSR driver is already in active use for RZ/G1 since +commits c0b2d75d2a4bf6a3 ("clk: renesas: cpg-mssr: Add R8A7743 support") +and 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support"). + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +(cherry picked from commit 67c995b55e1ade919a0037723ecc9210c79007f8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/renesas-cpg-mssr.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/renesas/renesas-cpg-mssr.c ++++ b/drivers/clk/renesas/renesas-cpg-mssr.c +@@ -43,7 +43,7 @@ + * Module Standby and Software Reset register offets. + * + * If the registers exist, these are valid for SH-Mobile, R-Mobile, +- * R-Car Gen 2, and R-Car Gen 3. ++ * R-Car Gen2, R-Car Gen3, and RZ/G1. + * These are NOT valid for R-Car Gen1 and RZ/A1! + */ + diff --git a/patches.renesas/0019-clk-renesas-cpg-mssr-Rename-cpg_mssr_priv.mstp_lock.patch b/patches.renesas/0019-clk-renesas-cpg-mssr-Rename-cpg_mssr_priv.mstp_lock.patch new file mode 100644 index 0000000000000..145a09bb010ec --- /dev/null +++ b/patches.renesas/0019-clk-renesas-cpg-mssr-Rename-cpg_mssr_priv.mstp_lock.patch @@ -0,0 +1,64 @@ +From df8d4a6120036c61f31ad5f523ce0236595c32c4 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 20 Jan 2017 10:58:11 +0100 +Subject: [PATCH 019/255] clk: renesas: cpg-mssr: Rename + cpg_mssr_priv.mstp_lock + +The spinlock is used to protect Read-Modify-Write register accesses, +which won't be limited to SMSTPCR register accesses. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +(cherry picked from commit a4ea6a0f83073f256547a49fa6433806cee2cc87) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/renesas-cpg-mssr.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/clk/renesas/renesas-cpg-mssr.c ++++ b/drivers/clk/renesas/renesas-cpg-mssr.c +@@ -98,7 +98,7 @@ static const u16 srcr[] = { + * + * @dev: CPG/MSSR device + * @base: CPG/MSSR register block base address +- * @mstp_lock: protects writes to SMSTPCR ++ * @rmw_lock: protects RMW register accesses + * @clks: Array containing all Core and Module Clocks + * @num_core_clks: Number of Core Clocks in clks[] + * @num_mod_clks: Number of Module Clocks in clks[] +@@ -107,7 +107,7 @@ static const u16 srcr[] = { + struct cpg_mssr_priv { + struct device *dev; + void __iomem *base; +- spinlock_t mstp_lock; ++ spinlock_t rmw_lock; + + struct clk **clks; + unsigned int num_core_clks; +@@ -144,7 +144,7 @@ static int cpg_mstp_clock_endisable(stru + + dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, + enable ? "ON" : "OFF"); +- spin_lock_irqsave(&priv->mstp_lock, flags); ++ spin_lock_irqsave(&priv->rmw_lock, flags); + + value = readl(priv->base + SMSTPCR(reg)); + if (enable) +@@ -153,7 +153,7 @@ static int cpg_mstp_clock_endisable(stru + value |= bitmask; + writel(value, priv->base + SMSTPCR(reg)); + +- spin_unlock_irqrestore(&priv->mstp_lock, flags); ++ spin_unlock_irqrestore(&priv->rmw_lock, flags); + + if (!enable) + return 0; +@@ -550,7 +550,7 @@ static int __init cpg_mssr_probe(struct + return -ENOMEM; + + priv->dev = dev; +- spin_lock_init(&priv->mstp_lock); ++ spin_lock_init(&priv->rmw_lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(dev, res); diff --git a/patches.renesas/0020-clk-renesas-cpg-mssr-Add-support-for-reset-control.patch b/patches.renesas/0020-clk-renesas-cpg-mssr-Add-support-for-reset-control.patch new file mode 100644 index 0000000000000..46618cf71aa95 --- /dev/null +++ b/patches.renesas/0020-clk-renesas-cpg-mssr-Add-support-for-reset-control.patch @@ -0,0 +1,194 @@ +From 20cad7aa5686445380d9e26bc3ae49f1c534ddb8 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 20 Jan 2017 11:03:03 +0100 +Subject: [PATCH 020/255] clk: renesas: cpg-mssr: Add support for reset control +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add optional support for the Reset Control feature of the Renesas Clock +Pulse Generator / Module Standby and Software Reset module on R-Car +Gen2, R-Car Gen3, and RZ/G1 SoCs. + +This allows to reset SoC devices using the Reset Controller API. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Philipp Zabel <p.zabel@pengutronix.de> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +(cherry picked from commit 6197aa65c4905532943155d03031ba0f3a4b2a3b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/renesas-cpg-mssr.c | 126 +++++++++++++++++++++++++++++++++ + 1 file changed, 126 insertions(+) + +--- a/drivers/clk/renesas/renesas-cpg-mssr.c ++++ b/drivers/clk/renesas/renesas-cpg-mssr.c +@@ -16,6 +16,7 @@ + #include <linux/clk.h> + #include <linux/clk-provider.h> + #include <linux/clk/renesas.h> ++#include <linux/delay.h> + #include <linux/device.h> + #include <linux/init.h> + #include <linux/mod_devicetable.h> +@@ -25,6 +26,7 @@ + #include <linux/platform_device.h> + #include <linux/pm_clock.h> + #include <linux/pm_domain.h> ++#include <linux/reset-controller.h> + #include <linux/slab.h> + + #include <dt-bindings/clock/renesas-cpg-mssr.h> +@@ -96,6 +98,7 @@ static const u16 srcr[] = { + /** + * Clock Pulse Generator / Module Standby and Software Reset Private Data + * ++ * @rcdev: Optional reset controller entity + * @dev: CPG/MSSR device + * @base: CPG/MSSR register block base address + * @rmw_lock: protects RMW register accesses +@@ -105,6 +108,9 @@ static const u16 srcr[] = { + * @last_dt_core_clk: ID of the last Core Clock exported to DT + */ + struct cpg_mssr_priv { ++#ifdef CONFIG_RESET_CONTROLLER ++ struct reset_controller_dev rcdev; ++#endif + struct device *dev; + void __iomem *base; + spinlock_t rmw_lock; +@@ -494,6 +500,122 @@ static int __init cpg_mssr_add_clk_domai + return 0; + } + ++#ifdef CONFIG_RESET_CONTROLLER ++ ++#define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev) ++ ++static int cpg_mssr_reset(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); ++ unsigned int reg = id / 32; ++ unsigned int bit = id % 32; ++ u32 bitmask = BIT(bit); ++ unsigned long flags; ++ u32 value; ++ ++ dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); ++ ++ /* Reset module */ ++ spin_lock_irqsave(&priv->rmw_lock, flags); ++ value = readl(priv->base + SRCR(reg)); ++ value |= bitmask; ++ writel(value, priv->base + SRCR(reg)); ++ spin_unlock_irqrestore(&priv->rmw_lock, flags); ++ ++ /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ ++ udelay(35); ++ ++ /* Release module from reset state */ ++ writel(bitmask, priv->base + SRSTCLR(reg)); ++ ++ return 0; ++} ++ ++static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id) ++{ ++ struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); ++ unsigned int reg = id / 32; ++ unsigned int bit = id % 32; ++ u32 bitmask = BIT(bit); ++ unsigned long flags; ++ u32 value; ++ ++ dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); ++ ++ spin_lock_irqsave(&priv->rmw_lock, flags); ++ value = readl(priv->base + SRCR(reg)); ++ value |= bitmask; ++ writel(value, priv->base + SRCR(reg)); ++ spin_unlock_irqrestore(&priv->rmw_lock, flags); ++ return 0; ++} ++ ++static int cpg_mssr_deassert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); ++ unsigned int reg = id / 32; ++ unsigned int bit = id % 32; ++ u32 bitmask = BIT(bit); ++ ++ dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); ++ ++ writel(bitmask, priv->base + SRSTCLR(reg)); ++ return 0; ++} ++ ++static int cpg_mssr_status(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); ++ unsigned int reg = id / 32; ++ unsigned int bit = id % 32; ++ u32 bitmask = BIT(bit); ++ ++ return !!(readl(priv->base + SRCR(reg)) & bitmask); ++} ++ ++static const struct reset_control_ops cpg_mssr_reset_ops = { ++ .reset = cpg_mssr_reset, ++ .assert = cpg_mssr_assert, ++ .deassert = cpg_mssr_deassert, ++ .status = cpg_mssr_status, ++}; ++ ++static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev, ++ const struct of_phandle_args *reset_spec) ++{ ++ struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); ++ unsigned int unpacked = reset_spec->args[0]; ++ unsigned int idx = MOD_CLK_PACK(unpacked); ++ ++ if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { ++ dev_err(priv->dev, "Invalid reset index %u\n", unpacked); ++ return -EINVAL; ++ } ++ ++ return idx; ++} ++ ++static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) ++{ ++ priv->rcdev.ops = &cpg_mssr_reset_ops; ++ priv->rcdev.of_node = priv->dev->of_node; ++ priv->rcdev.of_reset_n_cells = 1; ++ priv->rcdev.of_xlate = cpg_mssr_reset_xlate; ++ priv->rcdev.nr_resets = priv->num_mod_clks; ++ return devm_reset_controller_register(priv->dev, &priv->rcdev); ++} ++ ++#else /* !CONFIG_RESET_CONTROLLER */ ++static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) ++{ ++ return 0; ++} ++#endif /* !CONFIG_RESET_CONTROLLER */ ++ ++ + static const struct of_device_id cpg_mssr_match[] = { + #ifdef CONFIG_ARCH_R8A7743 + { +@@ -591,6 +713,10 @@ static int __init cpg_mssr_probe(struct + if (error) + return error; + ++ error = cpg_mssr_reset_controller_register(priv); ++ if (error) ++ return error; ++ + return 0; + } + diff --git a/patches.renesas/0021-clk-renesas-r8a7795-Add-IIC-DVFS-clock.patch b/patches.renesas/0021-clk-renesas-r8a7795-Add-IIC-DVFS-clock.patch new file mode 100644 index 0000000000000..518f8c47adf9d --- /dev/null +++ b/patches.renesas/0021-clk-renesas-r8a7795-Add-IIC-DVFS-clock.patch @@ -0,0 +1,29 @@ +From 23f57c51befad045a8d440f02de3cba743b7e5ff Mon Sep 17 00:00:00 2001 +From: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Date: Mon, 23 May 2016 11:05:42 +0900 +Subject: [PATCH 021/255] clk: renesas: r8a7795: Add IIC-DVFS clock + +This patch adds DVFS clock for R8A7795 SoC. + +Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> +Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 2c8e79898c9af08e04b36d3678384642b59f6509) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c +@@ -221,6 +221,7 @@ static const struct mssr_mod_clk r8a7795 + DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), + DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2), + DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2), ++ DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP), + DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2), + DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2), + DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2), diff --git a/patches.renesas/0022-clk-renesas-r8a7796-Add-IIC-DVFS-clock.patch b/patches.renesas/0022-clk-renesas-r8a7796-Add-IIC-DVFS-clock.patch new file mode 100644 index 0000000000000..06b1908bc5eec --- /dev/null +++ b/patches.renesas/0022-clk-renesas-r8a7796-Add-IIC-DVFS-clock.patch @@ -0,0 +1,28 @@ +From 20b209556d436e789d3201d1b892805dc8e5b54a Mon Sep 17 00:00:00 2001 +From: Khiem Nguyen <khiem.nguyen.xt@renesas.com> +Date: Mon, 4 Apr 2016 09:01:19 +0700 +Subject: [PATCH 022/255] clk: renesas: r8a7796: Add IIC-DVFS clock + +This patch adds DVFS clock for R8A7796 SoC. + +Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com> +Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit d963654e109565cf73399815d7585917f2d69a30) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c +@@ -192,6 +192,7 @@ static const struct mssr_mod_clk r8a7796 + DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4), + DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), + DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6), ++ DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP), + DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6), + DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6), + DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2), diff --git a/patches.renesas/0023-clk-renesas-mstp-ensure-register-writes-complete.patch b/patches.renesas/0023-clk-renesas-mstp-ensure-register-writes-complete.patch new file mode 100644 index 0000000000000..ea9b792af19fa --- /dev/null +++ b/patches.renesas/0023-clk-renesas-mstp-ensure-register-writes-complete.patch @@ -0,0 +1,36 @@ +From fb4488f61538f1e252c7c8c1d86f665404e9a4cb Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Tue, 14 Feb 2017 11:08:05 -0500 +Subject: [PATCH 023/255] clk: renesas: mstp: ensure register writes complete + +When there is no status bit, it is possible for the clock enable/disable +operation to have not completed by the time the driver code resumes +execution. This is due to the fact that write operations are sometimes +queued and delayed internally. Doing a read ensures the write operations +has completed. + +Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi") +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> +(cherry picked from commit f59de563358eb9351b7f8f0ba2d3be2ebb70b93d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/clk-mstp.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/clk/renesas/clk-mstp.c ++++ b/drivers/clk/renesas/clk-mstp.c +@@ -91,6 +91,12 @@ static int cpg_mstp_clock_endisable(stru + value |= bitmask; + cpg_mstp_write(group, value, group->smstpcr); + ++ if (!group->mstpsr) { ++ /* dummy read to ensure write has completed */ ++ cpg_mstp_read(group, group->smstpcr); ++ barrier_data(group->smstpcr); ++ } ++ + spin_unlock_irqrestore(&group->lock, flags); + + if (!enable || !group->mstpsr) diff --git a/patches.renesas/0024-arm64-dts-r8a7796-Add-all-MSIOF-nodes.patch b/patches.renesas/0024-arm64-dts-r8a7796-Add-all-MSIOF-nodes.patch new file mode 100644 index 0000000000000..12475187b6eef --- /dev/null +++ b/patches.renesas/0024-arm64-dts-r8a7796-Add-all-MSIOF-nodes.patch @@ -0,0 +1,78 @@ +From ec1b7e5de758d76029855497c6ecd3b43a640a38 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 21 Nov 2016 18:26:53 +0100 +Subject: [PATCH 024/255] arm64: dts: r8a7796: Add all MSIOF nodes + +Add the device nodes for all MSIOF SPI controllers. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 80fab06e258da76232356d8a0b390d4bc25e6917) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 54 +++++++++++++++++++++++++++++++ + 1 file changed, 54 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -373,6 +373,60 @@ + status = "disabled"; + }; + ++ msiof0: spi@e6e90000 { ++ compatible = "renesas,msiof-r8a7796"; ++ reg = <0 0xe6e90000 0 0x0064>; ++ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 211>; ++ dmas = <&dmac1 0x41>, <&dmac1 0x40>, ++ <&dmac2 0x41>, <&dmac2 0x40>; ++ dma-names = "tx", "rx"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ msiof1: spi@e6ea0000 { ++ compatible = "renesas,msiof-r8a7796"; ++ reg = <0 0xe6ea0000 0 0x0064>; ++ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 210>; ++ dmas = <&dmac1 0x43>, <&dmac1 0x42>, ++ <&dmac2 0x43>, <&dmac2 0x42>; ++ dma-names = "tx", "rx"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ msiof2: spi@e6c00000 { ++ compatible = "renesas,msiof-r8a7796"; ++ reg = <0 0xe6c00000 0 0x0064>; ++ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 209>; ++ dmas = <&dmac0 0x45>, <&dmac0 0x44>; ++ dma-names = "tx", "rx"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ msiof3: spi@e6c10000 { ++ compatible = "renesas,msiof-r8a7796"; ++ reg = <0 0xe6c10000 0 0x0064>; ++ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 208>; ++ dmas = <&dmac0 0x47>, <&dmac0 0x46>; ++ dma-names = "tx", "rx"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; diff --git a/patches.renesas/0025-arm64-dts-r8a7796-Add-CAN-external-clock-support.patch b/patches.renesas/0025-arm64-dts-r8a7796-Add-CAN-external-clock-support.patch new file mode 100644 index 0000000000000..a147838efaaee --- /dev/null +++ b/patches.renesas/0025-arm64-dts-r8a7796-Add-CAN-external-clock-support.patch @@ -0,0 +1,36 @@ +From ce5dfa7919e6afc48ea6c8fbdd7c461c791d1172 Mon Sep 17 00:00:00 2001 +From: Chris Paterson <chris.paterson2@renesas.com> +Date: Thu, 24 Nov 2016 16:13:39 +0000 +Subject: [PATCH 025/255] arm64: dts: r8a7796: Add CAN external clock support + +Adds external CAN clock node for r8a7796. This clock can be used as +fCAN clock of CAN and CAN FD controller. + +Based on a patch for r8a7795 by Ramesh Shanmugasundaram. + +Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8a6de0453954095c269efc5054da53c73bfc8298) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -69,6 +69,13 @@ + clock-frequency = <0>; + }; + ++ /* External CAN clock - to be overridden by boards that provide it */ ++ can_clk: can { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <0>; ++ }; ++ + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; diff --git a/patches.renesas/0026-arm64-dts-r8a7796-Add-CAN-support.patch b/patches.renesas/0026-arm64-dts-r8a7796-Add-CAN-support.patch new file mode 100644 index 0000000000000..a27933632a392 --- /dev/null +++ b/patches.renesas/0026-arm64-dts-r8a7796-Add-CAN-support.patch @@ -0,0 +1,59 @@ +From cdd6d58e95966097b125c2a03b1df0b3af733562 Mon Sep 17 00:00:00 2001 +From: Chris Paterson <chris.paterson2@renesas.com> +Date: Thu, 24 Nov 2016 16:13:40 +0000 +Subject: [PATCH 026/255] arm64: dts: r8a7796: Add CAN support + +Adds CAN controller nodes for r8a7796. + +Based on a patch for r8a7795 by Ramesh Shanmugasundaram. + +Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> +Acked-by: Rob Herring <robh@kernel.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 909c1625241515aa2a5027a24e17d77b54e8ce4b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -367,6 +367,36 @@ + status = "disabled"; + }; + ++ can0: can@e6c30000 { ++ compatible = "renesas,can-r8a7796", ++ "renesas,rcar-gen3-can"; ++ reg = <0 0xe6c30000 0 0x1000>; ++ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 916>, ++ <&cpg CPG_CORE R8A7796_CLK_CANFD>, ++ <&can_clk>; ++ clock-names = "clkp1", "clkp2", "can_clk"; ++ assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; ++ assigned-clock-rates = <40000000>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ ++ can1: can@e6c38000 { ++ compatible = "renesas,can-r8a7796", ++ "renesas,rcar-gen3-can"; ++ reg = <0 0xe6c38000 0 0x1000>; ++ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 915>, ++ <&cpg CPG_CORE R8A7796_CLK_CANFD>, ++ <&can_clk>; ++ clock-names = "clkp1", "clkp2", "can_clk"; ++ assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; ++ assigned-clock-rates = <40000000>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; diff --git a/patches.renesas/0027-arm64-dts-r8a7796-Add-CAN-FD-support.patch b/patches.renesas/0027-arm64-dts-r8a7796-Add-CAN-FD-support.patch new file mode 100644 index 0000000000000..8db1d857d4178 --- /dev/null +++ b/patches.renesas/0027-arm64-dts-r8a7796-Add-CAN-FD-support.patch @@ -0,0 +1,53 @@ +From ee2d4217219d57e5c2c91be1d8367bdbdc118aa6 Mon Sep 17 00:00:00 2001 +From: Chris Paterson <chris.paterson2@renesas.com> +Date: Thu, 24 Nov 2016 16:13:41 +0000 +Subject: [PATCH 027/255] arm64: dts: r8a7796: Add CAN FD support + +Adds CAN FD controller node for r8a7796. + +Based on a patch for r8a7795 by Ramesh Shanmugasundaram. + +Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> +Acked-by: Rob Herring <robh@kernel.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f4176d7c7c03ed23d8335465f309b44519fb6ad5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -397,6 +397,30 @@ + status = "disabled"; + }; + ++ canfd: can@e66c0000 { ++ compatible = "renesas,r8a7796-canfd", ++ "renesas,rcar-gen3-canfd"; ++ reg = <0 0xe66c0000 0 0x8000>; ++ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 914>, ++ <&cpg CPG_CORE R8A7796_CLK_CANFD>, ++ <&can_clk>; ++ clock-names = "fck", "canfd", "can_clk"; ++ assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; ++ assigned-clock-rates = <40000000>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ ++ channel0 { ++ status = "disabled"; ++ }; ++ ++ channel1 { ++ status = "disabled"; ++ }; ++ }; ++ + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; diff --git a/patches.renesas/0028-arm64-renesas-r8a7796-salvator-x-Add-board-part-numb.patch b/patches.renesas/0028-arm64-renesas-r8a7796-salvator-x-Add-board-part-numb.patch new file mode 100644 index 0000000000000..66175f513c47a --- /dev/null +++ b/patches.renesas/0028-arm64-renesas-r8a7796-salvator-x-Add-board-part-numb.patch @@ -0,0 +1,25 @@ +From ec2147f183a5247f7e767f3921696b3c2fcec25b Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 31 Aug 2016 11:17:34 +0200 +Subject: [PATCH 028/255] arm64: renesas: r8a7796/salvator-x: Add board part + number to DT bindings + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6be91f865660d56081fe67e969a4adf71c24cada) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/arm/shmobile.txt | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/arm/shmobile.txt ++++ b/Documentation/devicetree/bindings/arm/shmobile.txt +@@ -75,7 +75,7 @@ Boards: + compatible = "renesas,rskrza1", "renesas,r7s72100" + - Salvator-X (RTP0RC7795SIPB0010S) + compatible = "renesas,salvator-x", "renesas,r8a7795"; +- - Salvator-X ++ - Salvator-X (RTP0RC7796SIPB0011S) + compatible = "renesas,salvator-x", "renesas,r8a7796"; + - SILK (RTP0RC7794LCB00011S) + compatible = "renesas,silk", "renesas,r8a7794" diff --git a/patches.renesas/0029-arm64-dts-r8a7795-Use-renesas-rcar-gen3-usb2-phy-fal.patch b/patches.renesas/0029-arm64-dts-r8a7795-Use-renesas-rcar-gen3-usb2-phy-fal.patch new file mode 100644 index 0000000000000..3c1c9e799fa4e --- /dev/null +++ b/patches.renesas/0029-arm64-dts-r8a7795-Use-renesas-rcar-gen3-usb2-phy-fal.patch @@ -0,0 +1,50 @@ +From f058bd77cbb9a082eafee56f45c4e99dd7d2330c Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 1 Dec 2016 15:25:54 +0100 +Subject: [PATCH 029/255] arm64: dts: r8a7795: Use renesas,rcar-gen3-usb2-phy + fallback binding + +A fallback binding for the Renesas R-Car Gen3 for USB2.0 PHY driver was +added by commit cde7bc367f09 ("phy: rcar-gen3-usb2: add fallback binding"). +This patch makes use of this binding in the DT for the r8a7795 SoC. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 6695092b34a3edd69b617e86bf34236ee8f2dbad) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -1147,7 +1147,8 @@ + }; + + usb2_phy0: usb-phy@ee080200 { +- compatible = "renesas,usb2-phy-r8a7795"; ++ compatible = "renesas,usb2-phy-r8a7795", ++ "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; +@@ -1157,7 +1158,8 @@ + }; + + usb2_phy1: usb-phy@ee0a0200 { +- compatible = "renesas,usb2-phy-r8a7795"; ++ compatible = "renesas,usb2-phy-r8a7795", ++ "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +@@ -1166,7 +1168,8 @@ + }; + + usb2_phy2: usb-phy@ee0c0200 { +- compatible = "renesas,usb2-phy-r8a7795"; ++ compatible = "renesas,usb2-phy-r8a7795", ++ "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0c0200 0 0x700>; + clocks = <&cpg CPG_MOD 701>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; diff --git a/patches.renesas/0030-arm64-dts-r8a7795-add-sound-CTU-support.patch b/patches.renesas/0030-arm64-dts-r8a7795-add-sound-CTU-support.patch new file mode 100644 index 0000000000000..81449d5856b82 --- /dev/null +++ b/patches.renesas/0030-arm64-dts-r8a7795-add-sound-CTU-support.patch @@ -0,0 +1,63 @@ +From f2fec975c47503b8f5c4c605d4ffb9b8dc965b3e Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 6 Dec 2016 03:54:21 +0000 +Subject: [PATCH 030/255] arm64: dts: r8a7795: add sound CTU support + +This patch adds CTU (= Channel Transfer Unit) support which is needed +to sound mixing. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c9293d784d32c868e83079bb6d1e26f316c4148d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 1 + + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 13 +++++++++++++ + 2 files changed, 14 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +@@ -412,6 +412,7 @@ + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, ++ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, + <&audio_clk_c>, +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -920,6 +920,7 @@ + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, ++ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, +@@ -931,6 +932,7 @@ + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", ++ "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +@@ -947,6 +949,17 @@ + }; + }; + ++ rcar_sound,ctu { ++ ctu00: ctu-0 { }; ++ ctu01: ctu-1 { }; ++ ctu02: ctu-2 { }; ++ ctu03: ctu-3 { }; ++ ctu10: ctu-4 { }; ++ ctu11: ctu-5 { }; ++ ctu12: ctu-6 { }; ++ ctu13: ctu-7 { }; ++ }; ++ + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; diff --git a/patches.renesas/0031-arm64-dts-r8a7795-add-sound-MIX-support.patch b/patches.renesas/0031-arm64-dts-r8a7795-add-sound-MIX-support.patch new file mode 100644 index 0000000000000..4c32adddd78bf --- /dev/null +++ b/patches.renesas/0031-arm64-dts-r8a7795-add-sound-MIX-support.patch @@ -0,0 +1,56 @@ +From 4631bdf784ac6f168fd150e38a6fb621c218d01d Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 6 Dec 2016 03:54:58 +0000 +Subject: [PATCH 031/255] arm64: dts: r8a7795: add sound MIX support + +This patch adds MIX (= Mixer) support. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ad5805f3aa07c6eb6ef2578ee9b5f8ca9b0c28f2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 1 + + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 7 +++++++ + 2 files changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +@@ -413,6 +413,7 @@ + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, ++ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, + <&audio_clk_c>, +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -921,6 +921,7 @@ + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, ++ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, +@@ -932,6 +933,7 @@ + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", ++ "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; +@@ -949,6 +951,11 @@ + }; + }; + ++ rcar_sound,mix { ++ mix0: mix-0 { }; ++ mix1: mix-1 { }; ++ }; ++ + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; diff --git a/patches.renesas/0032-arm64-dts-r8a7795-Use-Gen-3-fallback-compat-string-f.patch b/patches.renesas/0032-arm64-dts-r8a7795-Use-Gen-3-fallback-compat-string-f.patch new file mode 100644 index 0000000000000..a8f0914b97fcd --- /dev/null +++ b/patches.renesas/0032-arm64-dts-r8a7795-Use-Gen-3-fallback-compat-string-f.patch @@ -0,0 +1,39 @@ +From 07a84ced16f62560cd753eee675132261eef86c4 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 8 Dec 2016 16:29:29 +0100 +Subject: [PATCH 032/255] arm64: dts: r8a7795: Use Gen 3 fallback compat string + for PCIE + +Use recently added en 3 fallback compat string for PCIE +in r8a7795 DT. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit fb04f4b8bd7ecf337a8cbebe176e0bbdd954ba31) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -1280,7 +1280,8 @@ + }; + + pciec0: pcie@fe000000 { +- compatible = "renesas,pcie-r8a7795"; ++ compatible = "renesas,pcie-r8a7795", ++ "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; +@@ -1305,7 +1306,8 @@ + }; + + pciec1: pcie@ee800000 { +- compatible = "renesas,pcie-r8a7795"; ++ compatible = "renesas,pcie-r8a7795", ++ "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; diff --git a/patches.renesas/0033-arm64-dts-r8a7795-Use-R-Car-Gen-3-fallback-binding-f.patch b/patches.renesas/0033-arm64-dts-r8a7795-Use-R-Car-Gen-3-fallback-binding-f.patch new file mode 100644 index 0000000000000..0745ac04f9d71 --- /dev/null +++ b/patches.renesas/0033-arm64-dts-r8a7795-Use-R-Car-Gen-3-fallback-binding-f.patch @@ -0,0 +1,93 @@ +From 69913ba5781503151b092a8be5f297a9eba1f3f3 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:54 +0100 +Subject: [PATCH 033/255] arm64: dts: r8a7795: Use R-Car Gen 3 fallback binding + for i2c nodes + +Use recently added R-Car Gen 3 fallback binding for i2c nodes in +DT for r8a7795 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7795 and the +fallback binding for R-Car Gen 3. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit d8ebefc9ace7c9810fd433e6ff18559e7c2f228a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 21 ++++++++++++++------- + 1 file changed, 14 insertions(+), 7 deletions(-) + +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -793,7 +793,8 @@ + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795"; ++ compatible = "renesas,i2c-r8a7795", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; +@@ -807,7 +808,8 @@ + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795"; ++ compatible = "renesas,i2c-r8a7795", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; +@@ -821,7 +823,8 @@ + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795"; ++ compatible = "renesas,i2c-r8a7795", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; +@@ -835,7 +838,8 @@ + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795"; ++ compatible = "renesas,i2c-r8a7795", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; +@@ -849,7 +853,8 @@ + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795"; ++ compatible = "renesas,i2c-r8a7795", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; +@@ -863,7 +868,8 @@ + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795"; ++ compatible = "renesas,i2c-r8a7795", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 919>; +@@ -877,7 +883,8 @@ + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7795"; ++ compatible = "renesas,i2c-r8a7795", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; diff --git a/patches.renesas/0034-arm64-dts-r8a7796-Use-R-Car-Gen-3-fallback-binding-f.patch b/patches.renesas/0034-arm64-dts-r8a7796-Use-R-Car-Gen-3-fallback-binding-f.patch new file mode 100644 index 0000000000000..26608edbbfc98 --- /dev/null +++ b/patches.renesas/0034-arm64-dts-r8a7796-Use-R-Car-Gen-3-fallback-binding-f.patch @@ -0,0 +1,93 @@ +From 7a3649c6a909b6b59971ac3a8ebc4ff9070ff433 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:55 +0100 +Subject: [PATCH 034/255] arm64: dts: r8a7796: Use R-Car Gen 3 fallback binding + for i2c nodes + +Use recently added R-Car Gen 3 fallback binding for i2c nodes in +DT for r8a7796 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7796 and the +fallback binding for R-Car Gen 3. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 5553e2196229501346f262a9ebdc4e4ed74ff45c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 21 ++++++++++++++------- + 1 file changed, 14 insertions(+), 7 deletions(-) + +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -269,7 +269,8 @@ + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796"; ++ compatible = "renesas,i2c-r8a7796", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; +@@ -284,7 +285,8 @@ + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796"; ++ compatible = "renesas,i2c-r8a7796", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; +@@ -299,7 +301,8 @@ + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796"; ++ compatible = "renesas,i2c-r8a7796", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; +@@ -314,7 +317,8 @@ + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796"; ++ compatible = "renesas,i2c-r8a7796", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; +@@ -328,7 +332,8 @@ + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796"; ++ compatible = "renesas,i2c-r8a7796", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; +@@ -342,7 +347,8 @@ + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796"; ++ compatible = "renesas,i2c-r8a7796", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 919>; +@@ -356,7 +362,8 @@ + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7796"; ++ compatible = "renesas,i2c-r8a7796", ++ "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; diff --git a/patches.renesas/0035-arm64-dts-r8a7796-salvator-x-Update-memory-node-to-4.patch b/patches.renesas/0035-arm64-dts-r8a7796-salvator-x-Update-memory-node-to-4.patch new file mode 100644 index 0000000000000..49f572ade75b5 --- /dev/null +++ b/patches.renesas/0035-arm64-dts-r8a7796-salvator-x-Update-memory-node-to-4.patch @@ -0,0 +1,40 @@ +From 61828dfa0f81f537d5ce84b1d6b843c3fa4a89ee Mon Sep 17 00:00:00 2001 +From: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Date: Thu, 15 Dec 2016 16:31:29 +0100 +Subject: [PATCH 035/255] arm64: dts: r8a7796: salvator-x: Update memory node + to 4 GiB map + +This patch updates memory region: + + - After changes, the new map of the Salvator-X board on R8A7796 SoC + Bank0: 2GiB RAM : 0x000048000000 -> 0x000bfffffff + Bank1: 2GiB RAM : 0x000600000000 -> 0x0067fffffff + + - Before changes, the old map looked like this: + Bank0: 2GiB RAM : 0x000048000000 -> 0x000bfffffff + +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +[geert: Correct size of old map] +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit d78fcc47e6814605eb90cd4ab1d79f9609ff32a4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +@@ -31,6 +31,11 @@ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + ++ memory@600000000 { ++ device_type = "memory"; ++ reg = <0x6 0x00000000 0x0 0x80000000>; ++ }; ++ + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; diff --git a/patches.renesas/0036-arm64-dts-renesas-r8a7796-Add-EthernetAVB-instance.patch b/patches.renesas/0036-arm64-dts-renesas-r8a7796-Add-EthernetAVB-instance.patch new file mode 100644 index 0000000000000..b9e75eff0dcfd --- /dev/null +++ b/patches.renesas/0036-arm64-dts-renesas-r8a7796-Add-EthernetAVB-instance.patch @@ -0,0 +1,67 @@ +From d8dde26fe15b3bf7e1b46c30d4e57512c0173846 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 6 Sep 2016 11:25:51 +0300 +Subject: [PATCH 036/255] arm64: dts: renesas: r8a7796: Add EthernetAVB + instance + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8e8b9eaef8fb05d9707087ea82c1c928317ac9f8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 43 +++++++++++++++++++++++++++++++ + 1 file changed, 43 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -428,6 +428,49 @@ + }; + }; + ++ avb: ethernet@e6800000 { ++ compatible = "renesas,etheravb-r8a7796", ++ "renesas,etheravb-rcar-gen3"; ++ reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; ++ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "ch0", "ch1", "ch2", "ch3", ++ "ch4", "ch5", "ch6", "ch7", ++ "ch8", "ch9", "ch10", "ch11", ++ "ch12", "ch13", "ch14", "ch15", ++ "ch16", "ch17", "ch18", "ch19", ++ "ch20", "ch21", "ch22", "ch23", ++ "ch24"; ++ clocks = <&cpg CPG_MOD 812>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ phy-mode = "rgmii-id"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; diff --git a/patches.renesas/0037-arm64-dts-r8a7796-salvator-x-Enable-EthernetAVB.patch b/patches.renesas/0037-arm64-dts-r8a7796-salvator-x-Enable-EthernetAVB.patch new file mode 100644 index 0000000000000..369765db48942 --- /dev/null +++ b/patches.renesas/0037-arm64-dts-r8a7796-salvator-x-Enable-EthernetAVB.patch @@ -0,0 +1,71 @@ +From d9bd12de0413f118f0711966a07a28dc210ccbb9 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 15 Dec 2016 17:24:04 +0100 +Subject: [PATCH 037/255] arm64: dts: r8a7796: salvator-x: Enable EthernetAVB + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +[geert: Add pinctrl] +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit dc36965a890515753671628cdf25365ee45e6206) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 32 +++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +@@ -18,6 +18,7 @@ + + aliases { + serial0 = &scif2; ++ ethernet0 = &avb; + }; + + chosen { +@@ -107,6 +108,11 @@ + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + ++ avb_pins: avb { ++ groups = "avb_mdc"; ++ function = "avb"; ++ }; ++ + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; +@@ -158,6 +164,32 @@ + }; + }; + ++&avb { ++ pinctrl-0 = <&avb_pins>; ++ pinctrl-names = "default"; ++ renesas,no-ether-link; ++ phy-handle = <&phy0>; ++ status = "okay"; ++ ++ phy0: ethernet-phy@0 { ++ rxc-skew-ps = <900>; ++ rxdv-skew-ps = <0>; ++ rxd0-skew-ps = <0>; ++ rxd1-skew-ps = <0>; ++ rxd2-skew-ps = <0>; ++ rxd3-skew-ps = <0>; ++ txc-skew-ps = <900>; ++ txen-skew-ps = <0>; ++ txd0-skew-ps = <0>; ++ txd1-skew-ps = <0>; ++ txd2-skew-ps = <0>; ++ txd3-skew-ps = <0>; ++ reg = <0>; ++ interrupt-parent = <&gpio2>; ++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ + &extal_clk { + clock-frequency = <16666666>; + }; diff --git a/patches.renesas/0038-arm64-dts-r8a7796-Use-R-Car-Gen-3-fallback-binding-f.patch b/patches.renesas/0038-arm64-dts-r8a7796-Use-R-Car-Gen-3-fallback-binding-f.patch new file mode 100644 index 0000000000000..df67ff2ba3031 --- /dev/null +++ b/patches.renesas/0038-arm64-dts-r8a7796-Use-R-Car-Gen-3-fallback-binding-f.patch @@ -0,0 +1,63 @@ +From 8ce1bc2358d2cfb975e4a32ef1d057ee70630cf5 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 20 Dec 2016 11:32:36 +0100 +Subject: [PATCH 038/255] arm64: dts: r8a7796: Use R-Car Gen 3 fallback binding + for msiof nodes + +Use recently added R-Car Gen 3 fallback binding for msiof nodes in +DT for r8a7796 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7796 and the +fallback binding for R-Car Gen 3. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 8b51f97138ca22b6ae728a434215a05b7e5bbc63) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -485,7 +485,8 @@ + }; + + msiof0: spi@e6e90000 { +- compatible = "renesas,msiof-r8a7796"; ++ compatible = "renesas,msiof-r8a7796", ++ "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 211>; +@@ -499,7 +500,8 @@ + }; + + msiof1: spi@e6ea0000 { +- compatible = "renesas,msiof-r8a7796"; ++ compatible = "renesas,msiof-r8a7796", ++ "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 210>; +@@ -513,7 +515,8 @@ + }; + + msiof2: spi@e6c00000 { +- compatible = "renesas,msiof-r8a7796"; ++ compatible = "renesas,msiof-r8a7796", ++ "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 209>; +@@ -526,7 +529,8 @@ + }; + + msiof3: spi@e6c10000 { +- compatible = "renesas,msiof-r8a7796"; ++ compatible = "renesas,msiof-r8a7796", ++ "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; diff --git a/patches.renesas/0039-arm64-dts-r8a7795-Add-PWM-support.patch b/patches.renesas/0039-arm64-dts-r8a7795-Add-PWM-support.patch new file mode 100644 index 0000000000000..eed758ccd142b --- /dev/null +++ b/patches.renesas/0039-arm64-dts-r8a7795-Add-PWM-support.patch @@ -0,0 +1,89 @@ +From 3d165529b731fd8584981792cdd50fea0a95b776 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sat, 19 Nov 2016 05:28:07 +0200 +Subject: [PATCH 039/255] arm64: dts: r8a7795: Add PWM support + +Add the 7 PWM channels to the r8a7795 device tree, in the disabled +state. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b2b9443beee5017ebdb3f2be9ef472c73d260481) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 63 +++++++++++++++++++++++++++++++ + 1 file changed, 63 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -895,6 +895,69 @@ + status = "disabled"; + }; + ++ pwm0: pwm@e6e30000 { ++ compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; ++ reg = <0 0xe6e30000 0 0x8>; ++ clocks = <&cpg CPG_MOD 523>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ #pwm-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ pwm1: pwm@e6e31000 { ++ compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; ++ reg = <0 0xe6e31000 0 0x8>; ++ clocks = <&cpg CPG_MOD 523>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ #pwm-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ pwm2: pwm@e6e32000 { ++ compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; ++ reg = <0 0xe6e32000 0 0x8>; ++ clocks = <&cpg CPG_MOD 523>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ #pwm-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ pwm3: pwm@e6e33000 { ++ compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; ++ reg = <0 0xe6e33000 0 0x8>; ++ clocks = <&cpg CPG_MOD 523>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ #pwm-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ pwm4: pwm@e6e34000 { ++ compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; ++ reg = <0 0xe6e34000 0 0x8>; ++ clocks = <&cpg CPG_MOD 523>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ #pwm-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ pwm5: pwm@e6e35000 { ++ compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; ++ reg = <0 0xe6e35000 0 0x8>; ++ clocks = <&cpg CPG_MOD 523>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ #pwm-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ pwm6: pwm@e6e36000 { ++ compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; ++ reg = <0 0xe6e36000 0 0x8>; ++ clocks = <&cpg CPG_MOD 523>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ #pwm-cells = <2>; ++ status = "disabled"; ++ }; ++ + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required diff --git a/patches.renesas/0040-arm64-dts-h3ulcb-follow-sound-CTU-MIX-supports.patch b/patches.renesas/0040-arm64-dts-h3ulcb-follow-sound-CTU-MIX-supports.patch new file mode 100644 index 0000000000000..413598562b563 --- /dev/null +++ b/patches.renesas/0040-arm64-dts-h3ulcb-follow-sound-CTU-MIX-supports.patch @@ -0,0 +1,29 @@ +From f496fa5c538936fe7ec0ec90b9f1e0ac48f17e1a Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 10 Jan 2017 07:41:28 +0000 +Subject: [PATCH 040/255] arm64: dts: h3ulcb: follow sound CTU/MIX supports + +commit 5bcd74e8a30d9259 ("arm64: dts: r8a7795: add sound MIX support") +commit 5be5ee41d011f26b ("arm64: dts: r8a7795: add sound CTU support") +added MIX/CTU support, and it updated clocks on SoC level. +Thus, h3ulcb should be updated + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b1980ff0c335eedbba10ea99a2a9feebb79642f8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +@@ -277,6 +277,8 @@ + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, ++ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, ++ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, + <&audio_clk_c>, diff --git a/patches.renesas/0041-arm64-dts-r8a7795-Add-missing-power-domains-property.patch b/patches.renesas/0041-arm64-dts-r8a7795-Add-missing-power-domains-property.patch new file mode 100644 index 0000000000000..128f05a152ed8 --- /dev/null +++ b/patches.renesas/0041-arm64-dts-r8a7795-Add-missing-power-domains-property.patch @@ -0,0 +1,27 @@ +From 6efd53ebf22232b79a0827f133bcc9a9c2e2951c Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 16 Jan 2017 17:57:53 +0100 +Subject: [PATCH 041/255] arm64: dts: r8a7795: Add missing power-domains + property for sata + +This went unnoticed as the sata_rcar driver doesn't support Runtime PM +yet, but manages module clocks manually. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 2cab226c345378b3cff652a9c8232f5070d31216) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -1149,6 +1149,7 @@ + reg = <0 0xee300000 0 0x1fff>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + status = "disabled"; + }; + diff --git a/patches.renesas/0042-arm64-dts-r8a7795-Add-R-Car-Gen3-thermal-support.patch b/patches.renesas/0042-arm64-dts-r8a7795-Add-R-Car-Gen3-thermal-support.patch new file mode 100644 index 0000000000000..535adec48b87c --- /dev/null +++ b/patches.renesas/0042-arm64-dts-r8a7795-Add-R-Car-Gen3-thermal-support.patch @@ -0,0 +1,87 @@ +From 612601e9d5b0743e8b773b6daea4e9175150b486 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Fri, 20 Jan 2017 12:26:42 +0100 +Subject: [PATCH 042/255] arm64: dts: r8a7795: Add R-Car Gen3 thermal support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Hien Dang <hien.dang.eb@renesas.com> +Signed-off-by: Thao Nguyen <thao.nguyen.yb@rvc.renesas.com> +Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com> +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Acked-by: Eduardo Valentin <edubezval@gmail.com> +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b443cd1740a28195e965d78b9478a88117ea73f9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 58 +++++++++++++++++++++++++++++++ + 1 file changed, 58 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -1648,5 +1648,63 @@ + }; + }; + }; ++ ++ tsc: thermal@e6198000 { ++ compatible = "renesas,r8a7795-thermal"; ++ reg = <0 0xe6198000 0 0x68>, ++ <0 0xe61a0000 0 0x5c>, ++ <0 0xe61a8000 0 0x5c>; ++ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 522>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ #thermal-sensor-cells = <1>; ++ status = "okay"; ++ }; ++ ++ thermal-zones { ++ sensor_thermal1: sensor-thermal1 { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsc 0>; ++ ++ trips { ++ sensor1_crit: sensor1-crit { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ sensor_thermal2: sensor-thermal2 { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsc 1>; ++ ++ trips { ++ sensor2_crit: sensor2-crit { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ sensor_thermal3: sensor-thermal3 { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsc 2>; ++ ++ trips { ++ sensor3_crit: sensor3-crit { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; + }; + }; diff --git a/patches.renesas/0043-arm64-dts-r8a7796-Add-R-Car-Gen3-thermal-support.patch b/patches.renesas/0043-arm64-dts-r8a7796-Add-R-Car-Gen3-thermal-support.patch new file mode 100644 index 0000000000000..164eda3a7caae --- /dev/null +++ b/patches.renesas/0043-arm64-dts-r8a7796-Add-R-Car-Gen3-thermal-support.patch @@ -0,0 +1,87 @@ +From a61ac2d76175c1a9516c9becd87aff9a37c4214e Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Fri, 20 Jan 2017 12:26:43 +0100 +Subject: [PATCH 043/255] arm64: dts: r8a7796: Add R-Car Gen3 thermal support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Hien Dang <hien.dang.eb@renesas.com> +Signed-off-by: Thao Nguyen <thao.nguyen.yb@rvc.renesas.com> +Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com> +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Acked-by: Eduardo Valentin <edubezval@gmail.com> +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit af25d1c2a9cac5fde6e77836c33a3689077ffd2a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 58 +++++++++++++++++++++++++++++++ + 1 file changed, 58 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -680,5 +680,63 @@ + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; ++ ++ tsc: thermal@e6198000 { ++ compatible = "renesas,r8a7796-thermal"; ++ reg = <0 0xe6198000 0 0x68>, ++ <0 0xe61a0000 0 0x5c>, ++ <0 0xe61a8000 0 0x5c>; ++ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 522>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ #thermal-sensor-cells = <1>; ++ status = "okay"; ++ }; ++ ++ thermal-zones { ++ sensor_thermal1: sensor-thermal1 { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsc 0>; ++ ++ trips { ++ sensor1_crit: sensor1-crit { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ sensor_thermal2: sensor-thermal2 { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsc 1>; ++ ++ trips { ++ sensor2_crit: sensor2-crit { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ sensor_thermal3: sensor-thermal3 { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsc 2>; ++ ++ trips { ++ sensor3_crit: sensor3-crit { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; + }; + }; diff --git a/patches.renesas/0044-arm64-dts-r8a7795-Link-ARM-GIC-to-clock-and-clock-do.patch b/patches.renesas/0044-arm64-dts-r8a7795-Link-ARM-GIC-to-clock-and-clock-do.patch new file mode 100644 index 0000000000000..01e5772aa5b03 --- /dev/null +++ b/patches.renesas/0044-arm64-dts-r8a7795-Link-ARM-GIC-to-clock-and-clock-do.patch @@ -0,0 +1,32 @@ +From 447566fcff6c7b5fc893f4139681b41ac15126f9 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 17 Jan 2017 13:49:19 +0100 +Subject: [PATCH 044/255] arm64: dts: r8a7795: Link ARM GIC to clock and clock + domain + +Link the ARM GIC to the INTC-AP module clock, and add it to the SYSC +"always-on" PM Domain, so it can be power managed using that clock. + +Note that currently the GIC-400 driver doesn't support module clocks nor +Runtime PM, so this must be handled as a critical clock. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b6e56e4c1fd747028437956f48832452462ef407) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -166,6 +166,9 @@ + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; ++ clocks = <&cpg CPG_MOD 408>; ++ clock-names = "clk"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + }; + + wdt0: watchdog@e6020000 { diff --git a/patches.renesas/0045-arm64-dts-r8a7796-Link-ARM-GIC-to-clock-and-clock-do.patch b/patches.renesas/0045-arm64-dts-r8a7796-Link-ARM-GIC-to-clock-and-clock-do.patch new file mode 100644 index 0000000000000..a75e4aa6d0f0b --- /dev/null +++ b/patches.renesas/0045-arm64-dts-r8a7796-Link-ARM-GIC-to-clock-and-clock-do.patch @@ -0,0 +1,32 @@ +From b26e82cebba6027bf5c87efcc68fb2048e6cf5c1 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 17 Jan 2017 13:49:20 +0100 +Subject: [PATCH 045/255] arm64: dts: r8a7796: Link ARM GIC to clock and clock + domain + +Link the ARM GIC to the INTC-AP module clock, and add it to the SYSC +"always-on" PM Domain, so it can be power managed using that clock. + +Note that currently the GIC-400 driver doesn't support module clocks nor +Runtime PM, so this must be handled as a critical clock. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0bacdbc76b5aad0c109198e0b289d759e0cb9a9b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -101,6 +101,9 @@ + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; ++ clocks = <&cpg CPG_MOD 408>; ++ clock-names = "clk"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + timer { diff --git a/patches.renesas/0046-arm64-dts-r8a7795-tidyup-audma-definition-order.patch b/patches.renesas/0046-arm64-dts-r8a7795-tidyup-audma-definition-order.patch new file mode 100644 index 0000000000000..bb57dff22f4fe --- /dev/null +++ b/patches.renesas/0046-arm64-dts-r8a7795-tidyup-audma-definition-order.patch @@ -0,0 +1,166 @@ +From 28b3bfb56d3b652e9e9a8eb897cf64ebfe3186ce Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 21 Dec 2016 04:56:54 +0000 +Subject: [PATCH 046/255] arm64: dts: r8a7795: tidyup audma definition order + +Current r8a7795.dtsi defines audma -> ipmmu -> dma order. +Because of this order, dma can connect to ipmmu, but +audma can't connect to it. +This patch moves audma order as ipmmu -> dma -> audma. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 769fa8369b9db469ffacb356766b78dd1c7eae5a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 132 +++++++++++++++---------------- + 1 file changed, 66 insertions(+), 66 deletions(-) + +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -340,72 +340,6 @@ + #power-domain-cells = <1>; + }; + +- audma0: dma-controller@ec700000 { +- compatible = "renesas,dmac-r8a7795", +- "renesas,rcar-dmac"; +- reg = <0 0xec700000 0 0x10000>; +- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 502>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #dma-cells = <1>; +- dma-channels = <16>; +- }; +- +- audma1: dma-controller@ec720000 { +- compatible = "renesas,dmac-r8a7795", +- "renesas,rcar-dmac"; +- reg = <0 0xec720000 0 0x10000>; +- interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH +- GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "error", +- "ch0", "ch1", "ch2", "ch3", +- "ch4", "ch5", "ch6", "ch7", +- "ch8", "ch9", "ch10", "ch11", +- "ch12", "ch13", "ch14", "ch15"; +- clocks = <&cpg CPG_MOD 501>; +- clock-names = "fck"; +- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- #dma-cells = <1>; +- dma-channels = <16>; +- }; +- + pfc: pfc@e6060000 { + compatible = "renesas,pfc-r8a7795"; + reg = <0 0xe6060000 0 0x50c>; +@@ -522,6 +456,72 @@ + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #dma-cells = <1>; ++ dma-channels = <16>; ++ }; ++ ++ audma0: dma-controller@ec700000 { ++ compatible = "renesas,dmac-r8a7795", ++ "renesas,rcar-dmac"; ++ reg = <0 0xec700000 0 0x10000>; ++ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "error", ++ "ch0", "ch1", "ch2", "ch3", ++ "ch4", "ch5", "ch6", "ch7", ++ "ch8", "ch9", "ch10", "ch11", ++ "ch12", "ch13", "ch14", "ch15"; ++ clocks = <&cpg CPG_MOD 502>; ++ clock-names = "fck"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ #dma-cells = <1>; ++ dma-channels = <16>; ++ }; ++ ++ audma1: dma-controller@ec720000 { ++ compatible = "renesas,dmac-r8a7795", ++ "renesas,rcar-dmac"; ++ reg = <0 0xec720000 0 0x10000>; ++ interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH ++ GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "error", ++ "ch0", "ch1", "ch2", "ch3", ++ "ch4", "ch5", "ch6", "ch7", ++ "ch8", "ch9", "ch10", "ch11", ++ "ch12", "ch13", "ch14", "ch15"; ++ clocks = <&cpg CPG_MOD 501>; ++ clock-names = "fck"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ #dma-cells = <1>; + dma-channels = <16>; + }; + diff --git a/patches.renesas/0047-arm64-dts-r8a7796-Mark-EthernetAVB-device-node-disab.patch b/patches.renesas/0047-arm64-dts-r8a7796-Mark-EthernetAVB-device-node-disab.patch new file mode 100644 index 0000000000000..f230e46cb606a --- /dev/null +++ b/patches.renesas/0047-arm64-dts-r8a7796-Mark-EthernetAVB-device-node-disab.patch @@ -0,0 +1,28 @@ +From c7dbf8b2634e3d952cc5c3e3fa4478db6bcab6e1 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 25 Jan 2017 14:19:31 +0100 +Subject: [PATCH 047/255] arm64: dts: r8a7796: Mark EthernetAVB device node + disabled + +Device nodes representing I/O devices should be marked disabled in the +SoC-specific DTS, and overridden by board-specific DTSes where needed. + +Fixes: 8e8b9eaef8fb05d9 ("arm64: dts: renesas: r8a7796: Add EthernetAVB instance") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7e1c23b94ed7f0d2719795a9828402003de5335d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -472,6 +472,7 @@ + phy-mode = "rgmii-id"; + #address-cells = <1>; + #size-cells = <0>; ++ status = "disabled"; + }; + + scif2: serial@e6e88000 { diff --git a/patches.renesas/0048-Input-gpio-keys-add-support-for-setkeycode.patch b/patches.renesas/0048-Input-gpio-keys-add-support-for-setkeycode.patch new file mode 100644 index 0000000000000..c12e631b5817c --- /dev/null +++ b/patches.renesas/0048-Input-gpio-keys-add-support-for-setkeycode.patch @@ -0,0 +1,177 @@ +From 1a3a2b379659d6b4f9c6113f227d33fb1f7c3161 Mon Sep 17 00:00:00 2001 +From: Hans de Goede <hdegoede@redhat.com> +Date: Sat, 21 Jan 2017 11:16:47 -0800 +Subject: [PATCH 048/255] Input: gpio-keys - add support for setkeycode + +gpio-keys input devices created by the soc_button_array driver are +configured with key-codes based on ACPI provided information. + +Unfortunately on some tablets this info is wrong, and we need to have +a quirk to fix things up. + +Add support for input_setkeycode to the gpio-keys driver, so that +the existing udev hwdb mechanism can be used to fix things up on these +tablets. + +Signed-off-by: Hans de Goede <hdegoede@redhat.com> +Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> +(cherry picked from commit 83e4947a569f4d544ef4a1361f51c91d73a9c915) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/input/keyboard/gpio_keys.c | 40 +++++++++++++++++++++++++------------ + 1 file changed, 28 insertions(+), 12 deletions(-) + +--- a/drivers/input/keyboard/gpio_keys.c ++++ b/drivers/input/keyboard/gpio_keys.c +@@ -36,6 +36,8 @@ struct gpio_button_data { + struct input_dev *input; + struct gpio_desc *gpiod; + ++ unsigned short *code; ++ + struct timer_list release_timer; + unsigned int release_delay; /* in msecs, for IRQ-only buttons */ + +@@ -52,6 +54,7 @@ struct gpio_keys_drvdata { + const struct gpio_keys_platform_data *pdata; + struct input_dev *input; + struct mutex disable_lock; ++ unsigned short *keymap; + struct gpio_button_data data[0]; + }; + +@@ -203,7 +206,7 @@ static ssize_t gpio_keys_attr_show_helpe + if (only_disabled && !bdata->disabled) + continue; + +- __set_bit(bdata->button->code, bits); ++ __set_bit(*bdata->code, bits); + } + + ret = scnprintf(buf, PAGE_SIZE - 1, "%*pbl", n_events, bits); +@@ -254,7 +257,7 @@ static ssize_t gpio_keys_attr_store_help + if (bdata->button->type != type) + continue; + +- if (test_bit(bdata->button->code, bits) && ++ if (test_bit(*bdata->code, bits) && + !bdata->button->can_disable) { + error = -EINVAL; + goto out; +@@ -269,7 +272,7 @@ static ssize_t gpio_keys_attr_store_help + if (bdata->button->type != type) + continue; + +- if (test_bit(bdata->button->code, bits)) ++ if (test_bit(*bdata->code, bits)) + gpio_keys_disable_button(bdata); + else + gpio_keys_enable_button(bdata); +@@ -371,7 +374,7 @@ static void gpio_keys_gpio_report_event( + if (state) + input_event(input, type, button->code, button->value); + } else { +- input_event(input, type, button->code, state); ++ input_event(input, type, *bdata->code, state); + } + input_sync(input); + } +@@ -411,7 +414,7 @@ static void gpio_keys_irq_timer(unsigned + + spin_lock_irqsave(&bdata->lock, flags); + if (bdata->key_pressed) { +- input_event(input, EV_KEY, bdata->button->code, 0); ++ input_event(input, EV_KEY, *bdata->code, 0); + input_sync(input); + bdata->key_pressed = false; + } +@@ -421,7 +424,6 @@ static void gpio_keys_irq_timer(unsigned + static irqreturn_t gpio_keys_irq_isr(int irq, void *dev_id) + { + struct gpio_button_data *bdata = dev_id; +- const struct gpio_keys_button *button = bdata->button; + struct input_dev *input = bdata->input; + unsigned long flags; + +@@ -433,11 +435,11 @@ static irqreturn_t gpio_keys_irq_isr(int + if (bdata->button->wakeup) + pm_wakeup_event(bdata->input->dev.parent, 0); + +- input_event(input, EV_KEY, button->code, 1); ++ input_event(input, EV_KEY, *bdata->code, 1); + input_sync(input); + + if (!bdata->release_delay) { +- input_event(input, EV_KEY, button->code, 0); ++ input_event(input, EV_KEY, *bdata->code, 0); + input_sync(input); + goto out; + } +@@ -465,12 +467,14 @@ static void gpio_keys_quiesce_key(void * + + static int gpio_keys_setup_key(struct platform_device *pdev, + struct input_dev *input, +- struct gpio_button_data *bdata, ++ struct gpio_keys_drvdata *ddata, + const struct gpio_keys_button *button, ++ int idx, + struct fwnode_handle *child) + { + const char *desc = button->desc ? button->desc : "gpio_keys"; + struct device *dev = &pdev->dev; ++ struct gpio_button_data *bdata = &ddata->data[idx]; + irq_handler_t isr; + unsigned long irqflags; + int irq; +@@ -577,7 +581,9 @@ static int gpio_keys_setup_key(struct pl + irqflags = 0; + } + +- input_set_capability(input, button->type ?: EV_KEY, button->code); ++ bdata->code = &ddata->keymap[idx]; ++ *bdata->code = button->code; ++ input_set_capability(input, button->type ?: EV_KEY, *bdata->code); + + /* + * Install custom action to cancel release timer and +@@ -750,6 +756,12 @@ static int gpio_keys_probe(struct platfo + return -ENOMEM; + } + ++ ddata->keymap = devm_kcalloc(dev, ++ pdata->nbuttons, sizeof(ddata->keymap[0]), ++ GFP_KERNEL); ++ if (!ddata->keymap) ++ return -ENOMEM; ++ + input = devm_input_allocate_device(dev); + if (!input) { + dev_err(dev, "failed to allocate input device\n"); +@@ -774,13 +786,16 @@ static int gpio_keys_probe(struct platfo + input->id.product = 0x0001; + input->id.version = 0x0100; + ++ input->keycode = ddata->keymap; ++ input->keycodesize = sizeof(ddata->keymap[0]); ++ input->keycodemax = pdata->nbuttons; ++ + /* Enable auto repeat feature of Linux input subsystem */ + if (pdata->rep) + __set_bit(EV_REP, input->evbit); + + for (i = 0; i < pdata->nbuttons; i++) { + const struct gpio_keys_button *button = &pdata->buttons[i]; +- struct gpio_button_data *bdata = &ddata->data[i]; + + if (!dev_get_platdata(dev)) { + child = device_get_next_child_node(&pdev->dev, child); +@@ -792,7 +807,8 @@ static int gpio_keys_probe(struct platfo + } + } + +- error = gpio_keys_setup_key(pdev, input, bdata, button, child); ++ error = gpio_keys_setup_key(pdev, input, ddata, ++ button, i, child); + if (error) { + fwnode_handle_put(child); + return error; diff --git a/patches.renesas/0049-gpio-rcar-set-IRQ-chip-parent_device.patch b/patches.renesas/0049-gpio-rcar-set-IRQ-chip-parent_device.patch new file mode 100644 index 0000000000000..686e610d9ed51 --- /dev/null +++ b/patches.renesas/0049-gpio-rcar-set-IRQ-chip-parent_device.patch @@ -0,0 +1,34 @@ +From bcf23f922df099e99b6ffa0050894eb73f316067 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Thu, 8 Dec 2016 18:32:27 +0100 +Subject: [PATCH 049/255] gpio: rcar: set IRQ chip parent_device +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This enables Runtime PM handling for interrupts. + +By setting the parent_device in struct irq_chip genirq will call the +pm_runtime_get/put APIs when an IRQ is requested/freed. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 47bd38a31adcd5b92f5e11919a101a310305dbb1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpio/gpio-rcar.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpio/gpio-rcar.c ++++ b/drivers/gpio/gpio-rcar.c +@@ -460,6 +460,7 @@ static int gpio_rcar_probe(struct platfo + + irq_chip = &p->irq_chip; + irq_chip->name = name; ++ irq_chip->parent_device = dev; + irq_chip->irq_mask = gpio_rcar_irq_disable; + irq_chip->irq_unmask = gpio_rcar_irq_enable; + irq_chip->irq_set_type = gpio_rcar_irq_set_type; diff --git a/patches.renesas/0050-gpio-rcar-Fine-grained-Runtime-PM-support.patch b/patches.renesas/0050-gpio-rcar-Fine-grained-Runtime-PM-support.patch new file mode 100644 index 0000000000000..0b5f51e3cf9c4 --- /dev/null +++ b/patches.renesas/0050-gpio-rcar-Fine-grained-Runtime-PM-support.patch @@ -0,0 +1,96 @@ +From 4486d679f997a2f6e9217aebdf2fce73df96f975 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 8 Dec 2016 18:32:28 +0100 +Subject: [PATCH 050/255] gpio: rcar: Fine-grained Runtime PM support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Currently gpio modules are runtime-resumed at probe time. This means the +gpio module will be active all the time (except during system suspend, +if not configured as a wake-up source). + +While an R-Car Gen2 gpio module retains pins configured for output at +the requested level while put in standby mode, gpio register cannot be +accessed while suspended. Unfortunately pm_runtime_get_sync() cannot be +called from all contexts where gpio register access is needed. Hence +move the Runtime PM handling from probe/remove time to gpio request/free +time, which is probably the best we can do. + +On r8a7791/koelsch, gpio modules 0, 1, 3, and 4 are now suspended during +normal use (gpio2 is used for LEDs and regulators, gpio5 for keys, gpio6 +for SD-Card CD & WP, gpio7 for keys and regulators). + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +[Niklas: s/gpio_to_priv(chip)/gpiochip_get_data(chip)/] +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> + +(cherry picked from commit 2d65472bcb3f2e1f305529655bb06054dc9e2804) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpio/gpio-rcar.c | 20 ++++++++++++++++---- + 1 file changed, 16 insertions(+), 4 deletions(-) + +--- a/drivers/gpio/gpio-rcar.c ++++ b/drivers/gpio/gpio-rcar.c +@@ -242,11 +242,24 @@ static void gpio_rcar_config_general_inp + + static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) + { +- return pinctrl_request_gpio(chip->base + offset); ++ struct gpio_rcar_priv *p = gpiochip_get_data(chip); ++ int error; ++ ++ error = pm_runtime_get_sync(&p->pdev->dev); ++ if (error < 0) ++ return error; ++ ++ error = pinctrl_request_gpio(chip->base + offset); ++ if (error) ++ pm_runtime_put(&p->pdev->dev); ++ ++ return error; + } + + static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) + { ++ struct gpio_rcar_priv *p = gpiochip_get_data(chip); ++ + pinctrl_free_gpio(chip->base + offset); + + /* +@@ -254,6 +267,8 @@ static void gpio_rcar_free(struct gpio_c + * drive the GPIO pin as an output. + */ + gpio_rcar_config_general_input_output_mode(chip, offset, false); ++ ++ pm_runtime_put(&p->pdev->dev); + } + + static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) +@@ -426,7 +441,6 @@ static int gpio_rcar_probe(struct platfo + } + + pm_runtime_enable(dev); +- pm_runtime_get_sync(dev); + + io = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); +@@ -495,7 +509,6 @@ static int gpio_rcar_probe(struct platfo + err1: + gpiochip_remove(gpio_chip); + err0: +- pm_runtime_put(dev); + pm_runtime_disable(dev); + return ret; + } +@@ -506,7 +519,6 @@ static int gpio_rcar_remove(struct platf + + gpiochip_remove(&p->gpio_chip); + +- pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); + return 0; + } diff --git a/patches.renesas/0051-regulator-gpio-correct-default-type.patch b/patches.renesas/0051-regulator-gpio-correct-default-type.patch new file mode 100644 index 0000000000000..1619a8640af47 --- /dev/null +++ b/patches.renesas/0051-regulator-gpio-correct-default-type.patch @@ -0,0 +1,27 @@ +From 4fd8b3925f1f8dc07a30cc074641a432bbdda071 Mon Sep 17 00:00:00 2001 +From: Hans Holmberg <hans@pixelmunchies.com> +Date: Fri, 3 Feb 2017 15:29:12 +0100 +Subject: [PATCH 051/255] regulator: gpio: correct default type + +The driver defaults to voltage, not current, type so correct +this in the device tree binding documentation. + +Signed-off-by: Hans Holmberg <hans@pixelmunchies.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 17db9f386632c9c9182a3318b89b742be08c1c2a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/regulator/gpio-regulator.txt | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt ++++ b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt +@@ -13,7 +13,7 @@ Optional properties: + - startup-delay-us : Startup time in microseconds. + - enable-active-high : Polarity of GPIO is active high (default is low). + - regulator-type : Specifies what is being regulated, must be either +- "voltage" or "current", defaults to current. ++ "voltage" or "current", defaults to voltage. + + Any property defined as part of the core regulator binding defined in + regulator.txt can also be used. diff --git a/patches.renesas/0052-i2c-riic-correctly-finish-transfers.patch b/patches.renesas/0052-i2c-riic-correctly-finish-transfers.patch new file mode 100644 index 0000000000000..cecce7e8c9f88 --- /dev/null +++ b/patches.renesas/0052-i2c-riic-correctly-finish-transfers.patch @@ -0,0 +1,105 @@ +From 8d91806a403aacbaa2f12e41421008c79eaf6523 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Tue, 7 Feb 2017 21:41:22 -0500 +Subject: [PATCH 052/255] i2c: riic: correctly finish transfers + +This fixes the condition where the controller has not fully completed its +final transfer and leaves the bus and controller in a undesirable state. + +At the end of the last transmitted byte, the existing driver would just +signal for a STOP condition to be transmitted then immediately signal +completion. However, the full STOP procedure might not have fully taken +place by the time the runtime PM shuts off the peripheral clock, leaving +the bus in a suspended state. + +Alternatively, the STOP condition on the bus may have completed, but when +the next transaction is requested by the upper layer, not all the +necessary register cleanup was finished from the last transfer which made +the driver return BUS BUSY when it really wasn't. + +This patch now makes all transmit and receive transactions wait for the +STOP condition to fully complete before signaling a completed transaction. +With this new method, runtime PM no longer seems to be an issue. + +Fixes: 310c18a41450 ("i2c: riic: add driver") +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Wolfram Sang <wsa@the-dreams.de> +(cherry picked from commit 71ccea095ea1d4efd004dab971be6d599e06fc3f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/i2c/busses/i2c-riic.c | 30 +++++++++++++++++++++++------- + 1 file changed, 23 insertions(+), 7 deletions(-) + +--- a/drivers/i2c/busses/i2c-riic.c ++++ b/drivers/i2c/busses/i2c-riic.c +@@ -80,6 +80,7 @@ + #define ICIER_TEIE 0x40 + #define ICIER_RIE 0x20 + #define ICIER_NAKIE 0x10 ++#define ICIER_SPIE 0x08 + + #define ICSR2_NACKF 0x10 + +@@ -216,11 +217,10 @@ static irqreturn_t riic_tend_isr(int irq + return IRQ_NONE; + } + +- if (riic->is_last || riic->err) ++ if (riic->is_last || riic->err) { ++ riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER); + writeb(ICCR2_SP, riic->base + RIIC_ICCR2); +- +- writeb(0, riic->base + RIIC_ICIER); +- complete(&riic->msg_done); ++ } + + return IRQ_HANDLED; + } +@@ -240,13 +240,13 @@ static irqreturn_t riic_rdrf_isr(int irq + + if (riic->bytes_left == 1) { + /* STOP must come before we set ACKBT! */ +- if (riic->is_last) ++ if (riic->is_last) { ++ riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER); + writeb(ICCR2_SP, riic->base + RIIC_ICCR2); ++ } + + riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3); + +- writeb(0, riic->base + RIIC_ICIER); +- complete(&riic->msg_done); + } else { + riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3); + } +@@ -259,6 +259,21 @@ static irqreturn_t riic_rdrf_isr(int irq + return IRQ_HANDLED; + } + ++static irqreturn_t riic_stop_isr(int irq, void *data) ++{ ++ struct riic_dev *riic = data; ++ ++ /* read back registers to confirm writes have fully propagated */ ++ writeb(0, riic->base + RIIC_ICSR2); ++ readb(riic->base + RIIC_ICSR2); ++ writeb(0, riic->base + RIIC_ICIER); ++ readb(riic->base + RIIC_ICIER); ++ ++ complete(&riic->msg_done); ++ ++ return IRQ_HANDLED; ++} ++ + static u32 riic_func(struct i2c_adapter *adap) + { + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +@@ -326,6 +341,7 @@ static struct riic_irq_desc riic_irqs[] + { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" }, + { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" }, + { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" }, ++ { .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" }, + { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" }, + }; + diff --git a/patches.renesas/0053-i2c-riic-fix-restart-condition.patch b/patches.renesas/0053-i2c-riic-fix-restart-condition.patch new file mode 100644 index 0000000000000..815f1273b9a3f --- /dev/null +++ b/patches.renesas/0053-i2c-riic-fix-restart-condition.patch @@ -0,0 +1,37 @@ +From ef8bf60b6afb42f0eccfa6b175fb5fda5f1a98ad Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Mon, 6 Mar 2017 15:20:51 -0500 +Subject: [PATCH 053/255] i2c: riic: fix restart condition + +While modifying the driver to use the STOP interrupt, the completion of the +intermediate transfers need to wake the driver back up in order to initiate +the next transfer (restart condition). Otherwise you get never ending +interrupts and only the first transfer sent. + +Fixes: 71ccea095ea1 ("i2c: riic: correctly finish transfers") +Reported-by: Simon Horman <horms@verge.net.au> +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Tested-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Wolfram Sang <wsa@the-dreams.de> +(cherry picked from commit 2501c1bb054290679baad0ff7f4f07c714251f4c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/i2c/busses/i2c-riic.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/i2c/busses/i2c-riic.c ++++ b/drivers/i2c/busses/i2c-riic.c +@@ -218,8 +218,12 @@ static irqreturn_t riic_tend_isr(int irq + } + + if (riic->is_last || riic->err) { +- riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER); ++ riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER); + writeb(ICCR2_SP, riic->base + RIIC_ICCR2); ++ } else { ++ /* Transfer is complete, but do not send STOP */ ++ riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER); ++ complete(&riic->msg_done); + } + + return IRQ_HANDLED; diff --git a/patches.renesas/0054-i2c-sh_mobile-document-support-for-r8a7796-R-Car-M3-.patch b/patches.renesas/0054-i2c-sh_mobile-document-support-for-r8a7796-R-Car-M3-.patch new file mode 100644 index 0000000000000..dc508463530ea --- /dev/null +++ b/patches.renesas/0054-i2c-sh_mobile-document-support-for-r8a7796-R-Car-M3-.patch @@ -0,0 +1,29 @@ +From 7b139ce366cdc76448413de02369ef6092bea74d Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 26 Jan 2017 09:47:31 +0100 +Subject: [PATCH 054/255] i2c: sh_mobile: document support for r8a7796 (R-Car + M3-W) + +Explicitly list per-SoC binding for r8a7796. No driver change +is required as the initialisation sequence is currently the same +as for the R-Car Gen3 fallback binding. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Wolfram Sang <wsa@the-dreams.de> +(cherry picked from commit 45345e9a85f94f2f7f563cd9b881a19e5d99c72c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt | 1 + + 1 file changed, 1 insertion(+) + +--- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt ++++ b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt +@@ -10,6 +10,7 @@ Required properties: + - "renesas,iic-r8a7793" (R-Car M2-N) + - "renesas,iic-r8a7794" (R-Car E2) + - "renesas,iic-r8a7795" (R-Car H3) ++ - "renesas,iic-r8a7796" (R-Car M3-W) + - "renesas,iic-sh73a0" (SH-Mobile AG5) + - "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device) + - "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device) diff --git a/patches.renesas/0055-iommu-ipmmu-vmsa-Restrict-IOMMU-Domain-Geometry-to-3.patch b/patches.renesas/0055-iommu-ipmmu-vmsa-Restrict-IOMMU-Domain-Geometry-to-3.patch new file mode 100644 index 0000000000000..c329969845a5e --- /dev/null +++ b/patches.renesas/0055-iommu-ipmmu-vmsa-Restrict-IOMMU-Domain-Geometry-to-3.patch @@ -0,0 +1,38 @@ +From bec3c77b8b85620bdcf4c1ad26de51fa2e4fc1c4 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 31 Jan 2017 12:17:07 +0100 +Subject: [PATCH 055/255] iommu/ipmmu-vmsa: Restrict IOMMU Domain Geometry to + 32-bit address space + +Currently, the IPMMU/VMSA driver supports 32-bit I/O Virtual Addresses +only, and thus sets io_pgtable_cfg.ias = 32. However, it doesn't force +a 32-bit IOVA space through the IOMMU Domain Geometry. + +Hence if a device (e.g. SYS-DMAC) rightfully configures a 40-bit DMA +mask, it will still be handed out a 40-bit IOVA, outside the 32-bit IOVA +space, leading to out-of-bounds accesses of the PGD when mapping the +IOVA. + +Force a 32-bit IOMMU Domain Geometry to fix this. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Robin Murphy <robin.murphy@arm.com> +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Joerg Roedel <jroedel@suse.de> +(cherry picked from commit 3b6bb5b705a4051c9899f5e3100c117c261d2742) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/iommu/ipmmu-vmsa.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/iommu/ipmmu-vmsa.c ++++ b/drivers/iommu/ipmmu-vmsa.c +@@ -313,6 +313,8 @@ static int ipmmu_domain_init_context(str + domain->cfg.ias = 32; + domain->cfg.oas = 40; + domain->cfg.tlb = &ipmmu_gather_ops; ++ domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); ++ domain->io_domain.geometry.force_aperture = true; + /* + * TODO: Add support for coherent walk through CCI with DVM and remove + * cache handling. For now, delegate it to the io-pgtable code. diff --git a/patches.renesas/0056-mtd-m25p80-consider-max-message-size-in-m25p80_read.patch b/patches.renesas/0056-mtd-m25p80-consider-max-message-size-in-m25p80_read.patch new file mode 100644 index 0000000000000..249ce85e6fdd1 --- /dev/null +++ b/patches.renesas/0056-mtd-m25p80-consider-max-message-size-in-m25p80_read.patch @@ -0,0 +1,31 @@ +From d3f0852f138f74a6c4a827ff1b13c95019dd3b88 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit <hkallweit1@gmail.com> +Date: Fri, 28 Oct 2016 07:58:46 +0200 +Subject: [PATCH 056/255] mtd: m25p80: consider max message size in m25p80_read + +Consider a message size limit when calculating the maximum amount +of data that can be read. + +The message size limit has been introduced with 4.9, so cc it +to stable. + +Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> +Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> +(cherry picked from commit 9e276de6a367cde07c1a63522152985d4e5cca8b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mtd/devices/m25p80.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -172,7 +172,8 @@ static ssize_t m25p80_read(struct spi_no + + t[1].rx_buf = buf; + t[1].rx_nbits = m25p80_rx_nbits(nor); +- t[1].len = min(len, spi_max_transfer_size(spi)); ++ t[1].len = min3(len, spi_max_transfer_size(spi), ++ spi_max_message_size(spi) - t[0].len); + spi_message_add_tail(&t[1], &m); + + ret = spi_sync(spi, &m); diff --git a/patches.renesas/0057-mtd-spi-nor-add-dt-support-for-Everspin-MRAMs.patch b/patches.renesas/0057-mtd-spi-nor-add-dt-support-for-Everspin-MRAMs.patch new file mode 100644 index 0000000000000..049b5c702d7d8 --- /dev/null +++ b/patches.renesas/0057-mtd-spi-nor-add-dt-support-for-Everspin-MRAMs.patch @@ -0,0 +1,60 @@ +From eab36c1c55544ea9ec35563a0874df5053952d9f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de> +Date: Tue, 17 Jan 2017 12:03:38 +0100 +Subject: [PATCH 057/255] mtd: spi-nor: add dt support for Everspin MRAMs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MR25 family doesn't support JEDEC, so they need explicit mentioning +in the list of supported spi IDs. This makes it possible to add these +using for example: + + compatible = "everspin,mr25h40"; + +There was already an entry for mr25h256. Move that one out of the "keep +for compatibility" section and put in a new group for Everspin MRAMs. + +Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> +Acked-by: Rob Herring <robh@kernel.org> +Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> +(cherry picked from commit 3a08e933415c58689797c5bdc825e78a808fffe1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 ++ + drivers/mtd/devices/m25p80.c | 6 +++++- + 2 files changed, 7 insertions(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt ++++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt +@@ -14,6 +14,8 @@ Required properties: + at25df641 + at26df081a + mr25h256 ++ mr25h10 ++ mr25h40 + mx25l4005a + mx25l1606e + mx25l6405d +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -289,7 +289,6 @@ static const struct spi_device_id m25p_i + * should be kept for backward compatibility. + */ + {"at25df321a"}, {"at25df641"}, {"at26df081a"}, +- {"mr25h256"}, + {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"}, + {"mx25l25635e"},{"mx66l51235l"}, + {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"}, +@@ -306,6 +305,11 @@ static const struct spi_device_id m25p_i + {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"}, + {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"}, + ++ /* Everspin MRAMs (non-JEDEC) */ ++ { "mr25h256" }, /* 256 Kib, 40 MHz */ ++ { "mr25h10" }, /* 1 Mib, 40 MHz */ ++ { "mr25h40" }, /* 4 Mib, 40 MHz */ ++ + { }, + }; + MODULE_DEVICE_TABLE(spi, m25p_ids); diff --git a/patches.renesas/0058-ARM-shmobile-defconfig-Enable-CONFIG_VIDEO_ADV7604.patch b/patches.renesas/0058-ARM-shmobile-defconfig-Enable-CONFIG_VIDEO_ADV7604.patch new file mode 100644 index 0000000000000..a03966329c634 --- /dev/null +++ b/patches.renesas/0058-ARM-shmobile-defconfig-Enable-CONFIG_VIDEO_ADV7604.patch @@ -0,0 +1,30 @@ +From 6cd751ed6ed4d28468b6c5895316b1ca5347f31d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Fri, 18 Nov 2016 16:00:44 +0100 +Subject: [PATCH 058/255] ARM: shmobile: defconfig: Enable CONFIG_VIDEO_ADV7604 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The adv7612 is used on Gen2 boards (Lager, Koelsch and Gose) for HDMI +input. Enable support for this chip in shmobile_defconfig. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1682a9c5694d228041dc7ff59f49427c83920675) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/shmobile_defconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/configs/shmobile_defconfig ++++ b/arch/arm/configs/shmobile_defconfig +@@ -145,6 +145,7 @@ CONFIG_VIDEO_RENESAS_JPU=y + CONFIG_VIDEO_RENESAS_VSP1=y + # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set + CONFIG_VIDEO_ADV7180=y ++CONFIG_VIDEO_ADV7604=y + CONFIG_VIDEO_ML86V7667=y + CONFIG_DRM=y + CONFIG_DRM_I2C_ADV7511=y diff --git a/patches.renesas/0059-ARM-shmobile-defconfig-Enable-CMA-for-DMA.patch b/patches.renesas/0059-ARM-shmobile-defconfig-Enable-CMA-for-DMA.patch new file mode 100644 index 0000000000000..e57e218a71a99 --- /dev/null +++ b/patches.renesas/0059-ARM-shmobile-defconfig-Enable-CMA-for-DMA.patch @@ -0,0 +1,45 @@ +From eee448302c913f7680046b1dab0d366a6e0293b5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Fri, 18 Nov 2016 16:00:45 +0100 +Subject: [PATCH 059/255] ARM: shmobile: defconfig: Enable CMA for DMA +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +To be able to use VIN with larger frame sizes CMA memory are needed for +DMA. If this is not enabled trying to capture large frames can result in +errors such as: + +rcar-vin e6ef0000.video: dma_alloc_coherent of size 8388608 failed + +A CMA area of 64MB are needed for v4l2-compliance to pass on all formats +on the largest possible frame size of 2048x2048. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 77af670a7698bbc4dc9fd8bbd553b33bfb16b68a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/shmobile_defconfig | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/arm/configs/shmobile_defconfig ++++ b/arch/arm/configs/shmobile_defconfig +@@ -33,6 +33,7 @@ CONFIG_HAVE_ARM_ARCH_TIMER=y + CONFIG_NR_CPUS=8 + CONFIG_AEABI=y + CONFIG_HIGHMEM=y ++CONFIG_CMA=y + CONFIG_ZBOOT_ROM_TEXT=0x0 + CONFIG_ZBOOT_ROM_BSS=0x0 + CONFIG_ARM_APPENDED_DTB=y +@@ -58,6 +59,8 @@ CONFIG_CAN_RCAR=y + CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" + CONFIG_DEVTMPFS=y + CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_DMA_CMA=y ++CONFIG_CMA_SIZE_MBYTES=64 + CONFIG_SIMPLE_PM_BUS=y + CONFIG_MTD=y + CONFIG_MTD_BLOCK=y diff --git a/patches.renesas/0060-ARM-shmobile-defconfig-Enable-r8a774-35-SoCs.patch b/patches.renesas/0060-ARM-shmobile-defconfig-Enable-r8a774-35-SoCs.patch new file mode 100644 index 0000000000000..729cbffec47da --- /dev/null +++ b/patches.renesas/0060-ARM-shmobile-defconfig-Enable-r8a774-35-SoCs.patch @@ -0,0 +1,26 @@ +From 13c8dff451612fc093654a9e638e7535e6a4e3f0 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 6 Dec 2016 14:32:52 +0100 +Subject: [PATCH 060/255] ARM: shmobile: defconfig: Enable r8a774[35] SoCs + +Enable recently added r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit d234e29dae04b224a63e39bc29938fa77819b3f1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/configs/shmobile_defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm/configs/shmobile_defconfig ++++ b/arch/arm/configs/shmobile_defconfig +@@ -14,6 +14,8 @@ CONFIG_ARCH_EMEV2=y + CONFIG_ARCH_R7S72100=y + CONFIG_ARCH_R8A73A4=y + CONFIG_ARCH_R8A7740=y ++CONFIG_ARCH_R8A7743=y ++CONFIG_ARCH_R8A7745=y + CONFIG_ARCH_R8A7778=y + CONFIG_ARCH_R8A7779=y + CONFIG_ARCH_R8A7790=y diff --git a/patches.renesas/0061-ARM-dts-r8a7743-Move-RST-node-before-SYSC-node.patch b/patches.renesas/0061-ARM-dts-r8a7743-Move-RST-node-before-SYSC-node.patch new file mode 100644 index 0000000000000..4ed6e5b7d7574 --- /dev/null +++ b/patches.renesas/0061-ARM-dts-r8a7743-Move-RST-node-before-SYSC-node.patch @@ -0,0 +1,41 @@ +From 115ebe196a2fb3190fbdbf0eef1481a36dfcda78 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 18 Nov 2016 11:24:22 +0100 +Subject: [PATCH 061/255] ARM: dts: r8a7743: Move RST node before SYSC node + +To preserve both alphabetical (label) and numerical ordering (unit +address). + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a97f1dfb7f6eec1998d51e7335e265be5c6314a1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7743.dtsi | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/r8a7743.dtsi ++++ b/arch/arm/boot/dts/r8a7743.dtsi +@@ -102,17 +102,17 @@ + #power-domain-cells = <0>; + }; + ++ rst: reset-controller@e6160000 { ++ compatible = "renesas,r8a7743-rst"; ++ reg = <0 0xe6160000 0 0x100>; ++ }; ++ + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7743-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7743-rst"; +- reg = <0 0xe6160000 0 0x100>; +- }; +- + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; diff --git a/patches.renesas/0062-ARM-dts-r8a7745-Move-RST-node-before-SYSC-node.patch b/patches.renesas/0062-ARM-dts-r8a7745-Move-RST-node-before-SYSC-node.patch new file mode 100644 index 0000000000000..baa9c3476875c --- /dev/null +++ b/patches.renesas/0062-ARM-dts-r8a7745-Move-RST-node-before-SYSC-node.patch @@ -0,0 +1,41 @@ +From 8446ed915e5738e91c35aa82802e2e0f31ddc4f1 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 18 Nov 2016 11:24:23 +0100 +Subject: [PATCH 062/255] ARM: dts: r8a7745: Move RST node before SYSC node + +To preserve both alphabetical (label) and numerical ordering (unit +address). + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 13ae6ac495846b54ad47d71075bbaf9d8224d356) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7745.dtsi | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/r8a7745.dtsi ++++ b/arch/arm/boot/dts/r8a7745.dtsi +@@ -102,17 +102,17 @@ + #power-domain-cells = <0>; + }; + ++ rst: reset-controller@e6160000 { ++ compatible = "renesas,r8a7745-rst"; ++ reg = <0 0xe6160000 0 0x100>; ++ }; ++ + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7745-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + +- rst: reset-controller@e6160000 { +- compatible = "renesas,r8a7745-rst"; +- reg = <0 0xe6160000 0 0x100>; +- }; +- + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; diff --git a/patches.renesas/0063-ARM-dts-r8a7743-Add-device-node-for-PRR.patch b/patches.renesas/0063-ARM-dts-r8a7743-Add-device-node-for-PRR.patch new file mode 100644 index 0000000000000..355f08a9c80c7 --- /dev/null +++ b/patches.renesas/0063-ARM-dts-r8a7743-Add-device-node-for-PRR.patch @@ -0,0 +1,30 @@ +From 0d862b3d90f8a1f0d4f5401dae495cd9f87333a8 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 18 Nov 2016 11:37:42 +0100 +Subject: [PATCH 063/255] ARM: dts: r8a7743: Add device node for PRR + +Add a device node for the Product Register, which provides SoC product +and revision information. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 11d4407e939e74e89a29df88b1557b59ece9e9f9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7743.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm/boot/dts/r8a7743.dtsi ++++ b/arch/arm/boot/dts/r8a7743.dtsi +@@ -102,6 +102,11 @@ + #power-domain-cells = <0>; + }; + ++ prr: chipid@ff000044 { ++ compatible = "renesas,prr"; ++ reg = <0 0xff000044 0 4>; ++ }; ++ + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7743-rst"; + reg = <0 0xe6160000 0 0x100>; diff --git a/patches.renesas/0064-ARM-dts-r8a7745-Add-device-node-for-PRR.patch b/patches.renesas/0064-ARM-dts-r8a7745-Add-device-node-for-PRR.patch new file mode 100644 index 0000000000000..f6aa8e66c402b --- /dev/null +++ b/patches.renesas/0064-ARM-dts-r8a7745-Add-device-node-for-PRR.patch @@ -0,0 +1,30 @@ +From 8924412081600c2b2a7f7b66e7ea2bb6072132df Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 18 Nov 2016 11:37:43 +0100 +Subject: [PATCH 064/255] ARM: dts: r8a7745: Add device node for PRR + +Add a device node for the Product Register, which provides SoC product +and revision information. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8916c7b58319fa27eae25c0c9b9a4cd68b9b30bd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7745.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm/boot/dts/r8a7745.dtsi ++++ b/arch/arm/boot/dts/r8a7745.dtsi +@@ -102,6 +102,11 @@ + #power-domain-cells = <0>; + }; + ++ prr: chipid@ff000044 { ++ compatible = "renesas,prr"; ++ reg = <0 0xff000044 0 4>; ++ }; ++ + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7745-rst"; + reg = <0 0xe6160000 0 0x100>; diff --git a/patches.renesas/0065-ARM-dts-r8a73a4-Use-SoC-specific-compat-string-for-m.patch b/patches.renesas/0065-ARM-dts-r8a73a4-Use-SoC-specific-compat-string-for-m.patch new file mode 100644 index 0000000000000..1a51d65ee00d1 --- /dev/null +++ b/patches.renesas/0065-ARM-dts-r8a73a4-Use-SoC-specific-compat-string-for-m.patch @@ -0,0 +1,38 @@ +From 47f8bc554c82685bd181cd6fbc636002ff7eff8d Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 24 Nov 2016 21:15:12 +0100 +Subject: [PATCH 065/255] ARM: dts: r8a73a4: Use SoC-specific compat string for + mmcif + +Use the SoC-specific compat string for mmcif in DT for the r8a73a4 SoC. +This is in keeping with the use of compat strings for mmcif for other +Renesas ARM based SoCs. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 5b0161743e194ab558143fdeea03243e35a5297f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a73a4.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/r8a73a4.dtsi ++++ b/arch/arm/boot/dts/r8a73a4.dtsi +@@ -440,7 +440,7 @@ + }; + + mmcif0: mmc@ee200000 { +- compatible = "renesas,sh-mmcif"; ++ compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; +@@ -450,7 +450,7 @@ + }; + + mmcif1: mmc@ee220000 { +- compatible = "renesas,sh-mmcif"; ++ compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; + reg = <0 0xee220000 0 0x80>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; diff --git a/patches.renesas/0066-ARM-dts-r8a7778-Use-SoC-specific-compat-string-for-m.patch b/patches.renesas/0066-ARM-dts-r8a7778-Use-SoC-specific-compat-string-for-m.patch new file mode 100644 index 0000000000000..c09dbcdaf5e1b --- /dev/null +++ b/patches.renesas/0066-ARM-dts-r8a7778-Use-SoC-specific-compat-string-for-m.patch @@ -0,0 +1,29 @@ +From 65977aaefd37386370c4318e5e25214e0329d4fb Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 24 Nov 2016 21:15:13 +0100 +Subject: [PATCH 066/255] ARM: dts: r8a7778: Use SoC-specific compat string for + mmcif + +Use the SoC-specific compat string for mmcif in DT for the r8a7778 SoC. +This is in keeping with the use of compat strings for mmcif for other +Renesas ARM based SoCs. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit f9be04fe05ee0a727471be10e1ec7c76d879b103) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7778.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/r8a7778.dtsi ++++ b/arch/arm/boot/dts/r8a7778.dtsi +@@ -369,7 +369,7 @@ + }; + + mmcif: mmc@ffe4e000 { +- compatible = "renesas,sh-mmcif"; ++ compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif"; + reg = <0xffe4e000 0x100>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_MMC>; diff --git a/patches.renesas/0067-ARM-dts-sh73a0-Use-SoC-specific-compat-string-for-mm.patch b/patches.renesas/0067-ARM-dts-sh73a0-Use-SoC-specific-compat-string-for-mm.patch new file mode 100644 index 0000000000000..c6bf4cc2a8495 --- /dev/null +++ b/patches.renesas/0067-ARM-dts-sh73a0-Use-SoC-specific-compat-string-for-mm.patch @@ -0,0 +1,29 @@ +From 135c8e10cdfdd5fbf3da163436931e6b91773ef0 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 24 Nov 2016 21:15:14 +0100 +Subject: [PATCH 067/255] ARM: dts: sh73a0: Use SoC-specific compat string for + mmcif + +Use the SoC-specific compat string for mmcif in DT for the sh73a0 SoC. +This is in keeping with the use of compat strings for mmcif for other +Renesas ARM based SoCs. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 5ff43b37ce967ffbcc4a93c76a9b270e441a72e6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/sh73a0.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/sh73a0.dtsi ++++ b/arch/arm/boot/dts/sh73a0.dtsi +@@ -263,7 +263,7 @@ + }; + + mmcif: mmc@e6bd0000 { +- compatible = "renesas,sh-mmcif"; ++ compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif"; + reg = <0xe6bd0000 0x100>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; diff --git a/patches.renesas/0068-ARM-dts-gose-Add-da9063-PMIC-device-node-for-system-.patch b/patches.renesas/0068-ARM-dts-gose-Add-da9063-PMIC-device-node-for-system-.patch new file mode 100644 index 0000000000000..01dbab2e3aa1f --- /dev/null +++ b/patches.renesas/0068-ARM-dts-gose-Add-da9063-PMIC-device-node-for-system-.patch @@ -0,0 +1,50 @@ +From 1685f251c8cc5a2cdac88cd67214e380b814fdf6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 17 Nov 2016 19:37:46 +0100 +Subject: [PATCH 068/255] ARM: dts: gose: Add da9063 PMIC device node for + system restart + +Enable i2c6, and add a device node for the da9063 PMIC, with subnodes +for rtc and wdt. Regulator support is not yet included. + +This allows the system to be restarted when the watchdog timer times +out, or when a system restart is requested. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c20839a36132462496f939b0d13afee009c9a547) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7793-gose.dts | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/arch/arm/boot/dts/r8a7793-gose.dts ++++ b/arch/arm/boot/dts/r8a7793-gose.dts +@@ -538,6 +538,27 @@ + }; + }; + ++&i2c6 { ++ status = "okay"; ++ clock-frequency = <100000>; ++ ++ pmic@58 { ++ compatible = "dlg,da9063"; ++ reg = <0x58>; ++ interrupt-parent = <&irqc0>; ++ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-controller; ++ ++ rtc { ++ compatible = "dlg,da9063-rtc"; ++ }; ++ ++ wdt { ++ compatible = "dlg,da9063-watchdog"; ++ }; ++ }; ++}; ++ + &rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; diff --git a/patches.renesas/0069-ARM-dts-r8a7790-Use-renesas-rcar-gen2-usb-phy-fallba.patch b/patches.renesas/0069-ARM-dts-r8a7790-Use-renesas-rcar-gen2-usb-phy-fallba.patch new file mode 100644 index 0000000000000..a4b8ed625f2ea --- /dev/null +++ b/patches.renesas/0069-ARM-dts-r8a7790-Use-renesas-rcar-gen2-usb-phy-fallba.patch @@ -0,0 +1,30 @@ +From f2e8cd66a962e329b9a7ffcef7d2ff8baf7d2519 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 1 Dec 2016 15:25:51 +0100 +Subject: [PATCH 069/255] ARM: dts: r8a7790: Use renesas,rcar-gen2-usb-phy + fallback binding + +A fallback binding for the Renesas R-Car Gen2 PHY driver was +added by commit 7777cb8ba08d ("phy: rcar-gen2: add fallback binding"). +This patch makes use of this binding in the DT for the r8a7790 SoC. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 3b0922c55e17b11e41f27c7730804623414bcf19) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -883,7 +883,8 @@ + }; + + usbphy: usb-phy@e6590100 { +- compatible = "renesas,usb-phy-r8a7790"; ++ compatible = "renesas,usb-phy-r8a7790", ++ "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; diff --git a/patches.renesas/0070-ARM-dts-r8a7791-Use-renesas-rcar-gen2-usb-phy-fallba.patch b/patches.renesas/0070-ARM-dts-r8a7791-Use-renesas-rcar-gen2-usb-phy-fallba.patch new file mode 100644 index 0000000000000..6d1664b6e803a --- /dev/null +++ b/patches.renesas/0070-ARM-dts-r8a7791-Use-renesas-rcar-gen2-usb-phy-fallba.patch @@ -0,0 +1,30 @@ +From 52c83511724fb7ca5f78b6b4a33b096b31b92995 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 1 Dec 2016 15:25:52 +0100 +Subject: [PATCH 070/255] ARM: dts: r8a7791: Use renesas,rcar-gen2-usb-phy + fallback binding + +A fallback binding for the Renesas R-Car Gen2 PHY driver was +added by commit 7777cb8ba08d ("phy: rcar-gen2: add fallback binding"). +This patch makes use of this binding in the DT for the r8a7791 SoC. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit c39a6e76db7e1bc87b95f3dae7f7e4405f2854eb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -934,7 +934,8 @@ + }; + + usbphy: usb-phy@e6590100 { +- compatible = "renesas,usb-phy-r8a7791"; ++ compatible = "renesas,usb-phy-r8a7791", ++ "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; diff --git a/patches.renesas/0071-ARM-dts-r8a7794-Use-renesas-rcar-gen2-usb-phy-fallba.patch b/patches.renesas/0071-ARM-dts-r8a7794-Use-renesas-rcar-gen2-usb-phy-fallba.patch new file mode 100644 index 0000000000000..e14890f42f343 --- /dev/null +++ b/patches.renesas/0071-ARM-dts-r8a7794-Use-renesas-rcar-gen2-usb-phy-fallba.patch @@ -0,0 +1,30 @@ +From 33faecaa607a7e925bc79f766943c46dbcfc25f1 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 1 Dec 2016 15:25:53 +0100 +Subject: [PATCH 071/255] ARM: dts: r8a7794: Use renesas,rcar-gen2-usb-phy + fallback binding + +A fallback binding for the Renesas R-Car Gen2 PHY driver was +added by commit 7777cb8ba08d ("phy: rcar-gen2: add fallback binding"). +This patch makes use of this binding in the DT for the r8a7794 SoC. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit f81c163b38bedd95c75ab45929d190106166db11) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794.dtsi | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -878,7 +878,8 @@ + }; + + usbphy: usb-phy@e6590100 { +- compatible = "renesas,usb-phy-r8a7794"; ++ compatible = "renesas,usb-phy-r8a7794", ++ "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; diff --git a/patches.renesas/0072-ARM-dts-r8a7779-Use-R-Car-Gen-1-fallback-binding-for.patch b/patches.renesas/0072-ARM-dts-r8a7779-Use-R-Car-Gen-1-fallback-binding-for.patch new file mode 100644 index 0000000000000..26c976677a2bf --- /dev/null +++ b/patches.renesas/0072-ARM-dts-r8a7779-Use-R-Car-Gen-1-fallback-binding-for.patch @@ -0,0 +1,59 @@ +From a931783d4a59abbe0fb496a6fbf0567bfb0a5929 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:47 +0100 +Subject: [PATCH 072/255] ARM: dts: r8a7779: Use R-Car Gen 1 fallback binding + for i2c nodes + +Use recently added R-Car Gen 1 fallback binding for i2c nodes in +DT for r8a7779 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7779 and the +fallback binding for R-Car Gen 1. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 137d27f10f638781d5487b44302c2a2ee5d12655) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7779.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/r8a7779.dtsi ++++ b/arch/arm/boot/dts/r8a7779.dtsi +@@ -173,7 +173,7 @@ + i2c0: i2c@ffc70000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7779"; ++ compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; + reg = <0xffc70000 0x1000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_I2C0>; +@@ -184,7 +184,7 @@ + i2c1: i2c@ffc71000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7779"; ++ compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; + reg = <0xffc71000 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_I2C1>; +@@ -195,7 +195,7 @@ + i2c2: i2c@ffc72000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7779"; ++ compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; + reg = <0xffc72000 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_I2C2>; +@@ -206,7 +206,7 @@ + i2c3: i2c@ffc73000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7779"; ++ compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; + reg = <0xffc73000 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_I2C3>; diff --git a/patches.renesas/0073-ARM-dts-r8a7778-Use-R-Car-Gen-1-fallback-binding-for.patch b/patches.renesas/0073-ARM-dts-r8a7778-Use-R-Car-Gen-1-fallback-binding-for.patch new file mode 100644 index 0000000000000..6998f638337e8 --- /dev/null +++ b/patches.renesas/0073-ARM-dts-r8a7778-Use-R-Car-Gen-1-fallback-binding-for.patch @@ -0,0 +1,59 @@ +From 803407c62b489dbb1996ffb4a6fb7e5dff601ecd Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:48 +0100 +Subject: [PATCH 073/255] ARM: dts: r8a7778: Use R-Car Gen 1 fallback binding + for i2c nodes + +Use recently added R-Car Gen 1 fallback binding for i2c nodes in +DT for r8a7778 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7778 and the +fallback binding for R-Car Gen 1. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit eb6f2adfa5ad2b3494d9c751b1e1a21356ad7b62) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7778.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/r8a7778.dtsi ++++ b/arch/arm/boot/dts/r8a7778.dtsi +@@ -150,7 +150,7 @@ + i2c0: i2c@ffc70000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7778"; ++ compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; + reg = <0xffc70000 0x1000>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C0>; +@@ -161,7 +161,7 @@ + i2c1: i2c@ffc71000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7778"; ++ compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; + reg = <0xffc71000 0x1000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C1>; +@@ -172,7 +172,7 @@ + i2c2: i2c@ffc72000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7778"; ++ compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; + reg = <0xffc72000 0x1000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C2>; +@@ -183,7 +183,7 @@ + i2c3: i2c@ffc73000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7778"; ++ compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; + reg = <0xffc73000 0x1000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C3>; diff --git a/patches.renesas/0074-ARM-dts-r8a7790-Use-R-Car-Gen-2-fallback-binding-for.patch b/patches.renesas/0074-ARM-dts-r8a7790-Use-R-Car-Gen-2-fallback-binding-for.patch new file mode 100644 index 0000000000000..ecc983484cc96 --- /dev/null +++ b/patches.renesas/0074-ARM-dts-r8a7790-Use-R-Car-Gen-2-fallback-binding-for.patch @@ -0,0 +1,59 @@ +From 650538a206476c41f6dba7ead1395399153a25d5 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:49 +0100 +Subject: [PATCH 074/255] ARM: dts: r8a7790: Use R-Car Gen 2 fallback binding + for i2c nodes + +Use recently added R-Car Gen 2 fallback binding for i2c nodes in +DT for r8a7790 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7790 and the +fallback binding for R-Car Gen 2. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 82f8bfbef9864f6165b7741e251bf74827079604) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -480,7 +480,7 @@ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7790"; ++ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_I2C0>; +@@ -492,7 +492,7 @@ + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7790"; ++ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_I2C1>; +@@ -504,7 +504,7 @@ + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7790"; ++ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_I2C2>; +@@ -516,7 +516,7 @@ + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7790"; ++ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_I2C3>; diff --git a/patches.renesas/0075-ARM-dts-r8a7791-Use-R-Car-Gen-2-fallback-binding-for.patch b/patches.renesas/0075-ARM-dts-r8a7791-Use-R-Car-Gen-2-fallback-binding-for.patch new file mode 100644 index 0000000000000..0e1a6293531c1 --- /dev/null +++ b/patches.renesas/0075-ARM-dts-r8a7791-Use-R-Car-Gen-2-fallback-binding-for.patch @@ -0,0 +1,77 @@ +From cc8c1076576fbdfe87a8c25a94ee0ae99bf8e5b5 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:50 +0100 +Subject: [PATCH 075/255] ARM: dts: r8a7791: Use R-Car Gen 2 fallback binding + for i2c nodes + +Use recently added R-Car Gen 2 fallback binding for i2c nodes in +DT for r8a7791 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7791 and the +fallback binding for R-Car Gen 2. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit c7407ca7ef61ff91cfa3c130de59061171102cf3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -444,7 +444,7 @@ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7791"; ++ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C0>; +@@ -456,7 +456,7 @@ + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7791"; ++ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C1>; +@@ -468,7 +468,7 @@ + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7791"; ++ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C2>; +@@ -480,7 +480,7 @@ + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7791"; ++ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C3>; +@@ -492,7 +492,7 @@ + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7791"; ++ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C4>; +@@ -505,7 +505,7 @@ + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7791"; ++ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C5>; diff --git a/patches.renesas/0076-ARM-dts-r8a7792-Use-R-Car-Gen-2-fallback-binding-for.patch b/patches.renesas/0076-ARM-dts-r8a7792-Use-R-Car-Gen-2-fallback-binding-for.patch new file mode 100644 index 0000000000000..cc7d3965219ea --- /dev/null +++ b/patches.renesas/0076-ARM-dts-r8a7792-Use-R-Car-Gen-2-fallback-binding-for.patch @@ -0,0 +1,83 @@ +From afe7b3495f783d870d1f3886f9ea744a3c31a724 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:51 +0100 +Subject: [PATCH 076/255] ARM: dts: r8a7792: Use R-Car Gen 2 fallback binding + for i2c nodes + +Use recently added R-Car Gen 2 fallback binding for i2c nodes in +DT for r8a7792 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7792 and the +fallback binding for R-Car Gen 2. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit cfcb93b33f35879cfe06add3859fd869e3d1c9e2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7792.dtsi | 18 ++++++++++++------ + 1 file changed, 12 insertions(+), 6 deletions(-) + +--- a/arch/arm/boot/dts/r8a7792.dtsi ++++ b/arch/arm/boot/dts/r8a7792.dtsi +@@ -498,7 +498,8 @@ + + /* I2C doesn't need pinmux */ + i2c0: i2c@e6508000 { +- compatible = "renesas,i2c-r8a7792"; ++ compatible = "renesas,i2c-r8a7792", ++ "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_I2C0>; +@@ -510,7 +511,8 @@ + }; + + i2c1: i2c@e6518000 { +- compatible = "renesas,i2c-r8a7792"; ++ compatible = "renesas,i2c-r8a7792", ++ "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_I2C1>; +@@ -522,7 +524,8 @@ + }; + + i2c2: i2c@e6530000 { +- compatible = "renesas,i2c-r8a7792"; ++ compatible = "renesas,i2c-r8a7792", ++ "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_I2C2>; +@@ -534,7 +537,8 @@ + }; + + i2c3: i2c@e6540000 { +- compatible = "renesas,i2c-r8a7792"; ++ compatible = "renesas,i2c-r8a7792", ++ "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_I2C3>; +@@ -546,7 +550,8 @@ + }; + + i2c4: i2c@e6520000 { +- compatible = "renesas,i2c-r8a7792"; ++ compatible = "renesas,i2c-r8a7792", ++ "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_I2C4>; +@@ -558,7 +563,8 @@ + }; + + i2c5: i2c@e6528000 { +- compatible = "renesas,i2c-r8a7792"; ++ compatible = "renesas,i2c-r8a7792", ++ "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_I2C5>; diff --git a/patches.renesas/0077-ARM-dts-r8a7793-Use-R-Car-Gen-2-fallback-binding-for.patch b/patches.renesas/0077-ARM-dts-r8a7793-Use-R-Car-Gen-2-fallback-binding-for.patch new file mode 100644 index 0000000000000..b9ce92d250d08 --- /dev/null +++ b/patches.renesas/0077-ARM-dts-r8a7793-Use-R-Car-Gen-2-fallback-binding-for.patch @@ -0,0 +1,77 @@ +From 68b934d17b17dbee5017d481ac702527d16d077c Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:52 +0100 +Subject: [PATCH 077/255] ARM: dts: r8a7793: Use R-Car Gen 2 fallback binding + for i2c nodes + +Use recently added R-Car Gen 2 fallback binding for i2c nodes in +DT for r8a7793 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7793 and the +fallback binding for R-Car Gen 2. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit b3bb35a862007712aa277bfa94bdf80be67772da) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7793.dtsi | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/arch/arm/boot/dts/r8a7793.dtsi ++++ b/arch/arm/boot/dts/r8a7793.dtsi +@@ -411,7 +411,7 @@ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7793"; ++ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7793_CLK_I2C0>; +@@ -423,7 +423,7 @@ + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7793"; ++ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7793_CLK_I2C1>; +@@ -435,7 +435,7 @@ + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7793"; ++ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7793_CLK_I2C2>; +@@ -447,7 +447,7 @@ + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7793"; ++ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7793_CLK_I2C3>; +@@ -459,7 +459,7 @@ + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7793"; ++ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7793_CLK_I2C4>; +@@ -472,7 +472,7 @@ + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,i2c-r8a7793"; ++ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7793_CLK_I2C5>; diff --git a/patches.renesas/0078-ARM-dts-r8a7794-Use-R-Car-Gen-2-fallback-binding-for.patch b/patches.renesas/0078-ARM-dts-r8a7794-Use-R-Car-Gen-2-fallback-binding-for.patch new file mode 100644 index 0000000000000..1b2e1bfaeb7bf --- /dev/null +++ b/patches.renesas/0078-ARM-dts-r8a7794-Use-R-Car-Gen-2-fallback-binding-for.patch @@ -0,0 +1,77 @@ +From 6095913292c0adc173fcd6ae48ae433a8835ab9a Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:53 +0100 +Subject: [PATCH 078/255] ARM: dts: r8a7794: Use R-Car Gen 2 fallback binding + for i2c nodes + +Use recently added R-Car Gen 2 fallback binding for i2c nodes in +DT for r8a7794 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7794 and the +fallback binding for R-Car Gen 2. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 5e6173897c03f13366edefca98dd4712d3ddb0d4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794.dtsi | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -611,7 +611,7 @@ + + /* The memory map in the User's Manual maps the cores to bus numbers */ + i2c0: i2c@e6508000 { +- compatible = "renesas,i2c-r8a7794"; ++ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_I2C0>; +@@ -623,7 +623,7 @@ + }; + + i2c1: i2c@e6518000 { +- compatible = "renesas,i2c-r8a7794"; ++ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_I2C1>; +@@ -635,7 +635,7 @@ + }; + + i2c2: i2c@e6530000 { +- compatible = "renesas,i2c-r8a7794"; ++ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_I2C2>; +@@ -647,7 +647,7 @@ + }; + + i2c3: i2c@e6540000 { +- compatible = "renesas,i2c-r8a7794"; ++ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_I2C3>; +@@ -659,7 +659,7 @@ + }; + + i2c4: i2c@e6520000 { +- compatible = "renesas,i2c-r8a7794"; ++ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_I2C4>; +@@ -671,7 +671,7 @@ + }; + + i2c5: i2c@e6528000 { +- compatible = "renesas,i2c-r8a7794"; ++ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_I2C5>; diff --git a/patches.renesas/0079-ARM-dts-r8a7790-Use-R-Car-Gen-2-fallback-binding-for.patch b/patches.renesas/0079-ARM-dts-r8a7790-Use-R-Car-Gen-2-fallback-binding-for.patch new file mode 100644 index 0000000000000..5a8edc562fc0e --- /dev/null +++ b/patches.renesas/0079-ARM-dts-r8a7790-Use-R-Car-Gen-2-fallback-binding-for.patch @@ -0,0 +1,63 @@ +From bdbf79deae2d18a3f0d2d02865630bc4bd9ce4e5 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:56 +0100 +Subject: [PATCH 079/255] ARM: dts: r8a7790: Use R-Car Gen 2 fallback binding + for iic nodes + +Use recently added R-Car Gen 2 fallback binding for iic nodes in +DT for r8a7790 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7790 and the +fallback binding for R-Car Gen 2. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit b8075eea36546f55aca0d645561b6713d9ae562e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -528,7 +528,8 @@ + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; ++ compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", ++ "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_IIC0>; +@@ -542,7 +543,8 @@ + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; ++ compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", ++ "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_IIC1>; +@@ -556,7 +558,8 @@ + iic2: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; ++ compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", ++ "renesas,rmobile-iic"; + reg = <0 0xe6520000 0 0x425>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_IIC2>; +@@ -570,7 +573,8 @@ + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; ++ compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", ++ "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; diff --git a/patches.renesas/0080-ARM-dts-r8a7791-Use-R-Car-Gen-2-fallback-binding-for.patch b/patches.renesas/0080-ARM-dts-r8a7791-Use-R-Car-Gen-2-fallback-binding-for.patch new file mode 100644 index 0000000000000..71b64c2e655f8 --- /dev/null +++ b/patches.renesas/0080-ARM-dts-r8a7791-Use-R-Car-Gen-2-fallback-binding-for.patch @@ -0,0 +1,54 @@ +From bf9e60c8e6a8363510e5e423a2cf99917cbe2a10 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:57 +0100 +Subject: [PATCH 080/255] ARM: dts: r8a7791: Use R-Car Gen 2 fallback binding + for iic nodes + +Use recently added R-Car Gen 2 fallback binding for iic nodes in +DT for r8a7791 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7791 and the +fallback binding for R-Car Gen 2. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8d76bf8a6a6b3201b309faa623842ba3ec426b7a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -518,7 +518,8 @@ + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; ++ compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic", ++ "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; +@@ -532,7 +533,8 @@ + i2c7: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; ++ compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic", ++ "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_IIC0>; +@@ -546,7 +548,8 @@ + i2c8: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; ++ compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic", ++ "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_IIC1>; diff --git a/patches.renesas/0081-ARM-dts-r8a7793-Use-R-Car-Gen-2-fallback-binding-for.patch b/patches.renesas/0081-ARM-dts-r8a7793-Use-R-Car-Gen-2-fallback-binding-for.patch new file mode 100644 index 0000000000000..2dabae41bb610 --- /dev/null +++ b/patches.renesas/0081-ARM-dts-r8a7793-Use-R-Car-Gen-2-fallback-binding-for.patch @@ -0,0 +1,53 @@ +From 1c7a5b193c3e302c7c6983ecc3289767b4a700c1 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:58 +0100 +Subject: [PATCH 081/255] ARM: dts: r8a7793: Use R-Car Gen 2 fallback binding + for iic nodes + +Use recently added R-Car Gen 2 fallback binding for iic nodes in +DT for r8a7793 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7793 and the +fallback binding for R-Car Gen 2. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 21b3f9862943acd6ec92ad02d36ffdfe353e6b66) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7793.dtsi | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/r8a7793.dtsi ++++ b/arch/arm/boot/dts/r8a7793.dtsi +@@ -485,7 +485,8 @@ + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic"; ++ compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic", ++ "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>; +@@ -499,7 +500,8 @@ + i2c7: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic"; ++ compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic", ++ "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7793_CLK_IIC0>; +@@ -513,7 +515,8 @@ + i2c8: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; +- compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic"; ++ compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic", ++ "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7793_CLK_IIC1>; diff --git a/patches.renesas/0082-ARM-dts-r8a7794-Use-R-Car-Gen-2-fallback-binding-for.patch b/patches.renesas/0082-ARM-dts-r8a7794-Use-R-Car-Gen-2-fallback-binding-for.patch new file mode 100644 index 0000000000000..5fd47efb9487f --- /dev/null +++ b/patches.renesas/0082-ARM-dts-r8a7794-Use-R-Car-Gen-2-fallback-binding-for.patch @@ -0,0 +1,43 @@ +From b9b3cff83ef6ecf62457f6601501d9df3364cfd8 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 13 Dec 2016 12:45:59 +0100 +Subject: [PATCH 082/255] ARM: dts: r8a7794: Use R-Car Gen 2 fallback binding + for iic nodes + +Use recently added R-Car Gen 2 fallback binding for iic nodes in +DT for r8a7794 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7794 and the +fallback binding for R-Car Gen 2. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 40a99dbb99b1a50c11b95578d7300e5756e7662f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794.dtsi | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -683,7 +683,8 @@ + }; + + i2c6: i2c@e6500000 { +- compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic"; ++ compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic", ++ "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_IIC0>; +@@ -697,7 +698,8 @@ + }; + + i2c7: i2c@e6510000 { +- compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic"; ++ compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic", ++ "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_IIC1>; diff --git a/patches.renesas/0083-ARM-dts-r8a7791-Use-R-Car-Gen-2-fallback-binding-for.patch b/patches.renesas/0083-ARM-dts-r8a7791-Use-R-Car-Gen-2-fallback-binding-for.patch new file mode 100644 index 0000000000000..0bf6874d8b226 --- /dev/null +++ b/patches.renesas/0083-ARM-dts-r8a7791-Use-R-Car-Gen-2-fallback-binding-for.patch @@ -0,0 +1,53 @@ +From a3d9cc012f16951b812aeb3d802cc7c8eb8e1768 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 20 Dec 2016 11:32:37 +0100 +Subject: [PATCH 083/255] ARM: dts: r8a7791: Use R-Car Gen 2 fallback binding + for msiof nodes + +Use recently added R-Car Gen 2 fallback binding for msiof nodes in +DT for r8a7791 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7791 and the +fallback binding for R-Car Gen 2. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit fdda1f9e23f17effe32fd349aefab665b58b8d64) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -1521,7 +1521,8 @@ + }; + + msiof0: spi@e6e20000 { +- compatible = "renesas,msiof-r8a7791"; ++ compatible = "renesas,msiof-r8a7791", ++ "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; +@@ -1535,7 +1536,8 @@ + }; + + msiof1: spi@e6e10000 { +- compatible = "renesas,msiof-r8a7791"; ++ compatible = "renesas,msiof-r8a7791", ++ "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; +@@ -1549,7 +1551,8 @@ + }; + + msiof2: spi@e6e00000 { +- compatible = "renesas,msiof-r8a7791"; ++ compatible = "renesas,msiof-r8a7791", ++ "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; diff --git a/patches.renesas/0084-ARM-dts-r8a7792-Use-R-Car-Gen-2-fallback-binding-for.patch b/patches.renesas/0084-ARM-dts-r8a7792-Use-R-Car-Gen-2-fallback-binding-for.patch new file mode 100644 index 0000000000000..39dfd86e12eb5 --- /dev/null +++ b/patches.renesas/0084-ARM-dts-r8a7792-Use-R-Car-Gen-2-fallback-binding-for.patch @@ -0,0 +1,43 @@ +From 868b7a493dd27ce1af87206b2d65fd5a9cfaba30 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 20 Dec 2016 11:32:38 +0100 +Subject: [PATCH 084/255] ARM: dts: r8a7792: Use R-Car Gen 2 fallback binding + for msiof nodes + +Use recently added R-Car Gen 2 fallback binding for msiof nodes in +DT for r8a7792 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7792 and the +fallback binding for R-Car Gen 2. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 50a15093c6f1bf5f89b9954075b27b52c0322beb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7792.dtsi | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/r8a7792.dtsi ++++ b/arch/arm/boot/dts/r8a7792.dtsi +@@ -591,7 +591,8 @@ + }; + + msiof0: spi@e6e20000 { +- compatible = "renesas,msiof-r8a7792"; ++ compatible = "renesas,msiof-r8a7792", ++ "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>; +@@ -605,7 +606,8 @@ + }; + + msiof1: spi@e6e10000 { +- compatible = "renesas,msiof-r8a7792"; ++ compatible = "renesas,msiof-r8a7792", ++ "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>; diff --git a/patches.renesas/0085-ARM-dts-r8a7790-Use-R-Car-Gen-2-fallback-binding-for.patch b/patches.renesas/0085-ARM-dts-r8a7790-Use-R-Car-Gen-2-fallback-binding-for.patch new file mode 100644 index 0000000000000..9827c0691ccd8 --- /dev/null +++ b/patches.renesas/0085-ARM-dts-r8a7790-Use-R-Car-Gen-2-fallback-binding-for.patch @@ -0,0 +1,63 @@ +From b19f7470e59ac387e29d62914dec3b3fac927ac8 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Tue, 20 Dec 2016 11:32:39 +0100 +Subject: [PATCH 085/255] ARM: dts: r8a7790: Use R-Car Gen 2 fallback binding + for msiof nodes + +Use recently added R-Car Gen 2 fallback binding for msiof nodes in +DT for r8a7790 SoC. + +This has no run-time effect for the current driver as the initialisation +sequence is the same for the SoC-specific binding for r8a7790 and the +fallback binding for R-Car Gen 2. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 654450baf2afba86cf328e1849ccac61ec4630af) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -1508,7 +1508,8 @@ + }; + + msiof0: spi@e6e20000 { +- compatible = "renesas,msiof-r8a7790"; ++ compatible = "renesas,msiof-r8a7790", ++ "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; +@@ -1522,7 +1523,8 @@ + }; + + msiof1: spi@e6e10000 { +- compatible = "renesas,msiof-r8a7790"; ++ compatible = "renesas,msiof-r8a7790", ++ "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; +@@ -1536,7 +1538,8 @@ + }; + + msiof2: spi@e6e00000 { +- compatible = "renesas,msiof-r8a7790"; ++ compatible = "renesas,msiof-r8a7790", ++ "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; +@@ -1550,7 +1553,8 @@ + }; + + msiof3: spi@e6c90000 { +- compatible = "renesas,msiof-r8a7790"; ++ compatible = "renesas,msiof-r8a7790", ++ "renesas,rcar-gen2-msiof"; + reg = <0 0xe6c90000 0 0x0064>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; diff --git a/patches.renesas/0086-ARM-shmobile-apmu-Add-more-register-documentation.patch b/patches.renesas/0086-ARM-shmobile-apmu-Add-more-register-documentation.patch new file mode 100644 index 0000000000000..473b4b71e3c97 --- /dev/null +++ b/patches.renesas/0086-ARM-shmobile-apmu-Add-more-register-documentation.patch @@ -0,0 +1,44 @@ +From 948417ce5dfce9b4c4397df3baa542a32a652592 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 5 Dec 2016 11:39:37 +0100 +Subject: [PATCH 086/255] ARM: shmobile: apmu: Add more register documentation + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 460d4117a4714f3e9ae600974df03632139728ec) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/platsmp-apmu.c | 14 ++++++++++---- + 1 file changed, 10 insertions(+), 4 deletions(-) + +--- a/arch/arm/mach-shmobile/platsmp-apmu.c ++++ b/arch/arm/mach-shmobile/platsmp-apmu.c +@@ -31,9 +31,15 @@ static struct { + int bit; + } apmu_cpus[NR_CPUS]; + +-#define WUPCR_OFFS 0x10 +-#define PSTR_OFFS 0x40 +-#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) ++#define WUPCR_OFFS 0x10 /* Wake Up Control Register */ ++#define PSTR_OFFS 0x40 /* Power Status Register */ ++#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) ++ /* CPUn Power Status Control Register */ ++ ++/* Power Status Register */ ++#define CPUNST(r, n) (((r) >> (n * 4)) & 3) /* CPUn Status Bit */ ++#define CPUST_RUN 0 /* Run Mode */ ++#define CPUST_STANDBY 3 /* CoreStandby Mode */ + + static int __maybe_unused apmu_power_on(void __iomem *p, int bit) + { +@@ -59,7 +65,7 @@ static int __maybe_unused apmu_power_off + int k; + + for (k = 0; k < 1000; k++) { +- if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3) ++ if (CPUNST(readl_relaxed(p + PSTR_OFFS), bit) == CPUST_STANDBY) + return 1; + + mdelay(1); diff --git a/patches.renesas/0087-ARM-shmobile-apmu-Add-debug-resource-reset-for-secon.patch b/patches.renesas/0087-ARM-shmobile-apmu-Add-debug-resource-reset-for-secon.patch new file mode 100644 index 0000000000000..0f3ce9d1fe709 --- /dev/null +++ b/patches.renesas/0087-ARM-shmobile-apmu-Add-debug-resource-reset-for-secon.patch @@ -0,0 +1,68 @@ +From 463cf90aea2706afe2d5b3b7d95957c4a14f8b1e Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 5 Dec 2016 11:39:38 +0100 +Subject: [PATCH 087/255] ARM: shmobile: apmu: Add debug resource reset for + secondary CPU boot + +In debug mode (MD21=1), reset requests derived from power-shutoff to the +AP-system CPU cores must be enabled before the AP-system CPU cores +resume from power-shutoff for the first time. Else resume may fail, +causing the system to hang during boot. + +As setting these bits is a no-op in normal mode, there's no need to +check the actual state of MD21 first. + +Inspired by CPU-specific patches in the BSP by Hisashi Nakamura +<hisashi.nakamura.ak@renesas.com>. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 10f778a97845e8b10af8878af99c9cfe6c31baf9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/platsmp-apmu.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/arch/arm/mach-shmobile/platsmp-apmu.c ++++ b/arch/arm/mach-shmobile/platsmp-apmu.c +@@ -35,12 +35,18 @@ static struct { + #define PSTR_OFFS 0x40 /* Power Status Register */ + #define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) + /* CPUn Power Status Control Register */ ++#define DBGRCR_OFFS 0x180 /* Debug Resource Reset Control Reg. */ + + /* Power Status Register */ + #define CPUNST(r, n) (((r) >> (n * 4)) & 3) /* CPUn Status Bit */ + #define CPUST_RUN 0 /* Run Mode */ + #define CPUST_STANDBY 3 /* CoreStandby Mode */ + ++/* Debug Resource Reset Control Register */ ++#define DBGCPUREN BIT(24) /* CPU Other Reset Request Enable */ ++#define DBGCPUNREN(n) BIT((n) + 20) /* CPUn Reset Request Enable */ ++#define DBGCPUPREN BIT(19) /* CPU Peripheral Reset Req. Enable */ ++ + static int __maybe_unused apmu_power_on(void __iomem *p, int bit) + { + /* request power on */ +@@ -84,6 +90,8 @@ static int __maybe_unused apmu_wrap(int + #ifdef CONFIG_SMP + static void apmu_init_cpu(struct resource *res, int cpu, int bit) + { ++ u32 x; ++ + if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem) + return; + +@@ -91,6 +99,11 @@ static void apmu_init_cpu(struct resourc + apmu_cpus[cpu].bit = bit; + + pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res); ++ ++ /* Setup for debug mode */ ++ x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS); ++ x |= DBGCPUREN | DBGCPUNREN(bit) | DBGCPUPREN; ++ writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS); + } + + static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit), diff --git a/patches.renesas/0088-ARM-shmobile-apmu-Allow-booting-secondary-CPU-cores-.patch b/patches.renesas/0088-ARM-shmobile-apmu-Allow-booting-secondary-CPU-cores-.patch new file mode 100644 index 0000000000000..5c971bf6a76f0 --- /dev/null +++ b/patches.renesas/0088-ARM-shmobile-apmu-Allow-booting-secondary-CPU-cores-.patch @@ -0,0 +1,44 @@ +From 3cff35bc630d64b3e63a939ee91a86f80da415e9 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 5 Dec 2016 11:39:39 +0100 +Subject: [PATCH 088/255] ARM: shmobile: apmu: Allow booting secondary CPU + cores in debug mode + +Now debug resource reset is handled properly, allow booting secondary +CPU cores when hardware debug mode is enabled (MD21=1) on SoCs using the +"renesas,apmu" enable method. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d03c8f78d03af2a46127537dd1daa67164e53c09) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/platsmp-apmu.c | 14 +------------- + 1 file changed, 1 insertion(+), 13 deletions(-) + +--- a/arch/arm/mach-shmobile/platsmp-apmu.c ++++ b/arch/arm/mach-shmobile/platsmp-apmu.c +@@ -216,21 +216,9 @@ static void __init shmobile_smp_apmu_pre + rcar_gen2_pm_init(); + } + +-static int shmobile_smp_apmu_boot_secondary_md21(unsigned int cpu, +- struct task_struct *idle) +-{ +- /* Error out when hardware debug mode is enabled */ +- if (rcar_gen2_read_mode_pins() & BIT(21)) { +- pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu); +- return -ENOTSUPP; +- } +- +- return shmobile_smp_apmu_boot_secondary(cpu, idle); +-} +- + static struct smp_operations apmu_smp_ops __initdata = { + .smp_prepare_cpus = shmobile_smp_apmu_prepare_cpus_dt, +- .smp_boot_secondary = shmobile_smp_apmu_boot_secondary_md21, ++ .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, + #ifdef CONFIG_HOTPLUG_CPU + .cpu_can_disable = shmobile_smp_cpu_can_disable, + .cpu_die = shmobile_smp_apmu_cpu_die, diff --git a/patches.renesas/0089-ARM-shmobile-r8a7791-Allow-booting-secondary-CPU-cor.patch b/patches.renesas/0089-ARM-shmobile-r8a7791-Allow-booting-secondary-CPU-cor.patch new file mode 100644 index 0000000000000..8c3decc62427f --- /dev/null +++ b/patches.renesas/0089-ARM-shmobile-r8a7791-Allow-booting-secondary-CPU-cor.patch @@ -0,0 +1,43 @@ +From 4acd9cfff9819a1ad0fd0759a24f7da6a32be934 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 5 Dec 2016 11:39:40 +0100 +Subject: [PATCH 089/255] ARM: shmobile: r8a7791: Allow booting secondary CPU + cores in debug mode + +Now debug resource reset is handled properly, allow booting secondary +CPU cores when hardware debug mode is enabled (MD21=1, SW8-4=OFF on +koelsch) on legacy r8a7791. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 367ed998fa3e04d8bde42f431e880cd3e5922095) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/smp-r8a7791.c | 14 +------------- + 1 file changed, 1 insertion(+), 13 deletions(-) + +--- a/arch/arm/mach-shmobile/smp-r8a7791.c ++++ b/arch/arm/mach-shmobile/smp-r8a7791.c +@@ -42,21 +42,9 @@ static void __init r8a7791_smp_prepare_c + rcar_gen2_pm_init(); + } + +-static int r8a7791_smp_boot_secondary(unsigned int cpu, +- struct task_struct *idle) +-{ +- /* Error out when hardware debug mode is enabled */ +- if (rcar_gen2_read_mode_pins() & BIT(21)) { +- pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu); +- return -ENOTSUPP; +- } +- +- return shmobile_smp_apmu_boot_secondary(cpu, idle); +-} +- + const struct smp_operations r8a7791_smp_ops __initconst = { + .smp_prepare_cpus = r8a7791_smp_prepare_cpus, +- .smp_boot_secondary = r8a7791_smp_boot_secondary, ++ .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, + #ifdef CONFIG_HOTPLUG_CPU + .cpu_can_disable = shmobile_smp_cpu_can_disable, + .cpu_die = shmobile_smp_apmu_cpu_die, diff --git a/patches.renesas/0090-ARM-shmobile-rcar-gen2-Remove-unused-rcar_gen2_read_.patch b/patches.renesas/0090-ARM-shmobile-rcar-gen2-Remove-unused-rcar_gen2_read_.patch new file mode 100644 index 0000000000000..a29356536492e --- /dev/null +++ b/patches.renesas/0090-ARM-shmobile-rcar-gen2-Remove-unused-rcar_gen2_read_.patch @@ -0,0 +1,62 @@ +From 9aae041bed378e3f58a9f29a3b02f3184386d0ad Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 5 Dec 2016 11:39:41 +0100 +Subject: [PATCH 090/255] ARM: shmobile: rcar-gen2: Remove unused + rcar_gen2_read_mode_pins() + +After + 1. commit 9f5ce39ddb8f68b3 ("ARM: shmobile: rcar-gen2: Obtain extal + frequency from DT"), + 2. commit 80951f04c3f92533 ("ARM: shmobile: rcar-gen2: Stop passing + mode pins state to clock driver"), + 3. and handling of debug resource reset, +there are no more users of rcar_gen2_read_mode_pins() left. +Remove the function and its support definitions. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 70def3e53694a65c5583fb5f411491a5074bab18) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/rcar-gen2.h | 2 -- + arch/arm/mach-shmobile/setup-rcar-gen2.c | 18 ------------------ + 2 files changed, 20 deletions(-) + +--- a/arch/arm/mach-shmobile/rcar-gen2.h ++++ b/arch/arm/mach-shmobile/rcar-gen2.h +@@ -2,8 +2,6 @@ + #define __ASM_RCAR_GEN2_H__ + + void rcar_gen2_timer_init(void); +-#define MD(nr) BIT(nr) +-u32 rcar_gen2_read_mode_pins(void); + void rcar_gen2_reserve(void); + void rcar_gen2_pm_init(void); + +--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c ++++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c +@@ -29,24 +29,6 @@ + #include "common.h" + #include "rcar-gen2.h" + +-#define MODEMR 0xe6160060 +- +-u32 rcar_gen2_read_mode_pins(void) +-{ +- static u32 mode; +- static bool mode_valid; +- +- if (!mode_valid) { +- void __iomem *modemr = ioremap_nocache(MODEMR, 4); +- BUG_ON(!modemr); +- mode = ioread32(modemr); +- iounmap(modemr); +- mode_valid = true; +- } +- +- return mode; +-} +- + static unsigned int __init get_extal_freq(void) + { + struct device_node *cpg, *extal; diff --git a/patches.renesas/0091-ARM-dts-r8a7779-marzen-Fix-sata-device-status.patch b/patches.renesas/0091-ARM-dts-r8a7779-marzen-Fix-sata-device-status.patch new file mode 100644 index 0000000000000..ff7e19ab3255d --- /dev/null +++ b/patches.renesas/0091-ARM-dts-r8a7779-marzen-Fix-sata-device-status.patch @@ -0,0 +1,40 @@ +From 7030bfbcc59fb0c891c85cf1da755ca8643bc00c Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 16 Jan 2017 17:56:53 +0100 +Subject: [PATCH 091/255] ARM: dts: r8a7779, marzen: Fix sata device status + +Device nodes representing I/O devices should be marked disabled in the +SoC-specific DTS, and overridden by board-specific DTSes where needed. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e8aa6811ca9547bc82baa6ed44c38dde01fb0d86) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7779-marzen.dts | 4 ++++ + arch/arm/boot/dts/r8a7779.dtsi | 1 + + 2 files changed, 5 insertions(+) + +--- a/arch/arm/boot/dts/r8a7779-marzen.dts ++++ b/arch/arm/boot/dts/r8a7779-marzen.dts +@@ -216,6 +216,10 @@ + }; + }; + ++&sata { ++ status = "okay"; ++}; ++ + &scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; +--- a/arch/arm/boot/dts/r8a7779.dtsi ++++ b/arch/arm/boot/dts/r8a7779.dtsi +@@ -347,6 +347,7 @@ + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7779_CLK_SATA>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; ++ status = "disabled"; + }; + + sdhi0: sd@ffe4c000 { diff --git a/patches.renesas/0092-ARM-dts-r8a7743-Link-ARM-GIC-to-clock-and-clock-doma.patch b/patches.renesas/0092-ARM-dts-r8a7743-Link-ARM-GIC-to-clock-and-clock-doma.patch new file mode 100644 index 0000000000000..c0d6e112353d8 --- /dev/null +++ b/patches.renesas/0092-ARM-dts-r8a7743-Link-ARM-GIC-to-clock-and-clock-doma.patch @@ -0,0 +1,32 @@ +From 857bf66c19ef49738c8d960ed14ab01d2439c76a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 17 Jan 2017 13:49:17 +0100 +Subject: [PATCH 092/255] ARM: dts: r8a7743: Link ARM GIC to clock and clock + domain + +Link the ARM GIC to the INTC-SYS module clock, and add it to the SYSC +"always-on" PM Domain, so it can be power managed using that clock. + +Note that currently the GIC-400 driver doesn't support module clocks nor +Runtime PM, so this must be handled as a critical clock. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7add1da17ac8d5c4a2ecc967843ca5b55ce35fa6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7743.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/arm/boot/dts/r8a7743.dtsi ++++ b/arch/arm/boot/dts/r8a7743.dtsi +@@ -60,6 +60,9 @@ + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; ++ clocks = <&cpg CPG_MOD 408>; ++ clock-names = "clk"; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + }; + + irqc: interrupt-controller@e61c0000 { diff --git a/patches.renesas/0093-ARM-dts-r8a7745-Link-ARM-GIC-to-clock-and-clock-doma.patch b/patches.renesas/0093-ARM-dts-r8a7745-Link-ARM-GIC-to-clock-and-clock-doma.patch new file mode 100644 index 0000000000000..7c5827508976b --- /dev/null +++ b/patches.renesas/0093-ARM-dts-r8a7745-Link-ARM-GIC-to-clock-and-clock-doma.patch @@ -0,0 +1,32 @@ +From 89b2bf953de2edb3b6c8a2e20cfe763181960b3d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 17 Jan 2017 13:49:18 +0100 +Subject: [PATCH 093/255] ARM: dts: r8a7745: Link ARM GIC to clock and clock + domain + +Link the ARM GIC to the INTC-SYS module clock, and add it to the SYSC +"always-on" PM Domain, so it can be power managed using that clock. + +Note that currently the GIC-400 driver doesn't support module clocks nor +Runtime PM, so this must be handled as a critical clock. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit db017f399639f68827edc954205803272ef20b24) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7745.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/arm/boot/dts/r8a7745.dtsi ++++ b/arch/arm/boot/dts/r8a7745.dtsi +@@ -60,6 +60,9 @@ + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; ++ clocks = <&cpg CPG_MOD 408>; ++ clock-names = "clk"; ++ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + }; + + irqc: interrupt-controller@e61c0000 { diff --git a/patches.renesas/0094-ARM-dts-r7s72100-add-ostm-to-device-tree.patch b/patches.renesas/0094-ARM-dts-r7s72100-add-ostm-to-device-tree.patch new file mode 100644 index 0000000000000..b68aeaf1d1263 --- /dev/null +++ b/patches.renesas/0094-ARM-dts-r7s72100-add-ostm-to-device-tree.patch @@ -0,0 +1,39 @@ +From ed99342207c376ac3b4fbd5239160f2634e24ced Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Mon, 23 Jan 2017 08:55:19 -0500 +Subject: [PATCH 094/255] ARM: dts: r7s72100: add ostm to device tree + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 69b5c6dceaa138859f03ca20e3adca7ddec6bae7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/arm/boot/dts/r7s72100.dtsi ++++ b/arch/arm/boot/dts/r7s72100.dtsi +@@ -505,4 +505,22 @@ + cap-sdio-irq; + status = "disabled"; + }; ++ ++ ostm0: timer@fcfec000 { ++ compatible = "renesas,r7s72100-ostm", "renesas,ostm"; ++ reg = <0xfcfec000 0x30>; ++ interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; ++ clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; ++ power-domains = <&cpg_clocks>; ++ status = "disabled"; ++ }; ++ ++ ostm1: timer@fcfec400 { ++ compatible = "renesas,r7s72100-ostm", "renesas,ostm"; ++ reg = <0xfcfec400 0x30>; ++ interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>; ++ clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; ++ power-domains = <&cpg_clocks>; ++ status = "disabled"; ++ }; + }; diff --git a/patches.renesas/0095-ARM-dts-rskrza1-add-ostm-DT-support.patch b/patches.renesas/0095-ARM-dts-rskrza1-add-ostm-DT-support.patch new file mode 100644 index 0000000000000..e28376be61e50 --- /dev/null +++ b/patches.renesas/0095-ARM-dts-rskrza1-add-ostm-DT-support.patch @@ -0,0 +1,31 @@ +From 33c31760ff927144b6787520998658854f475732 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Mon, 23 Jan 2017 08:55:20 -0500 +Subject: [PATCH 095/255] ARM: dts: rskrza1: add ostm DT support + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 37dfe2afc5618d42d3214a61ed017ce4bbc12254) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100-rskrza1.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts ++++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts +@@ -61,6 +61,14 @@ + status = "okay"; + }; + ++&ostm0 { ++ status = "okay"; ++}; ++ ++&ostm1 { ++ status = "okay"; ++}; ++ + &scif2 { + status = "okay"; + }; diff --git a/patches.renesas/0096-ARM-shmobile-rcar-gen2-Add-more-register-documentati.patch b/patches.renesas/0096-ARM-shmobile-rcar-gen2-Add-more-register-documentati.patch new file mode 100644 index 0000000000000..3f12b86bd59ec --- /dev/null +++ b/patches.renesas/0096-ARM-shmobile-rcar-gen2-Add-more-register-documentati.patch @@ -0,0 +1,83 @@ +From cc2657f086566fb81b3b01edbe2926a7de51cf58 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 25 Jan 2017 10:02:13 +0100 +Subject: [PATCH 096/255] ARM: shmobile: rcar-gen2: Add more register + documentation + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit aa7f39d51e33555fc45645c08bc74a74e22b166f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 ++++++++++++++++++++++++---------- + 1 file changed, 29 insertions(+), 11 deletions(-) + +--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c ++++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c +@@ -20,14 +20,30 @@ + + /* RST */ + #define RST 0xe6160000 +-#define CA15BAR 0x0020 +-#define CA7BAR 0x0030 +-#define CA15RESCNT 0x0040 +-#define CA7RESCNT 0x0044 ++ ++#define CA15BAR 0x0020 /* CA15 Boot Address Register */ ++#define CA7BAR 0x0030 /* CA7 Boot Address Register */ ++#define CA15RESCNT 0x0040 /* CA15 Reset Control Register */ ++#define CA7RESCNT 0x0044 /* CA7 Reset Control Register */ ++ ++/* SYS Boot Address Register */ ++#define SBAR_BAREN BIT(4) /* SBAR is valid */ ++ ++/* Reset Control Registers */ ++#define CA15RESCNT_CODE 0xa5a50000 ++#define CA15RESCNT_CPUS 0xf /* CPU0-3 */ ++#define CA7RESCNT_CODE 0x5a5a0000 ++#define CA7RESCNT_CPUS 0xf /* CPU0-3 */ ++ + + /* On-chip RAM */ + #define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */ + ++static inline u32 phys_to_sbar(phys_addr_t addr) ++{ ++ return (addr >> 8) & 0xfffffc00; ++} ++ + /* SYSC */ + #define SYSCIER 0x0c + #define SYSCIMR 0x10 +@@ -82,22 +98,24 @@ void __init rcar_gen2_pm_init(void) + + /* setup reset vectors */ + p = ioremap_nocache(RST, 0x63); +- bar = (boot_vector_addr >> 8) & 0xfffffc00; ++ bar = phys_to_sbar(boot_vector_addr); + if (has_a15) { + writel_relaxed(bar, p + CA15BAR); +- writel_relaxed(bar | 0x10, p + CA15BAR); ++ writel_relaxed(bar | SBAR_BAREN, p + CA15BAR); + + /* de-assert reset for CA15 CPUs */ +- writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | +- 0xa5a50000, p + CA15RESCNT); ++ writel_relaxed((readl_relaxed(p + CA15RESCNT) & ++ ~CA15RESCNT_CPUS) | CA15RESCNT_CODE, ++ p + CA15RESCNT); + } + if (has_a7) { + writel_relaxed(bar, p + CA7BAR); +- writel_relaxed(bar | 0x10, p + CA7BAR); ++ writel_relaxed(bar | SBAR_BAREN, p + CA7BAR); + + /* de-assert reset for CA7 CPUs */ +- writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | +- 0x5a5a0000, p + CA7RESCNT); ++ writel_relaxed((readl_relaxed(p + CA7RESCNT) & ++ ~CA7RESCNT_CPUS) | CA7RESCNT_CODE, ++ p + CA7RESCNT); + } + iounmap(p); + diff --git a/patches.renesas/0097-ARM-dts-r7s72100-add-power-domains-to-mmcif.patch b/patches.renesas/0097-ARM-dts-r7s72100-add-power-domains-to-mmcif.patch new file mode 100644 index 0000000000000..7418e70e7181f --- /dev/null +++ b/patches.renesas/0097-ARM-dts-r7s72100-add-power-domains-to-mmcif.patch @@ -0,0 +1,25 @@ +From cb50333d5a96772dcaf7b33f94df768ea08bf36a Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Mon, 23 Jan 2017 09:13:49 -0500 +Subject: [PATCH 097/255] ARM: dts: r7s72100: add power-domains to mmcif + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5786ac14239a0809ca13e6a6f77147e6bb04aa29) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/boot/dts/r7s72100.dtsi ++++ b/arch/arm/boot/dts/r7s72100.dtsi +@@ -475,6 +475,7 @@ + GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; ++ power-domains = <&cpg_clocks>; + reg-io-width = <4>; + bus-width = <8>; + status = "disabled"; diff --git a/patches.renesas/0098-ARM-DTS-Fix-register-map-for-virt-capable-GIC.patch b/patches.renesas/0098-ARM-DTS-Fix-register-map-for-virt-capable-GIC.patch new file mode 100644 index 0000000000000..d68d481c077f3 --- /dev/null +++ b/patches.renesas/0098-ARM-DTS-Fix-register-map-for-virt-capable-GIC.patch @@ -0,0 +1,499 @@ +From 7a197c474987b18e90026842698f0175a10b9834 Mon Sep 17 00:00:00 2001 +From: Marc Zyngier <marc.zyngier@arm.com> +Date: Wed, 18 Jan 2017 09:27:28 +0000 +Subject: [PATCH 098/255] ARM: DTS: Fix register map for virt-capable GIC + +Since everybody copied my own mistake from the DT binding example, +let's address all the offenders in one swift go. + +Most of them got the CPU interface size wrong (4kB, while it should +be 8kB), except for both keystone platforms which got the control +interface wrong (4kB instead of 8kB). + +In a few cases where I knew for sure what implementation was used, +I've added the "arm,gic-400" compatible string. I'm 99% sure that +this is what everyone is using, but short of having the TRM for +all the other SoCs, I've left them alone. + +Acked-by: Shawn Guo <shawnguo@kernel.org> +Acked-by: Tony Lindgren <tony@atomide.com> +Acked-by: Santosh Shilimkar <ssantosh@kernel.org> +Acked-by: Krzysztof Kozlowski <krzk@kernel.org> +Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> +Acked-by: Arnd Bergmann <arnd@arndb.de> +Acked-by: Matthias Brugger <matthias.bgg@gmail.com> +Acked-by: Heiko Stuebner <heiko@sntech.de> +Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> +Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> +Signed-off-by: Arnd Bergmann <arnd@arndb.de> +(cherry picked from commit 387720c93812f1e702c20c667cb003a356e24a6c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm/boot/dts/rk1108.dtsi +--- + arch/arm/boot/dts/alpine.dtsi | 2 +- + arch/arm/boot/dts/axm55xx.dtsi | 2 +- + arch/arm/boot/dts/dra7.dtsi | 2 +- + arch/arm/boot/dts/ecx-2000.dts | 2 +- + arch/arm/boot/dts/exynos3250.dtsi | 2 +- + arch/arm/boot/dts/exynos5.dtsi | 4 ++-- + arch/arm/boot/dts/exynos5260.dtsi | 2 +- + arch/arm/boot/dts/exynos5440.dtsi | 2 +- + arch/arm/boot/dts/imx6ul.dtsi | 4 ++-- + arch/arm/boot/dts/keystone-k2g.dtsi | 4 ++-- + arch/arm/boot/dts/keystone.dtsi | 4 ++-- + arch/arm/boot/dts/ls1021a.dtsi | 4 ++-- + arch/arm/boot/dts/mt2701.dtsi | 2 +- + arch/arm/boot/dts/mt6580.dtsi | 2 +- + arch/arm/boot/dts/mt6589.dtsi | 2 +- + arch/arm/boot/dts/mt7623.dtsi | 2 +- + arch/arm/boot/dts/mt8127.dtsi | 2 +- + arch/arm/boot/dts/mt8135.dtsi | 2 +- + arch/arm/boot/dts/omap5.dtsi | 2 +- + arch/arm/boot/dts/r8a73a4.dtsi | 2 +- + arch/arm/boot/dts/r8a7743.dtsi | 2 +- + arch/arm/boot/dts/r8a7745.dtsi | 2 +- + arch/arm/boot/dts/r8a7790.dtsi | 2 +- + arch/arm/boot/dts/r8a7791.dtsi | 2 +- + arch/arm/boot/dts/r8a7792.dtsi | 2 +- + arch/arm/boot/dts/r8a7793.dtsi | 2 +- + arch/arm/boot/dts/r8a7794.dtsi | 2 +- + arch/arm/boot/dts/rk3036.dtsi | 2 +- + arch/arm/boot/dts/rk322x.dtsi | 2 +- + arch/arm/boot/dts/rk3288.dtsi | 2 +- + arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- + arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++-- + arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- + arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +- + arch/arm/boot/dts/sun8i-h3.dtsi | 2 +- + arch/arm/boot/dts/sun9i-a80.dtsi | 2 +- + 36 files changed, 42 insertions(+), 42 deletions(-) + +--- a/arch/arm/boot/dts/alpine.dtsi ++++ b/arch/arm/boot/dts/alpine.dtsi +@@ -93,7 +93,7 @@ + interrupt-controller; + reg = <0x0 0xfb001000 0x0 0x1000>, + <0x0 0xfb002000 0x0 0x2000>, +- <0x0 0xfb004000 0x0 0x1000>, ++ <0x0 0xfb004000 0x0 0x2000>, + <0x0 0xfb006000 0x0 0x2000>; + interrupts = + <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; +--- a/arch/arm/boot/dts/axm55xx.dtsi ++++ b/arch/arm/boot/dts/axm55xx.dtsi +@@ -62,7 +62,7 @@ + #address-cells = <0>; + interrupt-controller; + reg = <0x20 0x01001000 0 0x1000>, +- <0x20 0x01002000 0 0x1000>, ++ <0x20 0x01002000 0 0x2000>, + <0x20 0x01004000 0 0x2000>, + <0x20 0x01006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | +--- a/arch/arm/boot/dts/dra7.dtsi ++++ b/arch/arm/boot/dts/dra7.dtsi +@@ -57,7 +57,7 @@ + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x48211000 0x0 0x1000>, +- <0x0 0x48212000 0x0 0x1000>, ++ <0x0 0x48212000 0x0 0x2000>, + <0x0 0x48214000 0x0 0x2000>, + <0x0 0x48216000 0x0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; +--- a/arch/arm/boot/dts/ecx-2000.dts ++++ b/arch/arm/boot/dts/ecx-2000.dts +@@ -99,7 +99,7 @@ + interrupt-controller; + interrupts = <1 9 0xf04>; + reg = <0xfff11000 0x1000>, +- <0xfff12000 0x1000>, ++ <0xfff12000 0x2000>, + <0xfff14000 0x2000>, + <0xfff16000 0x2000>; + }; +--- a/arch/arm/boot/dts/exynos3250.dtsi ++++ b/arch/arm/boot/dts/exynos3250.dtsi +@@ -231,7 +231,7 @@ + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, +- <0x10482000 0x1000>, ++ <0x10482000 0x2000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; +--- a/arch/arm/boot/dts/exynos5.dtsi ++++ b/arch/arm/boot/dts/exynos5.dtsi +@@ -64,11 +64,11 @@ + }; + + gic: interrupt-controller@10481000 { +- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; ++ compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, +- <0x10482000 0x1000>, ++ <0x10482000 0x2000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; +--- a/arch/arm/boot/dts/exynos5260.dtsi ++++ b/arch/arm/boot/dts/exynos5260.dtsi +@@ -165,7 +165,7 @@ + #size-cells = <0>; + interrupt-controller; + reg = <0x10481000 0x1000>, +- <0x10482000 0x1000>, ++ <0x10482000 0x2000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; +--- a/arch/arm/boot/dts/exynos5440.dtsi ++++ b/arch/arm/boot/dts/exynos5440.dtsi +@@ -38,7 +38,7 @@ + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x2E1000 0x1000>, +- <0x2E2000 0x1000>, ++ <0x2E2000 0x2000>, + <0x2E4000 0x2000>, + <0x2E6000 0x2000>; + interrupts = <1 9 0xf04>; +--- a/arch/arm/boot/dts/imx6ul.dtsi ++++ b/arch/arm/boot/dts/imx6ul.dtsi +@@ -89,11 +89,11 @@ + }; + + intc: interrupt-controller@00a01000 { +- compatible = "arm,cortex-a7-gic"; ++ compatible = "arm,gic-400", "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, +- <0x00a02000 0x1000>, ++ <0x00a02000 0x2000>, + <0x00a04000 0x2000>, + <0x00a06000 0x2000>; + }; +--- a/arch/arm/boot/dts/keystone-k2g.dtsi ++++ b/arch/arm/boot/dts/keystone-k2g.dtsi +@@ -40,12 +40,12 @@ + }; + + gic: interrupt-controller@02561000 { +- compatible = "arm,cortex-a15-gic"; ++ compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x02561000 0x0 0x1000>, + <0x0 0x02562000 0x0 0x2000>, +- <0x0 0x02564000 0x0 0x1000>, ++ <0x0 0x02564000 0x0 0x2000>, + <0x0 0x02566000 0x0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; +--- a/arch/arm/boot/dts/keystone.dtsi ++++ b/arch/arm/boot/dts/keystone.dtsi +@@ -30,12 +30,12 @@ + }; + + gic: interrupt-controller { +- compatible = "arm,cortex-a15-gic"; ++ compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x02561000 0x0 0x1000>, + <0x0 0x02562000 0x0 0x2000>, +- <0x0 0x02564000 0x0 0x1000>, ++ <0x0 0x02564000 0x0 0x2000>, + <0x0 0x02566000 0x0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; +--- a/arch/arm/boot/dts/ls1021a.dtsi ++++ b/arch/arm/boot/dts/ls1021a.dtsi +@@ -108,11 +108,11 @@ + ranges; + + gic: interrupt-controller@1400000 { +- compatible = "arm,cortex-a7-gic"; ++ compatible = "arm,gic-400", "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0x0 0x1000>, +- <0x0 0x1402000 0x0 0x1000>, ++ <0x0 0x1402000 0x0 0x2000>, + <0x0 0x1404000 0x0 0x2000>, + <0x0 0x1406000 0x0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; +--- a/arch/arm/boot/dts/mt2701.dtsi ++++ b/arch/arm/boot/dts/mt2701.dtsi +@@ -134,7 +134,7 @@ + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10211000 0 0x1000>, +- <0 0x10212000 0 0x1000>, ++ <0 0x10212000 0 0x2000>, + <0 0x10214000 0 0x2000>, + <0 0x10216000 0 0x2000>; + }; +--- a/arch/arm/boot/dts/mt6580.dtsi ++++ b/arch/arm/boot/dts/mt6580.dtsi +@@ -91,7 +91,7 @@ + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, +- <0x10212000 0x1000>, ++ <0x10212000 0x2000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; +--- a/arch/arm/boot/dts/mt6589.dtsi ++++ b/arch/arm/boot/dts/mt6589.dtsi +@@ -102,7 +102,7 @@ + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, +- <0x10212000 0x1000>, ++ <0x10212000 0x2000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; +--- a/arch/arm/boot/dts/mt7623.dtsi ++++ b/arch/arm/boot/dts/mt7623.dtsi +@@ -104,7 +104,7 @@ + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10211000 0 0x1000>, +- <0 0x10212000 0 0x1000>, ++ <0 0x10212000 0 0x2000>, + <0 0x10214000 0 0x2000>, + <0 0x10216000 0 0x2000>; + }; +--- a/arch/arm/boot/dts/mt8127.dtsi ++++ b/arch/arm/boot/dts/mt8127.dtsi +@@ -129,7 +129,7 @@ + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10211000 0 0x1000>, +- <0 0x10212000 0 0x1000>, ++ <0 0x10212000 0 0x2000>, + <0 0x10214000 0 0x2000>, + <0 0x10216000 0 0x2000>; + }; +--- a/arch/arm/boot/dts/mt8135.dtsi ++++ b/arch/arm/boot/dts/mt8135.dtsi +@@ -221,7 +221,7 @@ + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10211000 0 0x1000>, +- <0 0x10212000 0 0x1000>, ++ <0 0x10212000 0 0x2000>, + <0 0x10214000 0 0x2000>, + <0 0x10216000 0 0x2000>; + }; +--- a/arch/arm/boot/dts/omap5.dtsi ++++ b/arch/arm/boot/dts/omap5.dtsi +@@ -92,7 +92,7 @@ + interrupt-controller; + #interrupt-cells = <3>; + reg = <0 0x48211000 0 0x1000>, +- <0 0x48212000 0 0x1000>, ++ <0 0x48212000 0 0x2000>, + <0 0x48214000 0 0x2000>, + <0 0x48216000 0 0x2000>; + interrupt-parent = <&gic>; +--- a/arch/arm/boot/dts/r8a73a4.dtsi ++++ b/arch/arm/boot/dts/r8a73a4.dtsi +@@ -465,7 +465,7 @@ + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, +- <0 0xf1002000 0 0x1000>, ++ <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; +--- a/arch/arm/boot/dts/r8a7743.dtsi ++++ b/arch/arm/boot/dts/r8a7743.dtsi +@@ -55,7 +55,7 @@ + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, +- <0 0xf1002000 0 0x1000>, ++ <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | +--- a/arch/arm/boot/dts/r8a7745.dtsi ++++ b/arch/arm/boot/dts/r8a7745.dtsi +@@ -55,7 +55,7 @@ + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, +- <0 0xf1002000 0 0x1000>, ++ <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -183,7 +183,7 @@ + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, +- <0 0xf1002000 0 0x1000>, ++ <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -114,7 +114,7 @@ + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, +- <0 0xf1002000 0 0x1000>, ++ <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; +--- a/arch/arm/boot/dts/r8a7792.dtsi ++++ b/arch/arm/boot/dts/r8a7792.dtsi +@@ -88,7 +88,7 @@ + #interrupt-cells = <3>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, +- <0 0xf1002000 0 0x1000>, ++ <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | +--- a/arch/arm/boot/dts/r8a7793.dtsi ++++ b/arch/arm/boot/dts/r8a7793.dtsi +@@ -105,7 +105,7 @@ + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, +- <0 0xf1002000 0 0x1000>, ++ <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -71,7 +71,7 @@ + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, +- <0 0xf1002000 0 0x1000>, ++ <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; +--- a/arch/arm/boot/dts/rk3036.dtsi ++++ b/arch/arm/boot/dts/rk3036.dtsi +@@ -187,7 +187,7 @@ + #address-cells = <0>; + + reg = <0x10139000 0x1000>, +- <0x1013a000 0x1000>, ++ <0x1013a000 0x2000>, + <0x1013c000 0x2000>, + <0x1013e000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; +--- a/arch/arm/boot/dts/rk322x.dtsi ++++ b/arch/arm/boot/dts/rk322x.dtsi +@@ -441,7 +441,7 @@ + #address-cells = <0>; + + reg = <0x32011000 0x1000>, +- <0x32012000 0x1000>, ++ <0x32012000 0x2000>, + <0x32014000 0x2000>, + <0x32016000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1109,7 +1109,7 @@ + #address-cells = <0>; + + reg = <0xffc01000 0x1000>, +- <0xffc02000 0x1000>, ++ <0xffc02000 0x2000>, + <0xffc04000 0x2000>, + <0xffc06000 0x2000>; + interrupts = <GIC_PPI 9 0xf04>; +--- a/arch/arm/boot/dts/sun6i-a31.dtsi ++++ b/arch/arm/boot/dts/sun6i-a31.dtsi +@@ -791,7 +791,7 @@ + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, +- <0x01c82000 0x1000>, ++ <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; +--- a/arch/arm/boot/dts/sun7i-a20.dtsi ++++ b/arch/arm/boot/dts/sun7i-a20.dtsi +@@ -1685,9 +1685,9 @@ + }; + + gic: interrupt-controller@01c81000 { +- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; ++ compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, +- <0x01c82000 0x1000>, ++ <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; +--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi ++++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi +@@ -488,7 +488,7 @@ + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, +- <0x01c82000 0x1000>, ++ <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; +--- a/arch/arm/boot/dts/sun8i-a83t.dtsi ++++ b/arch/arm/boot/dts/sun8i-a83t.dtsi +@@ -217,7 +217,7 @@ + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, +- <0x01c82000 0x1000>, ++ <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; +--- a/arch/arm/boot/dts/sun8i-h3.dtsi ++++ b/arch/arm/boot/dts/sun8i-h3.dtsi +@@ -533,7 +533,7 @@ + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, +- <0x01c82000 0x1000>, ++ <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; +--- a/arch/arm/boot/dts/sun9i-a80.dtsi ++++ b/arch/arm/boot/dts/sun9i-a80.dtsi +@@ -613,7 +613,7 @@ + gic: interrupt-controller@01c41000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c41000 0x1000>, +- <0x01c42000 0x1000>, ++ <0x01c42000 0x2000>, + <0x01c44000 0x2000>, + <0x01c46000 0x2000>; + interrupt-controller; diff --git a/patches.renesas/0099-clocksource-drivers-ostm-Document-renesas-ostm-timer.patch b/patches.renesas/0099-clocksource-drivers-ostm-Document-renesas-ostm-timer.patch new file mode 100644 index 0000000000000..465dc0950f57f --- /dev/null +++ b/patches.renesas/0099-clocksource-drivers-ostm-Document-renesas-ostm-timer.patch @@ -0,0 +1,50 @@ +From 85354f1d98b2cc8f4969b23601a8ee19a6693aca Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Fri, 27 Jan 2017 15:02:14 -0500 +Subject: [PATCH 099/255] clocksource/drivers/ostm: Document renesas-ostm timer + DT bindings + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Rob Herring <robh@kernel.org> +Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> +(cherry picked from commit a1966cd29d5fee2fada47b82dcb73126eb65dfd4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/timer/renesas,ostm.txt | 30 +++++++++++++++ + 1 file changed, 30 insertions(+) + create mode 100644 Documentation/devicetree/bindings/timer/renesas,ostm.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/timer/renesas,ostm.txt +@@ -0,0 +1,30 @@ ++* Renesas OS Timer (OSTM) ++ ++The OSTM is a multi-channel 32-bit timer/counter with fixed clock ++source that can operate in either interval count down timer or free-running ++compare match mode. ++ ++Channels are independent from each other. ++ ++Required Properties: ++ ++ - compatible: must be one or more of the following: ++ - "renesas,r7s72100-ostm" for the r7s72100 OSTM ++ - "renesas,ostm" for any OSTM ++ This is a fallback for the above renesas,*-ostm entries ++ ++ - reg: base address and length of the register block for a timer channel. ++ ++ - interrupts: interrupt specifier for the timer channel. ++ ++ - clocks: clock specifier for the timer channel. ++ ++Example: R7S72100 (RZ/A1H) OSTM node ++ ++ ostm0: timer@fcfec000 { ++ compatible = "renesas,r7s72100-ostm", "renesas,ostm"; ++ reg = <0xfcfec000 0x30>; ++ interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; ++ clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; ++ power-domains = <&cpg_clocks>; ++ }; diff --git a/patches.renesas/0100-clocksource-drivers-ostm-Add-renesas-ostm-timer-driv.patch b/patches.renesas/0100-clocksource-drivers-ostm-Add-renesas-ostm-timer-driv.patch new file mode 100644 index 0000000000000..f42c82eebe7d4 --- /dev/null +++ b/patches.renesas/0100-clocksource-drivers-ostm-Add-renesas-ostm-timer-driv.patch @@ -0,0 +1,328 @@ +From 3a270a74650943e0e033f0552536169c5f6966d8 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Fri, 27 Jan 2017 15:02:15 -0500 +Subject: [PATCH 100/255] clocksource/drivers/ostm: Add renesas-ostm timer + driver + +This patch adds a OSTM driver for the Renesas architecture. +The OS Timer (OSTM) has independent channels that can be +used as a freerun or interval times. +This driver uses the first probed device as a clocksource +and then any additional devices as clock events. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> +(cherry picked from commit fb6002a8268c493435d0e6d0d6ad17873919a7f6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/Kconfig | 1 + drivers/clocksource/Kconfig | 7 + drivers/clocksource/Makefile | 1 + drivers/clocksource/renesas-ostm.c | 265 +++++++++++++++++++++++++++++++++++++ + 4 files changed, 274 insertions(+) + create mode 100644 drivers/clocksource/renesas-ostm.c + +--- a/arch/arm/mach-shmobile/Kconfig ++++ b/arch/arm/mach-shmobile/Kconfig +@@ -57,6 +57,7 @@ config ARCH_R7S72100 + select PM + select PM_GENERIC_DOMAINS + select SYS_SUPPORTS_SH_MTU2 ++ select RENESAS_OSTM + + config ARCH_R8A73A4 + bool "R-Mobile APE6 (R8A73A40)" +--- a/drivers/clocksource/Kconfig ++++ b/drivers/clocksource/Kconfig +@@ -447,6 +447,13 @@ config SH_TIMER_MTU2 + Timer Pulse Unit 2 (MTU2) hardware available on SoCs from Renesas. + This hardware comes with 16 bit-timer registers. + ++config RENESAS_OSTM ++ bool "Renesas OSTM timer driver" if COMPILE_TEST ++ depends on GENERIC_CLOCKEVENTS ++ select CLKSRC_MMIO ++ help ++ Enables the support for the Renesas OSTM. ++ + config SH_TIMER_TMU + bool "Renesas TMU timer driver" if COMPILE_TEST + depends on GENERIC_CLOCKEVENTS +--- a/drivers/clocksource/Makefile ++++ b/drivers/clocksource/Makefile +@@ -8,6 +8,7 @@ obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += + obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o + obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o + obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o ++obj-$(CONFIG_RENESAS_OSTM) += renesas-ostm.o + obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o + obj-$(CONFIG_EM_TIMER_STI) += em_sti.o + obj-$(CONFIG_CLKBLD_I8253) += i8253.o +--- /dev/null ++++ b/drivers/clocksource/renesas-ostm.c +@@ -0,0 +1,265 @@ ++/* ++ * Renesas Timer Support - OSTM ++ * ++ * Copyright (C) 2017 Renesas Electronics America, Inc. ++ * Copyright (C) 2017 Chris Brandt ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#include <linux/of_address.h> ++#include <linux/of_irq.h> ++#include <linux/clk.h> ++#include <linux/clockchips.h> ++#include <linux/interrupt.h> ++#include <linux/sched_clock.h> ++#include <linux/slab.h> ++ ++/* ++ * The OSTM contains independent channels. ++ * The first OSTM channel probed will be set up as a free running ++ * clocksource. Additionally we will use this clocksource for the system ++ * schedule timer sched_clock(). ++ * ++ * The second (or more) channel probed will be set up as an interrupt ++ * driven clock event. ++ */ ++ ++struct ostm_device { ++ void __iomem *base; ++ unsigned long ticks_per_jiffy; ++ struct clock_event_device ced; ++}; ++ ++static void __iomem *system_clock; /* For sched_clock() */ ++ ++/* OSTM REGISTERS */ ++#define OSTM_CMP 0x000 /* RW,32 */ ++#define OSTM_CNT 0x004 /* R,32 */ ++#define OSTM_TE 0x010 /* R,8 */ ++#define OSTM_TS 0x014 /* W,8 */ ++#define OSTM_TT 0x018 /* W,8 */ ++#define OSTM_CTL 0x020 /* RW,8 */ ++ ++#define TE 0x01 ++#define TS 0x01 ++#define TT 0x01 ++#define CTL_PERIODIC 0x00 ++#define CTL_ONESHOT 0x02 ++#define CTL_FREERUN 0x02 ++ ++static struct ostm_device *ced_to_ostm(struct clock_event_device *ced) ++{ ++ return container_of(ced, struct ostm_device, ced); ++} ++ ++static void ostm_timer_stop(struct ostm_device *ostm) ++{ ++ if (readb(ostm->base + OSTM_TE) & TE) { ++ writeb(TT, ostm->base + OSTM_TT); ++ ++ /* ++ * Read back the register simply to confirm the write operation ++ * has completed since I/O writes can sometimes get queued by ++ * the bus architecture. ++ */ ++ while (readb(ostm->base + OSTM_TE) & TE) ++ ; ++ } ++} ++ ++static int __init ostm_init_clksrc(struct ostm_device *ostm, unsigned long rate) ++{ ++ /* ++ * irq not used (clock sources don't use interrupts) ++ */ ++ ++ ostm_timer_stop(ostm); ++ ++ writel(0, ostm->base + OSTM_CMP); ++ writeb(CTL_FREERUN, ostm->base + OSTM_CTL); ++ writeb(TS, ostm->base + OSTM_TS); ++ ++ return clocksource_mmio_init(ostm->base + OSTM_CNT, ++ "ostm", rate, ++ 300, 32, clocksource_mmio_readl_up); ++} ++ ++static u64 notrace ostm_read_sched_clock(void) ++{ ++ return readl(system_clock); ++} ++ ++static void __init ostm_init_sched_clock(struct ostm_device *ostm, ++ unsigned long rate) ++{ ++ system_clock = ostm->base + OSTM_CNT; ++ sched_clock_register(ostm_read_sched_clock, 32, rate); ++} ++ ++static int ostm_clock_event_next(unsigned long delta, ++ struct clock_event_device *ced) ++{ ++ struct ostm_device *ostm = ced_to_ostm(ced); ++ ++ ostm_timer_stop(ostm); ++ ++ writel(delta, ostm->base + OSTM_CMP); ++ writeb(CTL_ONESHOT, ostm->base + OSTM_CTL); ++ writeb(TS, ostm->base + OSTM_TS); ++ ++ return 0; ++} ++ ++static int ostm_shutdown(struct clock_event_device *ced) ++{ ++ struct ostm_device *ostm = ced_to_ostm(ced); ++ ++ ostm_timer_stop(ostm); ++ ++ return 0; ++} ++static int ostm_set_periodic(struct clock_event_device *ced) ++{ ++ struct ostm_device *ostm = ced_to_ostm(ced); ++ ++ if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) ++ ostm_timer_stop(ostm); ++ ++ writel(ostm->ticks_per_jiffy - 1, ostm->base + OSTM_CMP); ++ writeb(CTL_PERIODIC, ostm->base + OSTM_CTL); ++ writeb(TS, ostm->base + OSTM_TS); ++ ++ return 0; ++} ++ ++static int ostm_set_oneshot(struct clock_event_device *ced) ++{ ++ struct ostm_device *ostm = ced_to_ostm(ced); ++ ++ ostm_timer_stop(ostm); ++ ++ return 0; ++} ++ ++static irqreturn_t ostm_timer_interrupt(int irq, void *dev_id) ++{ ++ struct ostm_device *ostm = dev_id; ++ ++ if (clockevent_state_oneshot(&ostm->ced)) ++ ostm_timer_stop(ostm); ++ ++ /* notify clockevent layer */ ++ if (ostm->ced.event_handler) ++ ostm->ced.event_handler(&ostm->ced); ++ ++ return IRQ_HANDLED; ++} ++ ++static int __init ostm_init_clkevt(struct ostm_device *ostm, int irq, ++ unsigned long rate) ++{ ++ struct clock_event_device *ced = &ostm->ced; ++ int ret = -ENXIO; ++ ++ ret = request_irq(irq, ostm_timer_interrupt, ++ IRQF_TIMER | IRQF_IRQPOLL, ++ "ostm", ostm); ++ if (ret) { ++ pr_err("ostm: failed to request irq\n"); ++ return ret; ++ } ++ ++ ced->name = "ostm"; ++ ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; ++ ced->set_state_shutdown = ostm_shutdown; ++ ced->set_state_periodic = ostm_set_periodic; ++ ced->set_state_oneshot = ostm_set_oneshot; ++ ced->set_next_event = ostm_clock_event_next; ++ ced->shift = 32; ++ ced->rating = 300; ++ ced->cpumask = cpumask_of(0); ++ clockevents_config_and_register(ced, rate, 0xf, 0xffffffff); ++ ++ return 0; ++} ++ ++static int __init ostm_init(struct device_node *np) ++{ ++ struct ostm_device *ostm; ++ int ret = -EFAULT; ++ struct clk *ostm_clk = NULL; ++ int irq; ++ unsigned long rate; ++ ++ ostm = kzalloc(sizeof(*ostm), GFP_KERNEL); ++ if (!ostm) ++ return -ENOMEM; ++ ++ ostm->base = of_iomap(np, 0); ++ if (!ostm->base) { ++ pr_err("ostm: failed to remap I/O memory\n"); ++ goto err; ++ } ++ ++ irq = irq_of_parse_and_map(np, 0); ++ if (irq < 0) { ++ pr_err("ostm: Failed to get irq\n"); ++ goto err; ++ } ++ ++ ostm_clk = of_clk_get(np, 0); ++ if (IS_ERR(ostm_clk)) { ++ pr_err("ostm: Failed to get clock\n"); ++ ostm_clk = NULL; ++ goto err; ++ } ++ ++ ret = clk_prepare_enable(ostm_clk); ++ if (ret) { ++ pr_err("ostm: Failed to enable clock\n"); ++ goto err; ++ } ++ ++ rate = clk_get_rate(ostm_clk); ++ ostm->ticks_per_jiffy = (rate + HZ / 2) / HZ; ++ ++ /* ++ * First probed device will be used as system clocksource. Any ++ * additional devices will be used as clock events. ++ */ ++ if (!system_clock) { ++ ret = ostm_init_clksrc(ostm, rate); ++ ++ if (!ret) { ++ ostm_init_sched_clock(ostm, rate); ++ pr_info("ostm: used for clocksource\n"); ++ } ++ ++ } else { ++ ret = ostm_init_clkevt(ostm, irq, rate); ++ ++ if (!ret) ++ pr_info("ostm: used for clock events\n"); ++ } ++ ++err: ++ if (ret) { ++ clk_disable_unprepare(ostm_clk); ++ iounmap(ostm->base); ++ kfree(ostm); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++CLOCKSOURCE_OF_DECLARE(ostm, "renesas,ostm", ostm_init); diff --git a/patches.renesas/0101-PCI-rcar-Return-ENODEV-from-host-bridge-probe-when-n.patch b/patches.renesas/0101-PCI-rcar-Return-ENODEV-from-host-bridge-probe-when-n.patch new file mode 100644 index 0000000000000..a71b62b7a1819 --- /dev/null +++ b/patches.renesas/0101-PCI-rcar-Return-ENODEV-from-host-bridge-probe-when-n.patch @@ -0,0 +1,31 @@ +From 73582cecf60fca9237d71dfbd398c44f9d6bc3e6 Mon Sep 17 00:00:00 2001 +From: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> +Date: Fri, 16 Dec 2016 12:50:04 +0100 +Subject: [PATCH 101/255] PCI: rcar: Return -ENODEV from host bridge probe when + no card present + +R-Car PCIe does not support hotplug so it is appropriate to treat the +absence of a PCIe card as an -ENODEV error. + +Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> +[simon: updated changelog] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> +(cherry picked from commit e94888d23736cec51ba851f6e798d0eeb9ef5f41) + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pci/host/pcie-rcar.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pci/host/pcie-rcar.c ++++ b/drivers/pci/host/pcie-rcar.c +@@ -1165,7 +1165,7 @@ static int rcar_pcie_probe(struct platfo + err = hw_init_fn(pcie); + if (err) { + dev_info(dev, "PCIe link down\n"); +- err = 0; ++ err = -ENODEV; + goto err_pm_put; + } + diff --git a/patches.renesas/0102-PCI-rcar-Add-compatible-string-for-r8a7796.patch b/patches.renesas/0102-PCI-rcar-Add-compatible-string-for-r8a7796.patch new file mode 100644 index 0000000000000..b65dcf0a53818 --- /dev/null +++ b/patches.renesas/0102-PCI-rcar-Add-compatible-string-for-r8a7796.patch @@ -0,0 +1,29 @@ +From 5b0a75f9115dc0c2e0a7520ed306015ea1302540 Mon Sep 17 00:00:00 2001 +From: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> +Date: Wed, 21 Dec 2016 03:37:06 +0900 +Subject: [PATCH 102/255] PCI: rcar: Add compatible string for r8a7796 + +Add support for r8a7796. + +Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> +Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> +Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Rob Herring <robh@kernel.org> +(cherry picked from commit 8267b07526cabe2e2afc834a138ece8644af87ed) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 + + 1 file changed, 1 insertion(+) + +--- a/Documentation/devicetree/bindings/pci/rcar-pci.txt ++++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt +@@ -6,6 +6,7 @@ compatible: "renesas,pcie-r8a7779" for t + "renesas,pcie-r8a7791" for the R8A7791 SoC; + "renesas,pcie-r8a7793" for the R8A7793 SoC; + "renesas,pcie-r8a7795" for the R8A7795 SoC; ++ "renesas,pcie-r8a7796" for the R8A7796 SoC; + "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device. + "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device. + diff --git a/patches.renesas/0103-PCI-rcar-Use-of_device_get_match_data-to-simplify-pr.patch b/patches.renesas/0103-PCI-rcar-Use-of_device_get_match_data-to-simplify-pr.patch new file mode 100644 index 0000000000000..02703bbb32009 --- /dev/null +++ b/patches.renesas/0103-PCI-rcar-Use-of_device_get_match_data-to-simplify-pr.patch @@ -0,0 +1,57 @@ +From 7719ec7e0ca111c8af43e71e64ee98c33b6daac5 Mon Sep 17 00:00:00 2001 +From: Bjorn Helgaas <bhelgaas@google.com> +Date: Tue, 31 Jan 2017 16:35:42 -0600 +Subject: [PATCH 103/255] PCI: rcar: Use of_device_get_match_data() to simplify + probe + +This is a DT-only driver, so the only way to call rcar_pcie_probe() is to +match an entry in rcar_pcie_of_match[], so of_id cannot be NULL. + +Furthermore, of_id->data can only be NULL if an rcar_pcie_of_match[] entry +has a NULL .data member. That's a driver defect, and we don't want to +return -EINVAL, which is easy to ignore. We'd rather take the NULL pointer +dereference so we notice the problem and fix it. + +Use of_device_get_match_data() to retrieve the hw_init_fn pointer. No +functional change intended. + +Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ff1677e231651205e7e19770a677057dea05cb70) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pci/host/pcie-rcar.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +--- a/drivers/pci/host/pcie-rcar.c ++++ b/drivers/pci/host/pcie-rcar.c +@@ -1125,7 +1125,6 @@ static int rcar_pcie_probe(struct platfo + struct device *dev = &pdev->dev; + struct rcar_pcie *pcie; + unsigned int data; +- const struct of_device_id *of_id; + int err; + int (*hw_init_fn)(struct rcar_pcie *); + +@@ -1149,11 +1148,6 @@ static int rcar_pcie_probe(struct platfo + if (err) + return err; + +- of_id = of_match_device(rcar_pcie_of_match, dev); +- if (!of_id || !of_id->data) +- return -EINVAL; +- hw_init_fn = of_id->data; +- + pm_runtime_enable(dev); + err = pm_runtime_get_sync(dev); + if (err < 0) { +@@ -1162,6 +1156,7 @@ static int rcar_pcie_probe(struct platfo + } + + /* Failure to get a link might just be that no cards are inserted */ ++ hw_init_fn = of_device_get_match_data(dev); + err = hw_init_fn(pcie); + if (err) { + dev_info(dev, "PCIe link down\n"); diff --git a/patches.renesas/0104-net-phy-micrel-fix-crash-when-statistic-requested-fo.patch b/patches.renesas/0104-net-phy-micrel-fix-crash-when-statistic-requested-fo.patch new file mode 100644 index 0000000000000..48f3b5c61634f --- /dev/null +++ b/patches.renesas/0104-net-phy-micrel-fix-crash-when-statistic-requested-fo.patch @@ -0,0 +1,112 @@ +From 4ed77a4318233c728d3dd110c065a2ce24c69131 Mon Sep 17 00:00:00 2001 +From: Grygorii Strashko <grygorii.strashko@ti.com> +Date: Thu, 13 Apr 2017 14:11:27 -0500 +Subject: [PATCH 104/255] net: phy: micrel: fix crash when statistic requested + for KSZ9031 phy + +Now the command: + ethtool --phy-statistics eth0 +will cause system crash with meassage "Unable to handle kernel NULL pointer +dereference at virtual address 00000010" from: + + (kszphy_get_stats) from [<c069f1d8>] (ethtool_get_phy_stats+0xd8/0x210) + (ethtool_get_phy_stats) from [<c06a0738>] (dev_ethtool+0x5b8/0x228c) + (dev_ethtool) from [<c06b5484>] (dev_ioctl+0x3fc/0x964) + (dev_ioctl) from [<c0679f7c>] (sock_ioctl+0x170/0x2c0) + (sock_ioctl) from [<c02419d4>] (do_vfs_ioctl+0xa8/0x95c) + (do_vfs_ioctl) from [<c02422c4>] (SyS_ioctl+0x3c/0x64) + (SyS_ioctl) from [<c0107d60>] (ret_fast_syscall+0x0/0x44) + +The reason: phy_driver structure for KSZ9031 phy has no .probe() callback +defined. As result, struct phy_device *phydev->priv pointer will not be +initializes (null). +This issue will affect also following phys: + KSZ8795, KSZ886X, KSZ8873MLL, KSZ9031, KSZ9021, KSZ8061, KS8737 + +Fix it by: +- adding .probe() = kszphy_probe() callback to KSZ9031, KSZ9021 +phys. The kszphy_probe() can be re-used as it doesn't do any phy specific +settings. +- removing statistic callbacks from other phys (KSZ8795, KSZ886X, +KSZ8873MLL, KSZ8061, KS8737) as they doesn't have corresponding +statistic counters. + +Fixes: 2b2427d06426 ("phy: micrel: Add ethtool statistics counters") +Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> +Reviewed-by: Andrew Lunn <andrew@lunn.ch> +Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit bfe72442578bb112626e476ffe1f276504d85b95) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/phy/micrel.c | 17 ++--------------- + 1 file changed, 2 insertions(+), 15 deletions(-) + +--- a/drivers/net/phy/micrel.c ++++ b/drivers/net/phy/micrel.c +@@ -800,9 +800,6 @@ static struct phy_driver ksphy_driver[] + .read_status = genphy_read_status, + .ack_interrupt = kszphy_ack_interrupt, + .config_intr = kszphy_config_intr, +- .get_sset_count = kszphy_get_sset_count, +- .get_strings = kszphy_get_strings, +- .get_stats = kszphy_get_stats, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { +@@ -942,9 +939,6 @@ static struct phy_driver ksphy_driver[] + .read_status = genphy_read_status, + .ack_interrupt = kszphy_ack_interrupt, + .config_intr = kszphy_config_intr, +- .get_sset_count = kszphy_get_sset_count, +- .get_strings = kszphy_get_strings, +- .get_stats = kszphy_get_stats, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { +@@ -954,6 +948,7 @@ static struct phy_driver ksphy_driver[] + .features = PHY_GBIT_FEATURES, + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, + .driver_data = &ksz9021_type, ++ .probe = kszphy_probe, + .config_init = ksz9021_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, +@@ -973,6 +968,7 @@ static struct phy_driver ksphy_driver[] + .features = PHY_GBIT_FEATURES, + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, + .driver_data = &ksz9021_type, ++ .probe = kszphy_probe, + .config_init = ksz9031_config_init, + .config_aneg = genphy_config_aneg, + .read_status = ksz9031_read_status, +@@ -991,9 +987,6 @@ static struct phy_driver ksphy_driver[] + .config_init = kszphy_config_init, + .config_aneg = ksz8873mll_config_aneg, + .read_status = ksz8873mll_read_status, +- .get_sset_count = kszphy_get_sset_count, +- .get_strings = kszphy_get_strings, +- .get_stats = kszphy_get_stats, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { +@@ -1005,9 +998,6 @@ static struct phy_driver ksphy_driver[] + .config_init = kszphy_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, +- .get_sset_count = kszphy_get_sset_count, +- .get_strings = kszphy_get_strings, +- .get_stats = kszphy_get_stats, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { +@@ -1019,9 +1009,6 @@ static struct phy_driver ksphy_driver[] + .config_init = kszphy_config_init, + .config_aneg = ksz8873mll_config_aneg, + .read_status = ksz8873mll_read_status, +- .get_sset_count = kszphy_get_sset_count, +- .get_strings = kszphy_get_strings, +- .get_stats = kszphy_get_stats, + .suspend = genphy_suspend, + .resume = genphy_resume, + } }; diff --git a/patches.renesas/0105-Revert-phy-micrel-Disable-auto-negotiation-on-startu.patch b/patches.renesas/0105-Revert-phy-micrel-Disable-auto-negotiation-on-startu.patch new file mode 100644 index 0000000000000..6d1264efd3900 --- /dev/null +++ b/patches.renesas/0105-Revert-phy-micrel-Disable-auto-negotiation-on-startu.patch @@ -0,0 +1,39 @@ +From 966c476ad2b363ea14edb8e9050412b875397774 Mon Sep 17 00:00:00 2001 +From: "David S. Miller" <davem@davemloft.net> +Date: Wed, 26 Apr 2017 14:33:14 -0400 +Subject: [PATCH 105/255] Revert "phy: micrel: Disable auto negotiation on + startup" + +This reverts commit 99f81afc139c6edd14d77a91ee91685a414a1c66. + +It was papering over the real problem, which is fixed by commit +f555f34fdc58 ("net: phy: fix auto-negotiation stall due to unavailable +interrupt") + +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit b43bd72835a5f7adef81fe53fa1fbe7b0e43df8e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/phy/micrel.c | 11 ----------- + 1 file changed, 11 deletions(-) + +--- a/drivers/net/phy/micrel.c ++++ b/drivers/net/phy/micrel.c +@@ -297,17 +297,6 @@ static int kszphy_config_init(struct phy + if (priv->led_mode >= 0) + kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode); + +- if (phy_interrupt_is_valid(phydev)) { +- int ctl = phy_read(phydev, MII_BMCR); +- +- if (ctl < 0) +- return ctl; +- +- ret = phy_write(phydev, MII_BMCR, ctl & ~BMCR_ANENABLE); +- if (ret < 0) +- return ret; +- } +- + return 0; + } + diff --git a/patches.renesas/0106-phy-rcar-gen3-usb2-Replace-the-deprecated-extcon-API.patch b/patches.renesas/0106-phy-rcar-gen3-usb2-Replace-the-deprecated-extcon-API.patch new file mode 100644 index 0000000000000..abf570b141250 --- /dev/null +++ b/patches.renesas/0106-phy-rcar-gen3-usb2-Replace-the-deprecated-extcon-API.patch @@ -0,0 +1,36 @@ +From d1e2af75c79e808aa5e3ab142a97bb90fc3bdbdb Mon Sep 17 00:00:00 2001 +From: Chanwoo Choi <cw00.choi@samsung.com> +Date: Fri, 30 Dec 2016 13:11:28 +0900 +Subject: [PATCH 106/255] phy: rcar-gen3-usb2: Replace the deprecated extcon + API + +This patch replaces the deprecated extcon API as following: +- extcon_set_cable_state_() -> extcon_set_state_sync() + +Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> +Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> +(cherry picked from commit c6f30a5b8eaa4b4421989ef1e788db30a1f2e142) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/phy/phy-rcar-gen3-usb2.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/phy/phy-rcar-gen3-usb2.c ++++ b/drivers/phy/phy-rcar-gen3-usb2.c +@@ -94,11 +94,11 @@ static void rcar_gen3_phy_usb2_work(stru + work); + + if (ch->extcon_host) { +- extcon_set_cable_state_(ch->extcon, EXTCON_USB_HOST, true); +- extcon_set_cable_state_(ch->extcon, EXTCON_USB, false); ++ extcon_set_state_sync(ch->extcon, EXTCON_USB_HOST, true); ++ extcon_set_state_sync(ch->extcon, EXTCON_USB, false); + } else { +- extcon_set_cable_state_(ch->extcon, EXTCON_USB_HOST, false); +- extcon_set_cable_state_(ch->extcon, EXTCON_USB, true); ++ extcon_set_state_sync(ch->extcon, EXTCON_USB_HOST, false); ++ extcon_set_state_sync(ch->extcon, EXTCON_USB, true); + } + } + diff --git a/patches.renesas/0107-can-rcar_can-Do-not-print-virtual-addresses.patch b/patches.renesas/0107-can-rcar_can-Do-not-print-virtual-addresses.patch new file mode 100644 index 0000000000000..3980a980a7f78 --- /dev/null +++ b/patches.renesas/0107-can-rcar_can-Do-not-print-virtual-addresses.patch @@ -0,0 +1,35 @@ +From f7b7695a93d8e1a605721f3deaa6b09dc472192f Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 3 Apr 2017 12:11:26 +0200 +Subject: [PATCH 107/255] can: rcar_can: Do not print virtual addresses + +During probe, the rcar_can driver prints: + + rcar_can e6e80000.can: device registered (regs @ e08bc000, IRQ76) + +The "regs" value is a virtual address, exposing internal information, +hence stop printing it. The (useful) physical address is already +printed as part of the device name. + +Fixes: fd1159318e55e901 ("can: add Renesas R-Car CAN driver") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> +(cherry picked from commit ca257b9e2d807ab6cb2678ecc7b74aaf4651f597) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/can/rcar/rcar_can.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/net/can/rcar/rcar_can.c ++++ b/drivers/net/can/rcar/rcar_can.c +@@ -826,8 +826,7 @@ static int rcar_can_probe(struct platfor + + devm_can_led_init(ndev); + +- dev_info(&pdev->dev, "device registered (regs @ %p, IRQ%d)\n", +- priv->regs, ndev->irq); ++ dev_info(&pdev->dev, "device registered (IRQ%d)\n", ndev->irq); + + return 0; + fail_candev: diff --git a/patches.renesas/0108-dmaengine-rcar-dmac-Widen-DMA-mask-to-40-bits.patch b/patches.renesas/0108-dmaengine-rcar-dmac-Widen-DMA-mask-to-40-bits.patch new file mode 100644 index 0000000000000..8ebe149447814 --- /dev/null +++ b/patches.renesas/0108-dmaengine-rcar-dmac-Widen-DMA-mask-to-40-bits.patch @@ -0,0 +1,30 @@ +From e5ec9c4d40d011885447f89d80214b2c72ae854d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 13 Feb 2017 12:00:26 +0100 +Subject: [PATCH 108/255] dmaengine: rcar-dmac: Widen DMA mask to 40 bits + +By default, the DMA mask covers only the low 32-bit address space, which +causes SWIOTLB on arm64 to fall back to a bounce buffer for DMA +transfers involving memory outside the 32-bit address space. + +The R-Car DMA controller hardware supports a 40-bit address space, hence +widen the DMA mask to 40 bits to actually make use of this feature. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Vinod Koul <vinod.koul@intel.com> +(cherry picked from commit dc312349e87526dfe6387c1a82fafded706f0572) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/dma/sh/rcar-dmac.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/dma/sh/rcar-dmac.c ++++ b/drivers/dma/sh/rcar-dmac.c +@@ -1724,6 +1724,7 @@ static int rcar_dmac_probe(struct platfo + + dmac->dev = &pdev->dev; + platform_set_drvdata(pdev, dmac); ++ dma_set_mask_and_coherent(dmac->dev, DMA_BIT_MASK(40)); + + ret = rcar_dmac_parse_of(&pdev->dev, dmac); + if (ret < 0) diff --git a/patches.renesas/0109-media-v4l-vsp1-Adapt-vsp1_du_setup_lif-interface-to-.patch b/patches.renesas/0109-media-v4l-vsp1-Adapt-vsp1_du_setup_lif-interface-to-.patch new file mode 100644 index 0000000000000..88b9d94f0dea3 --- /dev/null +++ b/patches.renesas/0109-media-v4l-vsp1-Adapt-vsp1_du_setup_lif-interface-to-.patch @@ -0,0 +1,165 @@ +From dceaa86e92c24794bb5a4043686129d4774d6d60 Mon Sep 17 00:00:00 2001 +From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Date: Fri, 3 Mar 2017 06:31:48 -0300 +Subject: [PATCH 109/255] [media] v4l: vsp1: Adapt vsp1_du_setup_lif() + interface to use a structure + +The interface to configure the LIF in the VSP1 requires adapting the +function prototype for any changes. This makes extending the interface +difficult. + +Change the function prototype to pass a structure which can be easily +extended. + +This changes the means of disabling the pipeline, by now passing a NULL +configuration rather than passing either a 0 width or height. + +[Fixed kerneldoc, made vsp1_du_setup_lif() cfg argument const] + +Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Dave Airlie <airlied@redhat.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 8c71fff434e5ecf5ff27bd61db1bc9ac4c2b2a1b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 8 ++++++-- + drivers/media/platform/vsp1/vsp1_drm.c | 33 ++++++++++++++++----------------- + include/media/vsp1.h | 13 +++++++++++-- + 3 files changed, 33 insertions(+), 21 deletions(-) + +--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c +@@ -32,6 +32,10 @@ void rcar_du_vsp_enable(struct rcar_du_c + { + const struct drm_display_mode *mode = &crtc->crtc.state->adjusted_mode; + struct rcar_du_device *rcdu = crtc->group->dev; ++ struct vsp1_du_lif_config cfg = { ++ .width = mode->hdisplay, ++ .height = mode->vdisplay, ++ }; + struct rcar_du_plane_state state = { + .state = { + .crtc = &crtc->crtc, +@@ -66,12 +70,12 @@ void rcar_du_vsp_enable(struct rcar_du_c + */ + crtc->group->need_restart = true; + +- vsp1_du_setup_lif(crtc->vsp->vsp, mode->hdisplay, mode->vdisplay); ++ vsp1_du_setup_lif(crtc->vsp->vsp, &cfg); + } + + void rcar_du_vsp_disable(struct rcar_du_crtc *crtc) + { +- vsp1_du_setup_lif(crtc->vsp->vsp, 0, 0); ++ vsp1_du_setup_lif(crtc->vsp->vsp, NULL); + } + + void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc) +--- a/drivers/media/platform/vsp1/vsp1_drm.c ++++ b/drivers/media/platform/vsp1/vsp1_drm.c +@@ -54,12 +54,11 @@ EXPORT_SYMBOL_GPL(vsp1_du_init); + /** + * vsp1_du_setup_lif - Setup the output part of the VSP pipeline + * @dev: the VSP device +- * @width: output frame width in pixels +- * @height: output frame height in pixels ++ * @cfg: the LIF configuration + * +- * Configure the output part of VSP DRM pipeline for the given frame @width and +- * @height. This sets up formats on the BRU source pad, the WPF0 sink and source +- * pads, and the LIF sink pad. ++ * Configure the output part of VSP DRM pipeline for the given frame @cfg.width ++ * and @cfg.height. This sets up formats on the BRU source pad, the WPF0 sink ++ * and source pads, and the LIF sink pad. + * + * As the media bus code on the BRU source pad is conditioned by the + * configuration of the BRU sink 0 pad, we also set up the formats on all BRU +@@ -69,8 +68,7 @@ EXPORT_SYMBOL_GPL(vsp1_du_init); + * + * Return 0 on success or a negative error code on failure. + */ +-int vsp1_du_setup_lif(struct device *dev, unsigned int width, +- unsigned int height) ++int vsp1_du_setup_lif(struct device *dev, const struct vsp1_du_lif_config *cfg) + { + struct vsp1_device *vsp1 = dev_get_drvdata(dev); + struct vsp1_pipeline *pipe = &vsp1->drm->pipe; +@@ -79,11 +77,8 @@ int vsp1_du_setup_lif(struct device *dev + unsigned int i; + int ret; + +- dev_dbg(vsp1->dev, "%s: configuring LIF with format %ux%u\n", +- __func__, width, height); +- +- if (width == 0 || height == 0) { +- /* Zero width or height means the CRTC is being disabled, stop ++ if (!cfg) { ++ /* NULL configuration means the CRTC is being disabled, stop + * the pipeline and turn the light off. + */ + ret = vsp1_pipeline_stop(pipe); +@@ -108,6 +103,9 @@ int vsp1_du_setup_lif(struct device *dev + return 0; + } + ++ dev_dbg(vsp1->dev, "%s: configuring LIF with format %ux%u\n", ++ __func__, cfg->width, cfg->height); ++ + /* Configure the format at the BRU sinks and propagate it through the + * pipeline. + */ +@@ -117,8 +115,8 @@ int vsp1_du_setup_lif(struct device *dev + for (i = 0; i < bru->entity.source_pad; ++i) { + format.pad = i; + +- format.format.width = width; +- format.format.height = height; ++ format.format.width = cfg->width; ++ format.format.height = cfg->height; + format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32; + format.format.field = V4L2_FIELD_NONE; + +@@ -133,8 +131,8 @@ int vsp1_du_setup_lif(struct device *dev + } + + format.pad = bru->entity.source_pad; +- format.format.width = width; +- format.format.height = height; ++ format.format.width = cfg->width; ++ format.format.height = cfg->height; + format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32; + format.format.field = V4L2_FIELD_NONE; + +@@ -180,7 +178,8 @@ int vsp1_du_setup_lif(struct device *dev + /* Verify that the format at the output of the pipeline matches the + * requested frame size and media bus code. + */ +- if (format.format.width != width || format.format.height != height || ++ if (format.format.width != cfg->width || ++ format.format.height != cfg->height || + format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) { + dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__); + return -EPIPE; +--- a/include/media/vsp1.h ++++ b/include/media/vsp1.h +@@ -20,8 +20,17 @@ struct device; + + int vsp1_du_init(struct device *dev); + +-int vsp1_du_setup_lif(struct device *dev, unsigned int width, +- unsigned int height); ++/** ++ * struct vsp1_du_lif_config - VSP LIF configuration ++ * @width: output frame width ++ * @height: output frame height ++ */ ++struct vsp1_du_lif_config { ++ unsigned int width; ++ unsigned int height; ++}; ++ ++int vsp1_du_setup_lif(struct device *dev, const struct vsp1_du_lif_config *cfg); + + struct vsp1_du_atomic_config { + u32 pixelformat; diff --git a/patches.renesas/0110-media-v4l-rcar_fdp1-use-4.4s-to-format-a-4-byte-stri.patch b/patches.renesas/0110-media-v4l-rcar_fdp1-use-4.4s-to-format-a-4-byte-stri.patch new file mode 100644 index 0000000000000..290dc6f4fa950 --- /dev/null +++ b/patches.renesas/0110-media-v4l-rcar_fdp1-use-4.4s-to-format-a-4-byte-stri.patch @@ -0,0 +1,43 @@ +From d58f0edde79809384658d35ae052517a22486b08 Mon Sep 17 00:00:00 2001 +From: Nicolas Iooss <nicolas.iooss_linux@m4x.org> +Date: Mon, 26 Dec 2016 11:31:39 -0200 +Subject: [PATCH 110/255] [media] v4l: rcar_fdp1: use %4.4s to format a 4-byte + string + +Using %4s to format f->fmt.pix_mp.pixelformat in fdp1_try_fmt() and +fdp1_s_fmt() may lead to more characters being printed (when the byte +following field pixelformat is not zero). + +Add ".4" to the format specifier to limit the number of printed +characters to four. The resulting format specifier "%4.4s" is also used +by other media drivers to print pixelformat value. + +Signed-off-by: Nicolas Iooss <nicolas.iooss_linux@m4x.org> +Reviewed-by: Kieran Bingham <kieran@bingham.xyz> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 4c171636bc2beca81b25b07fbe4ac2a6ab27f982) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/rcar_fdp1.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/media/platform/rcar_fdp1.c ++++ b/drivers/media/platform/rcar_fdp1.c +@@ -1596,7 +1596,7 @@ static int fdp1_try_fmt(struct file *fil + else + fdp1_try_fmt_capture(ctx, NULL, &f->fmt.pix_mp); + +- dprintk(ctx->fdp1, "Try %s format: %4s (0x%08x) %ux%u field %u\n", ++ dprintk(ctx->fdp1, "Try %s format: %4.4s (0x%08x) %ux%u field %u\n", + V4L2_TYPE_IS_OUTPUT(f->type) ? "output" : "capture", + (char *)&f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.pixelformat, + f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.field); +@@ -1671,7 +1671,7 @@ static int fdp1_s_fmt(struct file *file, + + fdp1_set_format(ctx, &f->fmt.pix_mp, f->type); + +- dprintk(ctx->fdp1, "Set %s format: %4s (0x%08x) %ux%u field %u\n", ++ dprintk(ctx->fdp1, "Set %s format: %4.4s (0x%08x) %ux%u field %u\n", + V4L2_TYPE_IS_OUTPUT(f->type) ? "output" : "capture", + (char *)&f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.pixelformat, + f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.field); diff --git a/patches.renesas/0111-iio-adc-Add-Renesas-GyroADC-bindings.patch b/patches.renesas/0111-iio-adc-Add-Renesas-GyroADC-bindings.patch new file mode 100644 index 0000000000000..86235a1dcd14b --- /dev/null +++ b/patches.renesas/0111-iio-adc-Add-Renesas-GyroADC-bindings.patch @@ -0,0 +1,128 @@ +From f6623987f1a47c73cd2ba222dcda7a108f5d9aed Mon Sep 17 00:00:00 2001 +From: Marek Vasut <marek.vasut+renesas@gmail.com> +Date: Sat, 28 Jan 2017 00:08:36 +0100 +Subject: [PATCH 111/255] iio: adc: Add Renesas GyroADC bindings + +Add DT bindings for the Renesas RCar GyroADC block. This block is +a simple 4/8-channel ADC which samples 12/15/24 bits of data every +cycle from all channels. + +Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> +Cc: Geert Uytterhoeven <geert+renesas@glider.be> +Cc: Simon Horman <horms+renesas@verge.net.au> +Cc: Jonathan Cameron <jic23@kernel.org> +Cc: linux-renesas-soc@vger.kernel.org +Cc: Wolfram Sang <wsa@the-dreams.de> +Cc: Rob Herring <robh@kernel.org> +Acked-by: Rob Herring <robh@kernel.org> +Cc: devicetree@vger.kernel.org +Signed-off-by: Jonathan Cameron <jic23@kernel.org> +(cherry picked from commit ec2ef15335547d6b96dcfb92e2dcebe08e156bc2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt | 99 ++++++++++ + 1 file changed, 99 insertions(+) + create mode 100644 Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt +@@ -0,0 +1,99 @@ ++* Renesas RCar GyroADC device driver ++ ++The GyroADC block is a reduced SPI block with up to 8 chipselect lines, ++which supports the SPI protocol of a selected few SPI ADCs. The SPI ADCs ++are sampled by the GyroADC block in a round-robin fashion and the result ++presented in the GyroADC registers. ++ ++Required properties: ++- compatible: Should be "<soc-specific>", "renesas,rcar-gyroadc". ++ The <soc-specific> should be one of: ++ renesas,r8a7791-gyroadc - for the GyroADC block present ++ in r8a7791 SoC ++ renesas,r8a7792-gyroadc - for the GyroADC with interrupt ++ block present in r8a7792 SoC ++- reg: Address and length of the register set for the device ++- clocks: References to all the clocks specified in the clock-names ++ property as specified in ++ Documentation/devicetree/bindings/clock/clock-bindings.txt. ++- clock-names: Shall contain "fck" and "if". The "fck" is the GyroADC block ++ clock, the "if" is the interface clock. ++- power-domains: Must contain a reference to the PM domain, if available. ++- #address-cells: Should be <1> (setting for the subnodes) for all ADCs ++ except for "fujitsu,mb88101a". Should be <0> (setting for ++ only subnode) for "fujitsu,mb88101a". ++- #size-cells: Should be <0> (setting for the subnodes) ++ ++Sub-nodes: ++You must define subnode(s) which select the connected ADC type and reference ++voltage for the GyroADC channels. ++ ++Required properties for subnodes: ++- compatible: Should be either of: ++ "fujitsu,mb88101a" ++ - Fujitsu MB88101A compatible mode, ++ 12bit sampling, up to 4 channels can be sampled in ++ round-robin fashion. One Fujitsu chip supplies four ++ GyroADC channels with data as it contains four ADCs ++ on the chip and thus for 4-channel operation, single ++ MB88101A is required. The Cx chipselect lines of the ++ MB88101A connect directly to two CHS lines of the ++ GyroADC, no demuxer is required. The data out line ++ of each MB88101A connects to a shared input pin of ++ the GyroADC. ++ "ti,adcs7476" or "ti,adc121" or "adi,ad7476" ++ - TI ADCS7476 / TI ADC121 / ADI AD7476 compatible mode, ++ 15bit sampling, up to 8 channels can be sampled in ++ round-robin fashion. One TI/ADI chip supplies single ++ ADC channel with data, thus for 8-channel operation, ++ 8 chips are required. A 3:8 chipselect demuxer is ++ required to connect the nCS line of the TI/ADI chips ++ to the GyroADC, while MISO line of each TI/ADI ADC ++ connects to a shared input pin of the GyroADC. ++ "maxim,max1162" or "maxim,max11100" ++ - Maxim MAX1162 / Maxim MAX11100 compatible mode, ++ 16bit sampling, up to 8 channels can be sampled in ++ round-robin fashion. One Maxim chip supplies single ++ ADC channel with data, thus for 8-channel operation, ++ 8 chips are required. A 3:8 chipselect demuxer is ++ required to connect the nCS line of the MAX chips ++ to the GyroADC, while MISO line of each Maxim ADC ++ connects to a shared input pin of the GyroADC. ++- reg: Should be the number of the analog input. Should be present ++ for all ADCs except "fujitsu,mb88101a". ++- vref-supply: Reference to the channel reference voltage regulator. ++ ++Example: ++ vref_max1162: regulator-vref-max1162 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "MAX1162 Vref"; ++ regulator-min-microvolt = <4096000>; ++ regulator-max-microvolt = <4096000>; ++ }; ++ ++ adc@e6e54000 { ++ compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; ++ reg = <0 0xe6e54000 0 64>; ++ clocks = <&mstp9_clks R8A7791_CLK_GYROADC>, <&clk_65m>; ++ clock-names = "fck", "if"; ++ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; ++ ++ pinctrl-0 = <&adc_pins>; ++ pinctrl-names = "default"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ adc@0 { ++ reg = <0>; ++ compatible = "maxim,max1162"; ++ vref-supply = <&vref_max1162>; ++ }; ++ ++ adc@1 { ++ reg = <1>; ++ compatible = "maxim,max1162"; ++ vref-supply = <&vref_max1162>; ++ }; ++ }; diff --git a/patches.renesas/0112-iio-adc-Add-Renesas-GyroADC-driver.patch b/patches.renesas/0112-iio-adc-Add-Renesas-GyroADC-driver.patch new file mode 100644 index 0000000000000..0443039d95371 --- /dev/null +++ b/patches.renesas/0112-iio-adc-Add-Renesas-GyroADC-driver.patch @@ -0,0 +1,707 @@ +From 52dc4fbaf3f5b42ab0faa58ca2866523a5bccb6f Mon Sep 17 00:00:00 2001 +From: Marek Vasut <marek.vasut+renesas@gmail.com> +Date: Sat, 28 Jan 2017 00:08:37 +0100 +Subject: [PATCH 112/255] iio: adc: Add Renesas GyroADC driver + +Add IIO driver for the Renesas RCar GyroADC block. This block is a +simple 4/8-channel ADC which samples 12/15/24 bits of data every +cycle from all channels. + +Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> +Cc: Geert Uytterhoeven <geert+renesas@glider.be> +Cc: Simon Horman <horms+renesas@verge.net.au> +Cc: Jonathan Cameron <jic23@kernel.org> +Cc: linux-renesas-soc@vger.kernel.org +Cc: Wolfram Sang <wsa@the-dreams.de> +Signed-off-by: Jonathan Cameron <jic23@kernel.org> +(cherry picked from commit 059c53b3232960cfd38cc46de0a7bedd642021f5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + MAINTAINERS | 6 + drivers/iio/adc/Kconfig | 13 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/rcar-gyroadc.c | 631 +++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 651 insertions(+) + create mode 100644 drivers/iio/adc/rcar-gyroadc.c + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -10225,6 +10225,12 @@ L: linux-renesas-soc@vger.kernel.org + F: drivers/net/ethernet/renesas/ + F: include/linux/sh_eth.h + ++RENESAS R-CAR GYROADC DRIVER ++M: Marek Vasut <marek.vasut@gmail.com> ++L: linux-iio@vger.kernel.org ++S: Supported ++F: drivers/iio/adc/rcar_gyro_adc.c ++ + RENESAS USB2 PHY DRIVER + M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> + L: linux-renesas-soc@vger.kernel.org +--- a/drivers/iio/adc/Kconfig ++++ b/drivers/iio/adc/Kconfig +@@ -408,6 +408,19 @@ config QCOM_SPMI_VADC + To compile this driver as a module, choose M here: the module will + be called qcom-spmi-vadc. + ++config RCAR_GYRO_ADC ++ tristate "Renesas R-Car GyroADC driver" ++ depends on ARCH_RCAR_GEN2 || (ARM && COMPILE_TEST) ++ help ++ Say yes here to build support for the GyroADC found in Renesas ++ R-Car Gen2 SoCs. This block is a simple SPI offload engine for ++ reading data out of attached compatible ADCs in a round-robin ++ fashion. Up to 4 or 8 ADC channels are supported by this block, ++ depending on which ADCs are attached. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called rcar-gyroadc. ++ + config ROCKCHIP_SARADC + tristate "Rockchip SARADC driver" + depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST) +--- a/drivers/iio/adc/Makefile ++++ b/drivers/iio/adc/Makefile +@@ -39,6 +39,7 @@ obj-$(CONFIG_NAU7802) += nau7802.o + obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o + obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o + obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o ++obj-$(CONFIG_RCAR_GYRO_ADC) += rcar-gyroadc.o + obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o + obj-$(CONFIG_STX104) += stx104.o + obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o +--- /dev/null ++++ b/drivers/iio/adc/rcar-gyroadc.c +@@ -0,0 +1,631 @@ ++/* ++ * Renesas R-Car GyroADC driver ++ * ++ * Copyright 2016 Marek Vasut <marek.vasut@gmail.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <linux/module.h> ++#include <linux/platform_device.h> ++#include <linux/delay.h> ++#include <linux/kernel.h> ++#include <linux/slab.h> ++#include <linux/io.h> ++#include <linux/clk.h> ++#include <linux/of.h> ++#include <linux/of_irq.h> ++#include <linux/regulator/consumer.h> ++#include <linux/of_platform.h> ++#include <linux/err.h> ++#include <linux/pm_runtime.h> ++ ++#include <linux/iio/iio.h> ++#include <linux/iio/sysfs.h> ++#include <linux/iio/trigger.h> ++ ++#define DRIVER_NAME "rcar-gyroadc" ++ ++/* GyroADC registers. */ ++#define RCAR_GYROADC_MODE_SELECT 0x00 ++#define RCAR_GYROADC_MODE_SELECT_1_MB88101A 0x0 ++#define RCAR_GYROADC_MODE_SELECT_2_ADCS7476 0x1 ++#define RCAR_GYROADC_MODE_SELECT_3_MAX1162 0x3 ++ ++#define RCAR_GYROADC_START_STOP 0x04 ++#define RCAR_GYROADC_START_STOP_START BIT(0) ++ ++#define RCAR_GYROADC_CLOCK_LENGTH 0x08 ++#define RCAR_GYROADC_1_25MS_LENGTH 0x0c ++ ++#define RCAR_GYROADC_REALTIME_DATA(ch) (0x10 + ((ch) * 4)) ++#define RCAR_GYROADC_100MS_ADDED_DATA(ch) (0x30 + ((ch) * 4)) ++#define RCAR_GYROADC_10MS_AVG_DATA(ch) (0x50 + ((ch) * 4)) ++ ++#define RCAR_GYROADC_FIFO_STATUS 0x70 ++#define RCAR_GYROADC_FIFO_STATUS_EMPTY(ch) BIT(0 + (4 * (ch))) ++#define RCAR_GYROADC_FIFO_STATUS_FULL(ch) BIT(1 + (4 * (ch))) ++#define RCAR_GYROADC_FIFO_STATUS_ERROR(ch) BIT(2 + (4 * (ch))) ++ ++#define RCAR_GYROADC_INTR 0x74 ++#define RCAR_GYROADC_INTR_INT BIT(0) ++ ++#define RCAR_GYROADC_INTENR 0x78 ++#define RCAR_GYROADC_INTENR_INTEN BIT(0) ++ ++#define RCAR_GYROADC_SAMPLE_RATE 800 /* Hz */ ++ ++#define RCAR_GYROADC_RUNTIME_PM_DELAY_MS 2000 ++ ++enum rcar_gyroadc_model { ++ RCAR_GYROADC_MODEL_DEFAULT, ++ RCAR_GYROADC_MODEL_R8A7792, ++}; ++ ++struct rcar_gyroadc { ++ struct device *dev; ++ void __iomem *regs; ++ struct clk *iclk; ++ struct regulator *vref[8]; ++ unsigned int num_channels; ++ enum rcar_gyroadc_model model; ++ unsigned int mode; ++ unsigned int sample_width; ++}; ++ ++static void rcar_gyroadc_hw_init(struct rcar_gyroadc *priv) ++{ ++ const unsigned long clk_mhz = clk_get_rate(priv->iclk) / 1000000; ++ const unsigned long clk_mul = ++ (priv->mode == RCAR_GYROADC_MODE_SELECT_1_MB88101A) ? 10 : 5; ++ unsigned long clk_len = clk_mhz * clk_mul; ++ ++ /* ++ * According to the R-Car Gen2 datasheet Rev. 1.01, Sept 08 2014, ++ * page 77-7, clock length must be even number. If it's odd number, ++ * add one. ++ */ ++ if (clk_len & 1) ++ clk_len++; ++ ++ /* Stop the GyroADC. */ ++ writel(0, priv->regs + RCAR_GYROADC_START_STOP); ++ ++ /* Disable IRQ on V2H. */ ++ if (priv->model == RCAR_GYROADC_MODEL_R8A7792) ++ writel(0, priv->regs + RCAR_GYROADC_INTENR); ++ ++ /* Set mode and timing. */ ++ writel(priv->mode, priv->regs + RCAR_GYROADC_MODE_SELECT); ++ writel(clk_len, priv->regs + RCAR_GYROADC_CLOCK_LENGTH); ++ writel(clk_mhz * 1250, priv->regs + RCAR_GYROADC_1_25MS_LENGTH); ++} ++ ++static void rcar_gyroadc_hw_start(struct rcar_gyroadc *priv) ++{ ++ /* Start sampling. */ ++ writel(RCAR_GYROADC_START_STOP_START, ++ priv->regs + RCAR_GYROADC_START_STOP); ++ ++ /* ++ * Wait for the first conversion to complete. This is longer than ++ * the 1.25 mS in the datasheet because 1.25 mS is not enough for ++ * the hardware to deliver the first sample and the hardware does ++ * then return zeroes instead of valid data. ++ */ ++ mdelay(3); ++} ++ ++static void rcar_gyroadc_hw_stop(struct rcar_gyroadc *priv) ++{ ++ /* Stop the GyroADC. */ ++ writel(0, priv->regs + RCAR_GYROADC_START_STOP); ++} ++ ++#define RCAR_GYROADC_CHAN(_idx) { \ ++ .type = IIO_VOLTAGE, \ ++ .indexed = 1, \ ++ .channel = (_idx), \ ++ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ ++ BIT(IIO_CHAN_INFO_SCALE), \ ++ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ ++} ++ ++static const struct iio_chan_spec rcar_gyroadc_iio_channels_1[] = { ++ RCAR_GYROADC_CHAN(0), ++ RCAR_GYROADC_CHAN(1), ++ RCAR_GYROADC_CHAN(2), ++ RCAR_GYROADC_CHAN(3), ++}; ++ ++static const struct iio_chan_spec rcar_gyroadc_iio_channels_2[] = { ++ RCAR_GYROADC_CHAN(0), ++ RCAR_GYROADC_CHAN(1), ++ RCAR_GYROADC_CHAN(2), ++ RCAR_GYROADC_CHAN(3), ++ RCAR_GYROADC_CHAN(4), ++ RCAR_GYROADC_CHAN(5), ++ RCAR_GYROADC_CHAN(6), ++ RCAR_GYROADC_CHAN(7), ++}; ++ ++static const struct iio_chan_spec rcar_gyroadc_iio_channels_3[] = { ++ RCAR_GYROADC_CHAN(0), ++ RCAR_GYROADC_CHAN(1), ++ RCAR_GYROADC_CHAN(2), ++ RCAR_GYROADC_CHAN(3), ++ RCAR_GYROADC_CHAN(4), ++ RCAR_GYROADC_CHAN(5), ++ RCAR_GYROADC_CHAN(6), ++ RCAR_GYROADC_CHAN(7), ++}; ++ ++static int rcar_gyroadc_set_power(struct rcar_gyroadc *priv, bool on) ++{ ++ struct device *dev = priv->dev; ++ int ret; ++ ++ if (on) { ++ ret = pm_runtime_get_sync(dev); ++ if (ret < 0) ++ pm_runtime_put_noidle(dev); ++ } else { ++ pm_runtime_mark_last_busy(dev); ++ ret = pm_runtime_put_autosuspend(dev); ++ } ++ ++ return ret; ++} ++ ++static int rcar_gyroadc_read_raw(struct iio_dev *indio_dev, ++ struct iio_chan_spec const *chan, ++ int *val, int *val2, long mask) ++{ ++ struct rcar_gyroadc *priv = iio_priv(indio_dev); ++ struct regulator *consumer; ++ unsigned int datareg = RCAR_GYROADC_REALTIME_DATA(chan->channel); ++ unsigned int vref; ++ int ret; ++ ++ /* ++ * MB88101 is special in that it has only single regulator for ++ * all four channels. ++ */ ++ if (priv->mode == RCAR_GYROADC_MODE_SELECT_1_MB88101A) ++ consumer = priv->vref[0]; ++ else ++ consumer = priv->vref[chan->channel]; ++ ++ switch (mask) { ++ case IIO_CHAN_INFO_RAW: ++ if (chan->type != IIO_VOLTAGE) ++ return -EINVAL; ++ ++ /* Channel not connected. */ ++ if (!consumer) ++ return -EINVAL; ++ ++ ret = iio_device_claim_direct_mode(indio_dev); ++ if (ret) ++ return ret; ++ ++ ret = rcar_gyroadc_set_power(priv, true); ++ if (ret < 0) { ++ iio_device_release_direct_mode(indio_dev); ++ return ret; ++ } ++ ++ *val = readl(priv->regs + datareg); ++ *val &= BIT(priv->sample_width) - 1; ++ ++ ret = rcar_gyroadc_set_power(priv, false); ++ iio_device_release_direct_mode(indio_dev); ++ if (ret < 0) ++ return ret; ++ ++ return IIO_VAL_INT; ++ case IIO_CHAN_INFO_SCALE: ++ /* Channel not connected. */ ++ if (!consumer) ++ return -EINVAL; ++ ++ vref = regulator_get_voltage(consumer); ++ *val = vref / 1000; ++ *val2 = 1 << priv->sample_width; ++ ++ return IIO_VAL_FRACTIONAL; ++ case IIO_CHAN_INFO_SAMP_FREQ: ++ *val = RCAR_GYROADC_SAMPLE_RATE; ++ ++ return IIO_VAL_INT; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static int rcar_gyroadc_reg_access(struct iio_dev *indio_dev, ++ unsigned int reg, unsigned int writeval, ++ unsigned int *readval) ++{ ++ struct rcar_gyroadc *priv = iio_priv(indio_dev); ++ unsigned int maxreg = RCAR_GYROADC_FIFO_STATUS; ++ ++ if (readval == NULL) ++ return -EINVAL; ++ ++ if (reg % 4) ++ return -EINVAL; ++ ++ /* Handle the V2H case with extra interrupt block. */ ++ if (priv->model == RCAR_GYROADC_MODEL_R8A7792) ++ maxreg = RCAR_GYROADC_INTENR; ++ ++ if (reg > maxreg) ++ return -EINVAL; ++ ++ *readval = readl(priv->regs + reg); ++ ++ return 0; ++} ++ ++static const struct iio_info rcar_gyroadc_iio_info = { ++ .driver_module = THIS_MODULE, ++ .read_raw = rcar_gyroadc_read_raw, ++ .debugfs_reg_access = rcar_gyroadc_reg_access, ++}; ++ ++static const struct of_device_id rcar_gyroadc_match[] = { ++ { ++ /* R-Car compatible GyroADC */ ++ .compatible = "renesas,rcar-gyroadc", ++ .data = (void *)RCAR_GYROADC_MODEL_DEFAULT, ++ }, { ++ /* R-Car V2H specialty with interrupt registers. */ ++ .compatible = "renesas,r8a7792-gyroadc", ++ .data = (void *)RCAR_GYROADC_MODEL_R8A7792, ++ }, { ++ /* sentinel */ ++ } ++}; ++ ++MODULE_DEVICE_TABLE(of, rcar_gyroadc_match); ++ ++static const struct of_device_id rcar_gyroadc_child_match[] = { ++ /* Mode 1 ADCs */ ++ { ++ .compatible = "fujitsu,mb88101a", ++ .data = (void *)RCAR_GYROADC_MODE_SELECT_1_MB88101A, ++ }, ++ /* Mode 2 ADCs */ ++ { ++ .compatible = "ti,adcs7476", ++ .data = (void *)RCAR_GYROADC_MODE_SELECT_2_ADCS7476, ++ }, { ++ .compatible = "ti,adc121", ++ .data = (void *)RCAR_GYROADC_MODE_SELECT_2_ADCS7476, ++ }, { ++ .compatible = "adi,ad7476", ++ .data = (void *)RCAR_GYROADC_MODE_SELECT_2_ADCS7476, ++ }, ++ /* Mode 3 ADCs */ ++ { ++ .compatible = "maxim,max1162", ++ .data = (void *)RCAR_GYROADC_MODE_SELECT_3_MAX1162, ++ }, { ++ .compatible = "maxim,max11100", ++ .data = (void *)RCAR_GYROADC_MODE_SELECT_3_MAX1162, ++ }, ++ { /* sentinel */ } ++}; ++ ++static int rcar_gyroadc_parse_subdevs(struct iio_dev *indio_dev) ++{ ++ const struct of_device_id *of_id; ++ const struct iio_chan_spec *channels; ++ struct rcar_gyroadc *priv = iio_priv(indio_dev); ++ struct device *dev = priv->dev; ++ struct device_node *np = dev->of_node; ++ struct device_node *child; ++ struct regulator *vref; ++ unsigned int reg; ++ unsigned int adcmode, childmode; ++ unsigned int sample_width; ++ unsigned int num_channels; ++ int ret, first = 1; ++ ++ for_each_child_of_node(np, child) { ++ of_id = of_match_node(rcar_gyroadc_child_match, child); ++ if (!of_id) { ++ dev_err(dev, "Ignoring unsupported ADC \"%s\".", ++ child->name); ++ continue; ++ } ++ ++ childmode = (unsigned int)of_id->data; ++ switch (childmode) { ++ case RCAR_GYROADC_MODE_SELECT_1_MB88101A: ++ sample_width = 12; ++ channels = rcar_gyroadc_iio_channels_1; ++ num_channels = ARRAY_SIZE(rcar_gyroadc_iio_channels_1); ++ break; ++ case RCAR_GYROADC_MODE_SELECT_2_ADCS7476: ++ sample_width = 15; ++ channels = rcar_gyroadc_iio_channels_2; ++ num_channels = ARRAY_SIZE(rcar_gyroadc_iio_channels_2); ++ break; ++ case RCAR_GYROADC_MODE_SELECT_3_MAX1162: ++ sample_width = 16; ++ channels = rcar_gyroadc_iio_channels_3; ++ num_channels = ARRAY_SIZE(rcar_gyroadc_iio_channels_3); ++ break; ++ } ++ ++ /* ++ * MB88101 is special in that it's only a single chip taking ++ * up all the CHS lines. Thus, the DT binding is also special ++ * and has no reg property. If we run into such ADC, handle ++ * it here. ++ */ ++ if (childmode == RCAR_GYROADC_MODE_SELECT_1_MB88101A) { ++ reg = 0; ++ } else { ++ ret = of_property_read_u32(child, "reg", ®); ++ if (ret) { ++ dev_err(dev, ++ "Failed to get child reg property of ADC \"%s\".\n", ++ child->name); ++ return ret; ++ } ++ ++ /* Channel number is too high. */ ++ if (reg >= num_channels) { ++ dev_err(dev, ++ "Only %i channels supported with %s, but reg = <%i>.\n", ++ num_channels, child->name, reg); ++ return ret; ++ } ++ } ++ ++ /* Child node selected different mode than the rest. */ ++ if (!first && (adcmode != childmode)) { ++ dev_err(dev, ++ "Channel %i uses different ADC mode than the rest.\n", ++ reg); ++ return ret; ++ } ++ ++ /* Channel is valid, grab the regulator. */ ++ dev->of_node = child; ++ vref = devm_regulator_get(dev, "vref"); ++ dev->of_node = np; ++ if (IS_ERR(vref)) { ++ dev_dbg(dev, "Channel %i 'vref' supply not connected.\n", ++ reg); ++ return PTR_ERR(vref); ++ } ++ ++ priv->vref[reg] = vref; ++ ++ if (!first) ++ continue; ++ ++ /* First child node which passed sanity tests. */ ++ adcmode = childmode; ++ first = 0; ++ ++ priv->num_channels = num_channels; ++ priv->mode = childmode; ++ priv->sample_width = sample_width; ++ ++ indio_dev->channels = channels; ++ indio_dev->num_channels = num_channels; ++ ++ /* ++ * MB88101 is special and we only have one such device ++ * attached to the GyroADC at a time, so if we found it, ++ * we can stop parsing here. ++ */ ++ if (childmode == RCAR_GYROADC_MODE_SELECT_1_MB88101A) ++ break; ++ } ++ ++ if (first) { ++ dev_err(dev, "No valid ADC channels found, aborting.\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static void rcar_gyroadc_deinit_supplies(struct iio_dev *indio_dev) ++{ ++ struct rcar_gyroadc *priv = iio_priv(indio_dev); ++ unsigned int i; ++ ++ for (i = 0; i < priv->num_channels; i++) { ++ if (!priv->vref[i]) ++ continue; ++ ++ regulator_disable(priv->vref[i]); ++ } ++} ++ ++static int rcar_gyroadc_init_supplies(struct iio_dev *indio_dev) ++{ ++ struct rcar_gyroadc *priv = iio_priv(indio_dev); ++ struct device *dev = priv->dev; ++ unsigned int i; ++ int ret; ++ ++ for (i = 0; i < priv->num_channels; i++) { ++ if (!priv->vref[i]) ++ continue; ++ ++ ret = regulator_enable(priv->vref[i]); ++ if (ret) { ++ dev_err(dev, "Failed to enable regulator %i (ret=%i)\n", ++ i, ret); ++ goto err; ++ } ++ } ++ ++ return 0; ++ ++err: ++ rcar_gyroadc_deinit_supplies(indio_dev); ++ return ret; ++} ++ ++static int rcar_gyroadc_probe(struct platform_device *pdev) ++{ ++ const struct of_device_id *of_id = ++ of_match_device(rcar_gyroadc_match, &pdev->dev); ++ struct device *dev = &pdev->dev; ++ struct rcar_gyroadc *priv; ++ struct iio_dev *indio_dev; ++ struct resource *mem; ++ int ret; ++ ++ indio_dev = devm_iio_device_alloc(dev, sizeof(*priv)); ++ if (!indio_dev) { ++ dev_err(dev, "Failed to allocate IIO device.\n"); ++ return -ENOMEM; ++ } ++ ++ priv = iio_priv(indio_dev); ++ priv->dev = dev; ++ ++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ priv->regs = devm_ioremap_resource(dev, mem); ++ if (IS_ERR(priv->regs)) ++ return PTR_ERR(priv->regs); ++ ++ priv->iclk = devm_clk_get(dev, "if"); ++ if (IS_ERR(priv->iclk)) { ++ ret = PTR_ERR(priv->iclk); ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, "Failed to get IF clock (ret=%i)\n", ret); ++ return ret; ++ } ++ ++ ret = rcar_gyroadc_parse_subdevs(indio_dev); ++ if (ret) ++ return ret; ++ ++ ret = rcar_gyroadc_init_supplies(indio_dev); ++ if (ret) ++ return ret; ++ ++ priv->model = (enum rcar_gyroadc_model)of_id->data; ++ ++ platform_set_drvdata(pdev, indio_dev); ++ ++ indio_dev->name = DRIVER_NAME; ++ indio_dev->dev.parent = dev; ++ indio_dev->dev.of_node = pdev->dev.of_node; ++ indio_dev->info = &rcar_gyroadc_iio_info; ++ indio_dev->modes = INDIO_DIRECT_MODE; ++ ++ ret = clk_prepare_enable(priv->iclk); ++ if (ret) { ++ dev_err(dev, "Could not prepare or enable the IF clock.\n"); ++ goto err_clk_if_enable; ++ } ++ ++ pm_runtime_set_autosuspend_delay(dev, RCAR_GYROADC_RUNTIME_PM_DELAY_MS); ++ pm_runtime_use_autosuspend(dev); ++ pm_runtime_enable(dev); ++ ++ pm_runtime_get_sync(dev); ++ rcar_gyroadc_hw_init(priv); ++ rcar_gyroadc_hw_start(priv); ++ ++ ret = iio_device_register(indio_dev); ++ if (ret) { ++ dev_err(dev, "Couldn't register IIO device.\n"); ++ goto err_iio_device_register; ++ } ++ ++ pm_runtime_put_sync(dev); ++ ++ return 0; ++ ++err_iio_device_register: ++ rcar_gyroadc_hw_stop(priv); ++ pm_runtime_put_sync(dev); ++ pm_runtime_disable(dev); ++ pm_runtime_set_suspended(dev); ++ clk_disable_unprepare(priv->iclk); ++err_clk_if_enable: ++ rcar_gyroadc_deinit_supplies(indio_dev); ++ ++ return ret; ++} ++ ++static int rcar_gyroadc_remove(struct platform_device *pdev) ++{ ++ struct iio_dev *indio_dev = platform_get_drvdata(pdev); ++ struct rcar_gyroadc *priv = iio_priv(indio_dev); ++ struct device *dev = priv->dev; ++ ++ iio_device_unregister(indio_dev); ++ pm_runtime_get_sync(dev); ++ rcar_gyroadc_hw_stop(priv); ++ pm_runtime_put_sync(dev); ++ pm_runtime_disable(dev); ++ pm_runtime_set_suspended(dev); ++ clk_disable_unprepare(priv->iclk); ++ rcar_gyroadc_deinit_supplies(indio_dev); ++ ++ return 0; ++} ++ ++#if defined(CONFIG_PM) ++static int rcar_gyroadc_suspend(struct device *dev) ++{ ++ struct iio_dev *indio_dev = dev_get_drvdata(dev); ++ struct rcar_gyroadc *priv = iio_priv(indio_dev); ++ ++ rcar_gyroadc_hw_stop(priv); ++ ++ return 0; ++} ++ ++static int rcar_gyroadc_resume(struct device *dev) ++{ ++ struct iio_dev *indio_dev = dev_get_drvdata(dev); ++ struct rcar_gyroadc *priv = iio_priv(indio_dev); ++ ++ rcar_gyroadc_hw_start(priv); ++ ++ return 0; ++} ++#endif ++ ++static const struct dev_pm_ops rcar_gyroadc_pm_ops = { ++ SET_RUNTIME_PM_OPS(rcar_gyroadc_suspend, rcar_gyroadc_resume, NULL) ++}; ++ ++static struct platform_driver rcar_gyroadc_driver = { ++ .probe = rcar_gyroadc_probe, ++ .remove = rcar_gyroadc_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .of_match_table = rcar_gyroadc_match, ++ .pm = &rcar_gyroadc_pm_ops, ++ }, ++}; ++ ++module_platform_driver(rcar_gyroadc_driver); ++ ++MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>"); ++MODULE_DESCRIPTION("Renesas R-Car GyroADC driver"); ++MODULE_LICENSE("GPL"); diff --git a/patches.renesas/0113-iio-adc-handle-unknow-of_device_id-data.patch b/patches.renesas/0113-iio-adc-handle-unknow-of_device_id-data.patch new file mode 100644 index 0000000000000..49986e3b657e4 --- /dev/null +++ b/patches.renesas/0113-iio-adc-handle-unknow-of_device_id-data.patch @@ -0,0 +1,53 @@ +From 1d0272792aeca824e55424e5b057602594c65b23 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann <arnd@arndb.de> +Date: Fri, 3 Feb 2017 18:01:23 +0100 +Subject: [PATCH 113/255] iio: adc: handle unknow of_device_id data + +If we get an unknown 'childmode' value, a number of variables are not +initialized properly: + +drivers/iio/adc/rcar-gyroadc.c: In function 'rcar_gyroadc_probe': +drivers/iio/adc/rcar-gyroadc.c:390:5: error: 'num_channels' may be used uninitialized in this function [-Werror=maybe-uninitialized] +drivers/iio/adc/rcar-gyroadc.c:426:22: error: 'sample_width' may be used uninitialized in this function [-Werror=maybe-uninitialized] +drivers/iio/adc/rcar-gyroadc.c:428:23: error: 'channels' may be used uninitialized in this function [-Werror=maybe-uninitialized] + +The driver is currently correct, but handling this properly is more robust +for possible modifications. + +There is also a false-positive warning about adcmode being possibly uninitialized, +but that cannot happen as we also check the 'first' flag: + +drivers/iio/adc/rcar-gyroadc.c:398:26: error: 'adcmode' may be used uninitialized in this function [-Werror=maybe-uninitialized] + +This adds an initialization for 'adcmode' and bails out for any unknown childmode. + +Fixes: 059c53b32329 ("iio: adc: Add Renesas GyroADC driver") +Signed-off-by: Arnd Bergmann <arnd@arndb.de> +Acked-by: Marek Vasut <marek.vasut@gmail.com> +Signed-off-by: Jonathan Cameron <jic23@kernel.org> +(cherry picked from commit 17fa2dcbd6325ab877651bef04fca9dd828a2758) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/iio/adc/rcar-gyroadc.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/iio/adc/rcar-gyroadc.c ++++ b/drivers/iio/adc/rcar-gyroadc.c +@@ -336,7 +336,7 @@ static int rcar_gyroadc_parse_subdevs(st + struct device_node *child; + struct regulator *vref; + unsigned int reg; +- unsigned int adcmode, childmode; ++ unsigned int adcmode = -1, childmode; + unsigned int sample_width; + unsigned int num_channels; + int ret, first = 1; +@@ -366,6 +366,8 @@ static int rcar_gyroadc_parse_subdevs(st + channels = rcar_gyroadc_iio_channels_3; + num_channels = ARRAY_SIZE(rcar_gyroadc_iio_channels_3); + break; ++ default: ++ return -EINVAL; + } + + /* diff --git a/patches.renesas/0114-ASoC-rsnd-fixup-for_each_rsnd_mod_array-s-iterator-i.patch b/patches.renesas/0114-ASoC-rsnd-fixup-for_each_rsnd_mod_array-s-iterator-i.patch new file mode 100644 index 0000000000000..9ac12a47e0fd6 --- /dev/null +++ b/patches.renesas/0114-ASoC-rsnd-fixup-for_each_rsnd_mod_array-s-iterator-i.patch @@ -0,0 +1,49 @@ +From 0eb77118591ff58856547a14e840f598c163096b Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 20 Jan 2017 04:23:29 +0000 +Subject: [PATCH 114/255] ASoC: rsnd: fixup for_each_rsnd_mod_array{s} iterator + increment + +commit 5f222a292 ("ASoC: rsnd: use for_each_rsnd_mod_xxx() ...") +modifies rsnd_dai_call() to use for_each_rsnd_mod_arrays(). + +Current rsnd is incrementing iterator in rsnd_mod_next(), +but the iterator will indicate +1 position in for_each loop in +this case. Incremental position should be inside for() + +Reported-by: Hoan Nguyen An <na-hoan@jinso.co.jp> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 90ffc1ecc500c04bf43a45d804bb151505c0d6a6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 2 -- + sound/soc/sh/rcar/rsnd.h | 4 ++-- + 2 files changed, 2 insertions(+), 4 deletions(-) + +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -363,8 +363,6 @@ struct rsnd_mod *rsnd_mod_next(int *iter + if (!mod) + continue; + +- (*iterator)++; +- + return mod; + } + +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -374,10 +374,10 @@ struct rsnd_mod *rsnd_mod_next(int *iter + int array_size); + #define for_each_rsnd_mod(iterator, pos, io) \ + for (iterator = 0; \ +- (pos = rsnd_mod_next(&iterator, io, NULL, 0));) ++ (pos = rsnd_mod_next(&iterator, io, NULL, 0)); iterator++) + #define for_each_rsnd_mod_arrays(iterator, pos, io, array, size) \ + for (iterator = 0; \ +- (pos = rsnd_mod_next(&iterator, io, array, size));) ++ (pos = rsnd_mod_next(&iterator, io, array, size)); iterator++) + #define for_each_rsnd_mod_array(iterator, pos, io, array) \ + for_each_rsnd_mod_arrays(iterator, pos, io, array, ARRAY_SIZE(array)) + diff --git a/patches.renesas/0115-ASoC-rsnd-fixup-reset-timing-of-sync-convert_rate.patch b/patches.renesas/0115-ASoC-rsnd-fixup-reset-timing-of-sync-convert_rate.patch new file mode 100644 index 0000000000000..c7e747aedfe97 --- /dev/null +++ b/patches.renesas/0115-ASoC-rsnd-fixup-reset-timing-of-sync-convert_rate.patch @@ -0,0 +1,41 @@ +From 621972565ead9343b491066ce4754e12602982a7 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 2 Feb 2017 05:01:05 +0000 +Subject: [PATCH 115/255] ASoC: rsnd: fixup reset timing of sync convert_rate + +Sync convert rate settings should be availabled *after* Playing. +Thus, src->sync should be reset first of init function. +Otherwise, it will set remaining settings when it start playing. +This patch fixes it. Thanks to Yokoyama-san + +Reported-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit ef30da1c52c633a6eaa017ad0d075aaa809a6154) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/src.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -390,6 +390,9 @@ static int rsnd_src_init(struct rsnd_mod + { + struct rsnd_src *src = rsnd_mod_to_src(mod); + ++ /* reset sync convert_rate */ ++ src->sync.val = 0; ++ + rsnd_mod_power_on(mod); + + rsnd_src_activation(mod); +@@ -398,9 +401,6 @@ static int rsnd_src_init(struct rsnd_mod + + rsnd_src_status_clear(mod); + +- /* reset sync convert_rate */ +- src->sync.val = 0; +- + return 0; + } + diff --git a/patches.renesas/0116-ASoC-rcar-avoid-SSI_MODEx-settings-for-SSI8.patch b/patches.renesas/0116-ASoC-rcar-avoid-SSI_MODEx-settings-for-SSI8.patch new file mode 100644 index 0000000000000..7add8f730bd76 --- /dev/null +++ b/patches.renesas/0116-ASoC-rcar-avoid-SSI_MODEx-settings-for-SSI8.patch @@ -0,0 +1,36 @@ +From 6b9d80343b8bd5af4426d53180837859e252636b Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 3 Mar 2017 04:25:09 +0000 +Subject: [PATCH 116/255] ASoC: rcar: avoid SSI_MODEx settings for SSI8 + +SSI8 is is sharing pin with SSI7, and nothing to do for SSI_MODEx. +It is special pin and it needs special settings whole system, +but we can't confirm it, because we never have SSI8 available board. + +This patch fixup SSI_MODEx settings error for SSI8 on connection test, +but should be confirmed behavior on real board in the future. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 4b30eebfc35c67771b5f58d9274d3e321b72d7a8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/ssiu.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/sound/soc/sh/rcar/ssiu.c ++++ b/sound/soc/sh/rcar/ssiu.c +@@ -64,7 +64,11 @@ static int rsnd_ssiu_init(struct rsnd_mo + mask1 = (1 << 4) | (1 << 20); /* mask sync bit */ + mask2 = (1 << 4); /* mask sync bit */ + val1 = val2 = 0; +- if (rsnd_ssi_is_pin_sharing(io)) { ++ if (id == 8) { ++ /* ++ * SSI8 pin is sharing with SSI7, nothing to do. ++ */ ++ } else if (rsnd_ssi_is_pin_sharing(io)) { + int shift = -1; + + switch (id) { diff --git a/patches.renesas/0117-ASoC-rsnd-fix-sound-route-path-when-using-SRC6-SRC9.patch b/patches.renesas/0117-ASoC-rsnd-fix-sound-route-path-when-using-SRC6-SRC9.patch new file mode 100644 index 0000000000000..ded63d93e607b --- /dev/null +++ b/patches.renesas/0117-ASoC-rsnd-fix-sound-route-path-when-using-SRC6-SRC9.patch @@ -0,0 +1,83 @@ +From 8ce55797aec19d48fa9e54b57b09a32bd5e22095 Mon Sep 17 00:00:00 2001 +From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Date: Wed, 1 Mar 2017 03:51:00 +0000 +Subject: [PATCH 117/255] ASoC: rsnd: fix sound route path when using SRC6/SRC9 + +This patch fixes the problem that the missing value of the route path +setting table and incorrect values are set in the CMD_ROUTE_SELECT +register. + +Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +[Kuninori: shared data on MIX and non-MIX case] +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> + +(cherry picked from commit a1c2ff53726907aff5feb37e4cfd45c1ff626431) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/cmd.c | 36 ++++++++++++++++++++---------------- + 1 file changed, 20 insertions(+), 16 deletions(-) + +--- a/sound/soc/sh/rcar/cmd.c ++++ b/sound/soc/sh/rcar/cmd.c +@@ -31,23 +31,24 @@ static int rsnd_cmd_init(struct rsnd_mod + struct rsnd_mod *mix = rsnd_io_to_mod_mix(io); + struct device *dev = rsnd_priv_to_dev(priv); + u32 data; ++ u32 path[] = { ++ [1] = 1 << 0, ++ [5] = 1 << 8, ++ [6] = 1 << 12, ++ [9] = 1 << 15, ++ }; + + if (!mix && !dvc) + return 0; + ++ if (ARRAY_SIZE(path) < rsnd_mod_id(mod) + 1) ++ return -ENXIO; ++ + if (mix) { + struct rsnd_dai *rdai; + struct rsnd_mod *src; + struct rsnd_dai_stream *tio; + int i; +- u32 path[] = { +- [0] = 0, +- [1] = 1 << 0, +- [2] = 0, +- [3] = 0, +- [4] = 0, +- [5] = 1 << 8 +- }; + + /* + * it is assuming that integrater is well understanding about +@@ -70,16 +71,19 @@ static int rsnd_cmd_init(struct rsnd_mod + } else { + struct rsnd_mod *src = rsnd_io_to_mod_src(io); + +- u32 path[] = { +- [0] = 0x30000, +- [1] = 0x30001, +- [2] = 0x40000, +- [3] = 0x10000, +- [4] = 0x20000, +- [5] = 0x40100 ++ u8 cmd_case[] = { ++ [0] = 0x3, ++ [1] = 0x3, ++ [2] = 0x4, ++ [3] = 0x1, ++ [4] = 0x2, ++ [5] = 0x4, ++ [6] = 0x1, ++ [9] = 0x2, + }; + +- data = path[rsnd_mod_id(src)]; ++ data = path[rsnd_mod_id(src)] | ++ cmd_case[rsnd_mod_id(src)] << 16; + } + + dev_dbg(dev, "ctu/mix path = 0x%08x", data); diff --git a/patches.renesas/0118-ASoC-rcar-clear-DE-bit-only-in-PDMACHCR-when-it-stop.patch b/patches.renesas/0118-ASoC-rcar-clear-DE-bit-only-in-PDMACHCR-when-it-stop.patch new file mode 100644 index 0000000000000..a3d3844751aab --- /dev/null +++ b/patches.renesas/0118-ASoC-rcar-clear-DE-bit-only-in-PDMACHCR-when-it-stop.patch @@ -0,0 +1,56 @@ +From 2ccf181ab1dd4af6cffd9f7b1509b181e5aa3c73 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 14 Mar 2017 09:34:49 +0900 +Subject: [PATCH 118/255] ASoC: rcar: clear DE bit only in PDMACHCR when it + stops + +R-Car datasheet indicates "Clear DE in PDMACHCR" for transfer stop, +but current code clears all bits in PDMACHCR. +Because of this, DE bit might never been cleared, +and it causes CMD overflow. This patch fixes this issue. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 62a10498afb27370ec6018e9d802b74850fd8d9a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/dma.c | 18 ++++++++++++++++-- + 1 file changed, 16 insertions(+), 2 deletions(-) + +--- a/sound/soc/sh/rcar/dma.c ++++ b/sound/soc/sh/rcar/dma.c +@@ -454,6 +454,20 @@ static u32 rsnd_dmapp_read(struct rsnd_d + return ioread32(rsnd_dmapp_addr(dmac, dma, reg)); + } + ++static void rsnd_dmapp_bset(struct rsnd_dma *dma, u32 data, u32 mask, u32 reg) ++{ ++ struct rsnd_mod *mod = rsnd_mod_get(dma); ++ struct rsnd_priv *priv = rsnd_mod_to_priv(mod); ++ struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv); ++ volatile void __iomem *addr = rsnd_dmapp_addr(dmac, dma, reg); ++ u32 val = ioread32(addr); ++ ++ val &= ~mask; ++ val |= (data & mask); ++ ++ iowrite32(val, addr); ++} ++ + static int rsnd_dmapp_stop(struct rsnd_mod *mod, + struct rsnd_dai_stream *io, + struct rsnd_priv *priv) +@@ -461,10 +475,10 @@ static int rsnd_dmapp_stop(struct rsnd_m + struct rsnd_dma *dma = rsnd_mod_to_dma(mod); + int i; + +- rsnd_dmapp_write(dma, 0, PDMACHCR); ++ rsnd_dmapp_bset(dma, 0, PDMACHCR_DE, PDMACHCR); + + for (i = 0; i < 1024; i++) { +- if (0 == rsnd_dmapp_read(dma, PDMACHCR)) ++ if (0 == (rsnd_dmapp_read(dma, PDMACHCR) & PDMACHCR_DE)) + return 0; + udelay(1); + } diff --git a/patches.renesas/0119-ASoC-rcar-dma-remove-unnecessary-volatile.patch b/patches.renesas/0119-ASoC-rcar-dma-remove-unnecessary-volatile.patch new file mode 100644 index 0000000000000..0726891b38901 --- /dev/null +++ b/patches.renesas/0119-ASoC-rcar-dma-remove-unnecessary-volatile.patch @@ -0,0 +1,56 @@ +From 9022d90c85e7ba3e9efb1782d8e49b50dfab5ef1 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 16 Mar 2017 04:22:09 +0000 +Subject: [PATCH 119/255] ASoC: rcar: dma: remove unnecessary "volatile" + +commit 2a3af642eb20("ASoC: rcar: clear DE bit only in PDMACHCR...") +added rsnd_dmapp_bset(), but it used copy-paste. Thus, it had +unnecessary "volatile", and had below warning on x86. +This patch fix it. + + sound/soc/sh/rcar/dma.c: In function 'rsnd_dmapp_bset': +>> sound/soc/sh/rcar/dma.c:463:21: warning: passing argument 1 of \ + 'ioread32' discards 'volatile' qualifier from pointer target \ + type [-Wdiscarded-qualifiers] + u32 val = ioread32(addr); + ^~~~ + In file included from arch/x86/include/asm/io.h:203:0, + from arch/x86/include/asm/realmode.h:5, + from arch/x86/include/asm/acpi.h:33, + from arch/x86/include/asm/fixmap.h:19, + from arch/x86/include/asm/apic.h:10, + from arch/x86/include/asm/smp.h:12, + from include/linux/smp.h:59, + from include/linux/topology.h:33, + from include/linux/gfp.h:8, + from include/linux/idr.h:16, + from include/linux/kernfs.h:14, + from include/linux/sysfs.h:15, + from include/linux/kobject.h:21, + from include/linux/of.h:21, + from include/linux/of_dma.h:16, + from sound/soc/sh/rcar/dma.c:12: + include/asm-generic/iomap.h:31:21: note: expected 'void *' \ + but argument is of type 'volatile void *' + extern unsigned int ioread32(void __iomem *); + ^~~~~~~~ +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> + +(cherry picked from commit 9986943ef5d61a9bea3c86000d91d3b789f0060e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/dma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/sound/soc/sh/rcar/dma.c ++++ b/sound/soc/sh/rcar/dma.c +@@ -459,7 +459,7 @@ static void rsnd_dmapp_bset(struct rsnd_ + struct rsnd_mod *mod = rsnd_mod_get(dma); + struct rsnd_priv *priv = rsnd_mod_to_priv(mod); + struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv); +- volatile void __iomem *addr = rsnd_dmapp_addr(dmac, dma, reg); ++ void __iomem *addr = rsnd_dmapp_addr(dmac, dma, reg); + u32 val = ioread32(addr); + + val &= ~mask; diff --git a/patches.renesas/0120-spi-rspi-Remove-useless-memory-allocation-failure-me.patch b/patches.renesas/0120-spi-rspi-Remove-useless-memory-allocation-failure-me.patch new file mode 100644 index 0000000000000..17c6e6f9647c6 --- /dev/null +++ b/patches.renesas/0120-spi-rspi-Remove-useless-memory-allocation-failure-me.patch @@ -0,0 +1,30 @@ +From 6a3aee90392d5dafc14a73c9c098eb52b9a97ba1 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 4 Jan 2017 11:15:07 +0100 +Subject: [PATCH 120/255] spi: rspi: Remove useless memory allocation failure + message + +Printing an error on memory allocation failure is unnecessary. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit ffcfae3823751c72b615b57f700e563667002d09) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/spi/spi-rspi.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +--- a/drivers/spi/spi-rspi.c ++++ b/drivers/spi/spi-rspi.c +@@ -1227,10 +1227,8 @@ static int rspi_probe(struct platform_de + const struct spi_ops *ops; + + master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); +- if (master == NULL) { +- dev_err(&pdev->dev, "spi_alloc_master error.\n"); ++ if (master == NULL) + return -ENOMEM; +- } + + of_id = of_match_device(rspi_of_match, &pdev->dev); + if (of_id) { diff --git a/patches.renesas/0121-spi-rspi-Fixes-bogus-received-byte-in-qspi_transfer_.patch b/patches.renesas/0121-spi-rspi-Fixes-bogus-received-byte-in-qspi_transfer_.patch new file mode 100644 index 0000000000000..053b2c197767c --- /dev/null +++ b/patches.renesas/0121-spi-rspi-Fixes-bogus-received-byte-in-qspi_transfer_.patch @@ -0,0 +1,53 @@ +From aa695f54c79bb72710fce2a1c8dbd657afb8334d Mon Sep 17 00:00:00 2001 +From: DongCV <cv-dong@jinso.co.jp> +Date: Wed, 15 Feb 2017 19:50:51 +0900 +Subject: [PATCH 121/255] spi: rspi: Fixes bogus received byte in + qspi_transfer_in() + +In qspi_transfer_in(), when receiving the last n (or len) bytes of data, +one bogus byte was written in the receive buffer. +This code leads to a buffer overflow. + +"jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found +at 0x03b40000: 0x1900 instead +jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found +at 0x03b40004: 0x000c instead" + +The error message above happens when trying to mount, unmount, +and remount a jffs2-formatted device. +This patch removed the bogus write to fixes: 3be09bec42a800d4 +"spi: rspi: supports 32bytes buffer for DUAL and QUAD" + +And here is Geert's comment: + +"spi: rspi: Fix bogus received byte in qspi_transfer_in() +When there are less than QSPI_BUFFER_SIZE remaining bytes to be received, +qspi_transfer_in() writes one bogus byte in the receive buffer, possibly +leading to a buffer overflow. +This can be reproduced by mounting, unmounting, and remounting a +jffs2-formatted device, causing lots of warnings like: + +"jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found +at 0x03b40000: 0x1900 instead" + +Remove the bogus write to fix this. " + +Signed-off-by: DongCV <cv-dong@jinso.co.jp> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 7264abc7000d601726aefb05189ea524ee3995ba) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/spi/spi-rspi.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/spi/spi-rspi.c ++++ b/drivers/spi/spi-rspi.c +@@ -848,7 +848,6 @@ static int qspi_transfer_in(struct rspi_ + ret = rspi_pio_transfer(rspi, NULL, rx, n); + if (ret < 0) + return ret; +- *rx++ = ret; + } + n -= len; + } diff --git a/patches.renesas/0122-spi-rspi-Replaces-n-by-len-in-qspi_transfer_.patch b/patches.renesas/0122-spi-rspi-Replaces-n-by-len-in-qspi_transfer_.patch new file mode 100644 index 0000000000000..e1cbf18d66655 --- /dev/null +++ b/patches.renesas/0122-spi-rspi-Replaces-n-by-len-in-qspi_transfer_.patch @@ -0,0 +1,37 @@ +From 1e36189ab13e82d3789cbff04b957622ac53e1be Mon Sep 17 00:00:00 2001 +From: DongCV <cv-dong@jinso.co.jp> +Date: Wed, 15 Feb 2017 19:50:52 +0900 +Subject: [PATCH 122/255] spi: rspi: Replaces "n" by "len" in qspi_transfer_*() + +This patch replaced "n" by "len" bytes of data in qspi_transfer_in() and +qspi_transfer_out() function. This will make improving readability. + +Signed-off-by: DongCV <cv-dong@jinso.co.jp> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit ad16d4a83ddc86151b4a6efe257ba74eb30f9f8e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/spi/spi-rspi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/spi/spi-rspi.c ++++ b/drivers/spi/spi-rspi.c +@@ -808,7 +808,7 @@ static int qspi_transfer_out(struct rspi + for (i = 0; i < len; i++) + rspi_write_data(rspi, *tx++); + } else { +- ret = rspi_pio_transfer(rspi, tx, NULL, n); ++ ret = rspi_pio_transfer(rspi, tx, NULL, len); + if (ret < 0) + return ret; + } +@@ -845,7 +845,7 @@ static int qspi_transfer_in(struct rspi_ + for (i = 0; i < len; i++) + *rx++ = rspi_read_data(rspi); + } else { +- ret = rspi_pio_transfer(rspi, NULL, rx, n); ++ ret = rspi_pio_transfer(rspi, NULL, rx, len); + if (ret < 0) + return ret; + } diff --git a/patches.renesas/0123-ata-pass-queued-command-to-sff_data_xfer-method.patch b/patches.renesas/0123-ata-pass-queued-command-to-sff_data_xfer-method.patch new file mode 100644 index 0000000000000..81016f89647ea --- /dev/null +++ b/patches.renesas/0123-ata-pass-queued-command-to-sff_data_xfer-method.patch @@ -0,0 +1,408 @@ +From e534be0ba9c7a92163d493455e7fb533af05c3ec Mon Sep 17 00:00:00 2001 +From: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> +Date: Fri, 30 Dec 2016 15:01:17 +0100 +Subject: [PATCH 123/255] ata: pass queued command to ->sff_data_xfer method + +For Atari Falcon PATA support we need to check the current command +in its ->sff_data_xfer method. Update core code and all users +accordingly. + +There should be no functional changes caused by this patch. + +Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> +Signed-off-by: Tejun Heo <tj@kernel.org> +(cherry picked from commit 989e0aac1a801e9e9580632c9fd448a7aaca596a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/ata/libata-sff.c | 29 +++++++++++++++-------------- + drivers/ata/pata_at91.c | 6 +++--- + drivers/ata/pata_bf54x.c | 7 ++++--- + drivers/ata/pata_ep93xx.c | 4 ++-- + drivers/ata/pata_ixp4xx_cf.c | 4 ++-- + drivers/ata/pata_legacy.c | 15 +++++++++------ + drivers/ata/pata_octeon_cf.c | 12 ++++++------ + drivers/ata/pata_pcmcia.c | 6 +++--- + drivers/ata/pata_samsung_cf.c | 4 ++-- + drivers/ata/sata_rcar.c | 4 ++-- + include/linux/libata.h | 8 ++++---- + 11 files changed, 52 insertions(+), 47 deletions(-) + +--- a/drivers/ata/libata-sff.c ++++ b/drivers/ata/libata-sff.c +@@ -542,7 +542,7 @@ static inline void ata_tf_to_host(struct + + /** + * ata_sff_data_xfer - Transfer data by PIO +- * @dev: device to target ++ * @qc: queued command + * @buf: data buffer + * @buflen: buffer length + * @rw: read/write +@@ -555,10 +555,10 @@ static inline void ata_tf_to_host(struct + * RETURNS: + * Bytes consumed. + */ +-unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, ++unsigned int ata_sff_data_xfer(struct ata_queued_cmd *qc, unsigned char *buf, + unsigned int buflen, int rw) + { +- struct ata_port *ap = dev->link->ap; ++ struct ata_port *ap = qc->dev->link->ap; + void __iomem *data_addr = ap->ioaddr.data_addr; + unsigned int words = buflen >> 1; + +@@ -595,7 +595,7 @@ EXPORT_SYMBOL_GPL(ata_sff_data_xfer); + + /** + * ata_sff_data_xfer32 - Transfer data by PIO +- * @dev: device to target ++ * @qc: queued command + * @buf: data buffer + * @buflen: buffer length + * @rw: read/write +@@ -610,16 +610,17 @@ EXPORT_SYMBOL_GPL(ata_sff_data_xfer); + * Bytes consumed. + */ + +-unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf, ++unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf, + unsigned int buflen, int rw) + { ++ struct ata_device *dev = qc->dev; + struct ata_port *ap = dev->link->ap; + void __iomem *data_addr = ap->ioaddr.data_addr; + unsigned int words = buflen >> 2; + int slop = buflen & 3; + + if (!(ap->pflags & ATA_PFLAG_PIO32)) +- return ata_sff_data_xfer(dev, buf, buflen, rw); ++ return ata_sff_data_xfer(qc, buf, buflen, rw); + + /* Transfer multiple of 4 bytes */ + if (rw == READ) +@@ -658,7 +659,7 @@ EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); + + /** + * ata_sff_data_xfer_noirq - Transfer data by PIO +- * @dev: device to target ++ * @qc: queued command + * @buf: data buffer + * @buflen: buffer length + * @rw: read/write +@@ -672,14 +673,14 @@ EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); + * RETURNS: + * Bytes consumed. + */ +-unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf, ++unsigned int ata_sff_data_xfer_noirq(struct ata_queued_cmd *qc, unsigned char *buf, + unsigned int buflen, int rw) + { + unsigned long flags; + unsigned int consumed; + + local_irq_save(flags); +- consumed = ata_sff_data_xfer32(dev, buf, buflen, rw); ++ consumed = ata_sff_data_xfer32(qc, buf, buflen, rw); + local_irq_restore(flags); + + return consumed; +@@ -723,14 +724,14 @@ static void ata_pio_sector(struct ata_qu + buf = kmap_atomic(page); + + /* do the actual data transfer */ +- ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, ++ ap->ops->sff_data_xfer(qc, buf + offset, qc->sect_size, + do_write); + + kunmap_atomic(buf); + local_irq_restore(flags); + } else { + buf = page_address(page); +- ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, ++ ap->ops->sff_data_xfer(qc, buf + offset, qc->sect_size, + do_write); + } + +@@ -791,7 +792,7 @@ static void atapi_send_cdb(struct ata_po + DPRINTK("send cdb\n"); + WARN_ON_ONCE(qc->dev->cdb_len < 12); + +- ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1); ++ ap->ops->sff_data_xfer(qc, qc->cdb, qc->dev->cdb_len, 1); + ata_sff_sync(ap); + /* FIXME: If the CDB is for DMA do we need to do the transition delay + or is bmdma_start guaranteed to do it ? */ +@@ -868,14 +869,14 @@ next_sg: + buf = kmap_atomic(page); + + /* do the actual data transfer */ +- consumed = ap->ops->sff_data_xfer(dev, buf + offset, ++ consumed = ap->ops->sff_data_xfer(qc, buf + offset, + count, rw); + + kunmap_atomic(buf); + local_irq_restore(flags); + } else { + buf = page_address(page); +- consumed = ap->ops->sff_data_xfer(dev, buf + offset, ++ consumed = ap->ops->sff_data_xfer(qc, buf + offset, + count, rw); + } + +--- a/drivers/ata/pata_at91.c ++++ b/drivers/ata/pata_at91.c +@@ -286,10 +286,10 @@ static void pata_at91_set_piomode(struct + set_smc_timing(ap->dev, adev, info, &timing); + } + +-static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev, ++static unsigned int pata_at91_data_xfer_noirq(struct ata_queued_cmd *qc, + unsigned char *buf, unsigned int buflen, int rw) + { +- struct at91_ide_info *info = dev->link->ap->host->private_data; ++ struct at91_ide_info *info = qc->dev->link->ap->host->private_data; + unsigned int consumed; + unsigned int mode; + unsigned long flags; +@@ -301,7 +301,7 @@ static unsigned int pata_at91_data_xfer_ + regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) | + AT91_SMC_DBW_16); + +- consumed = ata_sff_data_xfer(dev, buf, buflen, rw); ++ consumed = ata_sff_data_xfer(qc, buf, buflen, rw); + + /* restore 8bit mode after data is written */ + regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) | +--- a/drivers/ata/pata_bf54x.c ++++ b/drivers/ata/pata_bf54x.c +@@ -1143,7 +1143,7 @@ static unsigned char bfin_bmdma_status(s + + /** + * bfin_data_xfer - Transfer data by PIO +- * @adev: device for this I/O ++ * @qc: queued command + * @buf: data buffer + * @buflen: buffer length + * @write_data: read/write +@@ -1151,10 +1151,11 @@ static unsigned char bfin_bmdma_status(s + * Note: Original code is ata_sff_data_xfer(). + */ + +-static unsigned int bfin_data_xfer(struct ata_device *dev, unsigned char *buf, ++static unsigned int bfin_data_xfer(struct ata_queued_cmd *qc, ++ unsigned char *buf, + unsigned int buflen, int rw) + { +- struct ata_port *ap = dev->link->ap; ++ struct ata_port *ap = qc->dev->link->ap; + void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; + unsigned int words = buflen >> 1; + unsigned short *buf16 = (u16 *)buf; +--- a/drivers/ata/pata_ep93xx.c ++++ b/drivers/ata/pata_ep93xx.c +@@ -474,11 +474,11 @@ static void ep93xx_pata_set_devctl(struc + } + + /* Note: original code is ata_sff_data_xfer */ +-static unsigned int ep93xx_pata_data_xfer(struct ata_device *adev, ++static unsigned int ep93xx_pata_data_xfer(struct ata_queued_cmd *qc, + unsigned char *buf, + unsigned int buflen, int rw) + { +- struct ata_port *ap = adev->link->ap; ++ struct ata_port *ap = qc->dev->link->ap; + struct ep93xx_pata_data *drv_data = ap->host->private_data; + u16 *data = (u16 *)buf; + unsigned int words = buflen >> 1; +--- a/drivers/ata/pata_ixp4xx_cf.c ++++ b/drivers/ata/pata_ixp4xx_cf.c +@@ -40,13 +40,13 @@ static int ixp4xx_set_mode(struct ata_li + return 0; + } + +-static unsigned int ixp4xx_mmio_data_xfer(struct ata_device *dev, ++static unsigned int ixp4xx_mmio_data_xfer(struct ata_queued_cmd *qc, + unsigned char *buf, unsigned int buflen, int rw) + { + unsigned int i; + unsigned int words = buflen >> 1; + u16 *buf16 = (u16 *) buf; +- struct ata_port *ap = dev->link->ap; ++ struct ata_port *ap = qc->dev->link->ap; + void __iomem *mmio = ap->ioaddr.data_addr; + struct ixp4xx_pata_data *data = dev_get_platdata(ap->host->dev); + +--- a/drivers/ata/pata_legacy.c ++++ b/drivers/ata/pata_legacy.c +@@ -303,11 +303,12 @@ static void pdc20230_set_piomode(struct + + } + +-static unsigned int pdc_data_xfer_vlb(struct ata_device *dev, ++static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc, + unsigned char *buf, unsigned int buflen, int rw) + { +- int slop = buflen & 3; ++ struct ata_device *dev = qc->dev; + struct ata_port *ap = dev->link->ap; ++ int slop = buflen & 3; + + /* 32bit I/O capable *and* we need to write a whole number of dwords */ + if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3) +@@ -340,7 +341,7 @@ static unsigned int pdc_data_xfer_vlb(st + } + local_irq_restore(flags); + } else +- buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw); ++ buflen = ata_sff_data_xfer_noirq(qc, buf, buflen, rw); + + return buflen; + } +@@ -702,9 +703,11 @@ static unsigned int qdi_qc_issue(struct + return ata_sff_qc_issue(qc); + } + +-static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf, +- unsigned int buflen, int rw) ++static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc, ++ unsigned char *buf, ++ unsigned int buflen, int rw) + { ++ struct ata_device *adev = qc->dev; + struct ata_port *ap = adev->link->ap; + int slop = buflen & 3; + +@@ -727,7 +730,7 @@ static unsigned int vlb32_data_xfer(stru + } + return (buflen + 3) & ~3; + } else +- return ata_sff_data_xfer(adev, buf, buflen, rw); ++ return ata_sff_data_xfer(qc, buf, buflen, rw); + } + + static int qdi_port(struct platform_device *dev, +--- a/drivers/ata/pata_octeon_cf.c ++++ b/drivers/ata/pata_octeon_cf.c +@@ -293,17 +293,17 @@ static void octeon_cf_set_dmamode(struct + /** + * Handle an 8 bit I/O request. + * +- * @dev: Device to access ++ * @qc: Queued command + * @buffer: Data buffer + * @buflen: Length of the buffer. + * @rw: True to write. + */ +-static unsigned int octeon_cf_data_xfer8(struct ata_device *dev, ++static unsigned int octeon_cf_data_xfer8(struct ata_queued_cmd *qc, + unsigned char *buffer, + unsigned int buflen, + int rw) + { +- struct ata_port *ap = dev->link->ap; ++ struct ata_port *ap = qc->dev->link->ap; + void __iomem *data_addr = ap->ioaddr.data_addr; + unsigned long words; + int count; +@@ -332,17 +332,17 @@ static unsigned int octeon_cf_data_xfer8 + /** + * Handle a 16 bit I/O request. + * +- * @dev: Device to access ++ * @qc: Queued command + * @buffer: Data buffer + * @buflen: Length of the buffer. + * @rw: True to write. + */ +-static unsigned int octeon_cf_data_xfer16(struct ata_device *dev, ++static unsigned int octeon_cf_data_xfer16(struct ata_queued_cmd *qc, + unsigned char *buffer, + unsigned int buflen, + int rw) + { +- struct ata_port *ap = dev->link->ap; ++ struct ata_port *ap = qc->dev->link->ap; + void __iomem *data_addr = ap->ioaddr.data_addr; + unsigned long words; + int count; +--- a/drivers/ata/pata_pcmcia.c ++++ b/drivers/ata/pata_pcmcia.c +@@ -90,7 +90,7 @@ static int pcmcia_set_mode_8bit(struct a + + /** + * ata_data_xfer_8bit - Transfer data by 8bit PIO +- * @dev: device to target ++ * @qc: queued command + * @buf: data buffer + * @buflen: buffer length + * @rw: read/write +@@ -101,10 +101,10 @@ static int pcmcia_set_mode_8bit(struct a + * Inherited from caller. + */ + +-static unsigned int ata_data_xfer_8bit(struct ata_device *dev, ++static unsigned int ata_data_xfer_8bit(struct ata_queued_cmd *qc, + unsigned char *buf, unsigned int buflen, int rw) + { +- struct ata_port *ap = dev->link->ap; ++ struct ata_port *ap = qc->dev->link->ap; + + if (rw == READ) + ioread8_rep(ap->ioaddr.data_addr, buf, buflen); +--- a/drivers/ata/pata_samsung_cf.c ++++ b/drivers/ata/pata_samsung_cf.c +@@ -263,10 +263,10 @@ static u8 pata_s3c_check_altstatus(struc + /* + * pata_s3c_data_xfer - Transfer data by PIO + */ +-static unsigned int pata_s3c_data_xfer(struct ata_device *dev, ++static unsigned int pata_s3c_data_xfer(struct ata_queued_cmd *qc, + unsigned char *buf, unsigned int buflen, int rw) + { +- struct ata_port *ap = dev->link->ap; ++ struct ata_port *ap = qc->dev->link->ap; + struct s3c_ide_info *info = ap->host->private_data; + void __iomem *data_addr = ap->ioaddr.data_addr; + unsigned int words = buflen >> 1, i; +--- a/drivers/ata/sata_rcar.c ++++ b/drivers/ata/sata_rcar.c +@@ -447,11 +447,11 @@ static void sata_rcar_exec_command(struc + ata_sff_pause(ap); + } + +-static unsigned int sata_rcar_data_xfer(struct ata_device *dev, ++static unsigned int sata_rcar_data_xfer(struct ata_queued_cmd *qc, + unsigned char *buf, + unsigned int buflen, int rw) + { +- struct ata_port *ap = dev->link->ap; ++ struct ata_port *ap = qc->dev->link->ap; + void __iomem *data_addr = ap->ioaddr.data_addr; + unsigned int words = buflen >> 1; + +--- a/include/linux/libata.h ++++ b/include/linux/libata.h +@@ -963,7 +963,7 @@ struct ata_port_operations { + void (*sff_tf_read)(struct ata_port *ap, struct ata_taskfile *tf); + void (*sff_exec_command)(struct ata_port *ap, + const struct ata_taskfile *tf); +- unsigned int (*sff_data_xfer)(struct ata_device *dev, ++ unsigned int (*sff_data_xfer)(struct ata_queued_cmd *qc, + unsigned char *buf, unsigned int buflen, int rw); + void (*sff_irq_on)(struct ata_port *); + bool (*sff_irq_check)(struct ata_port *); +@@ -1818,11 +1818,11 @@ extern void ata_sff_tf_load(struct ata_p + extern void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf); + extern void ata_sff_exec_command(struct ata_port *ap, + const struct ata_taskfile *tf); +-extern unsigned int ata_sff_data_xfer(struct ata_device *dev, ++extern unsigned int ata_sff_data_xfer(struct ata_queued_cmd *qc, + unsigned char *buf, unsigned int buflen, int rw); +-extern unsigned int ata_sff_data_xfer32(struct ata_device *dev, ++extern unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, + unsigned char *buf, unsigned int buflen, int rw); +-extern unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, ++extern unsigned int ata_sff_data_xfer_noirq(struct ata_queued_cmd *qc, + unsigned char *buf, unsigned int buflen, int rw); + extern void ata_sff_irq_on(struct ata_port *ap); + extern void ata_sff_irq_clear(struct ata_port *ap); diff --git a/patches.renesas/0124-sh_eth-handle-only-enabled-E-MAC-interrupts.patch b/patches.renesas/0124-sh_eth-handle-only-enabled-E-MAC-interrupts.patch new file mode 100644 index 0000000000000..6bf84d206c91d --- /dev/null +++ b/patches.renesas/0124-sh_eth-handle-only-enabled-E-MAC-interrupts.patch @@ -0,0 +1,30 @@ +From f03ad6c2af0ae8d76fd119961d39d553f0a0f2f2 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 4 Jan 2017 15:10:21 +0300 +Subject: [PATCH 124/255] sh_eth: handle only enabled E-MAC interrupts + +The driver should only handle the enabled E-MAC interrupts, like it does +for the E-DMAC interrupts since commit 3893b27345ac ("sh_eth: workaround +for spurious ECI interrupt"), so mask ECSR with ECSIPR when reading it +in sh_eth_error(). + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 4063469971af9611648382559c2d399cce03ae67) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -1549,7 +1549,8 @@ static void sh_eth_error(struct net_devi + u32 mask; + + if (intr_status & EESR_ECI) { +- felic_stat = sh_eth_read(ndev, ECSR); ++ felic_stat = sh_eth_read(ndev, ECSR) & ++ sh_eth_read(ndev, ECSIPR); + sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ + if (felic_stat & ECSR_ICD) + ndev->stats.tx_carrier_errors++; diff --git a/patches.renesas/0125-sh_eth-no-need-for-else-after-goto.patch b/patches.renesas/0125-sh_eth-no-need-for-else-after-goto.patch new file mode 100644 index 0000000000000..a7304feec6c3b --- /dev/null +++ b/patches.renesas/0125-sh_eth-no-need-for-else-after-goto.patch @@ -0,0 +1,37 @@ +From 955ebb247da75101463bbe090d3362d6ce26ab0a Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 4 Jan 2017 15:10:50 +0300 +Subject: [PATCH 125/255] sh_eth: no need for *else* after *goto* + +Well, checkpatch.pl complains about *else* after *return* and *break* but +not after *goto*... and it probably should have complained about the code +in sh_eth_error(). Win couple LoCs by removing that *else*. :-) + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 1940f240769ada7efe9d459991fe5dd80db3771a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 10 ++++------ + 1 file changed, 4 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -1556,13 +1556,11 @@ static void sh_eth_error(struct net_devi + ndev->stats.tx_carrier_errors++; + if (felic_stat & ECSR_LCHNG) { + /* Link Changed */ +- if (mdp->cd->no_psr || mdp->no_ether_link) { ++ if (mdp->cd->no_psr || mdp->no_ether_link) + goto ignore_link; +- } else { +- link_stat = (sh_eth_read(ndev, PSR)); +- if (mdp->ether_link_active_low) +- link_stat = ~link_stat; +- } ++ link_stat = sh_eth_read(ndev, PSR); ++ if (mdp->ether_link_active_low) ++ link_stat = ~link_stat; + if (!(link_stat & PHY_ST_LINK)) { + sh_eth_rcv_snd_disable(ndev); + } else { diff --git a/patches.renesas/0126-sh_eth-factor-out-sh_eth_emac_interrupt.patch b/patches.renesas/0126-sh_eth-factor-out-sh_eth_emac_interrupt.patch new file mode 100644 index 0000000000000..6fad390c19ab0 --- /dev/null +++ b/patches.renesas/0126-sh_eth-factor-out-sh_eth_emac_interrupt.patch @@ -0,0 +1,240 @@ +From c39b1f565ccbaedd3a0ba47e7b6a23bc9a4cc1d3 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 4 Jan 2017 15:11:21 +0300 +Subject: [PATCH 126/255] sh_eth: factor out sh_eth_emac_interrupt() + +The E-MAC interrupt (EESR.ECI) is not always caused by an error condition, +so it really shouldn't be handled by sh_eth_error(). Factor out the E-MAC +interrupt handler, sh_eth_emac_interrupt(), removing the ECI bit from the +EESR's values throughout the driver... + +Update Cogent Embedded's copyright and clean up the whitespace in Renesas' +copyright, while at it... + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 9b39f05ce8e0cf2857c37b72c0b3b92e6a026ed5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 102 +++++++++++++++++----------------- + drivers/net/ethernet/renesas/sh_eth.h | 2 + 2 files changed, 53 insertions(+), 51 deletions(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -1,9 +1,9 @@ + /* SuperH Ethernet device driver + * +- * Copyright (C) 2014 Renesas Electronics Corporation ++ * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2006-2012 Nobuhiro Iwamatsu + * Copyright (C) 2008-2014 Renesas Solutions Corp. +- * Copyright (C) 2013-2016 Cogent Embedded, Inc. ++ * Copyright (C) 2013-2017 Cogent Embedded, Inc. + * Copyright (C) 2014 Codethink Limited + * + * This program is free software; you can redistribute it and/or modify it +@@ -523,7 +523,7 @@ static struct sh_eth_cpu_data r7s72100_d + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | + EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | +- EESR_TDE | EESR_ECI, ++ EESR_TDE, + .fdr_value = 0x0000070f, + + .no_psr = 1, +@@ -562,7 +562,7 @@ static struct sh_eth_cpu_data r8a7740_da + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | + EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | +- EESR_TDE | EESR_ECI, ++ EESR_TDE, + .fdr_value = 0x0000070f, + + .apr = 1, +@@ -608,8 +608,7 @@ static struct sh_eth_cpu_data r8a777x_da + + .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | +- EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | +- EESR_ECI, ++ EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, + .fdr_value = 0x00000f0f, + + .apr = 1, +@@ -631,8 +630,7 @@ static struct sh_eth_cpu_data r8a779x_da + + .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | +- EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | +- EESR_ECI, ++ EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, + .fdr_value = 0x00000f0f, + + .trscer_err_mask = DESC_I_RINT8, +@@ -672,8 +670,7 @@ static struct sh_eth_cpu_data sh7724_dat + + .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | +- EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | +- EESR_ECI, ++ EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, + + .apr = 1, + .mpr = 1, +@@ -708,8 +705,7 @@ static struct sh_eth_cpu_data sh7757_dat + + .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | +- EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | +- EESR_ECI, ++ EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, + + .irq_flags = IRQF_SHARED, + .apr = 1, +@@ -777,7 +773,7 @@ static struct sh_eth_cpu_data sh7757_dat + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | + EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | +- EESR_TDE | EESR_ECI, ++ EESR_TDE, + .fdr_value = 0x0000072f, + + .irq_flags = IRQF_SHARED, +@@ -808,7 +804,7 @@ static struct sh_eth_cpu_data sh7734_dat + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | + EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | +- EESR_TDE | EESR_ECI, ++ EESR_TDE, + + .apr = 1, + .mpr = 1, +@@ -837,8 +833,7 @@ static struct sh_eth_cpu_data sh7763_dat + + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | +- EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | +- EESR_ECI, ++ EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, + + .apr = 1, + .mpr = 1, +@@ -1540,43 +1535,44 @@ static void sh_eth_rcv_snd_enable(struct + sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); + } + +-/* error control function */ +-static void sh_eth_error(struct net_device *ndev, u32 intr_status) ++/* E-MAC interrupt handler */ ++static void sh_eth_emac_interrupt(struct net_device *ndev) + { + struct sh_eth_private *mdp = netdev_priv(ndev); + u32 felic_stat; + u32 link_stat; +- u32 mask; + +- if (intr_status & EESR_ECI) { +- felic_stat = sh_eth_read(ndev, ECSR) & +- sh_eth_read(ndev, ECSIPR); +- sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ +- if (felic_stat & ECSR_ICD) +- ndev->stats.tx_carrier_errors++; +- if (felic_stat & ECSR_LCHNG) { +- /* Link Changed */ +- if (mdp->cd->no_psr || mdp->no_ether_link) +- goto ignore_link; +- link_stat = sh_eth_read(ndev, PSR); +- if (mdp->ether_link_active_low) +- link_stat = ~link_stat; +- if (!(link_stat & PHY_ST_LINK)) { +- sh_eth_rcv_snd_disable(ndev); +- } else { +- /* Link Up */ +- sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0); +- /* clear int */ +- sh_eth_modify(ndev, ECSR, 0, 0); +- sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, +- DMAC_M_ECI); +- /* enable tx and rx */ +- sh_eth_rcv_snd_enable(ndev); +- } ++ felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); ++ sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ ++ if (felic_stat & ECSR_ICD) ++ ndev->stats.tx_carrier_errors++; ++ if (felic_stat & ECSR_LCHNG) { ++ /* Link Changed */ ++ if (mdp->cd->no_psr || mdp->no_ether_link) ++ return; ++ link_stat = sh_eth_read(ndev, PSR); ++ if (mdp->ether_link_active_low) ++ link_stat = ~link_stat; ++ if (!(link_stat & PHY_ST_LINK)) { ++ sh_eth_rcv_snd_disable(ndev); ++ } else { ++ /* Link Up */ ++ sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0); ++ /* clear int */ ++ sh_eth_modify(ndev, ECSR, 0, 0); ++ sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, DMAC_M_ECI); ++ /* enable tx and rx */ ++ sh_eth_rcv_snd_enable(ndev); + } + } ++} ++ ++/* error control function */ ++static void sh_eth_error(struct net_device *ndev, u32 intr_status) ++{ ++ struct sh_eth_private *mdp = netdev_priv(ndev); ++ u32 mask; + +-ignore_link: + if (intr_status & EESR_TWB) { + /* Unused write back interrupt */ + if (intr_status & EESR_TABT) { /* Transmit Abort int */ +@@ -1657,14 +1653,16 @@ static irqreturn_t sh_eth_interrupt(int + + /* Get interrupt status */ + intr_status = sh_eth_read(ndev, EESR); +- /* Mask it with the interrupt mask, forcing ECI interrupt to be always +- * enabled since it's the one that comes thru regardless of the mask, +- * and we need to fully handle it in sh_eth_error() in order to quench +- * it as it doesn't get cleared by just writing 1 to the ECI bit... ++ /* Mask it with the interrupt mask, forcing ECI interrupt to be always ++ * enabled since it's the one that comes thru regardless of the mask, ++ * and we need to fully handle it in sh_eth_emac_interrupt() in order ++ * to quench it as it doesn't get cleared by just writing 1 to the ECI ++ * bit... + */ + intr_enable = sh_eth_read(ndev, EESIPR); + intr_status &= intr_enable | DMAC_M_ECI; +- if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) ++ if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | ++ cd->eesr_err_check)) + ret = IRQ_HANDLED; + else + goto out; +@@ -1696,6 +1694,10 @@ static irqreturn_t sh_eth_interrupt(int + netif_wake_queue(ndev); + } + ++ /* E-MAC interrupt */ ++ if (intr_status & EESR_ECI) ++ sh_eth_emac_interrupt(ndev); ++ + if (intr_status & cd->eesr_err_check) { + /* Clear error interrupts */ + sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -265,7 +265,7 @@ enum EESR_BIT { + EESR_RTO) + #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \ + EESR_RDE | EESR_RFRMER | EESR_ADE | \ +- EESR_TFE | EESR_TDE | EESR_ECI) ++ EESR_TFE | EESR_TDE) + + /* EESIPR */ + enum DMAC_IM_BIT { diff --git a/patches.renesas/0127-sh_eth-get-rid-of-sh_eth_cpu_data-shift_rd0.patch b/patches.renesas/0127-sh_eth-get-rid-of-sh_eth_cpu_data-shift_rd0.patch new file mode 100644 index 0000000000000..7c11592a40252 --- /dev/null +++ b/patches.renesas/0127-sh_eth-get-rid-of-sh_eth_cpu_data-shift_rd0.patch @@ -0,0 +1,65 @@ +From 0e0771aeae67214186e2af31366ce805b88a19c3 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sat, 7 Jan 2017 00:02:52 +0300 +Subject: [PATCH 127/255] sh_eth: get rid of 'sh_eth_cpu_data::shift_rd0' + +After checking all the available manuals, I have enough information to +conclude that the 'shift_rd0' flag is only relevant for the Ether cores +supporting so called "intelligent checksum" (and hence having CSMR) which +is indicated by the 'hw_crc' flag. Since all the relevant SoCs now have +both these flags set, we can at last get rid of the former flag... + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 2e653ff0758ae8e47499d588666eb77f6a0fc755) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 5 +---- + drivers/net/ethernet/renesas/sh_eth.h | 1 - + 2 files changed, 1 insertion(+), 5 deletions(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -537,7 +537,6 @@ static struct sh_eth_cpu_data r7s72100_d + .no_ade = 1, + .hw_crc = 1, + .tsu = 1, +- .shift_rd0 = 1, + }; + + static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) +@@ -577,7 +576,6 @@ static struct sh_eth_cpu_data r8a7740_da + .hw_crc = 1, + .tsu = 1, + .select_mii = 1, +- .shift_rd0 = 1, + }; + + /* There is CPU dependent code */ +@@ -816,7 +814,6 @@ static struct sh_eth_cpu_data sh7734_dat + .tsu = 1, + .hw_crc = 1, + .select_mii = 1, +- .shift_rd0 = 1, + }; + + /* SH7763 */ +@@ -1428,7 +1425,7 @@ static int sh_eth_rx(struct net_device * + * the RFS bits are from bit 25 to bit 16. So, the + * driver needs right shifting by 16. + */ +- if (mdp->cd->shift_rd0) ++ if (mdp->cd->hw_crc) + desc_status >>= 16; + + skb = mdp->rx_skbuff[entry]; +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -490,7 +490,6 @@ struct sh_eth_cpu_data { + unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */ + unsigned hw_crc:1; /* E-DMAC have CSMR */ + unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */ +- unsigned shift_rd0:1; /* shift Rx descriptor word 0 right by 16 */ + unsigned rmiimode:1; /* EtherC has RMIIMODE register */ + unsigned rtrate:1; /* EtherC has RTRATE register */ + }; diff --git a/patches.renesas/0128-sh_eth-rename-sh_eth_cpu_data-hw_crc.patch b/patches.renesas/0128-sh_eth-rename-sh_eth_cpu_data-hw_crc.patch new file mode 100644 index 0000000000000..dedf3f05e79a3 --- /dev/null +++ b/patches.renesas/0128-sh_eth-rename-sh_eth_cpu_data-hw_crc.patch @@ -0,0 +1,84 @@ +From 540b4904331b6a08d85b36a258bda411444dd77f Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sat, 7 Jan 2017 00:03:37 +0300 +Subject: [PATCH 128/255] sh_eth: rename 'sh_eth_cpu_data::hw_crc' + +The 'struct sh_eth_cpu_data' field indicating the "intelligent checksum" +support was misnamed 'hw_crc' -- rename it to 'hw_checksum'. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 62e04b7e0e3c2926bdcbcced9feb22478258d0c3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 12 ++++++------ + drivers/net/ethernet/renesas/sh_eth.h | 2 +- + 2 files changed, 7 insertions(+), 7 deletions(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -535,7 +535,7 @@ static struct sh_eth_cpu_data r7s72100_d + .rpadir_value = 2 << 16, + .no_trimd = 1, + .no_ade = 1, +- .hw_crc = 1, ++ .hw_checksum = 1, + .tsu = 1, + }; + +@@ -573,7 +573,7 @@ static struct sh_eth_cpu_data r8a7740_da + .rpadir_value = 2 << 16, + .no_trimd = 1, + .no_ade = 1, +- .hw_crc = 1, ++ .hw_checksum = 1, + .tsu = 1, + .select_mii = 1, + }; +@@ -812,7 +812,7 @@ static struct sh_eth_cpu_data sh7734_dat + .no_trimd = 1, + .no_ade = 1, + .tsu = 1, +- .hw_crc = 1, ++ .hw_checksum = 1, + .select_mii = 1, + }; + +@@ -928,7 +928,7 @@ static int sh_eth_reset(struct net_devic + sh_eth_write(ndev, 0x0, RDFFR); + + /* Reset HW CRC register */ +- if (mdp->cd->hw_crc) ++ if (mdp->cd->hw_checksum) + sh_eth_write(ndev, 0x0, CSMR); + + /* Select MII mode */ +@@ -1425,7 +1425,7 @@ static int sh_eth_rx(struct net_device * + * the RFS bits are from bit 25 to bit 16. So, the + * driver needs right shifting by 16. + */ +- if (mdp->cd->hw_crc) ++ if (mdp->cd->hw_checksum) + desc_status >>= 16; + + skb = mdp->rx_skbuff[entry]; +@@ -1999,7 +1999,7 @@ static size_t __sh_eth_get_regs(struct n + add_reg(MAFCR); + if (cd->rtrate) + add_reg(RTRATE); +- if (cd->hw_crc) ++ if (cd->hw_checksum) + add_reg(CSMR); + if (cd->select_mii) + add_reg(RMII_MII); +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -488,7 +488,7 @@ struct sh_eth_cpu_data { + unsigned rpadir:1; /* E-DMAC have RPADIR */ + unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */ + unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */ +- unsigned hw_crc:1; /* E-DMAC have CSMR */ ++ unsigned hw_checksum:1; /* E-DMAC has CSMR */ + unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */ + unsigned rmiimode:1; /* EtherC has RMIIMODE register */ + unsigned rtrate:1; /* EtherC has RTRATE register */ diff --git a/patches.renesas/0129-sh_eth-use-correct-name-for-ECMR_MPDE-bit.patch b/patches.renesas/0129-sh_eth-use-correct-name-for-ECMR_MPDE-bit.patch new file mode 100644 index 0000000000000..f3828aca89232 --- /dev/null +++ b/patches.renesas/0129-sh_eth-use-correct-name-for-ECMR_MPDE-bit.patch @@ -0,0 +1,32 @@ +From 2fdf09534576e9392b4293cb4f49d223f27e8fdc Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Mon, 9 Jan 2017 16:34:04 +0100 +Subject: [PATCH 129/255] sh_eth: use correct name for ECMR_MPDE bit +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This bit was wrongly named due to a typo, Sergei checked the SH7734/63 +manuals and this bit should be named MPDE. + +Suggested-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 6dcf45e514974a1ff10755015b5e06746a033e5f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -339,7 +339,7 @@ enum FELIC_MODE_BIT { + ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, + ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, + ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, +- ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, ++ ECMR_MPDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, + ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, + ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001, + }; diff --git a/patches.renesas/0130-sh_eth-add-generic-wake-on-lan-support-via-magic-pac.patch b/patches.renesas/0130-sh_eth-add-generic-wake-on-lan-support-via-magic-pac.patch new file mode 100644 index 0000000000000..95a82e641d20c --- /dev/null +++ b/patches.renesas/0130-sh_eth-add-generic-wake-on-lan-support-via-magic-pac.patch @@ -0,0 +1,240 @@ +From af32eba20f34e1e9161e190398b03df6b76b3913 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Mon, 9 Jan 2017 16:34:05 +0100 +Subject: [PATCH 130/255] sh_eth: add generic wake-on-lan support via magic + packet +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add generic functionality to support Wake-on-LAN using MagicPacket which +are supported by at least a few versions of sh_eth. Only add +functionality for WoL, no specific sh_eth versions are marked to support +WoL yet. + +WoL is enabled in the suspend callback by setting MagicPacket detection +and disabling all interrupts expect MagicPacket. In the resume path the +driver needs to reset the hardware to rearm the WoL logic, this prevents +the driver from simply restoring the registers and to take advantage of +that sh_eth was not suspended to reduce resume time. To reset the +hardware the driver closes and reopens the device just like it would do +in a normal suspend/resume scenario without WoL enabled, but it both +closes and opens the device in the resume callback since the device +needs to be open for WoL to work. + +One quirk needed for WoL is that the module clock needs to be prevented +from being switched off by Runtime PM. To keep the clock alive the +suspend callback need to call clk_enable() directly to increase the +usage count of the clock. Then when Runtime PM decreases the clock usage +count it won't reach 0 and be switched off. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit d8981d029da9d230955dabe596dbb30e7971b7b9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 114 +++++++++++++++++++++++++++++++--- + drivers/net/ethernet/renesas/sh_eth.h | 3 + 2 files changed, 109 insertions(+), 8 deletions(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -1562,6 +1562,8 @@ static void sh_eth_emac_interrupt(struct + sh_eth_rcv_snd_enable(ndev); + } + } ++ if (felic_stat & ECSR_MPD) ++ pm_wakeup_event(&mdp->pdev->dev, 0); + } + + /* error control function */ +@@ -2211,6 +2213,33 @@ static int sh_eth_set_ringparam(struct n + return 0; + } + ++static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) ++{ ++ struct sh_eth_private *mdp = netdev_priv(ndev); ++ ++ wol->supported = 0; ++ wol->wolopts = 0; ++ ++ if (mdp->cd->magic && mdp->clk) { ++ wol->supported = WAKE_MAGIC; ++ wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; ++ } ++} ++ ++static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) ++{ ++ struct sh_eth_private *mdp = netdev_priv(ndev); ++ ++ if (!mdp->cd->magic || !mdp->clk || wol->wolopts & ~WAKE_MAGIC) ++ return -EOPNOTSUPP; ++ ++ mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); ++ ++ device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); ++ ++ return 0; ++} ++ + static const struct ethtool_ops sh_eth_ethtool_ops = { + .get_regs_len = sh_eth_get_regs_len, + .get_regs = sh_eth_get_regs, +@@ -2225,6 +2254,8 @@ static const struct ethtool_ops sh_eth_e + .set_ringparam = sh_eth_set_ringparam, + .get_link_ksettings = sh_eth_get_link_ksettings, + .set_link_ksettings = sh_eth_set_link_ksettings, ++ .get_wol = sh_eth_get_wol, ++ .set_wol = sh_eth_set_wol, + }; + + /* network device open function */ +@@ -3029,6 +3060,11 @@ static int sh_eth_drv_probe(struct platf + goto out_release; + } + ++ /* Get clock, if not found that's OK but Wake-On-Lan is unavailable */ ++ mdp->clk = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(mdp->clk)) ++ mdp->clk = NULL; ++ + ndev->base_addr = res->start; + + spin_lock_init(&mdp->lock); +@@ -3123,6 +3159,9 @@ static int sh_eth_drv_probe(struct platf + if (ret) + goto out_napi_del; + ++ if (mdp->cd->magic && mdp->clk) ++ device_set_wakeup_capable(&pdev->dev, 1); ++ + /* print device information */ + netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", + (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); +@@ -3162,15 +3201,67 @@ static int sh_eth_drv_remove(struct plat + + #ifdef CONFIG_PM + #ifdef CONFIG_PM_SLEEP ++static int sh_eth_wol_setup(struct net_device *ndev) ++{ ++ struct sh_eth_private *mdp = netdev_priv(ndev); ++ ++ /* Only allow ECI interrupts */ ++ synchronize_irq(ndev->irq); ++ napi_disable(&mdp->napi); ++ sh_eth_write(ndev, DMAC_M_ECI, EESIPR); ++ ++ /* Enable MagicPacket */ ++ sh_eth_modify(ndev, ECMR, 0, ECMR_MPDE); ++ ++ /* Increased clock usage so device won't be suspended */ ++ clk_enable(mdp->clk); ++ ++ return enable_irq_wake(ndev->irq); ++} ++ ++static int sh_eth_wol_restore(struct net_device *ndev) ++{ ++ struct sh_eth_private *mdp = netdev_priv(ndev); ++ int ret; ++ ++ napi_enable(&mdp->napi); ++ ++ /* Disable MagicPacket */ ++ sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); ++ ++ /* The device needs to be reset to restore MagicPacket logic ++ * for next wakeup. If we close and open the device it will ++ * both be reset and all registers restored. This is what ++ * happens during suspend and resume without WoL enabled. ++ */ ++ ret = sh_eth_close(ndev); ++ if (ret < 0) ++ return ret; ++ ret = sh_eth_open(ndev); ++ if (ret < 0) ++ return ret; ++ ++ /* Restore clock usage count */ ++ clk_disable(mdp->clk); ++ ++ return disable_irq_wake(ndev->irq); ++} ++ + static int sh_eth_suspend(struct device *dev) + { + struct net_device *ndev = dev_get_drvdata(dev); ++ struct sh_eth_private *mdp = netdev_priv(ndev); + int ret = 0; + +- if (netif_running(ndev)) { +- netif_device_detach(ndev); ++ if (!netif_running(ndev)) ++ return 0; ++ ++ netif_device_detach(ndev); ++ ++ if (mdp->wol_enabled) ++ ret = sh_eth_wol_setup(ndev); ++ else + ret = sh_eth_close(ndev); +- } + + return ret; + } +@@ -3178,14 +3269,21 @@ static int sh_eth_suspend(struct device + static int sh_eth_resume(struct device *dev) + { + struct net_device *ndev = dev_get_drvdata(dev); ++ struct sh_eth_private *mdp = netdev_priv(ndev); + int ret = 0; + +- if (netif_running(ndev)) { ++ if (!netif_running(ndev)) ++ return 0; ++ ++ if (mdp->wol_enabled) ++ ret = sh_eth_wol_restore(ndev); ++ else + ret = sh_eth_open(ndev); +- if (ret < 0) +- return ret; +- netif_device_attach(ndev); +- } ++ ++ if (ret < 0) ++ return ret; ++ ++ netif_device_attach(ndev); + + return ret; + } +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -492,6 +492,7 @@ struct sh_eth_cpu_data { + unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */ + unsigned rmiimode:1; /* EtherC has RMIIMODE register */ + unsigned rtrate:1; /* EtherC has RTRATE register */ ++ unsigned magic:1; /* EtherC has ECMR.MPDE and ECSR.MPD */ + }; + + struct sh_eth_private { +@@ -500,6 +501,7 @@ struct sh_eth_private { + const u16 *reg_offset; + void __iomem *addr; + void __iomem *tsu_addr; ++ struct clk *clk; + u32 num_rx_ring; + u32 num_tx_ring; + dma_addr_t rx_desc_dma; +@@ -528,6 +530,7 @@ struct sh_eth_private { + unsigned no_ether_link:1; + unsigned ether_link_active_low:1; + unsigned is_opened:1; ++ unsigned wol_enabled:1; + }; + + static inline void sh_eth_soft_swap(char *src, int len) diff --git a/patches.renesas/0131-sh_eth-enable-wake-on-lan-for-R-Car-Gen2-devices.patch b/patches.renesas/0131-sh_eth-enable-wake-on-lan-for-R-Car-Gen2-devices.patch new file mode 100644 index 0000000000000..7aad65f5d6e85 --- /dev/null +++ b/patches.renesas/0131-sh_eth-enable-wake-on-lan-for-R-Car-Gen2-devices.patch @@ -0,0 +1,42 @@ +From 5d19ffacfcffab22e15a62b0e3fbfc7045aad427 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Mon, 9 Jan 2017 16:34:06 +0100 +Subject: [PATCH 131/255] sh_eth: enable wake-on-lan for R-Car Gen2 devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Tested on Gen2 r8a7791/Koelsch. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit e410d86d4aa79a1a37231af6aacd93b2c4395c46) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -622,8 +622,9 @@ static struct sh_eth_cpu_data r8a779x_da + + .register_type = SH_ETH_REG_FAST_RCAR, + +- .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, +- .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, ++ .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, ++ .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | ++ ECSIPR_MPDIP, + .eesipr_value = 0x01ff009f, + + .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, +@@ -638,6 +639,7 @@ static struct sh_eth_cpu_data r8a779x_da + .tpauser = 1, + .hw_swap = 1, + .rmiimode = 1, ++ .magic = 1, + }; + #endif /* CONFIG_OF */ + diff --git a/patches.renesas/0132-sh_eth-enable-wake-on-lan-for-r8a7740-armadillo.patch b/patches.renesas/0132-sh_eth-enable-wake-on-lan-for-r8a7740-armadillo.patch new file mode 100644 index 0000000000000..84578e45fd379 --- /dev/null +++ b/patches.renesas/0132-sh_eth-enable-wake-on-lan-for-r8a7740-armadillo.patch @@ -0,0 +1,30 @@ +From 05156d52187d6e3f11b3d811bfe4e9141c9b4f7a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Mon, 9 Jan 2017 16:34:07 +0100 +Subject: [PATCH 132/255] sh_eth: enable wake-on-lan for r8a7740/armadillo +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Geert Uytterhoeven reported WoL worked on his Armadillo board. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 33017e240f489b6353e33f2630f2c5cbd2ad1d13) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -576,6 +576,7 @@ static struct sh_eth_cpu_data r8a7740_da + .hw_checksum = 1, + .tsu = 1, + .select_mii = 1, ++ .magic = 1, + }; + + /* There is CPU dependent code */ diff --git a/patches.renesas/0133-sh_eth-enable-wake-on-lan-for-sh7734.patch b/patches.renesas/0133-sh_eth-enable-wake-on-lan-for-sh7734.patch new file mode 100644 index 0000000000000..0ea4cd506ca3d --- /dev/null +++ b/patches.renesas/0133-sh_eth-enable-wake-on-lan-for-sh7734.patch @@ -0,0 +1,30 @@ +From c5ef1300917211318e9499d17e6d5654fc1164cd Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Mon, 9 Jan 2017 16:34:08 +0100 +Subject: [PATCH 133/255] sh_eth: enable wake-on-lan for sh7734 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This is based on public datasheet for sh7734 which shows it has the +same behavior and registers for WoL as other versions of sh_eth. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 159c2a90442c6d5ad0b3d085e348979cd9a0ac1b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -817,6 +817,7 @@ static struct sh_eth_cpu_data sh7734_dat + .tsu = 1, + .hw_checksum = 1, + .select_mii = 1, ++ .magic = 1, + }; + + /* SH7763 */ diff --git a/patches.renesas/0134-sh_eth-enable-wake-on-lan-for-sh7763.patch b/patches.renesas/0134-sh_eth-enable-wake-on-lan-for-sh7763.patch new file mode 100644 index 0000000000000..33c3f0371ebe5 --- /dev/null +++ b/patches.renesas/0134-sh_eth-enable-wake-on-lan-for-sh7763.patch @@ -0,0 +1,30 @@ +From c387506d71ab35dc7ca5ab088224a6ea688a7aa9 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Mon, 9 Jan 2017 16:34:09 +0100 +Subject: [PATCH 134/255] sh_eth: enable wake-on-lan for sh7763 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This is based on public datasheet for sh7763 which shows it has the +same behavior and registers for WoL as other versions of sh_eth. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 267e1d5c7473cdb264c3153bf2adeb9d0c4bcae3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -845,6 +845,7 @@ static struct sh_eth_cpu_data sh7763_dat + .no_ade = 1, + .tsu = 1, + .irq_flags = IRQF_SHARED, ++ .magic = 1, + }; + + static struct sh_eth_cpu_data sh7619_data = { diff --git a/patches.renesas/0135-sh_eth-rename-EESIPR-bits.patch b/patches.renesas/0135-sh_eth-rename-EESIPR-bits.patch new file mode 100644 index 0000000000000..70235a14ae88e --- /dev/null +++ b/patches.renesas/0135-sh_eth-rename-EESIPR-bits.patch @@ -0,0 +1,163 @@ +From a6267861befde50cf80aa74195f0854b914a6b38 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 29 Jan 2017 15:07:34 +0300 +Subject: [PATCH 135/255] sh_eth: rename EESIPR bits + +Since the commit b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth") +the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with +the *enum* declaring the EESR bits (interrupt status) WRT bit naming and +formatting. I'd like to restore the consistency by using EESIPR as the bit +name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the +bits according to the available Renesas SH77{34|63} manuals; additionally, +reconstruct couple names using the EESR bit declaration above... + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 1a0bee6c1e788218fd1d141db320db970aace7f0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 22 ++++++++++---------- + drivers/net/ethernet/renesas/sh_eth.h | 36 +++++++++++++++++++++------------- + 2 files changed, 34 insertions(+), 24 deletions(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -556,7 +556,7 @@ static struct sh_eth_cpu_data r8a7740_da + + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, +- .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, + + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | +@@ -702,7 +702,7 @@ static struct sh_eth_cpu_data sh7757_dat + + .register_type = SH_ETH_REG_FAST_SH4, + +- .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, + + .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | +@@ -769,7 +769,7 @@ static struct sh_eth_cpu_data sh7757_dat + + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, +- .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, + + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | +@@ -800,7 +800,7 @@ static struct sh_eth_cpu_data sh7734_dat + + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, +- .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff, + + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | +@@ -830,7 +830,7 @@ static struct sh_eth_cpu_data sh7763_dat + + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, +- .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff, + + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | +@@ -851,7 +851,7 @@ static struct sh_eth_cpu_data sh7763_dat + static struct sh_eth_cpu_data sh7619_data = { + .register_type = SH_ETH_REG_FAST_SH3_SH2, + +- .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, + + .apr = 1, + .mpr = 1, +@@ -862,7 +862,7 @@ static struct sh_eth_cpu_data sh7619_dat + static struct sh_eth_cpu_data sh771x_data = { + .register_type = SH_ETH_REG_FAST_SH3_SH2, + +- .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, + .tsu = 1, + }; + +@@ -1559,10 +1559,10 @@ static void sh_eth_emac_interrupt(struct + sh_eth_rcv_snd_disable(ndev); + } else { + /* Link Up */ +- sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0); ++ sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); + /* clear int */ + sh_eth_modify(ndev, ECSR, 0, 0); +- sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, DMAC_M_ECI); ++ sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); + /* enable tx and rx */ + sh_eth_rcv_snd_enable(ndev); + } +@@ -1664,7 +1664,7 @@ static irqreturn_t sh_eth_interrupt(int + * bit... + */ + intr_enable = sh_eth_read(ndev, EESIPR); +- intr_status &= intr_enable | DMAC_M_ECI; ++ intr_status &= intr_enable | EESIPR_ECIIP; + if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | + cd->eesr_err_check)) + ret = IRQ_HANDLED; +@@ -3213,7 +3213,7 @@ static int sh_eth_wol_setup(struct net_d + /* Only allow ECI interrupts */ + synchronize_irq(ndev->irq); + napi_disable(&mdp->napi); +- sh_eth_write(ndev, DMAC_M_ECI, EESIPR); ++ sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); + + /* Enable MagicPacket */ + sh_eth_modify(ndev, ECMR, 0, ECMR_MPDE); +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -268,19 +268,29 @@ enum EESR_BIT { + EESR_TFE | EESR_TDE) + + /* EESIPR */ +-enum DMAC_IM_BIT { +- DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, +- DMAC_M_RABT = 0x02000000, +- DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, +- DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, +- DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, +- DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, +- DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, +- DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, +- DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, +- DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, +- DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, +- DMAC_M_RINT1 = 0x00000001, ++enum EESIPR_BIT { ++ EESIPR_TWBIP = 0x40000000, ++ EESIPR_TABTIP = 0x04000000, ++ EESIPR_RABTIP = 0x02000000, ++ EESIPR_RFCOFIP = 0x01000000, ++ EESIPR_ADEIP = 0x00800000, ++ EESIPR_ECIIP = 0x00400000, ++ EESIPR_FTCIP = 0x00200000, ++ EESIPR_TDEIP = 0x00100000, ++ EESIPR_TFUFIP = 0x00080000, ++ EESIPR_FRIP = 0x00040000, ++ EESIPR_RDEIP = 0x00020000, ++ EESIPR_RFOFIP = 0x00010000, ++ EESIPR_CNDIP = 0x00000800, ++ EESIPR_DLCIP = 0x00000400, ++ EESIPR_CDIP = 0x00000200, ++ EESIPR_TROIP = 0x00000100, ++ EESIPR_RMAFIP = 0x00000080, ++ EESIPR_RRFIP = 0x00000010, ++ EESIPR_RTLFIP = 0x00000008, ++ EESIPR_RTSFIP = 0x00000004, ++ EESIPR_PREIP = 0x00000002, ++ EESIPR_CERFIP = 0x00000001, + }; + + /* Receive descriptor 0 bits */ diff --git a/patches.renesas/0136-sh_eth-add-missing-EESIPR-bits.patch b/patches.renesas/0136-sh_eth-add-missing-EESIPR-bits.patch new file mode 100644 index 0000000000000..a6a0cf440a878 --- /dev/null +++ b/patches.renesas/0136-sh_eth-add-missing-EESIPR-bits.patch @@ -0,0 +1,50 @@ +From 26ecbecd6029de480455b69fd8b37017a08f6be4 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 29 Jan 2017 15:08:09 +0300 +Subject: [PATCH 136/255] sh_eth: add missing EESIPR bits + +Renesas SH77{34|63} manuals describe more EESIPR bits than the current +driver. Declare the new bits with the end goal of using the bit names +instead of the bare numbers for the 'sh_eth_cpu_data::eesipr_value' +initializers... + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 00300b2aac27556e2829cfd047b787af0f13b081) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.h | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.h ++++ b/drivers/net/ethernet/renesas/sh_eth.h +@@ -269,13 +269,17 @@ enum EESR_BIT { + + /* EESIPR */ + enum EESIPR_BIT { +- EESIPR_TWBIP = 0x40000000, ++ EESIPR_TWB1IP = 0x80000000, ++ EESIPR_TWBIP = 0x40000000, /* same as TWB0IP */ ++ EESIPR_TC1IP = 0x20000000, ++ EESIPR_TUCIP = 0x10000000, ++ EESIPR_ROCIP = 0x08000000, + EESIPR_TABTIP = 0x04000000, + EESIPR_RABTIP = 0x02000000, + EESIPR_RFCOFIP = 0x01000000, + EESIPR_ADEIP = 0x00800000, + EESIPR_ECIIP = 0x00400000, +- EESIPR_FTCIP = 0x00200000, ++ EESIPR_FTCIP = 0x00200000, /* same as TC0IP */ + EESIPR_TDEIP = 0x00100000, + EESIPR_TFUFIP = 0x00080000, + EESIPR_FRIP = 0x00040000, +@@ -286,6 +290,8 @@ enum EESIPR_BIT { + EESIPR_CDIP = 0x00000200, + EESIPR_TROIP = 0x00000100, + EESIPR_RMAFIP = 0x00000080, ++ EESIPR_CEEFIP = 0x00000040, ++ EESIPR_CELFIP = 0x00000020, + EESIPR_RRFIP = 0x00000010, + EESIPR_RTLFIP = 0x00000008, + EESIPR_RTSFIP = 0x00000004, diff --git a/patches.renesas/0137-sh_eth-stop-using-bare-numbers-for-EESIPR-values.patch b/patches.renesas/0137-sh_eth-stop-using-bare-numbers-for-EESIPR-values.patch new file mode 100644 index 0000000000000..485cfd81c7183 --- /dev/null +++ b/patches.renesas/0137-sh_eth-stop-using-bare-numbers-for-EESIPR-values.patch @@ -0,0 +1,189 @@ +From d0255e529160e52320a2a30d9b7ed69fde33f5a6 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 29 Jan 2017 15:13:48 +0300 +Subject: [PATCH 137/255] sh_eth: stop using bare numbers for EESIPR values + +Now that we have almost all EESIPR bits declared (and those that are +still not are most probably reserved anyway) we can at last replace the +bare numbers used for 'sh_eth_cpu_data::eesipr_value' initializers with +the bit names ORed together... + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 2b2d3eb41c920b47df2fcedd1489cf748bd09466) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 91 +++++++++++++++++++++++++++++----- + 1 file changed, 80 insertions(+), 11 deletions(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -518,7 +518,14 @@ static struct sh_eth_cpu_data r7s72100_d + + .ecsr_value = ECSR_ICD, + .ecsipr_value = ECSIPR_ICDIP, +- .eesipr_value = 0xe77f009f, ++ .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | ++ EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | ++ EESIPR_ECIIP | ++ EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | ++ EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | ++ EESIPR_RMAFIP | EESIPR_RRFIP | ++ EESIPR_RTLFIP | EESIPR_RTSFIP | ++ EESIPR_PREIP | EESIPR_CERFIP, + + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | +@@ -556,7 +563,14 @@ static struct sh_eth_cpu_data r8a7740_da + + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, +- .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | ++ EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | ++ EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | ++ 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | ++ EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | ++ EESIPR_CEEFIP | EESIPR_CELFIP | ++ EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | ++ EESIPR_PREIP | EESIPR_CERFIP, + + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | +@@ -603,7 +617,12 @@ static struct sh_eth_cpu_data r8a777x_da + + .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, + .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, +- .eesipr_value = 0x01ff009f, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | ++ EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | ++ EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | ++ EESIPR_RMAFIP | EESIPR_RRFIP | ++ EESIPR_RTLFIP | EESIPR_RTSFIP | ++ EESIPR_PREIP | EESIPR_CERFIP, + + .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | +@@ -626,7 +645,12 @@ static struct sh_eth_cpu_data r8a779x_da + .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | + ECSIPR_MPDIP, +- .eesipr_value = 0x01ff009f, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | ++ EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | ++ EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | ++ EESIPR_RMAFIP | EESIPR_RRFIP | ++ EESIPR_RTLFIP | EESIPR_RTSFIP | ++ EESIPR_PREIP | EESIPR_CERFIP, + + .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | +@@ -667,7 +691,12 @@ static struct sh_eth_cpu_data sh7724_dat + + .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, + .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, +- .eesipr_value = 0x01ff009f, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | ++ EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | ++ EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | ++ EESIPR_RMAFIP | EESIPR_RRFIP | ++ EESIPR_RTLFIP | EESIPR_RTSFIP | ++ EESIPR_PREIP | EESIPR_CERFIP, + + .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | +@@ -702,7 +731,14 @@ static struct sh_eth_cpu_data sh7757_dat + + .register_type = SH_ETH_REG_FAST_SH4, + +- .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | ++ EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | ++ EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | ++ 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | ++ EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | ++ EESIPR_CEEFIP | EESIPR_CELFIP | ++ EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | ++ EESIPR_PREIP | EESIPR_CERFIP, + + .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, + .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | +@@ -769,7 +805,14 @@ static struct sh_eth_cpu_data sh7757_dat + + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, +- .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | ++ EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | ++ EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | ++ 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | ++ EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | ++ EESIPR_CEEFIP | EESIPR_CELFIP | ++ EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | ++ EESIPR_PREIP | EESIPR_CERFIP, + + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | +@@ -800,7 +843,13 @@ static struct sh_eth_cpu_data sh7734_dat + + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, +- .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | ++ EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | ++ EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | ++ EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | ++ EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | ++ EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | ++ EESIPR_PREIP | EESIPR_CERFIP, + + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | +@@ -830,7 +879,13 @@ static struct sh_eth_cpu_data sh7763_dat + + .ecsr_value = ECSR_ICD | ECSR_MPD, + .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, +- .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | ++ EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | ++ EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | ++ EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | ++ EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | ++ EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | ++ EESIPR_PREIP | EESIPR_CERFIP, + + .tx_check = EESR_TC1 | EESR_FTC, + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | +@@ -851,7 +906,14 @@ static struct sh_eth_cpu_data sh7763_dat + static struct sh_eth_cpu_data sh7619_data = { + .register_type = SH_ETH_REG_FAST_SH3_SH2, + +- .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | ++ EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | ++ EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | ++ 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | ++ EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | ++ EESIPR_CEEFIP | EESIPR_CELFIP | ++ EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | ++ EESIPR_PREIP | EESIPR_CERFIP, + + .apr = 1, + .mpr = 1, +@@ -862,7 +924,14 @@ static struct sh_eth_cpu_data sh7619_dat + static struct sh_eth_cpu_data sh771x_data = { + .register_type = SH_ETH_REG_FAST_SH3_SH2, + +- .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, ++ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | ++ EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | ++ EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | ++ 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | ++ EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | ++ EESIPR_CEEFIP | EESIPR_CELFIP | ++ EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | ++ EESIPR_PREIP | EESIPR_CERFIP, + .tsu = 1, + }; + diff --git a/patches.renesas/0138-sh_eth-align-usage-of-sh_eth_modify-with-rest-of-dri.patch b/patches.renesas/0138-sh_eth-align-usage-of-sh_eth_modify-with-rest-of-dri.patch new file mode 100644 index 0000000000000..008dff888234d --- /dev/null +++ b/patches.renesas/0138-sh_eth-align-usage-of-sh_eth_modify-with-rest-of-dri.patch @@ -0,0 +1,35 @@ +From 30310fbf294abeb239bef88dfdfd33ce1e230f1c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Wed, 1 Feb 2017 15:41:54 +0100 +Subject: [PATCH 138/255] sh_eth: align usage of sh_eth_modify() with rest of + driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +To be consistent with the rest of the driver when setting bits using +sh_eth_modify() the same bit should also be cleared. This have no +functional change and should have been done from the start. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Suggested-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 5e2ed1329ee074229d5a2f4389035be818120980) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -3285,7 +3285,7 @@ static int sh_eth_wol_setup(struct net_d + sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); + + /* Enable MagicPacket */ +- sh_eth_modify(ndev, ECMR, 0, ECMR_MPDE); ++ sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); + + /* Increased clock usage so device won't be suspended */ + clk_enable(mdp->clk); diff --git a/patches.renesas/0139-sh_eth-fix-wakeup-event-reporting-from-MagicPacket.patch b/patches.renesas/0139-sh_eth-fix-wakeup-event-reporting-from-MagicPacket.patch new file mode 100644 index 0000000000000..e6f78dab87c14 --- /dev/null +++ b/patches.renesas/0139-sh_eth-fix-wakeup-event-reporting-from-MagicPacket.patch @@ -0,0 +1,44 @@ +From 58f11ee80caf5df895a4167e4298812f2fa995f0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Wed, 1 Feb 2017 15:41:55 +0100 +Subject: [PATCH 139/255] sh_eth: fix wakeup event reporting from MagicPacket +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +If a link change interrupt happens along side the MagicPacket interrupt +and the link change interrupt is ignored the interrupt handler will +return and the wakeup event is not registered. Fix this by moving the +MagicPacket check before the link change check. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Reported-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 0cf45a3b1e2c47bbcc9e75cbed5c660492e297da) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -1617,6 +1617,8 @@ static void sh_eth_emac_interrupt(struct + sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ + if (felic_stat & ECSR_ICD) + ndev->stats.tx_carrier_errors++; ++ if (felic_stat & ECSR_MPD) ++ pm_wakeup_event(&mdp->pdev->dev, 0); + if (felic_stat & ECSR_LCHNG) { + /* Link Changed */ + if (mdp->cd->no_psr || mdp->no_ether_link) +@@ -1636,8 +1638,6 @@ static void sh_eth_emac_interrupt(struct + sh_eth_rcv_snd_enable(ndev); + } + } +- if (felic_stat & ECSR_MPD) +- pm_wakeup_event(&mdp->pdev->dev, 0); + } + + /* error control function */ diff --git a/patches.renesas/0140-mmc-sh_mmcif-Remove-unused-use_cd_gpio-cd_gpio-from-.patch b/patches.renesas/0140-mmc-sh_mmcif-Remove-unused-use_cd_gpio-cd_gpio-from-.patch new file mode 100644 index 0000000000000..73e79a5e5fb66 --- /dev/null +++ b/patches.renesas/0140-mmc-sh_mmcif-Remove-unused-use_cd_gpio-cd_gpio-from-.patch @@ -0,0 +1,44 @@ +From 42818e0eaad81d5c85d703f9b1af1002379a6547 Mon Sep 17 00:00:00 2001 +From: Ulf Hansson <ulf.hansson@linaro.org> +Date: Fri, 30 Dec 2016 13:47:16 +0100 +Subject: [PATCH 140/255] mmc: sh_mmcif: Remove unused use_cd_gpio/cd_gpio from + platform data + +Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Reviewed-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 95cc4df716a210a19f0611215c49484d460250fd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mmcif.c | 6 ------ + include/linux/mmc/sh_mmcif.h | 2 -- + 2 files changed, 8 deletions(-) + +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -1509,12 +1509,6 @@ static int sh_mmcif_probe(struct platfor + } + } + +- if (pd && pd->use_cd_gpio) { +- ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); +- if (ret < 0) +- goto err_clk; +- } +- + mutex_init(&host->thread_lock); + + ret = mmc_add_host(mmc); +--- a/include/linux/mmc/sh_mmcif.h ++++ b/include/linux/mmc/sh_mmcif.h +@@ -35,10 +35,8 @@ struct sh_mmcif_plat_data { + int (*get_cd)(struct platform_device *pdef); + unsigned int slave_id_tx; /* embedded slave_id_[tr]x */ + unsigned int slave_id_rx; +- bool use_cd_gpio : 1; + bool ccs_unsupported : 1; + bool clk_ctrl2_present : 1; +- unsigned int cd_gpio; + u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */ + unsigned long caps; + u32 ocr; diff --git a/patches.renesas/0141-mmc-sh_mmcif-Remove-unused-get_cd-platform-callback.patch b/patches.renesas/0141-mmc-sh_mmcif-Remove-unused-get_cd-platform-callback.patch new file mode 100644 index 0000000000000..71d3177121d46 --- /dev/null +++ b/patches.renesas/0141-mmc-sh_mmcif-Remove-unused-get_cd-platform-callback.patch @@ -0,0 +1,59 @@ +From ecd167ab43ff8a80c1c7d2fc4468e63c15388113 Mon Sep 17 00:00:00 2001 +From: Ulf Hansson <ulf.hansson@linaro.org> +Date: Fri, 30 Dec 2016 13:47:17 +0100 +Subject: [PATCH 141/255] mmc: sh_mmcif: Remove unused ->get_cd() platform + callback + +Removing the callback also enables us to remove the sh_mmcif_get_cd() +altogether, as we convert to use mmc_gpio_get_cd() to the same kind of +work. + +Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 5957eeba530747e9d77daf2f300a186758be51d9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mmcif.c | 18 +----------------- + include/linux/mmc/sh_mmcif.h | 1 - + 2 files changed, 1 insertion(+), 18 deletions(-) + +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -1079,26 +1079,10 @@ static void sh_mmcif_set_ios(struct mmc_ + host->state = STATE_IDLE; + } + +-static int sh_mmcif_get_cd(struct mmc_host *mmc) +-{ +- struct sh_mmcif_host *host = mmc_priv(mmc); +- struct device *dev = sh_mmcif_host_to_dev(host); +- struct sh_mmcif_plat_data *p = dev->platform_data; +- int ret = mmc_gpio_get_cd(mmc); +- +- if (ret >= 0) +- return ret; +- +- if (!p || !p->get_cd) +- return -ENOSYS; +- else +- return p->get_cd(host->pd); +-} +- + static struct mmc_host_ops sh_mmcif_ops = { + .request = sh_mmcif_request, + .set_ios = sh_mmcif_set_ios, +- .get_cd = sh_mmcif_get_cd, ++ .get_cd = mmc_gpio_get_cd, + }; + + static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) +--- a/include/linux/mmc/sh_mmcif.h ++++ b/include/linux/mmc/sh_mmcif.h +@@ -32,7 +32,6 @@ + */ + + struct sh_mmcif_plat_data { +- int (*get_cd)(struct platform_device *pdef); + unsigned int slave_id_tx; /* embedded slave_id_[tr]x */ + unsigned int slave_id_rx; + bool ccs_unsupported : 1; diff --git a/patches.renesas/0142-mmc-sh_mmcif-Remove-unused-ccs_unsupported-from-the-.patch b/patches.renesas/0142-mmc-sh_mmcif-Remove-unused-ccs_unsupported-from-the-.patch new file mode 100644 index 0000000000000..0490633496a3d --- /dev/null +++ b/patches.renesas/0142-mmc-sh_mmcif-Remove-unused-ccs_unsupported-from-the-.patch @@ -0,0 +1,44 @@ +From 38db03ca6ac142eedb5eece18d8a0e0ae500064a Mon Sep 17 00:00:00 2001 +From: Ulf Hansson <ulf.hansson@linaro.org> +Date: Fri, 30 Dec 2016 13:47:18 +0100 +Subject: [PATCH 142/255] mmc: sh_mmcif: Remove unused ccs_unsupported from the + platform data + +There are currently no users of the ccs_unsupported member from the +platform data, so let's remove it. + +Note, as some of the sh_mmcif variants may not support ccs, let's keep the +current code in the driver, which deals with this. For future support, we +should invent a DT binding instead, but let's leave that until it's needed. + +Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Reviewed-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit 8020f71117042ed82287e4f51c48b57ce4c783df) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mmcif.c | 2 +- + include/linux/mmc/sh_mmcif.h | 1 - + 2 files changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -1427,7 +1427,7 @@ static int sh_mmcif_probe(struct platfor + host->mmc = mmc; + host->addr = reg; + host->timeout = msecs_to_jiffies(10000); +- host->ccs_enable = !pd || !pd->ccs_unsupported; ++ host->ccs_enable = true; + host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; + + host->pd = pdev; +--- a/include/linux/mmc/sh_mmcif.h ++++ b/include/linux/mmc/sh_mmcif.h +@@ -34,7 +34,6 @@ + struct sh_mmcif_plat_data { + unsigned int slave_id_tx; /* embedded slave_id_[tr]x */ + unsigned int slave_id_rx; +- bool ccs_unsupported : 1; + bool clk_ctrl2_present : 1; + u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */ + unsigned long caps; diff --git a/patches.renesas/0143-mmc-sh_mmcif-Remove-unused-clk_ctrl2_present-from-th.patch b/patches.renesas/0143-mmc-sh_mmcif-Remove-unused-clk_ctrl2_present-from-th.patch new file mode 100644 index 0000000000000..ad7a11819242a --- /dev/null +++ b/patches.renesas/0143-mmc-sh_mmcif-Remove-unused-clk_ctrl2_present-from-th.patch @@ -0,0 +1,45 @@ +From 2b07b253ed3c3b19d94222ff4f238224de24420e Mon Sep 17 00:00:00 2001 +From: Ulf Hansson <ulf.hansson@linaro.org> +Date: Fri, 30 Dec 2016 13:47:19 +0100 +Subject: [PATCH 143/255] mmc: sh_mmcif: Remove unused clk_ctrl2_present from + the platform data + +There are currently no users of the clk_ctrl2_present member from the +platform data, so let's remove it. + +Note, as some of the sh_mmcif variants may support clk_ctrl2, let's keep +the current code in the driver, which deals with this. For future support, +we should invent a DT binding instead, but let's leave that until it's +needed. + +Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Reviewed-by: Linus Walleij <linus.walleij@linaro.org> +(cherry picked from commit dba4bb484e9e495478f2bcf474393d33f7e0ec27) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mmcif.c | 2 +- + include/linux/mmc/sh_mmcif.h | 1 - + 2 files changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/mmc/host/sh_mmcif.c ++++ b/drivers/mmc/host/sh_mmcif.c +@@ -1428,7 +1428,7 @@ static int sh_mmcif_probe(struct platfor + host->addr = reg; + host->timeout = msecs_to_jiffies(10000); + host->ccs_enable = true; +- host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; ++ host->clk_ctrl2_enable = false; + + host->pd = pdev; + +--- a/include/linux/mmc/sh_mmcif.h ++++ b/include/linux/mmc/sh_mmcif.h +@@ -34,7 +34,6 @@ + struct sh_mmcif_plat_data { + unsigned int slave_id_tx; /* embedded slave_id_[tr]x */ + unsigned int slave_id_rx; +- bool clk_ctrl2_present : 1; + u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */ + unsigned long caps; + u32 ocr; diff --git a/patches.renesas/0144-mmc-tmio-use-SDIO-master-interrupt-bit-only-when-all.patch b/patches.renesas/0144-mmc-tmio-use-SDIO-master-interrupt-bit-only-when-all.patch new file mode 100644 index 0000000000000..f3c2301757232 --- /dev/null +++ b/patches.renesas/0144-mmc-tmio-use-SDIO-master-interrupt-bit-only-when-all.patch @@ -0,0 +1,58 @@ +From af0d980752ec94e3e66d8da378ca0a1808839460 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Fri, 9 Dec 2016 17:51:41 +0100 +Subject: [PATCH 144/255] mmc: tmio: use SDIO master interrupt bit only when + allowed + +The master bit to enable SDIO interrupts can only be accessed if +SCLKDIVEN bit allows that. However, the core uses the SDIO enable +callback at times when SCLKDIVEN forbids the change. This leads to +"timeout waiting for SD bus idle" messages. + +We now activate the master bit in probe once if SDIO is supported. IRQ +en-/disabling will be done now by the individual IRQ enablement bits +only. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Reviewed-by: Yasushi SHOJI <yashi@atmark-techno.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit c51ff6c6180e76a1ba96aef799a9c41aa80fcc95) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -140,12 +140,10 @@ static void tmio_mmc_enable_sdio_irq(str + + host->sdio_irq_mask = TMIO_SDIO_MASK_ALL & + ~TMIO_SDIO_STAT_IOIRQ; +- sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001); + sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask); + } else if (!enable && host->sdio_irq_enabled) { + host->sdio_irq_mask = TMIO_SDIO_MASK_ALL; + sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask); +- sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000); + + host->sdio_irq_enabled = false; + pm_runtime_mark_last_busy(mmc_dev(mmc)); +@@ -1232,7 +1230,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_ + if (pdata->flags & TMIO_MMC_SDIO_IRQ) { + _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL; + sd_ctrl_write16(_host, CTL_SDIO_IRQ_MASK, _host->sdio_irq_mask); +- sd_ctrl_write16(_host, CTL_TRANSACTION_CTL, 0x0000); ++ sd_ctrl_write16(_host, CTL_TRANSACTION_CTL, 0x0001); + } + + spin_lock_init(&_host->lock); +@@ -1280,6 +1278,9 @@ void tmio_mmc_host_remove(struct tmio_mm + struct platform_device *pdev = host->pdev; + struct mmc_host *mmc = host->mmc; + ++ if (host->pdata->flags & TMIO_MMC_SDIO_IRQ) ++ sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000); ++ + if (!host->native_hotplug) + pm_runtime_get_sync(&pdev->dev); + diff --git a/patches.renesas/0145-mmc-sh_mobile_sdhi-simplify-accessing-DT-data.patch b/patches.renesas/0145-mmc-sh_mobile_sdhi-simplify-accessing-DT-data.patch new file mode 100644 index 0000000000000..3b2b1de1ddecf --- /dev/null +++ b/patches.renesas/0145-mmc-sh_mobile_sdhi-simplify-accessing-DT-data.patch @@ -0,0 +1,57 @@ +From 374fc32c3ddab4d815ec3cd7144d3d30a3a5f828 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Mon, 12 Dec 2016 20:51:20 +0100 +Subject: [PATCH 145/255] mmc: sh_mobile_sdhi: simplify accessing DT data + +By using the helper of_device_get_match_data(), we can skip some +checking and make the code simpler. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit dc9f1a8d790ee766c47eca163261225680691e64) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 14 ++++---------- + 1 file changed, 4 insertions(+), 10 deletions(-) + +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -556,8 +556,7 @@ static void sh_mobile_sdhi_enable_dma(st + + static int sh_mobile_sdhi_probe(struct platform_device *pdev) + { +- const struct of_device_id *of_id = +- of_match_device(sh_mobile_sdhi_of_match, &pdev->dev); ++ const struct sh_mobile_sdhi_of_data *of_data = of_device_get_match_data(&pdev->dev); + struct sh_mobile_sdhi *priv; + struct tmio_mmc_data *mmc_data; + struct tmio_mmc_data *mmd = pdev->dev.platform_data; +@@ -598,9 +597,8 @@ static int sh_mobile_sdhi_probe(struct p + goto eprobe; + } + +- if (of_id && of_id->data) { +- const struct sh_mobile_sdhi_of_data *of_data = of_id->data; + ++ if (of_data) { + mmc_data->flags |= of_data->tmio_flags; + mmc_data->ocr_mask = of_data->tmio_ocr_mask; + mmc_data->capabilities |= of_data->capabilities; +@@ -671,14 +669,10 @@ static int sh_mobile_sdhi_probe(struct p + if (host->mmc->caps & MMC_CAP_UHS_SDR104) { + host->mmc->caps |= MMC_CAP_HW_RESET; + +- if (of_id && of_id->data) { +- const struct sh_mobile_sdhi_of_data *of_data; +- const struct sh_mobile_sdhi_scc *taps; ++ if (of_data) { ++ const struct sh_mobile_sdhi_scc *taps = of_data->taps; + bool hit = false; + +- of_data = of_id->data; +- taps = of_data->taps; +- + for (i = 0; i < of_data->taps_num; i++) { + if (taps[i].clk_rate == 0 || + taps[i].clk_rate == host->mmc->f_max) { diff --git a/patches.renesas/0146-mmc-sh_mobile_sdhi-improve-prerequisite-for-hw_reset.patch b/patches.renesas/0146-mmc-sh_mobile_sdhi-improve-prerequisite-for-hw_reset.patch new file mode 100644 index 0000000000000..629ff03374277 --- /dev/null +++ b/patches.renesas/0146-mmc-sh_mobile_sdhi-improve-prerequisite-for-hw_reset.patch @@ -0,0 +1,64 @@ +From c86823eb28834f75c555a0a7262b9676107b9908 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Mon, 12 Dec 2016 20:51:21 +0100 +Subject: [PATCH 146/255] mmc: sh_mobile_sdhi: improve prerequisite for + hw_reset + +We need a SCC unit for hw_reset. Those units can only be described in +of_data. So, of_data and a valid SCC offset are prerequisites for +enabling the hw_reset capability. Merge the two 'if' conditions into one +and add a check for an scc offset. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 6ade9a2c2da855ff38e74c4298976400feca968e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 30 ++++++++++++++---------------- + 1 file changed, 14 insertions(+), 16 deletions(-) + +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -666,27 +666,25 @@ static int sh_mobile_sdhi_probe(struct p + if (ret < 0) + goto efree; + +- if (host->mmc->caps & MMC_CAP_UHS_SDR104) { ++ if (of_data && of_data->scc_offset && host->mmc->caps & MMC_CAP_UHS_SDR104) { ++ const struct sh_mobile_sdhi_scc *taps = of_data->taps; ++ bool hit = false; ++ + host->mmc->caps |= MMC_CAP_HW_RESET; + +- if (of_data) { +- const struct sh_mobile_sdhi_scc *taps = of_data->taps; +- bool hit = false; +- +- for (i = 0; i < of_data->taps_num; i++) { +- if (taps[i].clk_rate == 0 || +- taps[i].clk_rate == host->mmc->f_max) { +- host->scc_tappos = taps->tap; +- hit = true; +- break; +- } ++ for (i = 0; i < of_data->taps_num; i++) { ++ if (taps[i].clk_rate == 0 || ++ taps[i].clk_rate == host->mmc->f_max) { ++ host->scc_tappos = taps->tap; ++ hit = true; ++ break; + } ++ } + +- if (!hit) +- dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n"); ++ if (!hit) ++ dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n"); + +- priv->scc_ctl = host->ctl + of_data->scc_offset; +- } ++ priv->scc_ctl = host->ctl + of_data->scc_offset; + } + + i = 0; diff --git a/patches.renesas/0147-mmc-sh_mobile_sdhi-improve-prerequisites-for-tuning.patch b/patches.renesas/0147-mmc-sh_mobile_sdhi-improve-prerequisites-for-tuning.patch new file mode 100644 index 0000000000000..5b08d3073ff2a --- /dev/null +++ b/patches.renesas/0147-mmc-sh_mobile_sdhi-improve-prerequisites-for-tuning.patch @@ -0,0 +1,53 @@ +From 6fcc6d9f216baf519067987fc4e058e29ba2f64c Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Mon, 12 Dec 2016 20:51:22 +0100 +Subject: [PATCH 147/255] mmc: sh_mobile_sdhi: improve prerequisites for tuning + +Prerequisites for tuning are the same as for hw_reset. We need an SCC +and a supported mode. Populate the tuning related functions only when +those conditions are met. This also removes a tiny race window. +Previously, the functions were populated when the SCC offset was not +initialized which could have led to an OOPS. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit e831ead3b3ddc4227cef10dc63d919fd7242d7b8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -621,11 +621,6 @@ static int sh_mobile_sdhi_probe(struct p + host->card_busy = sh_mobile_sdhi_card_busy; + host->start_signal_voltage_switch = + sh_mobile_sdhi_start_signal_voltage_switch; +- host->init_tuning = sh_mobile_sdhi_init_tuning; +- host->prepare_tuning = sh_mobile_sdhi_prepare_tuning; +- host->select_tuning = sh_mobile_sdhi_select_tuning; +- host->check_scc_error = sh_mobile_sdhi_check_scc_error; +- host->hw_reset = sh_mobile_sdhi_hw_reset; + } + + /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ +@@ -666,6 +661,7 @@ static int sh_mobile_sdhi_probe(struct p + if (ret < 0) + goto efree; + ++ /* Enable tuning iff we have an SCC and a supported mode */ + if (of_data && of_data->scc_offset && host->mmc->caps & MMC_CAP_UHS_SDR104) { + const struct sh_mobile_sdhi_scc *taps = of_data->taps; + bool hit = false; +@@ -685,6 +681,11 @@ static int sh_mobile_sdhi_probe(struct p + dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n"); + + priv->scc_ctl = host->ctl + of_data->scc_offset; ++ host->init_tuning = sh_mobile_sdhi_init_tuning; ++ host->prepare_tuning = sh_mobile_sdhi_prepare_tuning; ++ host->select_tuning = sh_mobile_sdhi_select_tuning; ++ host->check_scc_error = sh_mobile_sdhi_check_scc_error; ++ host->hw_reset = sh_mobile_sdhi_hw_reset; + } + + i = 0; diff --git a/patches.renesas/0148-mmc-sh_mobile_sdhi-remove-superfluous-check-in-hw_re.patch b/patches.renesas/0148-mmc-sh_mobile_sdhi-remove-superfluous-check-in-hw_re.patch new file mode 100644 index 0000000000000..5946ccce5b272 --- /dev/null +++ b/patches.renesas/0148-mmc-sh_mobile_sdhi-remove-superfluous-check-in-hw_re.patch @@ -0,0 +1,29 @@ +From 1a7aec08d1bb61d7bc8dd950513736e47cd382e1 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Mon, 12 Dec 2016 20:51:23 +0100 +Subject: [PATCH 148/255] mmc: sh_mobile_sdhi: remove superfluous check in + hw_reset + +The capability for HW_RESET is only activated if SDR104 is present, so +no need to check for SDR104 in the function itself again. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 97c64b2cd57608f7064810780056d17944f49128) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 3 --- + 1 file changed, 3 deletions(-) + +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -468,9 +468,6 @@ static void sh_mobile_sdhi_hw_reset(stru + { + struct sh_mobile_sdhi *priv; + +- if (!(host->mmc->caps & MMC_CAP_UHS_SDR104)) +- return; +- + priv = host_to_priv(host); + + /* Reset SCC */ diff --git a/patches.renesas/0149-mmc-sh_mobile_sdhi-remove-superfluous-check-in-init_.patch b/patches.renesas/0149-mmc-sh_mobile_sdhi-remove-superfluous-check-in-init_.patch new file mode 100644 index 0000000000000..c2431692d9989 --- /dev/null +++ b/patches.renesas/0149-mmc-sh_mobile_sdhi-remove-superfluous-check-in-init_.patch @@ -0,0 +1,29 @@ +From 895beeb9f9a78d1df746d36c8b23027bfb5519ef Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Mon, 12 Dec 2016 20:51:24 +0100 +Subject: [PATCH 149/255] mmc: sh_mobile_sdhi: remove superfluous check in + init_tuning + +The function will only be available if SDR104 was detected in probe, +so no need to check in the function itself again. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 7f9096f1c89ea698c22fde91285de2ef3eabd614) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 3 --- + 1 file changed, 3 deletions(-) + +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -335,9 +335,6 @@ static unsigned int sh_mobile_sdhi_init_ + { + struct sh_mobile_sdhi *priv; + +- if (!(host->mmc->caps & MMC_CAP_UHS_SDR104)) +- return 0; +- + priv = host_to_priv(host); + + /* set sampling clock selection range */ diff --git a/patches.renesas/0150-mmc-sh_mobile_sdhi-remove-superfluous-check-in-SCC-e.patch b/patches.renesas/0150-mmc-sh_mobile_sdhi-remove-superfluous-check-in-SCC-e.patch new file mode 100644 index 0000000000000..32dd5a2a01110 --- /dev/null +++ b/patches.renesas/0150-mmc-sh_mobile_sdhi-remove-superfluous-check-in-SCC-e.patch @@ -0,0 +1,33 @@ +From bce42a1c5866608e60c00657a72a683c461be0f5 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Mon, 12 Dec 2016 20:51:25 +0100 +Subject: [PATCH 150/255] mmc: sh_mobile_sdhi: remove superfluous check in SCC + error check + +The function will only be available if SDR104 was detected in probe, +so no need to check in the function itself again. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 03c5b0d90300fc725fc1fb644872b522483a2d7e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -441,12 +441,7 @@ static int sh_mobile_sdhi_select_tuning( + + static bool sh_mobile_sdhi_check_scc_error(struct tmio_mmc_host *host) + { +- struct sh_mobile_sdhi *priv; +- +- if (!(host->mmc->caps & MMC_CAP_UHS_SDR104)) +- return 0; +- +- priv = host_to_priv(host); ++ struct sh_mobile_sdhi *priv = host_to_priv(host); + + /* Check SCC error */ + if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & diff --git a/patches.renesas/0151-mmc-sh_mobile_sdhi-enable-HS200.patch b/patches.renesas/0151-mmc-sh_mobile_sdhi-enable-HS200.patch new file mode 100644 index 0000000000000..208fefaa0d4f9 --- /dev/null +++ b/patches.renesas/0151-mmc-sh_mobile_sdhi-enable-HS200.patch @@ -0,0 +1,28 @@ +From 73a988ba30fc3a18e557d4a29cc862ee870f603c Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Mon, 12 Dec 2016 20:51:26 +0100 +Subject: [PATCH 151/255] mmc: sh_mobile_sdhi: enable HS200 + +Setup tuning when the board is HS200 enabled. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit b1c95170f97ef19ff63a6da1eb2c70899186aecc) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -651,7 +651,9 @@ static int sh_mobile_sdhi_probe(struct p + goto efree; + + /* Enable tuning iff we have an SCC and a supported mode */ +- if (of_data && of_data->scc_offset && host->mmc->caps & MMC_CAP_UHS_SDR104) { ++ if (of_data && of_data->scc_offset && ++ (host->mmc->caps & MMC_CAP_UHS_SDR104 || ++ host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) { + const struct sh_mobile_sdhi_scc *taps = of_data->taps; + bool hit = false; + diff --git a/patches.renesas/0152-mmc-host-tmio-drop-superfluous-exit-path.patch b/patches.renesas/0152-mmc-host-tmio-drop-superfluous-exit-path.patch new file mode 100644 index 0000000000000..4a151637f5a07 --- /dev/null +++ b/patches.renesas/0152-mmc-host-tmio-drop-superfluous-exit-path.patch @@ -0,0 +1,71 @@ +From 51060f2d509fd12f3e817b017f0505f2cf2af689 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Fri, 6 Jan 2017 09:38:33 +0100 +Subject: [PATCH 152/255] mmc: host: tmio: drop superfluous exit path + +The probe exit path on error does nothing since commit 94b110aff8679b +("mmc: tmio: add tmio_mmc_host_alloc/free()"), so we can bail out +immediately. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit ad7014b3949b6c2b6ce46a546d6d204b5643e621) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 20 ++++++-------------- + 1 file changed, 6 insertions(+), 14 deletions(-) + +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -1143,7 +1143,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_ + + ret = mmc_of_parse(mmc); + if (ret < 0) +- goto host_free; ++ return ret; + + _host->pdata = pdata; + platform_set_drvdata(pdev, mmc); +@@ -1153,14 +1153,12 @@ int tmio_mmc_host_probe(struct tmio_mmc_ + + ret = tmio_mmc_init_ocr(_host); + if (ret < 0) +- goto host_free; ++ return ret; + + _host->ctl = devm_ioremap(&pdev->dev, + res_ctl->start, resource_size(res_ctl)); +- if (!_host->ctl) { +- ret = -ENOMEM; +- goto host_free; +- } ++ if (!_host->ctl) ++ return -ENOMEM; + + tmio_mmc_ops.card_busy = _host->card_busy; + tmio_mmc_ops.start_signal_voltage_switch = _host->start_signal_voltage_switch; +@@ -1198,10 +1196,8 @@ int tmio_mmc_host_probe(struct tmio_mmc_ + * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from + * looping forever... + */ +- if (mmc->f_min == 0) { +- ret = -EINVAL; +- goto host_free; +- } ++ if (mmc->f_min == 0) ++ return -EINVAL; + + /* + * While using internal tmio hardware logic for card detection, we need +@@ -1266,10 +1262,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_ + } + + return 0; +- +-host_free: +- +- return ret; + } + EXPORT_SYMBOL(tmio_mmc_host_probe); + diff --git a/patches.renesas/0153-mmc-tmio-Remove-redundant-check-of-mmc-slot.cd_irq.patch b/patches.renesas/0153-mmc-tmio-Remove-redundant-check-of-mmc-slot.cd_irq.patch new file mode 100644 index 0000000000000..173777f6f65d8 --- /dev/null +++ b/patches.renesas/0153-mmc-tmio-Remove-redundant-check-of-mmc-slot.cd_irq.patch @@ -0,0 +1,34 @@ +From 050cf2aa2edbbc361eba5e8a403b333794091eab Mon Sep 17 00:00:00 2001 +From: Ulf Hansson <ulf.hansson@linaro.org> +Date: Tue, 10 Jan 2017 16:10:52 +0100 +Subject: [PATCH 153/255] mmc: tmio: Remove redundant check of mmc->slot.cd_irq + +To validate whether native hotplug needs to be used, the tmio driver checks +whether the mmc->slot.cd_irq has been successfully assigned. + +This check is redundant at its current place in tmio_mmc_host_probe(), as +the mmc core assigns mmc->slot.cd_irq a valid value first when +mmc_gpiod_request_cd_irq() is called. Therefore, let's just remove the +check for now, as that also removes a layering violation of the tmio driver +accessing core specific data via ->slot.cd_irq. + +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +(cherry picked from commit efd7be7bfc8eb8942ba3dc319f323cfd0eda99e2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -1175,8 +1175,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_ + + _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD || + mmc->caps & MMC_CAP_NEEDS_POLL || +- !mmc_card_is_removable(mmc) || +- mmc->slot.cd_irq >= 0); ++ !mmc_card_is_removable(mmc)); + + /* + * On Gen2+, eMMC with NONREMOVABLE currently fails because native diff --git a/patches.renesas/0154-mmc-host-tmio-disable-clocks-when-unbinding.patch b/patches.renesas/0154-mmc-host-tmio-disable-clocks-when-unbinding.patch new file mode 100644 index 0000000000000..37497ceff0c7e --- /dev/null +++ b/patches.renesas/0154-mmc-host-tmio-disable-clocks-when-unbinding.patch @@ -0,0 +1,52 @@ +From 8f7ba7d5d1b58d1015257dfd8e926c46198dd0aa Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Tue, 17 Jan 2017 21:26:01 +0100 +Subject: [PATCH 154/255] mmc: host: tmio: disable clocks when unbinding + +Create a helper function to disable clocks and use it in remove(), too. +Now, clk_summary in debugfs reports the clocks as disabled and +unprepared after unbinding. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit dfcba5ffca989749d1fc49d5b82a2d007b1295b7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -900,6 +900,12 @@ static int tmio_mmc_clk_enable(struct tm + return host->clk_enable(host); + } + ++static void tmio_mmc_clk_disable(struct tmio_mmc_host *host) ++{ ++ if (host->clk_disable) ++ host->clk_disable(host); ++} ++ + static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd) + { + struct mmc_host *mmc = host->mmc; +@@ -1284,6 +1290,8 @@ void tmio_mmc_host_remove(struct tmio_mm + + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); ++ ++ tmio_mmc_clk_disable(host); + } + EXPORT_SYMBOL(tmio_mmc_host_remove); + +@@ -1298,8 +1306,7 @@ int tmio_mmc_host_runtime_suspend(struct + if (host->clk_cache) + tmio_mmc_clk_stop(host); + +- if (host->clk_disable) +- host->clk_disable(host); ++ tmio_mmc_clk_disable(host); + + return 0; + } diff --git a/patches.renesas/0155-mmc-host-tmio-refactor-calls-to-sdio-irq.patch b/patches.renesas/0155-mmc-host-tmio-refactor-calls-to-sdio-irq.patch new file mode 100644 index 0000000000000..3a6c1e7b00b50 --- /dev/null +++ b/patches.renesas/0155-mmc-host-tmio-refactor-calls-to-sdio-irq.patch @@ -0,0 +1,42 @@ +From 89fe53edf904968766b24e9a3ed9f8a952588602 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Thu, 19 Jan 2017 21:07:16 +0100 +Subject: [PATCH 155/255] mmc: host: tmio: refactor calls to sdio irq + +tmio_mmc_sdio_irq() is not used as a seperate irq handler anymore, so we +can make it similar to the other irq helper functions, namely: + +* only give the host as argument function which is what it really needs +* prefix function name with __ + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Acked-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit e4f38eb18aedd098b3019e82df07f583a5cbcc58) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -709,9 +709,8 @@ static bool __tmio_mmc_sdcard_irq(struct + return false; + } + +-static void tmio_mmc_sdio_irq(int irq, void *devid) ++static void __tmio_mmc_sdio_irq(struct tmio_mmc_host *host) + { +- struct tmio_mmc_host *host = devid; + struct mmc_host *mmc = host->mmc; + struct tmio_mmc_data *pdata = host->pdata; + unsigned int ireg, status; +@@ -752,7 +751,7 @@ irqreturn_t tmio_mmc_irq(int irq, void * + if (__tmio_mmc_sdcard_irq(host, ireg, status)) + return IRQ_HANDLED; + +- tmio_mmc_sdio_irq(irq, devid); ++ __tmio_mmc_sdio_irq(host); + + return IRQ_HANDLED; + } diff --git a/patches.renesas/0156-mmc-host-tmio-SDIO_STATUS_QUIRK-is-rather-SDIO_STATU.patch b/patches.renesas/0156-mmc-host-tmio-SDIO_STATUS_QUIRK-is-rather-SDIO_STATU.patch new file mode 100644 index 0000000000000..f212882e93c5e --- /dev/null +++ b/patches.renesas/0156-mmc-host-tmio-SDIO_STATUS_QUIRK-is-rather-SDIO_STATU.patch @@ -0,0 +1,60 @@ +From 4606a421dbb16e10a8018dff56b77b1542de61d7 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Thu, 19 Jan 2017 21:07:17 +0100 +Subject: [PATCH 156/255] mmc: host: tmio: SDIO_STATUS_QUIRK is rather + SDIO_STATUS_SETBITS + +QUIRK sounds like there is something wrong, but actually there are just +some bits which need to be 1. Rename it to be more clear. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 20dd03734cac41a0545dd24f5e81d8ff0c80874b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 6 ++---- + drivers/mmc/host/tmio_mmc_pio.c | 2 +- + include/linux/mfd/tmio.h | 6 ++---- + 3 files changed, 5 insertions(+), 9 deletions(-) + +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -641,10 +641,8 @@ static int sh_mobile_sdhi_probe(struct p + */ + mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; + +- /* +- * All SDHI need SDIO_INFO1 reserved bit +- */ +- mmc_data->flags |= TMIO_MMC_SDIO_STATUS_QUIRK; ++ /* All SDHI have SDIO status bits which must be 1 */ ++ mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; + + ret = tmio_mmc_host_probe(host, mmc_data); + if (ret < 0) +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -723,7 +723,7 @@ static void __tmio_mmc_sdio_irq(struct t + ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdio_irq_mask; + + sdio_status = status & ~TMIO_SDIO_MASK_ALL; +- if (pdata->flags & TMIO_MMC_SDIO_STATUS_QUIRK) ++ if (pdata->flags & TMIO_MMC_SDIO_STATUS_SETBITS) + sdio_status |= 6; + + sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status); +--- a/include/linux/mfd/tmio.h ++++ b/include/linux/mfd/tmio.h +@@ -94,10 +94,8 @@ + */ + #define TMIO_MMC_HAVE_CMD12_CTRL (1 << 7) + +-/* +- * Some controllers needs to set 1 on SDIO status reserved bits +- */ +-#define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8) ++/* Controller has some SDIO status bits which must be 1 */ ++#define TMIO_MMC_SDIO_STATUS_SETBITS (1 << 8) + + /* + * Some controllers have a 32-bit wide data port register diff --git a/patches.renesas/0157-mmc-tmio-discard-obsolete-SDIO-irqs-before-enabling-.patch b/patches.renesas/0157-mmc-tmio-discard-obsolete-SDIO-irqs-before-enabling-.patch new file mode 100644 index 0000000000000..f4f21d6dd3db7 --- /dev/null +++ b/patches.renesas/0157-mmc-tmio-discard-obsolete-SDIO-irqs-before-enabling-.patch @@ -0,0 +1,64 @@ +From 1e336b0d7c70bd78d887aa0eb8ef68333d0ac171 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Thu, 19 Jan 2017 21:07:18 +0100 +Subject: [PATCH 157/255] mmc: tmio: discard obsolete SDIO irqs before enabling + irqs + +Before enabling SDIO irqs, clear the status bit, so we discard old and +stale interrupts. Needed to get two wireless cards working. Use the +newly introduced macro in all places. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit ee28981535f4261ed5d127ddf4d1a3f8778f520d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc.h | 2 ++ + drivers/mmc/host/tmio_mmc_pio.c | 13 +++++++++++-- + 2 files changed, 13 insertions(+), 2 deletions(-) + +--- a/drivers/mmc/host/tmio_mmc.h ++++ b/drivers/mmc/host/tmio_mmc.h +@@ -90,6 +90,8 @@ + #define TMIO_SDIO_STAT_EXWT 0x8000 + #define TMIO_SDIO_MASK_ALL 0xc007 + ++#define TMIO_SDIO_SETBITS_MASK 0x0006 ++ + /* Define some IRQ masks */ + /* This is the mask used at reset by the chip */ + #define TMIO_MASK_ALL 0x837f031d +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -134,12 +134,21 @@ static void tmio_mmc_enable_sdio_irq(str + struct tmio_mmc_host *host = mmc_priv(mmc); + + if (enable && !host->sdio_irq_enabled) { ++ u16 sdio_status; ++ + /* Keep device active while SDIO irq is enabled */ + pm_runtime_get_sync(mmc_dev(mmc)); +- host->sdio_irq_enabled = true; + ++ host->sdio_irq_enabled = true; + host->sdio_irq_mask = TMIO_SDIO_MASK_ALL & + ~TMIO_SDIO_STAT_IOIRQ; ++ ++ /* Clear obsolete interrupts before enabling */ ++ sdio_status = sd_ctrl_read16(host, CTL_SDIO_STATUS) & ~TMIO_SDIO_MASK_ALL; ++ if (host->pdata->flags & TMIO_MMC_SDIO_STATUS_SETBITS) ++ sdio_status |= TMIO_SDIO_SETBITS_MASK; ++ sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status); ++ + sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask); + } else if (!enable && host->sdio_irq_enabled) { + host->sdio_irq_mask = TMIO_SDIO_MASK_ALL; +@@ -724,7 +733,7 @@ static void __tmio_mmc_sdio_irq(struct t + + sdio_status = status & ~TMIO_SDIO_MASK_ALL; + if (pdata->flags & TMIO_MMC_SDIO_STATUS_SETBITS) +- sdio_status |= 6; ++ sdio_status |= TMIO_SDIO_SETBITS_MASK; + + sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status); + diff --git a/patches.renesas/0158-mmc-sh_mobile_sdhi-add-support-for-2-clocks.patch b/patches.renesas/0158-mmc-sh_mobile_sdhi-add-support-for-2-clocks.patch new file mode 100644 index 0000000000000..e3c9bcb653a47 --- /dev/null +++ b/patches.renesas/0158-mmc-sh_mobile_sdhi-add-support-for-2-clocks.patch @@ -0,0 +1,71 @@ +From bcabe95c59f6813f5d0db93a0e27ec0c9121feb3 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Wed, 25 Jan 2017 15:28:08 -0500 +Subject: [PATCH 158/255] mmc: sh_mobile_sdhi: add support for 2 clocks + +Some controllers have 2 clock sources instead of 1. The 2nd clock +is for the internal card detect logic and must be enabled/disabled +along with the main core clock for proper operation. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +(cherry picked from commit 34a1654706c6cc20e7a9077063b307afe28ec66c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/sh_mobile_sdhi.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -143,6 +143,7 @@ MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_o + + struct sh_mobile_sdhi { + struct clk *clk; ++ struct clk *clk_cd; + struct tmio_mmc_data mmc_data; + struct tmio_mmc_dma dma_priv; + struct pinctrl *pinctrl; +@@ -190,6 +191,12 @@ static int sh_mobile_sdhi_clk_enable(str + if (ret < 0) + return ret; + ++ ret = clk_prepare_enable(priv->clk_cd); ++ if (ret < 0) { ++ clk_disable_unprepare(priv->clk); ++ return ret; ++ } ++ + /* + * The clock driver may not know what maximum frequency + * actually works, so it should be set with the max-frequency +@@ -255,6 +262,7 @@ static void sh_mobile_sdhi_clk_disable(s + struct sh_mobile_sdhi *priv = host_to_priv(host); + + clk_disable_unprepare(priv->clk); ++ clk_disable_unprepare(priv->clk_cd); + } + + static int sh_mobile_sdhi_card_busy(struct mmc_host *mmc) +@@ -572,6 +580,21 @@ static int sh_mobile_sdhi_probe(struct p + goto eprobe; + } + ++ /* ++ * Some controllers provide a 2nd clock just to run the internal card ++ * detection logic. Unfortunately, the existing driver architecture does ++ * not support a separation of clocks for runtime PM usage. When ++ * native hotplug is used, the tmio driver assumes that the core ++ * must continue to run for card detect to stay active, so we cannot ++ * disable it. ++ * Additionally, it is prohibited to supply a clock to the core but not ++ * to the card detect circuit. That leaves us with if separate clocks ++ * are presented, we must treat them both as virtually 1 clock. ++ */ ++ priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); ++ if (IS_ERR(priv->clk_cd)) ++ priv->clk_cd = NULL; ++ + priv->pinctrl = devm_pinctrl_get(&pdev->dev); + if (!IS_ERR(priv->pinctrl)) { + priv->pins_default = pinctrl_lookup_state(priv->pinctrl, diff --git a/patches.renesas/0159-mmc-sh_mobile_sdhi-explain-clock-bindings.patch b/patches.renesas/0159-mmc-sh_mobile_sdhi-explain-clock-bindings.patch new file mode 100644 index 0000000000000..332dab5b66675 --- /dev/null +++ b/patches.renesas/0159-mmc-sh_mobile_sdhi-explain-clock-bindings.patch @@ -0,0 +1,43 @@ +From 84e03feab423e6bde5568c8dcd35b7217ceec4a6 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Wed, 25 Jan 2017 15:28:09 -0500 +Subject: [PATCH 159/255] mmc: sh_mobile_sdhi: explain clock bindings + +In the case of a single clock source, you don't need names. However, +if the controller has 2 clock sources, you need to name them correctly +so the driver can find the 2nd one. The 2nd clock is for the internal +card detect logic. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Acked-by: Rob Herring <robh@kernel.org> +(cherry picked from commit 62a4cdead56e5715c61aadd41ab66f49bd3170f1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt ++++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +@@ -25,6 +25,19 @@ Required properties: + "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC + "renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC + ++- clocks: Most controllers only have 1 clock source per channel. However, on ++ some variations of this controller, the internal card detection ++ logic that exists in this controller is sectioned off to be run by a ++ separate second clock source to allow the main core clock to be turned ++ off to save power. ++ If 2 clocks are specified by the hardware, you must name them as ++ "core" and "cd". If the controller only has 1 clock, naming is not ++ required. ++ Below is the number clocks for each supported SoC: ++ 1: SH73A0, R8A73A4, R8A7740, R8A7778, R8A7779, R8A7790 ++ R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796 ++ 2: R7S72100 ++ + Optional properties: + - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable + - pinctrl-names: should be "default", "state_uhs" diff --git a/patches.renesas/0160-spi-sh-msiof-Remove-useless-memory-allocation-failur.patch b/patches.renesas/0160-spi-sh-msiof-Remove-useless-memory-allocation-failur.patch new file mode 100644 index 0000000000000..f1e86f2518d5b --- /dev/null +++ b/patches.renesas/0160-spi-sh-msiof-Remove-useless-memory-allocation-failur.patch @@ -0,0 +1,30 @@ +From 88b77c65e78474dcd9658f2436bccdbcfa6ef4fc Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 4 Jan 2017 11:15:08 +0100 +Subject: [PATCH 160/255] spi: sh-msiof: Remove useless memory allocation + failure message + +Printing an error on memory allocation failure is unnecessary. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit e7ad4a73364c21f40963a35631b285b60fa3198c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/spi/spi-sh-msiof.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +--- a/drivers/spi/spi-sh-msiof.c ++++ b/drivers/spi/spi-sh-msiof.c +@@ -1164,10 +1164,8 @@ static int sh_msiof_spi_probe(struct pla + int ret; + + master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); +- if (master == NULL) { +- dev_err(&pdev->dev, "failed to allocate spi master\n"); ++ if (master == NULL) + return -ENOMEM; +- } + + p = spi_master_get_devdata(master); + diff --git a/patches.renesas/0161-pinctrl-sh-pfc-r8a7796-Add-drive-strength-support.patch b/patches.renesas/0161-pinctrl-sh-pfc-r8a7796-Add-drive-strength-support.patch new file mode 100644 index 0000000000000..4121bf954a73d --- /dev/null +++ b/patches.renesas/0161-pinctrl-sh-pfc-r8a7796-Add-drive-strength-support.patch @@ -0,0 +1,429 @@ +From 422f62aa2ce7de207b46a43f0b5bbec82833a637 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Thu, 17 Nov 2016 16:09:19 +0100 +Subject: [PATCH 161/255] pinctrl: sh-pfc: r8a7796: Add drive strength support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Define the drive strength registers for the R8A7796. Add pins which are +not part of a GPIO bank nor can be muxed between different functions but +which still allow for their drive-strength to be configured. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 9e35d6fa825c02bdd00c24cb32299355702130bd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 359 +++++++++++++++++++++++++++++++++-- + 1 file changed, 347 insertions(+), 12 deletions(-) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +@@ -19,19 +19,21 @@ + #include "core.h" + #include "sh_pfc.h" + ++#define CFG_FLAGS SH_PFC_PIN_CFG_DRIVE_STRENGTH ++ + #define CPU_ALL_PORT(fn, sfx) \ +- PORT_GP_16(0, fn, sfx), \ +- PORT_GP_29(1, fn, sfx), \ +- PORT_GP_15(2, fn, sfx), \ +- PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ +- PORT_GP_1(3, 12, fn, sfx), \ +- PORT_GP_1(3, 13, fn, sfx), \ +- PORT_GP_1(3, 14, fn, sfx), \ +- PORT_GP_1(3, 15, fn, sfx), \ +- PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ +- PORT_GP_26(5, fn, sfx), \ +- PORT_GP_32(6, fn, sfx), \ +- PORT_GP_4(7, fn, sfx) ++ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ ++ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ ++ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) + /* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK +@@ -541,6 +543,23 @@ MOD_SEL0_2 MOD_SEL1_2 \ + MOD_SEL1_1 \ + MOD_SEL1_0 MOD_SEL2_0 + ++/* ++ * These pins are not able to be muxed but have other properties ++ * that can be set, such as drive-strength or pull-up/pull-down enable. ++ */ ++#define PINMUX_STATIC \ ++ FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ ++ FM(QSPI0_IO2) FM(QSPI0_IO3) \ ++ FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ ++ FM(QSPI1_IO2) FM(QSPI1_IO3) \ ++ FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ ++ FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ ++ FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ ++ FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ ++ FM(PRESETOUT) \ ++ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \ ++ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) ++ + enum { + PINMUX_RESERVED = 0, + +@@ -565,6 +584,7 @@ enum { + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS ++ PINMUX_STATIC + PINMUX_MARK_END, + #undef F_ + #undef FM +@@ -1484,10 +1504,76 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), + PINMUX_IPSR_NOGP(0, I2C_SEL_3_1), + PINMUX_IPSR_NOGP(0, I2C_SEL_5_1), ++ ++/* ++ * Static pins can not be muxed between different functions but ++ * still needs a mark entry in the pinmux list. Add each static ++ * pin to the list without an associated function. The sh-pfc ++ * core will do the right thing and skip trying to mux then pin ++ * while still applying configuration to it ++ */ ++#define FM(x) PINMUX_DATA(x##_MARK, 0), ++ PINMUX_STATIC ++#undef FM + }; + ++/* ++ * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs. ++ * Physical layout rows: A - AW, cols: 1 - 39. ++ */ ++#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) ++#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) ++#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) ++ + static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), ++ ++ /* ++ * Pins not associated with a GPIO port. ++ * ++ * The pin positions are different between different r8a7796 ++ * packages, all that is needed for the pfc driver is a unique ++ * number for each pin. To this end use the pin layout from ++ * R-Car M3SiP to calculate a unique number for each pin. ++ */ ++ SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + }; + + /* - EtherAVB --------------------------------------------------------------- */ +@@ -3187,6 +3273,254 @@ static const struct pinmux_cfg_reg pinmu + { }, + }; + ++static const struct pinmux_drive_reg pinmux_drive_regs[] = { ++ { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { ++ { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ ++ { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ ++ { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ ++ { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ ++ { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ ++ { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ ++ { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ ++ { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { ++ { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ ++ { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ ++ { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ ++ { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ ++ { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ ++ { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ ++ { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ ++ { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { ++ { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ ++ { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ ++ { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ ++ { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ ++ { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ ++ { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ ++ { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ ++ { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { ++ { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ ++ { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ ++ { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ ++ { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ ++ { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ ++ { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ ++ { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ ++ { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { ++ { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ ++ { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ ++ { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ ++ { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ ++ { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ ++ { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ ++ { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ ++ { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { ++ { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ ++ { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ ++ { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ ++ { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ ++ { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ ++ { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ ++ { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ ++ { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { ++ { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ ++ { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ ++ { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ ++ { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ ++ { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ ++ { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ ++ { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ ++ { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { ++ { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ ++ { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ ++ { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ ++ { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ ++ { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ ++ { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ ++ { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ ++ { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { ++ { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ ++ { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ ++ { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ ++ { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ ++ { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ ++ { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ ++ { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ ++ { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { ++ { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ ++ { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ ++ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ ++ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ ++ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ ++ { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ ++ { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ ++ { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { ++ { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ ++ { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ ++ { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ ++ { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ ++ { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ ++ { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ ++ { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ ++ { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { ++ { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ ++ { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ ++ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ ++ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ ++ { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ ++ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ ++ { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ ++ { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { ++ { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */ ++ { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */ ++ { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { ++ { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ ++ { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ ++ { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ ++ { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ ++ { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ ++ { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ ++ { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ ++ { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { ++ { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ ++ { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ ++ { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ ++ { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ ++ { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ ++ { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ ++ { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ ++ { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { ++ { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ ++ { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ ++ { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ ++ { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ ++ { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ ++ { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ ++ { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ ++ { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { ++ { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ ++ { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ ++ { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ ++ { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ ++ { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ ++ { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ ++ { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ ++ { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { ++ { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ ++ { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ ++ { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ ++ { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ ++ { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ ++ { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ ++ { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ ++ { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { ++ { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */ ++ { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ ++ { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ ++ { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ ++ { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */ ++ { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ ++ { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ ++ { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { ++ { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ ++ { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ ++ { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ ++ { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ ++ { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ ++ { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ ++ { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ ++ { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { ++ { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ ++ { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ ++ { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ ++ { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ ++ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ ++ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ ++ { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ ++ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { ++ { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ ++ { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ ++ { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ ++ { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ ++ { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */ ++ { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */ ++ { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ ++ { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { ++ { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ ++ { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ ++ { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ ++ { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ ++ { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ ++ { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ ++ { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ ++ { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { ++ { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ ++ { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ ++ { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ ++ { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ ++ { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ ++ { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ ++ { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ ++ { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { ++ { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ ++ { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ ++ { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ ++ { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ ++ { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ ++ { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ ++ { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ ++ } }, ++ { }, ++}; ++ + static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) + { + int bit = -EINVAL; +@@ -3221,6 +3555,7 @@ const struct sh_pfc_soc_info r8a7796_pin + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, ++ .drive_regs = pinmux_drive_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/patches.renesas/0162-pinctrl-sh-pfc-r8a7796-Add-bias-pinconf-support.patch b/patches.renesas/0162-pinctrl-sh-pfc-r8a7796-Add-bias-pinconf-support.patch new file mode 100644 index 0000000000000..09a78f5cd53f6 --- /dev/null +++ b/patches.renesas/0162-pinctrl-sh-pfc-r8a7796-Add-bias-pinconf-support.patch @@ -0,0 +1,407 @@ +From f025272c413eecc7dc20adf0c73a08ca620924f2 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Thu, 17 Nov 2016 16:09:20 +0100 +Subject: [PATCH 162/255] pinctrl: sh-pfc: r8a7796: Add bias pinconf support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Implements pull-up and pull-down. On this SoC there is no simple mapping +of GP pins to bias register bits, so we need a table. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 2d40bd24274d257796291804a82a0b07564a11f1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 354 +++++++++++++++++++++++++++++++---- + 1 file changed, 315 insertions(+), 39 deletions(-) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +@@ -19,7 +19,9 @@ + #include "core.h" + #include "sh_pfc.h" + +-#define CFG_FLAGS SH_PFC_PIN_CFG_DRIVE_STRENGTH ++#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ ++ SH_PFC_PIN_CFG_PULL_UP | \ ++ SH_PFC_PIN_CFG_PULL_DOWN) + + #define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ +@@ -558,7 +560,7 @@ MOD_SEL0_2 MOD_SEL1_2 \ + FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ + FM(PRESETOUT) \ + FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \ +- FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) ++ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) + + enum { + PINMUX_RESERVED = 0, +@@ -1536,44 +1538,48 @@ static const struct sh_pfc_pin pinmux_pi + * number for each pin. To this end use the pin layout from + * R-Car M3SiP to calculate a unique number for each pin. + */ +- SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + }; + + /* - EtherAVB --------------------------------------------------------------- */ +@@ -3536,8 +3542,278 @@ static int r8a7796_pin_to_pocctrl(struct + return bit; + } + ++#define PUEN 0xe6060400 ++#define PUD 0xe6060440 ++ ++#define PU0 0x00 ++#define PU1 0x04 ++#define PU2 0x08 ++#define PU3 0x0c ++#define PU4 0x10 ++#define PU5 0x14 ++#define PU6 0x18 ++ ++static const struct sh_pfc_bias_info bias_info[] = { ++ { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ ++ { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ ++ { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ ++ { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ ++ { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ ++ { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ ++ { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ ++ { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ ++ { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ ++ { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ ++ { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ ++ { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ ++ { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ ++ { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ ++ { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ ++ { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ ++ { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ ++ { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ ++ { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ ++ { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ ++ { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ ++ { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ ++ { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ ++ { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ ++ { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ ++ { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ ++ { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ ++ { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ ++ { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ ++ { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ ++ { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ ++ { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ ++ ++ { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ ++ { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ ++ { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ ++ { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ ++ { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ ++ { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ ++ { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ ++ { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ ++ { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ ++ { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ ++ { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ ++ { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ ++ { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ ++ { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ ++ { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ ++ { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ ++ { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ ++ { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ ++ { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ ++ { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ ++ { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ ++ { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ ++ { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ ++ { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ ++ { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ ++ { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ ++ { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ ++ { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ ++ { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ ++ { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ ++ { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ ++ { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ ++ ++ { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ ++ { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ ++ { RCAR_GP_PIN(7, 3), PU2, 29 }, /* GP7_03 */ ++ { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ ++ { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ ++ { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ ++ { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ ++ { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ ++ { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ ++ { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ ++ { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ ++ { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ ++ { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ ++ { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ ++ { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ ++ { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ ++ { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ ++ { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ ++ { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ ++ { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ ++ { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ ++ { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ ++ { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ ++ { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ ++ { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ ++ { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ ++ { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ ++ { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ ++ { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ ++ { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ ++ { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ ++ { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */ ++ ++ { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ ++ { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ ++ { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ ++ { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ ++ { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ ++ { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ ++ { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ ++ { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ ++ { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ ++ { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ ++ { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ ++ { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ ++ { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ ++ { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ ++ { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ ++ { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ ++ { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ ++ { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ ++ { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ ++ { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ ++ { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ ++ { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ ++ { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ ++ /* bit 8 n/a */ ++ { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ ++ { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ ++ { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ ++ { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ ++ { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ ++ { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST */ ++ /* bit 1 n/a on M3*/ ++ { PIN_A_NUMBER('R', 8), PU3, 0 }, /* DU_DOTCLKIN2 */ ++ ++ { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ ++ { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ ++ { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ ++ { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ ++ { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ ++ { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ ++ { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ ++ { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ ++ { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ ++ { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ ++ { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ ++ { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ ++ { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ ++ { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ ++ { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ ++ { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ ++ { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ ++ { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ ++ { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ ++ { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ ++ { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ ++ { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ ++ { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ ++ { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ ++ { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ ++ { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ ++ { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ ++ { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ ++ { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ ++ { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ ++ { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ ++ { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ ++ ++ { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ ++ { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ ++ { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ ++ { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ ++ { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ ++ { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ ++ { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ ++ { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ ++ { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ ++ { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ ++ { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ ++ { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ ++ { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ ++ { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ ++ { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ ++ { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ ++ { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ ++ { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ ++ { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ ++ { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ ++ { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ ++ { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ ++ { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ ++ { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ ++ { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ ++ { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ ++ { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ ++ { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ ++ { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ ++ { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ ++ { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ ++ { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ ++ ++ { RCAR_GP_PIN(6, 31), PU6, 6 }, /* GP6_31 */ ++ { RCAR_GP_PIN(6, 30), PU6, 5 }, /* GP6_30 */ ++ { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ ++ { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ ++ { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ ++ { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ ++ { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ ++}; ++ ++static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, ++ unsigned int pin) ++{ ++ const struct sh_pfc_bias_info *info; ++ u32 reg; ++ u32 bit; ++ ++ info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); ++ if (!info) ++ return PIN_CONFIG_BIAS_DISABLE; ++ ++ reg = info->reg; ++ bit = BIT(info->bit); ++ ++ if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit)) ++ return PIN_CONFIG_BIAS_DISABLE; ++ else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) ++ return PIN_CONFIG_BIAS_PULL_UP; ++ else ++ return PIN_CONFIG_BIAS_PULL_DOWN; ++} ++ ++static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, ++ unsigned int bias) ++{ ++ const struct sh_pfc_bias_info *info; ++ u32 enable, updown; ++ u32 reg; ++ u32 bit; ++ ++ info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); ++ if (!info) ++ return; ++ ++ reg = info->reg; ++ bit = BIT(info->bit); ++ ++ enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; ++ if (bias != PIN_CONFIG_BIAS_DISABLE) ++ enable |= bit; ++ ++ updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; ++ if (bias == PIN_CONFIG_BIAS_PULL_UP) ++ updown |= bit; ++ ++ sh_pfc_write_reg(pfc, PUD + reg, 32, updown); ++ sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); ++} ++ + static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { + .pin_to_pocctrl = r8a7796_pin_to_pocctrl, ++ .get_bias = r8a7796_pinmux_get_bias, ++ .set_bias = r8a7796_pinmux_set_bias, + }; + + const struct sh_pfc_soc_info r8a7796_pinmux_info = { diff --git a/patches.renesas/0163-pinctrl-sh-pfc-r8a7795-Support-none-GPIO-pins-bias-s.patch b/patches.renesas/0163-pinctrl-sh-pfc-r8a7795-Support-none-GPIO-pins-bias-s.patch new file mode 100644 index 0000000000000..cc7128113df0c --- /dev/null +++ b/patches.renesas/0163-pinctrl-sh-pfc-r8a7795-Support-none-GPIO-pins-bias-s.patch @@ -0,0 +1,500 @@ +From d4b0f1e11796ae9d17254f05b2660ce167dcd761 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Thu, 17 Nov 2016 16:26:31 +0100 +Subject: [PATCH 163/255] pinctrl: sh-pfc: r8a7795: Support none GPIO pins bias + setting +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There are pins on the r8a7795 which are not part of a GPIO bank nor +can be muxed between different functions. They do however allow for the +bias to be configured. Add those pins to the list of pins and +to the bias configuration array. + +The pins can now be referred to in DT by function names and their bias +setting set. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 4c2fb44d60b92c4e3e744f49767da23f4eaf1b98) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 450 +++++++++++++++++++---------------- + 1 file changed, 249 insertions(+), 201 deletions(-) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +@@ -538,7 +538,7 @@ MOD_SEL0_2_1 MOD_SEL1_2 \ + FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ + FM(CLKOUT) FM(PRESETOUT) \ + FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ +- FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) ++ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) + + enum { + PINMUX_RESERVED = 0, +@@ -1461,46 +1461,50 @@ static const struct sh_pfc_pin pinmux_pi + * number for each pin. To this end use the pin layout from + * R-Car H3SiP to calculate a unique number for each pin. + */ +- SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + }; + + /* - AUDIO CLOCK ------------------------------------------------------------ */ +@@ -5415,167 +5419,211 @@ static int r8a7795_pin_to_pocctrl(struct + #define PU6 0x18 + + static const struct sh_pfc_bias_info bias_info[] = { +- { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ +- { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ +- { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ +- +- { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ +- { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ +- { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ +- { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ +- { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ +- { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ +- { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ +- { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ +- { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ +- { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ +- { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ +- { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ +- { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ +- { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ +- { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ +- { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ +- { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ +- { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ +- { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ +- { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ +- { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ +- { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ +- { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ +- { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ +- { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ +- { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ +- { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ +- { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ +- { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ +- { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ +- { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ +- { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ +- +- { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ +- { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ +- { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ +- { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ +- { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ +- { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ +- { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ +- { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ +- { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ +- { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ +- { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ +- { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ +- { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ +- { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ +- { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ +- { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ +- { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ +- { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ +- { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ +- { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ +- { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ +- { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ +- { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ +- { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ +- { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ +- { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ +- { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ +- { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ +- +- { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ +- { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ +- { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ +- { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ +- { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ +- { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ +- { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ +- { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ +- { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ +- { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ +- { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ +- { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ +- { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ +- { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ +- { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ +- { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ +- { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ +- { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ +- { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ +- { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ +- { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ +- { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ +- +- { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ +- { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ +- { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ +- { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ +- { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ +- { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ +- { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ +- { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ +- { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ +- { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ +- { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ +- { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ +- { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ +- { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ +- { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ +- { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ +- { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ +- { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ +- { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ +- { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ +- { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ +- { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ +- { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ +- { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ +- { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ +- { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ +- { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ +- { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ +- { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ +- { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ +- { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ +- { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ +- +- { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ +- { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ +- { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ +- { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ +- { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ +- { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ +- { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ +- { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ +- { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ +- { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ +- { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ +- { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ +- { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ +- { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ +- { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ +- { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ +- { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ +- { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ +- { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ +- { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ +- { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ +- { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ +- { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ +- { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ +- { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ +- { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ +- { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ +- { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ +- { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ +- { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ +- { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ +- +- { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */ +- { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */ +- { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ +- { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ +- { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ +- { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ +- { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ ++ { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ ++ { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ ++ { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ ++ { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ ++ { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ ++ { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ ++ { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ ++ { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ ++ { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ ++ { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ ++ { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ ++ { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ ++ { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ ++ { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ ++ { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ ++ { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ ++ { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ ++ { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ ++ { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ ++ { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ ++ { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ ++ { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ ++ { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ ++ { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ ++ { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ ++ { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ ++ { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ ++ { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ ++ { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ ++ { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ ++ { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ ++ { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ ++ ++ { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ ++ { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ ++ { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ ++ { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ ++ { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ ++ { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ ++ { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ ++ { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ ++ { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ ++ { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ ++ { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ ++ { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ ++ { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ ++ { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ ++ { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ ++ { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ ++ { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ ++ { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ ++ { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ ++ { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ ++ { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ ++ { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ ++ { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ ++ { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ ++ { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ ++ { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ ++ { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ ++ { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ ++ { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ ++ { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ ++ { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ ++ { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ ++ ++ { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ ++ { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ ++ { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ ++ { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ ++ { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ ++ { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ ++ { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ ++ { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ ++ { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ ++ { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ ++ { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ ++ { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ ++ { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ ++ { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ ++ { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ ++ { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ ++ { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ ++ { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ ++ { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ ++ { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ ++ { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ ++ { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ ++ { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ ++ { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ ++ { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ ++ { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ ++ { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ ++ { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ ++ { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ ++ { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ ++ { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ ++ { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */ ++ ++ { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ ++ { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ ++ { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ ++ { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ ++ { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ ++ { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ ++ { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ ++ { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ ++ { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ ++ { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ ++ { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ ++ { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ ++ { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ ++ { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ ++ { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ ++ { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ ++ { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ ++ { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ ++ { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ ++ { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ ++ { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ ++ { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ ++ { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ ++ /* bit 8 n/a */ ++ { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ ++ { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ ++ { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ ++ { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ ++ { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ ++ { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */ ++ { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */ ++ { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */ ++ ++ { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ ++ { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ ++ { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ ++ { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ ++ { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ ++ { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ ++ { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ ++ { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ ++ { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ ++ { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ ++ { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ ++ { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ ++ { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ ++ { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ ++ { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ ++ { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ ++ { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ ++ { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ ++ { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ ++ { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ ++ { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ ++ { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ ++ { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ ++ { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ ++ { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ ++ { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ ++ { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ ++ { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ ++ { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ ++ { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ ++ { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ ++ { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ ++ ++ { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ ++ { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ ++ { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ ++ { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ ++ { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ ++ { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ ++ { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ ++ { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ ++ { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ ++ { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ ++ { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ ++ { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ ++ { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ ++ { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ ++ { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ ++ { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ ++ { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ ++ { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ ++ { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ ++ { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ ++ { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ ++ { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ ++ { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ ++ { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ ++ { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ ++ { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ ++ { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ ++ { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ ++ { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ ++ { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ ++ { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ ++ { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ ++ ++ { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */ ++ { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */ ++ { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ ++ { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ ++ { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ ++ { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ ++ { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ + }; + + static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, diff --git a/patches.renesas/0164-pinctrl-sh-pfc-r8a7796-Add-CAN-support.patch b/patches.renesas/0164-pinctrl-sh-pfc-r8a7796-Add-CAN-support.patch new file mode 100644 index 0000000000000..8a93d589a7e03 --- /dev/null +++ b/patches.renesas/0164-pinctrl-sh-pfc-r8a7796-Add-CAN-support.patch @@ -0,0 +1,99 @@ +From 8dce3caf9d6ff741fbff23389f0d6c50b4b85043 Mon Sep 17 00:00:00 2001 +From: Chris Paterson <chris.paterson2@renesas.com> +Date: Tue, 22 Nov 2016 13:49:02 +0000 +Subject: [PATCH 164/255] pinctrl: sh-pfc: r8a7796: Add CAN support + +This patch adds CAN[0-1] pinmux support to r8a7796 SoC. + +Based on a patch for r8a7795 by Ramesh Shanmugasundaram. + +Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit cf75341accab1a90895936cff380c38f6d0777f5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 52 +++++++++++++++++++++++++++++++++++ + 1 file changed, 52 insertions(+) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +@@ -1647,6 +1647,38 @@ static const unsigned int avb_avtp_captu + AVB_AVTP_CAPTURE_B_MARK, + }; + ++/* - CAN ------------------------------------------------------------------ */ ++static const unsigned int can0_data_a_pins[] = { ++ /* TX, RX */ ++ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), ++}; ++static const unsigned int can0_data_a_mux[] = { ++ CAN0_TX_A_MARK, CAN0_RX_A_MARK, ++}; ++static const unsigned int can0_data_b_pins[] = { ++ /* TX, RX */ ++ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), ++}; ++static const unsigned int can0_data_b_mux[] = { ++ CAN0_TX_B_MARK, CAN0_RX_B_MARK, ++}; ++static const unsigned int can1_data_pins[] = { ++ /* TX, RX */ ++ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), ++}; ++static const unsigned int can1_data_mux[] = { ++ CAN1_TX_MARK, CAN1_RX_MARK, ++}; ++ ++/* - CAN Clock -------------------------------------------------------------- */ ++static const unsigned int can_clk_pins[] = { ++ /* CLK */ ++ RCAR_GP_PIN(1, 25), ++}; ++static const unsigned int can_clk_mux[] = { ++ CAN_CLK_MARK, ++}; ++ + /* - DRIF0 --------------------------------------------------------------- */ + static const unsigned int drif0_ctrl_a_pins[] = { + /* CLK, SYNC */ +@@ -2425,6 +2457,10 @@ static const struct sh_pfc_pin_group pin + SH_PFC_PIN_GROUP(avb_avtp_capture_a), + SH_PFC_PIN_GROUP(avb_avtp_match_b), + SH_PFC_PIN_GROUP(avb_avtp_capture_b), ++ SH_PFC_PIN_GROUP(can0_data_a), ++ SH_PFC_PIN_GROUP(can0_data_b), ++ SH_PFC_PIN_GROUP(can1_data), ++ SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(drif0_ctrl_a), + SH_PFC_PIN_GROUP(drif0_data0_a), + SH_PFC_PIN_GROUP(drif0_data1_a), +@@ -2539,6 +2575,19 @@ static const char * const avb_groups[] = + "avb_avtp_capture_b", + }; + ++static const char * const can0_groups[] = { ++ "can0_data_a", ++ "can0_data_b", ++}; ++ ++static const char * const can1_groups[] = { ++ "can1_data", ++}; ++ ++static const char * const can_clk_groups[] = { ++ "can_clk", ++}; ++ + static const char * const drif0_groups[] = { + "drif0_ctrl_a", + "drif0_data0_a", +@@ -2698,6 +2747,9 @@ static const char * const sdhi3_groups[] + + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(avb), ++ SH_PFC_FUNCTION(can0), ++ SH_PFC_FUNCTION(can1), ++ SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(drif0), + SH_PFC_FUNCTION(drif1), + SH_PFC_FUNCTION(drif2), diff --git a/patches.renesas/0165-pinctrl-sh-pfc-r8a7796-Add-CAN-FD-support.patch b/patches.renesas/0165-pinctrl-sh-pfc-r8a7796-Add-CAN-FD-support.patch new file mode 100644 index 0000000000000..36c4cf488e04a --- /dev/null +++ b/patches.renesas/0165-pinctrl-sh-pfc-r8a7796-Add-CAN-FD-support.patch @@ -0,0 +1,84 @@ +From 39192eaff1017b2bb2d418f4ffe3769d3d211076 Mon Sep 17 00:00:00 2001 +From: Chris Paterson <chris.paterson2@renesas.com> +Date: Tue, 22 Nov 2016 13:49:03 +0000 +Subject: [PATCH 165/255] pinctrl: sh-pfc: r8a7796: Add CAN FD support + +This patch adds CAN FD[0-1] pinmux support to r8a7796 SoC. + +Based on a patch for r8a7795 by Ramesh Shanmugasundaram. + +Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 3dc93dcea67c967308db8ba00bac1334cf43a083) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 37 +++++++++++++++++++++++++++++++++++ + 1 file changed, 37 insertions(+) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +@@ -1679,6 +1679,29 @@ static const unsigned int can_clk_mux[] + CAN_CLK_MARK, + }; + ++/* - CAN FD --------------------------------------------------------------- */ ++static const unsigned int canfd0_data_a_pins[] = { ++ /* TX, RX */ ++ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), ++}; ++static const unsigned int canfd0_data_a_mux[] = { ++ CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, ++}; ++static const unsigned int canfd0_data_b_pins[] = { ++ /* TX, RX */ ++ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), ++}; ++static const unsigned int canfd0_data_b_mux[] = { ++ CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, ++}; ++static const unsigned int canfd1_data_pins[] = { ++ /* TX, RX */ ++ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), ++}; ++static const unsigned int canfd1_data_mux[] = { ++ CANFD1_TX_MARK, CANFD1_RX_MARK, ++}; ++ + /* - DRIF0 --------------------------------------------------------------- */ + static const unsigned int drif0_ctrl_a_pins[] = { + /* CLK, SYNC */ +@@ -2461,6 +2484,9 @@ static const struct sh_pfc_pin_group pin + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can_clk), ++ SH_PFC_PIN_GROUP(canfd0_data_a), ++ SH_PFC_PIN_GROUP(canfd0_data_b), ++ SH_PFC_PIN_GROUP(canfd1_data), + SH_PFC_PIN_GROUP(drif0_ctrl_a), + SH_PFC_PIN_GROUP(drif0_data0_a), + SH_PFC_PIN_GROUP(drif0_data1_a), +@@ -2588,6 +2614,15 @@ static const char * const can_clk_groups + "can_clk", + }; + ++static const char * const canfd0_groups[] = { ++ "canfd0_data_a", ++ "canfd0_data_b", ++}; ++ ++static const char * const canfd1_groups[] = { ++ "canfd1_data", ++}; ++ + static const char * const drif0_groups[] = { + "drif0_ctrl_a", + "drif0_data0_a", +@@ -2750,6 +2785,8 @@ static const struct sh_pfc_function pinm + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), ++ SH_PFC_FUNCTION(canfd0), ++ SH_PFC_FUNCTION(canfd1), + SH_PFC_FUNCTION(drif0), + SH_PFC_FUNCTION(drif1), + SH_PFC_FUNCTION(drif2), diff --git a/patches.renesas/0166-pinctrl-sh-pfc-r8a7796-Add-MSIOF-pins-groups-and-fun.patch b/patches.renesas/0166-pinctrl-sh-pfc-r8a7796-Add-MSIOF-pins-groups-and-fun.patch new file mode 100644 index 0000000000000..915836433e82b --- /dev/null +++ b/patches.renesas/0166-pinctrl-sh-pfc-r8a7796-Add-MSIOF-pins-groups-and-fun.patch @@ -0,0 +1,962 @@ +From 36027a1df7185e4b739a4324ba3126c425b1c2b0 Mon Sep 17 00:00:00 2001 +From: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Date: Wed, 16 Mar 2016 12:22:06 +0900 +Subject: [PATCH 166/255] pinctrl: sh-pfc: r8a7796: Add MSIOF pins, groups and + functions + +This patch adds MSIOF{0,1,2,3} pins, groups and functions to R8A7796 +SoC. + +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +[geert: Correct MSIOF3 SS1_E/SS2_E pins] +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> + +(cherry picked from commit 4753231cc94683903135b9ca6d71eaab79f81349) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 913 +++++++++++++++++++++++++++++++++++ + 1 file changed, 913 insertions(+) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +@@ -2049,6 +2049,705 @@ static const unsigned int i2c6_c_mux[] = + SDA6_C_MARK, SCL6_C_MARK, + }; + ++/* - MSIOF0 ----------------------------------------------------------------- */ ++static const unsigned int msiof0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 17), ++}; ++static const unsigned int msiof0_clk_mux[] = { ++ MSIOF0_SCK_MARK, ++}; ++static const unsigned int msiof0_sync_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(5, 18), ++}; ++static const unsigned int msiof0_sync_mux[] = { ++ MSIOF0_SYNC_MARK, ++}; ++static const unsigned int msiof0_ss1_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(5, 19), ++}; ++static const unsigned int msiof0_ss1_mux[] = { ++ MSIOF0_SS1_MARK, ++}; ++static const unsigned int msiof0_ss2_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(5, 21), ++}; ++static const unsigned int msiof0_ss2_mux[] = { ++ MSIOF0_SS2_MARK, ++}; ++static const unsigned int msiof0_txd_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(5, 20), ++}; ++static const unsigned int msiof0_txd_mux[] = { ++ MSIOF0_TXD_MARK, ++}; ++static const unsigned int msiof0_rxd_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(5, 22), ++}; ++static const unsigned int msiof0_rxd_mux[] = { ++ MSIOF0_RXD_MARK, ++}; ++/* - MSIOF1 ----------------------------------------------------------------- */ ++static const unsigned int msiof1_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 8), ++}; ++static const unsigned int msiof1_clk_a_mux[] = { ++ MSIOF1_SCK_A_MARK, ++}; ++static const unsigned int msiof1_sync_a_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(6, 9), ++}; ++static const unsigned int msiof1_sync_a_mux[] = { ++ MSIOF1_SYNC_A_MARK, ++}; ++static const unsigned int msiof1_ss1_a_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(6, 5), ++}; ++static const unsigned int msiof1_ss1_a_mux[] = { ++ MSIOF1_SS1_A_MARK, ++}; ++static const unsigned int msiof1_ss2_a_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(6, 6), ++}; ++static const unsigned int msiof1_ss2_a_mux[] = { ++ MSIOF1_SS2_A_MARK, ++}; ++static const unsigned int msiof1_txd_a_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(6, 7), ++}; ++static const unsigned int msiof1_txd_a_mux[] = { ++ MSIOF1_TXD_A_MARK, ++}; ++static const unsigned int msiof1_rxd_a_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(6, 10), ++}; ++static const unsigned int msiof1_rxd_a_mux[] = { ++ MSIOF1_RXD_A_MARK, ++}; ++static const unsigned int msiof1_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 9), ++}; ++static const unsigned int msiof1_clk_b_mux[] = { ++ MSIOF1_SCK_B_MARK, ++}; ++static const unsigned int msiof1_sync_b_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(5, 3), ++}; ++static const unsigned int msiof1_sync_b_mux[] = { ++ MSIOF1_SYNC_B_MARK, ++}; ++static const unsigned int msiof1_ss1_b_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(5, 4), ++}; ++static const unsigned int msiof1_ss1_b_mux[] = { ++ MSIOF1_SS1_B_MARK, ++}; ++static const unsigned int msiof1_ss2_b_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(5, 0), ++}; ++static const unsigned int msiof1_ss2_b_mux[] = { ++ MSIOF1_SS2_B_MARK, ++}; ++static const unsigned int msiof1_txd_b_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(5, 8), ++}; ++static const unsigned int msiof1_txd_b_mux[] = { ++ MSIOF1_TXD_B_MARK, ++}; ++static const unsigned int msiof1_rxd_b_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(5, 7), ++}; ++static const unsigned int msiof1_rxd_b_mux[] = { ++ MSIOF1_RXD_B_MARK, ++}; ++static const unsigned int msiof1_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 17), ++}; ++static const unsigned int msiof1_clk_c_mux[] = { ++ MSIOF1_SCK_C_MARK, ++}; ++static const unsigned int msiof1_sync_c_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(6, 18), ++}; ++static const unsigned int msiof1_sync_c_mux[] = { ++ MSIOF1_SYNC_C_MARK, ++}; ++static const unsigned int msiof1_ss1_c_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int msiof1_ss1_c_mux[] = { ++ MSIOF1_SS1_C_MARK, ++}; ++static const unsigned int msiof1_ss2_c_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(6, 27), ++}; ++static const unsigned int msiof1_ss2_c_mux[] = { ++ MSIOF1_SS2_C_MARK, ++}; ++static const unsigned int msiof1_txd_c_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(6, 20), ++}; ++static const unsigned int msiof1_txd_c_mux[] = { ++ MSIOF1_TXD_C_MARK, ++}; ++static const unsigned int msiof1_rxd_c_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(6, 19), ++}; ++static const unsigned int msiof1_rxd_c_mux[] = { ++ MSIOF1_RXD_C_MARK, ++}; ++static const unsigned int msiof1_clk_d_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 12), ++}; ++static const unsigned int msiof1_clk_d_mux[] = { ++ MSIOF1_SCK_D_MARK, ++}; ++static const unsigned int msiof1_sync_d_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(5, 15), ++}; ++static const unsigned int msiof1_sync_d_mux[] = { ++ MSIOF1_SYNC_D_MARK, ++}; ++static const unsigned int msiof1_ss1_d_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(5, 16), ++}; ++static const unsigned int msiof1_ss1_d_mux[] = { ++ MSIOF1_SS1_D_MARK, ++}; ++static const unsigned int msiof1_ss2_d_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(5, 21), ++}; ++static const unsigned int msiof1_ss2_d_mux[] = { ++ MSIOF1_SS2_D_MARK, ++}; ++static const unsigned int msiof1_txd_d_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(5, 14), ++}; ++static const unsigned int msiof1_txd_d_mux[] = { ++ MSIOF1_TXD_D_MARK, ++}; ++static const unsigned int msiof1_rxd_d_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(5, 13), ++}; ++static const unsigned int msiof1_rxd_d_mux[] = { ++ MSIOF1_RXD_D_MARK, ++}; ++static const unsigned int msiof1_clk_e_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 0), ++}; ++static const unsigned int msiof1_clk_e_mux[] = { ++ MSIOF1_SCK_E_MARK, ++}; ++static const unsigned int msiof1_sync_e_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(3, 1), ++}; ++static const unsigned int msiof1_sync_e_mux[] = { ++ MSIOF1_SYNC_E_MARK, ++}; ++static const unsigned int msiof1_ss1_e_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(3, 4), ++}; ++static const unsigned int msiof1_ss1_e_mux[] = { ++ MSIOF1_SS1_E_MARK, ++}; ++static const unsigned int msiof1_ss2_e_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(3, 5), ++}; ++static const unsigned int msiof1_ss2_e_mux[] = { ++ MSIOF1_SS2_E_MARK, ++}; ++static const unsigned int msiof1_txd_e_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(3, 3), ++}; ++static const unsigned int msiof1_txd_e_mux[] = { ++ MSIOF1_TXD_E_MARK, ++}; ++static const unsigned int msiof1_rxd_e_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(3, 2), ++}; ++static const unsigned int msiof1_rxd_e_mux[] = { ++ MSIOF1_RXD_E_MARK, ++}; ++static const unsigned int msiof1_clk_f_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 23), ++}; ++static const unsigned int msiof1_clk_f_mux[] = { ++ MSIOF1_SCK_F_MARK, ++}; ++static const unsigned int msiof1_sync_f_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(5, 24), ++}; ++static const unsigned int msiof1_sync_f_mux[] = { ++ MSIOF1_SYNC_F_MARK, ++}; ++static const unsigned int msiof1_ss1_f_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(6, 1), ++}; ++static const unsigned int msiof1_ss1_f_mux[] = { ++ MSIOF1_SS1_F_MARK, ++}; ++static const unsigned int msiof1_ss2_f_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(6, 2), ++}; ++static const unsigned int msiof1_ss2_f_mux[] = { ++ MSIOF1_SS2_F_MARK, ++}; ++static const unsigned int msiof1_txd_f_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(6, 0), ++}; ++static const unsigned int msiof1_txd_f_mux[] = { ++ MSIOF1_TXD_F_MARK, ++}; ++static const unsigned int msiof1_rxd_f_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(5, 25), ++}; ++static const unsigned int msiof1_rxd_f_mux[] = { ++ MSIOF1_RXD_F_MARK, ++}; ++static const unsigned int msiof1_clk_g_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 6), ++}; ++static const unsigned int msiof1_clk_g_mux[] = { ++ MSIOF1_SCK_G_MARK, ++}; ++static const unsigned int msiof1_sync_g_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(3, 7), ++}; ++static const unsigned int msiof1_sync_g_mux[] = { ++ MSIOF1_SYNC_G_MARK, ++}; ++static const unsigned int msiof1_ss1_g_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(3, 10), ++}; ++static const unsigned int msiof1_ss1_g_mux[] = { ++ MSIOF1_SS1_G_MARK, ++}; ++static const unsigned int msiof1_ss2_g_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(3, 11), ++}; ++static const unsigned int msiof1_ss2_g_mux[] = { ++ MSIOF1_SS2_G_MARK, ++}; ++static const unsigned int msiof1_txd_g_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(3, 9), ++}; ++static const unsigned int msiof1_txd_g_mux[] = { ++ MSIOF1_TXD_G_MARK, ++}; ++static const unsigned int msiof1_rxd_g_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(3, 8), ++}; ++static const unsigned int msiof1_rxd_g_mux[] = { ++ MSIOF1_RXD_G_MARK, ++}; ++/* - MSIOF2 ----------------------------------------------------------------- */ ++static const unsigned int msiof2_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 9), ++}; ++static const unsigned int msiof2_clk_a_mux[] = { ++ MSIOF2_SCK_A_MARK, ++}; ++static const unsigned int msiof2_sync_a_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(1, 8), ++}; ++static const unsigned int msiof2_sync_a_mux[] = { ++ MSIOF2_SYNC_A_MARK, ++}; ++static const unsigned int msiof2_ss1_a_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(1, 6), ++}; ++static const unsigned int msiof2_ss1_a_mux[] = { ++ MSIOF2_SS1_A_MARK, ++}; ++static const unsigned int msiof2_ss2_a_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(1, 7), ++}; ++static const unsigned int msiof2_ss2_a_mux[] = { ++ MSIOF2_SS2_A_MARK, ++}; ++static const unsigned int msiof2_txd_a_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int msiof2_txd_a_mux[] = { ++ MSIOF2_TXD_A_MARK, ++}; ++static const unsigned int msiof2_rxd_a_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(1, 10), ++}; ++static const unsigned int msiof2_rxd_a_mux[] = { ++ MSIOF2_RXD_A_MARK, ++}; ++static const unsigned int msiof2_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 4), ++}; ++static const unsigned int msiof2_clk_b_mux[] = { ++ MSIOF2_SCK_B_MARK, ++}; ++static const unsigned int msiof2_sync_b_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(0, 5), ++}; ++static const unsigned int msiof2_sync_b_mux[] = { ++ MSIOF2_SYNC_B_MARK, ++}; ++static const unsigned int msiof2_ss1_b_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(0, 0), ++}; ++static const unsigned int msiof2_ss1_b_mux[] = { ++ MSIOF2_SS1_B_MARK, ++}; ++static const unsigned int msiof2_ss2_b_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(0, 1), ++}; ++static const unsigned int msiof2_ss2_b_mux[] = { ++ MSIOF2_SS2_B_MARK, ++}; ++static const unsigned int msiof2_txd_b_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(0, 7), ++}; ++static const unsigned int msiof2_txd_b_mux[] = { ++ MSIOF2_TXD_B_MARK, ++}; ++static const unsigned int msiof2_rxd_b_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(0, 6), ++}; ++static const unsigned int msiof2_rxd_b_mux[] = { ++ MSIOF2_RXD_B_MARK, ++}; ++static const unsigned int msiof2_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(2, 12), ++}; ++static const unsigned int msiof2_clk_c_mux[] = { ++ MSIOF2_SCK_C_MARK, ++}; ++static const unsigned int msiof2_sync_c_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(2, 11), ++}; ++static const unsigned int msiof2_sync_c_mux[] = { ++ MSIOF2_SYNC_C_MARK, ++}; ++static const unsigned int msiof2_ss1_c_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(2, 10), ++}; ++static const unsigned int msiof2_ss1_c_mux[] = { ++ MSIOF2_SS1_C_MARK, ++}; ++static const unsigned int msiof2_ss2_c_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(2, 9), ++}; ++static const unsigned int msiof2_ss2_c_mux[] = { ++ MSIOF2_SS2_C_MARK, ++}; ++static const unsigned int msiof2_txd_c_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(2, 14), ++}; ++static const unsigned int msiof2_txd_c_mux[] = { ++ MSIOF2_TXD_C_MARK, ++}; ++static const unsigned int msiof2_rxd_c_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(2, 13), ++}; ++static const unsigned int msiof2_rxd_c_mux[] = { ++ MSIOF2_RXD_C_MARK, ++}; ++static const unsigned int msiof2_clk_d_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 8), ++}; ++static const unsigned int msiof2_clk_d_mux[] = { ++ MSIOF2_SCK_D_MARK, ++}; ++static const unsigned int msiof2_sync_d_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(0, 9), ++}; ++static const unsigned int msiof2_sync_d_mux[] = { ++ MSIOF2_SYNC_D_MARK, ++}; ++static const unsigned int msiof2_ss1_d_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(0, 12), ++}; ++static const unsigned int msiof2_ss1_d_mux[] = { ++ MSIOF2_SS1_D_MARK, ++}; ++static const unsigned int msiof2_ss2_d_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(0, 13), ++}; ++static const unsigned int msiof2_ss2_d_mux[] = { ++ MSIOF2_SS2_D_MARK, ++}; ++static const unsigned int msiof2_txd_d_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(0, 11), ++}; ++static const unsigned int msiof2_txd_d_mux[] = { ++ MSIOF2_TXD_D_MARK, ++}; ++static const unsigned int msiof2_rxd_d_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(0, 10), ++}; ++static const unsigned int msiof2_rxd_d_mux[] = { ++ MSIOF2_RXD_D_MARK, ++}; ++/* - MSIOF3 ----------------------------------------------------------------- */ ++static const unsigned int msiof3_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 0), ++}; ++static const unsigned int msiof3_clk_a_mux[] = { ++ MSIOF3_SCK_A_MARK, ++}; ++static const unsigned int msiof3_sync_a_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(0, 1), ++}; ++static const unsigned int msiof3_sync_a_mux[] = { ++ MSIOF3_SYNC_A_MARK, ++}; ++static const unsigned int msiof3_ss1_a_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(0, 14), ++}; ++static const unsigned int msiof3_ss1_a_mux[] = { ++ MSIOF3_SS1_A_MARK, ++}; ++static const unsigned int msiof3_ss2_a_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(0, 15), ++}; ++static const unsigned int msiof3_ss2_a_mux[] = { ++ MSIOF3_SS2_A_MARK, ++}; ++static const unsigned int msiof3_txd_a_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(0, 3), ++}; ++static const unsigned int msiof3_txd_a_mux[] = { ++ MSIOF3_TXD_A_MARK, ++}; ++static const unsigned int msiof3_rxd_a_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(0, 2), ++}; ++static const unsigned int msiof3_rxd_a_mux[] = { ++ MSIOF3_RXD_A_MARK, ++}; ++static const unsigned int msiof3_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 2), ++}; ++static const unsigned int msiof3_clk_b_mux[] = { ++ MSIOF3_SCK_B_MARK, ++}; ++static const unsigned int msiof3_sync_b_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(1, 0), ++}; ++static const unsigned int msiof3_sync_b_mux[] = { ++ MSIOF3_SYNC_B_MARK, ++}; ++static const unsigned int msiof3_ss1_b_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(1, 4), ++}; ++static const unsigned int msiof3_ss1_b_mux[] = { ++ MSIOF3_SS1_B_MARK, ++}; ++static const unsigned int msiof3_ss2_b_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(1, 5), ++}; ++static const unsigned int msiof3_ss2_b_mux[] = { ++ MSIOF3_SS2_B_MARK, ++}; ++static const unsigned int msiof3_txd_b_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(1, 1), ++}; ++static const unsigned int msiof3_txd_b_mux[] = { ++ MSIOF3_TXD_B_MARK, ++}; ++static const unsigned int msiof3_rxd_b_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(1, 3), ++}; ++static const unsigned int msiof3_rxd_b_mux[] = { ++ MSIOF3_RXD_B_MARK, ++}; ++static const unsigned int msiof3_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 12), ++}; ++static const unsigned int msiof3_clk_c_mux[] = { ++ MSIOF3_SCK_C_MARK, ++}; ++static const unsigned int msiof3_sync_c_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(1, 13), ++}; ++static const unsigned int msiof3_sync_c_mux[] = { ++ MSIOF3_SYNC_C_MARK, ++}; ++static const unsigned int msiof3_txd_c_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(1, 15), ++}; ++static const unsigned int msiof3_txd_c_mux[] = { ++ MSIOF3_TXD_C_MARK, ++}; ++static const unsigned int msiof3_rxd_c_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(1, 14), ++}; ++static const unsigned int msiof3_rxd_c_mux[] = { ++ MSIOF3_RXD_C_MARK, ++}; ++static const unsigned int msiof3_clk_d_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 22), ++}; ++static const unsigned int msiof3_clk_d_mux[] = { ++ MSIOF3_SCK_D_MARK, ++}; ++static const unsigned int msiof3_sync_d_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(1, 23), ++}; ++static const unsigned int msiof3_sync_d_mux[] = { ++ MSIOF3_SYNC_D_MARK, ++}; ++static const unsigned int msiof3_ss1_d_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(1, 26), ++}; ++static const unsigned int msiof3_ss1_d_mux[] = { ++ MSIOF3_SS1_D_MARK, ++}; ++static const unsigned int msiof3_txd_d_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(1, 25), ++}; ++static const unsigned int msiof3_txd_d_mux[] = { ++ MSIOF3_TXD_D_MARK, ++}; ++static const unsigned int msiof3_rxd_d_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(1, 24), ++}; ++static const unsigned int msiof3_rxd_d_mux[] = { ++ MSIOF3_RXD_D_MARK, ++}; ++ ++static const unsigned int msiof3_clk_e_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(2, 3), ++}; ++static const unsigned int msiof3_clk_e_mux[] = { ++ MSIOF3_SCK_E_MARK, ++}; ++static const unsigned int msiof3_sync_e_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(2, 2), ++}; ++static const unsigned int msiof3_sync_e_mux[] = { ++ MSIOF3_SYNC_E_MARK, ++}; ++static const unsigned int msiof3_ss1_e_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(2, 1), ++}; ++static const unsigned int msiof3_ss1_e_mux[] = { ++ MSIOF3_SS1_E_MARK, ++}; ++static const unsigned int msiof3_ss2_e_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(2, 0), ++}; ++static const unsigned int msiof3_ss2_e_mux[] = { ++ MSIOF3_SS1_E_MARK, ++}; ++static const unsigned int msiof3_txd_e_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(2, 5), ++}; ++static const unsigned int msiof3_txd_e_mux[] = { ++ MSIOF3_TXD_E_MARK, ++}; ++static const unsigned int msiof3_rxd_e_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(2, 4), ++}; ++static const unsigned int msiof3_rxd_e_mux[] = { ++ MSIOF3_RXD_E_MARK, ++}; ++ + /* - SCIF0 ------------------------------------------------------------------ */ + static const unsigned int scif0_data_pins[] = { + /* RX, TX */ +@@ -2532,6 +3231,105 @@ static const struct sh_pfc_pin_group pin + SH_PFC_PIN_GROUP(i2c6_a), + SH_PFC_PIN_GROUP(i2c6_b), + SH_PFC_PIN_GROUP(i2c6_c), ++ SH_PFC_PIN_GROUP(msiof0_clk), ++ SH_PFC_PIN_GROUP(msiof0_sync), ++ SH_PFC_PIN_GROUP(msiof0_ss1), ++ SH_PFC_PIN_GROUP(msiof0_ss2), ++ SH_PFC_PIN_GROUP(msiof0_txd), ++ SH_PFC_PIN_GROUP(msiof0_rxd), ++ SH_PFC_PIN_GROUP(msiof1_clk_a), ++ SH_PFC_PIN_GROUP(msiof1_sync_a), ++ SH_PFC_PIN_GROUP(msiof1_ss1_a), ++ SH_PFC_PIN_GROUP(msiof1_ss2_a), ++ SH_PFC_PIN_GROUP(msiof1_txd_a), ++ SH_PFC_PIN_GROUP(msiof1_rxd_a), ++ SH_PFC_PIN_GROUP(msiof1_clk_b), ++ SH_PFC_PIN_GROUP(msiof1_sync_b), ++ SH_PFC_PIN_GROUP(msiof1_ss1_b), ++ SH_PFC_PIN_GROUP(msiof1_ss2_b), ++ SH_PFC_PIN_GROUP(msiof1_txd_b), ++ SH_PFC_PIN_GROUP(msiof1_rxd_b), ++ SH_PFC_PIN_GROUP(msiof1_clk_c), ++ SH_PFC_PIN_GROUP(msiof1_sync_c), ++ SH_PFC_PIN_GROUP(msiof1_ss1_c), ++ SH_PFC_PIN_GROUP(msiof1_ss2_c), ++ SH_PFC_PIN_GROUP(msiof1_txd_c), ++ SH_PFC_PIN_GROUP(msiof1_rxd_c), ++ SH_PFC_PIN_GROUP(msiof1_clk_d), ++ SH_PFC_PIN_GROUP(msiof1_sync_d), ++ SH_PFC_PIN_GROUP(msiof1_ss1_d), ++ SH_PFC_PIN_GROUP(msiof1_ss2_d), ++ SH_PFC_PIN_GROUP(msiof1_txd_d), ++ SH_PFC_PIN_GROUP(msiof1_rxd_d), ++ SH_PFC_PIN_GROUP(msiof1_clk_e), ++ SH_PFC_PIN_GROUP(msiof1_sync_e), ++ SH_PFC_PIN_GROUP(msiof1_ss1_e), ++ SH_PFC_PIN_GROUP(msiof1_ss2_e), ++ SH_PFC_PIN_GROUP(msiof1_txd_e), ++ SH_PFC_PIN_GROUP(msiof1_rxd_e), ++ SH_PFC_PIN_GROUP(msiof1_clk_f), ++ SH_PFC_PIN_GROUP(msiof1_sync_f), ++ SH_PFC_PIN_GROUP(msiof1_ss1_f), ++ SH_PFC_PIN_GROUP(msiof1_ss2_f), ++ SH_PFC_PIN_GROUP(msiof1_txd_f), ++ SH_PFC_PIN_GROUP(msiof1_rxd_f), ++ SH_PFC_PIN_GROUP(msiof1_clk_g), ++ SH_PFC_PIN_GROUP(msiof1_sync_g), ++ SH_PFC_PIN_GROUP(msiof1_ss1_g), ++ SH_PFC_PIN_GROUP(msiof1_ss2_g), ++ SH_PFC_PIN_GROUP(msiof1_txd_g), ++ SH_PFC_PIN_GROUP(msiof1_rxd_g), ++ SH_PFC_PIN_GROUP(msiof2_clk_a), ++ SH_PFC_PIN_GROUP(msiof2_sync_a), ++ SH_PFC_PIN_GROUP(msiof2_ss1_a), ++ SH_PFC_PIN_GROUP(msiof2_ss2_a), ++ SH_PFC_PIN_GROUP(msiof2_txd_a), ++ SH_PFC_PIN_GROUP(msiof2_rxd_a), ++ SH_PFC_PIN_GROUP(msiof2_clk_b), ++ SH_PFC_PIN_GROUP(msiof2_sync_b), ++ SH_PFC_PIN_GROUP(msiof2_ss1_b), ++ SH_PFC_PIN_GROUP(msiof2_ss2_b), ++ SH_PFC_PIN_GROUP(msiof2_txd_b), ++ SH_PFC_PIN_GROUP(msiof2_rxd_b), ++ SH_PFC_PIN_GROUP(msiof2_clk_c), ++ SH_PFC_PIN_GROUP(msiof2_sync_c), ++ SH_PFC_PIN_GROUP(msiof2_ss1_c), ++ SH_PFC_PIN_GROUP(msiof2_ss2_c), ++ SH_PFC_PIN_GROUP(msiof2_txd_c), ++ SH_PFC_PIN_GROUP(msiof2_rxd_c), ++ SH_PFC_PIN_GROUP(msiof2_clk_d), ++ SH_PFC_PIN_GROUP(msiof2_sync_d), ++ SH_PFC_PIN_GROUP(msiof2_ss1_d), ++ SH_PFC_PIN_GROUP(msiof2_ss2_d), ++ SH_PFC_PIN_GROUP(msiof2_txd_d), ++ SH_PFC_PIN_GROUP(msiof2_rxd_d), ++ SH_PFC_PIN_GROUP(msiof3_clk_a), ++ SH_PFC_PIN_GROUP(msiof3_sync_a), ++ SH_PFC_PIN_GROUP(msiof3_ss1_a), ++ SH_PFC_PIN_GROUP(msiof3_ss2_a), ++ SH_PFC_PIN_GROUP(msiof3_txd_a), ++ SH_PFC_PIN_GROUP(msiof3_rxd_a), ++ SH_PFC_PIN_GROUP(msiof3_clk_b), ++ SH_PFC_PIN_GROUP(msiof3_sync_b), ++ SH_PFC_PIN_GROUP(msiof3_ss1_b), ++ SH_PFC_PIN_GROUP(msiof3_ss2_b), ++ SH_PFC_PIN_GROUP(msiof3_txd_b), ++ SH_PFC_PIN_GROUP(msiof3_rxd_b), ++ SH_PFC_PIN_GROUP(msiof3_clk_c), ++ SH_PFC_PIN_GROUP(msiof3_sync_c), ++ SH_PFC_PIN_GROUP(msiof3_txd_c), ++ SH_PFC_PIN_GROUP(msiof3_rxd_c), ++ SH_PFC_PIN_GROUP(msiof3_clk_d), ++ SH_PFC_PIN_GROUP(msiof3_sync_d), ++ SH_PFC_PIN_GROUP(msiof3_ss1_d), ++ SH_PFC_PIN_GROUP(msiof3_txd_d), ++ SH_PFC_PIN_GROUP(msiof3_rxd_d), ++ SH_PFC_PIN_GROUP(msiof3_clk_e), ++ SH_PFC_PIN_GROUP(msiof3_sync_e), ++ SH_PFC_PIN_GROUP(msiof3_ss1_e), ++ SH_PFC_PIN_GROUP(msiof3_ss2_e), ++ SH_PFC_PIN_GROUP(msiof3_txd_e), ++ SH_PFC_PIN_GROUP(msiof3_rxd_e), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), +@@ -2692,6 +3490,117 @@ static const char * const i2c6_groups[] + "i2c6_c", + }; + ++static const char * const msiof0_groups[] = { ++ "msiof0_clk", ++ "msiof0_sync", ++ "msiof0_ss1", ++ "msiof0_ss2", ++ "msiof0_txd", ++ "msiof0_rxd", ++}; ++ ++static const char * const msiof1_groups[] = { ++ "msiof1_clk_a", ++ "msiof1_sync_a", ++ "msiof1_ss1_a", ++ "msiof1_ss2_a", ++ "msiof1_txd_a", ++ "msiof1_rxd_a", ++ "msiof1_clk_b", ++ "msiof1_sync_b", ++ "msiof1_ss1_b", ++ "msiof1_ss2_b", ++ "msiof1_txd_b", ++ "msiof1_rxd_b", ++ "msiof1_clk_c", ++ "msiof1_sync_c", ++ "msiof1_ss1_c", ++ "msiof1_ss2_c", ++ "msiof1_txd_c", ++ "msiof1_rxd_c", ++ "msiof1_clk_d", ++ "msiof1_sync_d", ++ "msiof1_ss1_d", ++ "msiof1_ss2_d", ++ "msiof1_txd_d", ++ "msiof1_rxd_d", ++ "msiof1_clk_e", ++ "msiof1_sync_e", ++ "msiof1_ss1_e", ++ "msiof1_ss2_e", ++ "msiof1_txd_e", ++ "msiof1_rxd_e", ++ "msiof1_clk_f", ++ "msiof1_sync_f", ++ "msiof1_ss1_f", ++ "msiof1_ss2_f", ++ "msiof1_txd_f", ++ "msiof1_rxd_f", ++ "msiof1_clk_g", ++ "msiof1_sync_g", ++ "msiof1_ss1_g", ++ "msiof1_ss2_g", ++ "msiof1_txd_g", ++ "msiof1_rxd_g", ++}; ++ ++static const char * const msiof2_groups[] = { ++ "msiof2_clk_a", ++ "msiof2_sync_a", ++ "msiof2_ss1_a", ++ "msiof2_ss2_a", ++ "msiof2_txd_a", ++ "msiof2_rxd_a", ++ "msiof2_clk_b", ++ "msiof2_sync_b", ++ "msiof2_ss1_b", ++ "msiof2_ss2_b", ++ "msiof2_txd_b", ++ "msiof2_rxd_b", ++ "msiof2_clk_c", ++ "msiof2_sync_c", ++ "msiof2_ss1_c", ++ "msiof2_ss2_c", ++ "msiof2_txd_c", ++ "msiof2_rxd_c", ++ "msiof2_clk_d", ++ "msiof2_sync_d", ++ "msiof2_ss1_d", ++ "msiof2_ss2_d", ++ "msiof2_txd_d", ++ "msiof2_rxd_d", ++}; ++ ++static const char * const msiof3_groups[] = { ++ "msiof3_clk_a", ++ "msiof3_sync_a", ++ "msiof3_ss1_a", ++ "msiof3_ss2_a", ++ "msiof3_txd_a", ++ "msiof3_rxd_a", ++ "msiof3_clk_b", ++ "msiof3_sync_b", ++ "msiof3_ss1_b", ++ "msiof3_ss2_b", ++ "msiof3_txd_b", ++ "msiof3_rxd_b", ++ "msiof3_clk_c", ++ "msiof3_sync_c", ++ "msiof3_txd_c", ++ "msiof3_rxd_c", ++ "msiof3_clk_d", ++ "msiof3_sync_d", ++ "msiof3_ss1_d", ++ "msiof3_txd_d", ++ "msiof3_rxd_d", ++ "msiof3_clk_e", ++ "msiof3_sync_e", ++ "msiof3_ss1_e", ++ "msiof3_ss2_e", ++ "msiof3_txd_e", ++ "msiof3_rxd_e", ++}; ++ + static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", +@@ -2795,6 +3704,10 @@ static const struct sh_pfc_function pinm + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c6), ++ SH_PFC_FUNCTION(msiof0), ++ SH_PFC_FUNCTION(msiof1), ++ SH_PFC_FUNCTION(msiof2), ++ SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), diff --git a/patches.renesas/0167-pinctrl-sh-pfc-r8a7793-Implement-voltage-switching-f.patch b/patches.renesas/0167-pinctrl-sh-pfc-r8a7793-Implement-voltage-switching-f.patch new file mode 100644 index 0000000000000..ceb5cdcee122d --- /dev/null +++ b/patches.renesas/0167-pinctrl-sh-pfc-r8a7793-Implement-voltage-switching-f.patch @@ -0,0 +1,27 @@ +From ef077d11eb9d7d4f84a38be0faebdd7a251890a8 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 1 Dec 2016 14:21:07 +0100 +Subject: [PATCH 167/255] pinctrl: sh-pfc: r8a7793: Implement voltage switching + for SDHI + +Voltage switching is the same as on the r8a7791. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit aa6931f135d293cf6b0d527360845ff38455bc72) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -6459,6 +6459,7 @@ const struct sh_pfc_soc_info r8a7791_pin + #ifdef CONFIG_PINCTRL_PFC_R8A7793 + const struct sh_pfc_soc_info r8a7793_pinmux_info = { + .name = "r8a77930_pfc", ++ .ops = &r8a7791_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/patches.renesas/0168-pinctrl-sh-pfc-r8a7796-Add-HSCIF-pins-groups-and-fun.patch b/patches.renesas/0168-pinctrl-sh-pfc-r8a7796-Add-HSCIF-pins-groups-and-fun.patch new file mode 100644 index 0000000000000..d8ee0c2711aa8 --- /dev/null +++ b/patches.renesas/0168-pinctrl-sh-pfc-r8a7796-Add-HSCIF-pins-groups-and-fun.patch @@ -0,0 +1,329 @@ +From 4976404a26a63ebd1092b44a26924e1d4e73e5f8 Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Wed, 7 Dec 2016 17:44:46 +0100 +Subject: [PATCH 168/255] pinctrl: sh-pfc: r8a7796: Add HSCIF pins, groups, and + functions + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +[geert: Fix hscif2_clk_[bc]_mux[] and hscif4_ctrl_mux[]] +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> + +(cherry picked from commit 0e4e4999aac16641f47699e8929693b83a7a4d64) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 283 +++++++++++++++++++++++++++++++++++ + 1 file changed, 283 insertions(+) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +@@ -1998,6 +1998,213 @@ static const unsigned int du_disp_mux[] + DU_DISP_MARK, + }; + ++/* - HSCIF0 ----------------------------------------------------------------- */ ++static const unsigned int hscif0_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), ++}; ++static const unsigned int hscif0_data_mux[] = { ++ HRX0_MARK, HTX0_MARK, ++}; ++static const unsigned int hscif0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 12), ++}; ++static const unsigned int hscif0_clk_mux[] = { ++ HSCK0_MARK, ++}; ++static const unsigned int hscif0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), ++}; ++static const unsigned int hscif0_ctrl_mux[] = { ++ HRTS0_N_MARK, HCTS0_N_MARK, ++}; ++/* - HSCIF1 ----------------------------------------------------------------- */ ++static const unsigned int hscif1_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), ++}; ++static const unsigned int hscif1_data_a_mux[] = { ++ HRX1_A_MARK, HTX1_A_MARK, ++}; ++static const unsigned int hscif1_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int hscif1_clk_a_mux[] = { ++ HSCK1_A_MARK, ++}; ++static const unsigned int hscif1_ctrl_a_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), ++}; ++static const unsigned int hscif1_ctrl_a_mux[] = { ++ HRTS1_N_A_MARK, HCTS1_N_A_MARK, ++}; ++ ++static const unsigned int hscif1_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), ++}; ++static const unsigned int hscif1_data_b_mux[] = { ++ HRX1_B_MARK, HTX1_B_MARK, ++}; ++static const unsigned int hscif1_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 0), ++}; ++static const unsigned int hscif1_clk_b_mux[] = { ++ HSCK1_B_MARK, ++}; ++static const unsigned int hscif1_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), ++}; ++static const unsigned int hscif1_ctrl_b_mux[] = { ++ HRTS1_N_B_MARK, HCTS1_N_B_MARK, ++}; ++/* - HSCIF2 ----------------------------------------------------------------- */ ++static const unsigned int hscif2_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), ++}; ++static const unsigned int hscif2_data_a_mux[] = { ++ HRX2_A_MARK, HTX2_A_MARK, ++}; ++static const unsigned int hscif2_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 10), ++}; ++static const unsigned int hscif2_clk_a_mux[] = { ++ HSCK2_A_MARK, ++}; ++static const unsigned int hscif2_ctrl_a_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), ++}; ++static const unsigned int hscif2_ctrl_a_mux[] = { ++ HRTS2_N_A_MARK, HCTS2_N_A_MARK, ++}; ++ ++static const unsigned int hscif2_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), ++}; ++static const unsigned int hscif2_data_b_mux[] = { ++ HRX2_B_MARK, HTX2_B_MARK, ++}; ++static const unsigned int hscif2_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int hscif2_clk_b_mux[] = { ++ HSCK2_B_MARK, ++}; ++static const unsigned int hscif2_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), ++}; ++static const unsigned int hscif2_ctrl_b_mux[] = { ++ HRTS2_N_B_MARK, HCTS2_N_B_MARK, ++}; ++ ++static const unsigned int hscif2_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), ++}; ++static const unsigned int hscif2_data_c_mux[] = { ++ HRX2_C_MARK, HTX2_C_MARK, ++}; ++static const unsigned int hscif2_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 24), ++}; ++static const unsigned int hscif2_clk_c_mux[] = { ++ HSCK2_C_MARK, ++}; ++static const unsigned int hscif2_ctrl_c_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), ++}; ++static const unsigned int hscif2_ctrl_c_mux[] = { ++ HRTS2_N_C_MARK, HCTS2_N_C_MARK, ++}; ++/* - HSCIF3 ----------------------------------------------------------------- */ ++static const unsigned int hscif3_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), ++}; ++static const unsigned int hscif3_data_a_mux[] = { ++ HRX3_A_MARK, HTX3_A_MARK, ++}; ++static const unsigned int hscif3_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 22), ++}; ++static const unsigned int hscif3_clk_mux[] = { ++ HSCK3_MARK, ++}; ++static const unsigned int hscif3_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), ++}; ++static const unsigned int hscif3_ctrl_mux[] = { ++ HRTS3_N_MARK, HCTS3_N_MARK, ++}; ++ ++static const unsigned int hscif3_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), ++}; ++static const unsigned int hscif3_data_b_mux[] = { ++ HRX3_B_MARK, HTX3_B_MARK, ++}; ++static const unsigned int hscif3_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), ++}; ++static const unsigned int hscif3_data_c_mux[] = { ++ HRX3_C_MARK, HTX3_C_MARK, ++}; ++static const unsigned int hscif3_data_d_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), ++}; ++static const unsigned int hscif3_data_d_mux[] = { ++ HRX3_D_MARK, HTX3_D_MARK, ++}; ++/* - HSCIF4 ----------------------------------------------------------------- */ ++static const unsigned int hscif4_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), ++}; ++static const unsigned int hscif4_data_a_mux[] = { ++ HRX4_A_MARK, HTX4_A_MARK, ++}; ++static const unsigned int hscif4_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int hscif4_clk_mux[] = { ++ HSCK4_MARK, ++}; ++static const unsigned int hscif4_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), ++}; ++static const unsigned int hscif4_ctrl_mux[] = { ++ HRTS4_N_MARK, HCTS4_N_MARK, ++}; ++ ++static const unsigned int hscif4_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int hscif4_data_b_mux[] = { ++ HRX4_B_MARK, HTX4_B_MARK, ++}; ++ + /* - I2C -------------------------------------------------------------------- */ + static const unsigned int i2c1_a_pins[] = { + /* SDA, SCL */ +@@ -3224,6 +3431,34 @@ static const struct sh_pfc_pin_group pin + SH_PFC_PIN_GROUP(du_oddf), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du_disp), ++ SH_PFC_PIN_GROUP(hscif0_data), ++ SH_PFC_PIN_GROUP(hscif0_clk), ++ SH_PFC_PIN_GROUP(hscif0_ctrl), ++ SH_PFC_PIN_GROUP(hscif1_data_a), ++ SH_PFC_PIN_GROUP(hscif1_clk_a), ++ SH_PFC_PIN_GROUP(hscif1_ctrl_a), ++ SH_PFC_PIN_GROUP(hscif1_data_b), ++ SH_PFC_PIN_GROUP(hscif1_clk_b), ++ SH_PFC_PIN_GROUP(hscif1_ctrl_b), ++ SH_PFC_PIN_GROUP(hscif2_data_a), ++ SH_PFC_PIN_GROUP(hscif2_clk_a), ++ SH_PFC_PIN_GROUP(hscif2_ctrl_a), ++ SH_PFC_PIN_GROUP(hscif2_data_b), ++ SH_PFC_PIN_GROUP(hscif2_clk_b), ++ SH_PFC_PIN_GROUP(hscif2_ctrl_b), ++ SH_PFC_PIN_GROUP(hscif2_data_c), ++ SH_PFC_PIN_GROUP(hscif2_clk_c), ++ SH_PFC_PIN_GROUP(hscif2_ctrl_c), ++ SH_PFC_PIN_GROUP(hscif3_data_a), ++ SH_PFC_PIN_GROUP(hscif3_clk), ++ SH_PFC_PIN_GROUP(hscif3_ctrl), ++ SH_PFC_PIN_GROUP(hscif3_data_b), ++ SH_PFC_PIN_GROUP(hscif3_data_c), ++ SH_PFC_PIN_GROUP(hscif3_data_d), ++ SH_PFC_PIN_GROUP(hscif4_data_a), ++ SH_PFC_PIN_GROUP(hscif4_clk), ++ SH_PFC_PIN_GROUP(hscif4_ctrl), ++ SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c2_a), +@@ -3474,6 +3709,49 @@ static const char * const du_groups[] = + "du_disp", + }; + ++static const char * const hscif0_groups[] = { ++ "hscif0_data", ++ "hscif0_clk", ++ "hscif0_ctrl", ++}; ++ ++static const char * const hscif1_groups[] = { ++ "hscif1_data_a", ++ "hscif1_clk_a", ++ "hscif1_ctrl_a", ++ "hscif1_data_b", ++ "hscif1_clk_b", ++ "hscif1_ctrl_b", ++}; ++ ++static const char * const hscif2_groups[] = { ++ "hscif2_data_a", ++ "hscif2_clk_a", ++ "hscif2_ctrl_a", ++ "hscif2_data_b", ++ "hscif2_clk_b", ++ "hscif2_ctrl_b", ++ "hscif2_data_c", ++ "hscif2_clk_c", ++ "hscif2_ctrl_c", ++}; ++ ++static const char * const hscif3_groups[] = { ++ "hscif3_data_a", ++ "hscif3_clk", ++ "hscif3_ctrl", ++ "hscif3_data_b", ++ "hscif3_data_c", ++ "hscif3_data_d", ++}; ++ ++static const char * const hscif4_groups[] = { ++ "hscif4_data_a", ++ "hscif4_clk", ++ "hscif4_ctrl", ++ "hscif4_data_b", ++}; ++ + static const char * const i2c1_groups[] = { + "i2c1_a", + "i2c1_b", +@@ -3701,6 +3979,11 @@ static const struct sh_pfc_function pinm + SH_PFC_FUNCTION(drif2), + SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(du), ++ SH_PFC_FUNCTION(hscif0), ++ SH_PFC_FUNCTION(hscif1), ++ SH_PFC_FUNCTION(hscif2), ++ SH_PFC_FUNCTION(hscif3), ++ SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c6), diff --git a/patches.renesas/0169-pinctrl-sh-pfc-r8a7791-Add-ADI-pinconf-support.patch b/patches.renesas/0169-pinctrl-sh-pfc-r8a7791-Add-ADI-pinconf-support.patch new file mode 100644 index 0000000000000..8a010a217ccd5 --- /dev/null +++ b/patches.renesas/0169-pinctrl-sh-pfc-r8a7791-Add-ADI-pinconf-support.patch @@ -0,0 +1,132 @@ +From 8ecd1130c505e2f9342e5262b0aa9fa837e9a304 Mon Sep 17 00:00:00 2001 +From: Jacopo Mondi <jacopo@jmondi.org> +Date: Thu, 1 Dec 2016 23:14:12 +0100 +Subject: [PATCH 169/255] pinctrl: sh-pfc: r8a7791: Add ADI pinconf support + +Add pin configuration support for Gyro-ADC, named ADI on r8a7791 SoC. + +Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> +Tested-by: Marek Vasut <marek.vasut@gmail.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 07254d835dfc1e06a8cdfb565e7371176a4b93f9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 86 +++++++++++++++++++++++++++++++++++ + 1 file changed, 86 insertions(+) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -1695,6 +1695,72 @@ static const struct sh_pfc_pin pinmux_pi + PINMUX_GPIO_GP_ALL(), + }; + ++/* - ADI -------------------------------------------------------------------- */ ++static const unsigned int adi_common_pins[] = { ++ /* ADIDATA, ADICS/SAMP, ADICLK */ ++ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), ++}; ++static const unsigned int adi_common_mux[] = { ++ /* ADIDATA, ADICS/SAMP, ADICLK */ ++ ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK, ++}; ++static const unsigned int adi_chsel0_pins[] = { ++ /* ADICHS 0 */ ++ RCAR_GP_PIN(6, 27), ++}; ++static const unsigned int adi_chsel0_mux[] = { ++ /* ADICHS 0 */ ++ ADICHS0_MARK, ++}; ++static const unsigned int adi_chsel1_pins[] = { ++ /* ADICHS 1 */ ++ RCAR_GP_PIN(6, 28), ++}; ++static const unsigned int adi_chsel1_mux[] = { ++ /* ADICHS 1 */ ++ ADICHS1_MARK, ++}; ++static const unsigned int adi_chsel2_pins[] = { ++ /* ADICHS 2 */ ++ RCAR_GP_PIN(6, 29), ++}; ++static const unsigned int adi_chsel2_mux[] = { ++ /* ADICHS 2 */ ++ ADICHS2_MARK, ++}; ++static const unsigned int adi_common_b_pins[] = { ++ /* ADIDATA B, ADICS/SAMP B, ADICLK B */ ++ RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), ++}; ++static const unsigned int adi_common_b_mux[] = { ++ /* ADIDATA B, ADICS/SAMP B, ADICLK B */ ++ ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK, ++}; ++static const unsigned int adi_chsel0_b_pins[] = { ++ /* ADICHS B 0 */ ++ RCAR_GP_PIN(5, 28), ++}; ++static const unsigned int adi_chsel0_b_mux[] = { ++ /* ADICHS B 0 */ ++ ADICHS0_B_MARK, ++}; ++static const unsigned int adi_chsel1_b_pins[] = { ++ /* ADICHS B 1 */ ++ RCAR_GP_PIN(5, 29), ++}; ++static const unsigned int adi_chsel1_b_mux[] = { ++ /* ADICHS B 1 */ ++ ADICHS1_B_MARK, ++}; ++static const unsigned int adi_chsel2_b_pins[] = { ++ /* ADICHS B 2 */ ++ RCAR_GP_PIN(5, 30), ++}; ++static const unsigned int adi_chsel2_b_mux[] = { ++ /* ADICHS B 2 */ ++ ADICHS2_B_MARK, ++}; ++ + /* - Audio Clock ------------------------------------------------------------ */ + static const unsigned int audio_clk_a_pins[] = { + /* CLK */ +@@ -4347,6 +4413,14 @@ static const unsigned int vin2_clk_mux[] + }; + + static const struct sh_pfc_pin_group pinmux_groups[] = { ++ SH_PFC_PIN_GROUP(adi_common), ++ SH_PFC_PIN_GROUP(adi_chsel0), ++ SH_PFC_PIN_GROUP(adi_chsel1), ++ SH_PFC_PIN_GROUP(adi_chsel2), ++ SH_PFC_PIN_GROUP(adi_common_b), ++ SH_PFC_PIN_GROUP(adi_chsel0_b), ++ SH_PFC_PIN_GROUP(adi_chsel1_b), ++ SH_PFC_PIN_GROUP(adi_chsel2_b), + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clk_b_b), +@@ -4691,6 +4765,17 @@ static const struct sh_pfc_pin_group pin + SH_PFC_PIN_GROUP(vin2_clk), + }; + ++static const char * const adi_groups[] = { ++ "adi_common", ++ "adi_chsel0", ++ "adi_chsel1", ++ "adi_chsel2", ++ "adi_common_b", ++ "adi_chsel0_b", ++ "adi_chsel1_b", ++ "adi_chsel2_b", ++}; ++ + static const char * const audio_clk_groups[] = { + "audio_clk_a", + "audio_clk_b", +@@ -5196,6 +5281,7 @@ static const char * const vin2_groups[] + }; + + static const struct sh_pfc_function pinmux_functions[] = { ++ SH_PFC_FUNCTION(adi), + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), diff --git a/patches.renesas/0170-tty-serial-sh-sci-set-error-code-when-kasprintf-fail.patch b/patches.renesas/0170-tty-serial-sh-sci-set-error-code-when-kasprintf-fail.patch new file mode 100644 index 0000000000000..a8baafc662035 --- /dev/null +++ b/patches.renesas/0170-tty-serial-sh-sci-set-error-code-when-kasprintf-fail.patch @@ -0,0 +1,37 @@ +From 6bdd9719a00061d387517cd5690e2130525d5e6b Mon Sep 17 00:00:00 2001 +From: Pan Bian <bianpan2016@163.com> +Date: Sat, 3 Dec 2016 18:40:25 +0800 +Subject: [PATCH 170/255] tty: serial: sh-sci: set error code when kasprintf + fails + +When the call to kasprintf() returns a NULL pointer, function +sci_request_irq() frees the preallocated memory and returns 0 is +returned. Because 0 means no error, the caller of sci_request_irq() +will keep going, and the freed memory may be used or freed again. To +avoid the above issue, this patch assigns "-ENOMEM" to the return +variable ret. + +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=188691 + +Signed-off-by: Pan Bian <bianpan2016@163.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 623ac1d4a52f279d9379bae61ae1eb37c5767f96) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -1743,8 +1743,10 @@ static int sci_request_irq(struct sci_po + desc = sci_irq_desc + i; + port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", + dev_name(up->dev), desc->desc); +- if (!port->irqstr[j]) ++ if (!port->irqstr[j]) { ++ ret = -ENOMEM; + goto out_nomem; ++ } + + ret = request_irq(irq, desc->handler, up->irqflags, + port->irqstr[j], port); diff --git a/patches.renesas/0171-serial-sh-sci-Set-the-SCSCR-TE-and-RE-bits-in-the-dr.patch b/patches.renesas/0171-serial-sh-sci-Set-the-SCSCR-TE-and-RE-bits-in-the-dr.patch new file mode 100644 index 0000000000000..95448ed75f7c3 --- /dev/null +++ b/patches.renesas/0171-serial-sh-sci-Set-the-SCSCR-TE-and-RE-bits-in-the-dr.patch @@ -0,0 +1,62 @@ +From 605282473a9d30883cd53ac235957a26589e4437 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Jan 2017 16:43:23 +0200 +Subject: [PATCH 171/255] serial: sh-sci: Set the SCSCR TE and RE bits in the + driver + +The Transmit Enable and Receive Enable bits are set in the scscr field +of all instances of the sh-sci platform data. Set them in the driver +directly to prepare for their removal from platform data. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 9f8325b3c19cf2e5df6b9624480748421104d00c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -2345,7 +2345,8 @@ done: + serial_port_out(port, SCFCR, ctrl); + } + +- scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0); ++ scr_val |= SCSCR_RE | SCSCR_TE | ++ (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); + dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val); + serial_port_out(port, SCSCR, scr_val); + if ((srr + 1 == 5) && +@@ -2799,7 +2800,8 @@ static void serial_console_write(struct + + /* first save SCSCR then disable interrupts, keep clock source */ + ctrl = serial_port_in(port, SCSCR); +- ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | ++ ctrl_temp = SCSCR_RE | SCSCR_TE | ++ (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | + (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); + serial_port_out(port, SCSCR, ctrl_temp); + +@@ -3002,7 +3004,6 @@ sci_parse_dt(struct platform_device *pde + p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; + p->type = SCI_OF_TYPE(match->data); + p->regtype = SCI_OF_REGTYPE(match->data); +- p->scscr = SCSCR_RE | SCSCR_TE; + + if (of_find_property(np, "uart-has-rtscts", NULL)) + p->capabilities |= SCIx_HAVE_RTSCTS; +@@ -3170,9 +3171,9 @@ static int __init early_console_setup(st + sci_ports[0].cfg = &port_cfg; + sci_ports[0].cfg->type = type; + sci_probe_regmap(sci_ports[0].cfg); +- port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) | +- SCSCR_RE | SCSCR_TE; +- sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr); ++ port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); ++ sci_serial_out(&sci_ports[0].port, SCSCR, ++ SCSCR_RE | SCSCR_TE | port_cfg.scscr); + + device->con->write = serial_console_write; + return 0; diff --git a/patches.renesas/0172-serial-sh-sci-Don-t-rely-on-platform-data-flags-when.patch b/patches.renesas/0172-serial-sh-sci-Don-t-rely-on-platform-data-flags-when.patch new file mode 100644 index 0000000000000..8641e20ad253e --- /dev/null +++ b/patches.renesas/0172-serial-sh-sci-Don-t-rely-on-platform-data-flags-when.patch @@ -0,0 +1,59 @@ +From 72b1ef6ddb73200e5afaedb6f7440bfd8a7187a2 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Jan 2017 16:43:24 +0200 +Subject: [PATCH 172/255] serial: sh-sci: Don't rely on platform data flags + when not needed + +The UPF_BOOT_AUTOCONF platform data flag is set by all platforms, +hardcode it. + +The UPF_IOREMAP flag is set by a single SH platform and thus needs to be +kept. However, for ARM platforms, we can base the decision on whether an +OF node is present and bypass the platform data flags completely. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 3d73f32bfa312155a0990efd95803a3e7061140c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -2461,7 +2461,7 @@ static int sci_remap_port(struct uart_po + if (port->membase) + return 0; + +- if (port->flags & UPF_IOREMAP) { ++ if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { + port->membase = ioremap_nocache(port->mapbase, sport->reg_size); + if (unlikely(!port->membase)) { + dev_err(port->dev, "can't remap port#%d\n", port->line); +@@ -2483,7 +2483,7 @@ static void sci_release_port(struct uart + { + struct sci_port *sport = to_sci_port(port); + +- if (port->flags & UPF_IOREMAP) { ++ if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { + iounmap(port->membase); + port->membase = NULL; + } +@@ -2739,7 +2739,7 @@ static int sci_init_single(struct platfo + } + + port->type = p->type; +- port->flags = UPF_FIXED_PORT | p->flags; ++ port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; + port->regshift = p->regshift; + + /* +@@ -3001,7 +3001,6 @@ sci_parse_dt(struct platform_device *pde + + *dev_id = id; + +- p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; + p->type = SCI_OF_TYPE(match->data); + p->regtype = SCI_OF_REGTYPE(match->data); + diff --git a/patches.renesas/0173-serial-sh-sci-Fix-register-offsets-for-the-IRDA-seri.patch b/patches.renesas/0173-serial-sh-sci-Fix-register-offsets-for-the-IRDA-seri.patch new file mode 100644 index 0000000000000..dc937822a64e3 --- /dev/null +++ b/patches.renesas/0173-serial-sh-sci-Fix-register-offsets-for-the-IRDA-seri.patch @@ -0,0 +1,60 @@ +From 7407ea3dca099c60c5ac422e5c0b40b93d8bb946 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Jan 2017 16:43:32 +0200 +Subject: [PATCH 173/255] serial: sh-sci: Fix register offsets for the IRDA + serial port + +Even though most of its registers are 8-bit wide, the IRDA has two +16-bit registers that make it a 16-bit peripheral and not a 8-bit +peripheral with addresses shifted by one. Fix the registers offset in +the driver and the platform data regshift value. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit a752ba18af8285e3eeda572f40dddaebff0c3621) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/sh/kernel/cpu/sh3/setup-sh770x.c | 1 - + drivers/tty/serial/sh-sci.c | 17 ++++++++--------- + 2 files changed, 8 insertions(+), 10 deletions(-) + +--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c ++++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c +@@ -165,7 +165,6 @@ static struct plat_sci_port scif2_platfo + .scscr = SCSCR_TE | SCSCR_RE, + .type = PORT_IRDA, + .ops = &sh770x_sci_port_ops, +- .regshift = 1, + }; + + static struct resource scif2_resources[] = { +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -193,18 +193,17 @@ static const struct plat_sci_reg sci_reg + }, + + /* +- * Common definitions for legacy IrDA ports, dependent on +- * regshift value. ++ * Common definitions for legacy IrDA ports. + */ + [SCIx_IRDA_REGTYPE] = { + [SCSMR] = { 0x00, 8 }, +- [SCBRR] = { 0x01, 8 }, +- [SCSCR] = { 0x02, 8 }, +- [SCxTDR] = { 0x03, 8 }, +- [SCxSR] = { 0x04, 8 }, +- [SCxRDR] = { 0x05, 8 }, +- [SCFCR] = { 0x06, 8 }, +- [SCFDR] = { 0x07, 16 }, ++ [SCBRR] = { 0x02, 8 }, ++ [SCSCR] = { 0x04, 8 }, ++ [SCxTDR] = { 0x06, 8 }, ++ [SCxSR] = { 0x08, 16 }, ++ [SCxRDR] = { 0x0a, 8 }, ++ [SCFCR] = { 0x0c, 8 }, ++ [SCFDR] = { 0x0e, 16 }, + [SCTFDR] = sci_reg_invalid, + [SCRFDR] = sci_reg_invalid, + [SCSPTR] = sci_reg_invalid, diff --git a/patches.renesas/0174-serial-sh-sci-Remove-initialization-of-zero-fields-i.patch b/patches.renesas/0174-serial-sh-sci-Remove-initialization-of-zero-fields-i.patch new file mode 100644 index 0000000000000..4e66bd42858fe --- /dev/null +++ b/patches.renesas/0174-serial-sh-sci-Remove-initialization-of-zero-fields-i.patch @@ -0,0 +1,221 @@ +From 9c43e3295ad6351d0e75770a1b88ee7b507bebd8 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Jan 2017 16:43:33 +0200 +Subject: [PATCH 174/255] serial: sh-sci: Remove initialization of zero fields + in sci_port_params + +The compiler zeros uninitialized fields, don't zero them manually. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 40b34ddb0385a2a698dec150b50e6b400fc373a0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 94 -------------------------------------------- + 1 file changed, 94 deletions(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -160,14 +160,7 @@ struct plat_sci_reg { + u8 offset, size; + }; + +-/* Helper for invalidating specific entries of an inherited map. */ +-#define sci_reg_invalid { .offset = 0, .size = 0 } +- + static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { +- [SCIx_PROBE_REGTYPE] = { +- [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, +- }, +- + /* + * Common SCI definitions, dependent on the port's regshift + * value. +@@ -179,17 +172,6 @@ static const struct plat_sci_reg sci_reg + [SCxTDR] = { 0x03, 8 }, + [SCxSR] = { 0x04, 8 }, + [SCxRDR] = { 0x05, 8 }, +- [SCFCR] = sci_reg_invalid, +- [SCFDR] = sci_reg_invalid, +- [SCTFDR] = sci_reg_invalid, +- [SCRFDR] = sci_reg_invalid, +- [SCSPTR] = sci_reg_invalid, +- [SCLSR] = sci_reg_invalid, +- [HSSRR] = sci_reg_invalid, +- [SCPCR] = sci_reg_invalid, +- [SCPDR] = sci_reg_invalid, +- [SCDL] = sci_reg_invalid, +- [SCCKS] = sci_reg_invalid, + }, + + /* +@@ -204,15 +186,6 @@ static const struct plat_sci_reg sci_reg + [SCxRDR] = { 0x0a, 8 }, + [SCFCR] = { 0x0c, 8 }, + [SCFDR] = { 0x0e, 16 }, +- [SCTFDR] = sci_reg_invalid, +- [SCRFDR] = sci_reg_invalid, +- [SCSPTR] = sci_reg_invalid, +- [SCLSR] = sci_reg_invalid, +- [HSSRR] = sci_reg_invalid, +- [SCPCR] = sci_reg_invalid, +- [SCPDR] = sci_reg_invalid, +- [SCDL] = sci_reg_invalid, +- [SCCKS] = sci_reg_invalid, + }, + + /* +@@ -227,15 +200,8 @@ static const struct plat_sci_reg sci_reg + [SCxRDR] = { 0x24, 8 }, + [SCFCR] = { 0x18, 16 }, + [SCFDR] = { 0x1c, 16 }, +- [SCTFDR] = sci_reg_invalid, +- [SCRFDR] = sci_reg_invalid, +- [SCSPTR] = sci_reg_invalid, +- [SCLSR] = sci_reg_invalid, +- [HSSRR] = sci_reg_invalid, + [SCPCR] = { 0x30, 16 }, + [SCPDR] = { 0x34, 16 }, +- [SCDL] = sci_reg_invalid, +- [SCCKS] = sci_reg_invalid, + }, + + /* +@@ -249,16 +215,10 @@ static const struct plat_sci_reg sci_reg + [SCxSR] = { 0x14, 16 }, + [SCxRDR] = { 0x60, 8 }, + [SCFCR] = { 0x18, 16 }, +- [SCFDR] = sci_reg_invalid, + [SCTFDR] = { 0x38, 16 }, + [SCRFDR] = { 0x3c, 16 }, +- [SCSPTR] = sci_reg_invalid, +- [SCLSR] = sci_reg_invalid, +- [HSSRR] = sci_reg_invalid, + [SCPCR] = { 0x30, 16 }, + [SCPDR] = { 0x34, 16 }, +- [SCDL] = sci_reg_invalid, +- [SCCKS] = sci_reg_invalid, + }, + + /* +@@ -274,15 +234,8 @@ static const struct plat_sci_reg sci_reg + [SCxRDR] = { 0x14, 8 }, + [SCFCR] = { 0x18, 16 }, + [SCFDR] = { 0x1c, 16 }, +- [SCTFDR] = sci_reg_invalid, +- [SCRFDR] = sci_reg_invalid, + [SCSPTR] = { 0x20, 16 }, + [SCLSR] = { 0x24, 16 }, +- [HSSRR] = sci_reg_invalid, +- [SCPCR] = sci_reg_invalid, +- [SCPDR] = sci_reg_invalid, +- [SCDL] = sci_reg_invalid, +- [SCCKS] = sci_reg_invalid, + }, + + /* +@@ -297,15 +250,6 @@ static const struct plat_sci_reg sci_reg + [SCxRDR] = { 0x0a, 8 }, + [SCFCR] = { 0x0c, 8 }, + [SCFDR] = { 0x0e, 16 }, +- [SCTFDR] = sci_reg_invalid, +- [SCRFDR] = sci_reg_invalid, +- [SCSPTR] = sci_reg_invalid, +- [SCLSR] = sci_reg_invalid, +- [HSSRR] = sci_reg_invalid, +- [SCPCR] = sci_reg_invalid, +- [SCPDR] = sci_reg_invalid, +- [SCDL] = sci_reg_invalid, +- [SCCKS] = sci_reg_invalid, + }, + + /* +@@ -320,15 +264,8 @@ static const struct plat_sci_reg sci_reg + [SCxRDR] = { 0x14, 8 }, + [SCFCR] = { 0x18, 16 }, + [SCFDR] = { 0x1c, 16 }, +- [SCTFDR] = sci_reg_invalid, +- [SCRFDR] = sci_reg_invalid, + [SCSPTR] = { 0x20, 16 }, + [SCLSR] = { 0x24, 16 }, +- [HSSRR] = sci_reg_invalid, +- [SCPCR] = sci_reg_invalid, +- [SCPDR] = sci_reg_invalid, +- [SCDL] = sci_reg_invalid, +- [SCCKS] = sci_reg_invalid, + }, + + /* +@@ -344,13 +281,8 @@ static const struct plat_sci_reg sci_reg + [SCxRDR] = { 0x14, 8 }, + [SCFCR] = { 0x18, 16 }, + [SCFDR] = { 0x1c, 16 }, +- [SCTFDR] = sci_reg_invalid, +- [SCRFDR] = sci_reg_invalid, + [SCSPTR] = { 0x20, 16 }, + [SCLSR] = { 0x24, 16 }, +- [HSSRR] = sci_reg_invalid, +- [SCPCR] = sci_reg_invalid, +- [SCPDR] = sci_reg_invalid, + [SCDL] = { 0x30, 16 }, + [SCCKS] = { 0x34, 16 }, + }, +@@ -367,13 +299,9 @@ static const struct plat_sci_reg sci_reg + [SCxRDR] = { 0x14, 8 }, + [SCFCR] = { 0x18, 16 }, + [SCFDR] = { 0x1c, 16 }, +- [SCTFDR] = sci_reg_invalid, +- [SCRFDR] = sci_reg_invalid, + [SCSPTR] = { 0x20, 16 }, + [SCLSR] = { 0x24, 16 }, + [HSSRR] = { 0x40, 16 }, +- [SCPCR] = sci_reg_invalid, +- [SCPDR] = sci_reg_invalid, + [SCDL] = { 0x30, 16 }, + [SCCKS] = { 0x34, 16 }, + }, +@@ -391,15 +319,7 @@ static const struct plat_sci_reg sci_reg + [SCxRDR] = { 0x14, 8 }, + [SCFCR] = { 0x18, 16 }, + [SCFDR] = { 0x1c, 16 }, +- [SCTFDR] = sci_reg_invalid, +- [SCRFDR] = sci_reg_invalid, +- [SCSPTR] = sci_reg_invalid, + [SCLSR] = { 0x24, 16 }, +- [HSSRR] = sci_reg_invalid, +- [SCPCR] = sci_reg_invalid, +- [SCPDR] = sci_reg_invalid, +- [SCDL] = sci_reg_invalid, +- [SCCKS] = sci_reg_invalid, + }, + + /* +@@ -419,11 +339,6 @@ static const struct plat_sci_reg sci_reg + [SCRFDR] = { 0x20, 16 }, + [SCSPTR] = { 0x24, 16 }, + [SCLSR] = { 0x28, 16 }, +- [HSSRR] = sci_reg_invalid, +- [SCPCR] = sci_reg_invalid, +- [SCPDR] = sci_reg_invalid, +- [SCDL] = sci_reg_invalid, +- [SCCKS] = sci_reg_invalid, + }, + + /* +@@ -439,15 +354,6 @@ static const struct plat_sci_reg sci_reg + [SCxRDR] = { 0x24, 8 }, + [SCFCR] = { 0x18, 16 }, + [SCFDR] = { 0x1c, 16 }, +- [SCTFDR] = sci_reg_invalid, +- [SCRFDR] = sci_reg_invalid, +- [SCSPTR] = sci_reg_invalid, +- [SCLSR] = sci_reg_invalid, +- [HSSRR] = sci_reg_invalid, +- [SCPCR] = sci_reg_invalid, +- [SCPDR] = sci_reg_invalid, +- [SCDL] = sci_reg_invalid, +- [SCCKS] = sci_reg_invalid, + }, + }; + diff --git a/patches.renesas/0175-serial-sh-sci-Replace-regmap-array-with-port-paramet.patch b/patches.renesas/0175-serial-sh-sci-Replace-regmap-array-with-port-paramet.patch new file mode 100644 index 0000000000000..f231648a43d0f --- /dev/null +++ b/patches.renesas/0175-serial-sh-sci-Replace-regmap-array-with-port-paramet.patch @@ -0,0 +1,410 @@ +From 215037910bc0dbe6931f71d28e20b90c34126b21 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Jan 2017 16:43:34 +0200 +Subject: [PATCH 175/255] serial: sh-sci: Replace regmap array with port + parameters + +Turn the regmap two-dimensional array to an array of port parameters and +store a pointer to the port parameters in the sci_port structure. This +will allow handling additional port type dependent parameters. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit e095ee6b447a35ea90c523ce399d5a61753ade25) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 278 ++++++++++++++++++++++++-------------------- + 1 file changed, 155 insertions(+), 123 deletions(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -101,10 +101,19 @@ enum SCI_CLKS { + for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ + if ((_port)->sampling_rate_mask & SCI_SR((_sr))) + ++struct plat_sci_reg { ++ u8 offset, size; ++}; ++ ++struct sci_port_params { ++ const struct plat_sci_reg regs[SCIx_NR_REGS]; ++}; ++ + struct sci_port { + struct uart_port port; + + /* Platform configuration */ ++ const struct sci_port_params *params; + struct plat_sci_port *cfg; + unsigned int overrun_reg; + unsigned int overrun_mask; +@@ -156,69 +165,73 @@ to_sci_port(struct uart_port *uart) + return container_of(uart, struct sci_port, port); + } + +-struct plat_sci_reg { +- u8 offset, size; +-}; +- +-static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { ++static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { + /* + * Common SCI definitions, dependent on the port's regshift + * value. + */ + [SCIx_SCI_REGTYPE] = { +- [SCSMR] = { 0x00, 8 }, +- [SCBRR] = { 0x01, 8 }, +- [SCSCR] = { 0x02, 8 }, +- [SCxTDR] = { 0x03, 8 }, +- [SCxSR] = { 0x04, 8 }, +- [SCxRDR] = { 0x05, 8 }, ++ .regs = { ++ [SCSMR] = { 0x00, 8 }, ++ [SCBRR] = { 0x01, 8 }, ++ [SCSCR] = { 0x02, 8 }, ++ [SCxTDR] = { 0x03, 8 }, ++ [SCxSR] = { 0x04, 8 }, ++ [SCxRDR] = { 0x05, 8 }, ++ }, + }, + + /* + * Common definitions for legacy IrDA ports. + */ + [SCIx_IRDA_REGTYPE] = { +- [SCSMR] = { 0x00, 8 }, +- [SCBRR] = { 0x02, 8 }, +- [SCSCR] = { 0x04, 8 }, +- [SCxTDR] = { 0x06, 8 }, +- [SCxSR] = { 0x08, 16 }, +- [SCxRDR] = { 0x0a, 8 }, +- [SCFCR] = { 0x0c, 8 }, +- [SCFDR] = { 0x0e, 16 }, ++ .regs = { ++ [SCSMR] = { 0x00, 8 }, ++ [SCBRR] = { 0x02, 8 }, ++ [SCSCR] = { 0x04, 8 }, ++ [SCxTDR] = { 0x06, 8 }, ++ [SCxSR] = { 0x08, 16 }, ++ [SCxRDR] = { 0x0a, 8 }, ++ [SCFCR] = { 0x0c, 8 }, ++ [SCFDR] = { 0x0e, 16 }, ++ }, + }, + + /* + * Common SCIFA definitions. + */ + [SCIx_SCIFA_REGTYPE] = { +- [SCSMR] = { 0x00, 16 }, +- [SCBRR] = { 0x04, 8 }, +- [SCSCR] = { 0x08, 16 }, +- [SCxTDR] = { 0x20, 8 }, +- [SCxSR] = { 0x14, 16 }, +- [SCxRDR] = { 0x24, 8 }, +- [SCFCR] = { 0x18, 16 }, +- [SCFDR] = { 0x1c, 16 }, +- [SCPCR] = { 0x30, 16 }, +- [SCPDR] = { 0x34, 16 }, ++ .regs = { ++ [SCSMR] = { 0x00, 16 }, ++ [SCBRR] = { 0x04, 8 }, ++ [SCSCR] = { 0x08, 16 }, ++ [SCxTDR] = { 0x20, 8 }, ++ [SCxSR] = { 0x14, 16 }, ++ [SCxRDR] = { 0x24, 8 }, ++ [SCFCR] = { 0x18, 16 }, ++ [SCFDR] = { 0x1c, 16 }, ++ [SCPCR] = { 0x30, 16 }, ++ [SCPDR] = { 0x34, 16 }, ++ }, + }, + + /* + * Common SCIFB definitions. + */ + [SCIx_SCIFB_REGTYPE] = { +- [SCSMR] = { 0x00, 16 }, +- [SCBRR] = { 0x04, 8 }, +- [SCSCR] = { 0x08, 16 }, +- [SCxTDR] = { 0x40, 8 }, +- [SCxSR] = { 0x14, 16 }, +- [SCxRDR] = { 0x60, 8 }, +- [SCFCR] = { 0x18, 16 }, +- [SCTFDR] = { 0x38, 16 }, +- [SCRFDR] = { 0x3c, 16 }, +- [SCPCR] = { 0x30, 16 }, +- [SCPDR] = { 0x34, 16 }, ++ .regs = { ++ [SCSMR] = { 0x00, 16 }, ++ [SCBRR] = { 0x04, 8 }, ++ [SCSCR] = { 0x08, 16 }, ++ [SCxTDR] = { 0x40, 8 }, ++ [SCxSR] = { 0x14, 16 }, ++ [SCxRDR] = { 0x60, 8 }, ++ [SCFCR] = { 0x18, 16 }, ++ [SCTFDR] = { 0x38, 16 }, ++ [SCRFDR] = { 0x3c, 16 }, ++ [SCPCR] = { 0x30, 16 }, ++ [SCPDR] = { 0x34, 16 }, ++ }, + }, + + /* +@@ -226,46 +239,52 @@ static const struct plat_sci_reg sci_reg + * count registers. + */ + [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { +- [SCSMR] = { 0x00, 16 }, +- [SCBRR] = { 0x04, 8 }, +- [SCSCR] = { 0x08, 16 }, +- [SCxTDR] = { 0x0c, 8 }, +- [SCxSR] = { 0x10, 16 }, +- [SCxRDR] = { 0x14, 8 }, +- [SCFCR] = { 0x18, 16 }, +- [SCFDR] = { 0x1c, 16 }, +- [SCSPTR] = { 0x20, 16 }, +- [SCLSR] = { 0x24, 16 }, ++ .regs = { ++ [SCSMR] = { 0x00, 16 }, ++ [SCBRR] = { 0x04, 8 }, ++ [SCSCR] = { 0x08, 16 }, ++ [SCxTDR] = { 0x0c, 8 }, ++ [SCxSR] = { 0x10, 16 }, ++ [SCxRDR] = { 0x14, 8 }, ++ [SCFCR] = { 0x18, 16 }, ++ [SCFDR] = { 0x1c, 16 }, ++ [SCSPTR] = { 0x20, 16 }, ++ [SCLSR] = { 0x24, 16 }, ++ }, + }, + + /* + * Common SH-3 SCIF definitions. + */ + [SCIx_SH3_SCIF_REGTYPE] = { +- [SCSMR] = { 0x00, 8 }, +- [SCBRR] = { 0x02, 8 }, +- [SCSCR] = { 0x04, 8 }, +- [SCxTDR] = { 0x06, 8 }, +- [SCxSR] = { 0x08, 16 }, +- [SCxRDR] = { 0x0a, 8 }, +- [SCFCR] = { 0x0c, 8 }, +- [SCFDR] = { 0x0e, 16 }, ++ .regs = { ++ [SCSMR] = { 0x00, 8 }, ++ [SCBRR] = { 0x02, 8 }, ++ [SCSCR] = { 0x04, 8 }, ++ [SCxTDR] = { 0x06, 8 }, ++ [SCxSR] = { 0x08, 16 }, ++ [SCxRDR] = { 0x0a, 8 }, ++ [SCFCR] = { 0x0c, 8 }, ++ [SCFDR] = { 0x0e, 16 }, ++ }, + }, + + /* + * Common SH-4(A) SCIF(B) definitions. + */ + [SCIx_SH4_SCIF_REGTYPE] = { +- [SCSMR] = { 0x00, 16 }, +- [SCBRR] = { 0x04, 8 }, +- [SCSCR] = { 0x08, 16 }, +- [SCxTDR] = { 0x0c, 8 }, +- [SCxSR] = { 0x10, 16 }, +- [SCxRDR] = { 0x14, 8 }, +- [SCFCR] = { 0x18, 16 }, +- [SCFDR] = { 0x1c, 16 }, +- [SCSPTR] = { 0x20, 16 }, +- [SCLSR] = { 0x24, 16 }, ++ .regs = { ++ [SCSMR] = { 0x00, 16 }, ++ [SCBRR] = { 0x04, 8 }, ++ [SCSCR] = { 0x08, 16 }, ++ [SCxTDR] = { 0x0c, 8 }, ++ [SCxSR] = { 0x10, 16 }, ++ [SCxRDR] = { 0x14, 8 }, ++ [SCFCR] = { 0x18, 16 }, ++ [SCFDR] = { 0x1c, 16 }, ++ [SCSPTR] = { 0x20, 16 }, ++ [SCLSR] = { 0x24, 16 }, ++ }, + }, + + /* +@@ -273,37 +292,41 @@ static const struct plat_sci_reg sci_reg + * External Clock (BRG). + */ + [SCIx_SH4_SCIF_BRG_REGTYPE] = { +- [SCSMR] = { 0x00, 16 }, +- [SCBRR] = { 0x04, 8 }, +- [SCSCR] = { 0x08, 16 }, +- [SCxTDR] = { 0x0c, 8 }, +- [SCxSR] = { 0x10, 16 }, +- [SCxRDR] = { 0x14, 8 }, +- [SCFCR] = { 0x18, 16 }, +- [SCFDR] = { 0x1c, 16 }, +- [SCSPTR] = { 0x20, 16 }, +- [SCLSR] = { 0x24, 16 }, +- [SCDL] = { 0x30, 16 }, +- [SCCKS] = { 0x34, 16 }, ++ .regs = { ++ [SCSMR] = { 0x00, 16 }, ++ [SCBRR] = { 0x04, 8 }, ++ [SCSCR] = { 0x08, 16 }, ++ [SCxTDR] = { 0x0c, 8 }, ++ [SCxSR] = { 0x10, 16 }, ++ [SCxRDR] = { 0x14, 8 }, ++ [SCFCR] = { 0x18, 16 }, ++ [SCFDR] = { 0x1c, 16 }, ++ [SCSPTR] = { 0x20, 16 }, ++ [SCLSR] = { 0x24, 16 }, ++ [SCDL] = { 0x30, 16 }, ++ [SCCKS] = { 0x34, 16 }, ++ }, + }, + + /* + * Common HSCIF definitions. + */ + [SCIx_HSCIF_REGTYPE] = { +- [SCSMR] = { 0x00, 16 }, +- [SCBRR] = { 0x04, 8 }, +- [SCSCR] = { 0x08, 16 }, +- [SCxTDR] = { 0x0c, 8 }, +- [SCxSR] = { 0x10, 16 }, +- [SCxRDR] = { 0x14, 8 }, +- [SCFCR] = { 0x18, 16 }, +- [SCFDR] = { 0x1c, 16 }, +- [SCSPTR] = { 0x20, 16 }, +- [SCLSR] = { 0x24, 16 }, +- [HSSRR] = { 0x40, 16 }, +- [SCDL] = { 0x30, 16 }, +- [SCCKS] = { 0x34, 16 }, ++ .regs = { ++ [SCSMR] = { 0x00, 16 }, ++ [SCBRR] = { 0x04, 8 }, ++ [SCSCR] = { 0x08, 16 }, ++ [SCxTDR] = { 0x0c, 8 }, ++ [SCxSR] = { 0x10, 16 }, ++ [SCxRDR] = { 0x14, 8 }, ++ [SCFCR] = { 0x18, 16 }, ++ [SCFDR] = { 0x1c, 16 }, ++ [SCSPTR] = { 0x20, 16 }, ++ [SCLSR] = { 0x24, 16 }, ++ [HSSRR] = { 0x40, 16 }, ++ [SCDL] = { 0x30, 16 }, ++ [SCCKS] = { 0x34, 16 }, ++ }, + }, + + /* +@@ -311,15 +334,17 @@ static const struct plat_sci_reg sci_reg + * register. + */ + [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { +- [SCSMR] = { 0x00, 16 }, +- [SCBRR] = { 0x04, 8 }, +- [SCSCR] = { 0x08, 16 }, +- [SCxTDR] = { 0x0c, 8 }, +- [SCxSR] = { 0x10, 16 }, +- [SCxRDR] = { 0x14, 8 }, +- [SCFCR] = { 0x18, 16 }, +- [SCFDR] = { 0x1c, 16 }, +- [SCLSR] = { 0x24, 16 }, ++ .regs = { ++ [SCSMR] = { 0x00, 16 }, ++ [SCBRR] = { 0x04, 8 }, ++ [SCSCR] = { 0x08, 16 }, ++ [SCxTDR] = { 0x0c, 8 }, ++ [SCxSR] = { 0x10, 16 }, ++ [SCxRDR] = { 0x14, 8 }, ++ [SCFCR] = { 0x18, 16 }, ++ [SCFDR] = { 0x1c, 16 }, ++ [SCLSR] = { 0x24, 16 }, ++ }, + }, + + /* +@@ -327,18 +352,20 @@ static const struct plat_sci_reg sci_reg + * count registers. + */ + [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { +- [SCSMR] = { 0x00, 16 }, +- [SCBRR] = { 0x04, 8 }, +- [SCSCR] = { 0x08, 16 }, +- [SCxTDR] = { 0x0c, 8 }, +- [SCxSR] = { 0x10, 16 }, +- [SCxRDR] = { 0x14, 8 }, +- [SCFCR] = { 0x18, 16 }, +- [SCFDR] = { 0x1c, 16 }, +- [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ +- [SCRFDR] = { 0x20, 16 }, +- [SCSPTR] = { 0x24, 16 }, +- [SCLSR] = { 0x28, 16 }, ++ .regs = { ++ [SCSMR] = { 0x00, 16 }, ++ [SCBRR] = { 0x04, 8 }, ++ [SCSCR] = { 0x08, 16 }, ++ [SCxTDR] = { 0x0c, 8 }, ++ [SCxSR] = { 0x10, 16 }, ++ [SCxRDR] = { 0x14, 8 }, ++ [SCFCR] = { 0x18, 16 }, ++ [SCFDR] = { 0x1c, 16 }, ++ [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ ++ [SCRFDR] = { 0x20, 16 }, ++ [SCSPTR] = { 0x24, 16 }, ++ [SCLSR] = { 0x28, 16 }, ++ }, + }, + + /* +@@ -346,18 +373,20 @@ static const struct plat_sci_reg sci_reg + * registers. + */ + [SCIx_SH7705_SCIF_REGTYPE] = { +- [SCSMR] = { 0x00, 16 }, +- [SCBRR] = { 0x04, 8 }, +- [SCSCR] = { 0x08, 16 }, +- [SCxTDR] = { 0x20, 8 }, +- [SCxSR] = { 0x14, 16 }, +- [SCxRDR] = { 0x24, 8 }, +- [SCFCR] = { 0x18, 16 }, +- [SCFDR] = { 0x1c, 16 }, ++ .regs = { ++ [SCSMR] = { 0x00, 16 }, ++ [SCBRR] = { 0x04, 8 }, ++ [SCSCR] = { 0x08, 16 }, ++ [SCxTDR] = { 0x20, 8 }, ++ [SCxSR] = { 0x14, 16 }, ++ [SCxRDR] = { 0x24, 8 }, ++ [SCFCR] = { 0x18, 16 }, ++ [SCFDR] = { 0x1c, 16 }, ++ }, + }, + }; + +-#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) ++#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) + + /* + * The "offset" here is rather misleading, in that it refers to an enum +@@ -2563,6 +2592,8 @@ static int sci_init_single(struct platfo + return ret; + } + ++ sci_port->params = &sci_port_params[p->regtype]; ++ + switch (p->type) { + case PORT_SCIFB: + port->fifosize = 256; +@@ -3075,6 +3106,7 @@ static int __init early_console_setup(st + sci_ports[0].cfg = &port_cfg; + sci_ports[0].cfg->type = type; + sci_probe_regmap(sci_ports[0].cfg); ++ sci_ports[0].params = &sci_port_params[sci_ports[0].cfg->regtype]; + port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); + sci_serial_out(&sci_ports[0].port, SCSCR, + SCSCR_RE | SCSCR_TE | port_cfg.scscr); diff --git a/patches.renesas/0176-serial-sh-sci-Constify-platform-data.patch b/patches.renesas/0176-serial-sh-sci-Constify-platform-data.patch new file mode 100644 index 0000000000000..32645e2d1a4e7 --- /dev/null +++ b/patches.renesas/0176-serial-sh-sci-Constify-platform-data.patch @@ -0,0 +1,161 @@ +From 119495e90c300f3159b36ba85039e99fcd5b23da Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Jan 2017 16:43:35 +0200 +Subject: [PATCH 176/255] serial: sh-sci: Constify platform data + +The driver modifies platform data for internal purpose only. Fix that +and make the platform data structure const. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit daf5a8959a835bd91534e0ab049d0bfe8448536d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 97 ++++++++++++++++++++++---------------------- + 1 file changed, 49 insertions(+), 48 deletions(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -114,7 +114,7 @@ struct sci_port { + + /* Platform configuration */ + const struct sci_port_params *params; +- struct plat_sci_port *cfg; ++ const struct plat_sci_port *cfg; + unsigned int overrun_reg; + unsigned int overrun_mask; + unsigned int error_mask; +@@ -420,41 +420,6 @@ static void sci_serial_out(struct uart_p + WARN(1, "Invalid register access\n"); + } + +-static int sci_probe_regmap(struct plat_sci_port *cfg) +-{ +- switch (cfg->type) { +- case PORT_SCI: +- cfg->regtype = SCIx_SCI_REGTYPE; +- break; +- case PORT_IRDA: +- cfg->regtype = SCIx_IRDA_REGTYPE; +- break; +- case PORT_SCIFA: +- cfg->regtype = SCIx_SCIFA_REGTYPE; +- break; +- case PORT_SCIFB: +- cfg->regtype = SCIx_SCIFB_REGTYPE; +- break; +- case PORT_SCIF: +- /* +- * The SH-4 is a bit of a misnomer here, although that's +- * where this particular port layout originated. This +- * configuration (or some slight variation thereof) +- * remains the dominant model for all SCIFs. +- */ +- cfg->regtype = SCIx_SH4_SCIF_REGTYPE; +- break; +- case PORT_HSCIF: +- cfg->regtype = SCIx_HSCIF_REGTYPE; +- break; +- default: +- pr_err("Can't probe register map for given port\n"); +- return -EINVAL; +- } +- +- return 0; +-} +- + static void sci_port_enable(struct sci_port *sci_port) + { + unsigned int i; +@@ -2547,9 +2512,50 @@ found: + return 0; + } + ++static const struct sci_port_params * ++sci_probe_regmap(const struct plat_sci_port *cfg) ++{ ++ unsigned int regtype; ++ ++ if (cfg->regtype != SCIx_PROBE_REGTYPE) ++ return &sci_port_params[cfg->regtype]; ++ ++ switch (cfg->type) { ++ case PORT_SCI: ++ regtype = SCIx_SCI_REGTYPE; ++ break; ++ case PORT_IRDA: ++ regtype = SCIx_IRDA_REGTYPE; ++ break; ++ case PORT_SCIFA: ++ regtype = SCIx_SCIFA_REGTYPE; ++ break; ++ case PORT_SCIFB: ++ regtype = SCIx_SCIFB_REGTYPE; ++ break; ++ case PORT_SCIF: ++ /* ++ * The SH-4 is a bit of a misnomer here, although that's ++ * where this particular port layout originated. This ++ * configuration (or some slight variation thereof) ++ * remains the dominant model for all SCIFs. ++ */ ++ regtype = SCIx_SH4_SCIF_REGTYPE; ++ break; ++ case PORT_HSCIF: ++ regtype = SCIx_HSCIF_REGTYPE; ++ break; ++ default: ++ pr_err("Can't probe register map for given port\n"); ++ return NULL; ++ } ++ ++ return &sci_port_params[regtype]; ++} ++ + static int sci_init_single(struct platform_device *dev, + struct sci_port *sci_port, unsigned int index, +- struct plat_sci_port *p, bool early) ++ const struct plat_sci_port *p, bool early) + { + struct uart_port *port = &sci_port->port; + const struct resource *res; +@@ -2586,13 +2592,9 @@ static int sci_init_single(struct platfo + sci_port->irqs[3] = sci_port->irqs[0]; + } + +- if (p->regtype == SCIx_PROBE_REGTYPE) { +- ret = sci_probe_regmap(p); +- if (unlikely(ret)) +- return ret; +- } +- +- sci_port->params = &sci_port_params[p->regtype]; ++ sci_port->params = sci_probe_regmap(p); ++ if (unlikely(sci_port->params == NULL)) ++ return -EINVAL; + + switch (p->type) { + case PORT_SCIFB: +@@ -2812,7 +2814,7 @@ static char early_serial_buf[32]; + + static int sci_probe_earlyprintk(struct platform_device *pdev) + { +- struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); ++ const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); + + if (early_serial_console.data) + return -EEXIST; +@@ -3103,10 +3105,9 @@ static int __init early_console_setup(st + device->port.serial_out = sci_serial_out; + device->port.type = type; + memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); ++ port_cfg.type = type; + sci_ports[0].cfg = &port_cfg; +- sci_ports[0].cfg->type = type; +- sci_probe_regmap(sci_ports[0].cfg); +- sci_ports[0].params = &sci_port_params[sci_ports[0].cfg->regtype]; ++ sci_ports[0].params = sci_probe_regmap(&port_cfg); + port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); + sci_serial_out(&sci_ports[0].port, SCSCR, + SCSCR_RE | SCSCR_TE | port_cfg.scscr); diff --git a/patches.renesas/0177-serial-sh-sci-Extend-sci_port_params-with-more-port-.patch b/patches.renesas/0177-serial-sh-sci-Extend-sci_port_params-with-more-port-.patch new file mode 100644 index 0000000000000..dfffd28416801 --- /dev/null +++ b/patches.renesas/0177-serial-sh-sci-Extend-sci_port_params-with-more-port-.patch @@ -0,0 +1,403 @@ +From 628b5dcebf1aca1b9fef75bb4cb3ce4bc208841f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Jan 2017 16:43:36 +0200 +Subject: [PATCH 177/255] serial: sh-sci: Extend sci_port_params with more port + parameters + +The fifo size, overrun register and mask, sampling rate mask and error +mask all depend on the port type only and don't need to be computed at +runtime. Add them to the sci_port_parameters structure. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit b2f20ed9c483859e2e83cfb1a3193e40760c18ad) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 181 ++++++++++++++++++++++++-------------------- + drivers/tty/serial/sh-sci.h | 4 + 2 files changed, 102 insertions(+), 83 deletions(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -107,6 +107,12 @@ struct plat_sci_reg { + + struct sci_port_params { + const struct plat_sci_reg regs[SCIx_NR_REGS]; ++ unsigned int fifosize; ++ unsigned int overrun_reg; ++ unsigned int overrun_mask; ++ unsigned int sampling_rate_mask; ++ unsigned int error_mask; ++ unsigned int error_clear; + }; + + struct sci_port { +@@ -115,10 +121,6 @@ struct sci_port { + /* Platform configuration */ + const struct sci_port_params *params; + const struct plat_sci_port *cfg; +- unsigned int overrun_reg; +- unsigned int overrun_mask; +- unsigned int error_mask; +- unsigned int error_clear; + unsigned int sampling_rate_mask; + resource_size_t reg_size; + struct mctrl_gpios *gpios; +@@ -179,6 +181,12 @@ static const struct sci_port_params sci_ + [SCxSR] = { 0x04, 8 }, + [SCxRDR] = { 0x05, 8 }, + }, ++ .fifosize = 1, ++ .overrun_reg = SCxSR, ++ .overrun_mask = SCI_ORER, ++ .sampling_rate_mask = SCI_SR(32), ++ .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, ++ .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, + }, + + /* +@@ -195,6 +203,12 @@ static const struct sci_port_params sci_ + [SCFCR] = { 0x0c, 8 }, + [SCFDR] = { 0x0e, 16 }, + }, ++ .fifosize = 1, ++ .overrun_reg = SCxSR, ++ .overrun_mask = SCI_ORER, ++ .sampling_rate_mask = SCI_SR(32), ++ .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, ++ .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, + }, + + /* +@@ -213,6 +227,12 @@ static const struct sci_port_params sci_ + [SCPCR] = { 0x30, 16 }, + [SCPDR] = { 0x34, 16 }, + }, ++ .fifosize = 64, ++ .overrun_reg = SCxSR, ++ .overrun_mask = SCIFA_ORER, ++ .sampling_rate_mask = SCI_SR_SCIFAB, ++ .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, ++ .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, + }, + + /* +@@ -232,6 +252,12 @@ static const struct sci_port_params sci_ + [SCPCR] = { 0x30, 16 }, + [SCPDR] = { 0x34, 16 }, + }, ++ .fifosize = 256, ++ .overrun_reg = SCxSR, ++ .overrun_mask = SCIFA_ORER, ++ .sampling_rate_mask = SCI_SR_SCIFAB, ++ .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, ++ .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, + }, + + /* +@@ -251,6 +277,12 @@ static const struct sci_port_params sci_ + [SCSPTR] = { 0x20, 16 }, + [SCLSR] = { 0x24, 16 }, + }, ++ .fifosize = 16, ++ .overrun_reg = SCLSR, ++ .overrun_mask = SCLSR_ORER, ++ .sampling_rate_mask = SCI_SR(32), ++ .error_mask = SCIF_DEFAULT_ERROR_MASK, ++ .error_clear = SCIF_ERROR_CLEAR, + }, + + /* +@@ -267,6 +299,12 @@ static const struct sci_port_params sci_ + [SCFCR] = { 0x0c, 8 }, + [SCFDR] = { 0x0e, 16 }, + }, ++ .fifosize = 16, ++ .overrun_reg = SCLSR, ++ .overrun_mask = SCLSR_ORER, ++ .sampling_rate_mask = SCI_SR(32), ++ .error_mask = SCIF_DEFAULT_ERROR_MASK, ++ .error_clear = SCIF_ERROR_CLEAR, + }, + + /* +@@ -285,6 +323,12 @@ static const struct sci_port_params sci_ + [SCSPTR] = { 0x20, 16 }, + [SCLSR] = { 0x24, 16 }, + }, ++ .fifosize = 16, ++ .overrun_reg = SCLSR, ++ .overrun_mask = SCLSR_ORER, ++ .sampling_rate_mask = SCI_SR(32), ++ .error_mask = SCIF_DEFAULT_ERROR_MASK, ++ .error_clear = SCIF_ERROR_CLEAR, + }, + + /* +@@ -306,6 +350,12 @@ static const struct sci_port_params sci_ + [SCDL] = { 0x30, 16 }, + [SCCKS] = { 0x34, 16 }, + }, ++ .fifosize = 16, ++ .overrun_reg = SCLSR, ++ .overrun_mask = SCLSR_ORER, ++ .sampling_rate_mask = SCI_SR(32), ++ .error_mask = SCIF_DEFAULT_ERROR_MASK, ++ .error_clear = SCIF_ERROR_CLEAR, + }, + + /* +@@ -327,6 +377,12 @@ static const struct sci_port_params sci_ + [SCDL] = { 0x30, 16 }, + [SCCKS] = { 0x34, 16 }, + }, ++ .fifosize = 128, ++ .overrun_reg = SCLSR, ++ .overrun_mask = SCLSR_ORER, ++ .sampling_rate_mask = SCI_SR_RANGE(8, 32), ++ .error_mask = SCIF_DEFAULT_ERROR_MASK, ++ .error_clear = SCIF_ERROR_CLEAR, + }, + + /* +@@ -345,6 +401,12 @@ static const struct sci_port_params sci_ + [SCFDR] = { 0x1c, 16 }, + [SCLSR] = { 0x24, 16 }, + }, ++ .fifosize = 16, ++ .overrun_reg = SCLSR, ++ .overrun_mask = SCLSR_ORER, ++ .sampling_rate_mask = SCI_SR(32), ++ .error_mask = SCIF_DEFAULT_ERROR_MASK, ++ .error_clear = SCIF_ERROR_CLEAR, + }, + + /* +@@ -366,6 +428,12 @@ static const struct sci_port_params sci_ + [SCSPTR] = { 0x24, 16 }, + [SCLSR] = { 0x28, 16 }, + }, ++ .fifosize = 16, ++ .overrun_reg = SCLSR, ++ .overrun_mask = SCLSR_ORER, ++ .sampling_rate_mask = SCI_SR(32), ++ .error_mask = SCIF_DEFAULT_ERROR_MASK, ++ .error_clear = SCIF_ERROR_CLEAR, + }, + + /* +@@ -383,6 +451,12 @@ static const struct sci_port_params sci_ + [SCFCR] = { 0x18, 16 }, + [SCFDR] = { 0x1c, 16 }, + }, ++ .fifosize = 16, ++ .overrun_reg = SCxSR, ++ .overrun_mask = SCIFA_ORER, ++ .sampling_rate_mask = SCI_SR(16), ++ .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, ++ .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, + }, + }; + +@@ -545,7 +619,7 @@ static void sci_clear_SCxSR(struct uart_ + if (port->type == PORT_SCI) { + /* Just store the mask */ + serial_port_out(port, SCxSR, mask); +- } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) { ++ } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { + /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ + /* Only clear the status bits we want to clear */ + serial_port_out(port, SCxSR, +@@ -640,11 +714,13 @@ static void sci_init_pins(struct uart_po + + static int sci_txfill(struct uart_port *port) + { ++ struct sci_port *s = to_sci_port(port); ++ unsigned int fifo_mask = (s->params->fifosize << 1) - 1; + const struct plat_sci_reg *reg; + + reg = sci_getreg(port, SCTFDR); + if (reg->size) +- return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1); ++ return serial_port_in(port, SCTFDR) & fifo_mask; + + reg = sci_getreg(port, SCFDR); + if (reg->size) +@@ -660,15 +736,17 @@ static int sci_txroom(struct uart_port * + + static int sci_rxfill(struct uart_port *port) + { ++ struct sci_port *s = to_sci_port(port); ++ unsigned int fifo_mask = (s->params->fifosize << 1) - 1; + const struct plat_sci_reg *reg; + + reg = sci_getreg(port, SCRFDR); + if (reg->size) +- return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1); ++ return serial_port_in(port, SCRFDR) & fifo_mask; + + reg = sci_getreg(port, SCFDR); + if (reg->size) +- return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1); ++ return serial_port_in(port, SCFDR) & fifo_mask; + + return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; + } +@@ -879,7 +957,7 @@ static int sci_handle_errors(struct uart + struct sci_port *s = to_sci_port(port); + + /* Handle overruns */ +- if (status & s->overrun_mask) { ++ if (status & s->params->overrun_mask) { + port->icount.overrun++; + + /* overrun error */ +@@ -945,14 +1023,14 @@ static int sci_handle_fifo_overrun(struc + int copied = 0; + u16 status; + +- reg = sci_getreg(port, s->overrun_reg); ++ reg = sci_getreg(port, s->params->overrun_reg); + if (!reg->size) + return 0; + +- status = serial_port_in(port, s->overrun_reg); +- if (status & s->overrun_mask) { +- status &= ~s->overrun_mask; +- serial_port_out(port, s->overrun_reg, status); ++ status = serial_port_in(port, s->params->overrun_reg); ++ if (status & s->params->overrun_mask) { ++ status &= ~s->params->overrun_mask; ++ serial_port_out(port, s->params->overrun_reg, status); + + port->icount.overrun++; + +@@ -1541,12 +1619,10 @@ static irqreturn_t sci_mpxed_interrupt(i + + ssr_status = serial_port_in(port, SCxSR); + scr_status = serial_port_in(port, SCSCR); +- if (s->overrun_reg == SCxSR) ++ if (s->params->overrun_reg == SCxSR) + orer_status = ssr_status; +- else { +- if (sci_getreg(port, s->overrun_reg)->size) +- orer_status = serial_port_in(port, s->overrun_reg); +- } ++ else if (sci_getreg(port, s->params->overrun_reg)->size) ++ orer_status = serial_port_in(port, s->params->overrun_reg); + + err_enabled = scr_status & port_rx_irq_mask(port); + +@@ -1572,7 +1648,7 @@ static irqreturn_t sci_mpxed_interrupt(i + ret = sci_br_interrupt(irq, ptr); + + /* Overrun Interrupt */ +- if (orer_status & s->overrun_mask) { ++ if (orer_status & s->params->overrun_mask) { + sci_handle_fifo_overrun(port); + ret = IRQ_HANDLED; + } +@@ -2596,51 +2672,13 @@ static int sci_init_single(struct platfo + if (unlikely(sci_port->params == NULL)) + return -EINVAL; + +- switch (p->type) { +- case PORT_SCIFB: +- port->fifosize = 256; +- sci_port->overrun_reg = SCxSR; +- sci_port->overrun_mask = SCIFA_ORER; +- sci_port->sampling_rate_mask = SCI_SR_SCIFAB; +- break; +- case PORT_HSCIF: +- port->fifosize = 128; +- sci_port->overrun_reg = SCLSR; +- sci_port->overrun_mask = SCLSR_ORER; +- sci_port->sampling_rate_mask = SCI_SR_RANGE(8, 32); +- break; +- case PORT_SCIFA: +- port->fifosize = 64; +- sci_port->overrun_reg = SCxSR; +- sci_port->overrun_mask = SCIFA_ORER; +- sci_port->sampling_rate_mask = SCI_SR_SCIFAB; +- break; +- case PORT_SCIF: +- port->fifosize = 16; +- if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) { +- sci_port->overrun_reg = SCxSR; +- sci_port->overrun_mask = SCIFA_ORER; +- sci_port->sampling_rate_mask = SCI_SR(16); +- } else { +- sci_port->overrun_reg = SCLSR; +- sci_port->overrun_mask = SCLSR_ORER; +- sci_port->sampling_rate_mask = SCI_SR(32); +- } +- break; +- default: +- port->fifosize = 1; +- sci_port->overrun_reg = SCxSR; +- sci_port->overrun_mask = SCI_ORER; +- sci_port->sampling_rate_mask = SCI_SR(32); +- break; +- } +- + /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't + * match the SoC datasheet, this should be investigated. Let platform + * data override the sampling rate for now. + */ +- if (p->sampling_rate) +- sci_port->sampling_rate_mask = SCI_SR(p->sampling_rate); ++ sci_port->sampling_rate_mask = p->sampling_rate ++ ? SCI_SR(p->sampling_rate) ++ : sci_port->params->sampling_rate_mask; + + if (!early) { + ret = sci_init_clocks(sci_port, &dev->dev); +@@ -2656,29 +2694,10 @@ static int sci_init_single(struct platfo + sci_port->break_timer.function = sci_break_timer; + init_timer(&sci_port->break_timer); + +- /* +- * Establish some sensible defaults for the error detection. +- */ +- if (p->type == PORT_SCI) { +- sci_port->error_mask = SCI_DEFAULT_ERROR_MASK; +- sci_port->error_clear = SCI_ERROR_CLEAR; +- } else { +- sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK; +- sci_port->error_clear = SCIF_ERROR_CLEAR; +- } +- +- /* +- * Make the error mask inclusive of overrun detection, if +- * supported. +- */ +- if (sci_port->overrun_reg == SCxSR) { +- sci_port->error_mask |= sci_port->overrun_mask; +- sci_port->error_clear &= ~sci_port->overrun_mask; +- } +- + port->type = p->type; + port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; + port->regshift = p->regshift; ++ port->fifosize = sci_port->params->fifosize; + + /* + * The UART port needs an IRQ value, so we peg this to the RX IRQ +--- a/drivers/tty/serial/sh-sci.h ++++ b/drivers/tty/serial/sh-sci.h +@@ -151,12 +151,12 @@ enum { + #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) + #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) + +-#define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask) ++#define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask) + + #define SCxSR_RDxF_CLEAR(port) \ + (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR) + #define SCxSR_ERROR_CLEAR(port) \ +- (to_sci_port(port)->error_clear) ++ (to_sci_port(port)->params->error_clear) + #define SCxSR_TDxE_CLEAR(port) \ + (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR) + #define SCxSR_BREAK_CLEAR(port) \ diff --git a/patches.renesas/0178-serial-sh-sci-Remove-the-platform-data-dma-slave-rx-.patch b/patches.renesas/0178-serial-sh-sci-Remove-the-platform-data-dma-slave-rx-.patch new file mode 100644 index 0000000000000..9c8e72893856f --- /dev/null +++ b/patches.renesas/0178-serial-sh-sci-Remove-the-platform-data-dma-slave-rx-.patch @@ -0,0 +1,93 @@ +From 4bd9f694da5dd3392214353d5d18d2a1b77d383d Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Jan 2017 16:43:37 +0200 +Subject: [PATCH 178/255] serial: sh-sci: Remove the platform data dma slave + rx/tx channel IDs + +Only SH platforms still use platform data for the sh-sci, and none of +them declare DMA channels connected to the SCI. Remove the corresponding +platform data fields and simplify the driver accordingly. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 219fb0c1436e4893a290ba270bc0e644d02465a3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 23 ++++++----------------- + include/linux/serial_sci.h | 3 --- + 2 files changed, 6 insertions(+), 20 deletions(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -1387,20 +1387,14 @@ static void rx_timer_fn(unsigned long ar + } + + static struct dma_chan *sci_request_dma_chan(struct uart_port *port, +- enum dma_transfer_direction dir, +- unsigned int id) ++ enum dma_transfer_direction dir) + { +- dma_cap_mask_t mask; + struct dma_chan *chan; + struct dma_slave_config cfg; + int ret; + +- dma_cap_zero(mask); +- dma_cap_set(DMA_SLAVE, mask); +- +- chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, +- (void *)(unsigned long)id, port->dev, +- dir == DMA_MEM_TO_DEV ? "tx" : "rx"); ++ chan = dma_request_slave_channel(port->dev, ++ dir == DMA_MEM_TO_DEV ? "tx" : "rx"); + if (!chan) { + dev_warn(port->dev, + "dma_request_slave_channel_compat failed\n"); +@@ -1436,12 +1430,11 @@ static void sci_request_dma(struct uart_ + + dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); + +- if (!port->dev->of_node && +- (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)) ++ if (!port->dev->of_node) + return; + + s->cookie_tx = -EINVAL; +- chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx); ++ chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); + dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); + if (chan) { + s->chan_tx = chan; +@@ -1463,7 +1456,7 @@ static void sci_request_dma(struct uart_ + INIT_WORK(&s->work_tx, work_fn_tx); + } + +- chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx); ++ chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); + dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); + if (chan) { + unsigned int i; +@@ -2712,10 +2705,6 @@ static int sci_init_single(struct platfo + port->serial_in = sci_serial_in; + port->serial_out = sci_serial_out; + +- if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) +- dev_dbg(port->dev, "DMA tx %d, rx %d\n", +- p->dma_slave_tx, p->dma_slave_rx); +- + return 0; + } + +--- a/include/linux/serial_sci.h ++++ b/include/linux/serial_sci.h +@@ -71,9 +71,6 @@ struct plat_sci_port { + unsigned char regtype; + + struct plat_sci_port_ops *ops; +- +- unsigned int dma_slave_tx; +- unsigned int dma_slave_rx; + }; + + #endif /* __LINUX_SERIAL_SCI_H */ diff --git a/patches.renesas/0179-Input-touchscreen-drop-unnecessary-calls-to-device_i.patch b/patches.renesas/0179-Input-touchscreen-drop-unnecessary-calls-to-device_i.patch new file mode 100644 index 0000000000000..88c39c484d504 --- /dev/null +++ b/patches.renesas/0179-Input-touchscreen-drop-unnecessary-calls-to-device_i.patch @@ -0,0 +1,78 @@ +From 9f9344aee5ea067658de721eac5be380e4e1e527 Mon Sep 17 00:00:00 2001 +From: Guenter Roeck <linux@roeck-us.net> +Date: Sat, 21 Jan 2017 23:49:13 -0800 +Subject: [PATCH 179/255] Input: touchscreen - drop unnecessary calls to + device_init_wakeup + +Calling device_init_wakeup in the remove function is unnecessary since the +device is going away, and thus won't be able to cause any wakeups under any +circumstances. Besides, the driver cleanup code already handles the +necessary cleanup. + +Similarly, disabling wakeup in the probe error path is unnecessary, as is +disabling wakeup in the probe function in the first place. + +Signed-off-by: Guenter Roeck <linux@roeck-us.net> +Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> +(cherry picked from commit 8e1b4d83cf8b0e62f5a45792d07f027783c1a07c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/input/touchscreen/ads7846.c | 2 -- + drivers/input/touchscreen/bu21013_ts.c | 2 -- + drivers/input/touchscreen/eeti_ts.c | 1 - + drivers/input/touchscreen/lpc32xx_ts.c | 1 - + drivers/input/touchscreen/st1232.c | 1 - + 5 files changed, 7 deletions(-) + +--- a/drivers/input/touchscreen/ads7846.c ++++ b/drivers/input/touchscreen/ads7846.c +@@ -1462,8 +1462,6 @@ static int ads7846_remove(struct spi_dev + { + struct ads7846 *ts = spi_get_drvdata(spi); + +- device_init_wakeup(&spi->dev, false); +- + sysfs_remove_group(&spi->dev.kobj, &ads784x_attr_group); + + ads7846_disable(ts); +--- a/drivers/input/touchscreen/bu21013_ts.c ++++ b/drivers/input/touchscreen/bu21013_ts.c +@@ -637,8 +637,6 @@ static int bu21013_remove(struct i2c_cli + + kfree(bu21013_data); + +- device_init_wakeup(&client->dev, false); +- + return 0; + } + +--- a/drivers/input/touchscreen/eeti_ts.c ++++ b/drivers/input/touchscreen/eeti_ts.c +@@ -232,7 +232,6 @@ static int eeti_ts_probe(struct i2c_clie + */ + eeti_ts_stop(priv); + +- device_init_wakeup(&client->dev, 0); + return 0; + + err3: +--- a/drivers/input/touchscreen/lpc32xx_ts.c ++++ b/drivers/input/touchscreen/lpc32xx_ts.c +@@ -313,7 +313,6 @@ static int lpc32xx_ts_remove(struct plat + struct lpc32xx_tsc *tsc = platform_get_drvdata(pdev); + struct resource *res; + +- device_init_wakeup(&pdev->dev, 0); + free_irq(tsc->irq, tsc); + + input_unregister_device(tsc->dev); +--- a/drivers/input/touchscreen/st1232.c ++++ b/drivers/input/touchscreen/st1232.c +@@ -237,7 +237,6 @@ static int st1232_ts_remove(struct i2c_c + { + struct st1232_ts_data *ts = i2c_get_clientdata(client); + +- device_init_wakeup(&client->dev, 0); + st1232_ts_power(ts, false); + + return 0; diff --git a/patches.renesas/0180-usb-renesas_usbhs-mod_host-fix-typo-connecte-connect.patch b/patches.renesas/0180-usb-renesas_usbhs-mod_host-fix-typo-connecte-connect.patch new file mode 100644 index 0000000000000..6df8136f22e4f --- /dev/null +++ b/patches.renesas/0180-usb-renesas_usbhs-mod_host-fix-typo-connecte-connect.patch @@ -0,0 +1,27 @@ +From c39b17ffe5ced4b91822432703b1805bfb2c0c2b Mon Sep 17 00:00:00 2001 +From: Colin Ian King <colin.king@canonical.com> +Date: Wed, 28 Dec 2016 16:52:41 +0000 +Subject: [PATCH 180/255] usb: renesas_usbhs: mod_host: fix typo: "connecte" -> + "connected" + +trivial fix to typo in dev_dbg message + +Signed-off-by: Colin Ian King <colin.king@canonical.com> +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +(cherry picked from commit ff86110e26c53634fc6c413732f68a6489ea40b2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/renesas_usbhs/mod_host.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/usb/renesas_usbhs/mod_host.c ++++ b/drivers/usb/renesas_usbhs/mod_host.c +@@ -577,7 +577,7 @@ static struct usbhsh_device *usbhsh_devi + upphub = usbhsh_device_number(hpriv, parent); + hubport = usbhsh_device_hubport(udev); + +- dev_dbg(dev, "%s connecte to Hub [%d:%d](%p)\n", __func__, ++ dev_dbg(dev, "%s connected to Hub [%d:%d](%p)\n", __func__, + upphub, hubport, parent); + } + diff --git a/patches.renesas/0181-usb-renesas_usbhs-Replace-the-deprecated-extcon-API.patch b/patches.renesas/0181-usb-renesas_usbhs-Replace-the-deprecated-extcon-API.patch new file mode 100644 index 0000000000000..175fb2d02cfd4 --- /dev/null +++ b/patches.renesas/0181-usb-renesas_usbhs-Replace-the-deprecated-extcon-API.patch @@ -0,0 +1,29 @@ +From 5be741c4435d1e87f76b4cff63cc60a67aed6b5f Mon Sep 17 00:00:00 2001 +From: Chanwoo Choi <cw00.choi@samsung.com> +Date: Mon, 16 Jan 2017 21:37:02 +0900 +Subject: [PATCH 181/255] usb: renesas_usbhs: Replace the deprecated extcon API + +This patch replaces the deprecated extcon API as following: +- extcon_get_cable_state_() -> extcon_get_state() + +Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> +Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +(cherry picked from commit ea07b8cf08f71fe5fb49c02b4a29b92a6b357218) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/renesas_usbhs/common.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/usb/renesas_usbhs/common.c ++++ b/drivers/usb/renesas_usbhs/common.c +@@ -389,7 +389,7 @@ static void usbhsc_hotplug(struct usbhs_ + + if (enable && !mod) { + if (priv->edev) { +- cable = extcon_get_cable_state_(priv->edev, EXTCON_USB_HOST); ++ cable = extcon_get_state(priv->edev, EXTCON_USB_HOST); + if ((cable > 0 && id != USBHS_HOST) || + (!cable && id != USBHS_GADGET)) { + dev_info(&pdev->dev, diff --git a/patches.renesas/0182-xhci-simplify-if-statement-to-make-it-more-readable.patch b/patches.renesas/0182-xhci-simplify-if-statement-to-make-it-more-readable.patch new file mode 100644 index 0000000000000..7dcdeee6d5f82 --- /dev/null +++ b/patches.renesas/0182-xhci-simplify-if-statement-to-make-it-more-readable.patch @@ -0,0 +1,27 @@ +From 34b1ba6ee45abbfa5e20955806ba46d3cd3bd665 Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Mon, 23 Jan 2017 14:19:51 +0200 +Subject: [PATCH 182/255] xhci: simplify if statement to make it more readable + +No functional change, De Morgan !(A && B) = (!A || !B) + +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 505f581c48bc27cd72beb42df47b3012b617ea5c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -916,7 +916,8 @@ void xhci_stop_endpoint_command_watchdog + spin_lock_irqsave(&xhci->lock, flags); + + ep->stop_cmds_pending--; +- if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { ++ ++ if (ep->stop_cmds_pending || !(ep->ep_state & EP_HALT_PENDING)) { + xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, + "Stop EP timer ran, but no command pending, " + "exiting."); diff --git a/patches.renesas/0183-xhci-rename-EP_HALT_PENDING-to-EP_STOP_CMD_PENDING.patch b/patches.renesas/0183-xhci-rename-EP_HALT_PENDING-to-EP_STOP_CMD_PENDING.patch new file mode 100644 index 0000000000000..ab21ccb683e9b --- /dev/null +++ b/patches.renesas/0183-xhci-rename-EP_HALT_PENDING-to-EP_STOP_CMD_PENDING.patch @@ -0,0 +1,86 @@ +From a337e153766013c465bd074ebe8248c9c7cf3205 Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Mon, 23 Jan 2017 14:19:52 +0200 +Subject: [PATCH 183/255] xhci: rename EP_HALT_PENDING to EP_STOP_CMD_PENDING + +We don't want to confuse halted and stalled endpoint states with +a flag indicating we are waiting for a stop endpoint command to +finish or timeout + +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 9983a5fc39bfce7581db49f884aa782f24149d93) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 6 +++--- + drivers/usb/host/xhci.c | 6 +++--- + drivers/usb/host/xhci.h | 2 +- + 3 files changed, 7 insertions(+), 7 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -410,7 +410,7 @@ void xhci_ring_ep_doorbell(struct xhci_h + * pointer command pending because the device can choose to start any + * stream once the endpoint is on the HW schedule. + */ +- if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || ++ if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) || + (ep_state & EP_HALTED)) + return; + writel(DB_VALUE(ep_index, stream_id), db_addr); +@@ -626,7 +626,7 @@ static void td_to_noop(struct xhci_hcd * + static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, + struct xhci_virt_ep *ep) + { +- ep->ep_state &= ~EP_HALT_PENDING; ++ ep->ep_state &= ~EP_STOP_CMD_PENDING; + /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the + * timer is running on another CPU, we don't decrement stop_cmds_pending + * (since we didn't successfully stop the watchdog timer). +@@ -917,7 +917,7 @@ void xhci_stop_endpoint_command_watchdog + + ep->stop_cmds_pending--; + +- if (ep->stop_cmds_pending || !(ep->ep_state & EP_HALT_PENDING)) { ++ if (ep->stop_cmds_pending || !(ep->ep_state & EP_STOP_CMD_PENDING)) { + xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, + "Stop EP timer ran, but no command pending, " + "exiting."); +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1569,13 +1569,13 @@ int xhci_urb_dequeue(struct usb_hcd *hcd + /* Queue a stop endpoint command, but only if this is + * the first cancellation to be handled. + */ +- if (!(ep->ep_state & EP_HALT_PENDING)) { ++ if (!(ep->ep_state & EP_STOP_CMD_PENDING)) { + command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); + if (!command) { + ret = -ENOMEM; + goto done; + } +- ep->ep_state |= EP_HALT_PENDING; ++ ep->ep_state |= EP_STOP_CMD_PENDING; + ep->stop_cmds_pending++; + ep->stop_cmd_timer.expires = jiffies + + XHCI_STOP_EP_CMD_TIMEOUT * HZ; +@@ -3616,7 +3616,7 @@ void xhci_free_dev(struct usb_hcd *hcd, + + /* Stop any wayward timer functions (which may grab the lock) */ + for (i = 0; i < 31; ++i) { +- virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING; ++ virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING; + del_timer_sync(&virt_dev->eps[i].stop_cmd_timer); + } + +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -912,7 +912,7 @@ struct xhci_virt_ep { + unsigned int ep_state; + #define SET_DEQ_PENDING (1 << 0) + #define EP_HALTED (1 << 1) /* For stall handling */ +-#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ ++#define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ + /* Transitioning the endpoint to using streams, don't enqueue URBs */ + #define EP_GETTING_STREAMS (1 << 3) + #define EP_HAS_STREAMS (1 << 4) diff --git a/patches.renesas/0184-xhci-detect-stop-endpoint-race-using-pending-timer-i.patch b/patches.renesas/0184-xhci-detect-stop-endpoint-race-using-pending-timer-i.patch new file mode 100644 index 0000000000000..fa2d1c38e706e --- /dev/null +++ b/patches.renesas/0184-xhci-detect-stop-endpoint-race-using-pending-timer-i.patch @@ -0,0 +1,107 @@ +From de192b04234084684aa1a7c8b75634798f97fa0b Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Mon, 23 Jan 2017 14:19:53 +0200 +Subject: [PATCH 184/255] xhci: detect stop endpoint race using pending timer + instead of counter. + +A counter was used to find out if the stop endpoint completion raced with +the stop endpoint timeout timer. This was needed in case the stop ep +completion failed to delete the timer as it was running on anoter cpu. + +The EP_STOP_CMD_PENDING flag was not enough as a new stop endpoint command +may be queued between the command completion and timeout function, which +would set the flag back. + +Instead of the separate counter that was used we can detect the race by +checking both the STOP_EP_PENDING flag and timer_pending in the timeout +function. + +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit f99265965b3203baf5266994578db14851fbf7fa) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 27 +++++++++++---------------- + drivers/usb/host/xhci.c | 1 - + drivers/usb/host/xhci.h | 1 - + 3 files changed, 11 insertions(+), 18 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -627,12 +627,8 @@ static void xhci_stop_watchdog_timer_in_ + struct xhci_virt_ep *ep) + { + ep->ep_state &= ~EP_STOP_CMD_PENDING; +- /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the +- * timer is running on another CPU, we don't decrement stop_cmds_pending +- * (since we didn't successfully stop the watchdog timer). +- */ +- if (del_timer(&ep->stop_cmd_timer)) +- ep->stop_cmds_pending--; ++ /* Can't del_timer_sync in interrupt */ ++ del_timer(&ep->stop_cmd_timer); + } + + /* +@@ -898,10 +894,8 @@ static void xhci_kill_endpoint_urbs(stru + * simple flag to say whether there is a pending stop endpoint command for a + * particular endpoint. + * +- * Instead we use a combination of that flag and a counter for the number of +- * pending stop endpoint commands. If the timer is the tail end of the last +- * stop endpoint command, and the endpoint's command is still pending, we assume +- * the host is dying. ++ * Instead we use a combination of that flag and checking if a new timer is ++ * pending. + */ + void xhci_stop_endpoint_command_watchdog(unsigned long arg) + { +@@ -915,13 +909,11 @@ void xhci_stop_endpoint_command_watchdog + + spin_lock_irqsave(&xhci->lock, flags); + +- ep->stop_cmds_pending--; +- +- if (ep->stop_cmds_pending || !(ep->ep_state & EP_STOP_CMD_PENDING)) { +- xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, +- "Stop EP timer ran, but no command pending, " +- "exiting."); ++ /* bail out if cmd completed but raced with stop ep watchdog timer.*/ ++ if (!(ep->ep_state & EP_STOP_CMD_PENDING) || ++ timer_pending(&ep->stop_cmd_timer)) { + spin_unlock_irqrestore(&xhci->lock, flags); ++ xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit"); + return; + } + +@@ -930,7 +922,10 @@ void xhci_stop_endpoint_command_watchdog + /* Oops, HC is dead or dying or at least not responding to the stop + * endpoint command. + */ ++ + xhci->xhc_state |= XHCI_STATE_DYING; ++ ep->ep_state &= ~EP_STOP_CMD_PENDING; ++ + /* Disable interrupts from the host controller and start halting it */ + xhci_quiesce(xhci); + spin_unlock_irqrestore(&xhci->lock, flags); +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1576,7 +1576,6 @@ int xhci_urb_dequeue(struct usb_hcd *hcd + goto done; + } + ep->ep_state |= EP_STOP_CMD_PENDING; +- ep->stop_cmds_pending++; + ep->stop_cmd_timer.expires = jiffies + + XHCI_STOP_EP_CMD_TIMEOUT * HZ; + add_timer(&ep->stop_cmd_timer); +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -924,7 +924,6 @@ struct xhci_virt_ep { + unsigned int stopped_stream; + /* Watchdog timer for stop endpoint command to cancel URBs */ + struct timer_list stop_cmd_timer; +- int stop_cmds_pending; + struct xhci_hcd *xhci; + /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue + * command. We'll need to update the ring's dequeue segment and dequeue diff --git a/patches.renesas/0185-xhci-remove-unnecessary-check-for-pending-timer.patch b/patches.renesas/0185-xhci-remove-unnecessary-check-for-pending-timer.patch new file mode 100644 index 0000000000000..512094215f5b0 --- /dev/null +++ b/patches.renesas/0185-xhci-remove-unnecessary-check-for-pending-timer.patch @@ -0,0 +1,29 @@ +From b3432704da4772bf53505619cd98132893d3ec5d Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Mon, 23 Jan 2017 14:19:54 +0200 +Subject: [PATCH 185/255] xhci: remove unnecessary check for pending timer + +Checking if the command timeout timer is pending when queueing the +first command to the command ring is not really useful, remove it. + +Suggested-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 6b02e97491c9b4ef54a3b2295f2962b2ceeb25f8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -3818,8 +3818,7 @@ static int queue_command(struct xhci_hcd + list_add_tail(&cmd->cmd_list, &xhci->cmd_list); + + /* if there are no other commands queued we start the timeout timer */ +- if (xhci->cmd_list.next == &cmd->cmd_list && +- !delayed_work_pending(&xhci->cmd_timer)) { ++ if (xhci->cmd_list.next == &cmd->cmd_list) { + xhci->current_cmd = cmd; + xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); + } diff --git a/patches.renesas/0186-usb-xhci-remove-unnecessary-second-abort-try.patch b/patches.renesas/0186-usb-xhci-remove-unnecessary-second-abort-try.patch new file mode 100644 index 0000000000000..f33dfbdb05bf0 --- /dev/null +++ b/patches.renesas/0186-usb-xhci-remove-unnecessary-second-abort-try.patch @@ -0,0 +1,47 @@ +From dbca0492e7c02adc4a6569f705d1102e9573b5ec Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Mon, 23 Jan 2017 14:19:55 +0200 +Subject: [PATCH 186/255] usb: xhci: remove unnecessary second abort try + +The second try was a workaround for (what we thought was) command +ring failing to stop in the first place. But this turns out to be +due to the race that we have fixed(see "xhci: Fix race related to +abort operation"). With that fix, it is time to remove the second +try. + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 1cc6d8617b9107f22ab86cec168f7f53f5ef42be) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 18 +++++------------- + 1 file changed, 5 insertions(+), 13 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -362,19 +362,11 @@ static int xhci_abort_cmd_ring(struct xh + ret = xhci_handshake(&xhci->op_regs->cmd_ring, + CMD_RING_RUNNING, 0, 5 * 1000 * 1000); + if (ret < 0) { +- /* we are about to kill xhci, give it one more chance */ +- xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, +- &xhci->op_regs->cmd_ring); +- udelay(1000); +- ret = xhci_handshake(&xhci->op_regs->cmd_ring, +- CMD_RING_RUNNING, 0, 3 * 1000 * 1000); +- if (ret < 0) { +- xhci_err(xhci, "Stopped the command ring failed, " +- "maybe the host is dead\n"); +- xhci->xhc_state |= XHCI_STATE_DYING; +- xhci_halt(xhci); +- return -ESHUTDOWN; +- } ++ xhci_err(xhci, ++ "Stop command ring failed, maybe the host is dead\n"); ++ xhci->xhc_state |= XHCI_STATE_DYING; ++ xhci_halt(xhci); ++ return -ESHUTDOWN; + } + /* + * Writing the CMD_RING_ABORT bit should cause a cmd completion event, diff --git a/patches.renesas/0187-usb-host-xhci-Remove-unused-addr_64-variable-in-xhci.patch b/patches.renesas/0187-usb-host-xhci-Remove-unused-addr_64-variable-in-xhci.patch new file mode 100644 index 0000000000000..ef1b3466a1827 --- /dev/null +++ b/patches.renesas/0187-usb-host-xhci-Remove-unused-addr_64-variable-in-xhci.patch @@ -0,0 +1,28 @@ +From fd4df1a30954a108d74cfc8d72887e11844c62d2 Mon Sep 17 00:00:00 2001 +From: Baolin Wang <baolin.wang@linaro.org> +Date: Mon, 23 Jan 2017 14:19:56 +0200 +Subject: [PATCH 187/255] usb: host: xhci: Remove unused 'addr_64' variable in + xhci_hcd structure + +Since the 'addr_64' variable as legacy is unused now, then remove it from +xhci_hcd structure. + +Signed-off-by: Baolin Wang <baolin.wang@linaro.org> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit e22caf8bc140d8efa52922040c173c0b84647b66) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.h | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1548,7 +1548,6 @@ struct xhci_hcd { + u8 max_ports; + u8 isoc_threshold; + int event_ring_max; +- int addr_64; + /* 4KB min, 128MB max */ + int page_size; + /* Valid values are 12 to 20, inclusive */ diff --git a/patches.renesas/0188-xhci-Put-warning-message-on-a-single-line.patch b/patches.renesas/0188-xhci-Put-warning-message-on-a-single-line.patch new file mode 100644 index 0000000000000..e13c9ed8b5ed7 --- /dev/null +++ b/patches.renesas/0188-xhci-Put-warning-message-on-a-single-line.patch @@ -0,0 +1,29 @@ +From b0ccb2708be76445939d207c3ae108d3d60a42fc Mon Sep 17 00:00:00 2001 +From: Alexander Stein <alexander.stein@systec-electronic.com> +Date: Mon, 23 Jan 2017 14:19:57 +0200 +Subject: [PATCH 188/255] xhci: Put warning message on a single line + +This allows someone to grep for the complete warning message as in; +xhci-hcd xhci-hcd.0.auto: USB core suspending device not in U0/U1/U2. + +Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 52c31bd5294d838315ea0211a991cfcd60b625ff) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-hub.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/usb/host/xhci-hub.c ++++ b/drivers/usb/host/xhci-hub.c +@@ -999,8 +999,7 @@ int xhci_hub_control(struct usb_hcd *hcd + temp = readl(port_array[wIndex]); + if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) + || (temp & PORT_PLS_MASK) >= XDEV_U3) { +- xhci_warn(xhci, "USB core suspending device " +- "not in U0/U1/U2.\n"); ++ xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n"); + goto error; + } + diff --git a/patches.renesas/0189-usb-xhci-remove-unnecessary-assignment.patch b/patches.renesas/0189-usb-xhci-remove-unnecessary-assignment.patch new file mode 100644 index 0000000000000..096b1367ed249 --- /dev/null +++ b/patches.renesas/0189-usb-xhci-remove-unnecessary-assignment.patch @@ -0,0 +1,27 @@ +From 5f5161919cfbf2bc1fca90025eb20a5b4a87bd7b Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:00 +0200 +Subject: [PATCH 189/255] usb: xhci: remove unnecessary assignment + +Drop an unnecessary assignment in prepare_transfer(). + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 80c479622fb4564c40813c8f752d3fffd4c5be47) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -2847,8 +2847,6 @@ static int prepare_transfer(struct xhci_ + td->start_seg = ep_ring->enq_seg; + td->first_trb = ep_ring->enqueue; + +- urb_priv->td[td_index] = td; +- + return 0; + } + diff --git a/patches.renesas/0190-usb-xhci-avoid-unnecessary-calculation.patch b/patches.renesas/0190-usb-xhci-avoid-unnecessary-calculation.patch new file mode 100644 index 0000000000000..8a41754c1390a --- /dev/null +++ b/patches.renesas/0190-usb-xhci-avoid-unnecessary-calculation.patch @@ -0,0 +1,54 @@ +From 8c6ebb3a7bdd1298f47e6583899fbe66c537bf7c Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:01 +0200 +Subject: [PATCH 190/255] usb: xhci: avoid unnecessary calculation + +No need to calculate remainder and length_field, if there is +no data phase of a control transfer. + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit fb79a6da459b20554151eed84c991cd9bd35ff15) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -3240,7 +3240,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd * + struct usb_ctrlrequest *setup; + struct xhci_generic_trb *start_trb; + int start_cycle; +- u32 field, length_field, remainder; ++ u32 field; + struct urb_priv *urb_priv; + struct xhci_td *td; + +@@ -3313,16 +3313,16 @@ int xhci_queue_ctrl_tx(struct xhci_hcd * + else + field = TRB_TYPE(TRB_DATA); + +- remainder = xhci_td_remainder(xhci, 0, +- urb->transfer_buffer_length, +- urb->transfer_buffer_length, +- urb, 1); +- +- length_field = TRB_LEN(urb->transfer_buffer_length) | +- TRB_TD_SIZE(remainder) | +- TRB_INTR_TARGET(0); +- + if (urb->transfer_buffer_length > 0) { ++ u32 length_field, remainder; ++ ++ remainder = xhci_td_remainder(xhci, 0, ++ urb->transfer_buffer_length, ++ urb->transfer_buffer_length, ++ urb, 1); ++ length_field = TRB_LEN(urb->transfer_buffer_length) | ++ TRB_TD_SIZE(remainder) | ++ TRB_INTR_TARGET(0); + if (setup->bRequestType & USB_DIR_IN) + field |= TRB_DIR_IN; + queue_trb(xhci, ep_ring, true, diff --git a/patches.renesas/0191-usb-xhci-use-list_is_singular-for-cmd_list.patch b/patches.renesas/0191-usb-xhci-use-list_is_singular-for-cmd_list.patch new file mode 100644 index 0000000000000..0c15857eb3f7a --- /dev/null +++ b/patches.renesas/0191-usb-xhci-use-list_is_singular-for-cmd_list.patch @@ -0,0 +1,47 @@ +From 103b843025dddaf40557b50aa0c4163311765e39 Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:02 +0200 +Subject: [PATCH 191/255] usb: xhci: use list_is_singular for cmd_list + +Use list_is_singular() to check if cmd_list has only one entry. + +[use list_empty() in queue command instead -Mathias] +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> + +(cherry picked from commit daa47f2132dce31fcab7c6ebdcb957e598c768f2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -1428,7 +1428,7 @@ static void handle_cmd_completion(struct + } + + /* restart timer if this wasn't the last command */ +- if (cmd->cmd_list.next != &xhci->cmd_list) { ++ if (!list_is_singular(&xhci->cmd_list)) { + xhci->current_cmd = list_entry(cmd->cmd_list.next, + struct xhci_command, cmd_list); + xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); +@@ -3805,14 +3805,15 @@ static int queue_command(struct xhci_hcd + } + + cmd->command_trb = xhci->cmd_ring->enqueue; +- list_add_tail(&cmd->cmd_list, &xhci->cmd_list); + + /* if there are no other commands queued we start the timeout timer */ +- if (xhci->cmd_list.next == &cmd->cmd_list) { ++ if (list_empty(&xhci->cmd_list)) { + xhci->current_cmd = cmd; + xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); + } + ++ list_add_tail(&cmd->cmd_list, &xhci->cmd_list); ++ + queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, + field4 | xhci->cmd_ring->cycle_state); + return 0; diff --git a/patches.renesas/0192-usb-host-xhci-change-pre-increments-to-post-incremen.patch b/patches.renesas/0192-usb-host-xhci-change-pre-increments-to-post-incremen.patch new file mode 100644 index 0000000000000..9274257eb776e --- /dev/null +++ b/patches.renesas/0192-usb-host-xhci-change-pre-increments-to-post-incremen.patch @@ -0,0 +1,209 @@ +From 23f411e31f7d6c1a35a4be0d07e7545fa7e8fdec Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:04 +0200 +Subject: [PATCH 192/255] usb: host: xhci: change pre-increments to + post-increments + +This is a cleanup patch only, no functional changes. The idea is just to +make sure for loops look the same all over the driver. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 98871e9470a50c8c0154b7220495b60ec055e02f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-dbg.c | 20 ++++++++++---------- + drivers/usb/host/xhci-mem.c | 8 ++++---- + drivers/usb/host/xhci.c | 14 +++++++------- + 3 files changed, 21 insertions(+), 21 deletions(-) + +--- a/drivers/usb/host/xhci-dbg.c ++++ b/drivers/usb/host/xhci-dbg.c +@@ -177,7 +177,7 @@ static void xhci_print_ports(struct xhci + ports = HCS_MAX_PORTS(xhci->hcs_params1); + addr = &xhci->op_regs->port_status_base; + for (i = 0; i < ports; i++) { +- for (j = 0; j < NUM_PORT_REGS; ++j) { ++ for (j = 0; j < NUM_PORT_REGS; j++) { + xhci_dbg(xhci, "%p port %s reg = 0x%x\n", + addr, names[j], + (unsigned int) readl(addr)); +@@ -240,7 +240,7 @@ void xhci_print_run_regs(struct xhci_hcd + xhci_dbg(xhci, " %p: Microframe index = 0x%x\n", + &xhci->run_regs->microframe_index, + (unsigned int) temp); +- for (i = 0; i < 7; ++i) { ++ for (i = 0; i < 7; i++) { + temp = readl(&xhci->run_regs->rsvd[i]); + if (temp != XHCI_INIT_VALUE) + xhci_dbg(xhci, " WARN: %p: Rsvd[%i] = 0x%x\n", +@@ -259,7 +259,7 @@ void xhci_print_registers(struct xhci_hc + void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb) + { + int i; +- for (i = 0; i < 4; ++i) ++ for (i = 0; i < 4; i++) + xhci_dbg(xhci, "Offset 0x%x = 0x%x\n", + i*4, trb->generic.field[i]); + } +@@ -332,7 +332,7 @@ void xhci_debug_segment(struct xhci_hcd + u64 addr = seg->dma; + union xhci_trb *trb = seg->trbs; + +- for (i = 0; i < TRBS_PER_SEGMENT; ++i) { ++ for (i = 0; i < TRBS_PER_SEGMENT; i++) { + trb = &seg->trbs[i]; + xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", addr, + lower_32_bits(le64_to_cpu(trb->link.segment_ptr)), +@@ -413,7 +413,7 @@ void xhci_dbg_erst(struct xhci_hcd *xhci + int i; + struct xhci_erst_entry *entry; + +- for (i = 0; i < erst->num_entries; ++i) { ++ for (i = 0; i < erst->num_entries; i++) { + entry = &erst->entries[i]; + xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", + addr, +@@ -440,7 +440,7 @@ void xhci_dbg_cmd_ptrs(struct xhci_hcd * + static void dbg_rsvd64(struct xhci_hcd *xhci, u64 *ctx, dma_addr_t dma) + { + int i; +- for (i = 0; i < 4; ++i) { ++ for (i = 0; i < 4; i++) { + xhci_dbg(xhci, "@%p (virt) @%08llx " + "(dma) %#08llx - rsvd64[%d]\n", + &ctx[4 + i], (unsigned long long)dma, +@@ -496,7 +496,7 @@ static void xhci_dbg_slot_ctx(struct xhc + &slot_ctx->dev_state, + (unsigned long long)dma, slot_ctx->dev_state); + dma += field_size; +- for (i = 0; i < 4; ++i) { ++ for (i = 0; i < 4; i++) { + xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n", + &slot_ctx->reserved[i], (unsigned long long)dma, + slot_ctx->reserved[i], i); +@@ -519,7 +519,7 @@ static void xhci_dbg_ep_ctx(struct xhci_ + + if (last_ep < 31) + last_ep_ctx = last_ep + 1; +- for (i = 0; i < last_ep_ctx; ++i) { ++ for (i = 0; i < last_ep_ctx; i++) { + unsigned int epaddr = xhci_get_endpoint_address(i); + struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i); + dma_addr_t dma = ctx->dma + +@@ -544,7 +544,7 @@ static void xhci_dbg_ep_ctx(struct xhci_ + &ep_ctx->tx_info, + (unsigned long long)dma, ep_ctx->tx_info); + dma += field_size; +- for (j = 0; j < 3; ++j) { ++ for (j = 0; j < 3; j++) { + xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n", + &ep_ctx->reserved[j], + (unsigned long long)dma, +@@ -583,7 +583,7 @@ void xhci_dbg_ctx(struct xhci_hcd *xhci, + &ctrl_ctx->add_flags, (unsigned long long)dma, + ctrl_ctx->add_flags); + dma += field_size; +- for (i = 0; i < 6; ++i) { ++ for (i = 0; i < 6; i++) { + xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n", + &ctrl_ctx->rsvd2[i], (unsigned long long)dma, + ctrl_ctx->rsvd2[i], i); +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -943,7 +943,7 @@ void xhci_free_virt_device(struct xhci_h + if (dev->tt_info) + old_active_eps = dev->tt_info->active_eps; + +- for (i = 0; i < 31; ++i) { ++ for (i = 0; i < 31; i++) { + if (dev->eps[i].ring) + xhci_ring_free(xhci, dev->eps[i].ring); + if (dev->eps[i].stream_info) +@@ -1598,7 +1598,7 @@ void xhci_update_bw_info(struct xhci_hcd + unsigned int ep_type; + int i; + +- for (i = 1; i < 31; ++i) { ++ for (i = 1; i < 31; i++) { + bw_info = &virt_dev->eps[i].bw_info; + + /* We can't tell what endpoint type is being dropped, but +@@ -2583,9 +2583,9 @@ int xhci_mem_init(struct xhci_hcd *xhci, + * something other than the default (~1ms minimum between interrupts). + * See section 5.5.1.2. + */ +- for (i = 0; i < MAX_HC_SLOTS; ++i) ++ for (i = 0; i < MAX_HC_SLOTS; i++) + xhci->devs[i] = NULL; +- for (i = 0; i < USB_MAXCHILDREN; ++i) { ++ for (i = 0; i < USB_MAXCHILDREN; i++) { + xhci->bus_state[0].resume_done[i] = 0; + xhci->bus_state[1].resume_done[i] = 0; + /* Only the USB 2.0 completions will ever be used. */ +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -210,7 +210,7 @@ int xhci_reset(struct xhci_hcd *xhci) + ret = xhci_handshake(&xhci->op_regs->status, + STS_CNR, 0, 10 * 1000 * 1000); + +- for (i = 0; i < 2; ++i) { ++ for (i = 0; i < 2; i++) { + xhci->bus_state[i].port_c_suspend = 0; + xhci->bus_state[i].suspended_ports = 0; + xhci->bus_state[i].resuming_ports = 0; +@@ -1814,7 +1814,7 @@ static void xhci_zero_in_ctx(struct xhci + slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); + /* Endpoint 0 is always valid */ + slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); +- for (i = 1; i < 31; ++i) { ++ for (i = 1; i < 31; i++) { + ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i); + ep_ctx->ep_info = 0; + ep_ctx->ep_info2 = 0; +@@ -2786,7 +2786,7 @@ int xhci_check_bandwidth(struct usb_hcd + LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); + + /* Free any rings that were dropped, but not changed. */ +- for (i = 1; i < 31; ++i) { ++ for (i = 1; i < 31; i++) { + if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) && + !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) { + xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); +@@ -2798,7 +2798,7 @@ int xhci_check_bandwidth(struct usb_hcd + * Install any rings for completely new endpoints or changed endpoints, + * and free or cache any old rings from changed endpoints. + */ +- for (i = 1; i < 31; ++i) { ++ for (i = 1; i < 31; i++) { + if (!virt_dev->eps[i].new_ring) + continue; + /* Only cache or free the old ring if it exists. +@@ -2832,7 +2832,7 @@ void xhci_reset_bandwidth(struct usb_hcd + xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); + virt_dev = xhci->devs[udev->slot_id]; + /* Free any rings allocated for added endpoints */ +- for (i = 0; i < 31; ++i) { ++ for (i = 0; i < 31; i++) { + if (virt_dev->eps[i].new_ring) { + xhci_ring_free(xhci, virt_dev->eps[i].new_ring); + virt_dev->eps[i].new_ring = NULL; +@@ -3538,7 +3538,7 @@ int xhci_discover_or_reset_device(struct + + /* Everything but endpoint 0 is disabled, so free or cache the rings. */ + last_freed_endpoint = 1; +- for (i = 1; i < 31; ++i) { ++ for (i = 1; i < 31; i++) { + struct xhci_virt_ep *ep = &virt_dev->eps[i]; + + if (ep->ep_state & EP_HAS_STREAMS) { +@@ -3614,7 +3614,7 @@ void xhci_free_dev(struct usb_hcd *hcd, + virt_dev = xhci->devs[udev->slot_id]; + + /* Stop any wayward timer functions (which may grab the lock) */ +- for (i = 0; i < 31; ++i) { ++ for (i = 0; i < 31; i++) { + virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING; + del_timer_sync(&virt_dev->eps[i].stop_cmd_timer); + } diff --git a/patches.renesas/0193-usb-host-xhci-print-HCIVERSION-on-debug.patch b/patches.renesas/0193-usb-host-xhci-print-HCIVERSION-on-debug.patch new file mode 100644 index 0000000000000..752b2ea1d01a7 --- /dev/null +++ b/patches.renesas/0193-usb-host-xhci-print-HCIVERSION-on-debug.patch @@ -0,0 +1,31 @@ +From 0c318f2a25f85db18c6febf5b722732bc0c8ff5f Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:05 +0200 +Subject: [PATCH 193/255] usb: host: xhci: print HCIVERSION on debug + +When calling xhci_dbg_regs() we actually _do_ want to know XHCI's +version. This might help figure out why certain problems only happen +in some cases. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit ced09c95963795374c7f8710eeabca1d734315e2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-dbg.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/usb/host/xhci-dbg.c ++++ b/drivers/usb/host/xhci-dbg.c +@@ -37,10 +37,8 @@ void xhci_dbg_regs(struct xhci_hcd *xhci + &xhci->cap_regs->hc_capbase, temp); + xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n", + (unsigned int) HC_LENGTH(temp)); +-#if 0 + xhci_dbg(xhci, "// HCIVERSION: 0x%x\n", + (unsigned int) HC_VERSION(temp)); +-#endif + + xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs); + diff --git a/patches.renesas/0194-usb-host-xhci-rename-completion-codes-to-match-spec.patch b/patches.renesas/0194-usb-host-xhci-rename-completion-codes-to-match-spec.patch new file mode 100644 index 0000000000000..074c05d31af36 --- /dev/null +++ b/patches.renesas/0194-usb-host-xhci-rename-completion-codes-to-match-spec.patch @@ -0,0 +1,645 @@ +From f7ddfde30b9abf4c11431393a9d13eae3a3c8a7c Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:06 +0200 +Subject: [PATCH 194/255] usb: host: xhci: rename completion codes to match + spec + +Cleanup only. This patch is a mechaninal rename to make sure our macros +for TRB completion codes match what the specification uses to refer to +such errors. The idea behind this is that it makes it far easier to grep +the specification and match it with implementation. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 0b7c105a04ca793acf5d39ff9bafebe89182fc6b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-hub.c | 3 - + drivers/usb/host/xhci-ring.c | 124 +++++++++++++++++++++---------------------- + drivers/usb/host/xhci.c | 48 ++++++++-------- + drivers/usb/host/xhci.h | 106 ++++++++++++------------------------ + 4 files changed, 124 insertions(+), 157 deletions(-) + +--- a/drivers/usb/host/xhci-hub.c ++++ b/drivers/usb/host/xhci-hub.c +@@ -418,7 +418,8 @@ static int xhci_stop_device(struct xhci_ + /* Wait for last stop endpoint command to finish */ + wait_for_completion(cmd->completion); + +- if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) { ++ if (cmd->status == COMP_COMMAND_ABORTED || ++ cmd->status == COMP_STOPPED) { + xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); + ret = -ETIME; + } +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -304,10 +304,10 @@ static void xhci_handle_stopped_cmd_ring + /* Turn all aborted commands in list to no-ops, then restart */ + list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { + +- if (i_cmd->status != COMP_CMD_ABORT) ++ if (i_cmd->status != COMP_COMMAND_ABORTED) + continue; + +- i_cmd->status = COMP_CMD_STOP; ++ i_cmd->status = COMP_STOPPED; + + xhci_dbg(xhci, "Turn aborted command %p to no-op\n", + i_cmd->command_trb); +@@ -1041,10 +1041,10 @@ static void xhci_handle_cmd_set_deq(stru + unsigned int slot_state; + + switch (cmd_comp_code) { +- case COMP_TRB_ERR: ++ case COMP_TRB_ERROR: + xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); + break; +- case COMP_CTX_STATE: ++ case COMP_CONTEXT_STATE_ERROR: + xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); + ep_state = GET_EP_CTX_STATE(ep_ctx); + slot_state = le32_to_cpu(slot_ctx->dev_state); +@@ -1053,7 +1053,7 @@ static void xhci_handle_cmd_set_deq(stru + "Slot state = %u, EP state = %u", + slot_state, ep_state); + break; +- case COMP_EBADSLT: ++ case COMP_SLOT_NOT_ENABLED_ERROR: + xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", + slot_id); + break; +@@ -1250,7 +1250,7 @@ void xhci_cleanup_command_queue(struct x + { + struct xhci_command *cur_cmd, *tmp_cmd; + list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) +- xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT); ++ xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED); + } + + void xhci_handle_command_timeout(struct work_struct *work) +@@ -1273,7 +1273,7 @@ void xhci_handle_command_timeout(struct + return; + } + /* mark this command to be cancelled */ +- xhci->current_cmd->status = COMP_CMD_ABORT; ++ xhci->current_cmd->status = COMP_COMMAND_ABORTED; + + /* Make sure command ring is running before aborting it */ + hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); +@@ -1347,7 +1347,7 @@ static void handle_cmd_completion(struct + cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); + + /* If CMD ring stopped we own the trbs between enqueue and dequeue */ +- if (cmd_comp_code == COMP_CMD_STOP) { ++ if (cmd_comp_code == COMP_STOPPED) { + complete_all(&xhci->cmd_ring_stop_completion); + return; + } +@@ -1364,9 +1364,9 @@ static void handle_cmd_completion(struct + * The command ring is stopped now, but the xHC will issue a Command + * Ring Stopped event which will cause us to restart it. + */ +- if (cmd_comp_code == COMP_CMD_ABORT) { ++ if (cmd_comp_code == COMP_COMMAND_ABORTED) { + xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; +- if (cmd->status == COMP_CMD_ABORT) { ++ if (cmd->status == COMP_COMMAND_ABORTED) { + if (xhci->current_cmd == cmd) + xhci->current_cmd = NULL; + goto event_handled; +@@ -1402,8 +1402,8 @@ static void handle_cmd_completion(struct + break; + case TRB_CMD_NOOP: + /* Is this an aborted command turned to NO-OP? */ +- if (cmd->status == COMP_CMD_STOP) +- cmd_comp_code = COMP_CMD_STOP; ++ if (cmd->status == COMP_STOPPED) ++ cmd_comp_code = COMP_STOPPED; + break; + case TRB_RESET_EP: + WARN_ON(slot_id != TRB_TO_SLOT_ID( +@@ -1796,9 +1796,9 @@ static int xhci_requires_manual_halt_cle + unsigned int trb_comp_code) + { + /* TRB completion codes that may require a manual halt cleanup */ +- if (trb_comp_code == COMP_TX_ERR || +- trb_comp_code == COMP_BABBLE || +- trb_comp_code == COMP_SPLIT_ERR) ++ if (trb_comp_code == COMP_USB_TRANSACTION_ERROR || ++ trb_comp_code == COMP_BABBLE_DETECTED_ERROR || ++ trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR) + /* The 0.95 spec says a babbling control endpoint + * is not halted. The 0.96 spec says it is. Some HW + * claims to be 0.95 compliant, but it halts the control +@@ -1852,9 +1852,9 @@ static int finish_td(struct xhci_hcd *xh + if (skip) + goto td_cleanup; + +- if (trb_comp_code == COMP_STOP_INVAL || +- trb_comp_code == COMP_STOP || +- trb_comp_code == COMP_STOP_SHORT) { ++ if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID || ++ trb_comp_code == COMP_STOPPED || ++ trb_comp_code == COMP_STOPPED_SHORT_PACKET) { + /* The Endpoint Stop Command completion will take care of any + * stopped TDs. A stopped TD may be restarted, so don't update + * the ring dequeue pointer or take this TD off any lists yet. +@@ -1862,7 +1862,7 @@ static int finish_td(struct xhci_hcd *xh + ep->stopped_td = td; + return 0; + } +- if (trb_comp_code == COMP_STALL || ++ if (trb_comp_code == COMP_STALL_ERROR || + xhci_requires_manual_halt_cleanup(xhci, ep_ctx, + trb_comp_code)) { + /* Issue a reset endpoint command to clear the host side +@@ -1973,16 +1973,16 @@ static int process_ctrl_td(struct xhci_h + } + *status = 0; + break; +- case COMP_SHORT_TX: ++ case COMP_SHORT_PACKET: + *status = 0; + break; +- case COMP_STOP_SHORT: ++ case COMP_STOPPED_SHORT_PACKET: + if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) + td->urb->actual_length = remaining; + else + xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); + goto finish_td; +- case COMP_STOP: ++ case COMP_STOPPED: + switch (trb_type) { + case TRB_SETUP: + td->urb->actual_length = 0; +@@ -1996,7 +1996,7 @@ static int process_ctrl_td(struct xhci_h + trb_type); + goto finish_td; + } +- case COMP_STOP_INVAL: ++ case COMP_STOPPED_LENGTH_INVALID: + goto finish_td; + default: + if (!xhci_requires_manual_halt_cleanup(xhci, +@@ -2005,7 +2005,7 @@ static int process_ctrl_td(struct xhci_h + xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n", + trb_comp_code, ep_index); + /* else fall through */ +- case COMP_STALL: ++ case COMP_STALL_ERROR: + /* Did we transfer part of the data (middle) phase? */ + if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) + td->urb->actual_length = requested - remaining; +@@ -2076,35 +2076,35 @@ static int process_isoc_td(struct xhci_h + } + frame->status = 0; + break; +- case COMP_SHORT_TX: ++ case COMP_SHORT_PACKET: + frame->status = short_framestatus; + sum_trbs_for_length = true; + break; +- case COMP_BW_OVER: ++ case COMP_BANDWIDTH_OVERRUN_ERROR: + frame->status = -ECOMM; + break; +- case COMP_BUFF_OVER: +- case COMP_BABBLE: ++ case COMP_ISOCH_BUFFER_OVERRUN: ++ case COMP_BABBLE_DETECTED_ERROR: + frame->status = -EOVERFLOW; + break; +- case COMP_DEV_ERR: +- case COMP_STALL: ++ case COMP_INCOMPATIBLE_DEVICE_ERROR: ++ case COMP_STALL_ERROR: + frame->status = -EPROTO; + break; +- case COMP_TX_ERR: ++ case COMP_USB_TRANSACTION_ERROR: + frame->status = -EPROTO; + if (ep_trb != td->last_trb) + return 0; + break; +- case COMP_STOP: ++ case COMP_STOPPED: + sum_trbs_for_length = true; + break; +- case COMP_STOP_SHORT: ++ case COMP_STOPPED_SHORT_PACKET: + /* field normally containing residue now contains tranferred */ + frame->status = short_framestatus; + requested = remaining; + break; +- case COMP_STOP_INVAL: ++ case COMP_STOPPED_LENGTH_INVALID: + requested = 0; + remaining = 0; + break; +@@ -2181,16 +2181,16 @@ static int process_bulk_intr_td(struct x + } + *status = 0; + break; +- case COMP_SHORT_TX: ++ case COMP_SHORT_PACKET: + xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", + td->urb->ep->desc.bEndpointAddress, + requested, remaining); + *status = 0; + break; +- case COMP_STOP_SHORT: ++ case COMP_STOPPED_SHORT_PACKET: + td->urb->actual_length = remaining; + goto finish_td; +- case COMP_STOP_INVAL: ++ case COMP_STOPPED_LENGTH_INVALID: + /* stopped on ep trb with invalid length, exclude it */ + ep_trb_len = 0; + remaining = 0; +@@ -2296,50 +2296,50 @@ static int handle_tx_event(struct xhci_h + if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) + break; + if (xhci->quirks & XHCI_TRUST_TX_LENGTH) +- trb_comp_code = COMP_SHORT_TX; ++ trb_comp_code = COMP_SHORT_PACKET; + else + xhci_warn_ratelimited(xhci, + "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n"); +- case COMP_SHORT_TX: ++ case COMP_SHORT_PACKET: + break; +- case COMP_STOP: ++ case COMP_STOPPED: + xhci_dbg(xhci, "Stopped on Transfer TRB\n"); + break; +- case COMP_STOP_INVAL: ++ case COMP_STOPPED_LENGTH_INVALID: + xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); + break; +- case COMP_STOP_SHORT: ++ case COMP_STOPPED_SHORT_PACKET: + xhci_dbg(xhci, "Stopped with short packet transfer detected\n"); + break; +- case COMP_STALL: ++ case COMP_STALL_ERROR: + xhci_dbg(xhci, "Stalled endpoint\n"); + ep->ep_state |= EP_HALTED; + status = -EPIPE; + break; +- case COMP_TRB_ERR: ++ case COMP_TRB_ERROR: + xhci_warn(xhci, "WARN: TRB error on endpoint\n"); + status = -EILSEQ; + break; +- case COMP_SPLIT_ERR: +- case COMP_TX_ERR: ++ case COMP_SPLIT_TRANSACTION_ERROR: ++ case COMP_USB_TRANSACTION_ERROR: + xhci_dbg(xhci, "Transfer error on endpoint\n"); + status = -EPROTO; + break; +- case COMP_BABBLE: ++ case COMP_BABBLE_DETECTED_ERROR: + xhci_dbg(xhci, "Babble error on endpoint\n"); + status = -EOVERFLOW; + break; +- case COMP_DB_ERR: ++ case COMP_DATA_BUFFER_ERROR: + xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); + status = -ENOSR; + break; +- case COMP_BW_OVER: ++ case COMP_BANDWIDTH_OVERRUN_ERROR: + xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); + break; +- case COMP_BUFF_OVER: ++ case COMP_ISOCH_BUFFER_OVERRUN: + xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); + break; +- case COMP_UNDERRUN: ++ case COMP_RING_UNDERRUN: + /* + * When the Isoch ring is empty, the xHC will generate + * a Ring Overrun Event for IN Isoch endpoint or Ring +@@ -2352,7 +2352,7 @@ static int handle_tx_event(struct xhci_h + TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), + ep_index); + goto cleanup; +- case COMP_OVERRUN: ++ case COMP_RING_OVERRUN: + xhci_dbg(xhci, "overrun event on endpoint\n"); + if (!list_empty(&ep_ring->td_list)) + xhci_dbg(xhci, "Overrun Event for slot %d ep %d " +@@ -2360,11 +2360,11 @@ static int handle_tx_event(struct xhci_h + TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), + ep_index); + goto cleanup; +- case COMP_DEV_ERR: ++ case COMP_INCOMPATIBLE_DEVICE_ERROR: + xhci_warn(xhci, "WARN: detect an incompatible device"); + status = -EPROTO; + break; +- case COMP_MISSED_INT: ++ case COMP_MISSED_SERVICE_ERROR: + /* + * When encounter missed service error, one or more isoc tds + * may be missed by xHC. +@@ -2374,7 +2374,7 @@ static int handle_tx_event(struct xhci_h + ep->skip = true; + xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); + goto cleanup; +- case COMP_PING_ERR: ++ case COMP_NO_PING_RESPONSE_ERROR: + ep->skip = true; + xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n"); + goto cleanup; +@@ -2398,8 +2398,8 @@ static int handle_tx_event(struct xhci_h + * event if the device was suspended. Don't print + * warnings. + */ +- if (!(trb_comp_code == COMP_STOP || +- trb_comp_code == COMP_STOP_INVAL)) { ++ if (!(trb_comp_code == COMP_STOPPED || ++ trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { + xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", + TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), + ep_index); +@@ -2440,8 +2440,8 @@ static int handle_tx_event(struct xhci_h + * last TRB of the previous TD. The command completion handle + * will take care the rest. + */ +- if (!ep_seg && (trb_comp_code == COMP_STOP || +- trb_comp_code == COMP_STOP_INVAL)) { ++ if (!ep_seg && (trb_comp_code == COMP_STOPPED || ++ trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { + goto cleanup; + } + +@@ -2472,7 +2472,7 @@ static int handle_tx_event(struct xhci_h + skip_isoc_td(xhci, td, event, ep, &status); + goto cleanup; + } +- if (trb_comp_code == COMP_SHORT_TX) ++ if (trb_comp_code == COMP_SHORT_PACKET) + ep_ring->last_td_was_short = true; + else + ep_ring->last_td_was_short = false; +@@ -2505,8 +2505,8 @@ static int handle_tx_event(struct xhci_h + &status); + cleanup: + handling_skipped_tds = ep->skip && +- trb_comp_code != COMP_MISSED_INT && +- trb_comp_code != COMP_PING_ERR; ++ trb_comp_code != COMP_MISSED_SERVICE_ERROR && ++ trb_comp_code != COMP_NO_PING_RESPONSE_ERROR; + + /* + * Do not update event ring dequeue pointer if we're in a loop +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1829,32 +1829,32 @@ static int xhci_configure_endpoint_resul + int ret; + + switch (*cmd_status) { +- case COMP_CMD_ABORT: +- case COMP_CMD_STOP: ++ case COMP_COMMAND_ABORTED: ++ case COMP_STOPPED: + xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n"); + ret = -ETIME; + break; +- case COMP_ENOMEM: ++ case COMP_RESOURCE_ERROR: + dev_warn(&udev->dev, + "Not enough host controller resources for new device state.\n"); + ret = -ENOMEM; + /* FIXME: can we allocate more resources for the HC? */ + break; +- case COMP_BW_ERR: +- case COMP_2ND_BW_ERR: ++ case COMP_BANDWIDTH_ERROR: ++ case COMP_SECONDARY_BANDWIDTH_ERROR: + dev_warn(&udev->dev, + "Not enough bandwidth for new device state.\n"); + ret = -ENOSPC; + /* FIXME: can we go back to the old state? */ + break; +- case COMP_TRB_ERR: ++ case COMP_TRB_ERROR: + /* the HCD set up something wrong */ + dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, " + "add flag = 1, " + "and endpoint is not disabled.\n"); + ret = -EINVAL; + break; +- case COMP_DEV_ERR: ++ case COMP_INCOMPATIBLE_DEVICE_ERROR: + dev_warn(&udev->dev, + "ERROR: Incompatible device for endpoint configure command.\n"); + ret = -ENODEV; +@@ -1880,33 +1880,33 @@ static int xhci_evaluate_context_result( + struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id]; + + switch (*cmd_status) { +- case COMP_CMD_ABORT: +- case COMP_CMD_STOP: ++ case COMP_COMMAND_ABORTED: ++ case COMP_STOPPED: + xhci_warn(xhci, "Timeout while waiting for evaluate context command\n"); + ret = -ETIME; + break; +- case COMP_EINVAL: ++ case COMP_PARAMETER_ERROR: + dev_warn(&udev->dev, + "WARN: xHCI driver setup invalid evaluate context command.\n"); + ret = -EINVAL; + break; +- case COMP_EBADSLT: ++ case COMP_SLOT_NOT_ENABLED_ERROR: + dev_warn(&udev->dev, + "WARN: slot not enabled for evaluate context command.\n"); + ret = -EINVAL; + break; +- case COMP_CTX_STATE: ++ case COMP_CONTEXT_STATE_ERROR: + dev_warn(&udev->dev, + "WARN: invalid context state for evaluate context command.\n"); + xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1); + ret = -EINVAL; + break; +- case COMP_DEV_ERR: ++ case COMP_INCOMPATIBLE_DEVICE_ERROR: + dev_warn(&udev->dev, + "ERROR: Incompatible device for evaluate context command.\n"); + ret = -ENODEV; + break; +- case COMP_MEL_ERR: ++ case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: + /* Max Exit Latency too large error */ + dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n"); + ret = -EINVAL; +@@ -3502,13 +3502,13 @@ int xhci_discover_or_reset_device(struct + */ + ret = reset_device_cmd->status; + switch (ret) { +- case COMP_CMD_ABORT: +- case COMP_CMD_STOP: ++ case COMP_COMMAND_ABORTED: ++ case COMP_STOPPED: + xhci_warn(xhci, "Timeout waiting for reset device command\n"); + ret = -ETIME; + goto command_cleanup; +- case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */ +- case COMP_CTX_STATE: /* 0.96 completion code for same thing */ ++ case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */ ++ case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */ + xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n", + slot_id, + xhci_get_slot_state(xhci, virt_dev->out_ctx)); +@@ -3868,22 +3868,22 @@ static int xhci_setup_device(struct usb_ + * command on a timeout. + */ + switch (command->status) { +- case COMP_CMD_ABORT: +- case COMP_CMD_STOP: ++ case COMP_COMMAND_ABORTED: ++ case COMP_STOPPED: + xhci_warn(xhci, "Timeout while waiting for setup device command\n"); + ret = -ETIME; + break; +- case COMP_CTX_STATE: +- case COMP_EBADSLT: ++ case COMP_CONTEXT_STATE_ERROR: ++ case COMP_SLOT_NOT_ENABLED_ERROR: + xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n", + act, udev->slot_id); + ret = -EINVAL; + break; +- case COMP_TX_ERR: ++ case COMP_USB_TRANSACTION_ERROR: + dev_warn(&udev->dev, "Device not responding to setup %s.\n", act); + ret = -EPROTO; + break; +- case COMP_DEV_ERR: ++ case COMP_INCOMPATIBLE_DEVICE_ERROR: + dev_warn(&udev->dev, + "ERROR: Incompatible device for setup %s command\n", act); + ret = -ENODEV; +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1060,76 +1060,42 @@ struct xhci_transfer_event { + /* Completion Code - only applicable for some types of TRBs */ + #define COMP_CODE_MASK (0xff << 24) + #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) +-#define COMP_SUCCESS 1 +-/* Data Buffer Error */ +-#define COMP_DB_ERR 2 +-/* Babble Detected Error */ +-#define COMP_BABBLE 3 +-/* USB Transaction Error */ +-#define COMP_TX_ERR 4 +-/* TRB Error - some TRB field is invalid */ +-#define COMP_TRB_ERR 5 +-/* Stall Error - USB device is stalled */ +-#define COMP_STALL 6 +-/* Resource Error - HC doesn't have memory for that device configuration */ +-#define COMP_ENOMEM 7 +-/* Bandwidth Error - not enough room in schedule for this dev config */ +-#define COMP_BW_ERR 8 +-/* No Slots Available Error - HC ran out of device slots */ +-#define COMP_ENOSLOTS 9 +-/* Invalid Stream Type Error */ +-#define COMP_STREAM_ERR 10 +-/* Slot Not Enabled Error - doorbell rung for disabled device slot */ +-#define COMP_EBADSLT 11 +-/* Endpoint Not Enabled Error */ +-#define COMP_EBADEP 12 +-/* Short Packet */ +-#define COMP_SHORT_TX 13 +-/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ +-#define COMP_UNDERRUN 14 +-/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ +-#define COMP_OVERRUN 15 +-/* Virtual Function Event Ring Full Error */ +-#define COMP_VF_FULL 16 +-/* Parameter Error - Context parameter is invalid */ +-#define COMP_EINVAL 17 +-/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ +-#define COMP_BW_OVER 18 +-/* Context State Error - illegal context state transition requested */ +-#define COMP_CTX_STATE 19 +-/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ +-#define COMP_PING_ERR 20 +-/* Event Ring is full */ +-#define COMP_ER_FULL 21 +-/* Incompatible Device Error */ +-#define COMP_DEV_ERR 22 +-/* Missed Service Error - HC couldn't service an isoc ep within interval */ +-#define COMP_MISSED_INT 23 +-/* Successfully stopped command ring */ +-#define COMP_CMD_STOP 24 +-/* Successfully aborted current command and stopped command ring */ +-#define COMP_CMD_ABORT 25 +-/* Stopped - transfer was terminated by a stop endpoint command */ +-#define COMP_STOP 26 +-/* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */ +-#define COMP_STOP_INVAL 27 +-/* Same as COMP_EP_STOPPED, but a short packet detected */ +-#define COMP_STOP_SHORT 28 +-/* Max Exit Latency Too Large Error */ +-#define COMP_MEL_ERR 29 +-/* TRB type 30 reserved */ +-/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ +-#define COMP_BUFF_OVER 31 +-/* Event Lost Error - xHC has an "internal event overrun condition" */ +-#define COMP_ISSUES 32 +-/* Undefined Error - reported when other error codes don't apply */ +-#define COMP_UNKNOWN 33 +-/* Invalid Stream ID Error */ +-#define COMP_STRID_ERR 34 +-/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ +-#define COMP_2ND_BW_ERR 35 +-/* Split Transaction Error */ +-#define COMP_SPLIT_ERR 36 ++#define COMP_INVALID 0 ++#define COMP_SUCCESS 1 ++#define COMP_DATA_BUFFER_ERROR 2 ++#define COMP_BABBLE_DETECTED_ERROR 3 ++#define COMP_USB_TRANSACTION_ERROR 4 ++#define COMP_TRB_ERROR 5 ++#define COMP_STALL_ERROR 6 ++#define COMP_RESOURCE_ERROR 7 ++#define COMP_BANDWIDTH_ERROR 8 ++#define COMP_NO_SLOTS_AVAILABLE_ERROR 9 ++#define COMP_INVALID_STREAM_TYPE_ERROR 10 ++#define COMP_SLOT_NOT_ENABLED_ERROR 11 ++#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 ++#define COMP_SHORT_PACKET 13 ++#define COMP_RING_UNDERRUN 14 ++#define COMP_RING_OVERRUN 15 ++#define COMP_VF_EVENT_RING_FULL_ERROR 16 ++#define COMP_PARAMETER_ERROR 17 ++#define COMP_BANDWIDTH_OVERRUN_ERROR 18 ++#define COMP_CONTEXT_STATE_ERROR 19 ++#define COMP_NO_PING_RESPONSE_ERROR 20 ++#define COMP_EVENT_RING_FULL_ERROR 21 ++#define COMP_INCOMPATIBLE_DEVICE_ERROR 22 ++#define COMP_MISSED_SERVICE_ERROR 23 ++#define COMP_COMMAND_RING_STOPPED 24 ++#define COMP_COMMAND_ABORTED 25 ++#define COMP_STOPPED 26 ++#define COMP_STOPPED_LENGTH_INVALID 27 ++#define COMP_STOPPED_SHORT_PACKET 28 ++#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 ++#define COMP_ISOCH_BUFFER_OVERRUN 31 ++#define COMP_EVENT_LOST_ERROR 32 ++#define COMP_UNDEFINED_ERROR 33 ++#define COMP_INVALID_STREAM_ID_ERROR 34 ++#define COMP_SECONDARY_BANDWIDTH_ERROR 35 ++#define COMP_SPLIT_TRANSACTION_ERROR 36 + + struct xhci_link_trb { + /* 64-bit segment pointer*/ diff --git a/patches.renesas/0195-usb-host-xhci-simplify-irq-handler-return.patch b/patches.renesas/0195-usb-host-xhci-simplify-irq-handler-return.patch new file mode 100644 index 0000000000000..2e3edf4d1b2d7 --- /dev/null +++ b/patches.renesas/0195-usb-host-xhci-simplify-irq-handler-return.patch @@ -0,0 +1,87 @@ +From 3d71eb22895dbf5e5081b1b96976803e3c6eb090 Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:07 +0200 +Subject: [PATCH 195/255] usb: host: xhci: simplify irq handler return + +Instead of having several return points, let's use a local variable and +a single place to return. This makes the code slightly easier to read. + +[set ret = IRQ_HANDLED in default working case -Mathias] +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> + +(cherry picked from commit 76a35293b901915c5dcb4a87a4a0da8d7caf39fe) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 32 +++++++++++++++++--------------- + 1 file changed, 17 insertions(+), 15 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -2608,27 +2608,28 @@ static int xhci_handle_event(struct xhci + irqreturn_t xhci_irq(struct usb_hcd *hcd) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); +- u32 status; +- u64 temp_64; + union xhci_trb *event_ring_deq; ++ irqreturn_t ret = IRQ_NONE; + dma_addr_t deq; ++ u64 temp_64; ++ u32 status; + + spin_lock(&xhci->lock); + /* Check if the xHC generated the interrupt, or the irq is shared */ + status = readl(&xhci->op_regs->status); +- if (status == 0xffffffff) +- goto hw_died; +- +- if (!(status & STS_EINT)) { +- spin_unlock(&xhci->lock); +- return IRQ_NONE; ++ if (status == 0xffffffff) { ++ ret = IRQ_HANDLED; ++ goto out; + } ++ ++ if (!(status & STS_EINT)) ++ goto out; ++ + if (status & STS_FATAL) { + xhci_warn(xhci, "WARNING: Host System Error\n"); + xhci_halt(xhci); +-hw_died: +- spin_unlock(&xhci->lock); +- return IRQ_HANDLED; ++ ret = IRQ_HANDLED; ++ goto out; + } + + /* +@@ -2659,9 +2660,8 @@ hw_died: + temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); + xhci_write_64(xhci, temp_64 | ERST_EHB, + &xhci->ir_set->erst_dequeue); +- spin_unlock(&xhci->lock); +- +- return IRQ_HANDLED; ++ ret = IRQ_HANDLED; ++ goto out; + } + + event_ring_deq = xhci->event_ring->dequeue; +@@ -2686,10 +2686,12 @@ hw_died: + /* Clear the event handler busy flag (RW1C); event ring is empty. */ + temp_64 |= ERST_EHB; + xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); ++ ret = IRQ_HANDLED; + ++out: + spin_unlock(&xhci->lock); + +- return IRQ_HANDLED; ++ return ret; + } + + irqreturn_t xhci_msi_irq(int irq, void *hcd) diff --git a/patches.renesas/0196-usb-host-xhci-use-slightly-better-list-helpers.patch b/patches.renesas/0196-usb-host-xhci-use-slightly-better-list-helpers.patch new file mode 100644 index 0000000000000..093d13f2ac6b5 --- /dev/null +++ b/patches.renesas/0196-usb-host-xhci-use-slightly-better-list-helpers.patch @@ -0,0 +1,94 @@ +From 17fe56b3294003385f4706221ad468bc0eb991dc Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:09 +0200 +Subject: [PATCH 196/255] usb: host: xhci: use slightly better list helpers + +Replace list_entry() with list_first_entry() and list_for_each() with +list_for_each_entry(). This makes the code slightly more readable. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 04861f83367eaa3f32e3a1433afe8274e9a5f7f1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 19 ++++++++++--------- + 1 file changed, 10 insertions(+), 9 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -689,7 +689,6 @@ static void xhci_handle_cmd_stop_ep(stru + unsigned int ep_index; + struct xhci_ring *ep_ring; + struct xhci_virt_ep *ep; +- struct list_head *entry; + struct xhci_td *cur_td = NULL; + struct xhci_td *last_unlinked_td; + +@@ -706,6 +705,8 @@ static void xhci_handle_cmd_stop_ep(stru + memset(&deq_state, 0, sizeof(deq_state)); + ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); + ep = &xhci->devs[slot_id]->eps[ep_index]; ++ last_unlinked_td = list_last_entry(&ep->cancelled_td_list, ++ struct xhci_td, cancelled_td_list); + + if (list_empty(&ep->cancelled_td_list)) { + xhci_stop_watchdog_timer_in_irq(xhci, ep); +@@ -719,8 +720,7 @@ static void xhci_handle_cmd_stop_ep(stru + * it. We're also in the event handler, so we can't get re-interrupted + * if another Stop Endpoint command completes + */ +- list_for_each(entry, &ep->cancelled_td_list) { +- cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); ++ list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) { + xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, + "Removing canceled TD starting at 0x%llx (dma).", + (unsigned long long)xhci_trb_virt_to_dma( +@@ -762,7 +762,7 @@ remove_finished_td: + */ + list_del_init(&cur_td->td_list); + } +- last_unlinked_td = cur_td; ++ + xhci_stop_watchdog_timer_in_irq(xhci, ep); + + /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ +@@ -784,7 +784,7 @@ remove_finished_td: + * So stop when we've completed the URB for the last TD we unlinked. + */ + do { +- cur_td = list_entry(ep->cancelled_td_list.next, ++ cur_td = list_first_entry(&ep->cancelled_td_list, + struct xhci_td, cancelled_td_list); + list_del_init(&cur_td->cancelled_td_list); + +@@ -1338,7 +1338,7 @@ static void handle_cmd_completion(struct + return; + } + +- cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list); ++ cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list); + + cancel_delayed_work(&xhci->cmd_timer); + +@@ -1429,8 +1429,8 @@ static void handle_cmd_completion(struct + + /* restart timer if this wasn't the last command */ + if (!list_is_singular(&xhci->cmd_list)) { +- xhci->current_cmd = list_entry(cmd->cmd_list.next, +- struct xhci_command, cmd_list); ++ xhci->current_cmd = list_first_entry(&cmd->cmd_list, ++ struct xhci_command, cmd_list); + xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); + } else if (xhci->current_cmd == cmd) { + xhci->current_cmd = NULL; +@@ -2424,7 +2424,8 @@ static int handle_tx_event(struct xhci_h + goto cleanup; + } + +- td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); ++ td = list_first_entry(&ep_ring->td_list, struct xhci_td, ++ td_list); + if (ep->skip) + td_num--; + diff --git a/patches.renesas/0197-usb-host-xhci-reorder-variable-definitions.patch b/patches.renesas/0197-usb-host-xhci-reorder-variable-definitions.patch new file mode 100644 index 0000000000000..b4e27084cd4a1 --- /dev/null +++ b/patches.renesas/0197-usb-host-xhci-reorder-variable-definitions.patch @@ -0,0 +1,47 @@ +From 472de28e1eeda25e4fedaea6781e8196d9288404 Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:10 +0200 +Subject: [PATCH 197/255] usb: host: xhci: reorder variable definitions + +no functional changes. Simple cleanup to make sure variables are ordered +in a 'reverse christmas tree' fashion. While at that, also remove an +obsolete comment which doesn't apply anymore. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit be0f50c2e3c4bb9bd8fcb4b89879ae62308019bf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 12 ++++-------- + 1 file changed, 4 insertions(+), 8 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -1825,22 +1825,18 @@ int xhci_is_vendor_info_code(struct xhci + return 0; + } + +-/* +- * Finish the td processing, remove the td from td list; +- * Return 1 if the urb can be given back. +- */ + static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, + union xhci_trb *ep_trb, struct xhci_transfer_event *event, + struct xhci_virt_ep *ep, int *status, bool skip) + { + struct xhci_virt_device *xdev; +- struct xhci_ring *ep_ring; +- unsigned int slot_id; +- int ep_index; +- struct urb *urb = NULL; + struct xhci_ep_ctx *ep_ctx; ++ struct xhci_ring *ep_ring; + struct urb_priv *urb_priv; ++ struct urb *urb = NULL; ++ unsigned int slot_id; + u32 trb_comp_code; ++ int ep_index; + + slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); + xdev = xhci->devs[slot_id]; diff --git a/patches.renesas/0198-usb-host-xhci-introduce-xhci_td_cleanup.patch b/patches.renesas/0198-usb-host-xhci-introduce-xhci_td_cleanup.patch new file mode 100644 index 0000000000000..f1231a609a285 --- /dev/null +++ b/patches.renesas/0198-usb-host-xhci-introduce-xhci_td_cleanup.patch @@ -0,0 +1,134 @@ +From 1eb94a825e9c0bb4890e2c8c4154b8b7f371b954 Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:11 +0200 +Subject: [PATCH 198/255] usb: host: xhci: introduce xhci_td_cleanup() + +By extracting xhci_td_cleanup() from finish_td(), code before clearer +and easier to follow. + +There are no functional changes with this patch. It's merely a cleanup. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 55fa4396b24db2adbcf5659ce3d7397c31e6b51c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 92 +++++++++++++++++++++++-------------------- + 1 file changed, 50 insertions(+), 42 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -1825,6 +1825,55 @@ int xhci_is_vendor_info_code(struct xhci + return 0; + } + ++static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td, ++ struct xhci_ring *ep_ring, int *status) ++{ ++ struct urb_priv *urb_priv; ++ struct urb *urb = NULL; ++ ++ /* Clean up the endpoint's TD list */ ++ urb = td->urb; ++ urb_priv = urb->hcpriv; ++ ++ /* if a bounce buffer was used to align this td then unmap it */ ++ if (td->bounce_seg) ++ xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); ++ ++ /* Do one last check of the actual transfer length. ++ * If the host controller said we transferred more data than the buffer ++ * length, urb->actual_length will be a very big number (since it's ++ * unsigned). Play it safe and say we didn't transfer anything. ++ */ ++ if (urb->actual_length > urb->transfer_buffer_length) { ++ xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", ++ urb->transfer_buffer_length, urb->actual_length); ++ urb->actual_length = 0; ++ *status = 0; ++ } ++ list_del_init(&td->td_list); ++ /* Was this TD slated to be cancelled but completed anyway? */ ++ if (!list_empty(&td->cancelled_td_list)) ++ list_del_init(&td->cancelled_td_list); ++ ++ inc_td_cnt(urb); ++ /* Giveback the urb when all the tds are completed */ ++ if (last_td_in_urb(td)) { ++ if ((urb->actual_length != urb->transfer_buffer_length && ++ (urb->transfer_flags & URB_SHORT_NOT_OK)) || ++ (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) ++ xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", ++ urb, urb->actual_length, ++ urb->transfer_buffer_length, *status); ++ ++ /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ++ *status = 0; ++ xhci_giveback_urb_in_irq(xhci, td, *status); ++ } ++ ++ return 0; ++} ++ + static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, + union xhci_trb *ep_trb, struct xhci_transfer_event *event, + struct xhci_virt_ep *ep, int *status, bool skip) +@@ -1832,8 +1881,6 @@ static int finish_td(struct xhci_hcd *xh + struct xhci_virt_device *xdev; + struct xhci_ep_ctx *ep_ctx; + struct xhci_ring *ep_ring; +- struct urb_priv *urb_priv; +- struct urb *urb = NULL; + unsigned int slot_id; + u32 trb_comp_code; + int ep_index; +@@ -1876,46 +1923,7 @@ static int finish_td(struct xhci_hcd *xh + } + + td_cleanup: +- /* Clean up the endpoint's TD list */ +- urb = td->urb; +- urb_priv = urb->hcpriv; +- +- /* if a bounce buffer was used to align this td then unmap it */ +- if (td->bounce_seg) +- xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); +- +- /* Do one last check of the actual transfer length. +- * If the host controller said we transferred more data than the buffer +- * length, urb->actual_length will be a very big number (since it's +- * unsigned). Play it safe and say we didn't transfer anything. +- */ +- if (urb->actual_length > urb->transfer_buffer_length) { +- xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", +- urb->transfer_buffer_length, urb->actual_length); +- urb->actual_length = 0; +- *status = 0; +- } +- list_del_init(&td->td_list); +- /* Was this TD slated to be cancelled but completed anyway? */ +- if (!list_empty(&td->cancelled_td_list)) +- list_del_init(&td->cancelled_td_list); +- +- inc_td_cnt(urb); +- /* Giveback the urb when all the tds are completed */ +- if (last_td_in_urb(td)) { +- if ((urb->actual_length != urb->transfer_buffer_length && +- (urb->transfer_flags & URB_SHORT_NOT_OK)) || +- (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) +- xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", +- urb, urb->actual_length, +- urb->transfer_buffer_length, *status); +- +- /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ +- if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) +- *status = 0; +- xhci_giveback_urb_in_irq(xhci, td, *status); +- } +- return 0; ++ return xhci_td_cleanup(xhci, td, ep_ring, status); + } + + /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */ diff --git a/patches.renesas/0199-usb-host-xhci-remove-bogus-__releases-__acquires-ann.patch b/patches.renesas/0199-usb-host-xhci-remove-bogus-__releases-__acquires-ann.patch new file mode 100644 index 0000000000000..7002e85b4970e --- /dev/null +++ b/patches.renesas/0199-usb-host-xhci-remove-bogus-__releases-__acquires-ann.patch @@ -0,0 +1,29 @@ +From 804aff6c2d4f3d9d74b4921fddeeef6ae7a5059c Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:12 +0200 +Subject: [PATCH 199/255] usb: host: xhci: remove bogus + __releases()/__acquires() annotation + +handle_tx_event() is not releasing xhci->lock nor reacquiring it, remove +the bogus annotation. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit f3899a28e2b8a6f208187033789ac0f038d3c08e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -2226,8 +2226,6 @@ finish_td: + */ + static int handle_tx_event(struct xhci_hcd *xhci, + struct xhci_transfer_event *event) +- __releases(&xhci->lock) +- __acquires(&xhci->lock) + { + struct xhci_virt_device *xdev; + struct xhci_virt_ep *ep; diff --git a/patches.renesas/0200-usb-host-xhci-check-for-a-valid-ring-when-unmapping-.patch b/patches.renesas/0200-usb-host-xhci-check-for-a-valid-ring-when-unmapping-.patch new file mode 100644 index 0000000000000..51a5db616afa7 --- /dev/null +++ b/patches.renesas/0200-usb-host-xhci-check-for-a-valid-ring-when-unmapping-.patch @@ -0,0 +1,29 @@ +From 06b343e6491daae63773eb5ef03d90596a4ddf96 Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:13 +0200 +Subject: [PATCH 200/255] usb: host: xhci: check for a valid ring when + unmapping bounce buffer + +This way we can remove checks for valid ring from call sites of +xhci_unmap_td_bounce_buffer() + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit f45e2a02112a1ed03925521c9f48e4bdc25c7032) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -655,7 +655,7 @@ static void xhci_unmap_td_bounce_buffer( + struct xhci_segment *seg = td->bounce_seg; + struct urb *urb = td->urb; + +- if (!seg || !urb) ++ if (!ring || !seg || !urb) + return; + + if (usb_urb_dir_out(urb)) { diff --git a/patches.renesas/0201-usb-host-xhci-unconditionally-call-xhci_unmap_td_bou.patch b/patches.renesas/0201-usb-host-xhci-unconditionally-call-xhci_unmap_td_bou.patch new file mode 100644 index 0000000000000..cbeea8bbc59c1 --- /dev/null +++ b/patches.renesas/0201-usb-host-xhci-unconditionally-call-xhci_unmap_td_bou.patch @@ -0,0 +1,51 @@ +From 547161efca2c19b5fca1a02e8716dd0a95c07e08 Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:14 +0200 +Subject: [PATCH 201/255] usb: host: xhci: unconditionally call + xhci_unmap_td_bounce_buffer() + +xhci_unmap_td_bounce_buffer() already checks for a valid td->bounce_seg +and bails out early if that's invalid. There's no need to check for this +twice. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit a60f2f2ffabe14a559510dcf347bef9a7a312516) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 9 +++------ + 1 file changed, 3 insertions(+), 6 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -793,8 +793,7 @@ remove_finished_td: + * just overwrite it (because the URB has been unlinked). + */ + ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); +- if (ep_ring && cur_td->bounce_seg) +- xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td); ++ xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td); + inc_td_cnt(cur_td->urb); + if (last_td_in_urb(cur_td)) + xhci_giveback_urb_in_irq(xhci, cur_td, 0); +@@ -820,8 +819,7 @@ static void xhci_kill_ring_urbs(struct x + if (!list_empty(&cur_td->cancelled_td_list)) + list_del_init(&cur_td->cancelled_td_list); + +- if (cur_td->bounce_seg) +- xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); ++ xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); + + inc_td_cnt(cur_td->urb); + if (last_td_in_urb(cur_td)) +@@ -1836,8 +1834,7 @@ static int xhci_td_cleanup(struct xhci_h + urb_priv = urb->hcpriv; + + /* if a bounce buffer was used to align this td then unmap it */ +- if (td->bounce_seg) +- xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); ++ xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); + + /* Do one last check of the actual transfer length. + * If the host controller said we transferred more data than the buffer diff --git a/patches.renesas/0202-xhci-Introduce-helper-to-turn-one-TRB-into-a-no-op.patch b/patches.renesas/0202-xhci-Introduce-helper-to-turn-one-TRB-into-a-no-op.patch new file mode 100644 index 0000000000000..4f44a0dbe5204 --- /dev/null +++ b/patches.renesas/0202-xhci-Introduce-helper-to-turn-one-TRB-into-a-no-op.patch @@ -0,0 +1,63 @@ +From 86866e7445ac9ead508402559f4a6c64fc4d6a94 Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:15 +0200 +Subject: [PATCH 202/255] xhci: Introduce helper to turn one TRB into a no-op + +Useful for turning both transfer and command trbs +into no-ops. + +Based on earlier code by Felipe Balbi <felipe.balbi@linux.intel.com> + +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit ae1e3f07320884ff25354d8233dc18d5283b0bb8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 29 +++++++++++++++++------------ + 1 file changed, 17 insertions(+), 12 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -129,6 +129,21 @@ static void inc_td_cnt(struct urb *urb) + urb_priv->td_cnt++; + } + ++static void trb_to_noop(union xhci_trb *trb, u32 noop_type) ++{ ++ if (trb_is_link(trb)) { ++ /* unchain chained link TRBs */ ++ trb->link.control &= cpu_to_le32(~TRB_CHAIN); ++ } else { ++ trb->generic.field[0] = 0; ++ trb->generic.field[1] = 0; ++ trb->generic.field[2] = 0; ++ /* Preserve only the cycle bit of this TRB */ ++ trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); ++ trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type)); ++ } ++} ++ + /* Updates trb to point to the next TRB in the ring, and updates seg if the next + * TRB is in a new segment. This does not skip over link TRBs, and it does not + * effect the ring dequeue or enqueue pointers. +@@ -592,18 +607,8 @@ static void td_to_noop(struct xhci_hcd * + union xhci_trb *trb = td->first_trb; + + while (1) { +- if (trb_is_link(trb)) { +- /* unchain chained link TRBs */ +- trb->link.control &= cpu_to_le32(~TRB_CHAIN); +- } else { +- trb->generic.field[0] = 0; +- trb->generic.field[1] = 0; +- trb->generic.field[2] = 0; +- /* Preserve only the cycle bit of this TRB */ +- trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); +- trb->generic.field[3] |= cpu_to_le32( +- TRB_TYPE(TRB_TR_NOOP)); +- } ++ trb_to_noop(trb, TRB_TR_NOOP); ++ + /* flip cycle if asked to */ + if (flip_cycle && trb != td->first_trb && trb != td->last_trb) + trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE); diff --git a/patches.renesas/0203-xhci-use-the-trb_to_noop-helper-for-command-trbs.patch b/patches.renesas/0203-xhci-use-the-trb_to_noop-helper-for-command-trbs.patch new file mode 100644 index 0000000000000..868917ed1a374 --- /dev/null +++ b/patches.renesas/0203-xhci-use-the-trb_to_noop-helper-for-command-trbs.patch @@ -0,0 +1,46 @@ +From ed9c0e52ee23f8a06e3eb752a6824d4abd31c685 Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:16 +0200 +Subject: [PATCH 203/255] xhci: use the trb_to_noop() helper for command trbs + +Remove duplicate code by using trb_to_noop() when +handling Aborted commads + +Based on earlier code by Felipe Balbi <felipe.balbi@linux.intel.com> + +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 5278204c98188ac9fd2e75b936eec1015d062a75) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 12 ++---------- + 1 file changed, 2 insertions(+), 10 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -314,7 +314,6 @@ static void xhci_handle_stopped_cmd_ring + struct xhci_command *cur_cmd) + { + struct xhci_command *i_cmd; +- u32 cycle_state; + + /* Turn all aborted commands in list to no-ops, then restart */ + list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { +@@ -326,15 +325,8 @@ static void xhci_handle_stopped_cmd_ring + + xhci_dbg(xhci, "Turn aborted command %p to no-op\n", + i_cmd->command_trb); +- /* get cycle state from the original cmd trb */ +- cycle_state = le32_to_cpu( +- i_cmd->command_trb->generic.field[3]) & TRB_CYCLE; +- /* modify the command trb to no-op command */ +- i_cmd->command_trb->generic.field[0] = 0; +- i_cmd->command_trb->generic.field[1] = 0; +- i_cmd->command_trb->generic.field[2] = 0; +- i_cmd->command_trb->generic.field[3] = cpu_to_le32( +- TRB_TYPE(TRB_CMD_NOOP) | cycle_state); ++ ++ trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP); + + /* + * caller waiting for completion is called when command diff --git a/patches.renesas/0204-usb-host-xhci-convert-to-list_for_each_entry_safe.patch b/patches.renesas/0204-usb-host-xhci-convert-to-list_for_each_entry_safe.patch new file mode 100644 index 0000000000000..ddbcb41f2d987 --- /dev/null +++ b/patches.renesas/0204-usb-host-xhci-convert-to-list_for_each_entry_safe.patch @@ -0,0 +1,60 @@ +From 38cdfd1d15a427e1010347cbbbd4fe4781427f4e Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:17 +0200 +Subject: [PATCH 204/255] usb: host: xhci: convert to + list_for_each_entry_safe() + +instead of using while(!list_empty()) followed by list_first_entry(), we +can actually use list_for_each_entry_safe(). + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit a54cfae3c7727c2c172fdcd5886b4235b833da6c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 15 ++++++++------- + 1 file changed, 8 insertions(+), 7 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -808,11 +808,11 @@ remove_finished_td: + static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) + { + struct xhci_td *cur_td; ++ struct xhci_td *tmp; + +- while (!list_empty(&ring->td_list)) { +- cur_td = list_first_entry(&ring->td_list, +- struct xhci_td, td_list); ++ list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) { + list_del_init(&cur_td->td_list); ++ + if (!list_empty(&cur_td->cancelled_td_list)) + list_del_init(&cur_td->cancelled_td_list); + +@@ -828,6 +828,7 @@ static void xhci_kill_endpoint_urbs(stru + int slot_id, int ep_index) + { + struct xhci_td *cur_td; ++ struct xhci_td *tmp; + struct xhci_virt_ep *ep; + struct xhci_ring *ring; + +@@ -856,12 +857,12 @@ static void xhci_kill_endpoint_urbs(stru + slot_id, ep_index); + xhci_kill_ring_urbs(xhci, ring); + } +- while (!list_empty(&ep->cancelled_td_list)) { +- cur_td = list_first_entry(&ep->cancelled_td_list, +- struct xhci_td, cancelled_td_list); +- list_del_init(&cur_td->cancelled_td_list); + ++ list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list, ++ cancelled_td_list) { ++ list_del_init(&cur_td->cancelled_td_list); + inc_td_cnt(cur_td->urb); ++ + if (last_td_in_urb(cur_td)) + xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); + } diff --git a/patches.renesas/0205-usb-host-xhci-combine-event-TRB-completion-debugging.patch b/patches.renesas/0205-usb-host-xhci-combine-event-TRB-completion-debugging.patch new file mode 100644 index 0000000000000..ef551b18f24b4 --- /dev/null +++ b/patches.renesas/0205-usb-host-xhci-combine-event-TRB-completion-debugging.patch @@ -0,0 +1,109 @@ +From c823c464a858884b075f6ccb19792538f44d776f Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:18 +0200 +Subject: [PATCH 205/255] usb: host: xhci: combine event TRB completion + debugging messages + +If we just provide a helper to convert completion code to string, we can +combine all debugging messages into a single print. + +[keep the old debug messages, for warn and grep -Mathias] +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> + +(cherry picked from commit ed6d643b14e7bc2fac794a0bbac7dd742ca2ed80) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.h | 80 ++++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 80 insertions(+) + +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1097,6 +1097,86 @@ struct xhci_transfer_event { + #define COMP_SECONDARY_BANDWIDTH_ERROR 35 + #define COMP_SPLIT_TRANSACTION_ERROR 36 + ++static inline const char *xhci_trb_comp_code_string(u8 status) ++{ ++ switch (status) { ++ case COMP_INVALID: ++ return "Invalid"; ++ case COMP_SUCCESS: ++ return "Success"; ++ case COMP_DATA_BUFFER_ERROR: ++ return "Data Buffer Error"; ++ case COMP_BABBLE_DETECTED_ERROR: ++ return "Babble Detected"; ++ case COMP_USB_TRANSACTION_ERROR: ++ return "USB Transaction Error"; ++ case COMP_TRB_ERROR: ++ return "TRB Error"; ++ case COMP_STALL_ERROR: ++ return "Stall Error"; ++ case COMP_RESOURCE_ERROR: ++ return "Resource Error"; ++ case COMP_BANDWIDTH_ERROR: ++ return "Bandwidth Error"; ++ case COMP_NO_SLOTS_AVAILABLE_ERROR: ++ return "No Slots Available Error"; ++ case COMP_INVALID_STREAM_TYPE_ERROR: ++ return "Invalid Stream Type Error"; ++ case COMP_SLOT_NOT_ENABLED_ERROR: ++ return "Slot Not Enabled Error"; ++ case COMP_ENDPOINT_NOT_ENABLED_ERROR: ++ return "Endpoint Not Enabled Error"; ++ case COMP_SHORT_PACKET: ++ return "Short Packet"; ++ case COMP_RING_UNDERRUN: ++ return "Ring Underrun"; ++ case COMP_RING_OVERRUN: ++ return "Ring Overrun"; ++ case COMP_VF_EVENT_RING_FULL_ERROR: ++ return "VF Event Ring Full Error"; ++ case COMP_PARAMETER_ERROR: ++ return "Parameter Error"; ++ case COMP_BANDWIDTH_OVERRUN_ERROR: ++ return "Bandwidth Overrun Error"; ++ case COMP_CONTEXT_STATE_ERROR: ++ return "Context State Error"; ++ case COMP_NO_PING_RESPONSE_ERROR: ++ return "No Ping Response Error"; ++ case COMP_EVENT_RING_FULL_ERROR: ++ return "Event Ring Full Error"; ++ case COMP_INCOMPATIBLE_DEVICE_ERROR: ++ return "Incompatible Device Error"; ++ case COMP_MISSED_SERVICE_ERROR: ++ return "Missed Service Error"; ++ case COMP_COMMAND_RING_STOPPED: ++ return "Command Ring Stopped"; ++ case COMP_COMMAND_ABORTED: ++ return "Command Aborted"; ++ case COMP_STOPPED: ++ return "Stopped"; ++ case COMP_STOPPED_LENGTH_INVALID: ++ return "Stopped - Length Invalid"; ++ case COMP_STOPPED_SHORT_PACKET: ++ return "Stopped - Short Packet"; ++ case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: ++ return "Max Exit Latency Too Large Error"; ++ case COMP_ISOCH_BUFFER_OVERRUN: ++ return "Isoch Buffer Overrun"; ++ case COMP_EVENT_LOST_ERROR: ++ return "Event Lost Error"; ++ case COMP_UNDEFINED_ERROR: ++ return "Undefined Error"; ++ case COMP_INVALID_STREAM_ID_ERROR: ++ return "Invalid Stream ID Error"; ++ case COMP_SECONDARY_BANDWIDTH_ERROR: ++ return "Secondary Bandwidth Error"; ++ case COMP_SPLIT_TRANSACTION_ERROR: ++ return "Split Transaction Error"; ++ default: ++ return "Unknown!!"; ++ } ++} ++ + struct xhci_link_trb { + /* 64-bit segment pointer*/ + __le64 segment_ptr; diff --git a/patches.renesas/0206-usb-host-xhci-make-a-generic-TRB-tracer.patch b/patches.renesas/0206-usb-host-xhci-make-a-generic-TRB-tracer.patch new file mode 100644 index 0000000000000..ee31d23f974c3 --- /dev/null +++ b/patches.renesas/0206-usb-host-xhci-make-a-generic-TRB-tracer.patch @@ -0,0 +1,518 @@ +From e69caaab839079cadd29abdff525ddfd4cb65ce4 Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:19 +0200 +Subject: [PATCH 206/255] usb: host: xhci: make a generic TRB tracer + +instead of having a tracer that can only trace command completions, +let's promote this tracer so it can trace and decode any TRB. + +With that, it will be easier to extrapolate the lifetime of any TRB +which might help debugging certain issues. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit a37c3f76e6a6b5eabacb1364c2218b0daafab18a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 14 + + drivers/usb/host/xhci-trace.h | 55 ++++--- + drivers/usb/host/xhci.h | 329 ++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 375 insertions(+), 23 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -1322,6 +1322,9 @@ static void handle_cmd_completion(struct + + cmd_dma = le64_to_cpu(event->cmd_trb); + cmd_trb = xhci->cmd_ring->dequeue; ++ ++ trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic); ++ + cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, + cmd_trb); + /* +@@ -1338,8 +1341,6 @@ static void handle_cmd_completion(struct + + cancel_delayed_work(&xhci->cmd_timer); + +- trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event); +- + cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); + + /* If CMD ring stopped we own the trbs between enqueue and dequeue */ +@@ -2482,6 +2483,10 @@ static int handle_tx_event(struct xhci_h + + ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / + sizeof(*ep_trb)]; ++ ++ trace_xhci_handle_transfer(ep_ring, ++ (struct xhci_generic_trb *) ep_trb); ++ + /* + * No-op TRB should not trigger interrupts. + * If ep_trb is a no-op TRB, it means the +@@ -2548,6 +2553,8 @@ static int xhci_handle_event(struct xhci + xhci->event_ring->cycle_state) + return 0; + ++ trace_xhci_handle_event(xhci->event_ring, &event->generic); ++ + /* + * Barrier between reading the TRB_CYCLE (valid) flag above and any + * speculative reads of the event's flags/data below. +@@ -2717,6 +2724,9 @@ static void queue_trb(struct xhci_hcd *x + trb->field[1] = cpu_to_le32(field2); + trb->field[2] = cpu_to_le32(field3); + trb->field[3] = cpu_to_le32(field4); ++ ++ trace_xhci_queue_trb(ring, trb); ++ + inc_enq(xhci, ring, more_trbs_coming); + } + +--- a/drivers/usb/host/xhci-trace.h ++++ b/drivers/usb/host/xhci-trace.h +@@ -115,34 +115,47 @@ DEFINE_EVENT(xhci_log_ctx, xhci_address_ + TP_ARGS(xhci, ctx, ep_num) + ); + +-DECLARE_EVENT_CLASS(xhci_log_event, +- TP_PROTO(void *trb_va, struct xhci_generic_trb *ev), +- TP_ARGS(trb_va, ev), ++DECLARE_EVENT_CLASS(xhci_log_trb, ++ TP_PROTO(struct xhci_ring *ring, struct xhci_generic_trb *trb), ++ TP_ARGS(ring, trb), + TP_STRUCT__entry( +- __field(void *, va) +- __field(u64, dma) +- __field(u32, status) +- __field(u32, flags) +- __dynamic_array(u8, trb, sizeof(struct xhci_generic_trb)) ++ __field(u32, type) ++ __field(u32, field0) ++ __field(u32, field1) ++ __field(u32, field2) ++ __field(u32, field3) + ), + TP_fast_assign( +- __entry->va = trb_va; +- __entry->dma = ((u64)le32_to_cpu(ev->field[1])) << 32 | +- le32_to_cpu(ev->field[0]); +- __entry->status = le32_to_cpu(ev->field[2]); +- __entry->flags = le32_to_cpu(ev->field[3]); +- memcpy(__get_dynamic_array(trb), trb_va, +- sizeof(struct xhci_generic_trb)); ++ __entry->type = ring->type; ++ __entry->field0 = le32_to_cpu(trb->field[0]); ++ __entry->field1 = le32_to_cpu(trb->field[1]); ++ __entry->field2 = le32_to_cpu(trb->field[2]); ++ __entry->field3 = le32_to_cpu(trb->field[3]); + ), +- TP_printk("\ntrb_dma=@%llx, trb_va=@%p, status=%08x, flags=%08x", +- (unsigned long long) __entry->dma, __entry->va, +- __entry->status, __entry->flags ++ TP_printk("%s: %s", xhci_ring_type_string(__entry->type), ++ xhci_decode_trb(__entry->field0, __entry->field1, ++ __entry->field2, __entry->field3) + ) + ); + +-DEFINE_EVENT(xhci_log_event, xhci_cmd_completion, +- TP_PROTO(void *trb_va, struct xhci_generic_trb *ev), +- TP_ARGS(trb_va, ev) ++DEFINE_EVENT(xhci_log_trb, xhci_handle_event, ++ TP_PROTO(struct xhci_ring *ring, struct xhci_generic_trb *trb), ++ TP_ARGS(ring, trb) ++); ++ ++DEFINE_EVENT(xhci_log_trb, xhci_handle_command, ++ TP_PROTO(struct xhci_ring *ring, struct xhci_generic_trb *trb), ++ TP_ARGS(ring, trb) ++); ++ ++DEFINE_EVENT(xhci_log_trb, xhci_handle_transfer, ++ TP_PROTO(struct xhci_ring *ring, struct xhci_generic_trb *trb), ++ TP_ARGS(ring, trb) ++); ++ ++DEFINE_EVENT(xhci_log_trb, xhci_queue_trb, ++ TP_PROTO(struct xhci_ring *ring, struct xhci_generic_trb *trb), ++ TP_ARGS(ring, trb) + ); + + #endif /* __XHCI_TRACE_H */ +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1199,6 +1199,27 @@ struct xhci_event_cmd { + + /* Address device - disable SetAddress */ + #define TRB_BSR (1<<9) ++ ++/* Configure Endpoint - Deconfigure */ ++#define TRB_DC (1<<9) ++ ++/* Stop Ring - Transfer State Preserve */ ++#define TRB_TSP (1<<9) ++ ++/* Force Event */ ++#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) ++#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) ++ ++/* Set Latency Tolerance Value */ ++#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) ++ ++/* Get Port Bandwidth */ ++#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) ++ ++/* Force Header */ ++#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) ++#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) ++ + enum xhci_setup_dev { + SETUP_CONTEXT_ONLY, + SETUP_CONTEXT_ADDRESS, +@@ -1222,16 +1243,21 @@ enum xhci_setup_dev { + #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) + #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) + ++/* Link TRB specific fields */ ++#define TRB_TC (1<<1) + + /* Port Status Change Event TRB fields */ + /* Port ID - bits 31:24 */ + #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) + ++#define EVENT_DATA (1 << 2) ++ + /* Normal TRB fields */ + /* transfer_len bitmasks - bits 0:16 */ + #define TRB_LEN(p) ((p) & 0x1ffff) + /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ + #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) ++#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) + /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ + #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) + /* Interrupter Target - which MSI-X vector to target the completion event at */ +@@ -1359,6 +1385,80 @@ union xhci_trb { + /* Get NEC firmware revision. */ + #define TRB_NEC_GET_FW 49 + ++static inline const char *xhci_trb_type_string(u8 type) ++{ ++ switch (type) { ++ case TRB_NORMAL: ++ return "Normal"; ++ case TRB_SETUP: ++ return "Setup Stage"; ++ case TRB_DATA: ++ return "Data Stage"; ++ case TRB_STATUS: ++ return "Status Stage"; ++ case TRB_ISOC: ++ return "Isoch"; ++ case TRB_LINK: ++ return "Link"; ++ case TRB_EVENT_DATA: ++ return "Event Data"; ++ case TRB_TR_NOOP: ++ return "No-Op"; ++ case TRB_ENABLE_SLOT: ++ return "Enable Slot Command"; ++ case TRB_DISABLE_SLOT: ++ return "Disable Slot Command"; ++ case TRB_ADDR_DEV: ++ return "Address Device Command"; ++ case TRB_CONFIG_EP: ++ return "Configure Endpoint Command"; ++ case TRB_EVAL_CONTEXT: ++ return "Evaluate Context Command"; ++ case TRB_RESET_EP: ++ return "Reset Endpoint Command"; ++ case TRB_STOP_RING: ++ return "Stop Ring Command"; ++ case TRB_SET_DEQ: ++ return "Set TR Dequeue Pointer Command"; ++ case TRB_RESET_DEV: ++ return "Reset Device Command"; ++ case TRB_FORCE_EVENT: ++ return "Force Event Command"; ++ case TRB_NEG_BANDWIDTH: ++ return "Negotiate Bandwidth Command"; ++ case TRB_SET_LT: ++ return "Set Latency Tolerance Value Command"; ++ case TRB_GET_BW: ++ return "Get Port Bandwidth Command"; ++ case TRB_FORCE_HEADER: ++ return "Force Header Command"; ++ case TRB_CMD_NOOP: ++ return "No-Op Command"; ++ case TRB_TRANSFER: ++ return "Transfer Event"; ++ case TRB_COMPLETION: ++ return "Command Completion Event"; ++ case TRB_PORT_STATUS: ++ return "Port Status Change Event"; ++ case TRB_BANDWIDTH_EVENT: ++ return "Bandwidth Request Event"; ++ case TRB_DOORBELL: ++ return "Doorbell Event"; ++ case TRB_HC_EVENT: ++ return "Host Controller Event"; ++ case TRB_DEV_NOTE: ++ return "Device Notification Event"; ++ case TRB_MFINDEX_WRAP: ++ return "MFINDEX Wrap Event"; ++ case TRB_NEC_CMD_COMP: ++ return "NEC Command Completion Event"; ++ case TRB_NEC_GET_FW: ++ return "NET Get Firmware Revision Command"; ++ default: ++ return "UNKNOWN"; ++ } ++} ++ + #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) + /* Above, but for __le32 types -- can avoid work by swapping constants: */ + #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ +@@ -1435,6 +1535,28 @@ enum xhci_ring_type { + TYPE_EVENT, + }; + ++static inline const char *xhci_ring_type_string(enum xhci_ring_type type) ++{ ++ switch (type) { ++ case TYPE_CTRL: ++ return "CTRL"; ++ case TYPE_ISOC: ++ return "ISOC"; ++ case TYPE_BULK: ++ return "BULK"; ++ case TYPE_INTR: ++ return "INTR"; ++ case TYPE_STREAM: ++ return "STREAM"; ++ case TYPE_COMMAND: ++ return "CMD"; ++ case TYPE_EVENT: ++ return "EVENT"; ++ } ++ ++ return "UNKNOWN"; ++} ++ + struct xhci_ring { + struct xhci_segment *first_seg; + struct xhci_segment *last_seg; +@@ -2034,4 +2156,211 @@ static inline struct xhci_ring *xhci_urb + urb->stream_id); + } + ++static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, ++ u32 field3) ++{ ++ static char str[256]; ++ int type = TRB_FIELD_TO_TYPE(field3); ++ ++ switch (type) { ++ case TRB_LINK: ++ sprintf(str, ++ "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", ++ field1, field0, ++ xhci_trb_comp_code_string(GET_COMP_CODE(field2)), ++ EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), ++ /* Macro decrements 1, maybe it shouldn't?!? */ ++ TRB_TO_EP_INDEX(field3) + 1, ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field3 & EVENT_DATA ? 'E' : 'e', ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_TRANSFER: ++ case TRB_COMPLETION: ++ case TRB_PORT_STATUS: ++ case TRB_BANDWIDTH_EVENT: ++ case TRB_DOORBELL: ++ case TRB_HC_EVENT: ++ case TRB_DEV_NOTE: ++ case TRB_MFINDEX_WRAP: ++ sprintf(str, ++ "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", ++ field1, field0, ++ xhci_trb_comp_code_string(GET_COMP_CODE(field2)), ++ EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), ++ /* Macro decrements 1, maybe it shouldn't?!? */ ++ TRB_TO_EP_INDEX(field3) + 1, ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field3 & EVENT_DATA ? 'E' : 'e', ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ ++ break; ++ case TRB_SETUP: ++ sprintf(str, ++ "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", ++ field0 & 0xff, ++ (field0 & 0xff00) >> 8, ++ (field0 & 0xff000000) >> 24, ++ (field0 & 0xff0000) >> 16, ++ (field1 & 0xff00) >> 8, ++ field1 & 0xff, ++ (field1 & 0xff000000) >> 16 | ++ (field1 & 0xff0000) >> 16, ++ TRB_LEN(field2), GET_TD_SIZE(field2), ++ GET_INTR_TARGET(field2), ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field3 & TRB_BEI ? 'B' : 'b', ++ field3 & TRB_IDT ? 'I' : 'i', ++ field3 & TRB_IOC ? 'I' : 'i', ++ field3 & TRB_CHAIN ? 'C' : 'c', ++ field3 & TRB_NO_SNOOP ? 'S' : 's', ++ field3 & TRB_ISP ? 'I' : 'i', ++ field3 & TRB_ENT ? 'E' : 'e', ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_NORMAL: ++ case TRB_DATA: ++ case TRB_STATUS: ++ case TRB_ISOC: ++ case TRB_EVENT_DATA: ++ case TRB_TR_NOOP: ++ sprintf(str, ++ "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", ++ field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), ++ GET_INTR_TARGET(field2), ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field3 & TRB_BEI ? 'B' : 'b', ++ field3 & TRB_IDT ? 'I' : 'i', ++ field3 & TRB_IOC ? 'I' : 'i', ++ field3 & TRB_CHAIN ? 'C' : 'c', ++ field3 & TRB_NO_SNOOP ? 'S' : 's', ++ field3 & TRB_ISP ? 'I' : 'i', ++ field3 & TRB_ENT ? 'E' : 'e', ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ ++ case TRB_CMD_NOOP: ++ case TRB_ENABLE_SLOT: ++ sprintf(str, ++ "%s: flags %c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_DISABLE_SLOT: ++ case TRB_NEG_BANDWIDTH: ++ sprintf(str, ++ "%s: slot %d flags %c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ TRB_TO_SLOT_ID(field3), ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_ADDR_DEV: ++ sprintf(str, ++ "%s: ctx %08x%08x slot %d flags %c:%c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field1, field0, ++ TRB_TO_SLOT_ID(field3), ++ field3 & TRB_BSR ? 'B' : 'b', ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_CONFIG_EP: ++ sprintf(str, ++ "%s: ctx %08x%08x slot %d flags %c:%c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field1, field0, ++ TRB_TO_SLOT_ID(field3), ++ field3 & TRB_DC ? 'D' : 'd', ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_EVAL_CONTEXT: ++ sprintf(str, ++ "%s: ctx %08x%08x slot %d flags %c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field1, field0, ++ TRB_TO_SLOT_ID(field3), ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_RESET_EP: ++ sprintf(str, ++ "%s: ctx %08x%08x slot %d ep %d flags %c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field1, field0, ++ TRB_TO_SLOT_ID(field3), ++ /* Macro decrements 1, maybe it shouldn't?!? */ ++ TRB_TO_EP_INDEX(field3) + 1, ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_STOP_RING: ++ sprintf(str, ++ "%s: slot %d sp %d ep %d flags %c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ TRB_TO_SLOT_ID(field3), ++ TRB_TO_SUSPEND_PORT(field3), ++ /* Macro decrements 1, maybe it shouldn't?!? */ ++ TRB_TO_EP_INDEX(field3) + 1, ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_SET_DEQ: ++ sprintf(str, ++ "%s: deq %08x%08x stream %d slot %d ep %d flags %c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field1, field0, ++ TRB_TO_STREAM_ID(field2), ++ TRB_TO_SLOT_ID(field3), ++ /* Macro decrements 1, maybe it shouldn't?!? */ ++ TRB_TO_EP_INDEX(field3) + 1, ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_RESET_DEV: ++ sprintf(str, ++ "%s: slot %d flags %c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ TRB_TO_SLOT_ID(field3), ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_FORCE_EVENT: ++ sprintf(str, ++ "%s: event %08x%08x vf intr %d vf id %d flags %c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field1, field0, ++ TRB_TO_VF_INTR_TARGET(field2), ++ TRB_TO_VF_ID(field3), ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_SET_LT: ++ sprintf(str, ++ "%s: belt %d flags %c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ TRB_TO_BELT(field3), ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_GET_BW: ++ sprintf(str, ++ "%s: ctx %08x%08x slot %d speed %d flags %c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field1, field0, ++ TRB_TO_SLOT_ID(field3), ++ TRB_TO_DEV_SPEED(field3), ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_FORCE_HEADER: ++ sprintf(str, ++ "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field2, field1, field0 & 0xffffffe0, ++ TRB_TO_PACKET_TYPE(field0), ++ TRB_TO_ROOTHUB_PORT(field3), ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ default: ++ sprintf(str, ++ "type '%s' -> raw %08x %08x %08x %08x", ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field0, field1, field2, field3); ++ } ++ ++ return str; ++} ++ ++ + #endif /* __LINUX_XHCI_HCD_H */ diff --git a/patches.renesas/0207-usb-host-xhci-add-urb_enqueue-dequeue-giveback-trace.patch b/patches.renesas/0207-usb-host-xhci-add-urb_enqueue-dequeue-giveback-trace.patch new file mode 100644 index 0000000000000..9994ecbe68cbd --- /dev/null +++ b/patches.renesas/0207-usb-host-xhci-add-urb_enqueue-dequeue-giveback-trace.patch @@ -0,0 +1,130 @@ +From dc2a19b1b1626287d9fd4949a440b1b2f668bb73 Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:20 +0200 +Subject: [PATCH 207/255] usb: host: xhci: add urb_enqueue/dequeue/giveback + tracers + +These three new tracers will help us tie TRBs into URBs by *also* +looking into URB lifetime. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 5abdc2e6e12ff040a218dc807be4c4d9866b265f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 1 + drivers/usb/host/xhci-trace.h | 70 ++++++++++++++++++++++++++++++++++++++++++ + drivers/usb/host/xhci.c | 5 +++ + 3 files changed, 76 insertions(+) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -642,6 +642,7 @@ static void xhci_giveback_urb_in_irq(str + usb_hcd_unlink_urb_from_ep(hcd, urb); + spin_unlock(&xhci->lock); + usb_hcd_giveback_urb(hcd, urb, status); ++ trace_xhci_urb_giveback(urb); + spin_lock(&xhci->lock); + } + +--- a/drivers/usb/host/xhci-trace.h ++++ b/drivers/usb/host/xhci-trace.h +@@ -158,6 +158,76 @@ DEFINE_EVENT(xhci_log_trb, xhci_queue_tr + TP_ARGS(ring, trb) + ); + ++DECLARE_EVENT_CLASS(xhci_log_urb, ++ TP_PROTO(struct urb *urb), ++ TP_ARGS(urb), ++ TP_STRUCT__entry( ++ __field(void *, urb) ++ __field(unsigned int, pipe) ++ __field(unsigned int, stream) ++ __field(int, status) ++ __field(unsigned int, flags) ++ __field(int, num_mapped_sgs) ++ __field(int, num_sgs) ++ __field(int, length) ++ __field(int, actual) ++ __field(int, epnum) ++ __field(int, dir_in) ++ __field(int, type) ++ ), ++ TP_fast_assign( ++ __entry->urb = urb; ++ __entry->pipe = urb->pipe; ++ __entry->stream = urb->stream_id; ++ __entry->status = urb->status; ++ __entry->flags = urb->transfer_flags; ++ __entry->num_mapped_sgs = urb->num_mapped_sgs; ++ __entry->num_sgs = urb->num_sgs; ++ __entry->length = urb->transfer_buffer_length; ++ __entry->actual = urb->actual_length; ++ __entry->epnum = usb_endpoint_num(&urb->ep->desc); ++ __entry->dir_in = usb_endpoint_dir_in(&urb->ep->desc); ++ __entry->type = usb_endpoint_type(&urb->ep->desc); ++ ), ++ TP_printk("ep%d%s-%s: urb %p pipe %u length %d/%d sgs %d/%d stream %d flags %08x", ++ __entry->epnum, __entry->dir_in ? "in" : "out", ++ ({ char *s; ++ switch (__entry->type) { ++ case USB_ENDPOINT_XFER_INT: ++ s = "intr"; ++ break; ++ case USB_ENDPOINT_XFER_CONTROL: ++ s = "control"; ++ break; ++ case USB_ENDPOINT_XFER_BULK: ++ s = "bulk"; ++ break; ++ case USB_ENDPOINT_XFER_ISOC: ++ s = "isoc"; ++ break; ++ default: ++ s = "UNKNOWN"; ++ } s; }), __entry->urb, __entry->pipe, __entry->actual, ++ __entry->length, __entry->num_mapped_sgs, ++ __entry->num_sgs, __entry->stream, __entry->flags ++ ) ++); ++ ++DEFINE_EVENT(xhci_log_urb, xhci_urb_enqueue, ++ TP_PROTO(struct urb *urb), ++ TP_ARGS(urb) ++); ++ ++DEFINE_EVENT(xhci_log_urb, xhci_urb_giveback, ++ TP_PROTO(struct urb *urb), ++ TP_ARGS(urb) ++); ++ ++DEFINE_EVENT(xhci_log_urb, xhci_urb_dequeue, ++ TP_PROTO(struct urb *urb), ++ TP_ARGS(urb) ++); ++ + #endif /* __XHCI_TRACE_H */ + + /* this part must be outside header guard */ +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1389,6 +1389,8 @@ int xhci_urb_enqueue(struct usb_hcd *hcd + urb_priv->td_cnt = 0; + urb->hcpriv = urb_priv; + ++ trace_xhci_urb_enqueue(urb); ++ + if (usb_endpoint_xfer_control(&urb->ep->desc)) { + /* Check to see if the max packet size for the default control + * endpoint changed during FS device enumeration +@@ -1515,6 +1517,9 @@ int xhci_urb_dequeue(struct usb_hcd *hcd + + xhci = hcd_to_xhci(hcd); + spin_lock_irqsave(&xhci->lock, flags); ++ ++ trace_xhci_urb_dequeue(urb); ++ + /* Make sure the URB hasn't completed or been unlinked already */ + ret = usb_hcd_check_unlink_urb(hcd, urb, status); + if (ret || !urb->hcpriv) diff --git a/patches.renesas/0208-usb-host-xhci-convert-several-if-to-a-single-switch-.patch b/patches.renesas/0208-usb-host-xhci-convert-several-if-to-a-single-switch-.patch new file mode 100644 index 0000000000000..cab446ebcf733 --- /dev/null +++ b/patches.renesas/0208-usb-host-xhci-convert-several-if-to-a-single-switch-.patch @@ -0,0 +1,42 @@ +From e579a27a32a7da75d8ea58d8e2919cfa724200f6 Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:21 +0200 +Subject: [PATCH 208/255] usb: host: xhci: convert several if() to a single + switch statement + +when getting endpoint type, a switch statement looks +better than a series of if () branches. There are no +functional changes with this patch, cleanup only. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit c0e625c41abbcc12c4981823889e3dc126252fb5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-mem.c | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -1414,14 +1414,16 @@ static u32 xhci_get_endpoint_type(struct + + in = usb_endpoint_dir_in(&ep->desc); + +- if (usb_endpoint_xfer_control(&ep->desc)) ++ switch (usb_endpoint_type(&ep->desc)) { ++ case USB_ENDPOINT_XFER_CONTROL: + return CTRL_EP; +- if (usb_endpoint_xfer_bulk(&ep->desc)) ++ case USB_ENDPOINT_XFER_BULK: + return in ? BULK_IN_EP : BULK_OUT_EP; +- if (usb_endpoint_xfer_isoc(&ep->desc)) ++ case USB_ENDPOINT_XFER_ISOC: + return in ? ISOC_IN_EP : ISOC_OUT_EP; +- if (usb_endpoint_xfer_int(&ep->desc)) ++ case USB_ENDPOINT_XFER_INT: + return in ? INT_IN_EP : INT_OUT_EP; ++ } + return 0; + } + diff --git a/patches.renesas/0209-usb-host-xhci-add-xhci_virt_device-tracer.patch b/patches.renesas/0209-usb-host-xhci-add-xhci_virt_device-tracer.patch new file mode 100644 index 0000000000000..edd0b0f107e7f --- /dev/null +++ b/patches.renesas/0209-usb-host-xhci-add-xhci_virt_device-tracer.patch @@ -0,0 +1,138 @@ +From db7e3a1af9f2c9262e7709904fa331c0ca508a3d Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:23 +0200 +Subject: [PATCH 209/255] usb: host: xhci: add xhci_virt_device tracer + +Let's start tracing at least part of an xhci_virt_device lifetime. We +might want to extend this tracepoint class later, but for now it already +exposes quite a bit of valuable information. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit a711edeeb1a1e80fb8626ee28acc15f084dcb107) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-hub.c | 2 + + drivers/usb/host/xhci-mem.c | 7 +++++ + drivers/usb/host/xhci-trace.h | 57 ++++++++++++++++++++++++++++++++++++++++++ + drivers/usb/host/xhci.c | 1 + 4 files changed, 67 insertions(+) + +--- a/drivers/usb/host/xhci-hub.c ++++ b/drivers/usb/host/xhci-hub.c +@@ -389,6 +389,8 @@ static int xhci_stop_device(struct xhci_ + if (!virt_dev) + return -ENODEV; + ++ trace_xhci_stop_device(virt_dev); ++ + cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); + if (!cmd) { + xhci_dbg(xhci, "Couldn't allocate command structure.\n"); +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -936,6 +936,9 @@ void xhci_free_virt_device(struct xhci_h + return; + + dev = xhci->devs[slot_id]; ++ ++ trace_xhci_free_virt_device(dev); ++ + xhci->dcbaa->dev_context_ptrs[slot_id] = 0; + if (!dev) + return; +@@ -1075,6 +1078,8 @@ int xhci_alloc_virt_device(struct xhci_h + &xhci->dcbaa->dev_context_ptrs[slot_id], + le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id])); + ++ trace_xhci_alloc_virt_device(dev); ++ + return 1; + fail: + xhci_free_virt_device(xhci, slot_id); +@@ -1249,6 +1254,8 @@ int xhci_setup_addressable_virt_dev(stru + ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma | + dev->eps[0].ring->cycle_state); + ++ trace_xhci_setup_addressable_virt_device(dev); ++ + /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ + + return 0; +--- a/drivers/usb/host/xhci-trace.h ++++ b/drivers/usb/host/xhci-trace.h +@@ -158,6 +158,63 @@ DEFINE_EVENT(xhci_log_trb, xhci_queue_tr + TP_ARGS(ring, trb) + ); + ++DECLARE_EVENT_CLASS(xhci_log_virt_dev, ++ TP_PROTO(struct xhci_virt_device *vdev), ++ TP_ARGS(vdev), ++ TP_STRUCT__entry( ++ __field(void *, vdev) ++ __field(unsigned long long, out_ctx) ++ __field(unsigned long long, in_ctx) ++ __field(int, devnum) ++ __field(int, state) ++ __field(int, speed) ++ __field(u8, portnum) ++ __field(u8, level) ++ __field(int, slot_id) ++ ), ++ TP_fast_assign( ++ __entry->vdev = vdev; ++ __entry->in_ctx = (unsigned long long) vdev->in_ctx->dma; ++ __entry->out_ctx = (unsigned long long) vdev->out_ctx->dma; ++ __entry->devnum = vdev->udev->devnum; ++ __entry->state = vdev->udev->state; ++ __entry->speed = vdev->udev->speed; ++ __entry->portnum = vdev->udev->portnum; ++ __entry->level = vdev->udev->level; ++ __entry->slot_id = vdev->udev->slot_id; ++ ), ++ TP_printk("vdev %p ctx %llx | %llx num %d state %d speed %d port %d level %d slot %d", ++ __entry->vdev, __entry->in_ctx, __entry->out_ctx, ++ __entry->devnum, __entry->state, __entry->speed, ++ __entry->portnum, __entry->level, __entry->slot_id ++ ) ++); ++ ++DEFINE_EVENT(xhci_log_virt_dev, xhci_alloc_virt_device, ++ TP_PROTO(struct xhci_virt_device *vdev), ++ TP_ARGS(vdev) ++); ++ ++DEFINE_EVENT(xhci_log_virt_dev, xhci_free_virt_device, ++ TP_PROTO(struct xhci_virt_device *vdev), ++ TP_ARGS(vdev) ++); ++ ++DEFINE_EVENT(xhci_log_virt_dev, xhci_setup_device, ++ TP_PROTO(struct xhci_virt_device *vdev), ++ TP_ARGS(vdev) ++); ++ ++DEFINE_EVENT(xhci_log_virt_dev, xhci_setup_addressable_virt_device, ++ TP_PROTO(struct xhci_virt_device *vdev), ++ TP_ARGS(vdev) ++); ++ ++DEFINE_EVENT(xhci_log_virt_dev, xhci_stop_device, ++ TP_PROTO(struct xhci_virt_device *vdev), ++ TP_ARGS(vdev) ++); ++ + DECLARE_EVENT_CLASS(xhci_log_urb, + TP_PROTO(struct urb *urb), + TP_ARGS(urb), +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -3854,6 +3854,7 @@ static int xhci_setup_device(struct usb_ + le32_to_cpu(slot_ctx->dev_info) >> 27); + + spin_lock_irqsave(&xhci->lock, flags); ++ trace_xhci_setup_device(virt_dev); + ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma, + udev->slot_id, setup); + if (ret) { diff --git a/patches.renesas/0210-xhci-rename-size-variable-to-num_tds.patch b/patches.renesas/0210-xhci-rename-size-variable-to-num_tds.patch new file mode 100644 index 0000000000000..60984594032cd --- /dev/null +++ b/patches.renesas/0210-xhci-rename-size-variable-to-num_tds.patch @@ -0,0 +1,67 @@ +From d03f4ba30be03a65d4e55b5e432ba4c35117a91c Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:24 +0200 +Subject: [PATCH 210/255] xhci: rename size variable to num_tds + +No functinal changes. +num_tds describes the number of transfer descriptor better than "size" + +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit e6f7caa3de7a6a093e23d2722e45676a6e886e4c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1343,7 +1343,7 @@ int xhci_urb_enqueue(struct usb_hcd *hcd + int ret = 0; + unsigned int slot_id, ep_index; + struct urb_priv *urb_priv; +- int size, i; ++ int num_tds, i; + + if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, + true, true, __func__) <= 0) +@@ -1360,32 +1360,32 @@ int xhci_urb_enqueue(struct usb_hcd *hcd + } + + if (usb_endpoint_xfer_isoc(&urb->ep->desc)) +- size = urb->number_of_packets; ++ num_tds = urb->number_of_packets; + else if (usb_endpoint_is_bulk_out(&urb->ep->desc) && + urb->transfer_buffer_length > 0 && + urb->transfer_flags & URB_ZERO_PACKET && + !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc))) +- size = 2; ++ num_tds = 2; + else +- size = 1; ++ num_tds = 1; + + urb_priv = kzalloc(sizeof(struct urb_priv) + +- size * sizeof(struct xhci_td *), mem_flags); ++ num_tds * sizeof(struct xhci_td *), mem_flags); + if (!urb_priv) + return -ENOMEM; + +- buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags); ++ buffer = kzalloc(num_tds * sizeof(struct xhci_td), mem_flags); + if (!buffer) { + kfree(urb_priv); + return -ENOMEM; + } + +- for (i = 0; i < size; i++) { ++ for (i = 0; i < num_tds; i++) { + urb_priv->td[i] = buffer; + buffer++; + } + +- urb_priv->length = size; ++ urb_priv->length = num_tds; + urb_priv->td_cnt = 0; + urb->hcpriv = urb_priv; + diff --git a/patches.renesas/0211-xhci-Rename-variables-related-to-transfer-descritpor.patch b/patches.renesas/0211-xhci-Rename-variables-related-to-transfer-descritpor.patch new file mode 100644 index 0000000000000..a2696d348b587 --- /dev/null +++ b/patches.renesas/0211-xhci-Rename-variables-related-to-transfer-descritpor.patch @@ -0,0 +1,128 @@ +From fd64265d9c1d9b5d14252e1f15e7cfa9ce9c47cf Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:25 +0200 +Subject: [PATCH 211/255] xhci: Rename variables related to transfer + descritpors + +urb_priv structure has a count on how many TDs the +URB contains, and how many of those TD's we have handled. + +rename: +length -> num_tds +td_cnt -> num_tds_done + +No functional changes + +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 9ef7fbbb4fdfb857e606a9fd550faa8011cce5e2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 10 +++++----- + drivers/usb/host/xhci.c | 14 +++++++------- + drivers/usb/host/xhci.h | 4 ++-- + 3 files changed, 14 insertions(+), 14 deletions(-) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -119,14 +119,14 @@ static bool last_td_in_urb(struct xhci_t + { + struct urb_priv *urb_priv = td->urb->hcpriv; + +- return urb_priv->td_cnt == urb_priv->length; ++ return urb_priv->num_tds_done == urb_priv->num_tds; + } + + static void inc_td_cnt(struct urb *urb) + { + struct urb_priv *urb_priv = urb->hcpriv; + +- urb_priv->td_cnt++; ++ urb_priv->num_tds_done++; + } + + static void trb_to_noop(union xhci_trb *trb, u32 noop_type) +@@ -2058,7 +2058,7 @@ static int process_isoc_td(struct xhci_h + ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); + trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); + urb_priv = td->urb->hcpriv; +- idx = urb_priv->td_cnt; ++ idx = urb_priv->num_tds_done; + frame = &td->urb->iso_frame_desc[idx]; + requested = frame->length; + remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); +@@ -2137,7 +2137,7 @@ static int skip_isoc_td(struct xhci_hcd + + ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); + urb_priv = td->urb->hcpriv; +- idx = urb_priv->td_cnt; ++ idx = urb_priv->num_tds_done; + frame = &td->urb->iso_frame_desc[idx]; + + /* The transfer is partly done. */ +@@ -3134,7 +3134,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd * + urb_priv = urb->hcpriv; + + /* Deal with URB_ZERO_PACKET - need one more td/trb */ +- if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->length > 1) ++ if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1) + need_zero_pkt = true; + + td = urb_priv->td[0]; +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1385,8 +1385,8 @@ int xhci_urb_enqueue(struct usb_hcd *hcd + buffer++; + } + +- urb_priv->length = num_tds; +- urb_priv->td_cnt = 0; ++ urb_priv->num_tds = num_tds; ++ urb_priv->num_tds_done = 0; + urb->hcpriv = urb_priv; + + trace_xhci_urb_enqueue(urb); +@@ -1529,8 +1529,8 @@ int xhci_urb_dequeue(struct usb_hcd *hcd + xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, + "HW died, freeing TD."); + urb_priv = urb->hcpriv; +- for (i = urb_priv->td_cnt; +- i < urb_priv->length && xhci->devs[urb->dev->slot_id]; ++ for (i = urb_priv->num_tds_done; ++ i < urb_priv->num_tds && xhci->devs[urb->dev->slot_id]; + i++) { + td = urb_priv->td[i]; + if (!list_empty(&td->td_list)) +@@ -1555,8 +1555,8 @@ int xhci_urb_dequeue(struct usb_hcd *hcd + } + + urb_priv = urb->hcpriv; +- i = urb_priv->td_cnt; +- if (i < urb_priv->length) ++ i = urb_priv->num_tds_done; ++ if (i < urb_priv->num_tds) + xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, + "Cancel URB %p, dev %s, ep 0x%x, " + "starting at offset 0x%llx", +@@ -1566,7 +1566,7 @@ int xhci_urb_dequeue(struct usb_hcd *hcd + urb_priv->td[i]->start_seg, + urb_priv->td[i]->first_trb)); + +- for (; i < urb_priv->length; i++) { ++ for (; i < urb_priv->num_tds; i++) { + td = urb_priv->td[i]; + list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); + } +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1608,8 +1608,8 @@ struct xhci_scratchpad { + }; + + struct urb_priv { +- int length; +- int td_cnt; ++ int num_tds; ++ int num_tds_done; + struct xhci_td *td[0]; + }; + diff --git a/patches.renesas/0212-xhci-simplify-how-we-store-TDs-in-urb-private-data.patch b/patches.renesas/0212-xhci-simplify-how-we-store-TDs-in-urb-private-data.patch new file mode 100644 index 0000000000000..804b78eaef427 --- /dev/null +++ b/patches.renesas/0212-xhci-simplify-how-we-store-TDs-in-urb-private-data.patch @@ -0,0 +1,193 @@ +From 16082b87853b93a25922e59440045f57fb5df292 Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:26 +0200 +Subject: [PATCH 212/255] xhci: simplify how we store TDs in urb private data + +Instead of storing a zero length array of td pointers, and then +allocate memory both for the td pointer array and the td's, just +use a zero length array of actual td's in urb private data. + +old: + +struct urb_priv { + struct xhci_td *td[0] +} + +new: + +struct urb_priv { + struct xhci_td td[0] +} + +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 7e64b0373af50fa46d3bf441f1c079615bbdf77f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-mem.c | 5 +---- + drivers/usb/host/xhci-ring.c | 20 ++++++++++---------- + drivers/usb/host/xhci.c | 24 ++++++------------------ + drivers/usb/host/xhci.h | 2 +- + 4 files changed, 18 insertions(+), 33 deletions(-) + +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -1828,10 +1828,7 @@ struct xhci_command *xhci_alloc_command( + + void xhci_urb_free_priv(struct urb_priv *urb_priv) + { +- if (urb_priv) { +- kfree(urb_priv->td[0]); +- kfree(urb_priv); +- } ++ kfree(urb_priv); + } + + void xhci_free_command(struct xhci_hcd *xhci, +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -2841,7 +2841,7 @@ static int prepare_transfer(struct xhci_ + return ret; + + urb_priv = urb->hcpriv; +- td = urb_priv->td[td_index]; ++ td = &urb_priv->td[td_index]; + + INIT_LIST_HEAD(&td->td_list); + INIT_LIST_HEAD(&td->cancelled_td_list); +@@ -3137,7 +3137,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd * + if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1) + need_zero_pkt = true; + +- td = urb_priv->td[0]; ++ td = &urb_priv->td[0]; + + /* + * Don't give the first TRB to the hardware (by toggling the cycle bit) +@@ -3230,7 +3230,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd * + ret = prepare_transfer(xhci, xhci->devs[slot_id], + ep_index, urb->stream_id, + 1, urb, 1, mem_flags); +- urb_priv->td[1]->last_trb = ring->enqueue; ++ urb_priv->td[1].last_trb = ring->enqueue; + field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; + queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); + } +@@ -3282,7 +3282,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd * + return ret; + + urb_priv = urb->hcpriv; +- td = urb_priv->td[0]; ++ td = &urb_priv->td[0]; + + /* + * Don't give the first TRB to the hardware (by toggling the cycle bit) +@@ -3570,7 +3570,7 @@ static int xhci_queue_isoc_tx(struct xhc + return ret; + goto cleanup; + } +- td = urb_priv->td[i]; ++ td = &urb_priv->td[i]; + + /* use SIA as default, if frame id is used overwrite it */ + sia_frame_id = TRB_SIA; +@@ -3677,20 +3677,20 @@ cleanup: + /* Clean up a partially enqueued isoc transfer. */ + + for (i--; i >= 0; i--) +- list_del_init(&urb_priv->td[i]->td_list); ++ list_del_init(&urb_priv->td[i].td_list); + + /* Use the first TD as a temporary variable to turn the TDs we've queued + * into No-ops with a software-owned cycle bit. That way the hardware + * won't accidentally start executing bogus TDs when we partially + * overwrite them. td->first_trb and td->start_seg are already set. + */ +- urb_priv->td[0]->last_trb = ep_ring->enqueue; ++ urb_priv->td[0].last_trb = ep_ring->enqueue; + /* Every TRB except the first & last will have its cycle bit flipped. */ +- td_to_noop(xhci, ep_ring, urb_priv->td[0], true); ++ td_to_noop(xhci, ep_ring, &urb_priv->td[0], true); + + /* Reset the ring enqueue back to the first TRB and its cycle bit. */ +- ep_ring->enqueue = urb_priv->td[0]->first_trb; +- ep_ring->enq_seg = urb_priv->td[0]->start_seg; ++ ep_ring->enqueue = urb_priv->td[0].first_trb; ++ ep_ring->enq_seg = urb_priv->td[0].start_seg; + ep_ring->cycle_state = start_cycle; + ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; + usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1338,12 +1338,11 @@ command_cleanup: + int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); +- struct xhci_td *buffer; + unsigned long flags; + int ret = 0; + unsigned int slot_id, ep_index; + struct urb_priv *urb_priv; +- int num_tds, i; ++ int num_tds; + + if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, + true, true, __func__) <= 0) +@@ -1370,21 +1369,10 @@ int xhci_urb_enqueue(struct usb_hcd *hcd + num_tds = 1; + + urb_priv = kzalloc(sizeof(struct urb_priv) + +- num_tds * sizeof(struct xhci_td *), mem_flags); ++ num_tds * sizeof(struct xhci_td), mem_flags); + if (!urb_priv) + return -ENOMEM; + +- buffer = kzalloc(num_tds * sizeof(struct xhci_td), mem_flags); +- if (!buffer) { +- kfree(urb_priv); +- return -ENOMEM; +- } +- +- for (i = 0; i < num_tds; i++) { +- urb_priv->td[i] = buffer; +- buffer++; +- } +- + urb_priv->num_tds = num_tds; + urb_priv->num_tds_done = 0; + urb->hcpriv = urb_priv; +@@ -1532,7 +1520,7 @@ int xhci_urb_dequeue(struct usb_hcd *hcd + for (i = urb_priv->num_tds_done; + i < urb_priv->num_tds && xhci->devs[urb->dev->slot_id]; + i++) { +- td = urb_priv->td[i]; ++ td = &urb_priv->td[i]; + if (!list_empty(&td->td_list)) + list_del_init(&td->td_list); + if (!list_empty(&td->cancelled_td_list)) +@@ -1563,11 +1551,11 @@ int xhci_urb_dequeue(struct usb_hcd *hcd + urb, urb->dev->devpath, + urb->ep->desc.bEndpointAddress, + (unsigned long long) xhci_trb_virt_to_dma( +- urb_priv->td[i]->start_seg, +- urb_priv->td[i]->first_trb)); ++ urb_priv->td[i].start_seg, ++ urb_priv->td[i].first_trb)); + + for (; i < urb_priv->num_tds; i++) { +- td = urb_priv->td[i]; ++ td = &urb_priv->td[i]; + list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); + } + +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1610,7 +1610,7 @@ struct xhci_scratchpad { + struct urb_priv { + int num_tds; + int num_tds_done; +- struct xhci_td *td[0]; ++ struct xhci_td td[0]; + }; + + /* diff --git a/patches.renesas/0213-xhci-refactor-xhci_urb_enqueue.patch b/patches.renesas/0213-xhci-refactor-xhci_urb_enqueue.patch new file mode 100644 index 0000000000000..1589d15a9daaf --- /dev/null +++ b/patches.renesas/0213-xhci-refactor-xhci_urb_enqueue.patch @@ -0,0 +1,141 @@ +From 5e5a6008f3024ed20a17fce204e5167555b0aa41 Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Mon, 23 Jan 2017 14:20:27 +0200 +Subject: [PATCH 213/255] xhci: refactor xhci_urb_enqueue + +Use switch instead of several if statements + +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 6969408de2681e1f9dfaed0b311d067ce3c75474) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.c | 93 +++++++++++++++++++----------------------------- + 1 file changed, 37 insertions(+), 56 deletions(-) + +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1340,7 +1340,7 @@ int xhci_urb_enqueue(struct usb_hcd *hcd + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + unsigned long flags; + int ret = 0; +- unsigned int slot_id, ep_index; ++ unsigned int slot_id, ep_index, ep_state; + struct urb_priv *urb_priv; + int num_tds; + +@@ -1354,8 +1354,7 @@ int xhci_urb_enqueue(struct usb_hcd *hcd + if (!HCD_HW_ACCESSIBLE(hcd)) { + if (!in_interrupt()) + xhci_dbg(xhci, "urb submitted during PCI suspend\n"); +- ret = -ESHUTDOWN; +- goto exit; ++ return -ESHUTDOWN; + } + + if (usb_endpoint_xfer_isoc(&urb->ep->desc)) +@@ -1392,69 +1391,51 @@ int xhci_urb_enqueue(struct usb_hcd *hcd + return ret; + } + } ++ } + +- /* We have a spinlock and interrupts disabled, so we must pass +- * atomic context to this function, which may allocate memory. +- */ +- spin_lock_irqsave(&xhci->lock, flags); +- if (xhci->xhc_state & XHCI_STATE_DYING) +- goto dying; ++ spin_lock_irqsave(&xhci->lock, flags); ++ ++ if (xhci->xhc_state & XHCI_STATE_DYING) { ++ xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n", ++ urb->ep->desc.bEndpointAddress, urb); ++ ret = -ESHUTDOWN; ++ goto free_priv; ++ } ++ ++ switch (usb_endpoint_type(&urb->ep->desc)) { ++ ++ case USB_ENDPOINT_XFER_CONTROL: + ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb, +- slot_id, ep_index); +- if (ret) +- goto free_priv; +- spin_unlock_irqrestore(&xhci->lock, flags); +- } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) { +- spin_lock_irqsave(&xhci->lock, flags); +- if (xhci->xhc_state & XHCI_STATE_DYING) +- goto dying; +- if (xhci->devs[slot_id]->eps[ep_index].ep_state & +- EP_GETTING_STREAMS) { +- xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep " +- "is transitioning to using streams.\n"); +- ret = -EINVAL; +- } else if (xhci->devs[slot_id]->eps[ep_index].ep_state & +- EP_GETTING_NO_STREAMS) { +- xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep " +- "is transitioning to " +- "not having streams.\n"); ++ slot_id, ep_index); ++ break; ++ case USB_ENDPOINT_XFER_BULK: ++ ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; ++ if (ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) { ++ xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n", ++ ep_state); + ret = -EINVAL; +- } else { +- ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, +- slot_id, ep_index); ++ break; + } +- if (ret) +- goto free_priv; +- spin_unlock_irqrestore(&xhci->lock, flags); +- } else if (usb_endpoint_xfer_int(&urb->ep->desc)) { +- spin_lock_irqsave(&xhci->lock, flags); +- if (xhci->xhc_state & XHCI_STATE_DYING) +- goto dying; ++ ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, ++ slot_id, ep_index); ++ break; ++ ++ ++ case USB_ENDPOINT_XFER_INT: + ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb, + slot_id, ep_index); +- if (ret) +- goto free_priv; +- spin_unlock_irqrestore(&xhci->lock, flags); +- } else { +- spin_lock_irqsave(&xhci->lock, flags); +- if (xhci->xhc_state & XHCI_STATE_DYING) +- goto dying; ++ break; ++ ++ case USB_ENDPOINT_XFER_ISOC: + ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb, + slot_id, ep_index); +- if (ret) +- goto free_priv; +- spin_unlock_irqrestore(&xhci->lock, flags); + } +-exit: +- return ret; +-dying: +- xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for " +- "non-responsive xHCI host.\n", +- urb->ep->desc.bEndpointAddress, urb); +- ret = -ESHUTDOWN; ++ ++ if (ret) { + free_priv: +- xhci_urb_free_priv(urb_priv); +- urb->hcpriv = NULL; ++ xhci_urb_free_priv(urb_priv); ++ urb->hcpriv = NULL; ++ } + spin_unlock_irqrestore(&xhci->lock, flags); + return ret; + } diff --git a/patches.renesas/0214-xhci-plat-Register-shutdown-for-xhci_plat.patch b/patches.renesas/0214-xhci-plat-Register-shutdown-for-xhci_plat.patch new file mode 100644 index 0000000000000..b9f4acf5e6708 --- /dev/null +++ b/patches.renesas/0214-xhci-plat-Register-shutdown-for-xhci_plat.patch @@ -0,0 +1,28 @@ +From b17ecaa4b1913acf963fb1d36f871c3fa17ba528 Mon Sep 17 00:00:00 2001 +From: Adam Wallis <awallis@codeaurora.org> +Date: Tue, 28 Mar 2017 15:55:28 +0300 +Subject: [PATCH 214/255] xhci: plat: Register shutdown for xhci_plat + +Shutdown should be called for xhci_plat devices especially for +situations where kexec might be used by stopping DMA +transactions. + +Signed-off-by: Adam Wallis <awallis@codeaurora.org> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit b07c12517f2aed0add8ce18146bb426b14099392) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-plat.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -344,6 +344,7 @@ MODULE_DEVICE_TABLE(acpi, usb_xhci_acpi_ + static struct platform_driver usb_xhci_driver = { + .probe = xhci_plat_probe, + .remove = xhci_plat_remove, ++ .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "xhci-hcd", + .pm = DEV_PM_OPS, diff --git a/patches.renesas/0215-xhci-Set-URB-actual-length-for-stopped-control-trans.patch b/patches.renesas/0215-xhci-Set-URB-actual-length-for-stopped-control-trans.patch new file mode 100644 index 0000000000000..f2f63485b5545 --- /dev/null +++ b/patches.renesas/0215-xhci-Set-URB-actual-length-for-stopped-control-trans.patch @@ -0,0 +1,37 @@ +From a45cdd1c2e0fc7ad3a81d25a3603c42f2363460d Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Tue, 28 Mar 2017 15:55:29 +0300 +Subject: [PATCH 215/255] xhci: Set URB actual length for stopped control + transfers + +A control transfer that stopped at the status stage incorrectly +warned about a "unexpected TRB Type 4", and did not set the +transferred actual_length for the URB. + +The URB actual_length for control transfers should contain the +bytes transferred in the data stage. + +Bytes of a partially sent setup stage and missing bytes from +status stage should be left out. + +Cc: <stable@vger.kernel.org> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 0ab2881a406b9fd46224a3e8253bbc0141b4f844) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -1992,6 +1992,9 @@ static int process_ctrl_td(struct xhci_h + case TRB_NORMAL: + td->urb->actual_length = requested - remaining; + goto finish_td; ++ case TRB_STATUS: ++ td->urb->actual_length = requested; ++ goto finish_td; + default: + xhci_warn(xhci, "WARN: unexpected TRB Type %d\n", + trb_type); diff --git a/patches.renesas/0216-xhci-Manually-give-back-cancelled-URB-if-we-can-t-qu.patch b/patches.renesas/0216-xhci-Manually-give-back-cancelled-URB-if-we-can-t-qu.patch new file mode 100644 index 0000000000000..abbcac71d67b9 --- /dev/null +++ b/patches.renesas/0216-xhci-Manually-give-back-cancelled-URB-if-we-can-t-qu.patch @@ -0,0 +1,137 @@ +From a347cb5b19008f4f443ec7ab2f35d8a90630cb01 Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Tue, 28 Mar 2017 15:55:30 +0300 +Subject: [PATCH 216/255] xhci: Manually give back cancelled URB if we can't + queue it for cancel + +xhci needs to take care of four scenarios when asked to cancel a URB. + +1 URB is not queued or already given back. + usb_hcd_check_unlink_urb() will return an error, we pass the error on + +2 We fail to find xhci internal structures from urb private data such as + virtual device and endpoint ring. + Give back URB immediately, can't do anything about internal structures. + +3 URB private data has valid pointers to xhci internal data, but host is + not responding. + give back URB immedately and remove the URB from the endpoint lists. + +4 Everyting is working + add URB to cancel list, queue a command to stop the endpoint, after + which the URB can be turned to no-op or skipped, removed from lists, + and given back. + +We failed to give back the urb in case 2 where the correct device and +endpoint pointers could not be retrieved from URB private data. + +This caused a hang on Dell Inspiron 5558/0VNM2T at resume from suspend +as urb was never returned. + +[ 245.270505] INFO: task rtsx_usb_ms_1:254 blocked for more than 120 seconds. +[ 245.272244] Tainted: G W 4.11.0-rc3-ARCH #2 +[ 245.273983] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. +[ 245.275737] rtsx_usb_ms_1 D 0 254 2 0x00000000 +[ 245.277524] Call Trace: +[ 245.279278] __schedule+0x2d3/0x8a0 +[ 245.281077] schedule+0x3d/0x90 +[ 245.281961] usb_kill_urb.part.3+0x6c/0xa0 [usbcore] +[ 245.282861] ? wake_atomic_t_function+0x60/0x60 +[ 245.283760] usb_kill_urb+0x21/0x30 [usbcore] +[ 245.284649] usb_start_wait_urb+0xe5/0x170 [usbcore] +[ 245.285541] ? try_to_del_timer_sync+0x53/0x80 +[ 245.286434] usb_bulk_msg+0xbd/0x160 [usbcore] +[ 245.287326] rtsx_usb_send_cmd+0x63/0x90 [rtsx_usb] + +Reported-by: diego.viola@gmail.com +Tested-by: diego.viola@gmail.com +Cc: stable@vger.kernel.org +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit d3519b9d9606991a1305596348b6d690bfa3eb27) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.c | 43 +++++++++++++++++++++++++------------------ + 1 file changed, 25 insertions(+), 18 deletions(-) + +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1483,6 +1483,7 @@ int xhci_urb_dequeue(struct usb_hcd *hcd + struct xhci_ring *ep_ring; + struct xhci_virt_ep *ep; + struct xhci_command *command; ++ struct xhci_virt_device *vdev; + + xhci = hcd_to_xhci(hcd); + spin_lock_irqsave(&xhci->lock, flags); +@@ -1491,15 +1492,27 @@ int xhci_urb_dequeue(struct usb_hcd *hcd + + /* Make sure the URB hasn't completed or been unlinked already */ + ret = usb_hcd_check_unlink_urb(hcd, urb, status); +- if (ret || !urb->hcpriv) ++ if (ret) + goto done; ++ ++ /* give back URB now if we can't queue it for cancel */ ++ vdev = xhci->devs[urb->dev->slot_id]; ++ urb_priv = urb->hcpriv; ++ if (!vdev || !urb_priv) ++ goto err_giveback; ++ ++ ep_index = xhci_get_endpoint_index(&urb->ep->desc); ++ ep = &vdev->eps[ep_index]; ++ ep_ring = xhci_urb_to_transfer_ring(xhci, urb); ++ if (!ep || !ep_ring) ++ goto err_giveback; ++ + temp = readl(&xhci->op_regs->status); + if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) { + xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, + "HW died, freeing TD."); +- urb_priv = urb->hcpriv; + for (i = urb_priv->num_tds_done; +- i < urb_priv->num_tds && xhci->devs[urb->dev->slot_id]; ++ i < urb_priv->num_tds; + i++) { + td = &urb_priv->td[i]; + if (!list_empty(&td->td_list)) +@@ -1507,23 +1520,9 @@ int xhci_urb_dequeue(struct usb_hcd *hcd + if (!list_empty(&td->cancelled_td_list)) + list_del_init(&td->cancelled_td_list); + } +- +- usb_hcd_unlink_urb_from_ep(hcd, urb); +- spin_unlock_irqrestore(&xhci->lock, flags); +- usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN); +- xhci_urb_free_priv(urb_priv); +- return ret; +- } +- +- ep_index = xhci_get_endpoint_index(&urb->ep->desc); +- ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index]; +- ep_ring = xhci_urb_to_transfer_ring(xhci, urb); +- if (!ep_ring) { +- ret = -EINVAL; +- goto done; ++ goto err_giveback; + } + +- urb_priv = urb->hcpriv; + i = urb_priv->num_tds_done; + if (i < urb_priv->num_tds) + xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, +@@ -1560,6 +1559,14 @@ int xhci_urb_dequeue(struct usb_hcd *hcd + done: + spin_unlock_irqrestore(&xhci->lock, flags); + return ret; ++ ++err_giveback: ++ if (urb_priv) ++ xhci_urb_free_priv(urb_priv); ++ usb_hcd_unlink_urb_from_ep(hcd, urb); ++ spin_unlock_irqrestore(&xhci->lock, flags); ++ usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN); ++ return ret; + } + + /* Drop an endpoint from a new bandwidth configuration for this device. diff --git a/patches.renesas/0217-ravb-Add-tx-and-rx-clock-internal-delays-mode-of-APS.patch b/patches.renesas/0217-ravb-Add-tx-and-rx-clock-internal-delays-mode-of-APS.patch new file mode 100644 index 0000000000000..5cdd35eac5ace --- /dev/null +++ b/patches.renesas/0217-ravb-Add-tx-and-rx-clock-internal-delays-mode-of-APS.patch @@ -0,0 +1,104 @@ +From 0eb77c7eee992b750fc8ab3888c5abf2caea7140 Mon Sep 17 00:00:00 2001 +From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> +Date: Fri, 27 Jan 2017 20:46:26 +0100 +Subject: [PATCH 217/255] ravb: Add tx and rx clock internal delays mode of + APSR + +This patch enables tx and rx clock internal delay modes (TDM and RDM). + +This is to address a failure in the case of 1Gbps communication using the +by salvator-x board with the KSZ9031RNX phy. This has been reported to +occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs. + +With this change APSR internal delay modes are enabled for +"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows: + +phy mode | ASPR delay mode +-----------+---------------- +rgmii-id | TDM and RDM +rgmii-rxid | RDM +rgmii-txid | TDM + +Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 61fccb2d6274f77de6d16a0dc74eda813e90eb64) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/ravb.h | 10 ++++++++++ + drivers/net/ethernet/renesas/ravb_main.c | 23 +++++++++++++++++++++++ + 2 files changed, 33 insertions(+) + +--- a/drivers/net/ethernet/renesas/ravb.h ++++ b/drivers/net/ethernet/renesas/ravb.h +@@ -76,6 +76,7 @@ enum ravb_reg { + CDAR20 = 0x0060, + CDAR21 = 0x0064, + ESR = 0x0088, ++ APSR = 0x008C, /* R-Car Gen3 only */ + RCR = 0x0090, + RQC0 = 0x0094, + RQC1 = 0x0098, +@@ -248,6 +249,15 @@ enum ESR_BIT { + ESR_EIL = 0x00001000, + }; + ++/* APSR */ ++enum APSR_BIT { ++ APSR_MEMS = 0x00000002, ++ APSR_CMSW = 0x00000010, ++ APSR_DM = 0x00006000, /* Undocumented? */ ++ APSR_DM_RDM = 0x00002000, ++ APSR_DM_TDM = 0x00004000, ++}; ++ + /* RCR */ + enum RCR_BIT { + RCR_EFFS = 0x00000001, +--- a/drivers/net/ethernet/renesas/ravb_main.c ++++ b/drivers/net/ethernet/renesas/ravb_main.c +@@ -1921,6 +1921,23 @@ static void ravb_set_config_mode(struct + } + } + ++/* Set tx and rx clock internal delay modes */ ++static void ravb_set_delay_mode(struct net_device *ndev) ++{ ++ struct ravb_private *priv = netdev_priv(ndev); ++ int set = 0; ++ ++ if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || ++ priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ++ set |= APSR_DM_RDM; ++ ++ if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || ++ priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ++ set |= APSR_DM_TDM; ++ ++ ravb_modify(ndev, APSR, APSR_DM, set); ++} ++ + static int ravb_probe(struct platform_device *pdev) + { + struct device_node *np = pdev->dev.of_node; +@@ -2033,6 +2050,9 @@ static int ravb_probe(struct platform_de + /* Request GTI loading */ + ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); + ++ if (priv->chip_id != RCAR_GEN2) ++ ravb_set_delay_mode(ndev); ++ + /* Allocate descriptor base address table */ + priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; + priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, +@@ -2169,6 +2189,9 @@ static int __maybe_unused ravb_resume(st + /* Request GTI loading */ + ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); + ++ if (priv->chip_id != RCAR_GEN2) ++ ravb_set_delay_mode(ndev); ++ + /* Restore descriptor base address table */ + ravb_write(ndev, priv->desc_bat_dma, DBAT); + diff --git a/patches.renesas/0218-ravb-Support-1Gbps-on-R-Car-H3-ES1.1-and-R-Car-M3-W.patch b/patches.renesas/0218-ravb-Support-1Gbps-on-R-Car-H3-ES1.1-and-R-Car-M3-W.patch new file mode 100644 index 0000000000000..005f0bf788f84 --- /dev/null +++ b/patches.renesas/0218-ravb-Support-1Gbps-on-R-Car-H3-ES1.1-and-R-Car-M3-W.patch @@ -0,0 +1,54 @@ +From 857f329237b380fa7b69cb29952c17a451393aaf Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 27 Jan 2017 20:46:27 +0100 +Subject: [PATCH 218/255] ravb: Support 1Gbps on R-Car H3 ES1.1+ and R-Car M3-W + +The limitation to 10/100Mbit speeds on R-Car Gen3 is valid for R-Car H3 +ES1.0 only. Check for the exact SoC model to allow 1Gbps on newer +revisions of R-Car H3, and on R-Car M3-W. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 0e98f9d5f0b4a9012bd4fb5ff88b3ea290deb6a8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/ravb_main.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/renesas/ravb_main.c ++++ b/drivers/net/ethernet/renesas/ravb_main.c +@@ -31,6 +31,7 @@ + #include <linux/pm_runtime.h> + #include <linux/slab.h> + #include <linux/spinlock.h> ++#include <linux/sys_soc.h> + + #include <asm/div64.h> + +@@ -988,6 +989,11 @@ static void ravb_adjust_link(struct net_ + phy_print_status(phydev); + } + ++static const struct soc_device_attribute r8a7795es10[] = { ++ { .soc_id = "r8a7795", .revision = "ES1.0", }, ++ { /* sentinel */ } ++}; ++ + /* PHY init function */ + static int ravb_phy_init(struct net_device *ndev) + { +@@ -1023,10 +1029,10 @@ static int ravb_phy_init(struct net_devi + goto err_deregister_fixed_link; + } + +- /* This driver only support 10/100Mbit speeds on Gen3 ++ /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 + * at this time. + */ +- if (priv->chip_id == RCAR_GEN3) { ++ if (soc_device_match(r8a7795es10)) { + err = phy_set_max_speed(phydev, SPEED_100); + if (err) { + netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); diff --git a/patches.renesas/0219-ravb-Double-free-on-error-in-ravb_start_xmit.patch b/patches.renesas/0219-ravb-Double-free-on-error-in-ravb_start_xmit.patch new file mode 100644 index 0000000000000..c50daf65f7a0e --- /dev/null +++ b/patches.renesas/0219-ravb-Double-free-on-error-in-ravb_start_xmit.patch @@ -0,0 +1,36 @@ +From 8825e544269d30724022625eac0fa4ccc0cacca1 Mon Sep 17 00:00:00 2001 +From: Dan Carpenter <dan.carpenter@oracle.com> +Date: Sat, 22 Apr 2017 13:46:56 +0300 +Subject: [PATCH 219/255] ravb: Double free on error in ravb_start_xmit() + +If skb_put_padto() fails then it frees the skb. I shifted that code +up a bit to make my error handling a little simpler. + +Fixes: a0d2f20650e8 ("Renesas Ethernet AVB PTP clock driver") +Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> +Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 9199cb7677b388b42e3d95c755090dfc5ab2b11a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/ravb_main.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/drivers/net/ethernet/renesas/ravb_main.c ++++ b/drivers/net/ethernet/renesas/ravb_main.c +@@ -1516,11 +1516,12 @@ static netdev_tx_t ravb_start_xmit(struc + spin_unlock_irqrestore(&priv->lock, flags); + return NETDEV_TX_BUSY; + } +- entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); +- priv->tx_skb[q][entry / NUM_TX_DESC] = skb; + + if (skb_put_padto(skb, ETH_ZLEN)) +- goto drop; ++ goto exit; ++ ++ entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); ++ priv->tx_skb[q][entry / NUM_TX_DESC] = skb; + + buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + + entry / NUM_TX_DESC * DPTR_ALIGN; diff --git a/patches.renesas/0220-clk-add-devm_get_clk_from_child-API.patch b/patches.renesas/0220-clk-add-devm_get_clk_from_child-API.patch new file mode 100644 index 0000000000000..ec8f41ca490e9 --- /dev/null +++ b/patches.renesas/0220-clk-add-devm_get_clk_from_child-API.patch @@ -0,0 +1,140 @@ +From 27e90992b8093141112912cd24f241bf2f07c6f9 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 5 Dec 2016 05:23:20 +0000 +Subject: [PATCH 220/255] clk: add devm_get_clk_from_child() API + +Some driver is using this type of DT bindings for clock (more detail, +see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt). + + sound_soc { + ... + cpu { + clocks = <&xxx>; + ... + }; + codec { + clocks = <&xxx>; + ... + }; + }; + +Current driver in this case uses of_clk_get() for each node, but there +is no devm_of_clk_get() today. +OTOH, the problem of having devm_of_clk_get() is that it encourages the +use of of_clk_get() when clk_get() is more desirable. + +Thus, this patch adds new devm_get_clk_from_chile() which explicitly +reads as get a clock from a child node of this device. +By this function, we can also use this type of DT bindings + + sound_soc { + clocks = <&xxx>, <&xxx>; + clock-names = "cpu", "codec"; + clock-ranges; + ... + cpu { + ... + }; + codec { + ... + }; + }; + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +[sboyd@codeurora.org: Rename subject to clk + add API] +Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> + +(cherry picked from commit 71a2f11511b4d1dc8b8e326e10ec6533b534ddf1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/clk-devres.c | 21 +++++++++++++++++++++ + include/linux/clk.h | 29 +++++++++++++++++++++++++---- + 2 files changed, 46 insertions(+), 4 deletions(-) + +--- a/drivers/clk/clk-devres.c ++++ b/drivers/clk/clk-devres.c +@@ -53,3 +53,24 @@ void devm_clk_put(struct device *dev, st + WARN_ON(ret); + } + EXPORT_SYMBOL(devm_clk_put); ++ ++struct clk *devm_get_clk_from_child(struct device *dev, ++ struct device_node *np, const char *con_id) ++{ ++ struct clk **ptr, *clk; ++ ++ ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL); ++ if (!ptr) ++ return ERR_PTR(-ENOMEM); ++ ++ clk = of_clk_get_by_name(np, con_id); ++ if (!IS_ERR(clk)) { ++ *ptr = clk; ++ devres_add(dev, ptr); ++ } else { ++ devres_free(ptr); ++ } ++ ++ return clk; ++} ++EXPORT_SYMBOL(devm_get_clk_from_child); +--- a/include/linux/clk.h ++++ b/include/linux/clk.h +@@ -17,8 +17,9 @@ + #include <linux/notifier.h> + + struct device; +- + struct clk; ++struct device_node; ++struct of_phandle_args; + + /** + * DOC: clk notifier callback types +@@ -249,6 +250,23 @@ struct clk *clk_get(struct device *dev, + struct clk *devm_clk_get(struct device *dev, const char *id); + + /** ++ * devm_get_clk_from_child - lookup and obtain a managed reference to a ++ * clock producer from child node. ++ * @dev: device for clock "consumer" ++ * @np: pointer to clock consumer node ++ * @con_id: clock consumer ID ++ * ++ * This function parses the clocks, and uses them to look up the ++ * struct clk from the registered list of clock providers by using ++ * @np and @con_id ++ * ++ * The clock will automatically be freed when the device is unbound ++ * from the bus. ++ */ ++struct clk *devm_get_clk_from_child(struct device *dev, ++ struct device_node *np, const char *con_id); ++ ++/** + * clk_enable - inform the system when the clock source should be running. + * @clk: clock source + * +@@ -432,6 +450,12 @@ static inline struct clk *devm_clk_get(s + return NULL; + } + ++static inline struct clk *devm_get_clk_from_child(struct device *dev, ++ struct device_node *np, const char *con_id) ++{ ++ return NULL; ++} ++ + static inline void clk_put(struct clk *clk) {} + + static inline void devm_clk_put(struct device *dev, struct clk *clk) {} +@@ -501,9 +525,6 @@ static inline void clk_disable_unprepare + clk_unprepare(clk); + } + +-struct device_node; +-struct of_phandle_args; +- + #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) + struct clk *of_clk_get(struct device_node *np, int index); + struct clk *of_clk_get_by_name(struct device_node *np, const char *name); diff --git a/patches.renesas/0221-ASoC-simple-card-use-devm_get_clk_from_child.patch b/patches.renesas/0221-ASoC-simple-card-use-devm_get_clk_from_child.patch new file mode 100644 index 0000000000000..9eb4ab4a5d0e3 --- /dev/null +++ b/patches.renesas/0221-ASoC-simple-card-use-devm_get_clk_from_child.patch @@ -0,0 +1,105 @@ +From 2c9ee8866cd69f35af5cbcbf5ef15dcee76e1f7a Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Mon, 23 Jan 2017 07:29:42 +0000 +Subject: [PATCH 221/255] ASoC: simple-card: use devm_get_clk_from_child() + +Current simple-card-utils is getting clk by of_clk_get(), but didn't call +clk_free(). Now we can use devm_get_clk_from_child() for this purpose. +Let's use it. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit e984fd61e860ce3c45e79d69cf214b8cc6cae7d9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/sound/simple_card_utils.h | 11 ++++++----- + sound/soc/generic/simple-card-utils.c | 8 ++++---- + sound/soc/generic/simple-card.c | 4 ++-- + sound/soc/generic/simple-scu-card.c | 4 ++-- + 4 files changed, 14 insertions(+), 13 deletions(-) + +--- a/include/sound/simple_card_utils.h ++++ b/include/sound/simple_card_utils.h +@@ -34,11 +34,12 @@ int asoc_simple_card_set_dailink_name(st + int asoc_simple_card_parse_card_name(struct snd_soc_card *card, + char *prefix); + +-#define asoc_simple_card_parse_clk_cpu(node, dai_link, simple_dai) \ +- asoc_simple_card_parse_clk(node, dai_link->cpu_of_node, simple_dai) +-#define asoc_simple_card_parse_clk_codec(node, dai_link, simple_dai) \ +- asoc_simple_card_parse_clk(node, dai_link->codec_of_node, simple_dai) +-int asoc_simple_card_parse_clk(struct device_node *node, ++#define asoc_simple_card_parse_clk_cpu(dev, node, dai_link, simple_dai) \ ++ asoc_simple_card_parse_clk(dev, node, dai_link->cpu_of_node, simple_dai) ++#define asoc_simple_card_parse_clk_codec(dev, node, dai_link, simple_dai) \ ++ asoc_simple_card_parse_clk(dev, node, dai_link->codec_of_node, simple_dai) ++int asoc_simple_card_parse_clk(struct device *dev, ++ struct device_node *node, + struct device_node *dai_of_node, + struct asoc_simple_dai *simple_dai); + +--- a/sound/soc/generic/simple-card-utils.c ++++ b/sound/soc/generic/simple-card-utils.c +@@ -98,7 +98,8 @@ int asoc_simple_card_parse_card_name(str + } + EXPORT_SYMBOL_GPL(asoc_simple_card_parse_card_name); + +-int asoc_simple_card_parse_clk(struct device_node *node, ++int asoc_simple_card_parse_clk(struct device *dev, ++ struct device_node *node, + struct device_node *dai_of_node, + struct asoc_simple_dai *simple_dai) + { +@@ -111,14 +112,13 @@ int asoc_simple_card_parse_clk(struct de + * or "system-clock-frequency = <xxx>" + * or device's module clock. + */ +- clk = of_clk_get(node, 0); ++ clk = devm_get_clk_from_child(dev, node, NULL); + if (!IS_ERR(clk)) { + simple_dai->sysclk = clk_get_rate(clk); +- simple_dai->clk = clk; + } else if (!of_property_read_u32(node, "system-clock-frequency", &val)) { + simple_dai->sysclk = val; + } else { +- clk = of_clk_get(dai_of_node, 0); ++ clk = devm_get_clk_from_child(dev, dai_of_node, NULL); + if (!IS_ERR(clk)) + simple_dai->sysclk = clk_get_rate(clk); + } +--- a/sound/soc/generic/simple-card.c ++++ b/sound/soc/generic/simple-card.c +@@ -278,11 +278,11 @@ static int asoc_simple_card_dai_link_of( + if (ret < 0) + goto dai_link_of_err; + +- ret = asoc_simple_card_parse_clk_cpu(cpu, dai_link, cpu_dai); ++ ret = asoc_simple_card_parse_clk_cpu(dev, cpu, dai_link, cpu_dai); + if (ret < 0) + goto dai_link_of_err; + +- ret = asoc_simple_card_parse_clk_codec(codec, dai_link, codec_dai); ++ ret = asoc_simple_card_parse_clk_codec(dev, codec, dai_link, codec_dai); + if (ret < 0) + goto dai_link_of_err; + +--- a/sound/soc/generic/simple-scu-card.c ++++ b/sound/soc/generic/simple-scu-card.c +@@ -128,7 +128,7 @@ static int asoc_simple_card_dai_link_of( + if (ret) + return ret; + +- ret = asoc_simple_card_parse_clk_cpu(np, dai_link, dai_props); ++ ret = asoc_simple_card_parse_clk_cpu(dev, np, dai_link, dai_props); + if (ret < 0) + return ret; + +@@ -153,7 +153,7 @@ static int asoc_simple_card_dai_link_of( + if (ret < 0) + return ret; + +- ret = asoc_simple_card_parse_clk_codec(np, dai_link, dai_props); ++ ret = asoc_simple_card_parse_clk_codec(dev, np, dai_link, dai_props); + if (ret < 0) + return ret; + diff --git a/patches.renesas/0222-media-v4l-vsp1-Add-VIDIOC_EXPBUF-support.patch b/patches.renesas/0222-media-v4l-vsp1-Add-VIDIOC_EXPBUF-support.patch new file mode 100644 index 0000000000000..164b454d2e1c5 --- /dev/null +++ b/patches.renesas/0222-media-v4l-vsp1-Add-VIDIOC_EXPBUF-support.patch @@ -0,0 +1,26 @@ +From 1f88d5d1d4b8aad56b3233d7be6a96ffa9186c60 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 12 Dec 2016 08:37:42 -0200 +Subject: [PATCH 222/255] [media] v4l: vsp1: Add VIDIOC_EXPBUF support + +Use the vb2 ioctl handler directly. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Jacopo Mondi <jacopo@jmondi.org> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 5a66e2f60ef6a153bba387b1382e527248c959a0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_video.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/media/platform/vsp1/vsp1_video.c ++++ b/drivers/media/platform/vsp1/vsp1_video.c +@@ -1021,6 +1021,7 @@ static const struct v4l2_ioctl_ops vsp1_ + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, ++ .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_streamon = vsp1_video_streamon, diff --git a/patches.renesas/0223-sh-Don-t-set-sh-sci-port_reg.patch b/patches.renesas/0223-sh-Don-t-set-sh-sci-port_reg.patch new file mode 100644 index 0000000000000..f143610c67d5a --- /dev/null +++ b/patches.renesas/0223-sh-Don-t-set-sh-sci-port_reg.patch @@ -0,0 +1,184 @@ +From f5bab7a10bbcea5818692b9d3703550f58edf714 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Jan 2017 16:43:29 +0200 +Subject: [PATCH 223/255] sh: Don't set sh-sci port_reg + +The driver considers all negative or zero values of the port_reg field +as invalid. The four platforms that set the field to a register address +all use an address higher than 0x7fffffff, which is thus considered by +the driver as invalid. The feature is thus never used, remove it. + +The feature could be implemented properly in the future using the +pinctrl and GPIO APIs if desired. + +While at it, don't set the field to SCIx_NOT_SUPPORTED (-1) either, +leaving it unset leads to the same result. This will allow removing the +SCIx_NOT_SUPPORTED macro. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit bcce9daa87cd0ad44bf9bdd433eae0474f51e1e2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/sh/kernel/cpu/sh3/setup-sh770x.c + arch/sh/kernel/cpu/sh4/setup-sh7750.c + arch/sh/kernel/cpu/sh4a/setup-sh7366.c + arch/sh/kernel/cpu/sh4a/setup-sh7723.c + arch/sh/kernel/cpu/sh4a/setup-sh7724.c +--- + arch/sh/kernel/cpu/sh3/setup-sh770x.c | 2 -- + arch/sh/kernel/cpu/sh4/setup-sh7750.c | 1 - + arch/sh/kernel/cpu/sh4a/setup-sh7366.c | 1 - + arch/sh/kernel/cpu/sh4a/setup-sh7723.c | 6 ------ + arch/sh/kernel/cpu/sh4a/setup-sh7724.c | 9 --------- + 5 files changed, 19 deletions(-) + +--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c ++++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c +@@ -109,7 +109,6 @@ static struct platform_device rtc_device + }; + + static struct plat_sci_port scif0_platform_data = { +- .port_reg = 0xa4000136, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_TE | SCSCR_RE, + .type = PORT_SCI, +@@ -160,7 +159,6 @@ static struct platform_device scif1_devi + #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ + defined(CONFIG_CPU_SUBTYPE_SH7709) + static struct plat_sci_port scif2_platform_data = { +- .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_TE | SCSCR_RE, + .type = PORT_IRDA, +--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c ++++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c +@@ -38,7 +38,6 @@ static struct platform_device rtc_device + }; + + static struct plat_sci_port sci_platform_data = { +- .port_reg = 0xffe0001C, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_TE | SCSCR_RE, + .type = PORT_SCI, +--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c ++++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +@@ -20,7 +20,6 @@ + #include <asm/clock.h> + + static struct plat_sci_port scif0_platform_data = { +- .port_reg = 0xa405013e, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, +--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c ++++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +@@ -23,7 +23,6 @@ + + /* Serial */ + static struct plat_sci_port scif0_platform_data = { +- .port_reg = 0xa4050160, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, +@@ -46,7 +45,6 @@ static struct platform_device scif0_devi + }; + + static struct plat_sci_port scif1_platform_data = { +- .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, +@@ -69,7 +67,6 @@ static struct platform_device scif1_devi + }; + + static struct plat_sci_port scif2_platform_data = { +- .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, +@@ -93,7 +90,6 @@ static struct platform_device scif2_devi + + static struct plat_sci_port scif3_platform_data = { + .flags = UPF_BOOT_AUTOCONF, +- .port_reg = SCIx_NOT_SUPPORTED, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .sampling_rate = 8, + .type = PORT_SCIFA, +@@ -115,7 +111,6 @@ static struct platform_device scif3_devi + }; + + static struct plat_sci_port scif4_platform_data = { +- .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .sampling_rate = 8, +@@ -138,7 +133,6 @@ static struct platform_device scif4_devi + }; + + static struct plat_sci_port scif5_platform_data = { +- .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .sampling_rate = 8, +--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c ++++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +@@ -290,7 +290,6 @@ static struct platform_device dma1_devic + + /* Serial */ + static struct plat_sci_port scif0_platform_data = { +- .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, +@@ -313,7 +312,6 @@ static struct platform_device scif0_devi + }; + + static struct plat_sci_port scif1_platform_data = { +- .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, +@@ -336,7 +334,6 @@ static struct platform_device scif1_devi + }; + + static struct plat_sci_port scif2_platform_data = { +- .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, +@@ -359,10 +356,8 @@ static struct platform_device scif2_devi + }; + + static struct plat_sci_port scif3_platform_data = { +- .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, +- .sampling_rate = 8, + .type = PORT_SCIFA, + }; + +@@ -382,10 +377,8 @@ static struct platform_device scif3_devi + }; + + static struct plat_sci_port scif4_platform_data = { +- .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, +- .sampling_rate = 8, + .type = PORT_SCIFA, + }; + +@@ -405,10 +398,8 @@ static struct platform_device scif4_devi + }; + + static struct plat_sci_port scif5_platform_data = { +- .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, +- .sampling_rate = 8, + .type = PORT_SCIFA, + }; + diff --git a/patches.renesas/0224-serial-sh-sci-Remove-manual-break-debouncing.patch b/patches.renesas/0224-serial-sh-sci-Remove-manual-break-debouncing.patch new file mode 100644 index 0000000000000..a54e3849fb941 --- /dev/null +++ b/patches.renesas/0224-serial-sh-sci-Remove-manual-break-debouncing.patch @@ -0,0 +1,256 @@ +From 7d25ca02c11d60137c936991edb488b44208877f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Jan 2017 16:43:38 +0200 +Subject: [PATCH 224/255] serial: sh-sci: Remove manual break debouncing + +The sh-sci driver implements manual break debouncing for a few SH +platforms by reading the value of the RX pin port register. This feature +is optional and the driver considers all negative or zero values of the +platform data port_reg field as invalid. As the four platforms that set +the field to a register address all use an address higher than +0x7fffffff, the driver will always consider the value as invalid and +never perform debouncing. The feature is unused, remove it. + +Debouncing could be implemented properly in the future using the pinctrl +and GPIO APIs if desired. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit d5cb1319a91d4f1328b1c70b82c5899acd96af85) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 124 ++------------------------------------------ + include/linux/serial_sci.h | 5 - + 2 files changed, 7 insertions(+), 122 deletions(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -125,10 +125,6 @@ struct sci_port { + resource_size_t reg_size; + struct mctrl_gpios *gpios; + +- /* Break timer */ +- struct timer_list break_timer; +- int break_flag; +- + /* Clocks */ + struct clk *clks[SCI_NUM_CLKS]; + unsigned long clk_rates[SCI_NUM_CLKS]; +@@ -517,14 +513,6 @@ static void sci_port_disable(struct sci_ + if (!sci_port->port.dev) + return; + +- /* Cancel the break timer to ensure that the timer handler will not try +- * to access the hardware with clocks and power disabled. Reset the +- * break flag to make the break debouncing state machine ready for the +- * next break. +- */ +- del_timer_sync(&sci_port->break_timer); +- sci_port->break_flag = 0; +- + for (i = SCI_NUM_CLKS; i-- > 0; ) + clk_disable_unprepare(sci_port->clks[i]); + +@@ -751,20 +739,6 @@ static int sci_rxfill(struct uart_port * + return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; + } + +-/* +- * SCI helper for checking the state of the muxed port/RXD pins. +- */ +-static inline int sci_rxd_in(struct uart_port *port) +-{ +- struct sci_port *s = to_sci_port(port); +- +- if (s->cfg->port_reg <= 0) +- return 1; +- +- /* Cast for ARM damage */ +- return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg); +-} +- + /* ********************************************************************** * + * the interrupt related routines * + * ********************************************************************** */ +@@ -832,7 +806,6 @@ static void sci_transmit_chars(struct ua + + static void sci_receive_chars(struct uart_port *port) + { +- struct sci_port *sci_port = to_sci_port(port); + struct tty_port *tport = &port->state->port; + int i, count, copied = 0; + unsigned short status; +@@ -852,8 +825,7 @@ static void sci_receive_chars(struct uar + + if (port->type == PORT_SCI) { + char c = serial_port_in(port, SCxRDR); +- if (uart_handle_sysrq_char(port, c) || +- sci_port->break_flag) ++ if (uart_handle_sysrq_char(port, c)) + count = 0; + else + tty_insert_flip_char(tport, c, TTY_NORMAL); +@@ -862,25 +834,6 @@ static void sci_receive_chars(struct uar + char c = serial_port_in(port, SCxRDR); + + status = serial_port_in(port, SCxSR); +-#if defined(CONFIG_CPU_SH3) +- /* Skip "chars" during break */ +- if (sci_port->break_flag) { +- if ((c == 0) && +- (status & SCxSR_FER(port))) { +- count--; i--; +- continue; +- } +- +- /* Nonzero => end-of-break */ +- dev_dbg(port->dev, "debounce<%02x>\n", c); +- sci_port->break_flag = 0; +- +- if (STEPFN(c)) { +- count--; i--; +- continue; +- } +- } +-#endif /* CONFIG_CPU_SH3 */ + if (uart_handle_sysrq_char(port, c)) { + count--; i--; + continue; +@@ -918,37 +871,6 @@ static void sci_receive_chars(struct uar + } + } + +-#define SCI_BREAK_JIFFIES (HZ/20) +- +-/* +- * The sci generates interrupts during the break, +- * 1 per millisecond or so during the break period, for 9600 baud. +- * So dont bother disabling interrupts. +- * But dont want more than 1 break event. +- * Use a kernel timer to periodically poll the rx line until +- * the break is finished. +- */ +-static inline void sci_schedule_break_timer(struct sci_port *port) +-{ +- mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); +-} +- +-/* Ensure that two consecutive samples find the break over. */ +-static void sci_break_timer(unsigned long data) +-{ +- struct sci_port *port = (struct sci_port *)data; +- +- if (sci_rxd_in(&port->port) == 0) { +- port->break_flag = 1; +- sci_schedule_break_timer(port); +- } else if (port->break_flag == 1) { +- /* break is over. */ +- port->break_flag = 2; +- sci_schedule_break_timer(port); +- } else +- port->break_flag = 0; +-} +- + static int sci_handle_errors(struct uart_port *port) + { + int copied = 0; +@@ -968,35 +890,13 @@ static int sci_handle_errors(struct uart + } + + if (status & SCxSR_FER(port)) { +- if (sci_rxd_in(port) == 0) { +- /* Notify of BREAK */ +- struct sci_port *sci_port = to_sci_port(port); +- +- if (!sci_port->break_flag) { +- port->icount.brk++; +- +- sci_port->break_flag = 1; +- sci_schedule_break_timer(sci_port); +- +- /* Do sysrq handling. */ +- if (uart_handle_break(port)) +- return 0; +- +- dev_dbg(port->dev, "BREAK detected\n"); +- +- if (tty_insert_flip_char(tport, 0, TTY_BREAK)) +- copied++; +- } +- +- } else { +- /* frame error */ +- port->icount.frame++; ++ /* frame error */ ++ port->icount.frame++; + +- if (tty_insert_flip_char(tport, 0, TTY_FRAME)) +- copied++; ++ if (tty_insert_flip_char(tport, 0, TTY_FRAME)) ++ copied++; + +- dev_notice(port->dev, "frame error\n"); +- } ++ dev_notice(port->dev, "frame error\n"); + } + + if (status & SCxSR_PER(port)) { +@@ -1049,17 +949,11 @@ static int sci_handle_breaks(struct uart + int copied = 0; + unsigned short status = serial_port_in(port, SCxSR); + struct tty_port *tport = &port->state->port; +- struct sci_port *s = to_sci_port(port); + + if (uart_handle_break(port)) + return 0; + +- if (!s->break_flag && status & SCxSR_BRK(port)) { +-#if defined(CONFIG_CPU_SH3) +- /* Debounce break */ +- s->break_flag = 1; +-#endif +- ++ if (status & SCxSR_BRK(port)) { + port->icount.brk++; + + /* Notify of BREAK */ +@@ -2683,10 +2577,6 @@ static int sci_init_single(struct platfo + pm_runtime_enable(&dev->dev); + } + +- sci_port->break_timer.data = (unsigned long)sci_port; +- sci_port->break_timer.function = sci_break_timer; +- init_timer(&sci_port->break_timer); +- + port->type = p->type; + port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; + port->regshift = p->regshift; +--- a/include/linux/serial_sci.h ++++ b/include/linux/serial_sci.h +@@ -9,8 +9,6 @@ + * Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts) + */ + +-#define SCIx_NOT_SUPPORTED (-1) +- + /* Serial Control Register (@ = not supported by all parts) */ + #define SCSCR_TIE BIT(7) /* Transmit Interrupt Enable */ + #define SCSCR_RIE BIT(6) /* Receive Interrupt Enable */ +@@ -41,8 +39,6 @@ enum { + SCIx_NR_REGTYPES, + }; + +-struct device; +- + struct plat_sci_port_ops { + void (*init_pins)(struct uart_port *, unsigned int cflag); + }; +@@ -66,7 +62,6 @@ struct plat_sci_port { + /* + * Platform overrides if necessary, defaults otherwise. + */ +- int port_reg; + unsigned char regshift; + unsigned char regtype; + diff --git a/patches.renesas/0225-serial-sh-sci-Remove-unused-platform-data-capabiliti.patch b/patches.renesas/0225-serial-sh-sci-Remove-unused-platform-data-capabiliti.patch new file mode 100644 index 0000000000000..48e71ba7bc478 --- /dev/null +++ b/patches.renesas/0225-serial-sh-sci-Remove-unused-platform-data-capabiliti.patch @@ -0,0 +1,100 @@ +From 2b96c21b6e34f18968be422f502aabee24366f97 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Jan 2017 16:43:39 +0200 +Subject: [PATCH 225/255] serial: sh-sci: Remove unused platform data + capabilities field + +The field isn't set by any platform but is only used internally in the +driver to hold data parsed from DT. Move it to the sci_port structure. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 97ed9790c514066bfae67f22e084b505ed5af436) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 11 +++++++---- + include/linux/serial_sci.h | 6 ------ + 2 files changed, 7 insertions(+), 10 deletions(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -149,6 +149,7 @@ struct sci_port { + unsigned int rx_timeout; + #endif + ++ bool has_rtscts; + bool autorts; + }; + +@@ -680,7 +681,7 @@ static void sci_init_pins(struct uart_po + + /* Enable RXD and TXD pin functions */ + ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); +- if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) { ++ if (to_sci_port(port)->has_rtscts) { + /* RTS# is output, driven 1 */ + ctrl |= SCPCR_RTSC; + serial_port_out(port, SCPDR, +@@ -1738,7 +1739,7 @@ static void sci_set_mctrl(struct uart_po + + mctrl_gpio_set(s->gpios, mctrl); + +- if (!(s->cfg->capabilities & SCIx_HAVE_RTSCTS)) ++ if (!s->has_rtscts) + return; + + if (!(mctrl & TIOCM_RTS)) { +@@ -2815,6 +2816,7 @@ sci_parse_dt(struct platform_device *pde + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; + struct plat_sci_port *p; ++ struct sci_port *sp; + int id; + + if (!IS_ENABLED(CONFIG_OF) || !np) +@@ -2835,13 +2837,14 @@ sci_parse_dt(struct platform_device *pde + return NULL; + } + ++ sp = &sci_ports[id]; + *dev_id = id; + + p->type = SCI_OF_TYPE(match->data); + p->regtype = SCI_OF_REGTYPE(match->data); + + if (of_find_property(np, "uart-has-rtscts", NULL)) +- p->capabilities |= SCIx_HAVE_RTSCTS; ++ sp->has_rtscts = true; + + return p; + } +@@ -2869,7 +2872,7 @@ static int sci_probe_single(struct platf + if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS) + return PTR_ERR(sciport->gpios); + +- if (p->capabilities & SCIx_HAVE_RTSCTS) { ++ if (sciport->has_rtscts) { + if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, + UART_GPIO_CTS)) || + !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, +--- a/include/linux/serial_sci.h ++++ b/include/linux/serial_sci.h +@@ -44,17 +44,11 @@ struct plat_sci_port_ops { + }; + + /* +- * Port-specific capabilities +- */ +-#define SCIx_HAVE_RTSCTS BIT(0) +- +-/* + * Platform device specific platform_data struct + */ + struct plat_sci_port { + unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ + upf_t flags; /* UPF_* flags */ +- unsigned long capabilities; /* Port features/capabilities */ + + unsigned int sampling_rate; + unsigned int scscr; /* SCSCR initialization */ diff --git a/patches.renesas/0226-serial-sh-sci-Compute-the-regshift-value-for-SCI-por.patch b/patches.renesas/0226-serial-sh-sci-Compute-the-regshift-value-for-SCI-por.patch new file mode 100644 index 0000000000000..a15f61d5c66f3 --- /dev/null +++ b/patches.renesas/0226-serial-sh-sci-Compute-the-regshift-value-for-SCI-por.patch @@ -0,0 +1,109 @@ +From 861cb580245b6d19b116575e828849373d86d159 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 11 Jan 2017 16:43:40 +0200 +Subject: [PATCH 226/255] serial: sh-sci: Compute the regshift value for SCI + ports + +SCI instances found in SH SoCs have different spacing between registers +depending on the SoC. The platform data contains a regshift field that +tells the driver by how many bits to shift the register offset to +compute its address. We can compute the regshift value automatically +based on the memory resource size, there's no need to pass the value +through platform data. + +Fix the sh7750 SCI and sh7760 SIM port memory resources length to ensure +proper computation of the regshift value. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit dfc80387aefb78161f83732804c6d01c89c24595) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/sh/kernel/cpu/sh4/setup-sh7760.c +--- + arch/sh/kernel/cpu/sh3/setup-sh770x.c | 1 - + arch/sh/kernel/cpu/sh4/setup-sh7750.c | 3 +-- + arch/sh/kernel/cpu/sh4/setup-sh7760.c | 10 ++++++++-- + drivers/tty/serial/sh-sci.c | 8 +++++++- + include/linux/serial_sci.h | 1 - + 5 files changed, 16 insertions(+), 7 deletions(-) + +--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c ++++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c +@@ -113,7 +113,6 @@ static struct plat_sci_port scif0_platfo + .scscr = SCSCR_TE | SCSCR_RE, + .type = PORT_SCI, + .ops = &sh770x_sci_port_ops, +- .regshift = 1, + }; + + static struct resource scif0_resources[] = { +--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c ++++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c +@@ -41,11 +41,10 @@ static struct plat_sci_port sci_platform + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_TE | SCSCR_RE, + .type = PORT_SCI, +- .regshift = 2, + }; + + static struct resource sci_resources[] = { +- DEFINE_RES_MEM(0xffe00000, 0x100), ++ DEFINE_RES_MEM(0xffe00000, 0x20), + DEFINE_RES_IRQ(evt2irq(0x4e0)), + }; + +--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c ++++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c +@@ -205,12 +205,18 @@ static struct platform_device scif2_devi + static struct plat_sci_port scif3_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, ++ /* ++ * This is actually a SIM card module serial port, based on an SCI with ++ * additional registers. The sh-sci driver doesn't support the SIM port ++ * type, declare it as a SCI. Don't declare the additional registers in ++ * the memory resource or the driver will compute an incorrect regshift ++ * value. ++ */ + .type = PORT_SCI, +- .regshift = 2, + }; + + static struct resource scif3_resources[] = { +- DEFINE_RES_MEM(0xfe480000, 0x100), ++ DEFINE_RES_MEM(0xfe480000, 0x10), + DEFINE_RES_IRQ(evt2irq(0xc00)), + DEFINE_RES_IRQ(evt2irq(0xc20)), + DEFINE_RES_IRQ(evt2irq(0xc40)), +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -2580,9 +2580,15 @@ static int sci_init_single(struct platfo + + port->type = p->type; + port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; +- port->regshift = p->regshift; + port->fifosize = sci_port->params->fifosize; + ++ if (port->type == PORT_SCI) { ++ if (sci_port->reg_size >= 0x20) ++ port->regshift = 2; ++ else ++ port->regshift = 1; ++ } ++ + /* + * The UART port needs an IRQ value, so we peg this to the RX IRQ + * for the multi-IRQ ports, which is where we are primarily +--- a/include/linux/serial_sci.h ++++ b/include/linux/serial_sci.h +@@ -56,7 +56,6 @@ struct plat_sci_port { + /* + * Platform overrides if necessary, defaults otherwise. + */ +- unsigned char regshift; + unsigned char regtype; + + struct plat_sci_port_ops *ops; diff --git a/patches.renesas/0227-serial-sh-sci-Reformat-sci_parse_dt-for-git-diff.patch b/patches.renesas/0227-serial-sh-sci-Reformat-sci_parse_dt-for-git-diff.patch new file mode 100644 index 0000000000000..bf560d25900f4 --- /dev/null +++ b/patches.renesas/0227-serial-sh-sci-Reformat-sci_parse_dt-for-git-diff.patch @@ -0,0 +1,33 @@ +From e792492c0246157d7ae04c38322ce3e04c8f0b1c Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 25 Jan 2017 15:55:49 +0100 +Subject: [PATCH 227/255] serial: sh-sci: Reformat sci_parse_dt() for git diff + +As the function header of sci_parse_dt() is split in an unusual way, +"git diff" gets confused when changes to the body of the function are +made, and attributes them to the wrong function. + +Reformat the function header to fix this. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 54b12c48f0c603f25bac3c7c58a02cee65610171) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -2816,8 +2816,8 @@ static const struct of_device_id of_sci_ + }; + MODULE_DEVICE_TABLE(of, of_sci_match); + +-static struct plat_sci_port * +-sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id) ++static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, ++ unsigned int *dev_id) + { + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; diff --git a/patches.renesas/0228-serial-sh-sci-add-FIFO-trigger-bits.patch b/patches.renesas/0228-serial-sh-sci-add-FIFO-trigger-bits.patch new file mode 100644 index 0000000000000..96ab5b49367a4 --- /dev/null +++ b/patches.renesas/0228-serial-sh-sci-add-FIFO-trigger-bits.patch @@ -0,0 +1,51 @@ +From a631740d6e09004d2fdf0e1a69e0f5fbaeab9e6a Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Thu, 2 Feb 2017 18:10:14 +0100 +Subject: [PATCH 228/255] serial: sh-sci: add FIFO trigger bits + +Defines the bits controlling FIFO thresholds, adds the additional +HSCIF registers to the register map. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 54e14ae2f3e82b327853e40afa9382a984a56742) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 2 ++ + drivers/tty/serial/sh-sci.h | 6 ++++++ + 2 files changed, 8 insertions(+) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -373,6 +373,8 @@ static const struct sci_port_params sci_ + [HSSRR] = { 0x40, 16 }, + [SCDL] = { 0x30, 16 }, + [SCCKS] = { 0x34, 16 }, ++ [HSRTRGR] = { 0x54, 16 }, ++ [HSTTRGR] = { 0x58, 16 }, + }, + .fifosize = 128, + .overrun_reg = SCLSR, +--- a/drivers/tty/serial/sh-sci.h ++++ b/drivers/tty/serial/sh-sci.h +@@ -29,6 +29,8 @@ enum { + SCPDR, /* Serial Port Data Register */ + SCDL, /* BRG Frequency Division Register */ + SCCKS, /* BRG Clock Select Register */ ++ HSRTRGR, /* Rx FIFO Data Count Trigger Register */ ++ HSTTRGR, /* Tx FIFO Data Count Trigger Register */ + + SCIx_NR_REGS, + }; +@@ -99,6 +101,10 @@ enum { + #define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK)) + + /* SCFCR (FIFO Control Register) */ ++#define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */ ++#define SCFCR_RTRG0 BIT(6) ++#define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */ ++#define SCFCR_TTRG0 BIT(4) + #define SCFCR_MCE BIT(3) /* Modem Control Enable */ + #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */ + #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */ diff --git a/patches.renesas/0229-serial-sh-sci-consider-DR-data-ready-bit-adequately.patch b/patches.renesas/0229-serial-sh-sci-consider-DR-data-ready-bit-adequately.patch new file mode 100644 index 0000000000000..5a44a7182af74 --- /dev/null +++ b/patches.renesas/0229-serial-sh-sci-consider-DR-data-ready-bit-adequately.patch @@ -0,0 +1,31 @@ +From 3be3a15c397dad6bbe7de365f533af405306690b Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Thu, 2 Feb 2017 18:10:15 +0100 +Subject: [PATCH 229/255] serial: sh-sci: consider DR (data ready) bit + adequately + +To allow operation with a higher RX FIFO interrupt threshold in PIO +mode, it is necessary to consider the DR bit ("FIFO not full, but no +data received for 1.5 frames") as an indicator that data can be read. +Otherwise the driver will let data rot in the FIFO until the threshold +is reached. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 88641c79c501735efe3b638ccad57ec077ed47f7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/tty/serial/sh-sci.h ++++ b/drivers/tty/serial/sh-sci.h +@@ -151,7 +151,7 @@ enum { + #define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */ + + #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) +-#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) ++#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF) + #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) + #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) + #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) diff --git a/patches.renesas/0230-serial-sh-sci-implement-FIFO-threshold-register-sett.patch b/patches.renesas/0230-serial-sh-sci-implement-FIFO-threshold-register-sett.patch new file mode 100644 index 0000000000000..e0452bd8794e1 --- /dev/null +++ b/patches.renesas/0230-serial-sh-sci-implement-FIFO-threshold-register-sett.patch @@ -0,0 +1,85 @@ +From afc2193b96640358512cc4cafbda052da42bd4db Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Thu, 2 Feb 2017 18:10:16 +0100 +Subject: [PATCH 230/255] serial: sh-sci: implement FIFO threshold register + setting + +Sets the closest match for a desired RX trigger level. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit a380ed461f66d1b843cf13380a43a5fe790b8430) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 59 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 59 insertions(+) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -974,6 +974,65 @@ static int sci_handle_breaks(struct uart + return copied; + } + ++static int scif_set_rtrg(struct uart_port *port, int rx_trig) ++{ ++ unsigned int bits; ++ ++ if (rx_trig < 1) ++ rx_trig = 1; ++ if (rx_trig >= port->fifosize) ++ rx_trig = port->fifosize; ++ ++ /* HSCIF can be set to an arbitrary level. */ ++ if (sci_getreg(port, HSRTRGR)->size) { ++ serial_port_out(port, HSRTRGR, rx_trig); ++ return rx_trig; ++ } ++ ++ switch (port->type) { ++ case PORT_SCIF: ++ if (rx_trig < 4) { ++ bits = 0; ++ rx_trig = 1; ++ } else if (rx_trig < 8) { ++ bits = SCFCR_RTRG0; ++ rx_trig = 4; ++ } else if (rx_trig < 14) { ++ bits = SCFCR_RTRG1; ++ rx_trig = 8; ++ } else { ++ bits = SCFCR_RTRG0 | SCFCR_RTRG1; ++ rx_trig = 14; ++ } ++ break; ++ case PORT_SCIFA: ++ case PORT_SCIFB: ++ if (rx_trig < 16) { ++ bits = 0; ++ rx_trig = 1; ++ } else if (rx_trig < 32) { ++ bits = SCFCR_RTRG0; ++ rx_trig = 16; ++ } else if (rx_trig < 48) { ++ bits = SCFCR_RTRG1; ++ rx_trig = 32; ++ } else { ++ bits = SCFCR_RTRG0 | SCFCR_RTRG1; ++ rx_trig = 48; ++ } ++ break; ++ default: ++ WARN(1, "unknown FIFO configuration"); ++ return 1; ++ } ++ ++ serial_port_out(port, SCFCR, ++ (serial_port_in(port, SCFCR) & ++ ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); ++ ++ return rx_trig; ++} ++ + #ifdef CONFIG_SERIAL_SH_SCI_DMA + static void sci_dma_tx_complete(void *arg) + { diff --git a/patches.renesas/0231-serial-sh-sci-increase-RX-FIFO-trigger-defaults-for-.patch b/patches.renesas/0231-serial-sh-sci-increase-RX-FIFO-trigger-defaults-for-.patch new file mode 100644 index 0000000000000..71e14789c691b --- /dev/null +++ b/patches.renesas/0231-serial-sh-sci-increase-RX-FIFO-trigger-defaults-for-.patch @@ -0,0 +1,84 @@ +From 391e4ad5fa7900897f6e7514d0507662f49159a3 Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Fri, 3 Feb 2017 11:38:17 +0100 +Subject: [PATCH 231/255] serial: sh-sci: increase RX FIFO trigger defaults for + (H)SCIF + +Sets reasonable trigger defaults for the various SCIF variants. +Also corrects the FIFO size for SH7705-style ports. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 18e8cf159177100e69d528293f8cf6875c0b1bca) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 29 ++++++++++++++++++++++++++++- + 1 file changed, 28 insertions(+), 1 deletion(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -148,6 +148,7 @@ struct sci_port { + struct timer_list rx_timer; + unsigned int rx_timeout; + #endif ++ int rx_trigger; + + bool has_rtscts; + bool autorts; +@@ -450,7 +451,7 @@ static const struct sci_port_params sci_ + [SCFCR] = { 0x18, 16 }, + [SCFDR] = { 0x1c, 16 }, + }, +- .fifosize = 16, ++ .fifosize = 64, + .overrun_reg = SCxSR, + .overrun_mask = SCIFA_ORER, + .sampling_rate_mask = SCI_SR(16), +@@ -2064,6 +2065,7 @@ static void sci_reset(struct uart_port * + { + const struct plat_sci_reg *reg; + unsigned int status; ++ struct sci_port *s = to_sci_port(port); + + do { + status = serial_port_in(port, SCxSR); +@@ -2083,6 +2085,9 @@ static void sci_reset(struct uart_port * + status &= ~(SCLSR_TO | SCLSR_ORER); + serial_port_out(port, SCLSR, status); + } ++ ++ if (s->rx_trigger > 1) ++ scif_set_rtrg(port, s->rx_trigger); + } + + static void sci_set_termios(struct uart_port *port, struct ktermios *termios, +@@ -2621,6 +2626,28 @@ static int sci_init_single(struct platfo + if (unlikely(sci_port->params == NULL)) + return -EINVAL; + ++ switch (p->type) { ++ case PORT_SCIFB: ++ sci_port->rx_trigger = 48; ++ break; ++ case PORT_HSCIF: ++ sci_port->rx_trigger = 64; ++ break; ++ case PORT_SCIFA: ++ sci_port->rx_trigger = 32; ++ break; ++ case PORT_SCIF: ++ if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) ++ /* RX triggering not implemented for this IP */ ++ sci_port->rx_trigger = 1; ++ else ++ sci_port->rx_trigger = 8; ++ break; ++ default: ++ sci_port->rx_trigger = 1; ++ break; ++ } ++ + /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't + * match the SoC datasheet, this should be investigated. Let platform + * data override the sampling rate for now. diff --git a/patches.renesas/0232-serial-sh-sci-SCIFA-B-RX-FIFO-software-timeout.patch b/patches.renesas/0232-serial-sh-sci-SCIFA-B-RX-FIFO-software-timeout.patch new file mode 100644 index 0000000000000..40a7e320bbb2a --- /dev/null +++ b/patches.renesas/0232-serial-sh-sci-SCIFA-B-RX-FIFO-software-timeout.patch @@ -0,0 +1,190 @@ +From cb0a3e47445a270db1fb100657582efce7674bfd Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Fri, 3 Feb 2017 11:38:18 +0100 +Subject: [PATCH 232/255] serial: sh-sci: SCIFA/B RX FIFO software timeout + +Implements support for FIFO fill thresholds greater than one with software +timeout. + +This mechanism is not possible (or at least not useful) on SCIF family +hardware other than SCIFA and SCIFB because they do not support turning off +the DR hardware timeout interrupt separately from the RI interrupt. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 039403765e5da3c6a4c2cc048c201bfad932033a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 101 +++++++++++++++++++++++++++++--------------- + 1 file changed, 68 insertions(+), 33 deletions(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -148,7 +148,10 @@ struct sci_port { + struct timer_list rx_timer; + unsigned int rx_timeout; + #endif ++ unsigned int rx_frame; + int rx_trigger; ++ struct timer_list rx_fifo_timer; ++ int rx_fifo_timeout; + + bool has_rtscts; + bool autorts; +@@ -1034,6 +1037,24 @@ static int scif_set_rtrg(struct uart_por + return rx_trig; + } + ++static int scif_rtrg_enabled(struct uart_port *port) ++{ ++ if (sci_getreg(port, HSRTRGR)->size) ++ return serial_port_in(port, HSRTRGR) != 0; ++ else ++ return (serial_port_in(port, SCFCR) & ++ (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; ++} ++ ++static void rx_fifo_timer_fn(unsigned long arg) ++{ ++ struct sci_port *s = (struct sci_port *)arg; ++ struct uart_port *port = &s->port; ++ ++ dev_dbg(port->dev, "Rx timed out\n"); ++ scif_set_rtrg(port, 1); ++} ++ + #ifdef CONFIG_SERIAL_SH_SCI_DMA + static void sci_dma_tx_complete(void *arg) + { +@@ -1473,10 +1494,10 @@ static inline void sci_free_dma(struct u + + static irqreturn_t sci_rx_interrupt(int irq, void *ptr) + { +-#ifdef CONFIG_SERIAL_SH_SCI_DMA + struct uart_port *port = ptr; + struct sci_port *s = to_sci_port(port); + ++#ifdef CONFIG_SERIAL_SH_SCI_DMA + if (s->chan_rx) { + u16 scr = serial_port_in(port, SCSCR); + u16 ssr = serial_port_in(port, SCxSR); +@@ -1501,6 +1522,14 @@ static irqreturn_t sci_rx_interrupt(int + } + #endif + ++ if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { ++ if (!scif_rtrg_enabled(port)) ++ scif_set_rtrg(port, s->rx_trigger); ++ ++ mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( ++ s->rx_frame * s->rx_fifo_timeout, 1000)); ++ } ++ + /* I think sci_receive_chars has to be called irrespective + * of whether the I_IXOFF is set, otherwise, how is the interrupt + * to be disabled? +@@ -2086,14 +2115,21 @@ static void sci_reset(struct uart_port * + serial_port_out(port, SCLSR, status); + } + +- if (s->rx_trigger > 1) +- scif_set_rtrg(port, s->rx_trigger); ++ if (s->rx_trigger > 1) { ++ if (s->rx_fifo_timeout) { ++ scif_set_rtrg(port, 1); ++ setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn, ++ (unsigned long)s); ++ } else { ++ scif_set_rtrg(port, s->rx_trigger); ++ } ++ } + } + + static void sci_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) + { +- unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i; ++ unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; + unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; + unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; + struct sci_port *s = to_sci_port(port); +@@ -2293,7 +2329,6 @@ done: + sci_set_mctrl(port, port->mctrl); + } + +-#ifdef CONFIG_SERIAL_SH_SCI_DMA + /* + * Calculate delay for 2 DMA buffers (4 FIFO). + * See serial_core.c::uart_update_timeout(). +@@ -2304,36 +2339,34 @@ done: + * value obtained by this formula is too small. Therefore, if the value + * is smaller than 20ms, use 20ms as the timeout value for DMA. + */ +- if (s->chan_rx) { +- unsigned int bits; ++ /* byte size and parity */ ++ switch (termios->c_cflag & CSIZE) { ++ case CS5: ++ bits = 7; ++ break; ++ case CS6: ++ bits = 8; ++ break; ++ case CS7: ++ bits = 9; ++ break; ++ default: ++ bits = 10; ++ break; ++ } + +- /* byte size and parity */ +- switch (termios->c_cflag & CSIZE) { +- case CS5: +- bits = 7; +- break; +- case CS6: +- bits = 8; +- break; +- case CS7: +- bits = 9; +- break; +- default: +- bits = 10; +- break; +- } ++ if (termios->c_cflag & CSTOPB) ++ bits++; ++ if (termios->c_cflag & PARENB) ++ bits++; + +- if (termios->c_cflag & CSTOPB) +- bits++; +- if (termios->c_cflag & PARENB) +- bits++; +- s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) / +- (baud / 10), 10); +- dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n", +- s->rx_timeout * 1000 / HZ, port->timeout); +- if (s->rx_timeout < msecs_to_jiffies(20)) +- s->rx_timeout = msecs_to_jiffies(20); +- } ++ s->rx_frame = (100 * bits * HZ) / (baud / 10); ++#ifdef CONFIG_SERIAL_SH_SCI_DMA ++ s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000); ++ dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n", ++ s->rx_timeout * 1000 / HZ, port->timeout); ++ if (s->rx_timeout < msecs_to_jiffies(20)) ++ s->rx_timeout = msecs_to_jiffies(20); + #endif + + if ((termios->c_cflag & CREAD) != 0) +@@ -2648,6 +2681,8 @@ static int sci_init_single(struct platfo + break; + } + ++ sci_port->rx_fifo_timeout = 0; ++ + /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't + * match the SoC datasheet, this should be investigated. Let platform + * data override the sampling rate for now. diff --git a/patches.renesas/0233-serial-sh-sci-make-RX-FIFO-parameters-tunable-via-sy.patch b/patches.renesas/0233-serial-sh-sci-make-RX-FIFO-parameters-tunable-via-sy.patch new file mode 100644 index 0000000000000..44e4ee5fccc32 --- /dev/null +++ b/patches.renesas/0233-serial-sh-sci-make-RX-FIFO-parameters-tunable-via-sy.patch @@ -0,0 +1,128 @@ +From a13ec4fba53f0672fe1836564bbe4208e63d4a22 Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Fri, 3 Feb 2017 11:38:19 +0100 +Subject: [PATCH 233/255] serial: sh-sci: make RX FIFO parameters tunable via + sysfs + +Allows tuning of the RX FIFO fill threshold and timeout. (The latter is +only applicable to SCIFA and SCIFB). + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 5d23188a473da0b2fe6849ccf03578eebfead30e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 87 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 87 insertions(+) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -1055,6 +1055,66 @@ static void rx_fifo_timer_fn(unsigned lo + scif_set_rtrg(port, 1); + } + ++static ssize_t rx_trigger_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct uart_port *port = dev_get_drvdata(dev); ++ struct sci_port *sci = to_sci_port(port); ++ ++ return sprintf(buf, "%d\n", sci->rx_trigger); ++} ++ ++static ssize_t rx_trigger_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, ++ size_t count) ++{ ++ struct uart_port *port = dev_get_drvdata(dev); ++ struct sci_port *sci = to_sci_port(port); ++ long r; ++ ++ if (kstrtol(buf, 0, &r) == -EINVAL) ++ return -EINVAL; ++ sci->rx_trigger = scif_set_rtrg(port, r); ++ scif_set_rtrg(port, 1); ++ return count; ++} ++ ++static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store); ++ ++static ssize_t rx_fifo_timeout_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct uart_port *port = dev_get_drvdata(dev); ++ struct sci_port *sci = to_sci_port(port); ++ ++ return sprintf(buf, "%d\n", sci->rx_fifo_timeout); ++} ++ ++static ssize_t rx_fifo_timeout_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, ++ size_t count) ++{ ++ struct uart_port *port = dev_get_drvdata(dev); ++ struct sci_port *sci = to_sci_port(port); ++ long r; ++ ++ if (kstrtol(buf, 0, &r) == -EINVAL) ++ return -EINVAL; ++ sci->rx_fifo_timeout = r; ++ scif_set_rtrg(port, 1); ++ if (r > 0) ++ setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn, ++ (unsigned long)sci); ++ return count; ++} ++ ++static DEVICE_ATTR(rx_fifo_timeout, 0644, rx_fifo_timeout_show, rx_fifo_timeout_store); ++ ++ + #ifdef CONFIG_SERIAL_SH_SCI_DMA + static void sci_dma_tx_complete(void *arg) + { +@@ -2892,6 +2952,15 @@ static int sci_remove(struct platform_de + + sci_cleanup_single(port); + ++ if (port->port.fifosize > 1) { ++ sysfs_remove_file(&dev->dev.kobj, ++ &dev_attr_rx_fifo_trigger.attr); ++ } ++ if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB) { ++ sysfs_remove_file(&dev->dev.kobj, ++ &dev_attr_rx_fifo_timeout.attr); ++ } ++ + return 0; + } + +@@ -3057,6 +3126,24 @@ static int sci_probe(struct platform_dev + if (ret) + return ret; + ++ if (sp->port.fifosize > 1) { ++ ret = sysfs_create_file(&dev->dev.kobj, ++ &dev_attr_rx_fifo_trigger.attr); ++ if (ret) ++ return ret; ++ } ++ if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB) { ++ ret = sysfs_create_file(&dev->dev.kobj, ++ &dev_attr_rx_fifo_timeout.attr); ++ if (ret) { ++ if (sp->port.fifosize > 1) { ++ sysfs_remove_file(&dev->dev.kobj, ++ &dev_attr_rx_fifo_trigger.attr); ++ } ++ return ret; ++ } ++ } ++ + #ifdef CONFIG_SH_STANDARD_BIOS + sh_bios_gdb_detach(); + #endif diff --git a/patches.renesas/0234-serial-sh-sci-fix-hardware-RX-trigger-level-setting.patch b/patches.renesas/0234-serial-sh-sci-fix-hardware-RX-trigger-level-setting.patch new file mode 100644 index 0000000000000..3c16d3165f19d --- /dev/null +++ b/patches.renesas/0234-serial-sh-sci-fix-hardware-RX-trigger-level-setting.patch @@ -0,0 +1,49 @@ +From 5ba3522b63be99e95e6aa4e1dfaae4143db04ea9 Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Wed, 8 Feb 2017 18:31:14 +0100 +Subject: [PATCH 234/255] serial: sh-sci: fix hardware RX trigger level setting + +1. Do not set the RX trigger level for software timeout devices on reset; +there is no timeout by default, and data will rot. +2. Do set the RX trigger level for hardware timeout devices when set +via sysfs attribute. + +Fixes SCIFA-type serial consoles. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 90afa5255f5c5ae67c869918e4c5f60b8580db70) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -1076,8 +1076,11 @@ static ssize_t rx_trigger_store(struct d + + if (kstrtol(buf, 0, &r) == -EINVAL) + return -EINVAL; ++ + sci->rx_trigger = scif_set_rtrg(port, r); +- scif_set_rtrg(port, 1); ++ if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) ++ scif_set_rtrg(port, 1); ++ + return count; + } + +@@ -2181,7 +2184,11 @@ static void sci_reset(struct uart_port * + setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn, + (unsigned long)s); + } else { +- scif_set_rtrg(port, s->rx_trigger); ++ if (port->type == PORT_SCIFA || ++ port->type == PORT_SCIFB) ++ scif_set_rtrg(port, 1); ++ else ++ scif_set_rtrg(port, s->rx_trigger); + } + } + } diff --git a/patches.renesas/0235-drm-bridge-Link-encoder-and-bridge-in-core-code.patch b/patches.renesas/0235-drm-bridge-Link-encoder-and-bridge-in-core-code.patch new file mode 100644 index 0000000000000..0f3efa42c3980 --- /dev/null +++ b/patches.renesas/0235-drm-bridge-Link-encoder-and-bridge-in-core-code.patch @@ -0,0 +1,577 @@ +From 4e2687321ce2c5283fe173d9986a03179dfe9c9c Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 28 Nov 2016 17:59:08 +0200 +Subject: [PATCH 235/255] drm: bridge: Link encoder and bridge in core code + +Instead of linking encoders and bridges in every driver (and getting it +wrong half of the time, as many drivers forget to set the drm_bridge +encoder pointer), do so in core code. The drm_bridge_attach() function +needs the encoder and optional previous bridge to perform that task, +update all the callers. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Stefan Agner <stefan@agner.ch> # For DCU +Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> # For atmel-hlcdc +Acked-by: Vincent Abriou <vincent.abriou@st.com> # For STI +Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> # For sun4i +Acked-by: Xinliang Liu <z.liuxinliang@hisilicon.com> # For hisilicon +Acked-by: Jyri Sarha <jsarha@ti.com> # For tilcdc +Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/1481709550-29226-4-git-send-email-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 3bb80f249525c059572d4bc89ac77ac2e511bcbe) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + drivers/gpu/drm/tilcdc/tilcdc_external.c +--- + drivers/gpu/drm/arc/arcpgu_hdmi.c | 5 -- + drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c | 4 - + drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 4 - + drivers/gpu/drm/bridge/dw-hdmi.c | 3 - + drivers/gpu/drm/drm_bridge.c | 48 +++++++++++++++------ + drivers/gpu/drm/drm_simple_kms_helper.c | 4 - + drivers/gpu/drm/exynos/exynos_dp.c | 5 -- + drivers/gpu/drm/exynos/exynos_drm_dsi.c | 6 -- + drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c | 5 -- + drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 5 -- + drivers/gpu/drm/imx/imx-ldb.c | 6 -- + drivers/gpu/drm/imx/parallel-display.c | 4 - + drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +-- + drivers/gpu/drm/mediatek/mtk_dsi.c | 24 +--------- + drivers/gpu/drm/mediatek/mtk_hdmi.c | 11 ++-- + drivers/gpu/drm/msm/dsi/dsi_manager.c | 17 ++++--- + drivers/gpu/drm/msm/edp/edp_bridge.c | 2 + drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 2 + drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c | 5 -- + drivers/gpu/drm/sti/sti_dvo.c | 3 - + drivers/gpu/drm/sti/sti_hda.c | 3 - + drivers/gpu/drm/sti/sti_hdmi.c | 3 - + drivers/gpu/drm/sun4i/sun4i_rgb.c | 13 ++--- + include/drm/drm_bridge.h | 3 - + 24 files changed, 85 insertions(+), 108 deletions(-) + +--- a/drivers/gpu/drm/arc/arcpgu_hdmi.c ++++ b/drivers/gpu/drm/arc/arcpgu_hdmi.c +@@ -47,10 +47,7 @@ int arcpgu_drm_hdmi_init(struct drm_devi + return ret; + + /* Link drm_bridge to encoder */ +- bridge->encoder = encoder; +- encoder->bridge = bridge; +- +- ret = drm_bridge_attach(drm, bridge); ++ ret = drm_bridge_attach(encoder, bridge, NULL); + if (ret) + drm_encoder_cleanup(encoder); + +--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c ++++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c +@@ -230,9 +230,7 @@ static int atmel_hlcdc_attach_endpoint(s + of_node_put(np); + + if (bridge) { +- output->encoder.bridge = bridge; +- bridge->encoder = &output->encoder; +- ret = drm_bridge_attach(dev, bridge); ++ ret = drm_bridge_attach(&output->encoder, bridge, NULL); + if (!ret) + return 0; + } +--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c ++++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +@@ -1227,12 +1227,10 @@ static int analogix_dp_create_bridge(str + + dp->bridge = bridge; + +- dp->encoder->bridge = bridge; + bridge->driver_private = dp; +- bridge->encoder = dp->encoder; + bridge->funcs = &analogix_dp_bridge_funcs; + +- ret = drm_bridge_attach(drm_dev, bridge); ++ ret = drm_bridge_attach(dp->encoder, bridge, NULL); + if (ret) { + DRM_ERROR("failed to attach drm bridge\n"); + return -EINVAL; +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -1841,13 +1841,12 @@ static int dw_hdmi_register(struct drm_d + hdmi->bridge = bridge; + bridge->driver_private = hdmi; + bridge->funcs = &dw_hdmi_bridge_funcs; +- ret = drm_bridge_attach(drm, bridge); ++ ret = drm_bridge_attach(encoder, bridge, NULL); + if (ret) { + DRM_ERROR("Failed to initialize bridge with drm\n"); + return -EINVAL; + } + +- encoder->bridge = bridge; + hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD; + + drm_connector_helper_add(&hdmi->connector, +--- a/drivers/gpu/drm/drm_bridge.c ++++ b/drivers/gpu/drm/drm_bridge.c +@@ -26,6 +26,7 @@ + #include <linux/mutex.h> + + #include <drm/drm_bridge.h> ++#include <drm/drm_encoder.h> + + /** + * DOC: overview +@@ -92,32 +93,53 @@ void drm_bridge_remove(struct drm_bridge + EXPORT_SYMBOL(drm_bridge_remove); + + /** +- * drm_bridge_attach - associate given bridge to our DRM device ++ * drm_bridge_attach - attach the bridge to an encoder's chain + * +- * @dev: DRM device +- * @bridge: bridge control structure +- * +- * Called by a kms driver to link one of our encoder/bridge to the given +- * bridge. ++ * @encoder: DRM encoder ++ * @bridge: bridge to attach ++ * @previous: previous bridge in the chain (optional) ++ * ++ * Called by a kms driver to link the bridge to an encoder's chain. The previous ++ * argument specifies the previous bridge in the chain. If NULL, the bridge is ++ * linked directly at the encoder's output. Otherwise it is linked at the ++ * previous bridge's output. + * +- * Note that setting up links between the bridge and our encoder/bridge +- * objects needs to be handled by the kms driver itself. ++ * If non-NULL the previous bridge must be already attached by a call to this ++ * function. + * + * RETURNS: + * Zero on success, error code on failure + */ +-int drm_bridge_attach(struct drm_device *dev, struct drm_bridge *bridge) ++int drm_bridge_attach(struct drm_encoder *encoder, struct drm_bridge *bridge, ++ struct drm_bridge *previous) + { +- if (!dev || !bridge) ++ int ret; ++ ++ if (!encoder || !bridge) ++ return -EINVAL; ++ ++ if (previous && (!previous->dev || previous->encoder != encoder)) + return -EINVAL; + + if (bridge->dev) + return -EBUSY; + +- bridge->dev = dev; ++ bridge->dev = encoder->dev; ++ bridge->encoder = encoder; + +- if (bridge->funcs->attach) +- return bridge->funcs->attach(bridge); ++ if (bridge->funcs->attach) { ++ ret = bridge->funcs->attach(bridge); ++ if (ret < 0) { ++ bridge->dev = NULL; ++ bridge->encoder = NULL; ++ return ret; ++ } ++ } ++ ++ if (previous) ++ previous->next = bridge; ++ else ++ encoder->bridge = bridge; + + return 0; + } +--- a/drivers/gpu/drm/drm_simple_kms_helper.c ++++ b/drivers/gpu/drm/drm_simple_kms_helper.c +@@ -182,9 +182,7 @@ static const struct drm_plane_funcs drm_ + int drm_simple_display_pipe_attach_bridge(struct drm_simple_display_pipe *pipe, + struct drm_bridge *bridge) + { +- bridge->encoder = &pipe->encoder; +- pipe->encoder.bridge = bridge; +- return drm_bridge_attach(pipe->encoder.dev, bridge); ++ return drm_bridge_attach(&pipe->encoder, bridge, NULL); + } + EXPORT_SYMBOL(drm_simple_display_pipe_attach_bridge); + +--- a/drivers/gpu/drm/exynos/exynos_dp.c ++++ b/drivers/gpu/drm/exynos/exynos_dp.c +@@ -99,7 +99,6 @@ static int exynos_dp_bridge_attach(struc + struct drm_connector *connector) + { + struct exynos_dp_device *dp = to_dp(plat_data); +- struct drm_encoder *encoder = &dp->encoder; + int ret; + + drm_connector_register(connector); +@@ -107,9 +106,7 @@ static int exynos_dp_bridge_attach(struc + + /* Pre-empt DP connector creation if there's a bridge */ + if (dp->ptn_bridge) { +- bridge->next = dp->ptn_bridge; +- dp->ptn_bridge->encoder = encoder; +- ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge); ++ ret = drm_bridge_attach(&dp->encoder, dp->ptn_bridge, bridge); + if (ret) { + DRM_ERROR("Failed to attach bridge to drm\n"); + bridge->next = NULL; +--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c ++++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c +@@ -1718,10 +1718,8 @@ static int exynos_dsi_bind(struct device + } + + bridge = of_drm_find_bridge(dsi->bridge_node); +- if (bridge) { +- encoder->bridge = bridge; +- drm_bridge_attach(drm_dev, bridge); +- } ++ if (bridge) ++ drm_bridge_attach(encoder, bridge, NULL); + + return mipi_dsi_host_register(&dsi->dsi_host); + } +--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c ++++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c +@@ -160,10 +160,7 @@ static int fsl_dcu_attach_endpoint(struc + if (!bridge) + return -ENODEV; + +- fsl_dev->encoder.bridge = bridge; +- bridge->encoder = &fsl_dev->encoder; +- +- return drm_bridge_attach(fsl_dev->drm, bridge); ++ return drm_bridge_attach(&fsl_dev->encoder, bridge, NULL); + } + + int fsl_dcu_create_outputs(struct fsl_dcu_drm_device *fsl_dev) +--- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c ++++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c +@@ -709,10 +709,7 @@ static int dsi_bridge_init(struct drm_de + int ret; + + /* associate the bridge to dsi encoder */ +- encoder->bridge = bridge; +- bridge->encoder = encoder; +- +- ret = drm_bridge_attach(dev, bridge); ++ ret = drm_bridge_attach(encoder, bridge, NULL); + if (ret) { + DRM_ERROR("failed to attach external bridge\n"); + return ret; +--- a/drivers/gpu/drm/imx/imx-ldb.c ++++ b/drivers/gpu/drm/imx/imx-ldb.c +@@ -466,10 +466,8 @@ static int imx_ldb_register(struct drm_d + DRM_MODE_ENCODER_LVDS, NULL); + + if (imx_ldb_ch->bridge) { +- imx_ldb_ch->bridge->encoder = encoder; +- +- imx_ldb_ch->encoder.bridge = imx_ldb_ch->bridge; +- ret = drm_bridge_attach(drm, imx_ldb_ch->bridge); ++ ret = drm_bridge_attach(&imx_ldb_ch->encoder, ++ imx_ldb_ch->bridge, NULL); + if (ret) { + DRM_ERROR("Failed to initialize bridge with drm\n"); + return ret; +--- a/drivers/gpu/drm/imx/parallel-display.c ++++ b/drivers/gpu/drm/imx/parallel-display.c +@@ -191,9 +191,7 @@ static int imx_pd_register(struct drm_de + drm_panel_attach(imxpd->panel, &imxpd->connector); + + if (imxpd->bridge) { +- imxpd->bridge->encoder = encoder; +- encoder->bridge = imxpd->bridge; +- ret = drm_bridge_attach(drm, imxpd->bridge); ++ ret = drm_bridge_attach(encoder, imxpd->bridge, NULL); + if (ret < 0) { + dev_err(imxpd->dev, "failed to attach bridge: %d\n", + ret); +--- a/drivers/gpu/drm/mediatek/mtk_dpi.c ++++ b/drivers/gpu/drm/mediatek/mtk_dpi.c +@@ -63,6 +63,7 @@ enum mtk_dpi_out_color_format { + struct mtk_dpi { + struct mtk_ddp_comp ddp_comp; + struct drm_encoder encoder; ++ struct drm_bridge *bridge; + void __iomem *regs; + struct device *dev; + struct clk *engine_clk; +@@ -620,8 +621,7 @@ static int mtk_dpi_bind(struct device *d + /* Currently DPI0 is fixed to be driven by OVL1 */ + dpi->encoder.possible_crtcs = BIT(1); + +- dpi->encoder.bridge->encoder = &dpi->encoder; +- ret = drm_bridge_attach(dpi->encoder.dev, dpi->encoder.bridge); ++ ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL); + if (ret) { + dev_err(dev, "Failed to attach bridge: %d\n", ret); + goto err_cleanup; +@@ -718,9 +718,9 @@ static int mtk_dpi_probe(struct platform + + dev_info(dev, "Found bridge node: %s\n", bridge_node->full_name); + +- dpi->encoder.bridge = of_drm_find_bridge(bridge_node); ++ dpi->bridge = of_drm_find_bridge(bridge_node); + of_node_put(bridge_node); +- if (!dpi->encoder.bridge) ++ if (!dpi->bridge) + return -EPROBE_DEFER; + + comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI); +--- a/drivers/gpu/drm/mediatek/mtk_dsi.c ++++ b/drivers/gpu/drm/mediatek/mtk_dsi.c +@@ -622,26 +622,6 @@ static const struct drm_connector_helper + .get_modes = mtk_dsi_connector_get_modes, + }; + +-static int mtk_drm_attach_bridge(struct drm_bridge *bridge, +- struct drm_encoder *encoder) +-{ +- int ret; +- +- if (!bridge) +- return -ENOENT; +- +- encoder->bridge = bridge; +- bridge->encoder = encoder; +- ret = drm_bridge_attach(encoder->dev, bridge); +- if (ret) { +- DRM_ERROR("Failed to attach bridge to drm\n"); +- encoder->bridge = NULL; +- bridge->encoder = NULL; +- } +- +- return ret; +-} +- + static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi) + { + int ret; +@@ -692,8 +672,10 @@ static int mtk_dsi_create_conn_enc(struc + dsi->encoder.possible_crtcs = 1; + + /* If there's a bridge, attach to it and let it create the connector */ +- ret = mtk_drm_attach_bridge(dsi->bridge, &dsi->encoder); ++ ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL); + if (ret) { ++ DRM_ERROR("Failed to attach bridge to drm\n"); ++ + /* Otherwise create our own connector and attach to a panel */ + ret = mtk_dsi_create_connector(drm, dsi); + if (ret) +--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c ++++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c +@@ -149,6 +149,7 @@ struct hdmi_audio_param { + + struct mtk_hdmi { + struct drm_bridge bridge; ++ struct drm_bridge *next_bridge; + struct drm_connector conn; + struct device *dev; + struct phy *phy; +@@ -1314,9 +1315,9 @@ static int mtk_hdmi_bridge_attach(struct + return ret; + } + +- if (bridge->next) { +- bridge->next->encoder = bridge->encoder; +- ret = drm_bridge_attach(bridge->encoder->dev, bridge->next); ++ if (hdmi->next_bridge) { ++ ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, ++ bridge); + if (ret) { + dev_err(hdmi->dev, + "Failed to attach external bridge: %d\n", ret); +@@ -1510,8 +1511,8 @@ static int mtk_hdmi_dt_parse_pdata(struc + of_node_put(ep); + + if (!of_device_is_compatible(remote, "hdmi-connector")) { +- hdmi->bridge.next = of_drm_find_bridge(remote); +- if (!hdmi->bridge.next) { ++ hdmi->next_bridge = of_drm_find_bridge(remote); ++ if (!hdmi->next_bridge) { + dev_err(dev, "Waiting for external bridge\n"); + of_node_put(remote); + return -EPROBE_DEFER; +--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c ++++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c +@@ -579,6 +579,7 @@ struct drm_bridge *msm_dsi_manager_bridg + struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); + struct drm_bridge *bridge = NULL; + struct dsi_bridge *dsi_bridge; ++ struct drm_encoder *encoder; + int ret; + + dsi_bridge = devm_kzalloc(msm_dsi->dev->dev, +@@ -590,10 +591,18 @@ struct drm_bridge *msm_dsi_manager_bridg + + dsi_bridge->id = id; + ++ /* ++ * HACK: we may not know the external DSI bridge device's mode ++ * flags here. We'll get to know them only when the device ++ * attaches to the dsi host. For now, assume the bridge supports ++ * DSI video mode ++ */ ++ encoder = msm_dsi->encoders[MSM_DSI_VIDEO_ENCODER_ID]; ++ + bridge = &dsi_bridge->base; + bridge->funcs = &dsi_mgr_bridge_funcs; + +- ret = drm_bridge_attach(msm_dsi->dev, bridge); ++ ret = drm_bridge_attach(encoder, bridge, NULL); + if (ret) + goto fail; + +@@ -628,11 +637,7 @@ struct drm_connector *msm_dsi_manager_ex + encoder = msm_dsi->encoders[MSM_DSI_VIDEO_ENCODER_ID]; + + /* link the internal dsi bridge to the external bridge */ +- int_bridge->next = ext_bridge; +- /* set the external bridge's encoder as dsi's encoder */ +- ext_bridge->encoder = encoder; +- +- drm_bridge_attach(dev, ext_bridge); ++ drm_bridge_attach(encoder, ext_bridge, int_bridge); + + /* + * we need the drm_connector created by the external bridge +--- a/drivers/gpu/drm/msm/edp/edp_bridge.c ++++ b/drivers/gpu/drm/msm/edp/edp_bridge.c +@@ -106,7 +106,7 @@ struct drm_bridge *msm_edp_bridge_init(s + bridge = &edp_bridge->base; + bridge->funcs = &edp_bridge_funcs; + +- ret = drm_bridge_attach(edp->dev, bridge); ++ ret = drm_bridge_attach(edp->encoder, bridge, NULL); + if (ret) + goto fail; + +--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c ++++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +@@ -227,7 +227,7 @@ struct drm_bridge *msm_hdmi_bridge_init( + bridge = &hdmi_bridge->base; + bridge->funcs = &msm_hdmi_bridge_funcs; + +- ret = drm_bridge_attach(hdmi->dev, bridge); ++ ret = drm_bridge_attach(hdmi->encoder, bridge, NULL); + if (ret) + goto fail; + +--- a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c +@@ -124,10 +124,7 @@ int rcar_du_hdmienc_init(struct rcar_du_ + hdmienc->renc = renc; + + /* Link the bridge to the encoder. */ +- bridge->encoder = encoder; +- encoder->bridge = bridge; +- +- ret = drm_bridge_attach(rcdu->ddev, bridge); ++ ret = drm_bridge_attach(encoder, bridge, NULL); + if (ret) { + drm_encoder_cleanup(encoder); + return ret; +--- a/drivers/gpu/drm/sti/sti_dvo.c ++++ b/drivers/gpu/drm/sti/sti_dvo.c +@@ -478,14 +478,13 @@ static int sti_dvo_bind(struct device *d + return err; + } + +- err = drm_bridge_attach(drm_dev, bridge); ++ err = drm_bridge_attach(encoder, bridge, NULL); + if (err) { + DRM_ERROR("Failed to attach bridge\n"); + return err; + } + + dvo->bridge = bridge; +- encoder->bridge = bridge; + connector->encoder = encoder; + dvo->encoder = encoder; + +--- a/drivers/gpu/drm/sti/sti_hda.c ++++ b/drivers/gpu/drm/sti/sti_hda.c +@@ -707,9 +707,8 @@ static int sti_hda_bind(struct device *d + + bridge->driver_private = hda; + bridge->funcs = &sti_hda_bridge_funcs; +- drm_bridge_attach(drm_dev, bridge); ++ drm_bridge_attach(encoder, bridge, NULL); + +- encoder->bridge = bridge; + connector->encoder = encoder; + + drm_connector = (struct drm_connector *)connector; +--- a/drivers/gpu/drm/sti/sti_hdmi.c ++++ b/drivers/gpu/drm/sti/sti_hdmi.c +@@ -1308,9 +1308,8 @@ static int sti_hdmi_bind(struct device * + + bridge->driver_private = hdmi; + bridge->funcs = &sti_hdmi_bridge_funcs; +- drm_bridge_attach(drm_dev, bridge); ++ drm_bridge_attach(encoder, bridge, NULL); + +- encoder->bridge = bridge; + connector->encoder = encoder; + + drm_connector = (struct drm_connector *)connector; +--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c ++++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c +@@ -208,6 +208,7 @@ int sun4i_rgb_init(struct drm_device *dr + struct sun4i_drv *drv = drm->dev_private; + struct sun4i_tcon *tcon = drv->tcon; + struct drm_encoder *encoder; ++ struct drm_bridge *bridge; + struct sun4i_rgb *rgb; + int ret; + +@@ -218,8 +219,8 @@ int sun4i_rgb_init(struct drm_device *dr + encoder = &rgb->encoder; + + tcon->panel = sun4i_tcon_find_panel(tcon->dev->of_node); +- encoder->bridge = sun4i_tcon_find_bridge(tcon->dev->of_node); +- if (IS_ERR(tcon->panel) && IS_ERR(encoder->bridge)) { ++ bridge = sun4i_tcon_find_bridge(tcon->dev->of_node); ++ if (IS_ERR(tcon->panel) && IS_ERR(bridge)) { + dev_info(drm->dev, "No panel or bridge found... RGB output disabled\n"); + return 0; + } +@@ -260,16 +261,12 @@ int sun4i_rgb_init(struct drm_device *dr + } + } + +- if (!IS_ERR(encoder->bridge)) { +- encoder->bridge->encoder = &rgb->encoder; +- +- ret = drm_bridge_attach(drm, encoder->bridge); ++ if (!IS_ERR(bridge)) { ++ ret = drm_bridge_attach(encoder, bridge, NULL); + if (ret) { + dev_err(drm->dev, "Couldn't attach our bridge\n"); + goto err_cleanup_connector; + } +- } else { +- encoder->bridge = NULL; + } + + return 0; +--- a/include/drm/drm_bridge.h ++++ b/include/drm/drm_bridge.h +@@ -201,7 +201,8 @@ struct drm_bridge { + int drm_bridge_add(struct drm_bridge *bridge); + void drm_bridge_remove(struct drm_bridge *bridge); + struct drm_bridge *of_drm_find_bridge(struct device_node *np); +-int drm_bridge_attach(struct drm_device *dev, struct drm_bridge *bridge); ++int drm_bridge_attach(struct drm_encoder *encoder, struct drm_bridge *bridge, ++ struct drm_bridge *previous); + void drm_bridge_detach(struct drm_bridge *bridge); + + bool drm_bridge_mode_fixup(struct drm_bridge *bridge, diff --git a/patches.renesas/0236-drm-bridge-dw-hdmi-Merge-__hdmi_phy_i2c_write-and-hd.patch b/patches.renesas/0236-drm-bridge-dw-hdmi-Merge-__hdmi_phy_i2c_write-and-hd.patch new file mode 100644 index 0000000000000..76787d088ec50 --- /dev/null +++ b/patches.renesas/0236-drm-bridge-dw-hdmi-Merge-__hdmi_phy_i2c_write-and-hd.patch @@ -0,0 +1,45 @@ +From 751759a33255eba913de232c981a99802dca7b67 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:28:51 +0200 +Subject: [PATCH 236/255] drm: bridge: dw-hdmi: Merge __hdmi_phy_i2c_write and + hdmi_phy_i2c_write + +The latter is just an int wrapper around the former void function that +unconditionally returns 0. As the return value is never checked, merge +the two functions into one. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-2-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit cc7e96232763ff33418b088b436a564441347b15) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 9 +-------- + 1 file changed, 1 insertion(+), 8 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -868,7 +868,7 @@ static bool hdmi_phy_wait_i2c_done(struc + return true; + } + +-static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, ++static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, + unsigned char addr) + { + hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); +@@ -882,13 +882,6 @@ static void __hdmi_phy_i2c_write(struct + hdmi_phy_wait_i2c_done(hdmi, 1000); + } + +-static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, +- unsigned char addr) +-{ +- __hdmi_phy_i2c_write(hdmi, data, addr); +- return 0; +-} +- + static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) + { + hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, diff --git a/patches.renesas/0237-drm-bridge-dw-hdmi-Remove-unneeded-arguments-to-bind.patch b/patches.renesas/0237-drm-bridge-dw-hdmi-Remove-unneeded-arguments-to-bind.patch new file mode 100644 index 0000000000000..c80b18fd660f8 --- /dev/null +++ b/patches.renesas/0237-drm-bridge-dw-hdmi-Remove-unneeded-arguments-to-bind.patch @@ -0,0 +1,112 @@ +From a4b757e2e4b85c208eb723d63df4afa04c2f44e3 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:28:52 +0200 +Subject: [PATCH 237/255] drm: bridge: dw-hdmi: Remove unneeded arguments to + bind/unbind functions + +The master argument isn't used. The data argument, a void pointer, is +used by the bind function only where it's cast to a drm_device pointer, +which can easily be obtained from the encoder argument instead. Remove +them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-3-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit ecaa98f1e6f7ed3f79def1861f21ff2eac82b8e9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 8 +++----- + drivers/gpu/drm/imx/dw_hdmi-imx.c | 4 ++-- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 4 ++-- + include/drm/bridge/dw_hdmi.h | 5 ++--- + 4 files changed, 9 insertions(+), 12 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -1854,12 +1854,10 @@ static int dw_hdmi_register(struct drm_d + return 0; + } + +-int dw_hdmi_bind(struct device *dev, struct device *master, +- void *data, struct drm_encoder *encoder, ++int dw_hdmi_bind(struct device *dev, struct drm_encoder *encoder, + struct resource *iores, int irq, + const struct dw_hdmi_plat_data *plat_data) + { +- struct drm_device *drm = data; + struct device_node *np = dev->of_node; + struct platform_device_info pdevinfo; + struct device_node *ddc_node; +@@ -1992,7 +1990,7 @@ int dw_hdmi_bind(struct device *dev, str + if (ret) + goto err_iahb; + +- ret = dw_hdmi_register(drm, hdmi); ++ ret = dw_hdmi_register(encoder->dev, hdmi); + if (ret) + goto err_iahb; + +@@ -2059,7 +2057,7 @@ err_res: + } + EXPORT_SYMBOL_GPL(dw_hdmi_bind); + +-void dw_hdmi_unbind(struct device *dev, struct device *master, void *data) ++void dw_hdmi_unbind(struct device *dev) + { + struct dw_hdmi *hdmi = dev_get_drvdata(dev); + +--- a/drivers/gpu/drm/imx/dw_hdmi-imx.c ++++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c +@@ -249,7 +249,7 @@ static int dw_hdmi_imx_bind(struct devic + drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs, + DRM_MODE_ENCODER_TMDS, NULL); + +- ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data); ++ ret = dw_hdmi_bind(dev, encoder, iores, irq, plat_data); + + /* + * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), +@@ -264,7 +264,7 @@ static int dw_hdmi_imx_bind(struct devic + static void dw_hdmi_imx_unbind(struct device *dev, struct device *master, + void *data) + { +- return dw_hdmi_unbind(dev, master, data); ++ return dw_hdmi_unbind(dev); + } + + static const struct component_ops dw_hdmi_imx_ops = { +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -301,7 +301,7 @@ static int dw_hdmi_rockchip_bind(struct + drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs, + DRM_MODE_ENCODER_TMDS, NULL); + +- ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data); ++ ret = dw_hdmi_bind(dev, encoder, iores, irq, plat_data); + + /* + * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), +@@ -316,7 +316,7 @@ static int dw_hdmi_rockchip_bind(struct + static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, + void *data) + { +- return dw_hdmi_unbind(dev, master, data); ++ return dw_hdmi_unbind(dev); + } + + static const struct component_ops dw_hdmi_rockchip_ops = { +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -56,9 +56,8 @@ struct dw_hdmi_plat_data { + struct drm_display_mode *mode); + }; + +-void dw_hdmi_unbind(struct device *dev, struct device *master, void *data); +-int dw_hdmi_bind(struct device *dev, struct device *master, +- void *data, struct drm_encoder *encoder, ++void dw_hdmi_unbind(struct device *dev); ++int dw_hdmi_bind(struct device *dev, struct drm_encoder *encoder, + struct resource *iores, int irq, + const struct dw_hdmi_plat_data *plat_data); + diff --git a/patches.renesas/0238-drm-bridge-dw-hdmi-Remove-unused-function-parameter.patch b/patches.renesas/0238-drm-bridge-dw-hdmi-Remove-unused-function-parameter.patch new file mode 100644 index 0000000000000..2883f248f0e63 --- /dev/null +++ b/patches.renesas/0238-drm-bridge-dw-hdmi-Remove-unused-function-parameter.patch @@ -0,0 +1,53 @@ +From 5289ea4234e0a47ef04a44cef8ea71a7b656cfdc Mon Sep 17 00:00:00 2001 +From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:28:53 +0200 +Subject: [PATCH 238/255] drm: bridge: dw-hdmi: Remove unused function + parameter + +The 'prep' parameter passed to hdmi_phy_configure() is useless. It is +hardcoded as 0, and if set, simply prevents the configure function from +executing. + +Remove it. + +Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-4-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit dfa73065d61b6ce57aed90bb0d745c4b6f5b71e7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 7 ++----- + 1 file changed, 2 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -931,7 +931,7 @@ static void dw_hdmi_phy_sel_interface_co + HDMI_PHY_CONF0_SELDIPIF_MASK); + } + +-static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep, ++static int hdmi_phy_configure(struct dw_hdmi *hdmi, + unsigned char res, int cscon) + { + unsigned res_idx; +@@ -941,9 +941,6 @@ static int hdmi_phy_configure(struct dw_ + const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; + const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; + +- if (prep) +- return -EINVAL; +- + switch (res) { + case 0: /* color resolution 0 is 8 bit colour depth */ + case 8: +@@ -1072,7 +1069,7 @@ static int dw_hdmi_phy_init(struct dw_hd + dw_hdmi_phy_enable_powerdown(hdmi, true); + + /* Enable CSC */ +- ret = hdmi_phy_configure(hdmi, 0, 8, cscon); ++ ret = hdmi_phy_configure(hdmi, 8, cscon); + if (ret) + return ret; + } diff --git a/patches.renesas/0239-drm-bridge-dw-hdmi-Embed-drm_bridge-in-struct-dw_hdm.patch b/patches.renesas/0239-drm-bridge-dw-hdmi-Embed-drm_bridge-in-struct-dw_hdm.patch new file mode 100644 index 0000000000000..c066ca5896c65 --- /dev/null +++ b/patches.renesas/0239-drm-bridge-dw-hdmi-Embed-drm_bridge-in-struct-dw_hdm.patch @@ -0,0 +1,57 @@ +From 1067cf87533833fe297ee3c4f3aca74d76f9be58 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:28:54 +0200 +Subject: [PATCH 239/255] drm: bridge: dw-hdmi: Embed drm_bridge in struct + dw_hdmi + +The drm_bridge instance is always needed, there's no point in allocating +it separately. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-5-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 70c963ec4f15a13197524611875168f23acc4a97) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 13 +++---------- + 1 file changed, 3 insertions(+), 10 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -116,7 +116,7 @@ struct dw_hdmi_i2c { + struct dw_hdmi { + struct drm_connector connector; + struct drm_encoder *encoder; +- struct drm_bridge *bridge; ++ struct drm_bridge bridge; + + struct platform_device *audio; + enum dw_hdmi_devtype dev_type; +@@ -1806,7 +1806,7 @@ static irqreturn_t dw_hdmi_irq(int irq, + if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { + dev_dbg(hdmi->dev, "EVENT=%s\n", + phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); +- drm_helper_hpd_irq_event(hdmi->bridge->dev); ++ drm_helper_hpd_irq_event(hdmi->bridge.dev); + } + + hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); +@@ -1819,16 +1819,9 @@ static irqreturn_t dw_hdmi_irq(int irq, + static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi) + { + struct drm_encoder *encoder = hdmi->encoder; +- struct drm_bridge *bridge; ++ struct drm_bridge *bridge = &hdmi->bridge; + int ret; + +- bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL); +- if (!bridge) { +- DRM_ERROR("Failed to allocate drm bridge\n"); +- return -ENOMEM; +- } +- +- hdmi->bridge = bridge; + bridge->driver_private = hdmi; + bridge->funcs = &dw_hdmi_bridge_funcs; + ret = drm_bridge_attach(encoder, bridge, NULL); diff --git a/patches.renesas/0240-drm-bridge-dw-hdmi-Remove-encoder-field-from-struct-.patch b/patches.renesas/0240-drm-bridge-dw-hdmi-Remove-encoder-field-from-struct-.patch new file mode 100644 index 0000000000000..f24c39c355dbb --- /dev/null +++ b/patches.renesas/0240-drm-bridge-dw-hdmi-Remove-encoder-field-from-struct-.patch @@ -0,0 +1,65 @@ +From ef242ace1b51401f14217abd837cce456b22cf4d Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:28:55 +0200 +Subject: [PATCH 240/255] drm: bridge: dw-hdmi: Remove encoder field from + struct dw_hdmi + +The field isn't needed, remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-6-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 527b863f6ad4f4f1707cbc2237df9d83d0c848c1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 9 +++------ + 1 file changed, 3 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -115,7 +115,6 @@ struct dw_hdmi_i2c { + + struct dw_hdmi { + struct drm_connector connector; +- struct drm_encoder *encoder; + struct drm_bridge bridge; + + struct platform_device *audio; +@@ -1816,9 +1815,8 @@ static irqreturn_t dw_hdmi_irq(int irq, + return IRQ_HANDLED; + } + +-static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi) ++static int dw_hdmi_register(struct drm_encoder *encoder, struct dw_hdmi *hdmi) + { +- struct drm_encoder *encoder = hdmi->encoder; + struct drm_bridge *bridge = &hdmi->bridge; + int ret; + +@@ -1835,7 +1833,7 @@ static int dw_hdmi_register(struct drm_d + drm_connector_helper_add(&hdmi->connector, + &dw_hdmi_connector_helper_funcs); + +- drm_connector_init(drm, &hdmi->connector, ++ drm_connector_init(encoder->dev, &hdmi->connector, + &dw_hdmi_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + +@@ -1867,7 +1865,6 @@ int dw_hdmi_bind(struct device *dev, str + hdmi->dev = dev; + hdmi->dev_type = plat_data->dev_type; + hdmi->sample_rate = 48000; +- hdmi->encoder = encoder; + hdmi->disabled = true; + hdmi->rxsense = true; + hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); +@@ -1980,7 +1977,7 @@ int dw_hdmi_bind(struct device *dev, str + if (ret) + goto err_iahb; + +- ret = dw_hdmi_register(encoder->dev, hdmi); ++ ret = dw_hdmi_register(encoder, hdmi); + if (ret) + goto err_iahb; + diff --git a/patches.renesas/0241-drm-bridge-dw-hdmi-Don-t-forward-HPD-events-to-DRM-c.patch b/patches.renesas/0241-drm-bridge-dw-hdmi-Don-t-forward-HPD-events-to-DRM-c.patch new file mode 100644 index 0000000000000..a821d9874863e --- /dev/null +++ b/patches.renesas/0241-drm-bridge-dw-hdmi-Don-t-forward-HPD-events-to-DRM-c.patch @@ -0,0 +1,32 @@ +From a731f1a3dc018610df31aa41670687745724df24 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:28:56 +0200 +Subject: [PATCH 241/255] drm: bridge: dw-hdmi: Don't forward HPD events to DRM + core before attach + +Hotplug events should only be forwarded to the DRM core by the interrupt +handler when the bridge has been attached, otherwise the DRM device +pointer will be NULL, resulting in a crash. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-7-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit ba5d7e6160b7aed4df92d1764aa90790db0e7996) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -1805,7 +1805,8 @@ static irqreturn_t dw_hdmi_irq(int irq, + if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { + dev_dbg(hdmi->dev, "EVENT=%s\n", + phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); +- drm_helper_hpd_irq_event(hdmi->bridge.dev); ++ if (hdmi->bridge.dev) ++ drm_helper_hpd_irq_event(hdmi->bridge.dev); + } + + hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); diff --git a/patches.renesas/0242-drm-bridge-dw-hdmi-Move-IRQ-and-IO-resource-allocati.patch b/patches.renesas/0242-drm-bridge-dw-hdmi-Move-IRQ-and-IO-resource-allocati.patch new file mode 100644 index 0000000000000..288467401ed0d --- /dev/null +++ b/patches.renesas/0242-drm-bridge-dw-hdmi-Move-IRQ-and-IO-resource-allocati.patch @@ -0,0 +1,158 @@ +From c46f98a980f5aad6b8f99c4e7ab4e3e24ead1939 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:28:57 +0200 +Subject: [PATCH 242/255] drm: bridge: dw-hdmi: Move IRQ and IO resource + allocation to common code + +There's no need to duplicate identical code in multiple drivers (two at +the moment, one more to come soon). Move it to the dw-hdmi core where it +can be shared. If resource allocation ever becomes device-specific later +we'll always have the option of splitting it out again. + +While it at pass the platform device to the bind function to avoid +having to cast struct device to struct platform_device. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-8-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit c608119dfdde9710e4bd068d632beb68bb3517db) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 13 ++++++++++--- + drivers/gpu/drm/imx/dw_hdmi-imx.c | 12 +----------- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 12 +----------- + include/drm/bridge/dw_hdmi.h | 3 +-- + 4 files changed, 13 insertions(+), 27 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -1843,14 +1843,16 @@ static int dw_hdmi_register(struct drm_e + return 0; + } + +-int dw_hdmi_bind(struct device *dev, struct drm_encoder *encoder, +- struct resource *iores, int irq, ++int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, + const struct dw_hdmi_plat_data *plat_data) + { ++ struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct platform_device_info pdevinfo; + struct device_node *ddc_node; + struct dw_hdmi *hdmi; ++ struct resource *iores; ++ int irq; + int ret; + u32 val = 1; + u8 config0; +@@ -1903,6 +1905,7 @@ int dw_hdmi_bind(struct device *dev, str + dev_dbg(hdmi->dev, "no ddc property found\n"); + } + ++ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + hdmi->regs = devm_ioremap_resource(dev, iores); + if (IS_ERR(hdmi->regs)) { + ret = PTR_ERR(hdmi->regs); +@@ -1945,6 +1948,10 @@ int dw_hdmi_bind(struct device *dev, str + + initialize_hdmi_ih_mutes(hdmi); + ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ goto err_iahb; ++ + ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, + dw_hdmi_irq, IRQF_SHARED, + dev_name(dev), hdmi); +@@ -2025,7 +2032,7 @@ int dw_hdmi_bind(struct device *dev, str + if (hdmi->i2c) + dw_hdmi_i2c_init(hdmi); + +- dev_set_drvdata(dev, hdmi); ++ platform_set_drvdata(pdev, hdmi); + + return 0; + +--- a/drivers/gpu/drm/imx/dw_hdmi-imx.c ++++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c +@@ -207,8 +207,6 @@ static int dw_hdmi_imx_bind(struct devic + struct drm_device *drm = data; + struct drm_encoder *encoder; + struct imx_hdmi *hdmi; +- struct resource *iores; +- int irq; + int ret; + + if (!pdev->dev.of_node) +@@ -223,14 +221,6 @@ static int dw_hdmi_imx_bind(struct devic + hdmi->dev = &pdev->dev; + encoder = &hdmi->encoder; + +- irq = platform_get_irq(pdev, 0); +- if (irq < 0) +- return irq; +- +- iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!iores) +- return -ENXIO; +- + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); + /* + * If we failed to find the CRTC(s) which this encoder is +@@ -249,7 +239,7 @@ static int dw_hdmi_imx_bind(struct devic + drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs, + DRM_MODE_ENCODER_TMDS, NULL); + +- ret = dw_hdmi_bind(dev, encoder, iores, irq, plat_data); ++ ret = dw_hdmi_bind(pdev, encoder, plat_data); + + /* + * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -257,8 +257,6 @@ static int dw_hdmi_rockchip_bind(struct + struct drm_device *drm = data; + struct drm_encoder *encoder; + struct rockchip_hdmi *hdmi; +- struct resource *iores; +- int irq; + int ret; + + if (!pdev->dev.of_node) +@@ -273,14 +271,6 @@ static int dw_hdmi_rockchip_bind(struct + hdmi->dev = &pdev->dev; + encoder = &hdmi->encoder; + +- irq = platform_get_irq(pdev, 0); +- if (irq < 0) +- return irq; +- +- iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!iores) +- return -ENXIO; +- + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); + /* + * If we failed to find the CRTC(s) which this encoder is +@@ -301,7 +291,7 @@ static int dw_hdmi_rockchip_bind(struct + drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs, + DRM_MODE_ENCODER_TMDS, NULL); + +- ret = dw_hdmi_bind(dev, encoder, iores, irq, plat_data); ++ ret = dw_hdmi_bind(pdev, encoder, plat_data); + + /* + * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -57,8 +57,7 @@ struct dw_hdmi_plat_data { + }; + + void dw_hdmi_unbind(struct device *dev); +-int dw_hdmi_bind(struct device *dev, struct drm_encoder *encoder, +- struct resource *iores, int irq, ++int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, + const struct dw_hdmi_plat_data *plat_data); + + void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); diff --git a/patches.renesas/0243-drm-bridge-dw-hdmi-Reorder-functions-to-prepare-for-.patch b/patches.renesas/0243-drm-bridge-dw-hdmi-Reorder-functions-to-prepare-for-.patch new file mode 100644 index 0000000000000..e029830fbf2d6 --- /dev/null +++ b/patches.renesas/0243-drm-bridge-dw-hdmi-Reorder-functions-to-prepare-for-.patch @@ -0,0 +1,108 @@ +From 8ec211dda8911fe23ee4c7e4f6e86e5021819d76 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:28:58 +0200 +Subject: [PATCH 243/255] drm: bridge: dw-hdmi: Reorder functions to prepare + for next commit + +The next commit will reference structures and functions in a way that +currently requires forward declarations. Reorder the functions to avoid +that. No functional change to the code is performed. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-9-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit fd30b38c27c305fcb522bfa7911de241ee1799b5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 72 +++++++++++++++++++-------------------- + 1 file changed, 36 insertions(+), 36 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -1575,42 +1575,6 @@ static void dw_hdmi_update_phy_mask(stru + hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); + } + +-static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, +- struct drm_display_mode *orig_mode, +- struct drm_display_mode *mode) +-{ +- struct dw_hdmi *hdmi = bridge->driver_private; +- +- mutex_lock(&hdmi->mutex); +- +- /* Store the display mode for plugin/DKMS poweron events */ +- memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); +- +- mutex_unlock(&hdmi->mutex); +-} +- +-static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) +-{ +- struct dw_hdmi *hdmi = bridge->driver_private; +- +- mutex_lock(&hdmi->mutex); +- hdmi->disabled = true; +- dw_hdmi_update_power(hdmi); +- dw_hdmi_update_phy_mask(hdmi); +- mutex_unlock(&hdmi->mutex); +-} +- +-static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) +-{ +- struct dw_hdmi *hdmi = bridge->driver_private; +- +- mutex_lock(&hdmi->mutex); +- hdmi->disabled = false; +- dw_hdmi_update_power(hdmi); +- dw_hdmi_update_phy_mask(hdmi); +- mutex_unlock(&hdmi->mutex); +-} +- + static enum drm_connector_status + dw_hdmi_connector_detect(struct drm_connector *connector, bool force) + { +@@ -1703,6 +1667,42 @@ static const struct drm_connector_helper + .best_encoder = drm_atomic_helper_best_encoder, + }; + ++static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, ++ struct drm_display_mode *orig_mode, ++ struct drm_display_mode *mode) ++{ ++ struct dw_hdmi *hdmi = bridge->driver_private; ++ ++ mutex_lock(&hdmi->mutex); ++ ++ /* Store the display mode for plugin/DKMS poweron events */ ++ memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); ++ ++ mutex_unlock(&hdmi->mutex); ++} ++ ++static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) ++{ ++ struct dw_hdmi *hdmi = bridge->driver_private; ++ ++ mutex_lock(&hdmi->mutex); ++ hdmi->disabled = true; ++ dw_hdmi_update_power(hdmi); ++ dw_hdmi_update_phy_mask(hdmi); ++ mutex_unlock(&hdmi->mutex); ++} ++ ++static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) ++{ ++ struct dw_hdmi *hdmi = bridge->driver_private; ++ ++ mutex_lock(&hdmi->mutex); ++ hdmi->disabled = false; ++ dw_hdmi_update_power(hdmi); ++ dw_hdmi_update_phy_mask(hdmi); ++ mutex_unlock(&hdmi->mutex); ++} ++ + static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { + .enable = dw_hdmi_bridge_enable, + .disable = dw_hdmi_bridge_disable, diff --git a/patches.renesas/0244-drm-bridge-dw-hdmi-Create-connector-in-the-bridge-at.patch b/patches.renesas/0244-drm-bridge-dw-hdmi-Create-connector-in-the-bridge-at.patch new file mode 100644 index 0000000000000..38fadfa52495d --- /dev/null +++ b/patches.renesas/0244-drm-bridge-dw-hdmi-Create-connector-in-the-bridge-at.patch @@ -0,0 +1,85 @@ +From 8ffa1674cc6aace38d9b2df1cdc46e5850454a68 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:28:59 +0200 +Subject: [PATCH 244/255] drm: bridge: dw-hdmi: Create connector in the bridge + attach operation + +The DRM device is not guaranteed by the bridge API to be available +before the attach callback. The driver performs properly at the moment +as it doesn't use the drm_bridge_add() registration method. As this will +be changed later, move connector creation to attach time to ensure +compatibility with the API. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-10-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit d2ae94ae840bd0b347e417e88b1637df95d499ac) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 33 ++++++++++++++++++++------------- + 1 file changed, 20 insertions(+), 13 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -1667,6 +1667,25 @@ static const struct drm_connector_helper + .best_encoder = drm_atomic_helper_best_encoder, + }; + ++static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) ++{ ++ struct dw_hdmi *hdmi = bridge->driver_private; ++ struct drm_encoder *encoder = bridge->encoder; ++ struct drm_connector *connector = &hdmi->connector; ++ ++ connector->interlace_allowed = 1; ++ connector->polled = DRM_CONNECTOR_POLL_HPD; ++ ++ drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); ++ ++ drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs, ++ DRM_MODE_CONNECTOR_HDMIA); ++ ++ drm_mode_connector_attach_encoder(connector, encoder); ++ ++ return 0; ++} ++ + static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, + struct drm_display_mode *orig_mode, + struct drm_display_mode *mode) +@@ -1704,6 +1723,7 @@ static void dw_hdmi_bridge_enable(struct + } + + static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { ++ .attach = dw_hdmi_bridge_attach, + .enable = dw_hdmi_bridge_enable, + .disable = dw_hdmi_bridge_disable, + .mode_set = dw_hdmi_bridge_mode_set, +@@ -1829,17 +1849,6 @@ static int dw_hdmi_register(struct drm_e + return -EINVAL; + } + +- hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD; +- +- drm_connector_helper_add(&hdmi->connector, +- &dw_hdmi_connector_helper_funcs); +- +- drm_connector_init(encoder->dev, &hdmi->connector, +- &dw_hdmi_connector_funcs, +- DRM_MODE_CONNECTOR_HDMIA); +- +- drm_mode_connector_attach_encoder(&hdmi->connector, encoder); +- + return 0; + } + +@@ -1862,8 +1871,6 @@ int dw_hdmi_bind(struct platform_device + if (!hdmi) + return -ENOMEM; + +- hdmi->connector.interlace_allowed = 1; +- + hdmi->plat_data = plat_data; + hdmi->dev = dev; + hdmi->dev_type = plat_data->dev_type; diff --git a/patches.renesas/0245-drm-bridge-dw-hdmi-Implement-DRM-bridge-registration.patch b/patches.renesas/0245-drm-bridge-dw-hdmi-Implement-DRM-bridge-registration.patch new file mode 100644 index 0000000000000..cb5d592f4bdc3 --- /dev/null +++ b/patches.renesas/0245-drm-bridge-dw-hdmi-Implement-DRM-bridge-registration.patch @@ -0,0 +1,216 @@ +From befd34e3c24cd92f7f8bec303a9fda088f692b9a Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:29:00 +0200 +Subject: [PATCH 245/255] drm: bridge: dw-hdmi: Implement DRM bridge + registration + +As an option for drivers not based on the component framework, register +the bridge with the DRM core with the DRM bridge API. Existing drivers +based on dw_hdmi_bind() and dw_hdmi_unbind() are not affected as those +functions are preserved with their current behaviour. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-11-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 69497eb9234eb34994b9a0d2f2c17c4c09f2e969) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 112 +++++++++++++++++++++++++++------------ + include/drm/bridge/dw_hdmi.h | 3 + + 2 files changed, 83 insertions(+), 32 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -1836,24 +1836,9 @@ static irqreturn_t dw_hdmi_irq(int irq, + return IRQ_HANDLED; + } + +-static int dw_hdmi_register(struct drm_encoder *encoder, struct dw_hdmi *hdmi) +-{ +- struct drm_bridge *bridge = &hdmi->bridge; +- int ret; +- +- bridge->driver_private = hdmi; +- bridge->funcs = &dw_hdmi_bridge_funcs; +- ret = drm_bridge_attach(encoder, bridge, NULL); +- if (ret) { +- DRM_ERROR("Failed to initialize bridge with drm\n"); +- return -EINVAL; +- } +- +- return 0; +-} +- +-int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, +- const struct dw_hdmi_plat_data *plat_data) ++static struct dw_hdmi * ++__dw_hdmi_probe(struct platform_device *pdev, ++ const struct dw_hdmi_plat_data *plat_data) + { + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; +@@ -1869,7 +1854,7 @@ int dw_hdmi_bind(struct platform_device + + hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) +- return -ENOMEM; ++ return ERR_PTR(-ENOMEM); + + hdmi->plat_data = plat_data; + hdmi->dev = dev; +@@ -1896,7 +1881,7 @@ int dw_hdmi_bind(struct platform_device + break; + default: + dev_err(dev, "reg-io-width must be 1 or 4\n"); +- return -EINVAL; ++ return ERR_PTR(-EINVAL); + } + + ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); +@@ -1905,7 +1890,7 @@ int dw_hdmi_bind(struct platform_device + of_node_put(ddc_node); + if (!hdmi->ddc) { + dev_dbg(hdmi->dev, "failed to read ddc node\n"); +- return -EPROBE_DEFER; ++ return ERR_PTR(-EPROBE_DEFER); + } + + } else { +@@ -1956,8 +1941,10 @@ int dw_hdmi_bind(struct platform_device + initialize_hdmi_ih_mutes(hdmi); + + irq = platform_get_irq(pdev, 0); +- if (irq < 0) ++ if (irq < 0) { ++ ret = irq; + goto err_iahb; ++ } + + ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, + dw_hdmi_irq, IRQF_SHARED, +@@ -1988,11 +1975,11 @@ int dw_hdmi_bind(struct platform_device + hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, + HDMI_IH_PHY_STAT0); + +- ret = dw_hdmi_fb_registered(hdmi); +- if (ret) +- goto err_iahb; ++ hdmi->bridge.driver_private = hdmi; ++ hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; ++ hdmi->bridge.of_node = pdev->dev.of_node; + +- ret = dw_hdmi_register(encoder, hdmi); ++ ret = dw_hdmi_fb_registered(hdmi); + if (ret) + goto err_iahb; + +@@ -2041,7 +2028,7 @@ int dw_hdmi_bind(struct platform_device + + platform_set_drvdata(pdev, hdmi); + +- return 0; ++ return hdmi; + + err_iahb: + if (hdmi->i2c) { +@@ -2055,14 +2042,11 @@ err_isfr: + err_res: + i2c_put_adapter(hdmi->ddc); + +- return ret; ++ return ERR_PTR(ret); + } +-EXPORT_SYMBOL_GPL(dw_hdmi_bind); + +-void dw_hdmi_unbind(struct device *dev) ++static void __dw_hdmi_remove(struct dw_hdmi *hdmi) + { +- struct dw_hdmi *hdmi = dev_get_drvdata(dev); +- + if (hdmi->audio && !IS_ERR(hdmi->audio)) + platform_device_unregister(hdmi->audio); + +@@ -2077,6 +2061,70 @@ void dw_hdmi_unbind(struct device *dev) + else + i2c_put_adapter(hdmi->ddc); + } ++ ++/* ----------------------------------------------------------------------------- ++ * Probe/remove API, used from platforms based on the DRM bridge API. ++ */ ++int dw_hdmi_probe(struct platform_device *pdev, ++ const struct dw_hdmi_plat_data *plat_data) ++{ ++ struct dw_hdmi *hdmi; ++ int ret; ++ ++ hdmi = __dw_hdmi_probe(pdev, plat_data); ++ if (IS_ERR(hdmi)) ++ return PTR_ERR(hdmi); ++ ++ ret = drm_bridge_add(&hdmi->bridge); ++ if (ret < 0) { ++ __dw_hdmi_remove(hdmi); ++ return ret; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_probe); ++ ++void dw_hdmi_remove(struct platform_device *pdev) ++{ ++ struct dw_hdmi *hdmi = platform_get_drvdata(pdev); ++ ++ drm_bridge_remove(&hdmi->bridge); ++ ++ __dw_hdmi_remove(hdmi); ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_remove); ++ ++/* ----------------------------------------------------------------------------- ++ * Bind/unbind API, used from platforms based on the component framework. ++ */ ++int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, ++ const struct dw_hdmi_plat_data *plat_data) ++{ ++ struct dw_hdmi *hdmi; ++ int ret; ++ ++ hdmi = __dw_hdmi_probe(pdev, plat_data); ++ if (IS_ERR(hdmi)) ++ return PTR_ERR(hdmi); ++ ++ ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); ++ if (ret) { ++ dw_hdmi_remove(pdev); ++ DRM_ERROR("Failed to initialize bridge with drm\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_bind); ++ ++void dw_hdmi_unbind(struct device *dev) ++{ ++ struct dw_hdmi *hdmi = dev_get_drvdata(dev); ++ ++ __dw_hdmi_remove(hdmi); ++} + EXPORT_SYMBOL_GPL(dw_hdmi_unbind); + + MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -56,6 +56,9 @@ struct dw_hdmi_plat_data { + struct drm_display_mode *mode); + }; + ++int dw_hdmi_probe(struct platform_device *pdev, ++ const struct dw_hdmi_plat_data *plat_data); ++void dw_hdmi_remove(struct platform_device *pdev); + void dw_hdmi_unbind(struct device *dev); + int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, + const struct dw_hdmi_plat_data *plat_data); diff --git a/patches.renesas/0246-drm-bridge-dw-hdmi-Remove-PHY-configuration-resoluti.patch b/patches.renesas/0246-drm-bridge-dw-hdmi-Remove-PHY-configuration-resoluti.patch new file mode 100644 index 0000000000000..173ef600e8cfc --- /dev/null +++ b/patches.renesas/0246-drm-bridge-dw-hdmi-Remove-PHY-configuration-resoluti.patch @@ -0,0 +1,80 @@ +From d8a536dbc82a0b0075abe2b986a617d57cc3eaa2 Mon Sep 17 00:00:00 2001 +From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:29:01 +0200 +Subject: [PATCH 246/255] drm: bridge: dw-hdmi: Remove PHY configuration + resolution parameter + +The current code hard codes the call of hdmi_phy_configure() to be 8bpp +and provides extraneous error checking to verify that this hardcoded +value is correct. Simplify the implementation by removing the argument. + +Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-12-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 1acc6bdeee1ef2ecac3ba070a403827ab8f16be5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 27 +++++---------------------- + 1 file changed, 5 insertions(+), 22 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -930,31 +930,14 @@ static void dw_hdmi_phy_sel_interface_co + HDMI_PHY_CONF0_SELDIPIF_MASK); + } + +-static int hdmi_phy_configure(struct dw_hdmi *hdmi, +- unsigned char res, int cscon) ++static int hdmi_phy_configure(struct dw_hdmi *hdmi, int cscon) + { +- unsigned res_idx; + u8 val, msec; + const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; + const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; + const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; + const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; + +- switch (res) { +- case 0: /* color resolution 0 is 8 bit colour depth */ +- case 8: +- res_idx = DW_HDMI_RES_8; +- break; +- case 10: +- res_idx = DW_HDMI_RES_10; +- break; +- case 12: +- res_idx = DW_HDMI_RES_12; +- break; +- default: +- return -EINVAL; +- } +- + /* PLL/MPLL Cfg - always match on final entry */ + for (; mpll_config->mpixelclock != ~0UL; mpll_config++) + if (hdmi->hdmi_data.video_mode.mpixelclock <= +@@ -1004,11 +987,11 @@ static int hdmi_phy_configure(struct dw_ + HDMI_PHY_I2CM_SLAVE_ADDR); + hdmi_phy_test_clear(hdmi, 0); + +- hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06); +- hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15); ++ hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 0x06); ++ hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 0x15); + + /* CURRCTRL */ +- hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10); ++ hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 0x10); + + hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */ + hdmi_phy_i2c_write(hdmi, 0x0006, 0x17); +@@ -1068,7 +1051,7 @@ static int dw_hdmi_phy_init(struct dw_hd + dw_hdmi_phy_enable_powerdown(hdmi, true); + + /* Enable CSC */ +- ret = hdmi_phy_configure(hdmi, 8, cscon); ++ ret = hdmi_phy_configure(hdmi, cscon); + if (ret) + return ret; + } diff --git a/patches.renesas/0247-drm-bridge-dw-hdmi-Rename-CONF0-SPARECTRL-bit-to-SVS.patch b/patches.renesas/0247-drm-bridge-dw-hdmi-Rename-CONF0-SPARECTRL-bit-to-SVS.patch new file mode 100644 index 0000000000000..f5dfca7bfc5bf --- /dev/null +++ b/patches.renesas/0247-drm-bridge-dw-hdmi-Rename-CONF0-SPARECTRL-bit-to-SVS.patch @@ -0,0 +1,63 @@ +From ad95bf8f67c92bf2c77f4928444bc5985f28ac54 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:29:02 +0200 +Subject: [PATCH 247/255] drm: bridge: dw-hdmi: Rename CONF0 SPARECTRL bit to + SVSRET + +The bit is documented in a Rockchip BSP as + + #define m_SVSRET_SIG (1 << 5) /* depend on PHY_MHL_COMB0=1 */ + +This is confirmed by a Renesas platform, which uses a 2.0 DWC HDMI TX as +the RK3288. Rename the bit accordingly. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-13-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit f4104e8fe12c173fbba5e7e30b846e09eeb5bfbd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 8 ++++---- + drivers/gpu/drm/bridge/dw-hdmi.h | 4 ++-- + 2 files changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -895,11 +895,11 @@ static void dw_hdmi_phy_enable_tmds(stru + HDMI_PHY_CONF0_ENTMDS_MASK); + } + +-static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable) ++static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) + { + hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, +- HDMI_PHY_CONF0_SPARECTRL_OFFSET, +- HDMI_PHY_CONF0_SPARECTRL_MASK); ++ HDMI_PHY_CONF0_SVSRET_OFFSET, ++ HDMI_PHY_CONF0_SVSRET_MASK); + } + + static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) +@@ -1014,7 +1014,7 @@ static int hdmi_phy_configure(struct dw_ + dw_hdmi_phy_gen2_pddq(hdmi, 0); + + if (hdmi->dev_type == RK3288_HDMI) +- dw_hdmi_phy_enable_spare(hdmi, 1); ++ dw_hdmi_phy_enable_svsret(hdmi, 1); + + /*Wait for PHY PLL lock */ + msec = 5; +--- a/drivers/gpu/drm/bridge/dw-hdmi.h ++++ b/drivers/gpu/drm/bridge/dw-hdmi.h +@@ -847,8 +847,8 @@ enum { + HDMI_PHY_CONF0_PDZ_OFFSET = 7, + HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, + HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, +- HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20, +- HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5, ++ HDMI_PHY_CONF0_SVSRET_MASK = 0x20, ++ HDMI_PHY_CONF0_SVSRET_OFFSET = 5, + HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, + HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, diff --git a/patches.renesas/0248-drm-bridge-dw-hdmi-Reject-invalid-product-IDs.patch b/patches.renesas/0248-drm-bridge-dw-hdmi-Reject-invalid-product-IDs.patch new file mode 100644 index 0000000000000..77b3a6c8ccaa7 --- /dev/null +++ b/patches.renesas/0248-drm-bridge-dw-hdmi-Reject-invalid-product-IDs.patch @@ -0,0 +1,90 @@ +From 859a288601a5dd6322c0153da7d2baf1dba64922 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:29:03 +0200 +Subject: [PATCH 248/255] drm: bridge: dw-hdmi: Reject invalid product IDs + +The DWC HDMI TX can be recognized by the two product identification +registers. If the registers don't read as expect the IP will be very +different than what the driver has been designed for, or will be +misconfigured in a way that makes it non-operational (invalid memory +address, incorrect clocks, ...). We should reject this situation with an +error. + +While this isn't critical for proper operation with supported IPs at the +moment, the driver will soon gain automatic device-specific handling +based on runtime device identification. This change makes it easier to +implement that without having to default to a random guess in case the +device can't be identified. + +While at it print a readable version number in the device identification +message instead of raw register values. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-14-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 0527e12e8264ae96b1fcc550b4a9e5940f4ffc30) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 25 +++++++++++++++++++------ + drivers/gpu/drm/bridge/dw-hdmi.h | 8 ++++++++ + 2 files changed, 27 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -1832,6 +1832,9 @@ __dw_hdmi_probe(struct platform_device * + int irq; + int ret; + u32 val = 1; ++ u16 version; ++ u8 prod_id0; ++ u8 prod_id1; + u8 config0; + u8 config1; + +@@ -1914,12 +1917,22 @@ __dw_hdmi_probe(struct platform_device * + } + + /* Product and revision IDs */ +- dev_info(dev, +- "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n", +- hdmi_readb(hdmi, HDMI_DESIGN_ID), +- hdmi_readb(hdmi, HDMI_REVISION_ID), +- hdmi_readb(hdmi, HDMI_PRODUCT_ID0), +- hdmi_readb(hdmi, HDMI_PRODUCT_ID1)); ++ version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) ++ | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); ++ prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); ++ prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); ++ ++ if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || ++ (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { ++ dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", ++ version, prod_id0, prod_id1); ++ ret = -ENODEV; ++ goto err_iahb; ++ } ++ ++ dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP\n", ++ version >> 12, version & 0xfff, ++ prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without"); + + initialize_hdmi_ih_mutes(hdmi); + +--- a/drivers/gpu/drm/bridge/dw-hdmi.h ++++ b/drivers/gpu/drm/bridge/dw-hdmi.h +@@ -545,6 +545,14 @@ + #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 + + enum { ++/* PRODUCT_ID0 field values */ ++ HDMI_PRODUCT_ID0_HDMI_TX = 0xa0, ++ ++/* PRODUCT_ID1 field values */ ++ HDMI_PRODUCT_ID1_HDCP = 0xc0, ++ HDMI_PRODUCT_ID1_HDMI_RX = 0x02, ++ HDMI_PRODUCT_ID1_HDMI_TX = 0x01, ++ + /* CONFIG0_ID field values */ + HDMI_CONFIG0_I2S = 0x10, + diff --git a/patches.renesas/0249-drm-bridge-dw-hdmi-Detect-AHB-audio-DMA-using-correc.patch b/patches.renesas/0249-drm-bridge-dw-hdmi-Detect-AHB-audio-DMA-using-correc.patch new file mode 100644 index 0000000000000..17b11a58ec10a --- /dev/null +++ b/patches.renesas/0249-drm-bridge-dw-hdmi-Detect-AHB-audio-DMA-using-correc.patch @@ -0,0 +1,57 @@ +From 4931bfb681595c73c026b8e195dfd4c32f2e155d Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:29:04 +0200 +Subject: [PATCH 249/255] drm: bridge: dw-hdmi: Detect AHB audio DMA using + correct register + +Bit 0 in CONFIG1_ID tells whether the IP core uses an AHB slave +interface for control. The correct way to identify AHB audio DMA support +is through bit 1 in CONFIG3_ID. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-15-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 0c674948b7f4e4ffc19ba5af65a274e945c0c689) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 6 +++--- + drivers/gpu/drm/bridge/dw-hdmi.h | 4 ++++ + 2 files changed, 7 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -1836,7 +1836,7 @@ __dw_hdmi_probe(struct platform_device * + u8 prod_id0; + u8 prod_id1; + u8 config0; +- u8 config1; ++ u8 config3; + + hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) +@@ -1988,9 +1988,9 @@ __dw_hdmi_probe(struct platform_device * + pdevinfo.id = PLATFORM_DEVID_AUTO; + + config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); +- config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID); ++ config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); + +- if (config1 & HDMI_CONFIG1_AHB) { ++ if (config3 & HDMI_CONFIG3_AHBAUDDMA) { + struct dw_hdmi_audio_data audio; + + audio.phys = iores->start; +--- a/drivers/gpu/drm/bridge/dw-hdmi.h ++++ b/drivers/gpu/drm/bridge/dw-hdmi.h +@@ -559,6 +559,10 @@ enum { + /* CONFIG1_ID field values */ + HDMI_CONFIG1_AHB = 0x01, + ++/* CONFIG3_ID field values */ ++ HDMI_CONFIG3_AHBAUDDMA = 0x02, ++ HDMI_CONFIG3_GPAUD = 0x01, ++ + /* IH_FC_INT2 field values */ + HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03, + HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, diff --git a/patches.renesas/0250-drm-bridge-dw-hdmi-Handle-overflow-workaround-based-.patch b/patches.renesas/0250-drm-bridge-dw-hdmi-Handle-overflow-workaround-based-.patch new file mode 100644 index 0000000000000..cb3f3dff8a09a --- /dev/null +++ b/patches.renesas/0250-drm-bridge-dw-hdmi-Handle-overflow-workaround-based-.patch @@ -0,0 +1,120 @@ +From 087f2fefee2f4fa50b6e16e2b7359cae63002fbe Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:29:05 +0200 +Subject: [PATCH 250/255] drm: bridge: dw-hdmi: Handle overflow workaround + based on device version + +Use the device version queried at runtime instead of the device type +provided through platform data to handle the overflow workaround. This +will make support of other SoCs integrating the same HDMI TX controller +version easier. + +Among the supported platforms only i.MX6DL and i.MX6Q have been +identified as needing the workaround. Disabling it on Rockchip RK3288 +(which integrates a v2.00a controller) didn't produce any error or +artifact. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-16-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit be41fc55f1aa3c9ae0eb9e0b384db5150eca055f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 46 +++++++++++++++++++++++++++------------ + 1 file changed, 33 insertions(+), 13 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -117,8 +117,10 @@ struct dw_hdmi { + struct drm_connector connector; + struct drm_bridge bridge; + +- struct platform_device *audio; + enum dw_hdmi_devtype dev_type; ++ unsigned int version; ++ ++ struct platform_device *audio; + struct device *dev; + struct clk *isfr_clk; + struct clk *iahb_clk; +@@ -1323,19 +1325,38 @@ static void hdmi_enable_audio_clk(struct + /* Workaround to clear the overflow condition */ + static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) + { +- int count; ++ unsigned int count; ++ unsigned int i; + u8 val; + +- /* TMDS software reset */ +- hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); ++ /* ++ * Under some circumstances the Frame Composer arithmetic unit can miss ++ * an FC register write due to being busy processing the previous one. ++ * The issue can be worked around by issuing a TMDS software reset and ++ * then write one of the FC registers several times. ++ * ++ * The number of iterations matters and depends on the HDMI TX revision ++ * (and possibly on the platform). So far only i.MX6Q (v1.30a) and ++ * i.MX6DL (v1.31a) have been identified as needing the workaround, with ++ * 4 and 1 iterations respectively. ++ */ + +- val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); +- if (hdmi->dev_type == IMX6DL_HDMI) { +- hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); ++ switch (hdmi->version) { ++ case 0x130a: ++ count = 4; ++ break; ++ case 0x131a: ++ count = 1; ++ break; ++ default: + return; + } + +- for (count = 0; count < 4; count++) ++ /* TMDS software reset */ ++ hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); ++ ++ val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); ++ for (i = 0; i < count; i++) + hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); + } + +@@ -1832,7 +1853,6 @@ __dw_hdmi_probe(struct platform_device * + int irq; + int ret; + u32 val = 1; +- u16 version; + u8 prod_id0; + u8 prod_id1; + u8 config0; +@@ -1917,21 +1937,21 @@ __dw_hdmi_probe(struct platform_device * + } + + /* Product and revision IDs */ +- version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) +- | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); ++ hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) ++ | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); + prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); + prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); + + if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || + (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { + dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", +- version, prod_id0, prod_id1); ++ hdmi->version, prod_id0, prod_id1); + ret = -ENODEV; + goto err_iahb; + } + + dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP\n", +- version >> 12, version & 0xfff, ++ hdmi->version >> 12, hdmi->version & 0xfff, + prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without"); + + initialize_hdmi_ih_mutes(hdmi); diff --git a/patches.renesas/0251-drm-bridge-dw-hdmi-Detect-PHY-type-at-runtime.patch b/patches.renesas/0251-drm-bridge-dw-hdmi-Detect-PHY-type-at-runtime.patch new file mode 100644 index 0000000000000..b704067494419 --- /dev/null +++ b/patches.renesas/0251-drm-bridge-dw-hdmi-Detect-PHY-type-at-runtime.patch @@ -0,0 +1,144 @@ +From 40aac568e42ffb308a0d9aaf6a2694d9b60ccb0b Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:29:06 +0200 +Subject: [PATCH 251/255] drm: bridge: dw-hdmi: Detect PHY type at runtime + +Detect the PHY type and use it to handle the PHY type-specific SVSRET +signal. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-17-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit faba6c3cff177689aec132291b1cf537831d9a2e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 68 +++++++++++++++++++++++++++++++++++++-- + include/drm/bridge/dw_hdmi.h | 10 +++++ + 2 files changed, 75 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -113,6 +113,12 @@ struct dw_hdmi_i2c { + bool is_regaddr; + }; + ++struct dw_hdmi_phy_data { ++ enum dw_hdmi_phy_type type; ++ const char *name; ++ bool has_svsret; ++}; ++ + struct dw_hdmi { + struct drm_connector connector; + struct drm_bridge bridge; +@@ -134,7 +140,9 @@ struct dw_hdmi { + u8 edid[HDMI_EDID_LEN]; + bool cable_plugin; + ++ const struct dw_hdmi_phy_data *phy; + bool phy_enabled; ++ + struct drm_display_mode previous_mode; + + struct i2c_adapter *ddc; +@@ -1015,7 +1023,8 @@ static int hdmi_phy_configure(struct dw_ + dw_hdmi_phy_gen2_txpwron(hdmi, 1); + dw_hdmi_phy_gen2_pddq(hdmi, 0); + +- if (hdmi->dev_type == RK3288_HDMI) ++ /* The DWC MHL and HDMI 2.0 PHYs need the SVSRET signal to be set. */ ++ if (hdmi->phy->has_svsret) + dw_hdmi_phy_enable_svsret(hdmi, 1); + + /*Wait for PHY PLL lock */ +@@ -1840,6 +1849,54 @@ static irqreturn_t dw_hdmi_irq(int irq, + return IRQ_HANDLED; + } + ++static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { ++ { ++ .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, ++ .name = "DWC HDMI TX PHY", ++ }, { ++ .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, ++ .name = "DWC MHL PHY + HEAC PHY", ++ .has_svsret = true, ++ }, { ++ .type = DW_HDMI_PHY_DWC_MHL_PHY, ++ .name = "DWC MHL PHY", ++ .has_svsret = true, ++ }, { ++ .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, ++ .name = "DWC HDMI 3D TX PHY + HEAC PHY", ++ }, { ++ .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, ++ .name = "DWC HDMI 3D TX PHY", ++ }, { ++ .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, ++ .name = "DWC HDMI 2.0 TX PHY", ++ .has_svsret = true, ++ } ++}; ++ ++static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) ++{ ++ unsigned int i; ++ u8 phy_type; ++ ++ phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); ++ ++ for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { ++ if (dw_hdmi_phys[i].type == phy_type) { ++ hdmi->phy = &dw_hdmi_phys[i]; ++ return 0; ++ } ++ } ++ ++ if (phy_type == DW_HDMI_PHY_VENDOR_PHY) ++ dev_err(hdmi->dev, "Unsupported vendor HDMI PHY\n"); ++ else ++ dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", ++ phy_type); ++ ++ return -ENODEV; ++} ++ + static struct dw_hdmi * + __dw_hdmi_probe(struct platform_device *pdev, + const struct dw_hdmi_plat_data *plat_data) +@@ -1950,9 +2007,14 @@ __dw_hdmi_probe(struct platform_device * + goto err_iahb; + } + +- dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP\n", ++ ret = dw_hdmi_detect_phy(hdmi); ++ if (ret < 0) ++ goto err_iahb; ++ ++ dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", + hdmi->version >> 12, hdmi->version & 0xfff, +- prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without"); ++ prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", ++ hdmi->phy->name); + + initialize_hdmi_ih_mutes(hdmi); + +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -27,6 +27,16 @@ enum dw_hdmi_devtype { + RK3288_HDMI, + }; + ++enum dw_hdmi_phy_type { ++ DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00, ++ DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2, ++ DW_HDMI_PHY_DWC_MHL_PHY = 0xc2, ++ DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2, ++ DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2, ++ DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3, ++ DW_HDMI_PHY_VENDOR_PHY = 0xfe, ++}; ++ + struct dw_hdmi_mpll_config { + unsigned long mpixelclock; + struct { diff --git a/patches.renesas/0252-drm-bridge-dw-hdmi-Define-and-use-macros-for-PHY-reg.patch b/patches.renesas/0252-drm-bridge-dw-hdmi-Define-and-use-macros-for-PHY-reg.patch new file mode 100644 index 0000000000000..68c7563fe239b --- /dev/null +++ b/patches.renesas/0252-drm-bridge-dw-hdmi-Define-and-use-macros-for-PHY-reg.patch @@ -0,0 +1,140 @@ +From bcb9c654a4ef1faa21f7db2fad8f77a4f6b83913 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:29:07 +0200 +Subject: [PATCH 252/255] drm: bridge: dw-hdmi: Define and use macros for PHY + register addresses + +Replace the hardcoded register address numerical values with macros to +clarify the code. + +This change has been tested by comparing the assembly code before and +after the change. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-18-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit f0e7f2f3b6333a02dd7cb89822e6330631c9a3e3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 35 +++++++++++--------- + drivers/gpu/drm/bridge/dw-hdmi.h | 66 +++++++++++++++++++++++++++++++++++++++ + 2 files changed, 86 insertions(+), 15 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -997,21 +997,26 @@ static int hdmi_phy_configure(struct dw_ + HDMI_PHY_I2CM_SLAVE_ADDR); + hdmi_phy_test_clear(hdmi, 0); + +- hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 0x06); +- hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 0x15); +- +- /* CURRCTRL */ +- hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 0x10); +- +- hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */ +- hdmi_phy_i2c_write(hdmi, 0x0006, 0x17); +- +- hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19); /* TXTERM */ +- hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */ +- hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */ +- +- /* REMOVE CLK TERM */ +- hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */ ++ hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, ++ HDMI_3D_TX_PHY_CPCE_CTRL); ++ hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, ++ HDMI_3D_TX_PHY_GMPCTRL); ++ hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], ++ HDMI_3D_TX_PHY_CURRCTRL); ++ ++ hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); ++ hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, ++ HDMI_3D_TX_PHY_MSM_CTRL); ++ ++ hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); ++ hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, ++ HDMI_3D_TX_PHY_CKSYMTXCTRL); ++ hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, ++ HDMI_3D_TX_PHY_VLEVCTRL); ++ ++ /* Override and disable clock termination. */ ++ hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, ++ HDMI_3D_TX_PHY_CKCALCTRL); + + dw_hdmi_phy_enable_powerdown(hdmi, false); + +--- a/drivers/gpu/drm/bridge/dw-hdmi.h ++++ b/drivers/gpu/drm/bridge/dw-hdmi.h +@@ -1085,4 +1085,70 @@ enum { + HDMI_I2CM_CTLINT_ARB_MASK = 0x4, + }; + ++/* ++ * HDMI 3D TX PHY registers ++ */ ++#define HDMI_3D_TX_PHY_PWRCTRL 0x00 ++#define HDMI_3D_TX_PHY_SERDIVCTRL 0x01 ++#define HDMI_3D_TX_PHY_SERCKCTRL 0x02 ++#define HDMI_3D_TX_PHY_SERCKKILLCTRL 0x03 ++#define HDMI_3D_TX_PHY_TXRESCTRL 0x04 ++#define HDMI_3D_TX_PHY_CKCALCTRL 0x05 ++#define HDMI_3D_TX_PHY_CPCE_CTRL 0x06 ++#define HDMI_3D_TX_PHY_TXCLKMEASCTRL 0x07 ++#define HDMI_3D_TX_PHY_TXMEASCTRL 0x08 ++#define HDMI_3D_TX_PHY_CKSYMTXCTRL 0x09 ++#define HDMI_3D_TX_PHY_CMPSEQCTRL 0x0a ++#define HDMI_3D_TX_PHY_CMPPWRCTRL 0x0b ++#define HDMI_3D_TX_PHY_CMPMODECTRL 0x0c ++#define HDMI_3D_TX_PHY_MEASCTRL 0x0d ++#define HDMI_3D_TX_PHY_VLEVCTRL 0x0e ++#define HDMI_3D_TX_PHY_D2ACTRL 0x0f ++#define HDMI_3D_TX_PHY_CURRCTRL 0x10 ++#define HDMI_3D_TX_PHY_DRVANACTRL 0x11 ++#define HDMI_3D_TX_PHY_PLLMEASCTRL 0x12 ++#define HDMI_3D_TX_PHY_PLLPHBYCTRL 0x13 ++#define HDMI_3D_TX_PHY_GRP_CTRL 0x14 ++#define HDMI_3D_TX_PHY_GMPCTRL 0x15 ++#define HDMI_3D_TX_PHY_MPLLMEASCTRL 0x16 ++#define HDMI_3D_TX_PHY_MSM_CTRL 0x17 ++#define HDMI_3D_TX_PHY_SCRPB_STATUS 0x18 ++#define HDMI_3D_TX_PHY_TXTERM 0x19 ++#define HDMI_3D_TX_PHY_PTRPT_ENBL 0x1a ++#define HDMI_3D_TX_PHY_PATTERNGEN 0x1b ++#define HDMI_3D_TX_PHY_SDCAP_MODE 0x1c ++#define HDMI_3D_TX_PHY_SCOPEMODE 0x1d ++#define HDMI_3D_TX_PHY_DIGTXMODE 0x1e ++#define HDMI_3D_TX_PHY_STR_STATUS 0x1f ++#define HDMI_3D_TX_PHY_SCOPECNT0 0x20 ++#define HDMI_3D_TX_PHY_SCOPECNT1 0x21 ++#define HDMI_3D_TX_PHY_SCOPECNT2 0x22 ++#define HDMI_3D_TX_PHY_SCOPECNTCLK 0x23 ++#define HDMI_3D_TX_PHY_SCOPESAMPLE 0x24 ++#define HDMI_3D_TX_PHY_SCOPECNTMSB01 0x25 ++#define HDMI_3D_TX_PHY_SCOPECNTMSB2CK 0x26 ++ ++/* HDMI_3D_TX_PHY_CKCALCTRL values */ ++#define HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE BIT(15) ++ ++/* HDMI_3D_TX_PHY_MSM_CTRL values */ ++#define HDMI_3D_TX_PHY_MSM_CTRL_MPLL_PH_SEL_CK BIT(13) ++#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_CLK_REF_MPLL (0 << 1) ++#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_OFF (1 << 1) ++#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_PCLK (2 << 1) ++#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK (3 << 1) ++#define HDMI_3D_TX_PHY_MSM_CTRL_SCOPE_CK_SEL BIT(0) ++ ++/* HDMI_3D_TX_PHY_PTRPT_ENBL values */ ++#define HDMI_3D_TX_PHY_PTRPT_ENBL_OVERRIDE BIT(15) ++#define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT2 BIT(8) ++#define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT1 BIT(7) ++#define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT0 BIT(6) ++#define HDMI_3D_TX_PHY_PTRPT_ENBL_CK_REF_ENB BIT(5) ++#define HDMI_3D_TX_PHY_PTRPT_ENBL_RCAL_ENB BIT(4) ++#define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_CLK_ALIGN_ENB BIT(3) ++#define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_READY BIT(2) ++#define HDMI_3D_TX_PHY_PTRPT_ENBL_CKO_WORD_ENB BIT(1) ++#define HDMI_3D_TX_PHY_PTRPT_ENBL_REFCLK_ENB BIT(0) ++ + #endif /* __DW_HDMI_H__ */ diff --git a/patches.renesas/0253-drm-bridge-dw-hdmi-Fix-the-name-of-the-PHY-reset-mac.patch b/patches.renesas/0253-drm-bridge-dw-hdmi-Fix-the-name-of-the-PHY-reset-mac.patch new file mode 100644 index 0000000000000..1ed468fb8eeca --- /dev/null +++ b/patches.renesas/0253-drm-bridge-dw-hdmi-Fix-the-name-of-the-PHY-reset-mac.patch @@ -0,0 +1,54 @@ +From f198c768f1e44c6e644ab6be3a6d8e88b7846868 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:29:08 +0200 +Subject: [PATCH 253/255] drm: bridge: dw-hdmi: Fix the name of the PHY reset + macros + +The PHY reset signal is controlled by bit PHYRSTZ in the MC_PHYRSTZ +register. The signal is active low on Gen1 PHYs and active high on Gen2 +PHYs. The driver toggles the signal high then low, which is correct for +all currently supported platforms, but the register values macros are +incorrectly named. Replace them with a single macro named after the bit, +and add a comment to the source code to explain the behaviour. + +The driver's behaviour isn't changed by this rename, the code will still +need to be fixed to support Gen1 PHYs. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-19-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 54d72737b098f3597c57693e1aa96699a21b11fe) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 6 +++--- + drivers/gpu/drm/bridge/dw-hdmi.h | 3 +-- + 2 files changed, 4 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -986,9 +986,9 @@ static int hdmi_phy_configure(struct dw_ + /* gen2 pddq */ + dw_hdmi_phy_gen2_pddq(hdmi, 1); + +- /* PHY reset */ +- hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ); +- hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ); ++ /* PHY reset. The reset signal is active high on Gen2 PHYs. */ ++ hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); ++ hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); + + hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); + +--- a/drivers/gpu/drm/bridge/dw-hdmi.h ++++ b/drivers/gpu/drm/bridge/dw-hdmi.h +@@ -989,8 +989,7 @@ enum { + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, + + /* MC_PHYRSTZ field values */ +- HDMI_MC_PHYRSTZ_ASSERT = 0x0, +- HDMI_MC_PHYRSTZ_DEASSERT = 0x1, ++ HDMI_MC_PHYRSTZ_PHYRSTZ = 0x01, + + /* MC_HEACPHY_RST field values */ + HDMI_MC_HEACPHY_RST_ASSERT = 0x1, diff --git a/patches.renesas/0254-drm-bridge-dw-hdmi-Assert-SVSRET-before-resetting-th.patch b/patches.renesas/0254-drm-bridge-dw-hdmi-Assert-SVSRET-before-resetting-th.patch new file mode 100644 index 0000000000000..0698ffbeceaa2 --- /dev/null +++ b/patches.renesas/0254-drm-bridge-dw-hdmi-Assert-SVSRET-before-resetting-th.patch @@ -0,0 +1,46 @@ +From ab642a05e52a7fca9c4eb62ddc5a61c1a7af3cb7 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 17 Jan 2017 10:29:09 +0200 +Subject: [PATCH 254/255] drm: bridge: dw-hdmi: Assert SVSRET before resetting + the PHY + +According to the PHY IP core vendor, the SVSRET signal must be asserted +before resetting the PHY. Tests on RK3288 and R-Car Gen3 showed no +regression, the change should thus be safe. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-20-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 2668db37888ff63282147b00dcf54fa491831df3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -986,6 +986,10 @@ static int hdmi_phy_configure(struct dw_ + /* gen2 pddq */ + dw_hdmi_phy_gen2_pddq(hdmi, 1); + ++ /* Leave low power consumption mode by asserting SVSRET. */ ++ if (hdmi->phy->has_svsret) ++ dw_hdmi_phy_enable_svsret(hdmi, 1); ++ + /* PHY reset. The reset signal is active high on Gen2 PHYs. */ + hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); + hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); +@@ -1028,11 +1032,7 @@ static int hdmi_phy_configure(struct dw_ + dw_hdmi_phy_gen2_txpwron(hdmi, 1); + dw_hdmi_phy_gen2_pddq(hdmi, 0); + +- /* The DWC MHL and HDMI 2.0 PHYs need the SVSRET signal to be set. */ +- if (hdmi->phy->has_svsret) +- dw_hdmi_phy_enable_svsret(hdmi, 1); +- +- /*Wait for PHY PLL lock */ ++ /* Wait for PHY PLL lock */ + msec = 5; + do { + val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; diff --git a/patches.renesas/0255-drm-bridge-dw-hdmi-fix-building-without-CONFIG_OF.patch b/patches.renesas/0255-drm-bridge-dw-hdmi-fix-building-without-CONFIG_OF.patch new file mode 100644 index 0000000000000..91abafd081ec2 --- /dev/null +++ b/patches.renesas/0255-drm-bridge-dw-hdmi-fix-building-without-CONFIG_OF.patch @@ -0,0 +1,37 @@ +From 338ec844533e7bb1120f88f83a3fcc1d9618eef7 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann <arnd@arndb.de> +Date: Mon, 23 Jan 2017 13:20:38 +0100 +Subject: [PATCH 255/255] drm: bridge: dw-hdmi: fix building without CONFIG_OF + +The of_node member in struct drm_bridge is hidden when CONFIG_OF +is disabled, causing a build error: + +drivers/gpu/drm/bridge/dw-hdmi.c: In function '__dw_hdmi_probe': +drivers/gpu/drm/bridge/dw-hdmi.c:2063:14: error: 'struct drm_bridge' has no member named 'of_node' + +We could fix this either using a Kconfig dependency on CONFIG_OF +or making the one line conditional. The latter gives us better +compile test coverage, so this is what I'm doing here. + +Fixes: 69497eb9234e ("drm: bridge: dw-hdmi: Implement DRM bridge registration") +Signed-off-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170123122312.3290934-1-arnd@arndb.de +(cherry picked from commit d5ad78436a8829c9951d82b1b0bdec761dbabfa9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -2060,7 +2060,9 @@ __dw_hdmi_probe(struct platform_device * + + hdmi->bridge.driver_private = hdmi; + hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; ++#ifdef CONFIG_OF + hdmi->bridge.of_node = pdev->dev.of_node; ++#endif + + ret = dw_hdmi_fb_registered(hdmi); + if (ret) @@ -320,6 +320,261 @@ patches.renesas/0297-drm-dw_hdmi-use-of_get_i2c_adapter_by_node-interface.patch patches.renesas/0298-drm-bridge-dw_hdmi-add-dw-hdmi-i2c-bus-adapter-suppo.patch patches.renesas/0299-drm-bridge-add-DesignWare-HDMI-I2S-audio-support.patch +patches.renesas/0001-drm-bridge-adv7511-Initialize-regulators.patch +patches.renesas/0002-drm-bridge-adv7511-Use-work_struct-to-defer-hotplug-.patch +patches.renesas/0003-drm-bridge-adv7511-Switch-to-using-drm_kms_helper_ho.patch +patches.renesas/0004-drm-bridge-adv7511-Enable-HPD-interrupts-to-support-.patch +patches.renesas/0005-drm-bridge-adv7511-Rework-adv7511_power_on-off-so-th.patch +patches.renesas/0006-drm-bridge-adv7511-Reuse-__adv7511_power_on-off-when.patch +patches.renesas/0007-drm-bridge-adv7511-Re-write-the-i2c-address-before-E.patch +patches.renesas/0008-ASoC-ak4642-Replace-mdelay-function-to-msleep.patch +patches.renesas/0009-clk-renesas-r8a7796-Add-CAN-peripheral-clock.patch +patches.renesas/0010-clk-renesas-r8a7796-Add-CANFD-clock.patch +patches.renesas/0011-clk-renesas-r8a7796-Add-CAN-FD-peripheral-clock.patch +patches.renesas/0012-clk-renesas-r8a7796-Add-MSIOF-controller-clocks.patch +patches.renesas/0013-clk-renesas-cpg-mssr-Migrate-to-CLK_IS_CRITICAL.patch +patches.renesas/0014-clk-renesas-mstp-Make-INTC-SYS-a-critical-clock.patch +patches.renesas/0015-ARM-dts-r7s72100-add-ostm-clock-to-device-tree.patch +patches.renesas/0016-clk-renesas-mstp-Reformat-cpg_mstp_clock_register-fo.patch +patches.renesas/0017-dt-bindings-clock-renesas-cpg-mssr-Document-reset-co.patch +patches.renesas/0018-clk-renesas-cpg-mssr-Document-suitability-for-RZ-G1.patch +patches.renesas/0019-clk-renesas-cpg-mssr-Rename-cpg_mssr_priv.mstp_lock.patch +patches.renesas/0020-clk-renesas-cpg-mssr-Add-support-for-reset-control.patch +patches.renesas/0021-clk-renesas-r8a7795-Add-IIC-DVFS-clock.patch +patches.renesas/0022-clk-renesas-r8a7796-Add-IIC-DVFS-clock.patch +patches.renesas/0023-clk-renesas-mstp-ensure-register-writes-complete.patch +patches.renesas/0024-arm64-dts-r8a7796-Add-all-MSIOF-nodes.patch +patches.renesas/0025-arm64-dts-r8a7796-Add-CAN-external-clock-support.patch +patches.renesas/0026-arm64-dts-r8a7796-Add-CAN-support.patch +patches.renesas/0027-arm64-dts-r8a7796-Add-CAN-FD-support.patch +patches.renesas/0028-arm64-renesas-r8a7796-salvator-x-Add-board-part-numb.patch +patches.renesas/0029-arm64-dts-r8a7795-Use-renesas-rcar-gen3-usb2-phy-fal.patch +patches.renesas/0030-arm64-dts-r8a7795-add-sound-CTU-support.patch +patches.renesas/0031-arm64-dts-r8a7795-add-sound-MIX-support.patch +patches.renesas/0032-arm64-dts-r8a7795-Use-Gen-3-fallback-compat-string-f.patch +patches.renesas/0033-arm64-dts-r8a7795-Use-R-Car-Gen-3-fallback-binding-f.patch +patches.renesas/0034-arm64-dts-r8a7796-Use-R-Car-Gen-3-fallback-binding-f.patch +patches.renesas/0035-arm64-dts-r8a7796-salvator-x-Update-memory-node-to-4.patch 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