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authorEvgeniy Didin <didin@synopsys.com>2020-07-20 13:27:46 +0300
committerAntonio Borneo <borneo.antonio@gmail.com>2020-07-26 20:08:31 +0100
commitb2821b607460f8ce564b8b9d1cd968439058a108 (patch)
tree5586a92c195734b541e5ee06415d86d09b22dfa2
parent8fea8460dbc6ca23e34a16898e86231daab0594d (diff)
downloadopenocd-jz4730-b2821b607460f8ce564b8b9d1cd968439058a108.tar.gz
Introduce tcl config files for Synopsys HSDK board
With this commit we add tcl configure files for ARCv2 HS Development kit(HSDK). HSDK board has Quad-core ARC HS38 CPU with L1 and L2 caches. Change-Id: I372ef45428c7c7ca1421a6da3e5ed08b86f705e0 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5784 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
-rw-r--r--tcl/board/snps_hsdk.cfg18
-rw-r--r--tcl/cpu/arc/hs.tcl58
-rw-r--r--tcl/interface/ftdi/snps_sdp.cfg18
-rw-r--r--tcl/target/snps_hsdk.cfg86
4 files changed, 180 insertions, 0 deletions
diff --git a/tcl/board/snps_hsdk.cfg b/tcl/board/snps_hsdk.cfg
new file mode 100644
index 000000000..fed7343de
--- /dev/null
+++ b/tcl/board/snps_hsdk.cfg
@@ -0,0 +1,18 @@
+# Copyright (C) 2019, 2020 Synopsys, Inc.
+# Anton Kolesov <anton.kolesov@synopsys.com>
+# Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC HSDK Software Development Platform (HS38 cores)
+#
+
+source [find interface/ftdi/snps_sdp.cfg]
+adapter_khz 10000
+
+# ARCs supports only JTAG.
+transport select jtag
+
+# Configure SoC
+source [find target/snps_hsdk.cfg]
diff --git a/tcl/cpu/arc/hs.tcl b/tcl/cpu/arc/hs.tcl
new file mode 100644
index 000000000..f39f2a7d0
--- /dev/null
+++ b/tcl/cpu/arc/hs.tcl
@@ -0,0 +1,58 @@
+# Copyright (C) 2015, 2020 Synopsys, Inc.
+# Anton Kolesov <anton.kolesov@synopsys.com>
+# Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find cpu/arc/v2.tcl]
+
+proc arc_hs_examine_target { target } {
+ # Will set current target for us.
+ arc_v2_examine_target $target
+}
+
+proc arc_hs_init_regs { } {
+ arc_v2_init_regs
+
+ [target current] configure \
+ -event examine-end "arc_hs_examine_target [target current]"
+}
+
+# Scripts in "target" folder should call this function instead of direct
+# invocation of arc_common_reset.
+proc arc_hs_reset { {target ""} } {
+ arc_v2_reset $target
+
+ # Invalidate L2 cache if there is one.
+ set l2_config [$target arc jtag get-aux-reg 0x901]
+ # Will return 0, if cache is not present and register doesn't exist.
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ if { ($l2_config != 0) && (($l2_ctrl & 1) == 0) } {
+ puts "L2 cache is present and not disabled"
+
+ # Wait until BUSY bit is 0.
+ puts "Invalidating L2 cache..."
+ $target arc jtag set-aux-reg 0x905 1
+ # Dummy read of SLC_AUX_CACHE_CTRL bit, as described in:
+ # https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/arch/arc?id=c70c473396cbdec1168a6eff60e13029c0916854
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ while { ($l2_ctrl & 0x100) != 0 } {
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ }
+
+ # Flush cache if needed. If SLC_AUX_CACHE_CTRL.IM is 1, then invalidate
+ # operation already flushed everything.
+ if { ($l2_ctrl & 0x40) == 0 } {
+ puts "Flushing L2 cache..."
+ $target arc jtag set-aux-reg 0x904 1
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ while { [expr $l2_ctrl & 0x100] != 0 } {
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ }
+ }
+
+ puts "L2 cache has been flushed and invalidated."
+ }
+}
diff --git a/tcl/interface/ftdi/snps_sdp.cfg b/tcl/interface/ftdi/snps_sdp.cfg
new file mode 100644
index 000000000..8d91c6d3c
--- /dev/null
+++ b/tcl/interface/ftdi/snps_sdp.cfg
@@ -0,0 +1,18 @@
+# Copyright (C) 2020 Synopsys, Inc.
+# Anton Kolesov <anton.kolesov@synopsys.com>
+# Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys SDP Mainboard has embdded FT2232 chip, which is similiar to Digilent
+# HS-1, except that it uses channel B for JTAG communication, instead of
+# channel A.
+#
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+ftdi_layout_init 0x0088 0x008b
+ftdi_channel 1
+
+
diff --git a/tcl/target/snps_hsdk.cfg b/tcl/target/snps_hsdk.cfg
new file mode 100644
index 000000000..634e07adc
--- /dev/null
+++ b/tcl/target/snps_hsdk.cfg
@@ -0,0 +1,86 @@
+# Copyright (C) 2019,2020 Synopsys, Inc.
+# Anton Kolesov <anton.kolesov@synopsys.com>
+# Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# HS Development Kit SoC.
+#
+# Contains quad-core ARC HS38.
+#
+
+source [find cpu/arc/hs.tcl]
+
+set _coreid 0
+set _dbgbase [expr ($_coreid << 13)]
+
+# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
+# OpenOCD is concerned EM and HS are identical.
+set _CHIPNAME arc-em
+
+# OpenOCD discovers JTAG TAPs in reverse order.
+
+# ARC HS38 core 4
+set _TARGETNAME $_CHIPNAME.cpu4
+jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+# Flush L2$.
+$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr ($_coreid << 13)]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 4.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 3
+set _TARGETNAME $_CHIPNAME.cpu3
+jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr ($_coreid << 13)]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 3.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 2
+set _TARGETNAME $_CHIPNAME.cpu2
+jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr ($_coreid << 13)]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 2.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 1
+set _TARGETNAME $_CHIPNAME.cpu1
+jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
+arc_hs_init_regs
+
+# Enable L2 cache support for core 1.
+$_TARGETNAME arc cache l2 auto 1