MMP3: QSEVEN seperating GC 2D and 3D clock as per B1 silicon and disbaling qos for vmeta completely

Signed-off-by: dipen <dpatel@marvell.com>

2 files changed, 51 insertions, 9 deletions

diff --git a/arch/arm/mach-mmp/clock-mmp3.c b/arch/arm/mach-mmp/clock-mmp3.c
index ac6d3a5d2c695c..aed351583d529c 100644
--- a/arch/arm/mach-mmp/clock-mmp3.c
+++ b/arch/arm/mach-mmp/clock-mmp3.c
@@ -1016,6 +1016,7 @@ static struct notifier_block devfreq_reboot_notifier = {
 #define GC3D_AXICLK_EN		(1u << 2)
 
 #define GC2D3D_CLK_EN		(1u << 3)
+#define GC2D_CLK_EN		(1u << 20)
 
 #define GC_PWRUP(n)		((n & 3) << 9)
 #define GC_PWRUP_MSK		GC_PWRUP(3)
@@ -1082,14 +1083,16 @@ static int gc_clk_enable(struct clk *clk)
 	gc_rate_cfg &= GC_CLK_RATE_MSK;
 
 	GC_SET_BITS(gc_rate_cfg, GC_CLK_RATE_MSK);
-	GC_SET_BITS(GC2D3D_CLK_EN | GC2D_AXICLK_EN | GC3D_AXICLK_EN, 0);
+	GC_SET_BITS(GC2D_CLK_EN | GC2D3D_CLK_EN | GC2D_AXICLK_EN\
+			| GC3D_AXICLK_EN, 0);
 
 	return 0;
 }
 
 static void gc_clk_disable(struct clk *clk)
 {
-	GC_SET_BITS(0, GC2D_AXICLK_EN | GC3D_AXICLK_EN | GC2D3D_CLK_EN);
+	GC_SET_BITS(0, GC2D_AXICLK_EN | GC3D_AXICLK_EN | GC2D3D_CLK_EN\
+			| GC2D_CLK_EN);
 }
 
 static long gc_clk_round_rate(struct clk *clk, unsigned long rate)
@@ -3153,6 +3156,31 @@ struct clkops hsic_clk_ops = {
 	.disable	= hsic_clk_disable,
 };
 
+/* usb: fsic clock */
+static int fsic_clk_enable(struct clk *clk)
+{
+	uint32_t clk_rst;
+
+	clk_rst  =  __raw_readl(clk->clk_rst);
+	clk_rst |= 0x1b;
+	__raw_writel(clk_rst, clk->clk_rst);
+
+	return 0;
+}
+
+static void fsic_clk_disable(struct clk *clk)
+{
+	uint32_t clk_rst;
+
+	clk_rst  =  __raw_readl(clk->clk_rst);
+	clk_rst &= ~0x18;
+	__raw_writel(clk_rst, clk->clk_rst);
+}
+
+struct clkops fsic_clk_ops = {
+	.enable		= fsic_clk_enable,
+	.disable	= fsic_clk_disable,
+};
 static int pwm_clk_enable(struct clk *clk)
 {
 	struct clk *clk_apb = NULL, *clk_share = NULL;
@@ -3302,8 +3330,8 @@ static struct clk mmp3_list_clks[] = {
 			0x1b, 480000000, NULL, &hsic_clk_ops),
 	APMU_CLK_OPS("hsic2", NULL, "HSIC2CLK", USBHSIC2,
 			0x1b, 480000000, NULL, &hsic_clk_ops),
-	APMU_CLK("fsic", NULL, "FSICCLK", USBFSIC,
-			0x1b, 480000000, NULL),
+	APMU_CLK_OPS("fsic", NULL, "FSICCLK", USBFSIC,
+			0x1b, 480000000, NULL, &fsic_clk_ops),
 };
 
 static void mmp3_init_one_clock(struct clk *c)
diff --git a/arch/arm/mach-mmp/mmp3.c b/arch/arm/mach-mmp/mmp3.c
index dbeb90765db69f..aed37d2a1ba15d 100644
--- a/arch/arm/mach-mmp/mmp3.c
+++ b/arch/arm/mach-mmp/mmp3.c
@@ -982,17 +982,22 @@ static void mmp_vmeta_unset_op_constraint_work(struct work_struct *work)
 	struct vmeta_instance *vi = container_of(work, struct vmeta_instance, unset_op_work.work);
 
 	vi->vop_real = VMETA_OP_INVALID;
+//	pm_qos_update_request(&vi->qos_cpufreq_min, PM_QOS_DEFAULT_VALUE);
+#ifndef CONFIG_MACH_QSEVEN
 	pm_qos_update_request(&vi->qos_cpufreq_min, PM_QOS_DEFAULT_VALUE);
 	pm_qos_update_request(&vi->qos_ddrfreq_min, PM_QOS_DEFAULT_VALUE);
+#endif
 }
 
 int vmeta_init_constraint(struct vmeta_instance *vi)
 {
 	mutex_init(&vi->op_mutex);
 	INIT_DELAYED_WORK(&vi->unset_op_work, mmp_vmeta_unset_op_constraint_work);
+//	pm_qos_add_request(&vi->qos_cpufreq_min, PM_QOS_CPUFREQ_MIN,
+//			PM_QOS_DEFAULT_VALUE);
+#ifndef CONFIG_MACH_QSEVEN
 	pm_qos_add_request(&vi->qos_cpufreq_min, PM_QOS_CPUFREQ_MIN,
 			PM_QOS_DEFAULT_VALUE);
-#ifndef CONFIG_MACH_QSEVEN
 	pm_qos_add_request(&vi->qos_ddrfreq_min, PM_QOS_DDR_DEVFREQ_MIN,
 		PM_QOS_DEFAULT_VALUE);
 #endif
@@ -1002,8 +1007,11 @@ int vmeta_init_constraint(struct vmeta_instance *vi)
 int vmeta_clean_constraint(struct vmeta_instance *vi)
 {
 	cancel_delayed_work_sync(&vi->unset_op_work);
+//	pm_qos_remove_request(&vi->qos_cpufreq_min);
+#ifndef CONFIG_MACH_QSEVEN
 	pm_qos_remove_request(&vi->qos_cpufreq_min);
 	pm_qos_remove_request(&vi->qos_ddrfreq_min);
+#endif
 	printk(KERN_INFO "vmeta op clean up\n");
 
 	return 0;
@@ -1024,6 +1032,8 @@ int vmeta_runtime_constraint(struct vmeta_instance *vi, int on)
 	int vop = vi->vop;
 
 	mutex_lock(&vi->op_mutex);
+
+#if 0
 	if (on) {
 		cancel_delayed_work_sync(&vi->unset_op_work);
 		if (vop < VMETA_OP_MIN || vop > VMETA_OP_MAX) {
@@ -1060,6 +1070,8 @@ int vmeta_runtime_constraint(struct vmeta_instance *vi, int on)
 		schedule_delayed_work(&vi->unset_op_work, msecs_to_jiffies(vi->plat_data->power_down_ms));
 	}
 
+#endif
+
 out:
 	mutex_unlock(&vi->op_mutex);
 	return 0;
@@ -1394,6 +1406,7 @@ void mmp_zsp_platform_device_init(void)
 #define GC3D_AXI_RST_N		(1u << 0)
 
 #define GC2D3D_CLK_EN		(1u << 3)
+#define GC2D_CLK_EN		(1u << 20)
 #define GC2D3D_RST_N		(1u << 1)
 
 #define GC_PWRUP(n)		((n & 3) << 9)
@@ -1622,12 +1635,12 @@ int isppwr_power_control(int on)
 void gc_pwr(int power_on)
 {
 	unsigned long regval;
-
 	regval = __raw_readl(APMU_GC_CLK_RES_CTRL);
 	if (power_on) {
 		if (regval & (GC_PWRUP_MSK | GC_ISB))
 			return; /*Pwr is already on*/
 
+		pr_info("gc_pwr turning it on...\n");
 		/* 0, set to boot default value, source on PLL1*/
 		writel(GC_CLKRST_BOOT_DEFAULT, APMU_GC_CLK_RES_CTRL);
 
@@ -1665,7 +1678,7 @@ void gc_pwr(int power_on)
 
 		/* 6. enable GC clock */
 		regval = readl(APMU_GC_CLK_RES_CTRL);
-		regval |= GC2D3D_CLK_EN;
+		regval |= GC2D3D_CLK_EN | GC2D_CLK_EN;
 		writel(regval, APMU_GC_CLK_RES_CTRL);
 
 		/* 7. deassert resets*/
@@ -1680,7 +1693,8 @@ void gc_pwr(int power_on)
 
 		/* 8 gate clock */
 		regval = readl(APMU_GC_CLK_RES_CTRL);
-		regval &= ~(GC2D_AXICLK_EN | GC3D_AXICLK_EN | GC2D3D_CLK_EN);
+		regval &= ~(GC2D_AXICLK_EN | GC3D_AXICLK_EN | GC2D3D_CLK_EN
+				| GC2D_CLK_EN);
 		writel(regval, APMU_GC_CLK_RES_CTRL);
 
 	} else {
@@ -1699,7 +1713,7 @@ void gc_pwr(int power_on)
 
 		/* 3. make sure clock disabled*/
 		regval = readl(APMU_GC_CLK_RES_CTRL);
-		regval &= ~(GC2D_AXICLK_EN | GC3D_AXICLK_EN | GC2D3D_CLK_EN);
+		regval &= ~(GC2D_AXICLK_EN | GC3D_AXICLK_EN | GC2D3D_CLK_EN | GC2D_CLK_EN);
 		writel(regval, APMU_GC_CLK_RES_CTRL);
 
 		/* 4. turn off power */