diff options
| author | dipen <dpatel@marvell.com> | 2012-12-18 14:04:56 -0500 |
|---|---|---|
| committer | Lubomir Rintel <lkundrak@v3.sk> | 2019-07-22 19:40:06 +0200 |
| commit | ed4a43c2af0b4c564288100791891a46d8cff736 (patch) | |
| tree | ec261db04ce81fe233633e8da4593d95bae73bd3 | |
| parent | 1ac2a79534511704093609d430ef704c9b837c9c (diff) | |
| download | linux-mmp3-dell-ariel-ed4a43c2af0b4c564288100791891a46d8cff736.tar.gz | |
MMP3: QSEVEN correcting pll2 frequency reporting
Modified mmp3 system settings file to read 25 or 26Mhz
reference clock from the fsic
Signed-off-by: dipen <dpatel@marvell.com>
(cherry picked from commit 9e9bbf8e4fe196d440fe170b090f180fc29466e7)
Signed-off-by: Wen-chien Jesse Sung <jesse.sung@canonical.com>
| -rw-r--r-- | drivers/char/mmp3_systemsetting.c | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/drivers/char/mmp3_systemsetting.c b/drivers/char/mmp3_systemsetting.c index 1a8230b929845e..a809328853a5e3 100644 --- a/drivers/char/mmp3_systemsetting.c +++ b/drivers/char/mmp3_systemsetting.c @@ -20,6 +20,7 @@ #include <mach/regs-sspa.h> #define VCXO 26000000 +#define CRSTL 25000000 static u32 pd[9] = {2, 3, 4, 5, 6, 8, 10, 12, 16}; static char *ddr_inter[] = {"4k", "16k", "64k", "256k", "1024k", "512m", @@ -82,20 +83,17 @@ static struct audio_pll_output { static u32 pll_clk_calculate(u32 refdiv, u32 fbdiv, u32 postdiv) { - u32 input_clk; + u32 input_clk, tmp; u32 output_clk; u32 M, N; - switch (refdiv) { - case 3: - M = 3; + tmp = (__raw_readl(APMU_FSIC3_CLK_RES_CTRL) >> 8) & 0xF; + if (tmp == 0xD) input_clk = VCXO; - break; - default: - pr_debug("The PLL REFDIV should be 0x03\n"); - return 0; - } + else + input_clk = CRSTL; + M = refdiv; N = fbdiv; /* multiplied by 2 since pd is multiplied by 2 */ |