diff options
| author | nhcao <nhcao@marvell.com> | 2012-07-20 15:30:19 +0800 |
|---|---|---|
| committer | Lubomir Rintel <lkundrak@v3.sk> | 2019-07-22 19:39:58 +0200 |
| commit | bbf280bea2eebd187d81ad229ee0e7e3c665b721 (patch) | |
| tree | 6bf165666228c7e39e6ef2ab4a96a2f31ac26b1d | |
| parent | cc8c8aabf008867eebbb671563b5e8d90a01c239 (diff) | |
| download | linux-mmp3-dell-ariel-bbf280bea2eebd187d81ad229ee0e7e3c665b721.tar.gz | |
Audio: do not change to pll1 when zsp halt
Now, System will hang when doing frequency change. So remove this
operation when zsp halt.
Change-Id: Ia0dbb5985e9ee21c436e4750dbc16c31ae36d06f
Signed-off-by: nhcao <nhcao@marvell.com>
| -rw-r--r-- | arch/arm/mach-mmp/mmp3.c | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/arch/arm/mach-mmp/mmp3.c b/arch/arm/mach-mmp/mmp3.c index 49e9d8bb53d009..364ad2f1d7fea1 100644 --- a/arch/arm/mach-mmp/mmp3.c +++ b/arch/arm/mach-mmp/mmp3.c @@ -1195,29 +1195,8 @@ static void mmp_zsp_domain_on(int spd, int src, int asclk) static void mmp_zsp_domain_halt(void) { - u32 value; if (aud_pwr_status.zsp_cnt > 0) { aud_pwr_status.zsp_cnt--; - if (aud_pwr_status.zsp_cnt == 0) { - /* reset audio peripheral */ - __raw_modify(ZSP_AUD_DSA_CORE_CLK_RES, 0x0, 0x4); - udelay(100); - /* switch to pll1*/ - __raw_modify(ZSP_AUD_DSA_CORE_CLK_RES, 0x30, 0x0); - /* set divider 2*/ - __raw_modify(ZSP_AUD_CORE_FREQ_CHG, 0xE, 0x4); - /* enable divider*/ - __raw_modify(ZSP_AUD_DSA_CORE_CLK_RES, 0x0, 0x8); - /* enabled core clock and release reset*/ - __raw_modify(ZSP_AUD_DSA_CORE_CLK_RES, 0x4, 0x0); - udelay(10); - __raw_modify(ZSP_AUD_CORE_FREQ_CHG, 0x0, 0x1); - udelay(10); - do { - value = readl(ZSP_AUD_CORE_FREQ_CHG); - udelay(10); - } while ((value & 0x1) != 0); - } } if (aud_pwr_status.aud_dev_cnt > 0) @@ -1225,12 +1204,7 @@ static void mmp_zsp_domain_halt(void) if (aud_pwr_status.aud_pll_cnt > 0) { aud_pwr_status.aud_pll_cnt--; - if (aud_pwr_status.aud_pll_cnt == 0) { - __raw_modify(SSPA_AUD_PLL_CTRL1, 0x800, 0x0); - __raw_modify(SSPA_AUD_PLL_CTRL0, 0x1, 0x0); - } } - if (aud_pwr_status.main_pwr_cnt > 0) { aud_pwr_status.main_pwr_cnt--; if (aud_pwr_status.main_pwr_cnt == 0) { |