diff options
| author | Qiming Wu <wuqm@marvell.com> | 2012-09-04 13:14:05 +0800 |
|---|---|---|
| committer | Lubomir Rintel <lkundrak@v3.sk> | 2019-07-22 19:39:58 +0200 |
| commit | 228b5eea0ff0d186be5faba534ddfa87030d8ca9 (patch) | |
| tree | c08cefe262a20721167c8add5b9d08d15bda383b | |
| parent | 6ae2b6f8571e96ccc9eb7d009ab492386101053c (diff) | |
| download | linux-mmp3-dell-ariel-228b5eea0ff0d186be5faba534ddfa87030d8ca9.tar.gz | |
ARM: mmp: tune DDR setting to fix LCD flicker
LCD flicker is caused by blocking DDR access too much time during DDR
frequency change. So, with DE's suggestion, tune the DDR DLL reset timer
to reduce the blocking time of DDR access. Now, set the timer as
following:
533Mhz 0xf (temp value, will tune on Z3/A0)
400Mhz 0x8
312Mhz 0x7
208Mhz 0x5
156Mhz 0x4
The setting will be updated according to the target frequency during
table-based DDR frequency change.
Change-Id: I75aad04d8e7c5ae9545e2d3b0d7b099913dfc172
Signed-off-by: Qiming Wu <wuqm@marvell.com>
| -rw-r--r-- | arch/arm/mach-mmp/acpuclock-pxa988.c | 10 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/pxa988_ddr.h | 2 |
2 files changed, 9 insertions, 3 deletions
diff --git a/arch/arm/mach-mmp/acpuclock-pxa988.c b/arch/arm/mach-mmp/acpuclock-pxa988.c index e2dd2bcd2fa15f..9f9a2a241bc8af 100644 --- a/arch/arm/mach-mmp/acpuclock-pxa988.c +++ b/arch/arm/mach-mmp/acpuclock-pxa988.c @@ -314,6 +314,7 @@ static struct platform_ddr_setting lpddr2_setting[] = { .entry[1] = {DMCU_PHY_CTRL7, 0x13300aa9}, .entry[2] = {DMCU_PHY_CTRL8, 0x03300aa0}, .entry[3] = {DMCU_PHY_CTRL9, 0x000000aa}, + .entry[4] = {DMCU_PHY_CTRL13, 0x40218000}, }, }, @@ -336,6 +337,7 @@ static struct platform_ddr_setting lpddr2_setting[] = { .entry[1] = {DMCU_PHY_CTRL7, 0x13300aa9}, .entry[2] = {DMCU_PHY_CTRL8, 0x03300aa0}, .entry[3] = {DMCU_PHY_CTRL9, 0x000000aa}, + .entry[4] = {DMCU_PHY_CTRL13, 0x50218000}, }, }, @@ -358,6 +360,7 @@ static struct platform_ddr_setting lpddr2_setting[] = { .entry[1] = {DMCU_PHY_CTRL7, 0x13300aa9}, .entry[2] = {DMCU_PHY_CTRL8, 0x03300aa0}, .entry[3] = {DMCU_PHY_CTRL9, 0x000000aa}, + .entry[4] = {DMCU_PHY_CTRL13, 0x70218000}, }, }, @@ -380,6 +383,7 @@ static struct platform_ddr_setting lpddr2_setting[] = { .entry[1] = {DMCU_PHY_CTRL7, 0x13300aa9}, .entry[2] = {DMCU_PHY_CTRL8, 0x03300aa0}, .entry[3] = {DMCU_PHY_CTRL9, 0x000000aa}, + .entry[4] = {DMCU_PHY_CTRL13, 0x80218000}, }, }, @@ -402,6 +406,7 @@ static struct platform_ddr_setting lpddr2_setting[] = { .entry[1] = {DMCU_PHY_CTRL7, 0x13300aa9}, .entry[2] = {DMCU_PHY_CTRL8, 0x03300aa0}, .entry[3] = {DMCU_PHY_CTRL9, 0x000000aa}, + .entry[4] = {DMCU_PHY_CTRL13, 0xf0218000}, }, }, @@ -472,7 +477,7 @@ static void pxa988_ddr_lpm_table(void) LAST_ENTRY(DMCU_PHY_CTRL14, 0x80000000, 0); } -/* #define DDR_FC_PHY_TUNING 1 */ +#define DDR_FC_PHY_TUNING 1 static void pxa988_ddr_fc_table_lpddr2(struct platform_ddr_setting *setting) { struct ddr_timing *timing = &setting->timing; @@ -528,7 +533,8 @@ static void pxa988_ddr_fc_table_lpddr2(struct platform_ddr_setting *setting) INSERT_ENTRY(phy->entry[0].reg, phy->entry[0].val, table); INSERT_ENTRY(phy->entry[1].reg, phy->entry[1].val, table); INSERT_ENTRY(phy->entry[2].reg, phy->entry[2].val, table); - PAUSE_ENTRY(phy->entry[3].reg, phy->entry[3].val, table); + INSERT_ENTRY(phy->entry[3].reg, phy->entry[3].val, table); + PAUSE_ENTRY(phy->entry[4].reg, phy->entry[4].val, table); #endif /* 3. reset DLL */ diff --git a/arch/arm/mach-mmp/include/mach/pxa988_ddr.h b/arch/arm/mach-mmp/include/mach/pxa988_ddr.h index 762bdddccc430e..eb717048cd9d90 100644 --- a/arch/arm/mach-mmp/include/mach/pxa988_ddr.h +++ b/arch/arm/mach-mmp/include/mach/pxa988_ddr.h @@ -29,7 +29,7 @@ struct ddr_phy { * If the value is same for different frequency, * we could remove this part then. */ - struct ddr_setting_entry entry[4]; + struct ddr_setting_entry entry[5]; }; struct platform_ddr_setting { |